OPA2206 [TI]
OPA2206 Input-Overvoltage-Protected, 2-μV, 0.04-μV/°C, Low-Power Precision Op Amp;
| 型号： | OPA2206 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OPA2206 Input-Overvoltage-Protected, 2-μV, 0.04-μV/°C, Low-Power Precision Op Amp |
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| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OPA2206
SBOSA11A – MARCH 2020 – REVISED MARCH 2021
OPA2206 Input-Overvoltage-Protected, 2-µV, 0.04-µV/°C, Low-Power
Precision Op Amp
1 Features
3 Description
•
Integrated input overvoltage protection up to ±40 V
beyond supplies
e-trim™ operational amplifier performance
– Low offset voltage: 15 µV (max)
– Low offset voltage drift: ±0.2 µV/°C (max)
Super beta inputs
– Input bias current: 0.4 nA (max)
– Input current noise: 110 fA/√Hz
Low noise
– 0.1-Hz to 10-Hz: 0.2 µVPP
– Voltage noise: 8 nV/√Hz
AOL, CMRR, and PSRR: > 126 dB (full
temperature range)
Gain bandwidth product: 3.6 MHz
Low quiescent current: 220 µA (max)
Slew rate: 4 V/µs
Overload power limiter
Rail-to-rail output
EMI/RFI filtered inputs
Wide supply: 4.5 V to 36 V
Temperature range: –40°C to +125°C
Available in high grade (OPA2206) and standard
grade (OPA2206A)
The OPA2206 is the next generation of the industry-
standard OPAx277 family with the additional feature
of input overvoltage protection. The device is a
precision bipolar, e-trim operational amplifier with
super beta inputs. The device uses TI’s proprietary
trimming technology to achieve an impressive input
offset voltage of ±2 μV (typ) and an input offset
voltage drift of ±0.04 μV/°C (typ). The input
overvoltage protection activates when the input signal
exceeds the supply range and offers protection up to
40 V beyond either supply. This feature eliminates the
need for external cumbersome circuitry to prevent the
amplifier from damages.
•
•
•
•
Designed on a bipolar process, the OPA2206
provides a superb speed-to-power ratio of 3.6 MHz
for a mere 220 μA. The device also achieves a low
voltage noise density of only 8 nV/√Hz at 1 kHz.
Thanks to super-beta inputs, the OPA2206 has a very
low input bias current of 100 pA (typ) and a current
noise density of 110 fA/√Hz.
•
•
•
•
•
•
•
•
•
The high performance of the OPA2206 makes this
device an excellent choice for systems requiring
high precision and low power consumption, such as
high-density analog input modules in programmable
logic controllers, field and portable instrumentation
systems, and source measurement units. The
OPA2205 is a related product with the same op amp
core, without the input protection but with improved
broadband noise (7.2 nV/√Hz).
2 Applications
•
•
•
•
•
•
•
•
Analog input module
Mixed module (AI,AO,DI,DO)
Lab and field Instrumentation
Source measurement unit (SMU)
Digital multimeter (DMM)
Train control and management
String inverter
Device Information
PART NUMBER
OPA2206
PACKAGE(1)
BODY SIZE (NOM)
VSSOP (8)
3.00 mm × 3.00 mm
(1) For all available packages, see the package option
addendum at the end of the data sheet.
Data acquisition (DAQ)
7.5
80 k
20 k
±10 V
12 V
5
12 V
2.2 nF
2.5
0
100 nF
GND
100 nF
GND
–
+
3.74 k
11.8 k
2.2 nF
6.65 k
–
+
Output
-2.5
-5
OPA2206
TA = –40°C
TA = 25°C
TA = 85°C
TA = 125°C
2 V
OPA2206
330 pF
GND
100 nF
GND
100 nF
GND
12 V
-7.5
-60
12 V
GND
-40
-20
0
20
40
60
Common-mode Voltage (V)
OPA2206 Typical Application
OPA2206 Input Overvoltage Protection
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA2206
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SBOSA11A – MARCH 2020 – REVISED MARCH 2021
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions ........................4
6.4 Thermal Information: OPA2206 ................................. 4
6.5 Electrical Characteristics: VS = ±5 V ..........................5
6.6 Electrical Characteristics: VS = ±15 V ........................7
6.7 Typical Characteristics................................................9
7 Parameter Measurement Information..........................18
7.1 Typical Specifications and Distributions....................18
8 Detailed Description......................................................19
8.1 Overview...................................................................19
8.2 Functional Block Diagram.........................................19
8.3 Feature Description...................................................20
8.4 Device Functional Modes..........................................22
9 Application and Implementation..................................23
9.1 Application Information............................................. 23
9.2 Typical Applications.................................................. 23
10 Power Supply Recommendations..............................26
11 Layout...........................................................................26
11.1 Layout Guidelines................................................... 26
11.2 Layout Example...................................................... 27
12 Device and Documentation Support..........................28
12.1 Device Support....................................................... 28
12.2 Receiving Notification of Documentation Updates..28
12.3 Support Resources................................................. 28
12.5 Electrostatic Discharge Caution..............................28
12.6 Glossary..................................................................28
13 Mechanical, Packaging, and Orderable
Information.................................................................... 28
4 Revision History
Changes from Revision * (April 2020) to Revision A (March 2021)
Page
•
•
Changed OPA2206 from advanced information (preview) to production data (active).......................................1
Changed both Electrical Characteristics tables to show differentiated performance between OPA2206 (high
grade) and OPA2206A (standard grade)............................................................................................................5
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5 Pin Configuration and Functions
OUT A
œIN A
+IN A
Vœ
1
2
3
4
8
7
6
5
V+
OUT B
œIN B
+IN B
Not to scale
Figure 5-1. DGK (8-Pin VSSOP) Package, Top View
Table 5-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
3
+IN A
–IN A
+IN B
–IN B
I
I
Noninverting input, channel A
Inverting input, channel A
Noninverting input, channel B
Inverting input, channel B
Output, channel A
2
5
I
6
I
OUT A
OUT B
V+
1
O
O
—
—
7
Output, channel B
8
Positive (highest) power supply
Negative (lowest) power supply
V–
4
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
40
UNIT
V
Single supply
VS
Supply voltage, Vs = (V+) – (V–)
Dual supply
±20
Signal input pin voltage
Output short-circuit(2)
Operating temperature
Junction temperature
Storage temperature, Tstg
(V–) – 40
(V+) + 40
V
Continuous
TA
–40
–65
150
150
150
°C
°C
°C
TJ
TSTG
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
NOM
MAX
36
UNIT
V
Single supply
Dual supply
VS
TA
Supply voltage, VS = (V+) – (V–)
Operating temperature
±2.25
–40
±18
125
°C
6.4 Thermal Information: OPA2206
OPA2206
DGK (VSSOP)
8 PINS
175.6
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
℃/W
℃/W
℃/W
℃/W
℃/W
℃/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
63.1
97.2
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
7.8
ψJB
95.5
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics: VS = ±5 V
at TA = 25°C, VCM = VOUT = midsupply, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
±2
±15
±25
OPA2206
TA = –40°C to +125°C
VOS
Input offset voltage
μV
μV/°C
μV/V
dB
±8
±50
OPA2206A
TA = –40°C to +125°C
±80
OPA2206, TA = –40°C to +125°C
OPA2206A, TA = –40°C to +125°C
±0.04
±0.08
±0.05
±0.2
±0.5
±0.25
±0.5
±0.5
±1
dVOS/dT
PSRR
Input offset voltage drift
OPA2206,
VS = ±2.25 V to ±18 V
TA = –40°C to +125°C
Power supply rejection
ratio
±0.05
OPA2206A,
VS = ±2.25 V to ±18 V
TA = –40°C to +125°C
f = DC
130
110
Channel separation
f = 100 kHz
INPUT BIAS CURRENT
±0.1
±0.1
±0.1
±0.4
±0.6
±0.9
±0.5
±0.75
±1
OPA2206
TA = 0°C to 85°C
TA = –40°C to +125°C
IB
Input bias current
nA
nA
OPA2206A
TA = 0°C to 85°C
TA = –40°C to +125°C
±0.4
±0.5
±0.6
IOS
Input offset current
Input voltage noise
TA = 0°C to 85°C
TA = –40°C to +125°C
NOISE
en p-p
f = 0.1 Hz to 10 Hz
f = 10 Hz
0.2
8.4
8.1
8
μVPP
nV/√Hz
fA/√Hz
V
en
Input voltage noise density f = 100 Hz
f = 1 kHz
in
Input current noise
f = 1 kHz
110
INPUT VOLTAGE
VCM
Common-mode voltage
(V–) + 1
124
(V+) – 1.4
OPA2206, (V–) + 1 V < VCM < (V+) – 1.4 V,
TA = –40°C to +125°C
140
140
Common-mode rejection
ratio
CMRR
dB
OPA2206A, (V–) + 1 V < VCM < (V+) – 1.4 V,
TA = –40°C to +125°C
124
INPUT OVERVOLTAGE
Input overvoltage
TA = –40℃ to +125℃
(V–) – 40
(V+) + 40
10
V
protection
VS = 0 V,
(V–) – 40 V < VCM < (V+) +
40 V
4.8
Input current in overvoltage
protected mode
mA
TA = –40℃ to +125℃
See typical curves
INPUT IMPEDANCE
ZID
Differential
9 || 4.4
MΩ || pF
GΩ || pF
ZICM
Common-mode
300 || 4.4
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UNIT
SBOSA11A – MARCH 2020 – REVISED MARCH 2021
6.5 Electrical Characteristics: VS = ±5 V (continued)
at TA = 25°C, VCM = VOUT = midsupply, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
OPEN-LOOP GAIN
OPA2206,
RL = 10 kΩ
126
126
126
126
132
130
132
130
TA = –40°C to +125°C,
(V–) + 200 mV < VO < (V+)
– 200 mV
RL = 2 kΩ
RL = 10 kΩ
RL = 2 kΩ
AOL
Open-loop voltage gain
dB
OPA2206A,
TA = –40°C to +125°C,
(V–) + 200 mV < VO < (V+)
– 200 mV
FREQUENCY RESPONSE
GBW
SR
Gain-bandwidth product
3.6
3.2
67
MHz
V/μs
Slew rate
4-V step, G = –1
Phase margin
RL = 10 kΩ, CL = 25 pF
degrees
Falling
Rising
2.2
2.8
0.3
To 0.024% (12-bit),
4-V step, G = 1, CL = 30 pF
tS
Settling time
μs
Overload recovery time
G = –10
μs
%
Total harmonic distortion +
noise
THD+N
VO = 5 VPP, G = +1, f = 1 kHz, RL = 2 kΩ
0.0004
OUTPUT
RL = 10 kΩ
AOL > 126 dB
(V–) + 0.2
(V–) + 0.2
(V–) + 0.2
(V+) – 0.2
(V+) – 0.2
(V+) – 0.2
Voltage output swing from
rail
RL = 2 kΩ
V
TA = –40°C to +125°C, RL = 10 kΩ
ISC
Short-circuit current
Capacitive load drive
±25
mA
CLOAD
See Typical Characteristics
See Typical Characteristics
Open-loop output
impedance
RO
POWER SUPPLY
220
240
310
Quiescent current per
amplifier
IQ
IO = 0 mA
μA
TA = –40°C to +125°C
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6.6 Electrical Characteristics: VS = ±15 V
at TA = 25°C, VCM = VOUT = midsupply and RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
±2
±15
±25
OPA2206
TA = –40°C to +125°C
VOS
Input offset voltage
μV
μV/°C
μV/V
dB
±8
±50
OPA2206A
TA = –40°C to +125°C
±80
OPA2206, TA = –40°C to +125°C
OPA2206A, TA = –40°C to +125°C
±0.04
±0.08
±0.05
±0.2
±0.5
±0.25
±0.5
±0.5
±1
dVOS/dT
PSRR
Input offset voltage drift
OPA2206,
VS = ±2.25 V to ±18 V
TA = –40°C to +125°C
Power supply rejection
ratio
±0.05
OPA2206A,
VS = ±2.25 V to ±18 V
TA = –40°C to +125°C
f = DC
130
110
Channel separation
f = 100 kHz
INPUT BIAS CURRENT
±0.1
±0.1
±0.1
±0.4
±0.6
±0.9
±0.5
±1
OPA2206
TA = 0°C to 85°C
TA = –40°C to +125°C
IB
Input bias current
nA
nA
OPA2206A
TA = 0°C to 85°C
TA = –40°C to +125°C
±1.2
±0.4
±0.8
±0.9
IOS
Input offset current
Input voltage noise
TA = 0°C to 85°C
TA = –40°C to +125°C
NOISE
en p-p
f = 0.1 Hz to 10 Hz
f = 10 Hz
0.2
8.4
8.1
8
μVPP
nV/√Hz
fA/√Hz
V
en
Input voltage noise density f = 100 Hz
f = 1 kHz
in
Input current noise
f = 1 kHz
110
INPUT VOLTAGE
VCM
Common-mode voltage
(V–) + 1
126
(V+) – 1.4
OPA2206,
(V–) + 1 V < VCM < (V+) –
1.4 V
140
140
140
140
TA = –40°C to +125°C
TA = –40°C to +125°C
124
126
124
Common-mode rejection
ratio
CMRR
dB
OPA2206A,
(V–) + 1 V < VCM < (V+) –
1.4 V
INPUT OVERVOLTAGE
Input overvoltage
TA = –40℃ to +125℃
(V–) – 40
(V+) + 40
10
V
protection
VS = 0 V,
(V–) – 40 V < VCM < (V+) +
40 V
4.8
Input current in overvoltage
protected mode
mA
TA = –40°C to +125°C
See typical curves
INPUT IMPEDANCE
ZID
Differential
9 || 4.4
MΩ || pF
GΩ || pF
ZICM
Common-mode
300 || 4.3
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UNIT
SBOSA11A – MARCH 2020 – REVISED MARCH 2021
6.6 Electrical Characteristics: VS = ±15 V (continued)
at TA = 25°C, VCM = VOUT = midsupply and RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
OPEN-LOOP GAIN
RL = 10 kΩ,
(V–) + 200 mV < VO < (V+) –
200 mV
132
132
126
126
135
135
132
130
OPA2206,
TA = –40°C to +125°C
RL = 2 kΩ,
(V–) + 350 mV < VO < (V+) –
350 mV
AOL
Open-loop voltage gain
dB
RL = 10 kΩ,
(V–) + 200 mV < VO < (V+) –
200 mV
OPA2206A,
TA = –40°C to +125°C
RL = 2 kΩ,
(V–) + 350 mV < VO < (V+) –
350 mV
FREQUENCY RESPONSE
GBW
SR
Gain-bandwidth product
CL = 30 pF
3.6
4
MHz
V/μs
Slew rate
10-V step, G = –1
RL = 10 kΩ, CL = 25 pF
Phase margin
67
2.8
degrees
To 0.024% (12-bit),
10-V step, G = 1,
CL = 30 pF
Falling
Rising
tS
Settling time
μs
4.5
0.2
Overload recovery time
G = –10
μs
%
Total harmonic distortion +
noise
THD+N
VO = 5 VPP, G = +1, f = 1 kHz, RL = 2 kΩ
0.0004
OUTPUT
RL = 10 kΩ
AOL > 126 dB
(V–) + 0.2
(V–) + 0.35
(V–) + 0.2
(V+) + 0.2
(V+) + 0.35
(V+) + 0.2
Voltage output swing from
rail
RL = 2 kΩ
V
TA = –40°C to +125°C, RL = 10 kΩ
ISC
Short-circuit current
Capacitive load drive
±25
mA
CLOAD
See Typical Characteristics
See Typical Characteristics
Open-loop output
impedance
RO
POWER SUPPLY
220
240
310
Quiescent current per
amplifier
IQ
IO = 0 mA
μA
TA = –40°C to +125°C
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6.7 Typical Characteristics
at TA = 25°C, VS = ±15 V, VCM = VOUT = midsupply, and RL = 10 kΩ (unless otherwise noted)
Table 6-1. Table of Graphs
DESCRIPTION
FIGURE
Figure 6-1
Figure 6-2
Figure 6-3
Figure 6-4
Figure 6-5
Figure 6-6
Figure 6-7
Figure 6-8
Figure 6-9
Offset Voltage Production Distribution at 25°C
Offset Voltage Distribution at 125°C
Offset Voltage Distribution at -40°C
Offset Voltage vs Temperature
Offset Voltage Drift Production Distribution
Offset Voltage vs Output Voltage
Offset Voltage vs Power Supply Voltage
Power-Supply Rejection Ratio vs Temperature
Power-Supply and Common-Mode Rejection Ratio vs Frequency
Common-Mode Rejection Ratio vs Temperature
Offset Voltage vs Common-Mode Voltage
Offset Voltage vs Vcm at Low Supply
Offset Voltage vs Vcm at High Supply
Open-Loop Gain and Phase vs Frequency
Open-Loop Gain vs Distance from Supply
Open-Loop Gain vs Temperature
Figure 6-10
Figure 6-11
Figure 6-12
Figure 6-13
Figure 6-14
Figure 6-15
Figure 6-16
Figure 6-17
Figure 6-18
Figure 6-19
Figure 6-20
Figure 6-21
Figure 6-22
Figure 6-23
Figure 6-24
Figure 6-25
Figure 6-26
Figure 6-27
Figure 6-28
Figure 6-29
Figure 6-30
Figure 6-31
Figure 6-32
Figure 6-34
Figure 6-34
Figure 6-35
Figure 6-36
Figure 6-37
Figure 6-38
Figure 6-39
Figure 6-40
Figure 6-41
Figure 6-42
Figure 6-43
Figure 6-44
Figure 6-45
Figure 6-46
Closed-Loop Gain vs Frequency
Input Bias Production Distribution
Input Bias vs Common-Mode Voltage
Input Bias and Input Offset Current vs Temperature
Input Bias vs. Overvoltage Protected Common Mode Range
Input Offset Current Production Distribution
Voltage Noise Density vs Frequency
0.1-Hz To 10-Hz Noise
Total Harmonic Distortion + Noise Ratio vs Frequency
Total Harmonic Distortion + Noise Ratio vs Output Amplitude
Current Noise vs Frequency
Maximum Output Voltage vs Frequency
Output Voltage Swing vs Output Sourcing Current
Output Voltage Swing vs Output Sinking Current
Open-Loop Output Impedance vs Frequency
No Phase Reversal
Small-Signal Overshoot vs Capacitive Load, Gain = +1
Small-Signal Overshoot vs Capacitive Load, Gain = -1
Phase Margin vs Capacitive Load
Positive Overload Recovery, Gain = -1
Negative Overload Recovery, Gain = -1
Settling Time
Small-Signal Step Response, Gain = +1
Small-Signal Step Response, Gain = -1
Large-Signal Step Response, Gain = +1
Large-Signal Step Response, Gain = -1
Short-Circuit Current vs Temperature
Electromagnetic Interference Rejection (EMIRR)
Quiescent Current vs Supply Voltage
Quiescent Current vs Temperature
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6.7 Typical Characteristics
at TA = 25°C, VS = ±15 V, VCM = VOUT = midsupply, and RL = 10 kΩ (unless otherwise noted)
20
18
16
14
12
10
8
25
20
15
10
5
6
4
2
0
0
-10
-8
-6
-4
-2
0
2
4
6
8
10
-20
-15
-10
-5
0
5
10
15
20
125
15
Input-referenced Offset Voltage (µV)
Offset Voltage (µV)
Figure 6-1. Offset Voltage Production Distribution at 25°C
Figure 6-2. Offset Voltage Distribution at 125°C
20
20
10
0
15
10
5
+3 Sigma
–3 Sigma
-10
0
-20
-20
-50
-15
-10
-5
0
5
10
15
20
-25
0
25
50
75
100
Offset Voltage (µV)
Temperature (°C)
Figure 6-3. Offset Voltage Distribution at -40°C
Figure 6-4. Offset Voltage vs Temperature
15
12
9
10
5
0
6
-5
TA = –40°C
TA = 25°C
TA = 85°C
TA = 125°C
3
0
-10
-15
-0.1 -0.08 -0.06 -0.04 -0.02
0
0.02 0.04 0.06 0.08 0.1
-10
-5
0
5
10
Offset Voltage Drift (µV/°C)
Output Voltage (V)
Figure 6-5. Offset Voltage Drift Production Distribution
Figure 6-6. Offset Voltage vs Output Voltage
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6.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, VCM = VOUT = midsupply, and RL = 10 kΩ (unless otherwise noted)
200
190
180
170
160
150
140
0.0001
0.001
0.01
10
5
0
-5
0.1
-10
-50
-25
0
25
50
75
100
125
0
10
20
30
40
Temperature (°C)
Supply Voltage (V)
Figure 6-7. Offset Voltage vs Power Supply Voltage
Figure 6-8. Power-Supply Rejection Ratio vs Temperature
160
150
140
130
120
0.01
0.1
1
160
CMRR
–PSRR
+PSRR
140
120
100
80
60
40
20
0
1
10
100
1k
10k
100k
1M
10M
-50
-25
0
25
50
75
100
125
Frequency (Hz)
Temperature (°C)
Figure 6-9. Power-Supply and Common-Mode Rejection Ratio
vs Frequency
Figure 6-10. Common-Mode Rejection Ratio vs Temperature
10
15
10
5
5
0
0
-5
-5
-10
-10
-14.5
-14
-13.5
-13
-15
-10
-5
0
5
10
14
Common-mode Voltage (V)
Common-mode Voltage (V)
Figure 6-11. Offset Voltage vs Common-Mode Voltage
Figure 6-12. Offset Voltage vs Vcm at Low Supply
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6.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, VCM = VOUT = midsupply, and RL = 10 kΩ (unless otherwise noted)
15
10
5
160
140
120
100
80
240
Gain
Phase 200
160
120
80
60
40
40
0
0
20
-40
-80
-120
0
-5
12.5
-20
100m
13
13.5
14
1
10
100
1k
10k
100k
1M
10M
Common-mode Voltage (V)
Frequency (Hz)
Figure 6-13. Offset Voltage vs Vcm at High Supply
Figure 6-14. Open-Loop Gain and Phase vs Frequency
180
0.001
0.01
0.1
180
170
160
150
140
130
120
0.001
0.01
0.1
RL = 2 kohm
RL = 10 kohm
160
140
120
100
80
1
10
100
1
125
60
0.09
1000
0.15
-50
-25
0
25
50
75
100
0.1
0.11
0.12
0.13
0.14
Temperature (°C)
Distance from the Supply (V)
Figure 6-16. Open-Loop Gain vs Temperature
Figure 6-15. Open-Loop Gain vs Distance from Supply
50
40
Gain = +1
Gain = –1
Gain = +10
Gain = +100
40
30
20
10
0
35
30
25
20
15
10
5
-10
-20
-30
0
100
1k
10k
100k
1M
10M
-500 -400 -300 -200 -100
0
100 200 300 400 500
Frequency (Hz)
Input Bias Current (pA)
Figure 6-17. Closed-Loop Gain vs Frequency
Figure 6-18. Input Bias Production Distribution
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6.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, VCM = VOUT = midsupply, and RL = 10 kΩ (unless otherwise noted)
2.5
2
0.75
0.6
0.45
0.3
0.15
0
TA = –40°C
TA = 25°C
TA = 85°C
TA = 125°C
IB–
IB+
IOS
1.5
1
0.5
0
-0.5
-1
-1.5
-2
-2.5
-15 -12
-9
-6
-3
0
3
6
9
12
15
-50
-25
0
25
50
75
100
125
Common-Mode Voltage (V)
Temperature (°C)
Figure 6-19. Input Bias vs Common-Mode Voltage
Figure 6-20. Input Bias and Input Offset Current vs Temperature
7.5
50
5
2.5
0
40
30
20
10
0
-2.5
-5
TA = –40°C
TA = 25°C
TA = 85°C
TA = 125°C
-7.5
-60
-40
-20
0
20
40
60
-450
-300
-150
0
150
300
450
Common-mode Voltage (V)
Input-referenced Offset Current (pA)
Figure 6-21. Input Bias vs. Overvoltage Protected Common
Mode Range
Figure 6-22. Input Offset Current Production Distribution
100
10
1
100m
1
10
100
1k
10k
100k
Frequency (Hz)
Time (1 s/div)
Figure 6-23. Voltage Noise Density vs Frequency
Figure 6-24. 0.1-Hz To 10-Hz Noise
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6.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, VCM = VOUT = midsupply, and RL = 10 kΩ (unless otherwise noted)
-70
-80
-60
-66
G = –1, 10 kohm Load
G = –1, 2 kohm Load
G = +1, 10 kohm Load
G = +1, 2 kohm Load
G = +1, 2 kohm Load
G = –1, 2 kohm Load
G = +1, 10 kohm Load
G = –1, 10 kohm Load
-72
-78
-90
-84
-90
-100
-110
-120
-96
-102
-108
-114
-120
100
1k
Frequency (Hz)
10k
10m
100m
1
10
Amplitude (VRMS
)
Figure 6-25. Total Harmonic Distortion + Noise Ratio vs
Frequency
Figure 6-26. Total Harmonic Distortion + Noise Ratio vs Output
Amplitude
1000
100
10
40
Vs = ±18 V
Vs = ±2.25 V
35
30
25
20
15
10
5
0
100m
1
10
100
1k
10k
100k
1
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
Figure 6-27. Current Noise vs Frequency
Figure 6-28. Maximum Output Voltage vs Frequency
15
12.5
10
0
TA = –40°C
TA = 25°C
TA = 85°C
-2.5
-5
TA = 125°C
7.5
5
-7.5
-10
TA = –40°C
TA = 25°C
TA = 85°C
TA = 125°C
2.5
0
-12.5
-15
0
5
10
15
20
25
30
0
5
10
15
20
25
30
Output Current (mA)
Output Current (mA)
Figure 6-29. Output Voltage Swing vs Output Sourcing Current
Figure 6-30. Output Voltage Swing vs Output Sinking Current
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6.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, VCM = VOUT = midsupply, and RL = 10 kΩ (unless otherwise noted)
1000
Input (V)
Output (V)
100
10
1
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Time (100 µs/div)
Figure 6-31. Open-Loop Output Impedance vs Frequency
Figure 6-32. No Phase Reversal
60
100
90
80
70
60
50
40
30
20
10
0
RISO = 0 ohm
RISO = 25 ohm
RISO = 50 ohm
RISO = 0 ohm
RISO = 25 ohm
RISO = 50 ohm
50
40
30
20
10
0
30
100
Capactiance (pF)
1000
30
100
1000
Capactiance (pF)
Gain = 1
Gain = -1
Figure 6-33. Small-Signal Overshoot vs Capacitive Load
Figure 6-34. Small-Signal Overshoot vs Capacitive Load
80
VOUT
VIN
70
60
50
40
30
20
10
20
100
1000
Time (500 ns/div)
Capacitance (pF)
Gain = –1
Figure 6-36. Positive Overload Recovery
Figure 6-35. Phase Margin vs Capacitive Load
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6.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, VCM = VOUT = midsupply, and RL = 10 kΩ (unless otherwise noted)
3
Falling (mV)
Rising (mV)
2
1
0
-1
-2
VOUT
VIN
-3
2
3
4
5
6
Time (500 ns/div)
Time (uS)
Gain = –1
Figure 6-37. Negative Overload Recovery
Figure 6-38. Settling Time
VOUT (V)
VIN (V)
VOUT (V)
VIN (V)
Time (1 µS/Div)
Time (1 µS/Div)
Gain = 1
Gain = –1
Figure 6-39. Small-Signal Step Response
Figure 6-40. Small-Signal Step Response
VIN (V)
VOUT (V)
VOUT (V)
VIN (V)
Time (2 µS/Div)
Time (2 µS/Div)
Gain = 1
Gain = –1
Figure 6-41. Large-Signal Step Response
Figure 6-42. Large-Signal Step Response
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6.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, VCM = VOUT = midsupply, and RL = 10 kΩ (unless otherwise noted)
28
25
22
19
16
13
10
140
130
120
110
100
90
80
70
60
Positive Output Voltage
Negative Output Voltage
50
40
-50
-25
0
25
50
75
100
125
10
100
Frequency (MHz)
1000
6000
Temperature (°C)
Figure 6-43. Short-Circuit Current vs Temperature
Figure 6-44. Electromagnetic Interference Rejection (EMIRR)
250
360
320
280
240
200
160
120
200
150
100
50
Vs = 4.5 V
0
0
8
16
24
32
40
-50
-25
0
25
50
75
100
125
Supply Voltage (V)
Temperature (°C)
Figure 6-45. Quiescent Current vs Supply Voltage
Figure 6-46. Quiescent Current vs Temperature
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7 Parameter Measurement Information
7.1 Typical Specifications and Distributions
Designers often have questions about a typical specification of an amplifier in order to design a more robust
circuit. As a result of natural variations in process technology and manufacturing procedures, every specification
of an amplifier exhibits some amount of deviation from the ideal value, such as the input bias current of an
amplifier. These deviations often follow Gaussian (bell curve), or normal distributions. Circuit designers can
leverage this information to guardband their system, even when there is no minimum or maximum specification
in the Electrical Characteristics.
0.00312% 0.13185%
0.13185% 0.00312%
0.00002%
0.00002%
2.145% 13.59% 34.13% 34.13% 13.59% 2.145%
1
1 1 1 1 1 1 1 1
1
1
1
ꢀ-61 ꢀ-51 ꢀ-41 ꢀ-31 ꢀ-21 ꢀ-1
ꢀ+1 ꢀ+21 ꢀ+31 ꢀ+41 ꢀ+51 ꢀ+61
ꢀ
Figure 7-1. Ideal Gaussian Distribution
Figure 7-1 shows an example distribution, where µ, is the mean of the distribution, and where σ, or sigma, is the
standard deviation of a system. For a specification that exhibits this kind of distribution, approximately two-thirds
(68.26%) of all units can be expected to have a value within one standard deviation, or one sigma, of the mean
(from µ–σ to µ+σ).
Depending on the specification, values listed in the typical column of Electrical Characteristics are represented
in different ways. As a general guideline, if a specification naturally has a nonzero mean (for example, gain
bandwidth), then the typical value is equal to the mean (µ). However, if a specification naturally has a mean near
zero (for example, input bias current), then the typical value is equal to the mean plus one standard deviation (µ
+ σ) to most accurately represent the typical value.
Use this chart to calculate the approximate probability of a specification in a unit. For example, the OPA2206
typical input bias current is ±0.1 nA; therefore, 68.2% of all devices are expected to have an input bias from ±0.1
nA. At 4σ, 99.9937% of the distribution has an input bias less than ±0.28 nA, which means that 0.0063% of the
population is outside of these limits, and corresponds to approximately 1 in 15,873 units.
Units that are found to exceed any tested minimum or maximum specifications are removed from production
material. For example, the OPA2206 has a maximum input bias of ±0.4 nA at 25°C, and although this value
corresponds to approximately 6σ (~1 in 500 million units), TI removes any unit with a larger input bias from
production material.
For specifications with no value in the minimum or maximum column, consider selecting a sigma value of
sufficient guardband for your application, and design worst-case conditions using this value. This information
should only be used to estimate the performance of a device.
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8 Detailed Description
8.1 Overview
The OPA2206 is the first 36-V, bipolar, e-trim operational amplifier. This device uses a package-level offset trim
to minimize the offset voltage and offset voltage drift introduced during the manufacturing process. This trim is
performed after the device is assembled to remove any offset errors introduced throughout the manufacturing
process, and trim communication is disabled afterward. The device features super beta inputs that decrease the
input bias current and input current noise. The device also features input overvoltage protection that protects the
device for input voltages up to ±40 V beyond either supply rail.
8.2 Functional Block Diagram
V+
e-trimTM
Pre-Driver
OUT
Super Beta
Input Devices
+IN
IN
Overvoltage
Protection
Overload
Power
Limiter
V
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8.3 Feature Description
8.3.1 Input Overvoltage Protection
The inputs of the OPA2206 are individually protected for voltages up to ±40 V beyond either supply. For
example, a common-mode voltage anywhere between –55 V and +55 V does not cause damage when powered
from ±15-V supplies. Internal circuitry on each input provides low series impedance under normal signal
conditions thus maintaining high performance under normal operating conditions. If the input is overloaded,
the protection circuitry limits the input current to a value of approximately 4.8 mA.
During an input overvoltage condition, current flows through the input protection diodes into the power supplies,
as shown in Figure 8-1. If the power supplies are unable to sink current, then Zener diode clamps (ZD1 and
ZD2) must be placed on the power supplies to provide a current pathway to ground. During an overvoltage
condition, the input bias current of the inputs increase as shown in Figure 8-2.
+V
ZD1
+VS
IN
Overvoltage
Protection
Input Voltage
Source
+
Input Transistor
œ
-VS
ZD2
-V
Figure 8-1. OPA2206 Input Overvoltage Current Path
Figure 8-2 shows the input current for input voltages from –55 V to +55 V when the OPA2206 is powered by
±15-V supplies.
7.5
5
2.5
0
-2.5
TA = –40°C
TA = 25°C
TA = 85°C
TA = 125°C
-5
-7.5
-60
-40
-20
0
20
40
60
Common-mode Voltage (V)
Figure 8-2. OPA2206 Input Current vs Input Voltage (VS = ±15 V)
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8.3.2 Input Offset Trimming
The OPA2206 is the industry's first e-trim operational amplifier built on a bipolar process. The input offset
voltage of an amplifier is determined by the inherent mismatch between the input transistors. The offset can
be minimized using laser-trimming performed during the manufacturing process while the device is still in the
bare silicon form. However, when the silicon is packaged, the packaging process introduces additional offset due
to mechanic stresses. TI's new trimming processes are used to trim the offset after the packaging process is
complete to minimize both inherent and package-induced offsets. After trimming, communication is disabled to
make sure the amplifier operates properly in the final system.
A comparison between production offset values for a the industry popular, laser-trimmed OPA2277 amplifier and
the OPA2206 proprietary trim can be seen in Figure 8-3 and Figure 8-4.
20
18
16
14
12
10
8
16
14
12
10
8
Typical distribution
of packaged units.
Single, dual, and
quad included.
6
6
4
4
2
2
0
0
–50–45–40–35–30–25–20–15–10–5
0 5 10 15 20 25 30 35 40 45 50
-50 -40 -30 -20 -10
0
10
20
30
40
50
Offset Voltage (µV)
Input-referenced Offset Voltage (µV)
Figure 8-3. OPA2277 Laser-Trimmed Operational
Amplifier Offset
Figure 8-4. OPA2206 e-trim™ Operational Amplifier
Offset
The OPA2206 is also trimmed at two temperatures to minimize the input offset voltage drift over temperature.
The final performance of the offset drift can be seen in Figure 8-5.
15
12
9
6
3
0
-0.1 -0.08 -0.06 -0.04 -0.02
0
0.02 0.04 0.06 0.08 0.1
Offset Voltage Drift (µV/°C)
Figure 8-5. OPA2206 e-trim™ Operational Amplifier Drift
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8.3.3 Lower Input Bias With Super-Beta Inputs
The OPA2206 has a super-beta input transistor architecture. In a transistor, the beta value is the ratio between
the current flowing into the base and the current flowing from the collector to the emitter. A super-beta transistor
is one where the beta value has been increased from several hundred to thousands. In a bipolar amplifier, the
input bias current is the current flowing into the base of the input transistor pair, as well as a small leakage
current that flows through the ESD diodes. A super-beta input reduces the input bias current of the amplifier. In
addition, the super-beta inputs lower the input current noise that is directly related to the input bias current of the
device. A comparison between the input bias current of the OPA2277 and the OPA2206 super-beta input bias
currents can be seen in Figure 8-6 and Figure 8-7.
5
4
6
5
IBN
IBP
4
3
3
2
2
1
1
0
0
–1
–2
–3
–4
–5
-1
-2
-3
-4
-5
Curves represent typical
production units.
–75
–50
–25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
Figure 8-6. OPA2277 Input Bias Current
8.3.4 Overload Power Limiter
Figure 8-7. OPA2206 Super-Beta Input Bias Current
In many bipolar-based amplifiers, the output stage of the amplifier can draw significant (several milliamperes)
of quiescent current if the output voltage becomes clipped (meaning the output voltage becomes limited by the
negative or positive supply voltage). This condition can cause the system to enter a high-power consumption
state, and potentially cause oscillations between the power supply and signal chain. The OPA2206 has an
advanced output stage design that eliminates this problem. When the output voltage reaches the either supply
(V+ or V–), there is virtually no additional current consumption from the nominal quiescent current. This feature
helps eliminate any potential system problems when the signal chain is disrupted by a large external transient
voltage.
8.3.5 EMI Rejection
The OPA2206 uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from
sources, such as wireless communications and densely-populated boards with a mix of analog signal chain and
digital components. EMI immunity can be improved through circuit design techniques that improve the system
performance. Additional information can be found in the EMI Rejection Ratio of Operation Amplifiers application
report.
8.4 Device Functional Modes
The OPA2206 has two functional modes. The device enters normal operation with any supply between 4.5 V
(±2.25 V) and 36 V (±18 V), and an input voltage that meets the input common-mode voltage range shown in
Section 6.
If the input voltage exceeds the device specifications, the device will enter an overvoltage protection mode. In
this mode the input overvoltage protection sub-circuit will limit the voltage and current seen by the amplifier
core by adding additional impedance between the input pins and the amplifier core. Additional current that
is generated from the voltage drop across this input impedance is routed through the ESD structure of the
OPA2206, as shown in Figure 8-1.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The OPA2206 is a unity-gain stable operational amplifier with very low offset voltage, offset voltage drift, voltage
noise, current noise, and power consumption. The built-in overvoltage protection allows the device to protect
against signals outside of the expected range, a reverse connection, or in cases where the inputs are shorted
to a system supply. These features make this device a great choice for a variety of space-constrained and
power-constrained systems by removing the need for discrete protection such as clamping diodes.
9.2 Typical Applications
9.2.1 Voltage Attenuator
80 k
20 k
12 V
±10 V
12 V
2.2 nF
100 nF
GND
100 nF
GND
–
+
3.74 k
11.8 k
2.2 nF
6.65 k
–
Output
OPA2206
+
2 V
OPA2206
330 pF
GND
100 nF
GND
100 nF
GND
12 V
12 V
GND
Figure 9-1. OPA2206 Configured as a Voltage Attenuator
9.2.1.1 Design Requirements
The design requirements for this system are:
•
•
•
•
•
Input signal range: ±10 V
Input signal frequency: up to 10 kHz
3rd-order Butterworth filter -3-dB frequency: 20 kHz
Output voltage: 0 V to 5 V
Input protection: up to ±52 V
9.2.1.2 Detailed Design Procedure
In this design, a ±10-V, 10-kHz bandwidth, bipolar signal is attenuated and converted to a single-ended signal
and filtered by a 3rd-order Butterworth filter to drive a single-ended analog-to-digital converter (ADC). By using
the OPA2206, the input of the signal chain is protected from overvoltages up to 40 V beyond either supply. This
signal-chain design is common for programmable logic controllers (PLCs), low-power data acquisition systems
(DAQs) and field instruments where high precision, low power and signal fault protection are needed.
The OPA2206 was selected for this application because of the high supply range, high dc precision (2-µV offset
and 0.04-µV/°C offset drift), and low power consumption (220-µA quiescent current) that minimizes thermal
dissipation requirements. Because of the internal OVP topology, the device provides better dc and ac accuracy
under normal operating conditions compared to passive external protection and results in a smaller system
solution. Be sure to connect a zener diode between each supply to ground to provide a return path for the
current that is generated during a fault condition.
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The first stage of the signal chain is an attenuator and level-shifter. The input signal to this stage is bipolar ±10 V
that is attenuated to ±2.5 V, and then level-shifted so that the output is a single-ended, 0-V to 5-V signal. The
feedback and gain resistors were selected as 20 kΩ and 80 kΩ, respectively. Thus, the combined impedance
is 100 kΩ, which lowers the input current to the signal chain, and minimizes errors resulting from higher output
impedance sensors.
The second stage of the signal chain uses the second channel of the OPA2206 to create a 3rd-order Butterworth
filter with a –3-dB response of 20 kHz. For more information on filter design, refere to Texas Instrument's filter
design tool.
The output of this signal chain is shown in Figure 9-2 and the filter response is shown in Figure 9-3.
9.2.1.3 Application Curves
10
8
0
-20
Input
Output
6
4
-40
2
0
-60
-2
-4
-6
-8
-10
-80
-100
0.01
0.1
1
10
100
1000
0.2
0.24
0.28
0.32
0.36
0.4
Frequency (kHz)
Time (ms)
Figure 9-3. Attenuator + Filter Response
Figure 9-2. Input and Output Signal
9.2.2 Discrete, Two-Op-Amp Instrumentation Amplifier
Figure 9-4 shows the OPA2206 configured as a two op amp, discrete instrumentation amplifier. This
configuration allows for a differential signal measurement, such as the signal from a load cell, with higher input
impedance to the signal chain than most monolithic instrumentation amplifiers. Additionally, the input overvoltage
protection of the OPA2206 protects the signal chain from being damaged by fault conditions where the input
signal exceeds the supply voltage of the amplifier.
V+
V1
+
–
V
OUT = (V1 – V2)(1 + R2/R1)
OPA2206
R2
V
V+
R1
V2
+
–
OPA2206
V
R2
R1
GND
Figure 9-4. OPA2206 Configured as a Two Op Amp, Discrete Instrumentation Amplifier
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9.2.3 Input Buffer and Protection for ADC Driver
Section 9.2.1.1 shows the OPA2206 configured as an input buffer for an ADC driver using the THP210. The
high dc precision and low noise of the OPA2206 make this device an excellent choice for precision signal
chain conditioning. The low input bias of the amplifier minimizes dc errors created for higher output impedance
sensors. The integrated input overvoltage protection prevents damage to the signal chain due to an input fault
condition where the signal exceeds the supply range of the OPA2206, or if the inputs are shorted to a higher
supply rail. For more information on designing a precision ADC driver,see .
909
V+
470 pF
V+
2.1 k
2.74 k
100
–
+
OPA2206
1 nF
V
THP210
–
+
+
–
Input
Signal
VCM
ADS8912B
1.1 nF
2.1 k
V+
1 nF
GND
V
–
+
2.74 k
100
OPA2206
470 pF
V
909
Figure 9-5. OPA2206 Configured as Input-Signal-Chain Buffer
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10 Power Supply Recommendations
The OPA2206 operates with a supply between 4.5 V (±2.25 V) and 36 V (±18 V). Parameters that can exhibit
significant variance with regard to operating voltages are presented in Section 6.7.
11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
•
Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close
to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-supply
applications. Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as
well as through the individual op amp. Bypass capacitors are used to reduce the coupled noise by providing
low-impedance power sources local to the analog circuitry.
•
•
Make sure to physically separate digital and analog grounds and pay attention to the flow of the ground
current. Separate grounding for analog and digital portions of circuitry is one of the simplest and most
effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to
ground planes. A ground plane helps distribute heat and reduces EMI noise pickup.
In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better,
as opposed to in parallel with the noisy trace.
•
•
•
Place the external components as close to the device as possible. As shown in Figure 11-1, keep RF and RG
close to the inverting input to minimize parasitic capacitance.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
•
•
Clean the PCB following board assembly for best performance.
Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic
package. After any aqueous PCB cleaning process, bake the PCB assembly to remove moisture introduced
into the device packaging during the cleaning process. A low-temperature, post-cleaning bake at 85°C for 30
minutes is sufficient for most circumstances.
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11.2 Layout Example
VIN
+
VOUT
RG
RF
Figure 11-1. Schematic Representation
Place components close
to device and to each
other to reduce parasitic
errors
Run the input traces
as far away from
the supply lines
as possible
VS+
RF
NC
NC
Use a low-ESR,
ceramic bypass
capacitor
RG
GND
œIN
+IN
Vœ
V+
OUTPUT
NC
VIN
GND
GND
VSœ
VOUT
Ground (GND) plane on another layer
Use low-ESR,
ceramic bypass
capacitor
Figure 11-2. Operational Amplifier Board Layout for Noninverting Configuration
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
The following evaluation modules are available:
•
•
DIP-ADAPTER-EVM
DIYAMP-EVM
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
e-trim™ and TI E2E™ are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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13-Apr-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA2206ADGKR
OPA2206ADGKT
OPA2206DGKR
ACTIVE
ACTIVE
VSSOP
VSSOP
VSSOP
DGK
DGK
DGK
8
8
8
2500 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Call TI
-40 to 125
-40 to 125
-40 to 125
22A6
22A6
250
RoHS & Green
NIPDAU
Call TI
PREVIEW
2500
Non-RoHS &
Non-Green
XOPA2206DGKR
ACTIVE
VSSOP
DGK
8
2500
Non-RoHS &
Non-Green
Call TI
Call TI
-40 to 125
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
13-Apr-2021
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Apr-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA2206ADGKR
OPA2206ADGKT
VSSOP
VSSOP
DGK
DGK
8
8
2500
250
330.0
180.0
12.4
12.4
5.3
5.3
3.4
3.4
1.4
1.4
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Apr-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA2206ADGKR
OPA2206ADGKT
VSSOP
VSSOP
DGK
DGK
8
8
2500
250
853.0
210.0
449.0
185.0
35.0
35.0
Pack Materials-Page 2
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Copyright © 2021, Texas Instruments Incorporated
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