OPA2333P [TI]
GBW 大于 300kHz 的业内极致小尺寸、低功耗、高精度双路运算放大器;
| 型号： | OPA2333P |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | GBW 大于 300kHz 的业内极致小尺寸、低功耗、高精度双路运算放大器 放大器 运算放大器 |
| 文件： | 总30页 (文件大小：1929K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Support &
Community
Product
Folder
Order
Now
Tools &
Software
Technical
Documents
OPA2333P
ZHCSH14A –NOVEMBER 2017–REVISED DECEMBER 2017
OPA2333P 1.8V 微功耗零温漂运算放大器
1 特性
3 说明
1
•
•
•
•
•
•
•
•
•
低失调电压：10μV（最大值）
OPA2333P 是一款 CMOS 运算放大器，其使用专有自
动校准技术，可提供极低的失调电压（10μV，最大
值），同时随时间推移和温度变化实现接近于零的漂
移。这种高精度、低静态电流的微型放大器可提供高阻
抗输入（共模范围超出电源轨电压 100mV）和轨至轨
输出（摆幅在电源轨的 50mV 范围内）。此器件可以
使用低至 1.8V (±0.9V) 和高达 5.5V (±2.75V) 的单电
源或双电源，针对低电压、单电源运行情况进行了优
化。
零温漂：0.05μV/°C（最大值）
额定启动时间：500μs（最大值）
0.01Hz 至 10Hz 噪声：1.1μVPP
静态电流：17μA
单电源供电
电源电压：1.8V 至 5.5V
轨到轨输入/输出
微型封装尺寸：2mm × 2mm WSON
此外，OPA2333P 还 具有 额定最大启动时间。该额定
启动时间可确保放大器供电后 500μs 时间范围内具有
高精度性能，从而实现动态电源运行下的可靠耐用性。
2 应用
•
•
•
•
•
•
•
•
智能手机
可穿戴设备
健身和保健产品
电子称
OPA2333P 提供出色的 CMRR，而不存在与传统互补
输入级关联的交叉。该设计可在驱动模数转换器
(ADC) 的过程中实现优异的性能，而不会降低微分线
性。
医疗仪表
电池供电的仪器
手持测试设备
断路器
OPA2333P 采用 2mm × 2mm 8 引脚 WSON 封装以
及 额定工作温度范围是 –40°C 至 125°C。
器件信息(1)
器件型号
OPA2333P
封装
WSON (8)
封装尺寸（标称值）
2.00mm x 2.00mm
(1) 要了解所有可用封装，请参阅数据表末尾的可订购产品附录。
双向低侧电流分流放大器
失调电压与温度间的关系
-40èC
125èC
VREF
10
8
+5 V
œ
6
4
OPA2333P
+
Battery /
Power
VMIDSCALE
2
0
Supply
-2
-4
-6
-8
-10
Microcontroller
ADC
+
RSENSE
OPA2333P
-55
-25
5
35
65
95
125
150
Temperature (èC)
œ
+5 V
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SBOS908
OPA2333P
ZHCSH14A –NOVEMBER 2017–REVISED DECEMBER 2017
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information: OPA2333P.............................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 6
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 10
7.4 Device Functional Modes........................................ 13
8
9
Application and Implementation ........................ 14
8.1 Application Information............................................ 14
8.2 Typical Application .................................................. 14
Power Supply Recommendations...................... 18
10 Layout................................................................... 20
10.1 Layout Guidelines ................................................. 20
10.2 Layout Example .................................................... 20
11 器件和文档支持 ..................................................... 21
11.1 器件支持................................................................ 21
11.2 文档支持................................................................ 21
11.3 接收文档更新通知 ................................................. 21
11.4 社区资源................................................................ 21
11.5 商标....................................................................... 21
11.6 静电放电警告......................................................... 21
11.7 Glossary................................................................ 21
12 机械、封装和可订购信息....................................... 21
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (November 2017) to Revision A
Page
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
已删除 从标题中删除了“CMOS”并更改了措辞........................................................................................................................ 1
已添加 向“说明”中添加了新段落 2 ......................................................................................................................................... 1
已更改 更改了第 1 页的图形................................................................................................................................................... 1
Changed "DFN" to "DSG" Package ....................................................................................................................................... 3
Changed footnote reference for Common-mode and "0.5" V to "0.3" V in footnote 2 ........................................................... 4
Changed "10 mA" to "1 mA" in Abs Max footnotes 2 and 3................................................................................................... 4
Changed "-40" to "-55" in Abs Max MIN for TA ...................................................................................................................... 4
Changed "5" to "±5" in PSRR row of Electrical Characteristics ............................................................................................ 5
Deleted "±400" from second row of IB in Electrical Characteristics ....................................................................................... 5
Changed "100" Hz to "10" Hz in iN row of Electrical Characteristics ..................................................................................... 5
Deleted second row for AOL in Electrical Characteristics ..................................................................................................... 5
Deleted "CL = 100 pF" from Phase margin and Gain-bandwidth product rows of Electrical Characteristics ........................ 5
Deleted "RL = 2 kohm" rows ................................................................................................................................................. 5
Deleted from OUTPUT subsection of Electrical Characteristics ........................................................................................... 5
Deleted "±" from "5" in TYP column of ISC row in Electrical Characteristics ........................................................................ 5
Changed "Turnon" to "Start-up" in OUTPUT subsection of Electrical Characteristics .......................................................... 5
已添加 "Quiescent Current Production Distribution" graph ................................................................................................... 6
已更改 "DFN" to "WSON"; "SON" to "DFN" in WSON Package ......................................................................................... 13
已删除 "Single-Supply, Very Low Power, ECG Circuit" graphic........................................................................................... 18
已删除 删除了开发支持 中的“THS4281 极低功耗、高速、轨至轨输入和输出电压反馈运算放大器”.................................... 21
2
Copyright © 2017, Texas Instruments Incorporated
OPA2333P
www.ti.com.cn
ZHCSH14A –NOVEMBER 2017–REVISED DECEMBER 2017
5 Pin Configuration and Functions
DSG Package
8-Pin WSON With Exposed Thermal Pad
Top View
OUT A
œIN A
+IN A
Vœ
V+
1
2
3
4
8
7
6
5
OUT B
Thermal
Pad
œIN B
+IN B
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
+IN A
NO.
3
I
I
Noninverting input, channel A
Noninverting input, channel B
Inverting input, channel A
Inverting input, channel B
Output, channel A
+IN B
–IN A
–IN B
OUT A
OUT B
V+
5
2
I
6
I
1
O
O
—
—
—
7
Output, channel B
8
Positive (highest) power supply
Negative (lowest) power supply
Thermal Pad, Connect to V–
V–
4
Thermal Pad
—
Copyright © 2017, Texas Instruments Incorporated
3
OPA2333P
ZHCSH14A –NOVEMBER 2017–REVISED DECEMBER 2017
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
7
UNIT
V
Single-supply
Dual-supply
Supply voltage, VS = (V+)
- (V-)
±3.5
Common-mode(2)
Differential(3)
(V–) – 0.3
(V+) + 0.3
±0.5
Voltage
Current
Signal input pins
Output short current(4)
Temperature
±10
mA
Continuous
Operating, TA
Junction, TJ
Storage, Tstg
–55
–65
150
150
150
°C
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.3 V beyond the supply rails must
be current-limited to 1 mA or less.
(3) Input terminals are anti-parallel diode-clamped to each other. Input signals that can cause differential voltages of swing more than ±0.5
V must be current-limited to 1 mA or less.
(4) Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
±4000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins(2)
±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.8
NOM
MAX
5.5
UNIT
Single supply
Dual supply
VS
Supply voltage, [ (V+) – (V–) ]
Specified temperature
V
±0.9
–40
±2.75
125
°C
6.4 Thermal Information: OPA2333P
OPA2333P
DSG (WSON)
8 PINS
74.5
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
93.5
41.1
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
4.3
ΨJB
41.2
RθJC(bot)
15.7
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2017, Texas Instruments Incorporated
OPA2333P
www.ti.com.cn
ZHCSH14A –NOVEMBER 2017–REVISED DECEMBER 2017
6.5 Electrical Characteristics
At TA = 25°C, RL= 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
PARAMETER
OFFSET VOLTAGE
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOS
Input offset voltage
VS = 5 V
VS = 5 V
±2
0.02
1
±10
±0.05
±5
µV
dVOS/dT
PSRR
Input offset voltage drift
TA = –40°C to +125°C
TA = –40°C to +125°C
µV/°C
µV/V
µV/V
Power-supply rejection ratio 1.8 V ≤ VS ≤ 5.5 V
Channel separation, dc
0.1
INPUT BIAS CURRENT
±70
±150
±140
±200
±400
pA
pA
pA
IB
Input bias current
TA = –40°C to +125°C
IOS
Input offset current
NOISE
f = 0.1 Hz to 10 Hz, peak-to-peak
f = 0.1 Hz to 10 Hz, RMS
f = 10 Hz
1.1
0.2
55
µVPP
EN
Input voltage noise
µVRMS
nV/√Hz
nV/√Hz
fA/√Hz
eN
iN
Input voltage noise density
Input current noise density
f = 1 kHz
55
f = 10 Hz
100
INPUT VOLTAGE
Common-mode voltage
range
(V–) –
0.1
(V+) +
0.1
VCM
V
Common-mode rejection
ratio
CMRR
(V–) – 0.1 V ≤ VCM ≤ (V+) + 0.1 V, VS = 5.5 V
106
130
dB
INPUT IMPEDANCE
ZID
Differential
1013 || 2
1013 || 4
Ω || pF
Ω || pF
ZICM
Common-mode
OPEN-LOOP GAIN
(V–) + 100 mV ≤ VO
(V+) – 100 mV, RL = 10 kΩ
≤
AOL
Open-loop voltage gain
TA = –40°C to +125°C
106
130
dB
FREQUENCY RESPONSE
φm
Phase margin
VO = 10 mVPP
VO = 10 mVPP
VO = 4-V step
65
350
Degrees
kHz
GBW
SR
Gain-bandwidth product
Slew rate
G = 1
0.16
V/µs
OUTPUT
30
50
70
mV
mV
mA
Output voltage swing
TA = –40°C to +125°C
ISC
CL
ZO
Short-circuit current
Capactive load drive
±5
See Typical Characteristics
Open-loop output impedance f = 350 kHz, IO = 0 mA
Start-up time VS = 5 V
POWER SUPPLY
2
kΩ
100
500
µs
VS
Specified voltage
1.8
5.5
25
28
V
17
Quiescent current (per
amplifier)
IQ
IO = 0 A
µA
TA = –40°C to +125°C
TEMPERATURE RANGE
TA
TA
Specified range
Operating range
–40
–55
125
150
°C
°C
Copyright © 2017, Texas Instruments Incorporated
5
OPA2333P
ZHCSH14A –NOVEMBER 2017–REVISED DECEMBER 2017
www.ti.com.cn
6.6 Typical Characteristics
表 1. List of Typical Characteristics
TITLE
FIGURE
图 1
Offset Voltage Production Distribution
Offset Voltage Drift Production Distribution
Quiescent Current Production Distribution
Open-Loop Gain vs Frequency
图 2
图 3
图 4
Common-Mode Rejection Ratio vs Frequency
Power-Supply Rejection Ratio vs Frequency
Output Voltage Swing vs Output Current
Input Bias Current vs Common-Mode Voltage
Input Bias Current vs Temperature
Quiescent Current vs Temperature
Large-Signal Step Response
图 5
图 6
图 7
图 8
图 9
图 10
图 11
图 12
图 13
图 14
图 15
图 16
图 17
图 18
Small-Signal Step Response
Positive Overvoltage Recovery
Negative Overvoltage Recovery
Settling Time vs Closed-Loop Gain
Small-Signal Overshoot vs Load Capacitance
0.1-Hz to 10-Hz Noise
Current and Voltage Noise Spectral Density vs Frequency
At TA = 25°C, VS = 5 V, and CL = 0 pF, unless otherwise noted.
Offset Voltage Drift (mV/°C)
Offset Voltage (mV)
图 2. Offset Voltage Drift Production Distribution
图 1. Offset Voltage Production Distribution
6
版权 © 2017, Texas Instruments Incorporated
OPA2333P
www.ti.com.cn
ZHCSH14A –NOVEMBER 2017–REVISED DECEMBER 2017
At TA = 25°C, VS = 5 V, and CL = 0 pF, unless otherwise noted.
120
100
80
60
40
20
0
250
200
150
Phase
100
50
0
Gain
-50
-20
-100
10
100
1k
10k
100k
1M
Frequency (Hz)
IQ (mA)
VS = 5.5 V
图 4. Open-Loop Gain and Phase vs Frequency
图 3. Quiescent Current Production Distribution
140
120
+PSRR
120
100
80
60
40
20
0
100
80
60
40
20
0
-PSRR
1
10
100
1k
10k
100k
1M
1
10
100
1k
10k
100k
1M
Frequency (Hz)
Frequency (Hz)
图 5. Common-Mode Rejection Ratio vs Frequency
图 6. Power-Supply Rejection Ratio vs Frequency
100
3
2
VS = ±2.75 V
VS = ±0.9 V
80
60
-IB
-40°C
40
1
+25°C
20
+125°C
0
0
+25°C
-40°C
-20
-40
-60
-80
-100
-1
-2
-3
+125°C
+25°C
+IB
-40°C
0
1
2
3
4
5
0
1
2
3
4
5
6
7
8
9
10
Common-Mode Voltage (V)
Output Current (mA)
图 8. Input Bias Current vs Common-Mode Voltage
图 7. Output Voltage Swing vs Output Current
版权 © 2017, Texas Instruments Incorporated
7
OPA2333P
ZHCSH14A –NOVEMBER 2017–REVISED DECEMBER 2017
www.ti.com.cn
At TA = 25°C, VS = 5 V, and CL = 0 pF, unless otherwise noted.
200
25
20
15
10
5
VS = 5.5 V
150
VS = 1.8 V
-IB
100
-IB
50
VS = 5.5 V
VS = 1.8 V
0
+IB
-50
-100
+IB
-150
-200
0
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
图 9. Input Bias Current vs Temperature
图 10. Quiescent Current vs Temperature
G = +1
RL = 10 kW
G = 1
RL = 10 kW
Time (5 ms/div)
Time (50 ms/div)
图 12. Small-Signal Step Response
图 11. Large-Signal Step Response
0
Input
Input
0
0
Output
10 kW
10 kW
+2.5 V
+2.5 V
1 kW
1 kW
Output
0
OPA333
OPA333
-2.5 V
-2.5 V
Time (50 ms/div)
Time (50 ms/div)
图 14. Negative Overvoltage Recovery
图 13. Positive Overvoltage Recovery
8
版权 © 2017, Texas Instruments Incorporated
OPA2333P
www.ti.com.cn
ZHCSH14A –NOVEMBER 2017–REVISED DECEMBER 2017
At TA = 25°C, VS = 5 V, and CL = 0 pF, unless otherwise noted.
600
40
35
30
25
20
15
10
5
4-V Step
500
400
300
200
0.001%
100
0.01%
0
0
10
100
1000
1
10
100
Load Capacitance (pF)
Gain (dB)
图 16. Small-Signal Overshoot
图 15. Settling Time vs Closed-Loop Gain
vs Load Capacitance
1000
100
10
1000
100
10
Continues with no 1/f (flicker) noise.
Current Noise
Voltage Noise
1
10
100
1k
10k
Frequency (Hz)
1s/div
图 17. 0.1-Hz to 10-Hz Noise
图 18. Current and Voltage Noise Spectral Density vs
Frequency
版权 © 2017, Texas Instruments Incorporated
9
OPA2333P
ZHCSH14A –NOVEMBER 2017–REVISED DECEMBER 2017
www.ti.com.cn
7 Detailed Description
7.1 Overview
The OPA2333P is a Zero-Drift, low-power, rail-to-rail input and output operational amplifier. The device operates
from 1.8 V to 5.5 V, is unity-gain stable, and is suitable for a wide range of general-purpose applications. The
Zero-Drift architecture provides ultra-low offset voltage and near-zero offset voltage drift.
7.2 Functional Block Diagram
C2
Notch
Filter
CHOP1
CHOP2
GM2
GM3
GM1
OUT
+IN
œIN
GM_FF
C1
Copyright © 2017, Texas Instruments Incorporated
7.3 Feature Description
The OPA2333P is unity-gain stable and free from unexpected output phase reversal. This device uses a
proprietary auto-calibration technique to provide low offset voltage and very low drift over time and temperature.
For lowest offset voltage and precision performance, optimize circuit layout and mechanical conditions. Avoid
temperature gradients that create thermoelectric (Seebeck) effects in the thermocouple junctions formed from
connecting dissimilar conductors. Cancel these thermally-generated potentials by assuring they are equal on
both input terminals. Other layout and design considerations include:
•
•
•
Use low thermoelectric-coefficient conditions (avoid dissimilar metals).
Thermally isolate components from power supplies or other heat sources.
Shield operational amplifier and input circuitry from air currents, such as cooling fans.
Following these guidelines reduces the likelihood of junctions being at different temperatures, which can cause
thermoelectric voltages of 0.1 μV/°C or higher, depending on materials used.
7.3.1 Operating Voltage
The OPA2333P operational amplifier operates over a power-supply range of 1.8 V to 5.5 V (±0.9 V to ±2.75 V).
Parameters that vary over supply voltage or temperature are shown in the Typical Characteristics section.
CAUTION
Supply voltages higher than +7 V (absolute maximum) can permanently damage the
device.
10
版权 © 2017, Texas Instruments Incorporated
OPA2333P
www.ti.com.cn
ZHCSH14A –NOVEMBER 2017–REVISED DECEMBER 2017
Feature Description (接下页)
7.3.2 Input Voltage
The OPA2333P input common-mode voltage range extends 0.1 V beyond the supply rails. The OPA2333P is
designed to cover the full range without the troublesome transition region found in some other rail-to-rail
amplifiers.
Typically, input bias current is approximately 70 pA; however, input voltages that exceed the power supplies can
cause excessive current to flow into or out of the input pins. Momentary voltages greater than the power supply
can be tolerated if the input current is limited to 10 mA. This limitation is easily accomplished with an input
resistor, as shown in 图 19.
Current-limiting resistor
required if input voltage
exceeds supply rails by
³ 0.5 V.
+5 V
IOVERLOAD
10 mA max
VOUT
VIN
5 kW
图 19. Input Current Protection
7.3.3 Internal Offset Correction
The OPA2333P operational amplifier uses an auto-calibration technique with
a
time-continuous
350-kHz operational amplifier in the signal path. This amplifier is zero-corrected every 8 μs using a proprietary
technique. Upon power up, the amplifier requires approximately 100 μs to achieve specified VOS accuracy. This
design has no aliasing or flicker noise.
7.3.4 Achieving Output Swing to the Op Amp Negative Rail
Some applications require output voltage swings from 0 V to a positive full-scale voltage (such as 2.5 V) with
excellent accuracy. With most single-supply operational amplifiers, problems arise when the output signal
approaches 0 V, near the lower output swing limit of a single-supply operational amplifier. A good, single-supply
operational amplifier may swing close to single-supply ground, but does not reach ground. The output of the
OPA2333P can be made to swing to, or slightly below, ground on a single-supply power source. This swing is
achieved with the use of the use of another resistor and an additional, more negative power supply than the
operational amplifier negative supply. A pulldown resistor can be connected between the output and the
additional negative supply to pull the output down below the value that the output would otherwise achieve, as
shown in 图 20.
V+ = +5 V
VOUT
VIN
RP = 20 kW
Op Amp V- = GND
-5 V
Additional
Negative
Supply
图 20. VOUT Range to Ground
版权 © 2017, Texas Instruments Incorporated
11
OPA2333P
ZHCSH14A –NOVEMBER 2017–REVISED DECEMBER 2017
www.ti.com.cn
Feature Description (接下页)
The OPA2333P has an output stage that allows the output voltage to be pulled to the negative supply rail, or
slightly below, using the technique previously described. This technique only works with some types of output
stages. The OPA2333P is characterized to perform with this technique; the recommended resistor value is
approximately 20 kΩ.
注
This configuration increases the current consumption by several hundreds of microamps.
Accuracy is excellent down to 0 V and as low as –2 mV. Limiting and nonlinearity occur below –2 mV, but
excellent accuracy returns after the output is again driven above –2 mV. Lowering the resistance of the pulldown
resistor allows the operational amplifier to swing even further below the negative rail. Resistances as low as
10 kΩ can be used to achieve excellent accuracy down to –10 mV.
7.3.5 Specified Start-Up Performance
The OPA2333P has a dedicated start-up circuit that ensures a fast, repeatable startup for all supply conditions.
The OPA2333P is specified to have a maximum start-up time that is production-tested as illustrated in the
configuration shown in 图 21. Start-up time is defined as the time from when the power supply reaches the
minimum specified voltage to the time the output has settled to within 20 mV of the nominal value. See 图 22.
10 kꢀ
V+
10 kꢀ
œ
Output
+
V-
图 21. OPA2333P Equivalent Start-Up Test Configuration
Supply
Voltage
3.3 V
Start-up Time
0 V
Voltage
+20 mV
-20 mV
Output
Voltage
Time
图 22. OPA2333P Start-Up Timing
12
版权 © 2017, Texas Instruments Incorporated
OPA2333P
www.ti.com.cn
ZHCSH14A –NOVEMBER 2017–REVISED DECEMBER 2017
Feature Description (接下页)
7.3.6 WSON Package
The OPA2333P is offered in an WSON-8 package (also known as DFN). The WSON is a QFN package with lead
contacts on only two sides of the bottom of the package. This leadless package maximizes board space and
enhances thermal and electrical characteristics through an exposed pad.
WSON packages are physically small, have a smaller routing area, improved thermal performance, and improved
electrical parasitics. Additionally, the absence of external leads eliminates bent-lead issues.
The WSON package can be easily mounted using standard PCB assembly techniques. See application reports
QFN/SON PCB Attachment and Quad Flatpack No-Lead Logic Packages, both available for download at
www.ti.com.
注
The exposed leadframe die pad on the bottom of the package should be connected to V–
or left unconnected.
7.4 Device Functional Modes
The OPA2333P device has a single functional mode. The device is powered on as long as the power supply
voltage is between 1.8 V (±0.9 V) and 5.5 V (±2.75 V).
版权 © 2017, Texas Instruments Incorporated
13
OPA2333P
ZHCSH14A –NOVEMBER 2017–REVISED DECEMBER 2017
www.ti.com.cn
8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The OPA2333P is a unity-gain stable, precision operational amplifier with very low offset voltage drift; these
devices are also free from output phase reversal. Applications with noisy or high-impedance power supplies
require decoupling capacitors close to the device power-supply pins. In most cases, 0.1-μF capacitors are
adequate.
8.2 Typical Application
8.2.1 Bidirectional Current-Sensing
This single-supply, low-side, bidirectional current-sensing solution detects load currents from –1 A to 1 A. The
single-ended output spans from 110 mV to 3.19 V. This design uses the OPA2333P because of its low offset
voltage and rail-to-rail input and output. One of the amplifiers is configured as a difference amplifier and the other
provides the reference voltage.
图 23 shows the solution.
VCC
VCC
VREF
R5
+
U1B
R6
ILOAD
R2
+
R1
+
VBUS
+
œ
VSHUNT
RSHUNT
VOUT
U1A
VCC
œ
R3
RL
R4
Copyright © 2016, Texas Instruments Incorporated
图 23. Bidirectional Current-Sensing Schematic
14
版权 © 2017, Texas Instruments Incorporated
OPA2333P
www.ti.com.cn
ZHCSH14A –NOVEMBER 2017–REVISED DECEMBER 2017
Typical Application (接下页)
8.2.1.1 Design Requirements
This solution has the following requirements:
•
•
•
Supply voltage: 3.3 V
Input: –1 A to 1 A
Output: 1.65 V ±1.54 V (110 mV to 3.19 V)
8.2.1.2 Detailed Design Procedure
The load current, ILOAD, flows through the shunt resistor (RSHUNT) to develop the shunt voltage, VSHUNT. The shunt
voltage is then amplified by the difference amplifier, which consists of U1A and R1 through R4. The gain of the
difference amplifier is set by the ratio of R4 to R3. To minimize errors, set R2 = R4 and R1 = R3. The reference
voltage, VREF, is supplied by buffering a resistor divider using U1B. The transfer function is given by 公式 1.
VOUT = VSHUNT ´ GainDiff_Amp + VREF
where
VSHUNT = ILOAD ´ RSHUNT
•
R4
GainDiff_Amp
=
R3
•
R6
R5 + R6
VREF = VCC
´
•
(1)
There are two types of errors in this design: offset and gain. Gain errors are introduced by the tolerance of the
shunt resistor and the ratios of R4 to R3 and, similarly, R2 to R1. Offset errors are introduced by the voltage
divider (R5 and R6) and how closely the ratio of R4/R3 matches R2/R1. The latter value impacts the CMRR of the
difference amplifier, which ultimately translates to an offset error.
Because this is a low-side measurement, the value of VSHUNT is the ground potential for the system load.
Therefore, it is important to place a maximum value on VSHUNT. In this design, the maximum value for VSHUNT is
set to 100 mV. 公式 2 calculates the maximum value of the shunt resistor given a maximum shunt voltage of 100
mV and maximum load current of 1 A.
VSHUNT(Max)
100 mV
1 A
= 100 mW
RSHUNT(Max)
=
=
ILOAD(Max)
(2)
The tolerance of RSHUNT is directly proportional to cost. For this design, a shunt resistor with a tolerance of 0.5%
was selected. If greater accuracy is required, select a 0.1% resistor or better.
The load current is bidirectional; therefore, the shunt voltage range is –100 mV to 100 mV. This voltage is divided
down by R1 and R2 before reaching the operational amplifier, U1A. Take care to ensure that the voltage present
at the noninverting node of U1A is within the common-mode range of the device. Therefore, it is important to use
an operational amplifier, such as the OPA2333P, that has a common-mode range that extends below the
negative supply voltage. Finally, to minimize offset error, note that the OPA2333P has a typical offset voltage of
±2 µV (±10 µV maximum).
Given a symmetric load current of –1 A to 1 A, the voltage divider resistors (R5 and R6) must be equal. To be
consistent with the shunt resistor, a tolerance of 0.5% was selected. To minimize power consumption,
10-kΩ resistors were used.
To set the gain of the difference amplifier, the common-mode range and output swing of the OPA2333P must be
considered. 公式 3 and 公式 4 depict the typical common-mode range and maximum output swing, respectively,
of the OPA2333P given a 3.3-V supply.
–100 mV < VCM < 3.4 V
100 mV < VOUT < 3.2 V
(3)
(4)
The gain of the difference amplifier can now be calculated as shown in 公式 5.
V
OUT_Max - VOUT_Min
3.2 V - 100 mV
100 mW ´ [1 A - (- 1A)]
V
V
= 15.5
=
GainDiff_Amp
=
R
SHUNT ´ (IMAX - IMIN
)
(5)
15
版权 © 2017, Texas Instruments Incorporated
OPA2333P
ZHCSH14A –NOVEMBER 2017–REVISED DECEMBER 2017
www.ti.com.cn
Typical Application (接下页)
The resistor value selected for R1 and R3 was 1 kΩ. 15.4 kΩ was selected for R2 and R4 because it is the
nearest standard value. Therefore, the ideal gain of the difference amplifier is 15.4 V/V.
The gain error of the circuit primarily depends on R1 through R4. As a result of this dependence, 0.1% resistors
were selected. This configuration reduces the likelihood that the design requires a two-point calibration. A simple
one-point calibration, if desired, removes the offset errors introduced by the 0.5% resistors.
8.2.1.3 Application Curve
3.30
1.65
0
-1.0
-0.5
0
0.5
1.0
Input Current (A)
图 24. Bidirectional Current-Sensing Circuit Performance:
Output Voltage vs Input Current
8.2.2 High-Side Voltage-to-Current (V-I) Converter
The circuit shown in 图 25 is a high-side voltage-to-current (V-I) converter. It translates to an input voltage of 0 V
to 2 V and output current of 0 mA to 100 mA. 图 26 shows the measured transfer function for this circuit. The low
offset voltage and offset drift of the OPA2333P facilitate excellent dc accuracy for the circuit.
V+
RS2
470 ꢀ
VRS2
RS3
4.7 ꢀ
IRS2
IRS3
R4
VRS3
10 kꢀ
C7
2200 pF
R5
A2
Q2
+
330 ꢀ
V+
200 ꢀ
+
Q1
A1
R3
+
VIN
1000 pF
C6
œ
VRS1
VLOAD
10 kꢀ
R2
RS1
2 kꢀ
RLOAD
ILOAD
IRS1
Copyright © 2016, Texas Instruments Incorporated
图 25. High-Side Voltage-to-Current (V-I) Converter
16
版权 © 2017, Texas Instruments Incorporated
OPA2333P
www.ti.com.cn
ZHCSH14A –NOVEMBER 2017–REVISED DECEMBER 2017
Typical Application (接下页)
8.2.2.1 Design Requirements
The design requirements are as follows:
•
•
•
Supply Voltage: 5 V DC
Input: 0 V to 2 V DC
Output: 0 mA to 100 mA DC
8.2.2.2 Detailed Design Procedure
The V-I transfer function of the circuit is based on the relationship between the input voltage, VIN, and the three
current sensing resistors, RS1, RS2, and RS3. The relationship between VIN and RS1 determines the current that
flows through the first stage of the design. The current gain from the first stage to the second stage is based on
the relationship between RS2 and RS3.
For a successful design, pay close attention to the dc characteristics of the operational amplifier chosen for the
application. To meet the performance goals, this application benefits from an operational amplifier with low offset
voltage, low temperature drift, and rail-to-rail output. The OPA2333P CMOS operational amplifier is a high-
precision, 2-uV offset, 0.02-μV/°C drift amplifier optimized for low-voltage, single-supply operation with an output
swing to within 50 mV of the positive rail. The OPA2333P family uses chopping techniques to provide low initial
offset voltage and near-zero drift over time and temperature. Low offset voltage and low drift reduce the offset
error in the system, making these devices appropriate for precise dc control. The rail-to-rail output stage of the
OPA2333P ensures that the output swing of the operational amplifier is able to fully control the gate of the
MOSFET devices within the supply rails.
A detailed error analysis, design procedure, and additional measured results are given in TIPD102.
8.2.2.3 Application Curve
0.1
Load
0.075
0.05
0.025
0
0
0.5
1
Input Voltage (V)
1.5
2
D001
图 26. Measured Transfer Function for High-Side V-I Converter
版权 © 2017, Texas Instruments Incorporated
17
OPA2333P
ZHCSH14A –NOVEMBER 2017–REVISED DECEMBER 2017
www.ti.com.cn
Typical Application (接下页)
8.2.3 Other Applications
Additional application ideas are shown in 图 27 and 图 28.
RG
zener(1)
V+
RSHUNT
(2)
R1
10 kW
MOSFET rated to
stand-off supply voltage
such as BSS84 for
up to 50 V.
+5V
V+
Two zener
biasing methods
are shown.(3)
Output
Load
RBIAS
RL
(1) Zener rated for op amp supply capability (that is, 5.1 V for OPA2333P).
(2) Current-limiting resistor.
(3) Choose zener biasing resistor or dual N-MOSFETs (FDG6301N, NTJD4001N, or Si1034).
图 27. High-Side Current Monitor
V1
-In
INA152
OPA2333
2
5
6
R2
VO
R1
R2
3
1
OPA2333
V2
+In
VO = (1 + 2R2 / R1) (V2 - V1)
图 28. Precision Instrumentation Amplifier
9 Power Supply Recommendations
The OPA2333P is specified for operation from 1.8 V to 5.5 V (±0.9 V to ±2.75 V); many specifications apply from
–40°C to 125°C. The Typical Characteristics presents parameters that can exhibit significant variance with regard
to operating voltage or temperature.
CAUTION
Supply voltages larger than 7 V can permanently damage the device (see Absolute
Maximum Ratings).
18
版权 © 2017, Texas Instruments Incorporated
OPA2333P
www.ti.com.cn
ZHCSH14A –NOVEMBER 2017–REVISED DECEMBER 2017
TI recommends placing 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in
from noisy or high-impedance power supplies. For more detailed information on bypass capacitor placement,
refer to the Layout section.
版权 © 2017, Texas Instruments Incorporated
19
OPA2333P
ZHCSH14A –NOVEMBER 2017–REVISED DECEMBER 2017
www.ti.com.cn
10 Layout
10.1 Layout Guidelines
10.1.1 General Layout Guidelines
Pay attention to good layout practices. Keep traces short and when possible and use a printed-circuit-board
(PCB) ground plane with surface-mount components placed as close to the device pins as possible. Place a 0.1-
μF capacitor closely across the supply pins. Apply these guidelines throughout the analog circuit to improve
performance and provide benefits, such as reducing the electromagnetic interference (EMI) susceptibility.
Operational amplifiers vary in susceptibility to radio frequency interference (RFI). RFI can generally be identified
as a variation in offset voltage or DC signal levels with changes in the interfering RF signal. The OPA2333P is
specifically designed to minimize susceptibility to RFI and demonstrates remarkably low sensitivity compared to
previous generation devices. Strong RF fields may still cause varying offset levels.
10.1.2 WSON (DFN) Layout Guidelines
Solder the exposed leadframe die pad on the WSON package to a thermal pad on the PCB. A mechanical
drawing showing an example layout is attached at the end of this data sheet. Refinements to this layout may be
necessary based on assembly process requirements. Mechanical drawings located at the end of this data sheet
list the physical dimensions for the package and pad. The five holes in the landing pattern are optional, and are
intended for use with thermal vias that connect the leadframe die pad to the heatsink area on the PCB.
Soldering the exposed pad significantly improves board-level reliability during temperature cycling, key push,
package shear, and similar board-level tests. Even with applications that have low-power dissipation, the
exposed pad must be soldered to the PCB to provide structural integrity and long-term reliability.
10.2 Layout Example
Place components close
VOUT A
to device and to each
other to reduce parasitic
errors
VS+
V+
OUT A
œIN A
+IN A
Vœ
Use a low-ESR,
ceramic bypass
capacitor
VOUT B
RF
RG
RF
OUT B
œIN B
+IN B
Run the input traces
as far away from
the supply lines
as possible
VIN A
RG
Place components close
to device and to each
other to reduce parasitic
errors
VSœ
VIN B
Run the input traces
as far away from
the supply lines
as possible
VSœ
Use low-ESR,
ceramic bypass
capacitor
Connect Exposed
Pad to VS-
Copyright © 2017, Texas Instruments Incorporated
图 29. Layout Example
20
版权 © 2017, Texas Instruments Incorporated
OPA2333P
www.ti.com.cn
ZHCSH14A –NOVEMBER 2017–REVISED DECEMBER 2017
11 器件和文档支持
11.1 器件支持
11.1.1 开发支持
关于此产品的开发支持，请参阅以下内容：
•
•
•
•
•
•
•
《高侧电压电流转换器，0V 至 2V，0mA 至 100mA，1% 满量程误差》
《低电平电压电流转换器参考设计，0V 至 5V 输入，0µA 至 5µA 输出》
《ADS8881x 18 位、1MSPS、串行接口、微功耗、微型、真差分输入、SAR 模数转换器》
《针对最低失真和最低噪声进行了优化的 18 位 1MSPS 数据采集参考设计》
《ADS1100 自校准 16 位模数转换器》
《REF31xx 15ppm/°C 最大值、100μA、SOT-23 系列电压基准》
《INA326、INA327 精密低漂移 CMOS 仪表放大器》
11.2 文档支持
11.2.1 相关文档
请参阅如下相关文档：
•
•
《QFN/SON PCB 连接》
零温漂放大器： 特性 和优势
11.3 接收文档更新通知
如需接收文档更新通知，请导航至 TI.com 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.5 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知和修
订此文档。如欲获取此数据表的浏览器版本，请参阅左侧的导航。
版权 © 2017, Texas Instruments Incorporated
21
PACKAGE OPTION ADDENDUM
www.ti.com
8-Apr-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA2333PIDSGR
OPA2333PIDSGT
ACTIVE
ACTIVE
WSON
WSON
DSG
DSG
8
8
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
-40 to 125
-40 to 125
1GFY
1GFY
Samples
Samples
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
8-Apr-2023
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA2333PIDSGR
OPA2333PIDSGT
WSON
WSON
DSG
DSG
8
8
3000
250
180.0
180.0
8.4
8.4
2.3
2.3
2.3
2.3
1.15
1.15
4.0
4.0
8.0
8.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA2333PIDSGR
OPA2333PIDSGT
WSON
WSON
DSG
DSG
8
8
3000
250
210.0
210.0
185.0
185.0
35.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DSG 8
2 x 2, 0.5 mm pitch
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224783/A
www.ti.com
PACKAGE OUTLINE
DSG0008A
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
B
A
0.32
0.18
PIN 1 INDEX AREA
2.1
1.9
0.4
0.2
ALTERNATIVE TERMINAL SHAPE
TYPICAL
0.8
0.7
C
SEATING PLANE
0.05
0.00
SIDE WALL
0.08 C
METAL THICKNESS
DIM A
OPTION 1
0.1
OPTION 2
0.2
EXPOSED
THERMAL PAD
(DIM A) TYP
0.9 0.1
5
4
6X 0.5
2X
1.5
9
1.6 0.1
8
1
0.32
0.18
PIN 1 ID
(45 X 0.25)
8X
0.4
0.2
8X
0.1
C A B
C
0.05
4218900/E 08/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.9)
(
0.2) VIA
8X (0.5)
TYP
1
8
8X (0.25)
(0.55)
SYMM
9
(1.6)
6X (0.5)
5
4
SYMM
(1.9)
(R0.05) TYP
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218900/E 08/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
8X (0.5)
METAL
8
SYMM
1
8X (0.25)
(0.45)
SYMM
9
(0.7)
6X (0.5)
5
4
(R0.05) TYP
(0.9)
(1.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 9:
87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4218900/E 08/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
相关型号：
©2020 ICPDF网 联系我们和版权申明