OPA2376-Q1 [TI]
低噪声、低静态电流精密运算放大器电子微调/交换;
| 型号： | OPA2376-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 低噪声、低静态电流精密运算放大器电子微调/交换 电子 放大器 运算放大器 |
| 文件： | 总38页 (文件大小：1877K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OPA376-Q1, OPA2376-Q1, OPA4376-Q1
ZHCS042C –APRIL 2011 –REVISED MARCH 2021
OPAx376-Q1 低噪声、低静态电流、
精密e-trim™ 运算放大器
1 特性
3 说明
• 符合面向汽车应用的AEC-Q100 标准：
– 温度等级1：–40°C 至+125°C，TA
• 功能安全型
OPAx376-Q1 系列代表了新一代低噪声e-trim™ 运算放
大器，可提供出色的直流精度和交流性能。该器件具有
轨到轨输出、低失调电压（最大值为 25μV）、低噪
声 (7.5nV/√Hz)、950μA 的静态电流（最大值）和
5.5MHz 带宽，对于各类精密和便携式应用极具吸引
力。此外，OPA376-Q1 拥有较宽的电源电压范围和出
色的 PSRR，因此非常适合直接由电池供电而无需调
节的应用。
– 可提供用于功能安全系统设计的文档（OPA376-
Q1 和OPA2376-Q1）
• 低噪声：1kHz 时为7.5nV/√Hz
• 0.1Hz 至10Hz 噪声：0.8μVPP
• 静态电流：760μA（典型值）
• 低失调电压：5μV（典型值）
• 增益带宽积：5.5MHz
OPA376-Q1（单通道版本）采用MicroSIZE SC70-5、
SOT23-5 和 SOIC-8 封装。OPA2376-Q1（双通道）
采用 SOIC-8 和 VSSOP-8 封装。OPA4376-Q1（四通
道）采用 TSSOP-14 封装。所有器件版本的额定工作
温度范围均为-40°C 至+125°C。
• 轨到轨输入和输出
• 单电源供电
• 电源电压：2.2V 至5.5V
• 节省空间的封装：
器件信息
封装(1)
– SC70、SOT-23、VSSOP、TSSOP
封装尺寸（标称值）
2.00mm × 1.25mm
2.90mm × 1.60mm
4.90mm × 3.91mm
4.90mm × 3.91mm
3.00mm × 3.00mm
5.00mm × 4.40mm
器件型号
2 应用
SC70 (5)
OPA376-Q1
SOT-23 (5)
SOIC (8)
• 车载充电器(OBC) 和无线充电器
• 逆变器和电机控制
• 直流/直流转换器
SOIC (8)
OPA2376-Q1
OPA4376-Q1
• 电池管理系统(BMS)
VSSOP (8)
TSSOP (14)
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
100
10
1
1
10
100
1k
10k
100k
Frequency (Hz)
Offset Voltage (mV)
输入电压噪声频谱密度
失调电压生产分配
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOS549
OPA376-Q1, OPA2376-Q1, OPA4376-Q1
ZHCS042C –APRIL 2011 –REVISED MARCH 2021
www.ti.com.cn
Table of Contents
7.4 Device Functional Modes..........................................15
8 Application and Implementation..................................16
8.1 Application Information............................................. 16
8.2 Typical Application.................................................... 19
9 Power Supply Recommendations................................20
10 Layout...........................................................................21
10.1 Layout Guidelines................................................... 21
10.2 Layout Example...................................................... 21
11 Device and Documentation Support..........................22
11.1 Device Support........................................................22
11.2 Documentation Support.......................................... 22
11.3 接收文档更新通知................................................... 22
11.4 支持资源..................................................................22
11.5 Trademarks............................................................. 23
11.6 静电放电警告...........................................................23
11.7 术语表..................................................................... 23
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 6
6.1 Absolute Maximum Ratings........................................ 6
6.2 ESD Ratings............................................................... 6
6.3 Recommended Operating Conditions.........................6
6.4 Thermal Information: OPA376-Q1.............................. 7
6.5 Thermal Information: OPA2376-Q1............................ 7
6.6 Thermal Information: OPA4376-Q1............................ 7
6.7 Electrical Characteristics.............................................8
6.8 Typical Characteristics................................................9
7 Detailed Description......................................................13
7.1 Overview...................................................................13
7.2 Functional Block Diagram.........................................13
7.3 Feature Description...................................................13
Information.................................................................... 23
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision B (May 2016) to Revision C (March 2021)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• 删除了特性中的HBM 和CDM 分级等级，并将其移至ESD 等级.................................................................... 1
• 向特性添加了功能安全链接................................................................................................................................1
• 更改了应用要点..................................................................................................................................................1
• Changed ESD Ratings to show HBM and CDM classification levels................................................................. 6
• Added Figure 6-8, Common-Mode Voltage vs Temperature ............................................................................. 9
• Added Figure 6-9, Offset Voltage vs Common-Mode Voltage ...........................................................................9
Changes from Revision A (January 2016) to Revision B (May 2016)
Page
• 更新了应用示例..................................................................................................................................................1
• Updated the Pin Functions Table for OPA4376-Q1............................................................................................ 3
• Updated HBM ESD Rating ................................................................................................................................ 6
• Changed units on Channel Separation ..............................................................................................................8
• Deleted the temperature range parameters from the Electrical Characteristics table........................................ 8
• Removed section regarding WCSP photosensitivity ....................................................................................... 21
Changes from Revision * (April 2011) to Revision A (January 2016)
Page
• 添加了引脚功能表、ESD 等级表、建议运行条件表、热性能信息表、特性说明部分、器件功能模式、应用
和实施部分、电源相关建议部分、布局部分、器件和文档支持部分以及机械、封装和可订购信息部分........ 1
• 已将OPA2376-Q1 器件发布为量产数据............................................................................................................1
• Added the Input Offset Voltage and Input Offset Voltage Drift section to the Feature Description ..................13
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5 Pin Configuration and Functions
OUT
V-
1
2
3
5
4
V+
+IN
V-
1
2
3
5
4
V+
+IN
-IN
-IN
OUT
图5-1. OPA376-Q1: DBV (5-Pin SOT-23) Package, 图5-2. OPA376-Q1: DCK (5-Pin SC70) Package, Top
Top View
View
NC(1)
-IN
+IN
V-
1
2
3
4
8
7
6
5
NC(1)
V+
-
+
OUT
NC(1)
(1) NC denotes no internal connection.
图5-3. OPA376-Q1: D (8-Pin SOIC) Package, Top View
表5-1. Pin Functions: OPA376-Q1
PIN
NO.
I/O
DESCRIPTION
NAME
+IN
SOT-23
SC70
SOIC
3
4
1
3
3
I
I
Noninverting input+
2
Inverting input–
–IN
NC
1, 5, 8
No internal connection
Output
—
1
—
4
—
OUT
V+
6
7
4
O
5
5
Positive (highest) power supply+
Negative (lowest) power supply–
—
—
2
2
V–
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OUT A
-IN A
+IN A
V-
1
2
3
4
8
7
6
5
V+
OUT B
-IN B
+IN B
图5-4. OPA2376-Q1: D (8-Pin SOIC) and DGK (8-Pin VSSOP) Packages, Top View
表5-2. Pin Functions: OPA2376-Q1
PIN
I/O
DESCRIPTION
NAME
+IN A
NO.
3
I
I
Noninverting input, channel A+
Inverting input, channel A–
Noninverting input, channel B+
Inverting input, channel B–
Output, channel A
2
–IN A
+IN B
–IN B
OUT A
OUT B
V–
5
I
6
I
1
O
O
7
Output, channel B
4
Negative (lowest) power supply
Positive (highest) power supply
—
—
V+
8
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OUT A
-IN A
+IN A
V+
1
2
3
4
5
6
7
14 OUT D
13 -IN D
12 +IN D
11 V-
+IN B
-IN B
OUT B
10 +IN C
9
8
-IN C
OUT C
图5-5. OPA4376-Q1: PW (14-Pin TSSOP) Package, Top View
表5-3. Pin Functions: OPA4376-Q1
PIN
I/O
DESCRIPTION
NAME
+IN A
NO.
3
I
I
Noninverting input, channel A+
Inverting input, channel A–
Noninverting input, channel B+
Inverting input, channel B–
Noninverting input, channel C+
Inverting input, channel C–
Noninverting input, channel D+
Inverting input, channel D–
Output, channel A
2
–IN A
+IN B
–IN B
+IN C
–IN C
+IN D
–IN D
OUT A
OUT B
OUT C
OUT D
V+
5
I
6
I
10
9
I
I
12
13
1
I
I
O
O
O
O
—
—
7
Output, channel B
8
Output, channel C
14
4
Output, channel D
Positive (highest) power supply
Negative (lowest) power supply
11
V–
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
V
Supply voltage
7
(V+) + 0.5
10
VS = (V+) –(V–)
Signal input pin voltage(2)
Signal input pin current(2)
Output short-circuit current(3)
Operating temperature
Junction temperature
Storage temperature
V
(V–) –0.5
–10
mA
Continuous
TA
125
150
150
°C
°C
°C
–40
TJ
Tstg
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails must
be current limited to 10 mA or less.
(3) Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per AEC Q100-002(1)
HBM ESD classification level 3A
±4000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per AEC Q100-011
CDM ESD classification level C6
±1000
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.2 (±1.1)
–40
MAX
5.5 (±2.75)
150
UNIT
V
Supply voltage
VS = (V+) –(V–)
TA
Operating temperature
°C
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6.4 Thermal Information: OPA376-Q1
OPA376-Q1
THERMAL METRIC(1)
DCK (SC70) DBV (SOT-23)
D (SOIC)
8 PINS
100.1
42.4
UNIT
5 PINS
267
5 PINS
273.8
126.8
85.9
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
80.9
54.8
1.2
41
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
10.9
4.8
ψJT
54.1
n/a
84.9
40.3
ψJB
RθJC(bot)
n/a
n/a
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Thermal Information: OPA2376-Q1
OPA2376-Q1
THERMAL METRIC(1)
D (SOIC)
8 PINS
111.1
54.7
DGK (VSSOP)
8 PINS
171.2
63.9
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
51.7
92.8
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
10.5
9.2
ψJT
51.2
91.2
ψJB
RθJC(bot)
n/a
n/a
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.6 Thermal Information: OPA4376-Q1
OPA4376-Q1
THERMAL METRIC(1)
PW (TSSOP)
14 PINS
107.8
29.6
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
52.6
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.5
ψJT
51.6
ψJB
RθJC(bot)
n/a
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.7 Electrical Characteristics
at TA = 25°C, RL = 10 kΩconnected to VS / 2, VCM = VS / 2, and VO UT = VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
5
0.26
0.32
5
25
1
μV
TA = –40°C to +85°C
μV/°C
μV/°C
μV/V
μV/V
Input offset voltage versus
temperature
dVOS/dT
2
TA = –40°C to +125°C
TA = 25°C
20
VS = 2.2 V to 5.5 V,
VCM < (V+) –1.3 V
Input offset voltage versus
power supply
PSRR
5
TA = –40°C to +125°C
Channel separation, dc (dual,
quad)
0.5
µV/V
INPUT BIAS CURRENT
TA = 25°C
0.2
See 节6.8
0.2
10
10
pA
pA
pA
IB
Input bias current
Input offset current
TA = –40°C to +125°C
IOS
NOISE
Input voltage noise
f = 0.1 Hz to 10 Hz
f = 1 kHz
0.8
7.5
2
μVPP
en
in
Input voltage noise density
Input current noise
nV/√Hz
fA/√Hz
f = 1 kHz
INPUT VOLTAGE
(V–) –
VCM
Common-mode voltage
Common-mode rejection ratio
(V+) + 0.1
V
See 图6-8
0.1
CMRR
76
90
dB
(V–) < VCM < (V+) –1.3 V
INPUT CAPACITANCE
Differential
6.5
13
pF
pF
Common-mode
OPEN-LOOP GAIN
120
120
134
126
dB
dB
50 mV < VO < (V+) –50 mV, RL = 10 kΩ
100 mV < VO < (V+) –100 mV, RL = 2 kΩ
AOL
Open-loop voltage gain
FREQUENCY RESPONSE
GBW
SR
Gain-bandwidth product
CL = 100 pF, VS = 5.5 V
5.5
MHz
V/μs
μs
Slew rate
G = 1, CL = 100 pF, VS = 5.5 V
2
1.6
0.1%, 2-V Step , G = 1, CL = 100 pF, VS = 5.5 V
0.01%, 2-V Step , G = 1, CL = 100 pF, VS = 5.5 V
VIN × Gain > VS
tS
Settling time
2
μs
Overload recovery time
THD + noise
0.33
μs
THD+N
0.00027%
VO = 1 VRMS, G = 1, f = 1 kHz, RL = 10 kΩ
OUTPUT
TA = 25°C
10
40
20
40
50
80
mV
mV
mV
mV
mA
RL = 10 kΩ
TA = –40°C to +125°C
Voltage output swing from rail
TA = 25°C
RL = 2 kΩ
TA = –40°C to +125°C
ISC
Short-circuit current
30 / –50
See 节6.8
150
CLOAD
RO
Capacitive load drive
Open-loop output impedance
Ω
POWER SUPPLY
VS Specified voltage
2.2
5.5
V
V
Operating voltage
2 to 5.5
760
TA = 25°C
950
1
μA
mA
IO = 0, VS = 5.5 V, VCM < (V+) –1.3
V
IQ
Quiescent current per amplifier
TA = –40°C to +125°C
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6.8 Typical Characteristics
at TA = 25°C, VS = 5 V, RL = 10 kΩconnected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
120
100
80
60
40
20
0
160
140
120
100
80
0
V(+) Power-Supply Rejection Ratio
-20
-40
Gain
-60
Phase
Common-Mode
Rejection Ratio
-80
60
-100
-120
-140
-160
-180
40
V(-) Power-Supply Rejection Ratio
20
0
-20
0.1
1
10
100
1k
10k
100k 1M
10M
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
图6-2. Power-Supply and Common-Mode Rejection Ratio vs
图6-1. Open-Loop Gain and Phase vs Frequency
Frequency
160
Open-Loop Gain (RL = 2kW)
140
120
Power-Supply Rejection Ratio
(VS = 2.1V to 5.5V)
100
80
-50
-25
0
25
50
75
100
125
150
Temperature (°C)
1s/div
图6-4. 0.1-Hz to 10-Hz Input Voltage Noise
图6-3. Open-Loop Gain and Power-Supply Rejection Ratio vs
Temperature
100
10
1
1
VS = 5V, VCM = 2V, VOUT = 1VRMS
0.1
0.01
Gain = 10V/V
0.001
Gain = 1V/V
0.0001
1
10
100
1k
10k
100k
10
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
图6-5. Input Voltage Noise Spectral Density
图6-6. Total Harmonic Distortion + Noise vs Frequency
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = 5 V, RL = 10 kΩconnected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
110
100
90
80
70
60
50
-50
-25
0
25
50
75
100
125
150
Temperature (°C)
VCM range for typical CMRR = 90 dB
图6-8. Common-Mode Voltage vs Temperature
图6-7. Common-Mode Rejection Ratio vs Temperature
1000
900
800
700
600
500
-50
-25
0
25
50
75
100
125
150
Temperature (°C)
TA = 125°C
图6-9. Offset Voltage vs Common-Mode Voltage
(V–) = 0 V
图6-10. Quiescent Current vs Temperature
75
50
1000
900
800
700
600
500
50
VS = ±2.75V
40
30
20
10
0
ISC+
ISC+
25
0
IQ
-25
-50
-75
-100
ISC-
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
-50
-25
0
25
50
75
100
125
150
Supply Voltage (V)
Temperature (°C)
图6-12. Short-Circuit Current vs Temperature
图6-11. Quiescent and Short-Circuit Current vs Supply Voltage
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = 5 V, RL = 10 kΩconnected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
3
2
1000
900
800
700
600
500
400
300
200
100
0
VS = ±2.75
1
+150°C
+125°C
+25°C
-40°C
0
-1
-2
-3
-50
-25
0
25
50
75
100
125
150
0
10
20
30
40
50
60
70
80
Output Current (mA)
Temperature (°C)
图6-14. Output Voltage vs Output Current
图6-13. Input Bias Current vs Temperature
½Offset Voltage Drift½ (mV/°C)
Offset Voltage (mV)
图6-16. Offset Voltage Drift Production Distribution
(–40°C to +125°C)
图6-15. Offset Voltage Production Distribution
6
50
VS = 5.5V
VS = 5V
G = +1V/V
5
4
3
2
1
0
40
30
20
10
0
VS = 2.5V
1k
10k
100k
1M
10M
10
100
1k
Frequency (Hz)
Load Capacitance (pF)
图6-17. Maximum Output Voltage vs Frequency
图6-18. Small-Signal Overshoot vs Load Capacitance
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = 5 V, RL = 10 kΩconnected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
G = +1
RL = 10kW
G = +1
RL = 2kW
CL = 50pF
CL = 50pF
Time (400ns/div)
Time (2ms/div)
图6-19. Small-Signal Pulse Response
图6-20. Large-Signal Pulse Response
140
120
100
80
100
10
1
0.01%
60
40
0.1%
20
0
0.1
10
100
1k
10k
100k
1M
10M
100M
1
10
100
Frequency (Hz)
Closed-Loop Gain (V/V)
图6-22. Channel Separation vs Frequency
图6-21. Settling Time vs Closed-Loop Gain
1k
100
10
1
400mA Load
2mA Load
0.1
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
图6-23. Open-Loop Output Resistance vs Frequency
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7 Detailed Description
7.1 Overview
The OPAx376-Q1 family belongs to a new generation of low-noise e-trim operational amplifiers, giving
customers outstanding dc precision and ac performance. Low noise, rail-to-rail input and output, low offset, and
drawing a low quiescent current, make these devices an excellent choice for a variety of precision and portable
applications. In addition, these devices have a wide supply range with excellent PSRR, making the OPAx376-Q1
a great option for applications that are battery powered without regulation.
7.2 Functional Block Diagram
V+
OPAx376
-IN
OUT
+IN
ꢀ
POR
e-trim
V-
7.3 Feature Description
The OPAx376-Q1 family of precision amplifiers offers excellent dc performance as well as excellent ac
performance. Operating from a single power-supply the OPAx376-Q1 is capable of driving large capacitive
loads, has a wide input common-mode voltage range, and is well-suited to drive the inputs of successive-
approximation response (SAR) analog-to-digital converters (ADCs) as well as 24-bit and higher resolution
converters. Including internal ESD protection, the OPAx376-Q1 family is offered in a variety of industry-standard
packages, including a wafer chip-scale package for applications that require space savings.
7.3.1 Operating Voltage
The OPAx376-Q1 family of amplifiers operate over a power-supply range of 2.2 V to 5.5 V (±1.1 V to ±2.75 V).
Many of the specifications apply from –40°C to +125°C. Parameters that can exhibit significant variance with
regard to operating voltage or temperature are presented in 节6.8.
7.3.2 Input Offset Voltage and Input Offset Voltage Drift
The OPAx376-Q1 family of e-trim operational amplifiers is manufactured using TI's proprietary trim technology, a
method of trimming internal device parameters during either wafer probing or final testing. Each amplifier is
trimmed in production, thereby minimizing errors associated with input offset voltage and input offset voltage
drift.
7.3.3 Capacitive Load and Stability
The OPAx376-Q1 series of amplifiers may be used in applications where driving a capacitive load is required. As
with all op amps, there may be specific instances where the OPAx376-Q1 can become unstable, leading to
oscillation. The particular op amp circuit configuration, layout, gain, and output loading are some of the factors to
consider when establishing whether an amplifier is be stable in operation. An op amp in the unity-gain (1 V/V)
buffer configuration and driving a capacitive load exhibits a greater tendency to be unstable than an amplifier
operated at a higher noise gain. The capacitive load, in conjunction with the op amp output resistance, creates a
pole within the feedback loop that degrades the phase margin. The degradation of the phase margin increases
as the capacitive loading increases.
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The OPAx376 in a unity-gain configuration can directly drive up to 250 pF of pure capacitive load. Increasing the
gain enhances the ability of the amplifier to drive greater capacitive loads; see the typical characteristic plot 图
6-18, Small-Signal Overshoot vs Load Capacitance. In unity-gain configurations, capacitive load drive can be
improved by inserting a small (10-Ω to 20-Ω) resistor, RS, in series with the output, as shown in 图 7-1. This
resistor significantly reduces ringing while maintaining dc performance for purely capacitive loads. However, if
there is a resistive load in parallel with the capacitive load, a voltage divider is created, introducing a gain error at
the output and slightly reducing the output swing. The error introduced is proportional to the ratio RS / RL, and is
generally negligible at low output current levels.
V+
RS
VOUT
OPA376
10W to
20W
VIN
CL
RL
图7-1. Improving Capacitive Load Drive
7.3.4 Common-Mode Voltage Range
The input common-mode voltage range of the OPAx376-Q1 series extends 100 mV beyond the supply rails. The
offset voltage of the amplifier is very low, from approximately (V–) to (V+) – 1 V, as shown in 图 7-2. The offset
voltage increases as common-mode voltage exceeds (V+) –1 V. Common-mode rejection is specified from
(V–) to (V+) –1.3 V.
3
2
1
0
-1
-2
-V
+V
-3
-0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Input Common-Mode Voltage (V)
图7-2. Offset and Common-Mode Voltage
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7.3.5 Input and ESD Protection
The OPAx376-Q1 family incorporates internal electrostatic discharge (ESD) protection circuits on all pins. In the
case of input and output pins, this protection primarily consists of current steering diodes connected between the
input and power-supply pins. These ESD protection diodes also provide in-circuit, input overdrive protection, as
long as the current is limited to 10 mA as stated in 节6.1.
图 7-3 shows how a series input resistor may be added to the driven input to limit the input current. The added
resistor contributes thermal noise at the amplifier input and its value must be kept to a minimum in noise-
sensitive applications.
V+
IOVERLOAD
10mA max
VOUT
OPA376
VIN
5kW
图7-3. Input Current Protection
7.4 Device Functional Modes
The OPAx376-Q1 has a single functional mode and is operational when the power-supply voltage is greater than
2.2 V (±1.1 V). The maximum power supply voltage for the OPAx376-Q1 is 5.5 V (±2.75 V).
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The OPAx376-Q1 family of e-trim operational amplifiers is built using a proprietary technique in which offset
voltage is adjusted during the final steps of manufacturing. This technique compensates for performance shifts
that can occur during the molding process. Through e-trim operational amplifier technology, the OPAx376-Q1
family delivers excellent offset voltage (5 μV, typical). Additionally, the amplifier boasts a fast slew rate, low drift,
low noise, and excellent PSRR and AOL. These 5.5-MHz CMOS op amps operate on 760 μA (typical) quiescent
current.
8.1.1 Basic Amplifier Configurations
The OPAx376-Q1 family is unity-gain stable. It does not exhibit output phase inversion when the input is
overdriven. A typical single-supply connection is shown in 图 8-1. The OPA376-Q1 is configured as a basic
inverting amplifier with a gain of –10 V/V. This single-supply connection has an output centered on the
common-mode voltage, VCM. For the circuit shown in 图 8-1, this voltage is 2.5 V, but may be any value within
the common-mode input voltage range.
R2
10kW
+5V
C1
100nF
R1
1kW
VOUT
OPA376
VIN
VCM = 2.5V
图8-1. Basic Single-Supply Connection
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8.1.2 Active Filtering
The OPA376-Q1 series is well-suited for filter applications requiring a wide bandwidth, fast slew rate, low-noise,
single-supply operational amplifier. 图 8-2 shows a 50-kHz, second-order, low-pass filter. The components have
been selected to provide a maximally-flat Butterworth response. Beyond the cutoff frequency, roll-off is –40 dB/
dec. The Butterworth response is ideal for applications requiring predictable gain characteristics such as the anti-
aliasing filter used ahead of an ADC.
R3
5.49kW
C2
150pF
V+
R1
R2
5.49kW
12.4kW
OPA376
VOUT
C1
1nF
VIN
(V+)/2
图8-2. Second-Order Butterworth, 50-kHz Low-Pass Filter
8.1.3 Driving an Analog-to-Digital Converter
The low noise and wide gain bandwidth of the OPA376-Q1 family make it an ideal driver for ADCs. 图 8-3
illustrates the OPA376-Q1 driving an ADS8327, 16-bit, 250-kSPS converter. The amplifier is connected as a
unity-gain, noninverting buffer.
+5V
C1
0.1mF
+5V
(1)
R1
100W
+IN
ADS8327
Low Power
16-Bit
OPA376
(1)
C3
-IN
1.2nF
500kSPS
VIN
REF IN
+5V
REF5040
4.096V
C4
100nF
(1) Suggested value; may require adjustment based on specific application.
图8-3. Driving an ADS8327
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8.1.4 Phantom-Powered Microphone
The circuit shown in 图8-4 depicts how a remote microphone amplifier can be powered by a phantom source on
the output side of the signal cable. The cable serves double duty, carrying both the differential output signal from
and dc power to the microphone amplifier stage.
An OPA2376-Q1 serves as a single-ended input to a differential output amplifier with a 6-dB gain. Common-
mode bias for the two op amps is provided by the dc voltage developed across the electret microphone element.
A 48-V phantom supply is reduced to 5.1 V by the series 6.8-kΩ resistors on the output side of the cable, and the
4.7-kΩ resistors and zener diode on the input side of the cable. AC coupling blocks the different dc voltage levels
from each other on each end of the cable.
An INA163 instrumentation amplifier provides differential inputs and receives the balanced audio signals from
the cable.
The INA163 gain may be set from 0 dB to 80 dB by selecting the RG value. The INA163 circuit is typical of the
input circuitry used in mixing consoles.
Phantom Power
(Provides power source for microphone)
48V
Microphone
100W
1mF
+
33mF
D1
5.1V
R1
2.7kW
R8
R9
C2
R6
4.7kW
4.7kW
R10
R11
33mF
+
100W
+15V
1/2
6.8kW
6.8kW
OPA2376
10mF
2
3
2
3
1kW
1kW
RG
INA163
10mF
Panasonic
WM-034CY
1
1
C3
R7
3.3kW
3.3kW
10kW
33mF
+
100W
1/2
Low-level differential audio signal
is transmitted differentially on the
same cable as power to the microphone.
OPA2376
-15V
+
10mF
Typical microphone input circuit used in mixing consoles.
图8-4. Phantom-Powered Electret Microphone
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8.1.5 Speech Bandpass-Filtered Data Acquisition System
图8-5 illustrates the OPA2376-Q1 driving a speech bandpass-filtered data acquisition system.
V+ = +2.7V to 5V
Passband 300Hz to 3kHz
R9
510kW
R1
R4
R2
1.5kW
20kW
1MW
C3
C1
33pF
1000pF
R7
R8
V+
8
1
VREF
51kW
150kW
1/2
7
6
DCLOCK
DOUT
OPA2376
+IN
2
1/2
R3
ADS7822
Electret
Serial
Microphone(1)
OPA2376
1MW
R6
12-Bit A/D
Interface
1000pF
C2
5
CS/SHDN
-IN
100kW
3
4
G = 100
R5
20kW
GND
(1) Electret microphone powered by R1.
图8-5. OPA2376-Q1 as a Speech Bandpass-Filtered Data Acquisition System
8.2 Typical Application
Low-pass filters are commonly employed in signal processing applications to reduce noise and prevent aliasing.
The OPA376-Q1 is ideally suited to construct high-speed, high-precision active filters. 图 8-6 shows a second-
order, low-pass filter commonly encountered in signal processing applications.
R4
2.94 kꢀ
C5
1 nF
œ
R1
590 ꢀ
R3
499 ꢀ
Output
+
Input
OPA376
C2
39 nF
图8-6. Typical Application Schematic
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8.2.1 Design Requirements
Use the following parameters for this design example:
• Gain = 5 V/V (inverting gain)
• Low-pass cutoff frequency = 25 kHz
• Second-order Chebyshev filter response with 3-dB gain peaking in the passband
8.2.2 Detailed Design Procedure
The infinite-gain multiple-feedback circuit for a low-pass network function is shown in 图 8-6. Use 方程式 1 to
calculate the voltage transfer function.
-1 R1R3C2C5
Output
Input
s =
( )
s2 + s C 1 R +1 R +1 R +1 R R C C
2
1
3
4
3 4 2 5
(1)
This circuit produces a signal inversion. For this circuit, the gain at dc and the low-pass cutoff frequency are
calculated by 方程式2:
R4
Gain =
R1
1
fC
=
1 R R C C
(
3 4 2 5
)
2p
(2)
Software tools are readily available to simplify filter design. WEBENCH® Filter Designer is a simple, powerful,
and easy-to-use active filter design program. The WEBENCH Filter Designer lets you create optimized filter
designs using a selection of TI operational amplifiers and passive components from TI's vendor partners.
Available as a web-based tool from the WEBENCH® Design Center, WEBENCH® Filter Designer allows you to
design, optimize, and simulate complete multi-stage active filter solutions within minutes.
8.2.3 Application Curve
20
0
-20
-40
-60
100
1k
10k
Frequency (Hz)
100k
1M
图8-7. Low-Pass Filter Transfer Function
9 Power Supply Recommendations
The OPAx376-Q1 family of devices is specified for operation from 2.2 V to 5.5 V (±1.1 V to ±2.75 V); many
specifications apply from –40°C to +125°C. Parameters that can exhibit significant variance with regard to
operating voltage or temperature are presented in 节6.8.
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10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp itself.
Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to
the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds paying attention to the flow of the ground current. For more detailed information refer to
the Circuit Board Layout Techniques application report.
• In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as
opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. As shown in 图10-1, keeping RF and RG
close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
• Cleaning the PCB following board assembly is recommended for best performance.
• Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic
package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to
remove moisture introduced into the device packaging during the cleaning process. A low-temperature, post-
cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
10.2 Layout Example
VIN
+
VOUT
RG
RF
(Schematic Representation)
Place components
close to device and to
each other to reduce
parasitic errors
Run the input
traces as far away
from the supply
lines as possible
VS+
RF
N/C
N/C
V+
RG
GND
GND
œIN
+IN
Vœ
OUTPUT
N/C
VIN
Use low-ESR, ceramic
bypass capacitor
GND
Use low-ESR,
ceramic bypass
capacitor
VOUT
VSœ
Ground (GND) plane on another layer
图10-1. Layout Example
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 TINA-TI™ Simulation Software (Free Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI™
simulation software is a free, fully-functional version of the TINA software, preloaded with a library of macro
models in addition to a range of both passive and active models. TINA-TI simulation software provides all the
conventional dc, transient, and frequency domain analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI simulation software offers extensive
post-processing capability that allows users to format results in a variety of ways. Virtual instruments offer the
ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-
start tool.
备注
These files require that either the TINA software (from DesignSoft™) or TINA-TI software be installed.
Download the free TINA-TI software from the TINA-TI folder.
11.1.1.2 TI Precision Designs
TI Precision Designs are analog solutions created by TI’s precision analog applications experts and offer the
theory of operation, component selection, simulation, complete PCB schematic and layout, bill of materials, and
measured performance of many useful circuits. TI Precision Designs are available online at http://
www.ti.com/ww/en/analog/precision-designs/.
11.1.1.3 WEBENCH® Filter Designer
WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The
WEBENCH® Filter Designer lets you create optimized filter designs using a selection of TI operational amplifiers
and passive components from TI's vendor partners.
Available as a web-based tool from the WEBENCH® Design Center, WEBENCH® Filter Designer allows you to
design, optimize, and simulate complete multistage active filter solutions within minutes.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, INA163 Low-Noise, Low-Distortion Instrumentation Amplifier data sheet
• Texas Instruments, Operational Amplifier Gain stability, Part 3: AC Gain-Error Analysis
• Texas Instruments, Operational Amplifier Gain Stability, Part 2: DC Gain-Error Analysis
• Texas Instruments, Op Amp Performance Analysis
• Texas Instruments, Shelf-Life Evaluation of Lead-Free Component Finishes
• Texas Instruments, Single-Supply Operation of Operational Amplifiers
• Texas Instruments, Tuning in Amplifiers
• Texas Instruments, Using Infinite-Gain, MFB Filter Topology in Fully Differential Active Filters
11.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
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链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.5 Trademarks
e-trim™, TINA-TI™, and TI E2E™ are trademarks of Texas Instruments.
TINA™ and DesignSoft™ are trademarks of DesignSoft, Inc.
WEBENCH® is a registered trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.6 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
11.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2023 Texas Instruments Incorporated
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Product Folder Links: OPA376-Q1 OPA2376-Q1 OPA4376-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA2376AQDRQ1
OPA2376QDGKRQ1
OPA376AQDBVRQ1
OPA4376AQPWRQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
D
8
8
2500 RoHS & Green
2500 RoHS & Green
3000 RoHS & Green
2000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
2376Q1
VSSOP
SOT-23
TSSOP
DGK
DBV
PW
NIPDAUAG
NIPDAU
2376
5
OUHQ
4376Q1
14
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA2376AQDRQ1
OPA2376QDGKRQ1
OPA376AQDBVRQ1
OPA4376AQPWRQ1
SOIC
D
8
8
2500
2500
3000
2000
330.0
330.0
179.0
330.0
12.4
12.4
8.4
6.4
5.3
3.2
6.9
5.2
3.4
3.2
5.6
2.1
1.4
1.4
1.6
8.0
8.0
4.0
8.0
12.0
12.0
8.0
Q1
Q1
Q3
Q1
VSSOP
SOT-23
TSSOP
DGK
DBV
PW
5
14
12.4
12.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA2376AQDRQ1
OPA2376QDGKRQ1
OPA376AQDBVRQ1
OPA4376AQPWRQ1
SOIC
D
8
8
2500
2500
3000
2000
356.0
366.0
213.0
356.0
356.0
364.0
191.0
356.0
35.0
50.0
35.0
35.0
VSSOP
SOT-23
TSSOP
DGK
DBV
PW
5
14
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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