OPA2377-Q1 [TI]
通过汽车级认证的轨到轨输入/输出、低噪声、5MHz CMOS 运算放大器;
| 型号： | OPA2377-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 通过汽车级认证的轨到轨输入/输出、低噪声、5MHz CMOS 运算放大器 放大器 运算放大器 |
| 文件： | 总33页 (文件大小：1116K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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OPA377-Q1, OPA2377-Q1, OPA4377-Q1
ZHCSF20A –MAY 2016–REVISED MAY 2016
OPAx377-Q1 低噪声、低静态电流、汽车级精密运算放大器
1 特性
3 说明
1
•
适用于汽车电子 应用
具有符合 AEC-Q100 的下列结果：
OPAx377-Q1 系列运算放大器属于高带宽 CMOS 放大
器，同时拥有超低噪声、低输入偏置电流和低偏移电压
特性，静态工作电流低至 0.76mA（典型值）。
•
–
–
–
器件温度 1 级：-40℃ 至 +125℃ 的环境运行温
度范围
OPAx377-Q1 运放针对低电压、单电源应用进行了 优
化。其交流和直流性能都非常出色，非常适合 诸如小
信号调节、音频和有源滤波器等各类应用。此外，该系
列器件还具有较宽的电源范围及优异的电源抑制比
(PSRR)，因此对于不经过稳压而直接由电池供电运行
的 应用 而言极具吸引力。
器件人体放电模式 (HBM) 静电放电 (ESD) 分类
等级 3A
器件组件充电模式 (CDM) ESD 分类等级 C6
•
•
•
•
•
•
•
•
•
低噪声：1kHz 时为 7.5nV/√Hz
0.1Hz 至 10Hz 噪声：0.8 μVPP
静态电流：760μA（典型值）
低偏移电压：250μV（典型值）
增益带宽积：5.5MHz
轨到轨输入和输出
OPA377-Q1 采用 SOT23-5 封装。OPA2377-Q1（双
通道版本）采用微型小外形尺寸 (MSOP)-8 封
装，OPA4377-Q1（四通道版本）采用 TSSOP-14 封
装。所有器件版本的额定工作温度范围均为 -40°C 至
+125°C。
单电源供电
电源电压：2.2V 至 5.5V
小型封装：
器件信息(1)
–
小外形尺寸晶体管 (SOT)-23、超薄小外形尺寸
(VSSOP) 和薄型小外形尺寸 (TSSOP)
器件型号
OPA377-Q1
封装
SOT-23 (5)
VSSOP (8)
TSSOP (14)
封装尺寸（标称值）
2.90mm x 1.60mm
3.00mm × 3.00mm
5.00mm x 4.40mm
OPA2377-Q1
OPA4377-Q1
2 应用
•
•
•
•
•
•
主动巡航控制
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
停车辅助
轮胎气压监视
信息娱乐系统
有源滤波
传感器信号调节
低侧电流感测放大器
Load
VS
VBAT
+
VOUT = ISHUNT x RSHUNT x (1 + RF/RG)
œ
ISHUNT
RSHUNT
RG
RF
Copyright © 2016, Texas
Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SBOS797
OPA377-Q1, OPA2377-Q1, OPA4377-Q1
ZHCSF20A –MAY 2016–REVISED MAY 2016
www.ti.com.cn
目录
7.3 Feature Description................................................. 14
7.4 Device Functional Modes........................................ 15
Application and Implementation ........................ 16
8.1 Application Information............................................ 16
8.2 Typical Application ................................................. 16
Power Supply Recommendations...................... 18
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 6
6.1 Absolute Maximum Ratings ...................................... 6
6.2 ESD Ratings ............................................................ 6
6.3 Recommended Operating Conditions....................... 6
6.4 Thermal Information: OPA377-Q1 ............................ 6
6.5 Thermal Information: OPA2377-Q1 .......................... 6
6.6 Thermal Information: OPA4377-Q1 .......................... 7
6.7 Electrical Characteristics: VS = 2.2 V to 5.5 V .......... 7
6.8 Typical Characteristics ............................................. 9
Detailed Description ............................................ 13
7.1 Overview ................................................................. 13
7.2 Functional Block Diagram ....................................... 13
8
9
10 Layout................................................................... 18
10.1 Layout Guidelines ................................................. 18
10.2 Layout Example .................................................... 18
11 器件和文档支持 ..................................................... 20
11.1 器件支持 ............................................................... 20
11.2 文档支持 ............................................................... 21
11.3 社区资源................................................................ 21
11.4 商标....................................................................... 21
11.5 静电放电警告......................................................... 21
11.6 Glossary................................................................ 21
12 机械、封装和可订购信息....................................... 21
7
4 修订历史记录
Changes from Original (May 2016) to Revision A
Page
•
已将器件状态由“产品预览”更改为“量产数据” .......................................................................................................................... 1
2
Copyright © 2016, Texas Instruments Incorporated
OPA377-Q1, OPA2377-Q1, OPA4377-Q1
www.ti.com.cn
ZHCSF20A –MAY 2016–REVISED MAY 2016
5 Pin Configuration and Functions
OPA377-Q1: DBV Package
5-Pin SOT23
Top View
OUT
1
2
3
5
4
V+
V-
+IN
-IN
Pin Functions: OPA377-Q1
PIN
NO.
DBV
3
I/O
DESCRIPTION
NAME
+IN
–IN
NC
OUT
V–
I
Noninverting input
Inverting input
4
I
—
1
—
O
—
—
No internal connection (can be left floating)
Output
2
Negative (lowest) power supply
Positive (highest) power supply
V+
5
Copyright © 2016, Texas Instruments Incorporated
3
OPA377-Q1, OPA2377-Q1, OPA4377-Q1
ZHCSF20A –MAY 2016–REVISED MAY 2016
www.ti.com.cn
OPA2377-Q1: DGK Package
8-Pin VSSOP and SOIC
Top View
OUT A
1
2
3
4
8
7
6
5
V+
-IN A
+IN A
V-
OUT B
-IN B
+IN B
Pin Functions: OPA2377-Q1
PIN
NO.
I/O
DESCRIPTION
NAME
–IN A
DGK
2
6
3
5
1
7
4
8
I
I
Inverting input, channel A
Inverting input, channel B
Noninverting input, channel A
Noninverting input, channel B
Output, channel A
–IN B
+IN A
+IN B
OUT A
OUT B
V–
I
I
O
O
—
—
Output, channel B
Negative (lowest) power supply
Positive (highest) power supply
V+
4
Copyright © 2016, Texas Instruments Incorporated
OPA377-Q1, OPA2377-Q1, OPA4377-Q1
www.ti.com.cn
ZHCSF20A –MAY 2016–REVISED MAY 2016
OPA4377-Q1: PW Package
14-Pin TSSOP
Top View
OUT A
-IN A
+IN A
V+
1
2
3
4
5
6
7
14 OUT D
13 -IN D
12 +IN D
11 V-
+IN B
-IN B
OUT B
10 +IN C
9
8
-IN C
OUT C
Pin Functions: OPA4377-Q1
PIN
NO.
PW
2
I/O
DESCRIPTION
NAME
–IN A
I
I
Inverting input, channel A
–IN B
–IN C
–IN D
+IN A
+IN B
+IN C
+IN D
OUT A
OUT B
OUT C
OUT D
V–
6
Inverting input, channel B
Inverting input, channel C
Inverting input, channel D
Noninverting input, channel A
Noninverting input, channel B
Noninverting input, channel C
Noninverting input, channel D
Output, channel A
9
I
13
3
I
I
5
I
10
12
1
I
I
O
O
O
O
—
—
7
Output, channel B
8
Output, channel C
14
11
4
Output, channel D
Negative (lowest) power supply
Positive (highest) power supply
V+
Copyright © 2016, Texas Instruments Incorporated
5
OPA377-Q1, OPA2377-Q1, OPA4377-Q1
ZHCSF20A –MAY 2016–REVISED MAY 2016
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
7
UNIT
V
VS = (V+) – (V–)
Supply voltage
Signal input terminal voltage(2)
Signal input terminal current(2)
Output short-circuit current(3)
Operating temperature
Junction temperature
(V–) – 0.5
–10
(V+) + 0.5
10
V
mA
Continuous
150
TA
–40
–65
°C
°C
°C
TJ
150
Tstg
Storage temperature
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails should
be current limited to 10 mA or less.
(3) Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
±4000
±1000
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.2
MAX
UNIT
V
Supply voltage
5.5
TA
Operating temperature
–40
150
°C
6.4 Thermal Information: OPA377-Q1
OPA377-Q1
THERMAL METRIC(1)
DBV (SOT23)
5 PINS
273.8
126.8
85.9
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
10.9
ψJB
84.9
RθJC(bot)
n/a
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Thermal Information: OPA2377-Q1
OPA2377-Q1
THERMAL METRIC(1)
DGK (VSSOP)
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
171.2
°C/W
°C/W
RθJC(top)
63.9
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6
Copyright © 2016, Texas Instruments Incorporated
OPA377-Q1, OPA2377-Q1, OPA4377-Q1
www.ti.com.cn
ZHCSF20A –MAY 2016–REVISED MAY 2016
Thermal Information: OPA2377-Q1 (continued)
OPA2377-Q1
THERMAL METRIC(1)
DGK (VSSOP)
UNIT
8 PINS
92.8
9.2
RθJB
ψJT
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
91.2
n/a
RθJC(bot)
6.6 Thermal Information: OPA4377-Q1
OPA4377-Q1
PW (TSSOP)
14 PINS
107.8
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
29.6
52.6
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.5
ψJB
51.6
RθJC(bot)
n/a
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.7 Electrical Characteristics: VS = 2.2 V to 5.5 V
At TA = 25°C, RL = 10 kΩ connected to VS/2, VCM = VS/2, and VOUT = VS/2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
VS = 5 V
0.25
5
1
mV
Input offset voltage
versus temperature
At TA = –40°C to +125°C, VS = 2.2 V to 5.5 V,
VCM < (V+) – 1.3 V
µV/V
Input offset voltage
versus drift
dVOS/dT
PSRR
At TA = –40°C to +125°C
0.32
2
μV/°C
Input offset voltage
versus power supply
At TA = 25°C, VS = 2.2 V to 5.5 V,
VCM < (V+) – 1.3 V
5
28
μV/V
Channel separation, dc (dual, quad)
0.5
µV/V
INPUT BIAS CURRENT
IIB
Input bias current
±0.2
±10
±10
pA
pA
pA
Input bias current
versus temperature
See Typical Characteristics
IOS
Input offset current
±0.2
NOISE
Input voltage noise
f = 0.1 Hz to 10 Hz
f = 1 kHz
0.8
7.5
2
μVPP
nV/√Hz
fA/√Hz
en
in
Input voltage noise density
Input current noise density
f = 1 kHz
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
Common-mode rejection ratio
(V–) – 0.1
70
(V+) + 0.1
V
CMRR
(V–) < VCM < (V+) – 1.3 V
90
dB
INPUT CAPACITANCE
Differential
6.5
13
pF
pF
Common-mode
OPEN-LOOP GAIN
50 mV < VO < (V+) – 50 mV, RL = 10 kΩ
100 mV < VO < (V+) – 100 mV, RL = 2 kΩ
112
134
126
dB
dB
AOL
Open-loop voltage gain
FREQUENCY RESPONSE, VS = 5.5 V
Copyright © 2016, Texas Instruments Incorporated
7
OPA377-Q1, OPA2377-Q1, OPA4377-Q1
ZHCSF20A –MAY 2016–REVISED MAY 2016
www.ti.com.cn
Electrical Characteristics: VS = 2.2 V to 5.5 V (continued)
At TA = 25°C, RL = 10 kΩ connected to VS/2, VCM = VS/2, and VOUT = VS/2, unless otherwise noted.
PARAMETER
Gain-bandwidth product
Slew rate
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MHz
V/μs
μs
GBW
SR
5.5
G = +1
2
1.6
At 0.1%, 2-V step, G = +1
At 0.01%, 2-V step, G = +1
VIN × Gain > VS
tS
Settling time
2
μs
Overload recovery time
0.33
μs
THD+N
Total harmonic distortion + noise
VO = 1 VRMS, G = +1, f = 1 kHz, RL = 10 kΩ
0.00027%
OUTPUT
At TA = 25°C, RL = 10 kΩ
10
20
40
mV
mV
mA
Voltage output swing from rail
At TA = –40°C to +125°C, RL = 10 kΩ
ISC
Short-circuit current
+30/–50
CLOAD
RO
Capacitive load drive
See Typical Characteristics
Open-loop output impedance
150
Ω
POWER SUPPLY
VS
Specified voltage
2.2
5.5
1.05
1.2
V
At TA = 25°C, IO = 0, VS = 5.5 V
At TA = –40°C to +125°C
0.76
mA
mA
Quiescent current
(per amplifier)
IQ
TEMPERATURE
Specified temperature
–40
+125
°C
8
Copyright © 2016, Texas Instruments Incorporated
OPA377-Q1, OPA2377-Q1, OPA4377-Q1
www.ti.com.cn
ZHCSF20A –MAY 2016–REVISED MAY 2016
6.8 Typical Characteristics
At TA = 25°C, VS = 5 V, RL = 10 kΩ connected to VS/2, VCM = VS/2, and VOUT = VS/2, unless otherwise noted.
120
100
80
60
40
20
0
160
140
120
100
80
0
V(+) Power-Supply Rejection Ratio
-20
-40
Gain
-60
Phase
Common-Mode
Rejection Ratio
-80
60
-100
-120
-140
-160
-180
40
V(-) Power-Supply Rejection Ratio
20
0
-20
10
100
1k
10k
100k
1M
10M
0.1
1
10
100
1k
10k
100k 1M
10M
Frequency (Hz)
Frequency (Hz)
Figure 2. Power-Supply and Common-Mode
Rejection Ratio vs Frequency
Figure 1. Open-Loop Gain and Phase vs Frequency
160
Open-Loop Gain (RL = 10kW)
140
120
100
80
Power-Supply Rejection Ratio
(VS = 2.2V to 5.5V)
1s/div
-50
-25
0
25
50
75
100
125
150
Temperature (°C)
Figure 4. 0.1-Hz to 10-Hz Input Voltage Noise
Figure 3. Open-Loop Gain and Power-Supply
Rejection Ratio vs Temperature
100
10
1
1
VS = 5V, VCM = 2V, VOUT = 1VRMS
0.1
0.01
Gain = 10V/V
Gain = 1V/V
0.001
0.0001
1
10
100
1k
10k
100k
10
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
Figure 5. Input Voltage Noise Spectral Density
Figure 6. Total Harmonic Distortion and Noise
vs Frequency
Copyright © 2016, Texas Instruments Incorporated
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OPA377-Q1, OPA2377-Q1, OPA4377-Q1
ZHCSF20A –MAY 2016–REVISED MAY 2016
www.ti.com.cn
Typical Characteristics (continued)
At TA = 25°C, VS = 5 V, RL = 10 kΩ connected to VS/2, VCM = VS/2, and VOUT = VS/2, unless otherwise noted.
110
100
90
1000
900
800
700
600
500
80
70
60
50
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Temperature (°C)
Temperature (°C)
Figure 7. Common-Mode Rejection Ratio
vs Temperature
Figure 8. Quiescent Current
vs Temperature
75
50
1000
900
800
700
600
500
50
40
30
20
10
0
VS = ±2.75V
ISC+
ISC+
25
0
IQ
-25
-50
-75
-100
ISC-
-50
-25
0
25
50
75
100
125
150
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Temperature (°C)
Supply Voltage (V)
Figure 10. Short-Circuit Current
vs Temperature
Figure 9. Quiescent and Short-Circuit Current
vs Supply Voltage
3
2
1000
900
800
700
600
500
400
300
200
100
0
VS = ±2.75
1
+150°C
+125°C
+25°C
-40°C
0
-1
-2
-3
0
10
20
30
40
50
60
70
80
-50
-25
0
25
50
75
100
125
150
Output Current (mA)
Temperature (°C)
Figure 12. Output Voltage vs Output Current
Figure 11. Input Bias Current vs Temperature
10
Copyright © 2016, Texas Instruments Incorporated
OPA377-Q1, OPA2377-Q1, OPA4377-Q1
www.ti.com.cn
ZHCSF20A –MAY 2016–REVISED MAY 2016
Typical Characteristics (continued)
At TA = 25°C, VS = 5 V, RL = 10 kΩ connected to VS/2, VCM = VS/2, and VOUT = VS/2, unless otherwise noted.
6
VS = 5.5V
VS = 5V
5
4
3
VS = 2.5V
2
1
0
1k
10k
100k
1M
10M
Frequency (Hz)
Offset Voltage (mV)
Figure 14. Maximum Output Voltage vs Frequency
Figure 13. Offset Voltage
Production Distribution
50
40
30
20
10
0
G = +1
RL = 10kW
G = +1V/V
CL = 50pF
10
100
1k
Time (400ns/div)
Load Capacitance (pF)
Figure 16.
Small-Signal Pulse Response
Figure 15.
Small-Signal Overshoot vs Load Capacitance
100
10
1
G = +1
RL = 2kW
CL = 50pF
0.01%
0.1%
0.1
Time (2ms/div)
1
10
100
Closed-Loop Gain (V/V)
Figure 17. Large-Signal Pulse Response
Figure 18. Settling Time vs Closed-Loop Gain
Copyright © 2016, Texas Instruments Incorporated
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OPA377-Q1, OPA2377-Q1, OPA4377-Q1
ZHCSF20A –MAY 2016–REVISED MAY 2016
www.ti.com.cn
Typical Characteristics (continued)
At TA = 25°C, VS = 5 V, RL = 10 kΩ connected to VS/2, VCM = VS/2, and VOUT = VS/2, unless otherwise noted.
140
120
100
80
1k
100
10
60
400mA Load
2mA Load
40
1
20
0
0.1
10
100
1k
10k
100k
1M
10M
100M
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
Figure 19. Channel Separation vs Frequency
Figure 20. Open-Loop Output Resistance vs Frequency
2
T = 25°C
T = 85°C
T = 125°C
1.5
1
VCM = 1.45 V
VCM = –2.75 V
0.5
0
–0.5
–1
–1.5
–2
–3 –2.8 –2.6 –2.4 –2.2 –2 1.4 1.6 1.8
VCM (V)
2
2.2 2.4
C013
Figure 21. Input Offset Voltage vs Common-Mode Voltage
12
Copyright © 2016, Texas Instruments Incorporated
OPA377-Q1, OPA2377-Q1, OPA4377-Q1
www.ti.com.cn
ZHCSF20A –MAY 2016–REVISED MAY 2016
7 Detailed Description
7.1 Overview
The OPAx377-Q1 family belongs to a new generation of low-noise operational amplifiers, giving customers
outstanding dc precision and ac performance. Low noise, rail-to-rail input and output, and low offset, drawing a
low quiescent current, make these devices ideal for a variety of precision and portable applications. In addition,
this device has a wide supply range with excellent PSRR, making it a suitable option for applications that are
battery-powered without regulation.
7.2 Functional Block Diagram
+V
-
NCH Input
Stage
+
-
+IN
Output
Stage
OUT
œ IN
+
+
PCH Input
Stage
t
Copyright © 2016, Texas Instruments Incorporated
œ V
Copyright © 2016, Texas Instruments Incorporated
13
OPA377-Q1, OPA2377-Q1, OPA4377-Q1
ZHCSF20A –MAY 2016–REVISED MAY 2016
www.ti.com.cn
7.3 Feature Description
7.3.1 Operating Characteristics
The OPAx377-Q1 family of amplifiers has parameters that are fully specified from 2.2 V to 5.5 V (±1.1 V to ±2.75
V). Many of the specifications apply from –40°C to +125°C. Parameters that can exhibit significant variance with
regard to operating voltage or temperature are presented in the Typical Characteristics section.
7.3.2 Common-Mode Voltage Range
The input common-mode voltage range of the OPAx377-Q1 series extends 100 mV beyond the supply rails. The
offset voltage of the amplifier is low, from approximately (V–) to (V+) – 1 V, as shown in Figure 22. The offset
voltage increases as common-mode voltage exceeds (V+) – 1 V. Common-mode rejection is specified from (V–)
to (V+) – 1.3 V.
3
2
1
0
-1
-2
-V
+V
-3
-0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Input Common-Mode Voltage (V)
Figure 22. Offset and Common-Mode Voltage
7.3.3 Input and ESD Protection
The OPAx377-Q1 family incorporates internal electrostatic discharge (ESD) protection circuits on all pins. In the
case of input and output pins, this protection primarily consists of current steering diodes connected between the
input and power-supply pins. These ESD protection diodes also provide in-circuit, input overdrive protection, as
long as the current is limited to 10 mA as stated in the Absolute Maximum Ratings table.
Figure 23 shows how a series input resistor may be added to the driven input to limit the input current. The
added resistor contributes thermal noise at the amplifier input and its value must be kept to a minimum in noise-
sensitive applications.
V+
IOVERLOAD
10 mA max
VOUT
OPA377-Q1
VIN
5 kW
Copyright © 2016, Texas Instruments Incorporated
Figure 23. Input Current Protection
14
Copyright © 2016, Texas Instruments Incorporated
OPA377-Q1, OPA2377-Q1, OPA4377-Q1
www.ti.com.cn
ZHCSF20A –MAY 2016–REVISED MAY 2016
Feature Description (continued)
7.3.4 EMI Susceptibility and Input Filtering
Operational amplifiers vary in susceptibility to electromagnetic interference (EMI). If conducted EMI enters the
operational amplifier, the dc offset observed at the amplifier output may shift from the nominal value while the
EMI is present. This shift is a result of signal rectification associated with the internal semiconductor junctions.
While all amplifier pin functions can be affected by EMI, the input pins are likely to be the most susceptible. The
OPAx377-Q1 operational amplifier family incorporates an internal input low-pass filter that reduces the amplifier
response to EMI. Both common-mode and differential mode filtering are provided by the input filter. The filter is
designed for a cutoff frequency of approximately 75 MHz (–3 dB), with a roll-off of 20 dB per decade.
7.3.5 Capacitive Load and Stability
The OPAx377-Q1 series of amplifiers may be used in applications where driving a capacitive load is required. As
with all op amps, there may be specific instances where the OPAx377-Q1 can become unstable, leading to
oscillation. The particular op amp circuit configuration, layout, gain, and output loading are some of the factors to
consider when establishing whether an amplifier will be stable in operation. An op amp in the unity-gain (1 V/V)
buffer configuration and driving a capacitive load exhibits a greater tendency to be unstable than an amplifier
operated at a higher noise gain. The capacitive load, in conjunction with the op amp output resistance, creates a
pole within the feedback loop that degrades the phase margin. The degradation of the phase margin increases
as the capacitive loading increases.
The OPAx377-Q1 in a unity-gain configuration can directly drive up to 250-pF pure capacitive load. Increasing
the gain enhances the ability of the amplifier to drive greater capacitive loads; see the typical characteristic plot,
Figure 15. In unity-gain configurations, capacitive load drive can be improved by inserting a small (10-Ω to 20-Ω)
resistor, RS, in series with the output, as shown in Figure 24. This resistor significantly reduces ringing while
maintaining dc performance for purely capacitive loads. However, if there is a resistive load in parallel with the
capacitive load, a voltage divider is created, introducing a gain error at the output and slightly reducing the output
swing. The error introduced is proportional to the ratio RS/RL, and is generally negligible at low output current
levels.
V +
RS
VOUT
OPA377-Q1
10 W to
20 W
VIN
CL
RL
Copyright © 2016, Texas Instruments Incorporated
Figure 24. Improving Capacitive Load Drive
7.4 Device Functional Modes
The OPAx377-Q1 has a single functional mode and is operational when the power-supply voltage is greater than
2.2 V (±1.1 V). The maximum power supply voltage for the OPAx376-Q1 is 5.5 V (±2.75 V).
Copyright © 2016, Texas Instruments Incorporated
15
OPA377-Q1, OPA2377-Q1, OPA4377-Q1
ZHCSF20A –MAY 2016–REVISED MAY 2016
www.ti.com.cn
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The OPAx377-Q1 family of operational amplifiers is built on a precision analog CMOS technology featuring low
noise and low offset voltage. The OPAx377-Q1 family delivers excellent offset voltage (250 μV, typical).
Additionally, the amplifier boasts a fast slew rate, low drift, low noise, and excellent PSRR and AOL. These 5.5-
MHz CMOS op amps operate on 760 μA (typical) quiescent current.
8.2 Typical Application
Low-pass filters are commonly employed in signal processing applications to reduce noise and prevent aliasing.
The OPA377-Q1 is ideally suited to construct high-speed, high-precision active filters. Figure 25 shows a
second-order, low-pass filter commonly encountered in signal processing applications.
R4
2.94 kꢀ
C5
1 nF
œ
R1
R3
Output
590 ꢀ
499 ꢀ
+
Input
C2
39 nF
Copyright © 2016, Texas Instruments Incorporated
Figure 25. Typical Application Schematic
8.2.1 Design Requirements
Use the following parameters for this design example:
•
•
•
Gain = 5 V/V (inverting gain)
Low-pass cutoff frequency = 25 kHz
Second-order Chebyshev filter response with 3-dB gain peaking in the passband
8.2.2 Detailed Design Procedure
The infinite-gain multiple-feedback circuit for a low-pass network function is shown in Figure 25. Use Equation 1
to calculate the voltage transfer function.
-1 R1R3C2C5
Output
Input
s =
( )
s2 + s C 1 R +1 R +1 R +1 R R C C
2
1
3
4
3 4 2 5
(1)
This circuit produces a signal inversion. For this circuit, the gain at dc and the low-pass cutoff frequency are
calculated by Equation 2:
R4
Gain =
R1
1
fC =
1 R R C C
(
3 4 2 5
)
2p
(2)
Software tools are readily available to simplify filter design. WEBENCH® Filter Designer is a simple, powerful,
and easy-to-use active filter design program. The WEBENCH Filter Designer lets you create optimized filter
designs using a selection of TI operational amplifiers and passive components from TI's vendor partners.
16
Copyright © 2016, Texas Instruments Incorporated
OPA377-Q1, OPA2377-Q1, OPA4377-Q1
www.ti.com.cn
ZHCSF20A –MAY 2016–REVISED MAY 2016
Typical Application (continued)
Available as a web-based tool from the WEBENCH® Design Center, WEBENCH® Filter Designer allows to
design, optimize, and simulate complete multi-stage active filter solutions within minutes.
8.2.3 Application Curve
20
0
-20
-40
-60
100
1k
10k
100k
1M
Frequency (Hz)
Figure 26. Low-Pass Filter Transfer Function
Copyright © 2016, Texas Instruments Incorporated
17
OPA377-Q1, OPA2377-Q1, OPA4377-Q1
ZHCSF20A –MAY 2016–REVISED MAY 2016
www.ti.com.cn
9 Power Supply Recommendations
The OPAx377-Q1 family of devices is specified for operation from 2.2 V to 5.5 V (±1.1 V to ±2.75 V); many
specifications apply from –40°C to +125°C. Parameters that can exhibit significant variance with regard to
operating voltage or temperature are presented in the Typical Characteristics section.
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices,
including:
•
Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power
sources local to the analog circuitry.
–
Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground,
placed as close to the device as possible. A single bypass capacitor from V+ to ground is
applicable for single-supply applications.
•
•
Separate grounding for analog and digital portions of circuitry is one of the simplest and most-
effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted
to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to
physically separate digital and analog grounds paying attention to the flow of the ground current. For
more detailed information refer to the application report, Circuit Board Layout Techniques, SLOA089.
In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces
as possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is
much better as opposed to in parallel with the noisy trace.
•
•
•
Place the external components as close to the device as possible. As shown in Figure 28, keeping
RF and RG close to the inverting input minimizes parasitic capacitance.
Keep the length of input traces as short as possible. Always remember that the input traces are the
most sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
•
•
Cleaning the PCB following board assembly is recommended for best performance.
Any precision integrated circuit may experience performance shifts due to moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is
recommended to remove moisture introduced into the device packaging during the cleaning process.
A low temperature, post cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
10.2 Layout Example
+
VIN
VOUT
œ
RG
RF
Copyright © 2016,
Texas Instruments Incorporated
Figure 27. Typical Schematic for PCB Layout Example
18
Copyright © 2016, Texas Instruments Incorporated
OPA377-Q1, OPA2377-Q1, OPA4377-Q1
www.ti.com.cn
ZHCSF20A –MAY 2016–REVISED MAY 2016
Layout Example (continued)
VS+
VOUT
VSœ
V+
OUT
GND
Vœ
Use a low-ESR,
ceramic bypass
Use a low-ESR,
ceramic bypass
capacitor.
capacitor.
RG
+IN
œIN
VIN
GND
GND
Run the input traces
as far away from
the supply lines
as possible.
Place components
close to the device
and to each other to
reduce parasitic
errors.
RF
Copyright © 2016, Texas Instruments Incorporated
Figure 28. Typical PCB Layout Example
版权 © 2016, Texas Instruments Incorporated
19
OPA377-Q1, OPA2377-Q1, OPA4377-Q1
ZHCSF20A –MAY 2016–REVISED MAY 2016
www.ti.com.cn
11 器件和文档支持
11.1 器件支持
11.1.1 开发支持
11.1.1.1 TINA-TI™（免费软件下载）
TINA™是一款简单、功能强大且易于使用的电路仿真程序，此程序基于 SPICE 引擎。 TINA-TI™ 是 TINA 软件的
一款免费全功能版本，除了一系列无源和有源模型外，此版本软件还预先载入了一个宏模型库。TINA-TI 提供所有
传统的 SPICE 直流、瞬态和频域分析，以及其他设计功能。
TINA-TI 可从 Analog eLab Design Center（模拟电子实验室设计中心）免费下载，它提供全面的后续处理能力，
使得用户能够以多种方式形成结果。虚拟仪器提供选择输入波形和探测电路节点、电压和波形的功能，从而创建一
个动态的快速入门工具。
注
这些文件需要安装 TINA 软件（由 DesignSoft™提供）或者 TINA-TI 软件。请从 TINA-TI 文
件夹 中下载免费的 TINA-TI 软件。
11.1.1.2 DIP 适配器 EVM
DIP 适配器 EVM 工具提供了一种简单而低成本的方式来针对小型表面贴装 IC 进行原型设计。评估工具适用于以下
TI 封装：D 或 U (SOIC-8)、PW (TSSOP-8)、DGK (MSOP-8)、DBV（SOT23-6、SOT23-5 和 SOT23-3）、DCK
（SC70-6 和 SC70-5）和 DRL (SOT563-6)。DIP 适配器 EVM 也可搭配引脚排使用或直接与现有电路相连。
11.1.1.3 通用运放 EVM
通用运放 EVM 是一系列通用空白电路板，可简化采用各种 IC 封装类型的电路板原型设计。借助评估模块电路板设
计，可以轻松快速地构造多种不同电路。共有
5
个模型可供选用，每个模型都对应一种特定封装类型。支持
PDIP、SOIC、MSOP、TSSOP 和 SOT23 封装。
注
这些电路板均为空白电路板，用户必须自行提供 IC。TI 建议您在订购通用运放 EVM 时申请
几个运放器件样品。
11.1.1.4 TI 高精度设计
TI 高精度设计是由 TI 公司的高精度模拟 应用 专家创建的模拟解决方案，提供了许多实用电路的工作原理、组件选
择、仿真、完整 PCB 电路原理图和布局布线、物料清单以及性能测量结果。欲获取 TI 高精度设计，请访问
http://www.ti.com.cn/ww/analog/precision-designs/。
11.1.1.5 WEBENCH®滤波器设计器
WEBENCH® 滤波器设计器是一款简单、功能强大且便于使用的有源滤波器设计程序。WEBENCH Filter Designer
通过选择 TI 运算放大器以及 TI 供应商合作伙伴的无源组件来构建优化滤波器设计方案。
WEBENCH® 设计中心以基于网络的工具形式提供 WEBENCH® Filter Designer。用户通过该工具可在短时间内完
成多级有源滤波器解决方案的设计、优化和仿真。
20
版权 © 2016, Texas Instruments Incorporated
OPA377-Q1, OPA2377-Q1, OPA4377-Q1
www.ti.com.cn
ZHCSF20A –MAY 2016–REVISED MAY 2016
11.2 文档支持
11.2.1 相关文档ꢀ
相关文档如下：
•
•
•
•
•
•
•
•
《电路板布局布线技巧》，SLOA089
《运算放大器增益稳定性，第 3 部分：交流增益误差分析》，SLYT383
《运算放大器增益稳定性，第 2 部分：直流增益误差分析》，SLYT374
《运算放大器性能分析》，SBOS054
《无铅组件涂层的保存期评估》，SZZA046
《运算放大器的单电源运行》，SBOA059
《调整放大器》，SBOA067
《在全差分有源滤波器中使用无限增益、MFB 滤波器拓扑》，SLYT343
11.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 商标
TINA-TI, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
11.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2016, Texas Instruments Incorporated
21
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA2377QDGKRQ1
OPA377QDBVRQ1
OPA4377AQPWRQ1
ACTIVE
ACTIVE
ACTIVE
VSSOP
SOT-23
TSSOP
DGK
DBV
PW
8
5
2500 RoHS & Green
3000 RoHS & Green
2000 RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
2377
377Q
NIPDAU
NIPDAU
14
4377Q1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA2377QDGKRQ1
OPA377QDBVRQ1
OPA4377AQPWRQ1
VSSOP
SOT-23
TSSOP
DGK
DBV
PW
8
5
2500
3000
2000
330.0
178.0
330.0
12.4
9.0
5.3
3.3
6.9
3.4
3.2
5.6
1.4
1.4
1.6
8.0
4.0
8.0
12.0
8.0
Q1
Q3
Q1
14
12.4
12.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA2377QDGKRQ1
OPA377QDBVRQ1
OPA4377AQPWRQ1
VSSOP
SOT-23
TSSOP
DGK
DBV
PW
8
5
2500
3000
2000
366.0
180.0
356.0
364.0
180.0
356.0
50.0
18.0
35.0
14
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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