OPA2626IDGKT [TI]
高带宽、高精度、低 THD+N、16 位和 18 位 ADC 驱动器》 | DGK | 8 | -40 to 125;
| 型号： | OPA2626IDGKT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 高带宽、高精度、低 THD+N、16 位和 18 位 ADC 驱动器》 | DGK | 8 | -40 to 125 放大器 驱动 光电二极管 驱动器 |
| 文件： | 总39页 (文件大小：2644K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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OPA2626
ZHCSF85A –JULY 2016–REVISED DECEMBER 2019
OPA2626 高速、高精度、低失真、16 位和 18 位
模数转换器 (ADC) 驱动器
1 特性
3 说明
1
•
出色的动态性能：
OPA2626 运算放大器是一款 16 位和 18 位、高精度
逐次逼近寄存器 (SAR) 型模数转换器 (ADC) 驱动器，
具有低总谐波失真 (THD) 和低噪声。该运算放大器在
额定工作条件下的 16 位稳定时间为 280ns，可提供真
正的 16 位有效位数 (ENOB)。该器件具有高直流精度
（失调电压仅为 100µV）、120MHz 的宽增益带宽积
以及 2.5nV/√Hz 的低宽带噪声，并且经优化可驱动 应
用 中的高吞吐量、高分辨率的 SAR ADC，如
ADS88xx 系列 SAR ADC。
–
低失真：100kHz 时，HD2 为 –122dBc，
HD3 为 –140dBc
–
–
–
–
–
增益带宽 (G = 100)：120MHz
压摆率：115V/µs
16 位稳定时间（4V 阶跃）：280ns
低电压噪声：10kHz 时为 2.5nV/√Hz
低输出阻抗：1MHz 时为 1Ω
•
出色的直流精度：
–
–
–
失调电压：±100µV（最大值）
失调电压温漂：±3µV/ºC（最大值）
低静态电流：2mA（典型值）
OPA2626 采用 8 引脚 VSSOP 封装，额定工作温度范
围为 –40°C 至 +125°C。
器件信息(1)
•
•
•
输入共模范围包括负电源轨
轨至轨输出
器件型号
OPA2626
封装
封装尺寸（标称值）
VSSOP (8)
3.00mm × 3.00mm
宽额定温度范围：–40°C 至 +125°C
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
2 应用
•
•
•
•
•
•
•
精密 SAR ADC 驱动器
精密电压基准缓冲器
可编程逻辑控制器
测试和测量设备
科学仪表
高吞吐量数据采集系统
高密度、多路复用数据采集系统
空白
SAR ADC 驱动器
高保真拓扑
改善了动态性能
1 kꢀ
1 kꢀ
（fIN = 10kHz，1MSPS FFT）
0
5 V
Input
THD = -110.8 dBc
SNR = 91.88 dB
SINAD = 91.86 dB
ENOB = 14.97
Voltage
-25
-50
RFLT
VREF
REF
3.3 V
4.7 ꢀ
+
VREF / 4
OPA626
AVDD
CFLT
ADS8860
GND
-75
10 nF
RFLT
-115.91 dBc (Third Harmonic)
-100
-125
-150
-175
4.7 ꢀ
0
50 100 150 200 250 300 350 400 450 500
Frequency (kHz)
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOS690
OPA2626
ZHCSF85A –JULY 2016–REVISED DECEMBER 2019
www.ti.com.cn
目录
8.2 Functional Block Diagram ....................................... 21
8.3 Feature Description................................................. 22
8.4 Device Functional Modes........................................ 23
Application and Implementation ........................ 23
9.1 Application Information............................................ 23
9.2 Typical Applications ................................................ 23
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics: High-Supply .................... 5
6.6 Electrical Characteristics: Low-Supply...................... 7
6.7 Typical Characteristics.............................................. 9
Parameter Measurement Information ................ 18
7.1 DC Parameter Measurements ................................ 18
7.2 Transient Parameter Measurements ...................... 19
7.3 AC Parameter Measurements ................................ 19
7.4 Noise Parameter Measurements ............................ 20
Detailed Description ............................................ 21
8.1 Overview ................................................................. 21
9
10 Power Supply Recommendations ..................... 28
11 Layout................................................................... 28
11.1 Layout Guidelines ................................................. 28
11.2 Layout Example .................................................... 29
12 器件和文档支持 ..................................................... 30
12.1 器件支持................................................................ 30
12.2 文档支持................................................................ 30
12.3 接收文档更新通知 ................................................. 30
12.4 社区资源................................................................ 30
12.5 商标....................................................................... 30
12.6 静电放电警告......................................................... 30
12.7 Glossary................................................................ 31
13 机械、封装和可订购信息....................................... 31
7
8
4 修订历史记录
Changes from Original (July 2016) to Revision A
Page
•
•
•
•
•
已删除 删除了文档中的 OPA626（5 引脚 SOT DBV 封装） ................................................................................................. 1
已添加 18-bit SAR ADC to amplifier description in Overview section ................................................................................. 21
已添加 18-bit level to device description in Application Information section ....................................................................... 23
已添加 (pins 3 and 4) to input terminals in Design Requirements section of first typical application for clarity .................. 24
已更改 description of slew and settle time in Design Requirements section of second typical application for clarity ........ 26
2
Copyright © 2016–2019, Texas Instruments Incorporated
OPA2626
www.ti.com.cn
ZHCSF85A –JULY 2016–REVISED DECEMBER 2019
5 Pin Configuration and Functions
OPA2626 DGK Package
8-Pin VSSOP
Top View
OUT A
œIN A
+IN A
Vœ
V+
1
8
7
6
5
OUT B
œIN B
+IN B
2
3
4
Pin Functions: OPA2626
PIN
I/O
DESCRIPTION
NAME
+IN A
NO.
3
I
I
Noninverting input for channel A
Inverting input for channel A
Noninverting input for channel B
Inverting input for channel B
Output terminal for channel A
Output terminal for channel B
Positive supply voltage
–IN A
+IN B
–IN B
OUT A
OUT B
V+
2
5
I
6
I
1
O
O
—
—
7
8
V–
4
Negative supply voltage
Copyright © 2016–2019, Texas Instruments Incorporated
3
OPA2626
ZHCSF85A –JULY 2016–REVISED DECEMBER 2019
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
6
UNIT
Supply voltage, VS
Input voltage(2)
Output voltage
(V+) – (V–)
V
+IN
(V–) – 0.3
(V–) – 0.3
(V–)
(V+) + 0.3
(V+) + 0.3
(V+)
10
V
V
–IN
OUT
+IN
Sink current
Source current
Temperature
–IN
10
mA
mA
°C
OUT
150
+IN
10
–IN
10
OUT
150
Operating junction
Operating free-air, TA
Storage, Tstg
–40
–55
–65
150
150
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) For input voltages beyond the power-supply rails, voltage or current must be limited.
6.2 ESD Ratings
VALUE
±3000
±1500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.7
NOM
MAX
5.5
UNIT
VS
VI
Supply input voltage, (V+) – (V–)
Input voltage
V
+IN
–IN
(V–)
(V–)
(V–)
–120
–40
(V+) – 1.15
(V+) – 1.15
(V+)
V
VO
IO
Output voltage
V
Output current
120
mA
°C
°C
TA
TJ
Operating free-air temperature
Operating junction temperature
125
–40
125
4
Copyright © 2016–2019, Texas Instruments Incorporated
OPA2626
www.ti.com.cn
ZHCSF85A –JULY 2016–REVISED DECEMBER 2019
6.4 Thermal Information
OPA2626
THERMAL METRIC(1)
DGK (VSSOP)
8 PINS
171.7
68.4
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
91.9
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
9.4
ψJB
90.5
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
6.5 Electrical Characteristics: High-Supply
at TA = 25°C, V+ = 5 V, V– = 0 V, VCOM = VO = 2.5 V, gain (G) = 1, RF = 1 kΩ, CF = 2.7 pF, CLOAD = 20 pF, and RLOAD = 2 kΩ
connected to 2.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
Unity gain frequency
Phase margin
VO = 10 mVPP
80
50
MHz
Degrees
MHz
φm
GBW
Gain-bandwidth product G = 100, VO = 10 mVPP
120
45
VO = 1-V step, G = 1
Slew rate
SR
V/µs
VO = 4-V step, G = 2
115
Settling time to 0.1%
(10-bit accuracy)
80
110
280
to 0.005%
(14-bit accuracy)
tsettle
Settling time
VO = 4-V step, G = 2
ns
to 0.00153%
(16-bit accuracy)
Overshoot
VO = 4-V step, G = 2
VO = 4-V step, G = 2
2.5%
3%
144
122
80
Undershoot
f = 10 kHz
f = 100 kHz
f = 1 MHz
f = 10 kHz
f = 100 kHz
f = 1 MHz
Second-order harmonic
distortion
HD2
HD3
VO = 2 VPP, G = 2
VO = 2 VPP, G = 2
dBc
dBc
155
140
80
Third-order harmonic
distortion
Second-order
intermodulation distortion
VO = 2 VPP, f = 1 MHz, 200-kHz tone spacing
VO = 2 VPP, f = 1 MHz, 200-kHz tone spacing
90
dBc
dBc
Third-order
intermodulation distortion
100
f = 0.1 Hz to 10 Hz, peak-to-peak
f = 0.1 Hz to 10 Hz, rms
f = 1 kHz
0.8
120
3.2
2.5
6.6
3.5
50
µVPP
VN
Vn
In
Input noise voltage
nVRMS
Input voltage noise
density
nV/√Hz
pA/√Hz
f = 10 kHz
f = 1 kHz
Input current noise
density
f = 10 kHz
tOR
Zo
Overload recovery time
G = 5
ns
Open-loop output
impedance
f = 1 MHz
1
Ω
At DC
150
127
Crosstalk
dB
f = 1 MHz
DC PERFORMANCE
Copyright © 2016–2019, Texas Instruments Incorporated
5
OPA2626
ZHCSF85A –JULY 2016–REVISED DECEMBER 2019
www.ti.com.cn
Electrical Characteristics: High-Supply (continued)
at TA = 25°C, V+ = 5 V, V– = 0 V, VCOM = VO = 2.5 V, gain (G) = 1, RF = 1 kΩ, CF = 2.7 pF, CLOAD = 20 pF, and RLOAD = 2 kΩ
connected to 2.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
±100
±300
±3
UNIT
µV
15
VOS
Input offset voltage
TA = –40°C to 125°C
TA = –40°C to 125°C
0.5
0.6
µV/°C
dVOS/dT
PSRR
Input offset voltage drift
±4
100
90
Power-supply rejection
ratio
2.7 V ≤ (V+) ≤ 5 V
dB
TA = –40°C to 125°C
120
2
4
5.7
6.5
IB
Input bias current
µA
nA/°C
nA
TA = –40°C to 125°C
TA = –40°C to 125°C
dIB/dT
IOS
Input bias current drift
Input offset current
Input offset current drift
15
20
120
150
350
TA = –40°C to 125°C
TA = –40°C to 125°C
dIOS/dT
0.6
nA/°C
OPEN LOOP GAIN
(V–) + 0.2 V < VO < (V+) – 0.2 V, RLOAD = 600 Ω
(V–) + 0.15 V < VO < (V+) – 0.15 V, RLOAD = 10 kΩ
110
114
(V–) + 0.2 V < VO < (V+) – 0.2 V,
RLOAD = 600 Ω
AOL
Open-loop gain
dB
106
110
128
132
TA = –40°C to 125°C
(V–) + 0.15 V < VO < (V+) – 0.15 V,
RLOAD = 10 kΩ
INPUT VOLTAGE
Common-mode voltage
range
(V+) –
1.15
VCM
TA = –40°C to 125°C
(V–)
V
100
90
117
115
Common-mode rejection
ratio
CMRR
(V–) < VCOM < (V+) – 1.15 V
dB
TA = –40°C to 125°C
INPUT IMPEDANCE
Differential input
impedance
ZID
27 || 1.2
47 || 1.5
KΩ || pF
MΩ || pF
Common-mode input
impedance
ZIC
OUTPUT
60
20
80
100
35
RLOAD = 600 Ω
RLOAD = 10 kΩ
TA = –40°C to 125°C
TA = –40°C to 125°C
Output voltage swing to
the rail
mV
mA
40
Isc
Short-circuit current
Capacitive load drive
130
CLOAD
See Typical Characteristics
POWER SUPPLY
2
2.2
3.1
Quiescent current per
amplifier
IQ
IO = 0 mA
mA
TA = –40°C to 125°C
6
Copyright © 2016–2019, Texas Instruments Incorporated
OPA2626
www.ti.com.cn
ZHCSF85A –JULY 2016–REVISED DECEMBER 2019
6.6 Electrical Characteristics: Low-Supply
at TA = 25°C, V+ = 2.7 V, V– = 0 V, VCOM = VO = 1.35 V, gain (G) = 1, RF = 1 kΩ, CF = 2.7 pF, CLOAD = 20 pF, and RLOAD
=
1 kΩ connected to 1.35 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
Unity gain frequency
Phase margin
VO = 10 mVPP
76
50
MHz
Degrees
MHz
φm
GBW
SR
Gain-bandwidth product G = 100, VO = 10 mVPP
110
45
Slew rate
VO = 1-V step, G = 2
V/µs
to 0.1%
80
tsettle
Settling time
VO = 1-V step, G = 2
to 0.01%
170
250
6%
5%
136
118
80
ns
to 0.000763% (17-bit accuracy)
Overshoot
VO = 1-V step, G = 2
VO = 1-V step, G = 2
Undershoot
f = 10 kHz
f = 100 kHz
f = 1 MHz
f = 10 kHz
f = 10 kHz
f = 100 kHz
f = 100 kHz
f = 1 MHz
f = 1 MHz
(V+) = 3.3 V, (V–) = 0 V,
VCOM = 1.1 V,
VO = 2 VPP
Second-order harmonic
distortion
HD2
HD3
dBc
dBc
143
143
130
125
85
(V+) = 3.3 V, (V–) = 0 V,
VCOM = 1.1 V,
VO = 2 VPP
Third-order harmonic
distortion
74
(V+) = 3.3 V, (V–) = 0 V, VCOM = 1.1 V, VO = 2 VPP
f = 1 MHz, 200-kHz tone spacing
,
Second-order
intermodulation distortion
95
dBc
dBc
(V+) = 3.3 V, (V–) = 0 V, VCOM = 1.1V, VO = 1 VPP
,
Third-order
intermodulation distortion
104
f = 1 MHz, 200-kHz tone spacing
f = 0.1 Hz to 10 Hz, peak-to-peak
f = 0.1 Hz to 10 Hz, rms
0.8
µVPP
VN
Vn
Input noise voltage
120
nVRMS
Input voltage noise
density
f = 10 kHz
2.5
nV/√Hz
Input current noise
density
In
f = 10 kHz
G = 5
3.5
35
pA/√Hz
tOR
Zo
Overload recovery time
ns
Open-loop output
impedance
f = 1 MHz
1.3
Ω
At DC
150
127
Crosstalk
dB
f = 1 MHz
DC PERFORMANCE
15
±100
±300
±3.1
±4
VOS
Input offset voltage
µV
TA = –40°C to 125°C
TA = –40°C to 125°C
0.5
0.6
2
dVOS/dT
Input offset voltage drift
µV/°C
4
IB
Input bias current
5.7
µA
nA/°C
nA
TA = –40°C to 125°C
TA = –40°C to 125°C
6.5
dIB/dT
IOS
Input bias current drift
Input offset current
Input offset current drift
15
20
120
150
200
TA = –40°C to 125°C
TA = –40°C to 125°C
dIOS/dT
80
pA/°C
OPEN-LOOP GAIN
Copyright © 2016–2019, Texas Instruments Incorporated
7
OPA2626
ZHCSF85A –JULY 2016–REVISED DECEMBER 2019
www.ti.com.cn
Electrical Characteristics: Low-Supply (continued)
at TA = 25°C, V+ = 2.7 V, V– = 0 V, VCOM = VO = 1.35 V, gain (G) = 1, RF = 1 kΩ, CF = 2.7 pF, CLOAD = 20 pF, and RLOAD
1 kΩ connected to 1.35 V (unless otherwise noted)
=
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
(V–) + 0.2 V < VO < (V+) – 0.2 V,
RLOAD = 600 Ω
110
(V–) + 0.15 V < VO < (V+) – 0.15 V,
RLOAD = 10 kΩ
114
100
104
AOL
Open-loop gain
dB
(V–) + 0.2 V < VO < (V+) – 0.2 V,
128
132
RLOAD = 600 Ω
TA = –40°C to 125°C
(V–) + 0.15 V < VO < (V+) – 0.15 V,
RLOAD = 10 kΩ
INPUT VOLTAGE
Common-mode voltage
range
(V+) –
1.15
VCM
TA = –40°C to 125°C
(V–)
V
100
90
117
115
Common-mode rejection
ratio
CMRR
(V–) < VCOM < (V+) – 1.15 V
dB
TA = –40°C to 125°C
INPUT IMPEDANCE
Differential input
impedance
ZID
27 || 0.8
47 || 1.2
KΩ || pF
MΩ || pF
Common-mode input
impedance
ZIC
OUTPUT
60
20
80
80
100
35
R LOAD = 600 Ω
R LOAD = 10 kΩ
TA = –40°C to 125°C
TA = –40°C to 125°C
Output voltage swing to
the rail
mV
mA
40
ISC
Short-circuit current
Capacitive load drive
CLOAD
See Typical Characteristics
POWER SUPPLY
2
2.1
2.8
Quiescent current per
amplifier
IQ
IO = 0 mA
mA
TA = –40°C to 125°C
8
版权 © 2016–2019, Texas Instruments Incorporated
OPA2626
www.ti.com.cn
ZHCSF85A –JULY 2016–REVISED DECEMBER 2019
6.7 Typical Characteristics
at TA = 25°C, V+ = 5 V, V– = 0 V, VCOM = VO = 2.5 V, gain (G) = 2, RF = 1 kΩ, CF= 2.7 pF, CLOAD= 20 pF, and RLOAD = 2 kΩ
connected to 2.5 V (unless otherwise noted)
25
20
25
20
15
15
10
10
5
5
0
0
Gain = 1
Gain = -1
Gain = 2
Gain = 5
Gain = 10
œ5
œ5
Gain = 1
Gain = -1
Gain = 2
Gain = 5
Gain = 10
œ10
œ15
œ20
œ25
œ10
œ15
œ20
œ25
10k
100k
1M
10M
100M
10k
100k
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
C004
C005
VO = 10 mVPP
VO = 2 VPP
图 1. Small-Signal Frequency Response for Various Gains
图 2. Large-Signal Frequency Response for Various Gains
2.5
10
8
5.5 V
2.0
2.7 V
6
1.5
1.0
4
2
0
0.5
œ2
œ4
0 pF
8.2 pF
22 pF
33 pF
47 pF
0.0
œ6
-0.5
œ8
-1.0
œ10
100k
1M
10M
100M
1M
10M
100M
Frequency (Hz)
1G
Frequency (Hz)
C006
C007
VO = 10 mVPP, G = 1
VO = 10 mVPP , G = 1
图 3. Small-Signal Frequency Response for Various Power
图 4. Small-Signal Frequency Response for Various
Supply Voltages
Capacitive Loads
2
1
2.5
2 kꢀ
1 kꢀ
600 ꢀ
2.0
1.5
1.0
0.5
0.0
-0.5
0
œ1
œ2
œ3
œ4
œ5
œ6
œ7
œ8
0 pF
8.2 pF
22 pF
33 pF
47 pF
10k
100k
1M
10M
100M
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
C007
C007
VO = 2 VPP, G = 1
VO = 10 mVPP , G = 1
图 5. Large-Signal Frequency Response for Various
图 6. Small-Signal Frequency Response for Various
Capacitive Loads
Resistive Loads
版权 © 2016–2019, Texas Instruments Incorporated
9
OPA2626
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Typical Characteristics (接下页)
at TA = 25°C, V+ = 5 V, V– = 0 V, VCOM = VO = 2.5 V, gain (G) = 2, RF = 1 kΩ, CF= 2.7 pF, CLOAD= 20 pF, and RLOAD = 2 kΩ
connected to 2.5 V (unless otherwise noted)
160
120
80
40
0
225
180
135
90
1000
100
10
45
Gain
Phase
0
-40
1
10
0.01 0.1
1
10 100 1k 10k 100k 1M 10M 100M
100
1k
10k 100k
Frequency (Hz)
1M
10M
100M
Frequency (Hz)
C024
VO = 10 mVPP
图 8. Open-Loop Output Impedance vs Frequency
图 7. Open-Loop Gain and Phase vs Frequency
140
120
100
80
140
120
100
80
60
60
40
40
PSRR+
PSRR-
20
20
0
0
1
10
100
1k
10k 100k 1M
10M 100M
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
100M
Frequency (Hz)
C025
图 10. Power-Supply Rejection Ratio vs Frequency
图 9. Common-Mode Rejection Ratio vs Frequency
5
60
55
50
45
40
35
30
25
20
15
10
Riso = 0 ꢀ, 5.5 V
Riso = 25 ꢀ, 5.5 V
Riso = 0 ꢀ, 2.7 V
Riso = 25 ꢀ, 2.7 V
Riso = 10 ꢀ, 5.5 V
Riso = 50 ꢀ, 5.5 V
Riso = 10 ꢀ, 2.7 V
Riso = 50 ꢀ, 2.7 V
0
œ5
Riso = 10 ꢀ
Riso = 25 ꢀ
Riso = 50 ꢀ
œ10
œ15
100k
1M
10M
100M
10
100
1000
10000
Frequency (Hz)
Load Capacitance (pF)
C024
C027
G = 1, CLOAD = 1.2 nF
G = 1, VO = 10 mVPP
图 11. Series Resistance for Capacitive Load Stability
图 12. Overshoot vs Capacitive Load, G = 1
10
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Typical Characteristics (接下页)
at TA = 25°C, V+ = 5 V, V– = 0 V, VCOM = VO = 2.5 V, gain (G) = 2, RF = 1 kΩ, CF= 2.7 pF, CLOAD= 20 pF, and RLOAD = 2 kΩ
connected to 2.5 V (unless otherwise noted)
50
45
40
35
30
25
20
15
10
5
0
œ20
Riso = 0 ꢀ, 5.5 V
Riso = 25 ꢀ, 5.5 V
Riso = 0 ꢀ, 2.7 V
Riso = 25 ꢀ, 2.7 V
Riso = 10 ꢀ, 5.5 V
Riso = 50 ꢀ, 5.5 V
Riso = 10 ꢀ, 2.7 V
Riso = 50 ꢀ, 2.7 V
HD2, Gain = 1
HD3, Gain = 1
HD2, Gain = 2
HD3, Gain = 2
œ40
œ60
œ80
œ100
œ120
œ140
œ160
œ180
0
10
100
1000
10000
1k
10k
100k
1M
Load Capacitance (pF)
Input Frequency (Hz)
C027
C010
G = –1, VO = 10 mVPP
VS = 5.5 V, VO = 2 VPP, RLOAD = 600 Ω
图 13. Overshoot vs Capacitive Load, G = –1
图 14. Distortion vs Frequency for Various Gains
0
œ20
0
HD2, Vs = 5.5 V
HD3, Vs = 5.5 V
HD2, Vs = 3.3 V
HD3, Vs = 3.3 V
HD2, Vs = 5.5 V
HD3, Vs = 5.5 V
HD2, Vs = 3.3 V
HD3, Vs = 3.3 V
œ20
œ40
œ40
œ60
œ60
œ80
œ80
œ100
œ120
œ140
œ160
œ180
œ100
œ120
œ140
œ160
1k
10k
100k
1M
1k
10k
100k
1M
Input Frequency (Hz)
Input Frequency (Hz)
C010
C010
G = 1, VO = 2 VPP, RLOAD = 600 Ω
G = 2, VO = 2 VPP, RLOAD = 600 Ω
图 15. Distortion vs Frequency for Various Power Supplies
图 16. Distortion vs Frequency for Various Power Supplies
0
0
f = 1 kHz
2 kꢀ
œ20
œ20
f = 10 kHz
1 kꢀ
f = 100 kHz
œ40
œ40
600 ꢀ
f = 1 MHz
œ60
œ60
œ80
œ80
œ100
œ120
œ140
œ160
œ100
œ120
œ140
œ160
1
2
3
4
1k
10k
100k
1M
Output Voltage (VPP
)
Input Frequency (Hz)
C013
C010
G = 1, RLOAD = 600 Ω
G = 1, VO = 2 VPP , RLOAD = 600 Ω
图 17. Total Harmonic Distortion vs Output Voltage for
图 18. Total Harmonic Distortion vs Frequency for Various
Various Frequencies
Loads
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Typical Characteristics (接下页)
at TA = 25°C, V+ = 5 V, V– = 0 V, VCOM = VO = 2.5 V, gain (G) = 2, RF = 1 kΩ, CF= 2.7 pF, CLOAD= 20 pF, and RLOAD = 2 kΩ
connected to 2.5 V (unless otherwise noted)
1000
100
10
1000
100
10
1
1
0.1
1
10
100
1k
10k
100k
0.1
1
10
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
C015
C015
图 19. Voltage Noise Density vs Frequency
图 20. Current Noise Density vs Frequency
-80
-100
-120
-140
-160
-180
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
Time (1 s/div)
C020
图 22. 0.1-Hz to 10-Hz Voltage Noise
图 21. Crosstalk vs Frequency
6
5
4
3
2
1
0
180
160
140
120
100
80
VS = 5 V
VS = 3.3 V
Rising, Gain = 1
Falling, Gain = 1
Rising, Gain = 2
Falling, Gain = 2
60
40
20
0
0
1
2
3
4
1k
10k
100k
1M
Frequency (Hz)
10M
100M
1G
Output Voltage Step (V)
C018
图 24. Maximum Output Voltage vs Frequency
图 23. Slew Rate vs Output Step Size
12
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Typical Characteristics (接下页)
at TA = 25°C, V+ = 5 V, V– = 0 V, VCOM = VO = 2.5 V, gain (G) = 2, RF = 1 kΩ, CF= 2.7 pF, CLOAD= 20 pF, and RLOAD = 2 kΩ
connected to 2.5 V (unless otherwise noted)
Time (200 ns/div)
Time (200 ns/div)
C020
C019
G = 1, VO = 4-V step
G = –1, VO = 4-V step
图 25. Large-Signal Pulse Response
图 26. Large-Signal Pulse Response
Time (200 ns/div)
Time (200 ns/div)
C029
C029
G = 1, VO = 10-mV step
G = –1, VO = 10-mV step
图 27. Small-Signal Pulse Response
图 28. Small-Signal Pulse Response
200
150
100
50
200
150
100
50
16-bit settling
16-bit settling
0
0
œ50
œ100
œ150
œ200
œ50
œ100
œ150
œ200
16-bit settling
16-bit settling
0
200
400
600
800
1000
0
200
400
600
800
1000
Time (ns)
Time (ns)
C032
C032
VO = 3.6-V step at t = 0 s
VO = 3.6-V step at t = 0 s
图 29. 16-Bit Negative Settling Time
图 30. 16-Bit Positive Settling Time
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Typical Characteristics (接下页)
at TA = 25°C, V+ = 5 V, V– = 0 V, VCOM = VO = 2.5 V, gain (G) = 2, RF = 1 kΩ, CF= 2.7 pF, CLOAD= 20 pF, and RLOAD = 2 kΩ
connected to 2.5 V (unless otherwise noted)
4
0.8
0.6
0.4
0.2
0.0
-0.2
4
3
2
1
0
3
2
1
0
œ1
œ2
œ3
œ4
Input
Input
Output
Output
-1
Time (200 µs/div)
Time (100 ns/div)
C031
C021
VS = ±2.75 V, G = 1
VS = ±2.75 V, G = 5
图 31. No Phase Reversal
图 32. Positive Overload Recovery
20
15
10
5
0.2
0.0
1
Input
Output
0
-0.2
-0.4
-0.6
-0.8
-1
-2
-3
0
-4
Time (100 ns/div)
C021
Offset Voltage (µV)
C013
VS = ±2.75 V, G = 5
Distribution taken from 3139 amplifiers, TA = 25°C
图 34. Input Offset Voltage Distribution
图 33. Negative Overload Recovery
20
15
10
5
20
15
10
5
0
0
Offset Voltage (µV)
Offset Voltage (µV)
C013
C013
Distribution taken from 80 amplifiers, TA = 125°C
Distribution taken from 80 amplifiers, TA = –40°C
图 35. Input Offset Voltage Distribution
图 36. Input Offset Voltage Distribution
14
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ZHCSF85A –JULY 2016–REVISED DECEMBER 2019
Typical Characteristics (接下页)
at TA = 25°C, V+ = 5 V, V– = 0 V, VCOM = VO = 2.5 V, gain (G) = 2, RF = 1 kΩ, CF= 2.7 pF, CLOAD= 20 pF, and RLOAD = 2 kΩ
connected to 2.5 V (unless otherwise noted)
30
25
20
15
10
5
35
30
25
20
15
10
5
0
0
Input Bias Current (µA)
Offset Voltage Drift (µV/°C)
C013
C013
Distribution taken from 75 amplifiers, TA = –40°C to +125°C
Distribution taken from 3139 amplifiers
图 37. Input Offset Voltage Drift Distribution
图 38. Input Bias Current Distribution
5
30
25
20
15
10
5
IB -
IB+
4
3
2
1
0
0
œ75 œ50 œ25
0
25
50
75
100 125 150
Temperature (°C)
C001
Input Offset Current (nA)
C013
Distribution taken from 3139 amplifiers
图 40. Input Offset Current Distribution
图 39. Input Bias Current vs Temperature
1000
100
10
30
20
VS
=
2.75 V, (Vœ) ≤ VCM ≤ (V+) œ 1.15
10
0
VS
= 1.35 V, (Vœ) ≤ VCM ≤ (V+) œ 1.15 V
œ10
œ20
œ30
1
œ75 œ50 œ25
0
25
50
75
100 125 150
œ75 œ50 œ25
0
25
50
75
100 125 150
Temperature (°C)
Temperature (°C)
C001
C001
图 41. Input Offset Current vs Temperature
图 42. Common-Mode Rejection Ratio vs Temperature
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Typical Characteristics (接下页)
at TA = 25°C, V+ = 5 V, V– = 0 V, VCOM = VO = 2.5 V, gain (G) = 2, RF = 1 kΩ, CF= 2.7 pF, CLOAD= 20 pF, and RLOAD = 2 kΩ
connected to 2.5 V (unless otherwise noted)
30
20
10
0
3.0
2.0
VS = 1.35 V
1.0
0.0
VS = 2.5 V
-10
-20
-30
œ1.0
œ2.0
œ3.0
œ75 œ50 œ25
0
25
50
75
100 125 150
œ75 œ50 œ25
0
25
50
75
100 125 150
Temperature (°C)
Temperature (°C)
C001
C001
2.7 V ≤ VS ≤ 5.5 V
RLOAD = 10 kΩ
图 43. Power-Supply Rejection Ratio vs Temperature
图 44. Open-Loop Gain vs Temperature With 10-kΩ Load
5.0
4.0
3.0
2.0
1
0
œ1
œ2
œ3
œ4
œ5
VS = 1.35 V
1.0
0.0
œ1.0
VS = 2.5 V
œ2.0
œ3.0
œ4.0
œ5.0
œ75 œ50 œ25
0
25
50
75
100 125 150
œ4
œ2
0
VCM (V)
2
4
Temperature (°C)
C001
C001
RLOAD = 600 Ω
VS = ±2.5 V
图 45. Open-Loop Gain vs Temperature With 600-Ω Load
图 46. Input Bias Current vs Input Common-Mode Voltage
50
40
50
30
25
20
10
VCM = œ2.5 V
0
0
VCM = 1.35 V
œ10
œ20
œ25
œ30
œ40
œ50
VS
=
2.75 V
2.6
VS
= 1.35 V
œ50
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.8
œ3
œ2
œ1
0
1
2
VSUPPLY (V)
VCM (V)
C001
C001
6 typical units shown, VS = ±1.35 V to ±2.75 V
6 typical units shown, VS = ±2.5 V
图 47. Input Offset Voltage vs Power-Supply Voltage
图 48. Input Offset Voltage vs Common-Mode Voltage
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Typical Characteristics (接下页)
at TA = 25°C, V+ = 5 V, V– = 0 V, VCOM = VO = 2.5 V, gain (G) = 2, RF = 1 kΩ, CF= 2.7 pF, CLOAD= 20 pF, and RLOAD = 2 kΩ
connected to 2.5 V (unless otherwise noted)
3
200
180
160
140
120
100
80
25°C
2
œ40°C
ISC, Sink
1
125°C
0
ISC, Source
-1
-2
-3
125°C
œ40°C
25°C
60
œ75 œ50 œ25
0
25
50
75
100 125 150
0
20
40
60
80 100 120 140 160 180 200
Temperature (°C)
IO (mA)
C001
C001
图 50. Short-Circuit Current vs Temperature
图 49. Output Voltage vs Output Current
3
2.5
2
3
2.5
2
VS
= 2.5 V
VS
= 1.35 V
1.5
1
1.5
1
0.5
0
0.5
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
œ75 œ50 œ25
0
25
50
75
100 125 150
Supply Voltage (V)
Temperature (°C)
C001
C001
图 51. Quiescent Current vs Power-Supply Voltage
图 52. Quiescent Current vs Temperature
3
2.5
2
1.5
1
0.5
0
-0.5
-1
-1.5
-2
-2.5
-3
0
0.2
0.4
0.6
Time (s)
0.8
1
1.2
D001
Powered on at t = 0 s, PCB dimensions: 4 in2, 2 layer, FR4
图 53. Warm-Up Time
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7 Parameter Measurement Information
7.1 DC Parameter Measurements
The circuit shown in 图 54 measures the dc input offset related parameters of the OPA2626. Input offset voltage,
power-supply rejection ratio, common-mode rejection ratio, and open-loop gain can be measured with this circuit.
The basic test procedure requires setting the inputs (the power-supply voltage, VS, and the common-mode
voltage, VCM), to the desired values. VO is set to the desired value by adjusting the loop-drive voltage while
measuring VO. After all inputs are configured, measure the input offset at the VX measurement point. Calculate
the input offset voltage by dividing the measured result by 101. Changing the voltages on the various inputs
changes the input offset voltage. The input parameters can be measured according to the relationships illustrated
in 公式 1 through 公式 5.
RCOMP = 1 kꢀ
CCOMP = 0.1 mF
RB = 1.26 kꢀ
+
Loop
Drive
30 V
œ
V+
VX
+
VOS
RA = 12.6 ꢀ
+
RIN = 12.6 ꢀ
-30 V
VO
RLOAD
V-
+
VCM
œ
图 54. DC-Parameters Measurement Circuit
VX
VOS
=
101
(1)
(2)
(3)
(4)
(5)
DVOS
DTemperature
DVOS
DVSUPPLY
DVOS
DVCM
VOSDrift
=
PSRR =
CMRR =
DVO
DVOS
AOL =
18
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ZHCSF85A –JULY 2016–REVISED DECEMBER 2019
7.2 Transient Parameter Measurements
The circuit shown in 图 55 measures the transient response of the OPA2626. Configure V+, V–, RISO, RLOAD, and
CLOAD as desired. Monitor the input and output voltages on an oscilloscope or other signal analyzer. Use this
circuit to measure large-signal and small-signal transient response, slew rate, overshoot, and capacitive-load
stability.
V+
RISO
+
O-Scope
CLOAD
V-
RLOAD
+
Input
œ
图 55. Pulse-Response Measurement Circuit
7.3 AC Parameter Measurements
The circuit shown in 图 56 measures the ac parameters of the OPA2626. Configure V+, V–, and CLOAD as
desired. The THS4271 family is used to buffer the input and output of the OPA2626 to prevent loading by the
gain phase analyzer. Monitor the input and output voltages on a gain phase analyzer. Use this circuit to measure
the gain bandwidth product, and open-loop gain versus frequency versus capacitive load.
249 ꢀ
249 ꢀ
50 ꢀ
+
Gain/Phase
Analyzer
249 ꢀ
249 ꢀ
50 ꢀ
1 kꢀ
1 kꢀ
+
+
CLOAD
图 56. AC-Parameters Measurement Circuit
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7.4 Noise Parameter Measurements
The circuit shown in 图 57 measures the voltage noise of the OPA2626. Configure V+, V–, and CLOAD as desired.
10 ꢀ
1 kꢀ
Spectrum
Analyzer
+
CLOAD
图 57. Voltage Noise Measurement Circuit
The circuit shown in 图 58 measures the current noise of the OPA2626. Configure V+, V– and CLOAD as desired.
Spectrum
Analyzer
+
CLOAD
100 kꢀ
图 58. Current Noise Measurement Circuit
The circuit shown in 图 59 measures the 0.1-Hz to 10-Hz voltage noise of the OPA2626. Configure V+, V–, and
CLOAD as desired.
0.1 Hz to 10 Hz
Active Bandpass Filter
10 ꢀ
1 kꢀ
O-Scope
+
40 db/dec
-80 db/dec
CLOAD
图 59. 0.1-Hz to 10-Hz Voltage-Noise Measurement Circuit
20
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8 Detailed Description
8.1 Overview
The OPA2626 is a fast-settling, high slew rate, high-bandwidth, voltage-feedback operational amplifier. Low
offset and low offset drift combine with the superior dynamic performance and low output impedance of this
device, resulting in an amplifier suited for driving 16-bit and 18-bit SAR ADCs, and buffering precision voltage
references in industrial applications. The OPA2626 includes low-noise input, slew boost, and rail-to-rail output
stages.
8.2 Functional Block Diagram
V+
Bias
+IN
Common
Mode
Feedback
Low Noise Input
Stage
Slew
Boost
Rail-to-Rail
Output Stage
OUT
-IN
Frequency
Compensation
Network
V-
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8.3 Feature Description
8.3.1 SAR ADC Driver
The OPA2626 is designed to drive precision (16-bit and 18-bit) SAR ADCs at sample rates up to 1 MSPS. The
combination of low output impedance, low THD, low noise, and fast settling time make the OPA2626 the ideal
choice for driving both the SAR ADC inputs, as well as the reference input to the ADC. Internal slew boost
circuitry increases the slew rate as a function of the input signal magnitude, resulting in settling from a 4-V step
input to 16-bit levels within 280 ns. Low output impedance (1 Ω at 1 MHz) ensures capacitive load stability with
minimal overshoot.
8.3.2 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress
(EOS). These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the
output pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly. A good understanding of this basic ESD
circuitry and how the ESD circuitry relates to an electrical overstress event is helpful. 图 60 provides a diagram of
the ESD circuits contained in the OPA2626. The ESD protection circuitry involves several current-steering diodes
connected from the input and output pins and routed back to the internal power-supply lines, where the diodes
meet at an absorption device or the power-supply ESD cell, internal to the operational amplifier. This protection
circuitry is intended to remain inactive during normal circuit operation.
V+
Power Supply
ESD Cell
30 O
+IN
+
–
30 O
OUT
– IN
V–
图 60. Simplified ESD Circuit
22
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8.4 Device Functional Modes
The OPA2626 has a single functional mode and is operational when the power supply voltage, VS, is between
2.7 V (±1.35 V) and 5.5 V (±2.75 V).
8.4.1 High-Drive Mode
The OPA2626 has a 120-MHz gain bandwidth, 2.5-nV/√Hz input-referred noise, and consumes 2 mA of
quiescent current. Additionally, the OPA2626 has an offset voltage of 100 µV (maximum) and an offset voltage
drift of 1 µV/°C (typical). This combination of high precision, high speed, and low noise makes this device
suitable for use as an input driver for high-precision, high-throughput SAR ADCs such as the ADS88xx family of
SAR ADCs, as illustrated in 图 61.
9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The OPA2626 consists of precision, high-speed, voltage-feedback operational amplifiers. Fast settling to 16-bit
and 18-bit levels, low THD, and low noise make the OPA2626 suitable for driving SAR ADC inputs and buffering
precision voltage references. With a wide power-supply voltage range from 2.7 V to 5.5 V, and operating from
–40°C to +125°C, the OPA2626 is suitable for a variety of high-speed, industrial applications. The following
sections show application information for the OPA2626. For simplicity, power-supply decoupling capacitors are
not shown in these diagrams.
9.2 Typical Applications
9.2.1 Single-Supply, 16-Bit, 1-MSPS SAR ADC Driver
1 kO
1 kO
5 V
RFLT
VREF
3.3 V
4.7 O
+
VREF / 4
OPA626
REF
AVDD
10 nF
CFLT
ADS8860
GND
4.7 O
RFLT
图 61. Single-Supply, 16-Bit, 1-MSPS SAR ADC Driver
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Typical Applications (接下页)
9.2.1.1 Design Requirements
A SAR ADC, such as the ADS8860 device, uses sampling capacitors on the data converter input. During the
signal acquisition phase, these sampling capacitors are connected to the ADC analog input terminals AINP and
AINN (pins 3 and 4), through a set of switches. After the acquisition period has elapsed, the internal sampling
capacitors are disconnected from the input terminals (pins 3 and 4) and connected to the ADC input through a
second set of switches, during this period the ADC is performing the analog-to-digital conversion. 图 62 shows
this architecture.
SAR ADC
RSW
AINP
CS/H
RSW
CS/H
AINN
图 62. Simplified SAR ADC Input
The SAR ADC inputs and sampling capacitors must be driven by the OPA2626 to 16-bit levels within the
acquisition time of the ADC. For the example illustrated in 图 61, the OPA2626 is used to drive the ADS8860 at a
sample rate of 1 MSPS.
9.2.1.2 Detailed Design Procedure
The circuit illustrated in 图 61 consists of the SAR ADC driver, a low-pass filter, and the SAR ADC. The SAR
ADC driver circuit consists of an OPA2626 configured in an inverting gain of 1. The filter consists of RFLT and
CFLT, connected between the OPA2626 output and the ADS8860 input. Selecting the proper values for each of
these passive components is critical to obtain the best performance from the ADC. Capacitor CFLT serves as a
charge reservoir, providing the necessary charge to the ADC sampling capacitors. The dynamic load presented
by the ADC creates a glitch on the filter capacitor, CFLT. To minimize the magnitude of this glitch, choose a value
for CFLT large enough to maintain a glitch amplitude of less than 100 mV. Maintaining such a low glitch amplitude
at the amplifier output makes sure that the amplifier remains in the linear operating region, and results in a
minimum settling time. Using 公式 6, a 10-nF capacitor is selected for CFLT
.
CFLT í 15ìCSH
(6)
Connecting a 10-nF capacitor directly to the OPA2626 output degrades the OPA2626 phase margin and results
in stability and settling-time problems. To properly drive the 10-nF capacitor, use a series resistor (RFLT) to
isolate the capacitor, CFLT, from the OPA2626. RFLT must be sized based upon several constraints. To
determination a suitable value for RFLT, consider the impact upon the THD resulting from the voltage divider
effect from RFLT reacting with the switch resistance (RSW) of the ADC input circuit, as well as the impact of the
output impedance upon amplifier stability. In this example, 4.7-Ω resistors are selected. In this design example,
图 13 can be used to estimate a suitable value for RISO. RISO represents the total resistance in series with CFLT
,
and in this example is equivalent to 2 × RFLT
.
For step-by-step design procedure, circuit schematics, bill of materials, printed circuit board (PCB) files, simulation results, and test results,
refer to the Power-optimized 16-bit 1MSPS Data Acquisition Block for Lowest Distortion and Noise Reference Design reference guide.
24
版权 © 2016–2019, Texas Instruments Incorporated
OPA2626
www.ti.com.cn
ZHCSF85A –JULY 2016–REVISED DECEMBER 2019
9.2.1.3 Application Curve
图 63 shows the performance of the circuit in 图 61.
0
THD = -110.8 dBc
-25
-50
-75
SNR = 91.88 dB
SINAD = 91.86 dB
ENOB = 14.97
-115.91 dBc (Third Harmonic)
-100
-125
-150
-175
0
50 100 150 200 250 300 350 400 450 500
Frequency (kHz)
4096-point FFT at 1 MSPS, fIN = 10 kHz , VIN = 1.5 VRMS
图 63. ADC Output FFT for 图 61
版权 © 2016–2019, Texas Instruments Incorporated
25
OPA2626
ZHCSF85A –JULY 2016–REVISED DECEMBER 2019
www.ti.com.cn
9.2.2 Single-Supply, 16-Bit, 1-MSPS, Multiplexed, SAR ADC Driver
In order to operate a high-resolution, 16-bit ADC at its maximum throughput, the full-scale voltage step must
settle to better than 16-bit accuracy at the ADC inputs within the minimum specified acquisition time (tACQ). This
settling imposes very stringent requirements on the driver amplifier in terms of large-signal bandwidth, slew rate,
and settling time. 图 64 shows a typical multiplexed ADC driver application using the OPA2626.
1.5 pF
8 kꢀ
2 kꢀ
5 V
VREF
5 V
RFLT
4.5 V
3.3 V
12.4 ꢀ
Mux
10 ꢀ
10 ꢀ
+
OPA320
REF
AVDD
+
1 nF
CFLT
TS5A3159
ADS8860
GND
100 pF
22 µF
Input
Voltage
12.4 ꢀ
RFLT
图 64. Single-Supply, 16-Bit, 1-MSPS, Multiplexed, SAR ADC Driver
9.2.2.1 Design Requirements
To optimize this circuit for performance, this design does not allow any large signal input transients at the driver
circuit inputs for a small quiet-time period (tQT) towards the end of the previous conversion. The input step
voltage can appear anytime from the beginning of conversion (CONVST rising edge) until the elapse of a half
cycle time (0.5 × tCYC). This timing constraint on the input step allows a minimum settling time of (tQT + tACQ) for
the ADC input to settle within the required accuracy, in the worst-case scenario. tQT + tACQ is the total time in
which the output of the amplifier has to slew and settle within the required accuracy before the next conversion
starts. 图 65 shows this timing sequence.
Transients Allowed
No Transients Allowed
CONVST
0.5 x tCYC_MIN = 500 ns
tQT
tACQ
Slewing
Settling
VIN
tCYC_MIN = 1 µs
Conversion
Sampling
图 65. Timing Diagram for Input Signals
26
版权 © 2016–2019, Texas Instruments Incorporated
OPA2626
www.ti.com.cn
ZHCSF85A –JULY 2016–REVISED DECEMBER 2019
9.2.2.2 Detailed Design Procedure
An ADC input driver circuit consists of two parts: a driving amplifier and a fly-wheel RC filter. The amplifier is
used for signal conditioning of the input voltage and the low output impedance provides a buffer between the
signal source and the ADC input. The RC filter helps attenuate the sampling charge-injection from the switched-
capacitor input stage of the ADC and acts as an antialiasing filter to band-limit the wideband noise contributed by
the front-end circuit. The design of the ADC input driver involves optimizing the bandwidth of the circuit, driven by
the following requirements:
•
The RFLT and CFLT filter bandwidth must be low to band-limit the noise fed into the input of the ADC, thereby
increasing the signal-to-noise ratio (SNR) of the system
•
The overall system bandwidth must be large enough to accommodate optimal settling of the input signal at
the ADC input before the conversion starts
CFLT is chosen based upon 公式 7. CFLT is chosen to be 1 nF.
CFLT í 15ìCSH
(7)
Connecting a 1-nF capacitor directly to the output of the OPA2626 degrades the OPA2626 phase margin and
results in stability and settling time problems. To properly drive the 1-nF capacitor, a series resistor, RFLT, is used
to isolate the capacitor, CFLT, from the OPA2626. RFLT must be sized based upon several constraints. To
determination a suitable value for RFLT, the system designer must consider the impact upon the THD resulting
from the voltage divider effect from RFLT reacting with the switch resistance, RSW, of the ADC input circuit as well
as the impact of the output impedance upon amplifier stability. In this example 12.4-Ω resistors are selected. In
this design example, 图 12 can be used to estimate a suitable value for RISO. RISO represents the total resistance
in series with CFLT, which in this example is equivalent to 2 × RFLT
.
For step-by-step design procedure, circuit schematics, bill of materials, printed circuit board (PCB) files, simulation results, and test
results, refer to the 18-Bit Data Acquisition (DAQ) Block Optimized for 1-μs Full-Scale Step Response reference guide.
9.2.2.3 Application Curves
图 66 and 图 67 show the performance of the circuit in 图 64.
2
1.5
1
2
1.5
1
0.5
0
0.5
0
-0.5
-1
-0.5
-1
-1.5
-2
-1.5
-2
0
500
1000
Time (ns)
1500
2000
0
500
1000
Time (ns)
1500
2000
图 66. Positive Transient Response for 图 64
图 67. Negative Transient Response for 图 64
版权 © 2016–2019, Texas Instruments Incorporated
27
OPA2626
ZHCSF85A –JULY 2016–REVISED DECEMBER 2019
www.ti.com.cn
10 Power Supply Recommendations
The OPA2626 is specified for operation from 2.7 V to 5.5 V (±1.35 V to ±2.75 V); many specifications apply from
–40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in the Typical Characteristics section. Place bypass capacitors close to the power-
supply pins to reduce errors coupling in from noisy or high-impedance power supplies. For more detailed
information on bypass capacitor placement, see the Layout section.
CAUTION
Supply voltages larger than 6 V can cause permanent damage to the device. See the
Absolute Maximum Ratings section.
11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
•
Use bypass capacitors to reduce the noise coupled from the power supply. Connect low ESR, ceramic,
bypass capacitors between the power-supply pins (V+ and V–) and the ground plane. Place the bypass
capacitors as close to the device as possible with the 100-nF capacitor closest to the device, as indicated in
图 68. For single-supply applications, bypass capacitors on the V– pin are not required.
•
Separate grounding for analog and digital portions of the circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup. Make sure
to physically separate digital and analog grounds paying attention to the flow of the ground current. (For more
details, see the Circuit Board Layout Techniques chapter extract.)
•
In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If the traces cannot be kept separate, crossing the sensitive trace perpendicular is better as
opposed to in parallel with the noisy trace.
•
•
Minimize parasitic coupling between +IN and OUT for best ac performance.
Place the external components as close to the device as possible. As illustrated in 图 68, keeping RF, CF,
and RG close to the inverting input minimizes parasitic capacitance.
•
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
•
•
Cleaning the PCB following board assembly is recommended for best performance.
Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, bake the PCB assembly to remove moisture
introduced into the device packaging during the cleaning process. A low-temperature, post-cleaning bake at
85°C for 30 minutes is sufficient for most circumstances.
28
版权 © 2016–2019, Texas Instruments Incorporated
OPA2626
www.ti.com.cn
ZHCSF85A –JULY 2016–REVISED DECEMBER 2019
11.2 Layout Example
Place components
close to device and to
each other to reduce
parasitic errors.
OUT 1
Use low-ESR,
ceramic bypass
capacitor . Place as
close to the device
as possible .
VS+
GND
OUT1
V+
RF
OUT 2
GND
IN1œ
IN1+
Vœ
OUT2
IN2œ
IN2+
RF
RG
RG
VIN 1
GND
VIN 2
Keep input traces short
and run the input traces
as far away from
the supply lines
Use low-ESR,
GND
ceramic bypass
capacitor . Place as
close to the device
as possible .
VSœ
Ground (GND) plane on another layer
as possible .
图 68. PCB Layout Example
版权 © 2016–2019, Texas Instruments Incorporated
29
OPA2626
ZHCSF85A –JULY 2016–REVISED DECEMBER 2019
www.ti.com.cn
12 器件和文档支持
12.1 器件支持
12.1.1 开发支持
12.1.1.1 TINA-TI™（免费软件下载）
TINA™是一款简单、功能强大且易于使用的电路仿真程序，此程序基于 SPICE 引擎。TINA-TI 是 TINA 软件的一
款免费全功能版本，除了一系列无源和有源模型外，此版本软件还预先载入了一个宏模型库。TINA-TI 提供所有传
统的 SPICE 直流、瞬态和频域分析，以及其他设计功能。
TINA-TI 可从 Analog eLab Design Center（模拟电子实验室设计中心）免费下载，它提供全面的后续处理能力，
使得用户能够以多种方式形成结果。虚拟仪器提供选择输入波形和探测电路节点、电压和波形的功能，从而创建一
个动态的快速入门工具。
12.1.1.2 TI 高精度设计
欲获取 TI 高精度设计，请访问 http://www.ti.com.cn/ww/analog/precision-designs/。TI 高精度设计是由 TI 公司高
精度模拟 应用 专家创建的模拟解决方案，提供了许多实用电路的工作原理、组件选择、仿真、完整印刷电路板
(PCB) 电路原理图和布局布线、物料清单以及性能测量结果。
12.2 文档支持
12.2.1 相关文档
请参阅如下相关文档：
•
•
•
•
•
•
德州仪器 (TI)，《快速稳定 16 位 1MSPS 多路复用器数据采集参考设计》 设计指南
德州仪器 (TI)，《针对最低失真和噪声进行功耗优化的 16 位 1MSPS 数据采集块参考设计》 参考指南
德州仪器 (TI)，《经优化可实现 1μs 满量程阶跃响应的 18 位数据采集 (DAQ) 块》 参考指南
德州仪器 (TI)，《电路板布局技巧》 章节摘录
德州仪器 (TI)，《THS427x 低噪声、高压摆率、单位增益稳定电压反馈放大器》 数据表
德州仪器 (TI)，《ADS8860 16 位、1MSPS、串行接口、微功耗、微型、单端输入、SAR 模数转换器》 数据表
12.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.4 社区资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 商标
E2E is a trademark of Texas Instruments.
TINA-TI is a trademark of Texas Instruments, Inc and DesignSoft, Inc.
TINA is a trademark of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
12.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
30
版权 © 2016–2019, Texas Instruments Incorporated
OPA2626
www.ti.com.cn
ZHCSF85A –JULY 2016–REVISED DECEMBER 2019
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2016–2019, Texas Instruments Incorporated
31
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2020 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA2626IDGKR
OPA2626IDGKT
ACTIVE
ACTIVE
VSSOP
VSSOP
DGK
DGK
8
8
2500 RoHS & Green
250 RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
16R6
16R6
NIPDAUAG
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jul-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA2626IDGKR
OPA2626IDGKT
VSSOP
VSSOP
DGK
DGK
8
8
2500
250
330.0
330.0
12.4
12.4
5.3
5.3
3.4
3.4
1.4
1.4
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jul-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA2626IDGKR
OPA2626IDGKT
VSSOP
VSSOP
DGK
DGK
8
8
2500
250
366.0
366.0
364.0
364.0
50.0
50.0
Pack Materials-Page 2
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2020 德州仪器半导体技术（上海）有限公司
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