OPA2863A [TI]
双路、高精度、低功耗、105MHz、12V RRIO 电压反馈放大器;
| 型号： | OPA2863A |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 双路、高精度、低功耗、105MHz、12V RRIO 电压反馈放大器 放大器 |
| 文件： | 总31页 (文件大小：1697K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OPA2863A
ZHCSOS5B –MAY 2022 –REVISED DECEMBER 2022
OPAx863A 105MHz、轨到轨输入和输出高精度放大器
1 特性
3 说明
• 增益带宽积：50 MHz
• 高精度
OPAx863A 器件是具有轨到轨输入和输出的单位增益
稳定、电压反馈、低功耗运算放大器，通过封装修整可
提供高精度性能、95μV 的最大输入失调电压和
1.2μV/℃ 的温漂，从而在整个温度范围内进行高精度
测量。
– 输入失调电压：95 µV（最大值）
– 失调漂移：1.2 μV/°C（最大值）
• 低功耗
– 静态电流：800 µA/通道（典型值）
– 电源电压：2.7V 至12.6V
• 输入电压噪声：6.3 nV/√Hz
• 压摆率：100V/µs
• 轨到轨输入和输出
• HD2/HD3：在20 kHz (2VPP) 时为–129dBc/–
138dBc
OPAx863A 器件每通道仅消耗 800µA，可提供 50MHz
的增益带宽积、100V/µs 的压摆率和 6.3nV/√Hz 的电
压噪声密度。具有 2.7V 电源电压的轨至轨输入级在便
携式电池供电型应用中非常有用。轨到轨输入级可在整
个输入共模电压范围内很好地适应增益带宽积和噪声，
从而在宽输入动态范围内实现出色的性能。
OPAx863A 器件包括过载功率限制功能，可限制输出
饱和时 IQ 的增加，从而避免电池供电的功率敏感型系
统中出现过度功率耗散。输出级具有短路保护功能，使
得该器件适用于恶劣的环境。
• 工作温度范围：
–40°C 至+125°C
• 其他特性：
– 过载功率限制
– 输出短路保护
封装信息(1)(3)
封装尺寸（标称值）
器件型号
OPA863A
OPA2863A
封装
2 应用
DBV（SOT23，5）
2.90mm × 1.60mm
(2)
• 低功耗SAR 和Δ-ΣADC 驱动器
• ADC 基准缓冲器
• 低侧电流感测
DSN（USON，10） 3.00mm × 3.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
(2) 预发布封装。
(3) 请参阅器件比较表
• 光电二极管TIA 接口
• 电感式传感
• 电池供电仪表
• 增益和有源滤波器级
5V
20
16
12
8
REF1933
3.3 V
Reference
3.3V
CFILT
RF
RG
3.3V
AVDD
–
RS
Sensor
OPAx863A
+
ZOUT
ADS7057
14-bit
CCB
4
2.5 MSPS
RS
0
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
Input Offset Drift (V/C)
OPAx863A 用作精密SAR ADC 输入驱动器
具有低输入失调电压漂移的高精度性能
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOSA95
OPA2863A
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ZHCSOS5B –MAY 2022 –REVISED DECEMBER 2022
Table of Contents
8.3 Feature Description...................................................20
8.4 Device Functional Modes..........................................21
9 Application and Implementation..................................22
9.1 Application Information............................................. 22
9.2 Typical Applications.................................................. 22
10 Power Supply Recommendations..............................24
11 Layout...........................................................................24
11.1 Layout Guidelines................................................... 24
11.2 Layout Example...................................................... 25
12 Device and Documentation Support..........................26
12.1 Documentation Support.......................................... 26
12.2 接收文档更新通知................................................... 26
12.3 支持资源..................................................................26
12.4 Trademarks.............................................................26
12.5 Electrostatic Discharge Caution..............................26
12.6 术语表..................................................................... 26
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions.........................5
7.4 Thermal Information....................................................5
7.5 Electrical Characteristics: VS = ±5 V ..........................6
7.6 Electrical Characteristics: VS = 3 V.............................8
7.7 Typical Characteristics: VS = ±5 V............................ 10
7.8 Typical Characteristics: VS = 3 V.............................. 15
7.9 Typical Characteristics: VS = 3 V to 10 V..................17
8 Detailed Description......................................................19
8.1 Overview...................................................................19
8.2 Functional Block Diagram.........................................19
Information.................................................................... 26
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision A (December 2022) to Revision B (December 2022)
Page
• Changed the description for the PD1 and PD2 pins from: high/floating = enabled to: high = enabled ..............3
Changes from Revision * (May 2022) to Revision A (December 2022)
Page
• 将数据表的状态从预告信息更改为“量产数据”.............................................................................................. 1
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ZHCSOS5B –MAY 2022 –REVISED DECEMBER 2022
5 Device Comparison Table
VOLTAGE NOISE
IQ / CHANNEL GBWP SLEW RATE
DEVICE
±VS (V)
AMPLIFIER DESCRIPTION
(mA)
0.80
2.7
(MHz)
(V/µs)
(nV/√Hz)
OPAx863A
LMH6643
OPAx810
OPAx837
±6.3
±6.4
50
100
6.3
17
Unity-gain stable RRIO Bipolar Amplifier
Unity-gain stable NRI/RRO Bipolar Amplifier
Unity-gain stable RRIO FET-Input Amplifier
Unity-gain stable NRI/RRO Bipolar Amplifier
65
130
±13.5
±2.7
3.6
70
200
6.3
4.7
0.6
50
105
Decompensated Gain of 6 V/V stable CMOS
Amplifier
OPAx607
±2.75
0.9
50
24
3.8
6 Pin Configuration and Functions
VOUT
VS+
5
1
2
3
VS-
VIN+
VIN-
4
图6-1. OPA863A DBV Package (Preview),
5-Pin SOT-23
(Top View)
表6-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
Power down.
Low = disabled, high = enabled
PD
I
—
VIN+
VIN–
VOUT
VS–
VS+
3
4
1
2
5
I
Noninverting input pin
Inverting input pin
I
O
P
P
Output pin
Negative power-supply pin
Positive power-supply pin
(1) I = input, O = output, and P = power.
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VOUT1
1
2
10 VS+
VIN1-
VIN1+
–
+
9
8
7
6
VOUT2
VIN2-
A
–
+
3
4
B
VS-
VIN2+
PD2
PD1
5
图6-2. OPA2863A DSN Package,
10-Pin USON with Exposed Power Pad
(Top View)
表6-2. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
Amplifier 1 power down.
Low = disabled, high = enabled
PD1
5
I
I
Amplifier 2 power down.
Low = disabled, high = enabled
PD2
6
2
3
I
I
Amplifier 1 inverting input pin
Amplifier 1 noninverting input pin
Amplifier 2 inverting input pin
Amplifier 2 noninverting input pin
Amplifier 1 output pin
VIN1–
VIN1+
VIN2–
VIN2+
VOUT1
VOUT2
VS–
8
I
7
I
1
O
O
P
P
9
Amplifier 2 output pin
4
Negative power-supply pin
Positive power-supply pin
VS+
10
Power pad. Electrically isolated from the device. Recommended connection to a
heat spreading plane, typically GND.
Power Pad
—
(1) I = input, O = output, and P = power.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
V
Supply voltage
VS– to VS+
13
1
Supply turn-on/off maximum dV/dt
V/µs
V
VI
VID
II
Input voltage
VS+ + 0.5
±1
VS– –0.5
Differential input voltage
Continuous input current(2)
Continuous output current(3)
Continuous power dissipation
Maximum junction temperature
Operating free-air temperature
Storage temperature
V
±10
mA
mA
IO
±30
See Thermal Information
150
TJ
°C
°C
°C
TA
125
150
–40
–65
Tstg
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) Continuous input current limit for both the ESD diodes to supply pins and amplifier differential input clamp diode. The differential input
clamp diode limits the voltage across it to 1 V with this continuous input current flowing through it.
(3) Long-term continuous current for electromigration limits.
7.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged device model (CDM), per JEDEC specification JESD22(2)
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.7
NOM
10
MAX
12.6
125
UNIT
V
VS+ - VS– Total supply voltage
TA Ambient temperature
25
°C
–40
7.4 Thermal Information
OPA2863A
THERMAL METRIC
DSN (USON)
10 PINS
52.4
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
41.7
Junction-to-board thermal resistance
25.5
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.6
ΨJT
YJB
25.5
RθJC(bot)
8.1
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7.5 Electrical Characteristics: VS = ±5 V
at G = 1 V/V, RF = 0 Ωfor G = 1 V/V, otherwise RF = 1 kΩ for other gains, CL = 1 pF, RL = 2 kΩreferenced to mid-supply,
input and output common-mode is at mid-supply, and TA ≅ 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
SSBW
GBWP
LSBW
Small-signal bandwidth
Gain-bandwidth product
Large-signal bandwidth
Bandwidth for 0.1-dB flatness
Slew rate
VOUT = 20 mVPP, G = 1
105
50
MHz
MHz
MHz
MHz
V/µs
ns
VOUT = 2 VPP
14
VOUT = 20 mVPP
15
SR
100
9
VOUT = 2–V step
Rise, fall time
VOUT = 200–mV step
VOUT = 2–V step
Settling time to 0.1%
50
ns
Settling time to 0.01%
70
ns
VOUT = 2–V step
Overshoot/undershoot
Overdrive recovery time
Overdrive recovery time
Second-order harmonic distortion
Third-order harmonic distortion
Second-order harmonic distortion
Third-order harmonic distortion
Input voltage noise
1
%
VOUT = 2–V step
70
ns
G = –1, 0.5 V overdrive beyond supplies
G = 1, 0.5 V overdrive beyond supplies
90
ns
HD2
HD3
HD2
HD3
eN
–129
–138
–107
–125
6.3
f = 20 kHz, VOUT = 2 VPP
f = 100 kHz, VOUT = 2 VPP
dBc
dBc
nV/√Hz
pA/√Hz
iN
Input current noise
0.5
Closed-loop output impedance
Channel-to-channel crosstalk
f = 1 MHz
0.2
Ω
f = 1 MHz, VOUT = 2 VPP
dBc
–120
DC PERFORMANCE
AOL
VOS
Open-loop voltage gain
VOUT = ±2.5 V
110
–95
–1.2
128
±10
±0.3
0.3
dB
µV
Input-referred offset voltage
Input offset voltage drift
95
1.2 µV/°C
0.73
1.2
TA = –40°C to +125°C
TA ≅ 25°C
Input bias current
µA
TA = –40°C to +85°C
TA = –40°C to +125°C
TA = –40°C to +125°C
1.6
Input bias current drift
Input offset current
±3
nA/°C
nA
-30
±10
30
INPUT
Input common-mode voltage range
Common-mode rejection ratio
VS++0.2
V
VS––0.2
CMRR
95
120
650 || 0.8
200 || 0.5
dB
VCM=VS––0.2 V to VS+ –1.6 V
Input impedance common-mode
Input impedance differential mode
MΩ|| pF
kΩ|| pF
OUTPUT
VS–+0.14
VS–+0.2
TA ≅ 25°C
VOL
Output voltage, low
Output voltage, high
V
V
VS–+0.15 VS–+0.22
TA = –40°C to +125°C
TA ≅ 25°C
VS+–0.2 VS+–0.14
VS+–0.2 VS+–0.15
VOH
TA = –40°C to +125°C
Linear output drive (sourcing/
sinking)
VOUT = ±2.5 V, ΔVOS < 1 mV(2)
23
30
45
mA
mA
Short-circuit current
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7.5 Electrical Characteristics: VS = ±5 V (continued)
at G = 1 V/V, RF = 0 Ωfor G = 1 V/V, otherwise RF = 1 kΩ for other gains, CL = 1 pF, RL = 2 kΩreferenced to mid-supply,
input and output common-mode is at mid-supply, and TA ≅ 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
800
925
TA ≈25°C
IQ
Quiescent current per amplifier
Power-supply rejection ratio
µA
dB
1040
TA = –40°C to +125°C
ΔVS = ±2 V(1)
PSRR
100
3.5
120
11
POWER DOWN
Enable voltage threshold
4.5
V
V
Specified on above VS+–0.5 V
Specified off below VS+–1.5 V
VPD ≤VS+–1.5 V
Disable voltage threshold
28
35
Power-down quiescent current per
channel
µA
VPD ≤VS+ –1.5 V, TA = –40°C to
+125°C
Power-down pin bias current
Turn-on time delay
1
8
2.5
µA
µs
µs
Turn-off time delay
3.5
AUXILIARY INPUT STAGE
Gain-bandwidth product
Input voltage noise
50
6.3
0.5
±10
0.2
MHz
nV/√Hz
pA/√Hz
μV
Input current noise
Input-referred offset voltage
95
0.6
1.3
–95
TA ≅ 25°C
Input bias current
µA
TA = –40°C to +125°C
VCM = 4.1 V to 5.2 V
ΔVS = ±0.6 V
Common-mode rejection ratio
Power supply rejection ratio
120
120
dB
dB
(1) Change in supply voltage from the default test condition with only one of the positive or negative supplies changing corresponding to
+PSRR and –PSRR.
(2) Change in input offset voltage from no-load condition.
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7.6 Electrical Characteristics: VS = 3 V
at G = 1, RF = 0 Ωfor G =1 V/V, otherwise RF = 1 kΩ for other gains, CL = 1 pF, RL = 2 kΩconnected to 1 V, input and
output VCM = 1 V, and TA ≅ 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
SSBW
GBWP
LSBW
Small-signal bandwidth
Gain-bandwidth product
Large-signal bandwidth
Bandwidth for 0.1-dB flatness
Slew rate
VOUT = 20 mVPP, G = 1
85
50
MHz
MHz
MHz
MHz
V/µs
ns
VOUT = 1 VPP
23
VOUT = 20 mVPP
VOUT = 1–V step
VOUT = 200–mV step
10
SR
53
Rise, fall time
10
Settling time to 0.1%
58
ns
%
VOUT = 1–V step
VOUT = 1–V step
Settling time to 0.01%
Overshoot
90
2
Undershoot
16
Overdrive recovery time
Overdrive recovery time
Second-order harmonic distortion
Third-order harmonic distortion
Second-order harmonic distortion
Third-order harmonic distortion
Input voltage noise
85
ns
ns
G = –1, 0.5V overdrive beyond supplies
G = 1, 0.5V overdrive beyond supplies
130
–123
–132
–109
–129
6.3
HD2
HD3
HD2
HD3
eN
f = 20 kHz, VOUT = 1 VPP
f = 100 kHz, VOUT = 1 VPP
dBc
dBc
nV/√Hz
pA/√Hz
iN
Input current noise
0.5
Closed-loop output impedance
Channel-to-channel crosstalk
f = 1 MHz
0.2
Ω
f = 1 MHz, VOUT = 1 VPP
dBc
–120
DC PERFORMANCE
AOL
VOS
Open-loop voltage gain
VOUT = 1 V to 2 V
104
–95
–1.2
123
±10
±0.3
0.3
dB
μV
Input-referred offset voltage
Input offset voltage drift
95
1.2
TA = –40°C to +125°C
TA ≅ 25°C
μV/°C
0.73
1.2
Input bias current
µA
TA = –40°C to +85°C
TA = –40°C to +125°C
TA = –40°C to +125°C
1.56
Input bias current drift
Input offset current
±3
nA/°C
nA
-30
±10
30
INPUT
Input common-mode voltage range
Common-mode rejection ratio
VS++0.2
V
VS––0.2
CMRR
92
115
360 || 0.9
200 || 0.5
dB
VCM = VS––0.2 V to VS+ –1.6 V
Input impedance common-mode
Input impedance differential mode
MΩ|| pF
kΩ|| pF
OUTPUT
VS–+ 0.13 VS–+ 0.15
VS–+ 0.13 VS–+ 0.16
TA ≅ 25°C
VOL
Output voltage, low
Output voltage, high
V
TA = –40°C to +125°C
TA ≅ 25°C
VS+–0.15 VS+–0.13
VS+–0.15 VS+–0.13
VOH
V
TA = –40°C to +125°C
Linear output drive (sourcing/
sinking)
VOUT = ±0.7 V, ΔVOS < 1 mV(2)
23
33
mA
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7.6 Electrical Characteristics: VS = 3 V (continued)
at G = 1, RF = 0 Ωfor G =1 V/V, otherwise RF = 1 kΩ for other gains, CL = 1 pF, RL = 2 kΩconnected to 1 V, input and
output VCM = 1 V, and TA ≅ 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Short-circuit current
45
mA
POWER SUPPLY
770
120
890
995
TA ≈25°C
IQ
Quiescent current per amplifier
µA
dB
TA = –40°C to +125°C
ΔVS = ±1 V(1)
PSRR
Power-supply rejection ratio
100
1.5
POWER DOWN
Enable voltage threshold
2.5
V
V
Specified on above VS+ –0.5 V
Specified off below VS+ –1.5 V
VPD ≤VS+ –1.5 V
Disable voltage threshold
8.5
20
30
Power-down quiescent current per
channel
µA
VPD ≤VS+ –1.5 V, TA = –40°C to
+125°C
Power-down pin bias current
Turn-on time delay
1
8
2.5
µA
µs
µs
Turn-off time delay
3.5
AUXILIARY INPUT STAGE
Gain-bandwidth product
Input voltage noise
50
6.3
0.5
±10
0.2
MHz
nV/√Hz
pA/√Hz
μV
Input current noise
Input-referred offset voltage
95
0.6
1.2
–95
TA ≅ 25°C
Input bias current
µA
TA = –40°C to +125°C
VCM = 2.1 V to 3.2 V
ΔVS = ±0.6 V
Common-mode rejection ratio
Power supply rejection ratio
115
115
dB
dB
(1) Change in supply voltage from the default test condition with only one of the positive or negative supplies changing corresponding to
+PSRR and –PSRR.
(2) Change in input offset voltage from no-load condition.
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7.7 Typical Characteristics: VS = ±5 V
at VS+ = 5 V, VS– = –5 V, RF = 0 Ωfor Gain = 1 V/V, otherwise RF = 1 kΩfor other gains, CL = 1 pF, RL = 2 kΩreferenced
to mid-supply, G = 1 V/V, input and output referenced to mid-supply, and TA ≅ 25°C (unless otherwise noted)
3
0
3
0
-3
-3
-6
-6
-9
-9
-12
-15
-18
-21
-12
-15
-18
-21
G = 1 V/V
G = -1 V/V
G = 2 V/V
G = 5 V/V
G = 10 V/V
RL = 2 k
RL = 500
100k
1M
10M
Frequency (Hz)
100M
100k
1M
10M
Frequency
100M
VOUT = 20 mVPP
VOUT = 20 mVPP
图7-1. Small-Signal Frequency Response vs Gain
图7-2. Small-Signal Frequency Response vs Output Load
VOUT = 20 mVPP
.
图7-3. Frequency Response vs Load Capacitance
图7-4. Frequency Response vs Output Voltage
3
-40
HD2, VOUT = 2 VPP
HD3, VOUT = 2 VPP
HD2, VOUT = 4 VPP
HD3, VOUT = 4 VPP
-60
-80
0
-3
-100
-120
-140
-160
-6
G = 1 V/V
G = 2 V/V
G = 5 V/V
G = 10 V/V
-9
100k
1M
10M
Frequency (Hz)
100M
1k
10k
100k
1M
10M
Frequency (Hz)
VOUT = 2 VPP
G = 1 V/V
图7-5. Large-Signal Frequency Response vs Gain
图7-6. Harmonic Distortion vs Frequency
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7.7 Typical Characteristics: VS = ±5 V (continued)
at VS+ = 5 V, VS– = –5 V, RF = 0 Ωfor Gain = 1 V/V, otherwise RF = 1 kΩfor other gains, CL = 1 pF, RL = 2 kΩreferenced
to mid-supply, G = 1 V/V, input and output referenced to mid-supply, and TA ≅ 25°C (unless otherwise noted)
-20
-40
0.15
HD2, G = 1 V/V
HD3, G = 1 V/V
HD2, G = 2 V/V
HD3, G = 2 V/V
0.1
-60
0.05
0
-80
-100
-120
-140
-160
-0.05
-0.1
-0.15
1k
10k
100k
1M
10M
Time (20 ns/div)
.
Frequency (Hz)
VOUT = 4 VPP
图7-8. Small-Signal Transient Response
图7-7. Harmonic Distortion vs Gain
1.25
0.75
6
4
Input
Output
2
0.25
0
-0.25
-0.75
-1.25
-2
-4
-6
Time (50 ns/div)
.
Time (100 ns/div)
Gain = 1 V/V
图7-9. Large-Signal Transient Response
图7-10. Input Overdrive Recovery
60
40
20
0
6
4
2
0
-2
-4
-6
Input x -1 V/V
Output
-20
-6 -5 -4 -3 -2 -1
0
1
2
3
4
5
6
Time (100 ns/div)
Gain = -1 V/V
Input Common-Mode Voltage (V)
Measured for 10 units
图7-11. Output Overdrive Recovery
图7-12. Input Offset Voltage vs Input Common-Mode Voltage
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7.7 Typical Characteristics: VS = ±5 V (continued)
at VS+ = 5 V, VS– = –5 V, RF = 0 Ωfor Gain = 1 V/V, otherwise RF = 1 kΩfor other gains, CL = 1 pF, RL = 2 kΩreferenced
to mid-supply, G = 1 V/V, input and output referenced to mid-supply, and TA ≅ 25°C (unless otherwise noted)
400
200
0
6
4
2
Sourcing
Sinking
0
-2
-4
-6
-200
-400
0
4
8
12
16
20
24
28
-5.5 -4.5 -3.5 -2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5
Output Current (mA)
Input Common-Mode Voltage (V)
.
.
图7-14. Output Voltage vs Load Current
图7-13. Input Bias Current vs Input Common-Mode Voltage
60
16000
12000
8000
4000
0
40
20
Sourcing
Sinking
0
-20
-40
-60
740
760
780
800
820
840
860
880
-40
-20
0
20
40
60
80
100
120
Ambient Temperature (C)
Quiescent Current per Channel (A)
Output saturated and then short-circuited to opposite supply
图7-15. Output Short-Circuit Current vs Ambient Temperature
16000
μ= 790 μA, σ= 13.8 μA
图7-16. Quiescent Current Distribution
12000
10000
8000
6000
4000
2000
0
12000
8000
4000
0
175
200
225
250
275
300
325
350
-40
-30
-20
-10
0
10
20
30
40
Input Bias Current (nA)
Input Offset Voltage (V)
μ= 265 nA, σ= 18.6 nA
μ= 0.1 μV, σ= 9.1 μV
图7-18. Input Offset Voltage Distribution
图7-17. Input Bias Current Distribution
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7.7 Typical Characteristics: VS = ±5 V (continued)
at VS+ = 5 V, VS– = –5 V, RF = 0 Ωfor Gain = 1 V/V, otherwise RF = 1 kΩfor other gains, CL = 1 pF, RL = 2 kΩreferenced
to mid-supply, G = 1 V/V, input and output referenced to mid-supply, and TA ≅ 25°C (unless otherwise noted)
0.96
0.93
0.9
20
16
12
8
0.87
0.84
0.81
0.78
0.75
0.72
0.69
0.66
4
-40
-20
0
20
40
60
80
100 120 140
0
Ambient Temperature (C)
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
35 units
Input Offset Drift (V/C)
80 units, μ= 0.01 μV/°C, σ= 0.29 μV/°C, DSN package
图7-19. Input Offset Voltage Drift Distribution
图7-20. Quiescent Current vs Ambient Temperature
700
650
600
550
500
450
400
350
300
250
200
150
100
50
100
80
60
40
20
0
-20
-40
-60
-80
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Ambient Temperature (C)
Ambient Temperature (C)
35 units
Normalized to 25°C values, 35 units, DSN package
图7-21. Input Bias Current vs Ambient Temperature
图7-22. Input Offset Voltage vs Ambient Temperature
8
6
8
VPD
VOUT x 10
6
4
4
2
2
0
0
-2
-4
-2
-4
-6
-8
-6
-8
VPD
VOUT x 10
Time (2 s/div)
Time (2 s/div)
.
.
图7-23. Turn-On Time to DC Input
图7-24. Turn-Off Time to DC Input
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7.7 Typical Characteristics: VS = ±5 V (continued)
at VS+ = 5 V, VS– = –5 V, RF = 0 Ωfor Gain = 1 V/V, otherwise RF = 1 kΩfor other gains, CL = 1 pF, RL = 2 kΩreferenced
to mid-supply, G = 1 V/V, input and output referenced to mid-supply, and TA ≅ 25°C (unless otherwise noted)
36000
32000
28000
24000
20000
16000
12000
8000
12
10
8
4000
0
6
8
10
12
14
16
18
6
-40
-20
0
20
40
60
80
100 120 140
Power-Down Quiescent Current per Channel (A)
Ambient Temperature (C)
μ= 9.3 μA, σ= 0.32 μA
.
图7-25. Power-Down Quiscent Current Distribution
图7-26. Power-Down IQ vs Ambient Temperature
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7.8 Typical Characteristics: VS = 3 V
at VS+ = 3 V, VS– = 0 V, RF = 0 Ωfor Gain = 1 V/V, otherwise RF = 1 kΩ for other gains, CL = 1 pF, RL = 2 kΩconnected to 1
V, G = 1 V/V, input and output VCM = 1 V, and TA ≅ 25°C (unless otherwise noted)
3
0
-40
HD2
HD3
-60
-3
-6
-80
-9
-100
-120
-140
-12
-15
-18
-21
G = 1 V/V
G = -1 V/V
G = 2 V/V
G = 5 V/V
G = 10 V/V
100k
1M
10M
Frequency (Hz)
100M
1k
10k
100k
1M
10M
Frequency (Hz)
VOUT = 20 mVPP
VOUT = 1 VPP
图7-27. Small-Signal Frequency Response vs Gain
图7-28. Harmonic Distortion vs Frequency
0.15
0.75
0.1
0.05
0
0.5
0.25
0
-0.05
-0.1
-0.25
-0.5
-0.75
-0.15
Time (20 ns/div)
Time (100 ns/div)
.
.
图7-29. Small-Signal Transient Response
图7-30. Large-Signal Transient Response
50
300
200
100
0
40
30
20
10
0
-100
-200
-300
-10
-20
-2
-1
0
1
2
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
Input Common-Mode Voltage (V)
Input Common-Mode Voltage (V)
VS = ±1.5 V
VS = ±1.5 V, Measured for 10 units
图7-32. Input Bias Current vs Input Common-Mode Voltage
图7-31. Input Offset Voltage vs Input Common-Mode Voltage
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7.8 Typical Characteristics: VS = 3 V (continued)
at VS+ = 3 V, VS– = 0 V, RF = 0 Ωfor Gain = 1 V/V, otherwise RF = 1 kΩ for other gains, CL = 1 pF, RL = 2 kΩconnected to 1
V, G = 1 V/V, input and output VCM = 1 V, and TA ≅ 25°C (unless otherwise noted)
3
2.5
2
60
40
20
0
Sourcing
Sinking
Sourcing
Sinking
1.5
1
-20
-40
-60
0.5
0
0
5
10
15
20
25
30
35
-40
-20
0
20
40
60
80
100
120
Output Current (mA)
Ambient Temperature (C)
.
Output saturated and then short-circuited to other supply
图7-33. Output Voltage vs Load Current
图7-34. Output Short-Circuit Current vs Ambient Temperature
4
3
4
VPD
VOUT x 10
3
2
1
0
2
1
0
VPD
VOUT x 10
-1
-1
Time (2 s/div)
Time (2 s/div)
.
.
图7-35. Turn-On Time to DC Input
图7-36. Turn-Off Time to DC Input
36000
32000
28000
24000
20000
16000
12000
8000
10
8
6
4
4000
0
4
6
8
10
12
14
-40
-20
0
20
40
60
80
100 120 140
Power-Down Quiescent Current per Channel (A)
Ambient Temperature (C)
μ= 7.36 μA, σ= 0.29 μA
.
图7-37. Power-Down Quiscent Current Distribution
图7-38. Power-Down IQ vs. Ambient Temperature
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7.9 Typical Characteristics: VS = 3 V to 10 V
at VOUT = 2 VPP, RF = 0 Ωfor Gain = 1 V/V, otherwise RF = 1 kΩ for other gains, CL = 1 pF, RL = 2 kΩreferenced to mid-
supply, G = 1 V/V, input and output referenced to mid-supply, and TA ≅ 25°C (unless otherwise noted)
135
120
105
90
210
180
150
120
90
3
Magnitude
Phase
0
-3
75
60
60
-6
45
30
-9
30
0
15
-30
-60
-90
-12
-15
0
VS = 10 V
VS = 3 V
-15
1
10
100
1k
10k 100k
1M
10M 100M
100k
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
Small-signal response
VOUT = 20 mVPP
图7-39. Open-Loop Gain and Phase vs Frequency
图7-40. Frequency Response vs Supply Voltage
100
10
Main Stage
Auxiliary Stage
10
1
1
10
0.1
10
100
1k 10k
Frequency (Hz)
100k
1M
100
1k
10k
100k
1M
D401
Frequency (Hz)
.
.
图7-41. Input Voltage Noise Density vs Frequency
图7-42. Input Current Noise Density vs Frequency
140
120
100
80
140
PSRR−
PSRR+
120
100
80
60
40
20
0
60
40
20
-20
100
1k
10k
100k
1M
10M
1
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
.
.
图7-43. Common-Mode Rejection Ratio vs Frequency
图7-44. Power Supply Rejection Ratio vs Frequency
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7.9 Typical Characteristics: VS = 3 V to 10 V (continued)
at VOUT = 2 VPP, RF = 0 Ωfor Gain = 1 V/V, otherwise RF = 1 kΩ for other gains, CL = 1 pF, RL = 2 kΩreferenced to mid-
supply, G = 1 V/V, input and output referenced to mid-supply, and TA ≅ 25°C (unless otherwise noted)
-60
100
80
60
40
20
0
-80
-100
-120
-140
Ch-A to Ch-B
Ch-B to Ch-A
100k
1M
10M
100M
1
10
100
1k
10k 100k
1M
10M 100M
Frequency (Hz)
Frequency (Hz)
DSN package
图7-46. Crosstalk vs Frequency
.
图7-45. Open-Loop Output Impedance vs Frequency
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8 Detailed Description
8.1 Overview
The OPAx863A bipolar voltage-feedback amplifiers offer 50 MHz gain-bandwidth product with a proprietary in-
package trim technology for high-precision performance with maximum 95 µV input offset voltage and 1.2 µV/℃
offset drift. The OPAx863A devices are low-power, rail-to-rail input and output (RRIO) operational amplifiers with
a voltage noise density of 6.3 nV/√Hz and 1/f noise corner at 25 Hz. The OPAx863A devices work in a wide-
supply voltage range from 2.7 V to 12.6 V and consumes only 800 µA quiescent current. The OPAx863A devices
operate with 2.7 V supply, are RRIO capable, consume low-power, and offer a power-down mode, which makes
them ideal amplifiers for 3.3-V or lower voltage applications that need superior AC performance. The amplifier's
main and auxiliary input stages are matched for gain bandwidth product (GBW), noise and offset voltage suitable
for applications which require wide dynamic input range and good SNR.
The device includes an overload power limit feature which limits the increase in quiescent current with over-
driven and saturated outputs to either of the supply rails. For more details of this overload power limit feature,
see 节8.3.2.1. The amplifier's output is protected against short-circuit fault conditions.
The OPAx863A devices feature a power-down mode (PD) with a PD quiescent current of 20 µA (maximum) with
a 3 V supply, with turn-on and turn-off time within less than 8 µs.
8.2 Functional Block Diagram
PD
VS+
OPAx863A
Auxiliary
NPN-
+
–
Stage
VIN+
EN
Output
Short-Circuit
Protection
CC
Main
PNP-
Stage
VOUT
+
–
Overload
Power
EN
Limiting
–
–
+
VIN–
VS+ –1.6 V
VS–
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8.3 Feature Description
8.3.1 Input Stage
The OPAx863A devices include a rail-to-rail input stage. The main stage differential pair using PNP bipolar
transistors operates for common-mode input voltages from VS–– 0.2 V till VS+ – 1.6 V. The amplifier inputs
transition into the auxiliary stage using NPN transistors for common-mode input voltages from VS+ – 1.6 V till
VS+ + 0.2 V. The PNP and NPN input stages offer a gain-bandwidth product of 50 MHz and a voltage noise
density of 6.3 nV/√Hz. The offset voltage for the two input stages is matched to lie within the device
specifications. The auxiliary NPN input stage does not use the slew boost circuit during large-signal transient
response. The input bias current for the PNP and NPN input stages is opposite in polarity, which adds an
additional offset based on the values of the gain-setting and feedback resistors. A common-mode input voltage
transition between these input stages will cause a crossover distortion which needs to be considered in high-
frequency applications requiring superior linearity. Limit the common-mode input voltage to VS+ – 1.6 V
(maximum) for main-stage operation across process and ambient temperature.
Since the OPAx863A devices are bipolar amplifiers, the two inputs are protected with anti-parallel back-to-back
diodes between them, which limits the maximum input differential voltage to 1 V. The amplifier is slew limited,
and the two inputs are pulled apart up to 1 V when the anti-parallel diodes begin to conduct in very fast input or
output transient conditions. Care must be taken to use gain-setting and feedback resistors large enough to limit
the current through these diodes in such conditions.
8.3.2 Output Stage
The OPAx863A devices feature a rail-to-rail output stage with possible signal swing from VS–+ 0.2 V to VS+–
0.2 V. Violating the output headroom to either of the supplies will cause output signal clipping and introduce
distortion.
The OPAx863A devices integrate an output short-circuit protection circuit, which makes the device rugged for
use in real-world applications.
8.3.2.1 Overload Power Limit
During overload or fault conditions, bipolar rail-to-rail output (RRO) amplifiers consume excessive quiescent
current (five to seven times) with saturated outputs. With saturated outputs, the output signal is clipped with
much higher base current from output pre-driver stage causing increase in device quiescent current. During this
condition, the negative feedback control is disabled and an input differential voltage appears thereby resulting in
an input overdrive. During input overdrive, the slew boost circuit engages to increase tail current which further
increases device quiescent current. This overall increase in quiescent current can cause excessive battery
discharge in portable products shortening operating lifetime or disturb the thermal equilibrium causing
irreversible damage due to increased system power dissipation in a multi-channel design.
The OPAx863A includes an intelligent overload detection circuit. This circuit monitors for output saturation and
limits the base drive from output pre-driver circuit and disables the slew boost circuit in this condition. As Table
8-1 provides, this feature limits the increase in device quiescent current to much smaller values.
表8-1. Quiescent Current with Saturated Outputs
Device
Input Differential
Voltage
Quiescent Current
during overload
Increase in IQ from
steady-state condition
OPAx863A with overload power limit
500 mV
500 mV
1.4 mA
1.8x
7.1x
Competitor amplifier without overload power limit
4.05 mA
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8.3.3 ESD Protection
As 图 8-1 shows, all device pins are protected with internal ESD protection diodes to the power supplies. These
diodes provide moderate protection to input overdrive voltages above the supplies. The protection diodes can
typically support 10-mA continuous input and output currents. Use series current limiting resistors if input
voltages exceeding the supply voltages occur at the amplifier inputs, which ensures the current through the ESD
diodes remains within their rated value. Since OPAx863A is a bipolar amplifier, the two inputs are protected with
anti-parallel back-to-back diodes between them which limits the maximum input differential voltage to
approximately 1 V. Care must be taken to use gain-setting and feedback resistors large enough to limit the
current through these diodes in fast slewing conditions.
VS+
Power Supply
ESD Cell
VIN+
PD
+
œ
VOUT
VIN-
VS-
图8-1. Internal ESD Protection
8.4 Device Functional Modes
8.4.1 Power-Down Mode
The OPAx863A includes a power-down mode for low-power standby operation with a quiescent current of 8.5
μA (typical) and high output impedance. Many low-power systems are active for only a small time interval when
the parameters of interest are measured and remain in low-power standby mode for a majority of the time for an
overall small average power consumption. The OPAx863A enables such a low-power operation with quick turn-
on within less than 8 μs. Refer to the Electrical Characteristics tables for power-down pin control thresholds.
The OPAx863A is enabled with the PD pin driven to VS+- 0.5 V or higher. The device powers down if the PD pin
is driven to VS+- 1.5 V or lower with a driver device capable of sinking approximately 1 μA (typical) current from
the PD pin. If level translation is needed to realize the PD pin thresholds for enable or power-down modes of
operation, an external pull-up resistor from PD pin to VS+ driven with an open-collector output should be used.
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
The OPAx863A devices are classic voltage-feedback amplifiers with each channel having two high-impedance
inputs and a low-impedance output. The combination of specifications with a GBW of 50 MHz, 6.3 nV/√Hz
noise, RRIO capability and high-precision performance consuming only 800 µA quiescent current make it an
ideal choice for use in precision data acquisition, reference buffering with fast settling, high gain and filter
circuits. The overload power limit makes OPAx863A truly low-power in high-gain multi-channel systems limiting
any increase in quiescent current during output overload conditions.
9.2 Typical Applications
9.2.1 Low-Power SAR ADC Driver and Reference Buffer
图 9-1 shows the use of the OPAx863A devices as a SAR ADC input driver driving the ADS7057. Sensors,
which are used for interface with the physical environment, exhibit high output impedance and cannot drive SAR
ADC inputs directly. A wide-GBW amplifier like the OPAx863A devices are needed to charge the switching
capacitors at the SAR ADC input and to settle fast to the required accuracy within the given acquisition time. The
OPAx863A's wide-GBW, high precision performance enables fast settling, high accuracy sensor measurements,
and reference buffering for precision ADCs.
5V
REF1933
3.3 V
3.3V
Reference
CFILT
RF
RG
3.3V
AVDD
–
RS
Sensor
OPAx863A
+
ZOUT
ADS7057
14-bit
CCB
2.5 MSPS
RS
图9-1. OPAx863A as Precision SAR ADC Driver
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9.2.2 Active Filters
Active filter circuits are used to amplify signals in the passband, attenuate signals in the stopband and also limit
the integrated noise at the amplifier's output. The OPAx863A with its wide bandwidth and high-precision
performance is suitable for designing multi-feedback (MFB) low-pass filter circuits.
9.2.2.1 Design Requirements
This section discusses the design of a MFB low-pass active filter with a cut-off frequency at 2 MHz and the
impact of amplifier's gain-bandwidth (GBW) on filter performance.
9.2.2.2 Detailed Design Procedure
图 9-2 shows the use of OPAx863A in a second-order multi-feedback (MFB) low-pass filter with a cut-off
frequency of 2 MHz. The passive component values are first selected for a cut-off frequency at 1 rad/sec and
later scaled for 2 MHz. The frequency response of the circuit in 图 9-2 is compared for various amplifiers with
different gain-bandwidth products and shown in 图9-3:
1k
37pF
1k
1k
VS+
–
VIN
OPAx863A
+
–
VOUT
+
168pF
VS-
图9-2. MFB Low-Pass Filter Circuit Using OPAx863A
表9-1. Impact of amplifier GBW on Cut-Off Frequency
Device
GBW (MHz)
Cut-off frequency (MHz)
TLV9051
LMV641
5
1.59
1.78
1.87
1.95
1.98
10
20
50
110
OPA2834
OPAx863A
OPA836
表9-1 provides the following benefits of using OPAx863A in an MFB low-pass filter circuit:
• High precision measurements with low offset voltage across operating temperature range for low-frequency
signals in passband
• High linearity due to the larger GBW and loop gain for low-frequency signals in passband
• Higher accuracy of cut-off frequency and its smaller variation over process and temperature
• Small integrated output noise due to low-pass filtering
As 图9-3 shows, the amplifier's gain-bandwidth, like the OPAx863A, should be at least 20x greater than the filter
cut-off frequency for a high-precision and linearity low-pass filter design.
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9.2.2.3 Application Curves
6
3
0
-3
-6
TLV9051
LMV641
OPA2834
OPAx863A
OPA836
-9
-12
1M
Frequency (Hz)
图9-3. MFB Low-Pass Filter Frequency Response vs GBW
10 Power Supply Recommendations
The OPAx863A devices are intended to operate on supplies ranging from 2.7 V to 12.6 V. The OPAx863A
devices may operate on single-sided supplies, split and balanced bipolar supplies, or unbalanced bipolar
supplies. Operating from a single supply can have numerous advantages. The DC errors, due to the –PSRR
term, can be minimized with the negative supply at ground. Typically, AC performance improves slightly at 10-V
operation with minimal increase in supply current. Minimize the distance (< 0.1 in) from the power supply pins to
high-frequency, 0.01-µF decoupling capacitors. A larger capacitor (2.2 µF typical) is used along with a high-
frequency, 0.01-µF supply-decoupling capacitor at the device supply pins. Only the positive supply has these
capacitors for single-supply operation. Use these capacitors from each supply to ground when a split-supply is
used. If necessary, place the larger capacitors further from the device and share these capacitors among several
devices in the same area of the printed circuit board (PCB). An optional supply decoupling capacitor across the
two power supplies (for split-supply operation) reduces second harmonic distortion.
11 Layout
11.1 Layout Guidelines
Achieving optimum performance with a high-frequency amplifier (like the OPAx863A devices) require careful
attention to board layout parasitics and external component types. The High Speed Amplifiers Generic DSN
Evaluation Module user's guide can be used as a reference when designing the circuit board. Recommendations
that optimize performance includes the following:
1. Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. Parasitic capacitance on the
output and inverting input pins can cause instability on the noninverting input and can react with the source
impedance to cause unintentional band-limiting. Open a window around the signal I/O pins in all of the
ground and power planes around those pins to reduce unwanted capacitance. Otherwise, ground and power
planes must be unbroken elsewhere on the board.
2. Minimize the distance (< 0.1 in) from the power-supply pins to high-frequency 0.01-µF decoupling
capacitors. Avoid narrow power and ground traces to minimize inductance between the pins and the
decoupling capacitors. The power-supply connections must always be decoupled with these capacitors.
Larger (2.2-µF to 6.8-µF) decoupling capacitors, effective at lower frequency, must also be used on the
supply pins. These can be placed somewhat farther from the device and shared among several devices in
the same area of the PC board.
3. Careful selection and placement of external components preserve the high frequency performance
of the OPAx863A devices. Resistors must be a low reactance type. Surface-mount resistors work best and
allow a tighter overall layout. Other network components, such as noninverting input termination resistors,
must also be placed close to the package. Keep resistor values as low as possible and consistent with load
driving considerations. Lowering the resistor values keep the resistor noise terms low and minimize the
effect of its parasitic capacitance; lower resistor values, however, increase the dynamic power consumption
because RF and RG become part of the amplifiers output load network.
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11.2 Layout Example
VS+
Representa ve schema c of a
single channel
CBYP
RS
+
–
CBYP
VS-
RF
RG
Ground and power plane exist on inner
layers.
Ground and power plane removed
from inner layers. Ground ll on outer
layers also removed
CBYP
RS
Place series output resistors close
to output pin to minimize
parasi c capacitance
10
9
1
2
RF
RS
Place bypass capacitors
close to power pins
RG
RF
Power
Pad
Place gain and feedback resistors close
to pins to minimize stray capacitance
8
3
RG
Place bypass capacitors
close to power pins
7
6
4
5
Remove GND and Power plane under
output and inver ng pins to minimize
stray PCB capacitance
CBYP
图11-1. Layout Recommendation for Dual-Channel DSN Package
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, High Speed Amplifiers Generic DSN Evaluation Module user's guide
• Texas Instruments, Single-Supply Op Amp Design Techniques application report
12.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
15-May-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA2863AIDSNR
ACTIVE
SON
DSN
10
5000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
2863A
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
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16-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA2863AIDSNR
SON
DSN
10
5000
330.0
12.4
3.15
3.15
0.75
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SON DSN 10
SPQ
Length (mm) Width (mm) Height (mm)
364.0 357.0 31.0
OPA2863AIDSNR
5000
Pack Materials-Page 2
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