OPA2890IDGSTG4 [TI]
Low-Power, Wideband, Voltage-Feedback OPERATIONAL AMPLIFIER with Disable; 低功耗，宽带电压反馈运算放大器具有禁用
| 型号： | OPA2890IDGSTG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Low-Power, Wideband, Voltage-Feedback OPERATIONAL AMPLIFIER with Disable |
| 文件： | 总35页 (文件大小：816K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OPA2890
www.ti.com.................................................................................................................................................... SBOS364B–DECEMBER 2007–REVISED MAY 2008
Low-Power, Wideband, Voltage-Feedback
OPERATIONAL AMPLIFIER with Disable
1
FEATURES
DESCRIPTION
2
•
FLEXIBLE SUPPLY RANGE:
+3V to +12V Single Supply
±1.5V to ±6V Dual Supplies
The OPA2890 represents a major step forward in
unity-gain stable, voltage-feedback op amps. A new
internal architecture provides slew rate and full-power
bandwidth previously found only in wideband,
current-feedback op amps. These capabilities give
exceptional single-supply operation. Using a single
+5V supply, the OPA2890 can deliver a 0.9V to 4.1V
output swing with over 30mA drive current and
210MHz bandwidth. This combination of features
makes the OPA2890 an ideal RGB line driver or
single-supply analog-to-digital converter (ADC) input
driver.
•
•
UNITY-GAIN STABLE
WIDEBAND +5V OPERATION: 90MHz
(G = 2V/V)
•
•
•
•
OUTPUT VOLTAGE SWING: ±4.1V
HIGH SLEW RATE: 400V/µs
LOW QUIESCENT CURRENT: 1.1mA/ch
LOW DISABLE CURRENT: 30µA/ch
APPLICATIONS
The low 1.1mA/ch supply current of the OPA2890 is
precisely trimmed at +25°C. This trim, along with low
temperature drift, ensures lower maximum supply
current than competing products. System power may
be reduced further using the optional disable control
pin (MSOP-10 package only). Leaving this disable pin
open, or holding it high, operates the OPA2890
normally. If pulled low, the OPA2890 supply current
drops to less than 30µA/ch while the output goes into
a high-impedance state.
•
•
•
•
•
•
•
VIDEO LINE DRIVING
xDSL LINE DRIVERS/RECEIVERS
HIGH-SPEED IMAGING CHANNELS
ADC BUFFERS
PORTABLE INSTRUMENTS
TRANSIMPEDANCE AMPLIFIERS
ACTIVE FILTERS
+5V
+6V
1kW
50W
ADS8472
VI
0V ® 4V
RELATED
OPERATIONAL AMPLIFIER
PRODUCTS
16W
1/2
500pF
200W
OPA2890
-6V
200W
SINGLES
DUALS
TRIPLES
16-Bit
1MSPS
SAR ADC
Low-power voltage-feedback
with disable
750W
750W
OPA890
0.01mF
Very low-power
OPA2889
OPA2690
voltage-feedback with disable
+6V
Voltage-feedback amplifier
with disable (1800V/µs)
OPA690
OPA3690
16W
1/2
375W
OPA2890
VREF/2
500kHz LP
Pole
-6V
Low Power, DC-Coupled, Single-to-Differential
Driver for ≤100kHz Inputs
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2008, Texas Instruments Incorporated
OPA2890
SBOS364B–DECEMBER 2007–REVISED MAY 2008.................................................................................................................................................... www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
SPECIFIED
PACKAGE
DESIGNATOR
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
PACKAGE-LEAD
OPA2890ID
OPA2890IDR
Rail, 75
OPA2890
SO-8
D
–40°C to +85°C
–40°C to +85°C
OPA2890
BPQ
Tape and Reel, 2500
Tape and Reel, 250
Tape and Reel, 2500
OPA2890IDGST
OPA2890IDGSR
OPA2890
MSOP-10
DGS
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range, unless otherwise noted.
OPA2890
UNIT
Power supply
±6.5
V
Internal power dissipation
See Thermal Characteristics
Input voltage range
±VS
–65 to +125
+260
V
Storage temperature range
Lead temperature (soldering, 10s)
Maximum junction temperature (TJ)
Minimum junction temperature: continuous operation, long-term reliability
ESD Rating:
°C
°C
°C
°C
+150
+140
Human body model (HBM)
Charge device model (CDM)
Machine model (MM)
2000
1500
200
V
V
V
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
PIN CONFIGURATIONS
SO-8
Top View
MSOP-10
Top View
Out A
-In A
+In A
-VS
1
2
3
4
8
7
6
5
+VS
+In A
DIS A
-VS
1
2
3
4
5
10 -In A
A
Out B
-In B
+In B
9
8
7
6
Out A
+VS
B
DIS B
+In B
Out B
-In B
2
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Product Folder Link(s): OPA2890
OPA2890
www.ti.com.................................................................................................................................................... SBOS364B–DECEMBER 2007–REVISED MAY 2008
ELECTRICAL CHARACTERISTICS: VS = ±5V
At TA = +25°C, RF = 0Ω, G = +1V/V, and RL = 200Ω, unless otherwise noted.
OPA2890ID, IDGS
TYP
MIN/MAX OVER TEMPERATURE
0°C to
–40°C to
+85°C(3)
MIN/
MAX
TEST
PARAMETER
CONDITIONS
+25°C
+25°C(2)
+70°C(3)
UNITS
LEVEL(1)
AC PERFORMANCE
Small-signal bandwidth
G = +1V/V, VO = 100mVPP, RF = 0Ω
G = +2V/V, VO = 100mVPP
G = +10V/V, VO = 100mVPP
G > +20V/V
250
100
12
MHz
MHz
MHz
MHz
MHz
dB
typ
min
min
min
typ
typ
typ
min
typ
typ
typ
C
B
B
B
C
C
C
B
C
C
C
60
8
50
7
45
6.5
78
Gain bandwidth product
Bandwidth for 0.1dB flatness
Peaking at a gain of +1V/V
Large-signal bandwidth
Slew rate
120
15
90
80
G = +2V/V, VO = 100mVPP
VO < 100mVPP
0.2
110
400
3.5
16
G = +2V/V, VO = 2VPP
G = +2V/V, VO = 2V step
0.2V step
MHz
V/µs
ns
300
275
270
Rise-and-fall time
Settling time to 0.02%
Settling time to 0.1%
Harmonic distortion
2nd harmonic
G = +1V/V, VO = 2V step
ns
10
ns
G = +2V/V, f = 1MHz, VO = 2VPP
RL = 200Ω
84
100
89
73
83
84
90
9
69
81
81
87
10
1.7
68
80
80
86
11
1.9
dBc
dBc
dBc
dBc
nV/√Hz
pA/√Hz
%
max
max
max
max
max
max
typ
B
B
B
B
B
B
C
C
C
RL ≥ 500Ω
3rd harmonic
RL = 200Ω
RL ≥ 500Ω
94
Input voltage noise
Input current noise
f > 100kHz
8
f > 100kHz
1
1.3
Differential gain
G = +2V/V, VO = 1.4VPP, RL = 150Ω
G = +2V/V, VO = 1.4VPP, RL = 150Ω
f = 5MHz, Input-referred
0.05
0.03
–68
Differential phase
°
typ
Channel-to-channel crosstalk
DC PERFORMANCE(4)
dB
typ
Open-loop voltage gain (AOL
)
VO = 0V, RL = 100Ω
VCM = 0V
62
±2
57
±5
56
±6.6
±35
±1.8
±5
54
±7.1
±35
±2
dB
mV
min
max
max
max
max
max
max
A
A
B
A
B
A
B
Input offset voltage
Average offset voltage drift
Input bias current
Average input bias current drift
Input offset current
Average input offset current drift
VCM = 0V
µV/°C
µA
VCM = 0V
±0.1
±70
±1.6
VCM = 0V
±6
nA/°C
nA
VCM = 0V
±350
±450
±2.5
±500
±2.5
VCM = 0V
nA/°C
INPUT
Common-mode input range (CMIR)(5)
Common-mode rejection ratio (CMRR)
Input impedance
±3.9
66
±3.8
±3.7
57
±3.6
56
V
min
min
A
A
VCM = 0V, Input-referred
60
dB
Differential
VCM = 0V
VCM = 0V
190 || 0.6
3.2 || 0.9
kΩ || pF
MΩ || pF
typ
typ
C
C
Common-mode
OUTPUT
Output voltage swing
No load
RL = 100Ω
±4.0
±3.6
±40
±3.9
±3.1
±35
±3.8
±3.05
±33
±3.7
±2.9
±30
V
V
min
min
min
typ
A
A
A
C
C
Output current, sourcing, sinking
Peak output current
VO = 0V
mA
mA
Ω
Output shorted to ground
G = +2V/V, f = 100kHz
±75
Closed-loop output impedance
0.04
typ
(1) Test levels: (A) 100% tested at +25°C. Over temperature limits set by characterization and simulation. (B) Limits set by characterization
and simulation. (C) Typical value only for information.
(2) Junction temperature = ambient for +25°C tested specifications.
(3) Junction temperature = ambient at low temperature limit; junction temperature = ambient +4°C at high temperature limit for over
temperature specifications.
(4) Current is considered positive out-of-node. VCM is the input common-mode voltage.
(5) Tested < 3dB below minimum specified CMRR at ±CMIR limits
Copyright © 2007–2008, Texas Instruments Incorporated
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OPA2890
SBOS364B–DECEMBER 2007–REVISED MAY 2008.................................................................................................................................................... www.ti.com
ELECTRICAL CHARACTERISTICS: VS = ±5V (continued)
At TA = +25°C, RF = 0Ω, G = +1V/V, and RL = 200Ω, unless otherwise noted.
OPA2890ID, IDGS
TYP
MIN/MAX OVER TEMPERATURE
0°C to
–40°C to
+85°C(3)
MIN/
MAX
TEST
PARAMETER
CONDITIONS
Disablelow
+25°C
+25°C(2)
+70°C(3)
UNITS
LEVEL(1)
DISABLE (MSOP-10 ONLY)
Power-down supply current (+VS)
Disable time
VDIS = 0, Both channels
VIN = 1VDC
60
7
110
120
150
µA
µs
ns
dB
pF
V
max
typ
A
C
C
C
C
A
A
A
Enable time
VIN = 1VDC
200
70
4
typ
Off isolation
G = +2V/V, f = 5MHz
typ
Output capacitance in disable
Enable voltage
typ
3.0
1.4
15
3.2
1.1
30
3.4
1.0
35
3.8
0.8
40
min
max
max
Disable voltage
V
Control pin input bias current (VDIS
POWER SUPPLY
)
VDIS = 0V, Each channel
µA
Specified operating voltage
Minimum operating voltage
Maximum operating voltage
Maximum quiescent current
Minimum quiescent current
±5
V
V
typ
typ
C
C
A
A
A
A
A
C
±1.5
±6.0
2.4
2.1
60
±6.0
2.45
2.05
58
±6.0
2.5
2.0
56
V
max
max
min
min
VS = ±5V, Both channels
VS = ±5V, Both channels
+VS = 4.5V to 5.5V
2.25
2.25
68
mA
mA
dB
Power-supply rejection ratio
(+PSRR)
THERMAL CHARACTERISTICS
Specified operating range: D and DGS packages
–40 to +85
°C
typ
Thermal resistance, θJA
Junction-to-
ambient
D
SO-8
100
135
°C/W
°C/W
typ
typ
C
C
DGS MSOP-10
4
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Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Link(s): OPA2890
OPA2890
www.ti.com.................................................................................................................................................... SBOS364B–DECEMBER 2007–REVISED MAY 2008
ELECTRICAL CHARACTERISTICS: VS = +5V
At RF = 0Ω, G = +1V/V, and RL = 100Ω, unless otherwise noted.
OPA2890ID, IDGS
TYP
MIN/MAX OVER TEMPERATURE
0°C to
–40°C to
+85°C(3)
MIN/
MAX
TEST
PARAMETER
CONDITIONS
+25°C
+25°C(2)
+70°C(3)
UNITS
LEVEL(1)
AC PERFORMANCE
Small-signal bandwidth
G = +1V/V, VO = 100mVPP, RF = 0Ω
G = +2V/V, VO = 100mVPP
G = +10V/V, VO = 100mVPP
G > +20V/V
210
90
MHz
MHz
MHz
MHz
MHz
dB
typ
min
min
min
typ
typ
typ
min
typ
typ
typ
C
B
B
B
C
C
C
B
C
C
C
55
8
45
6.8
70
40
6.3
68
12
Gain bandwidth product
Bandwidth for 0.1dB flatness
Peaking at a gain of +1V/V
Large-signal bandwidth
Slew rate
120
15
85
G = +2V/V, VO = 100mVPP
VO < 100mVPP
0.2
100
350
3.8
18
G = +2V/V, VO = 2VPP
G = +2V/V, VO = 2V step
0.2V step
MHz
V/µs
ns
250
200
175
Rise-and-fall time
Settling time to 0.02%
Settling time to 0.1%
Harmonic distortion
2nd harmonic
G = +1V/V, VO = 2V step
ns
12
ns
G = +2V/V, f = 1MHz, VO = 2VPP
RL = 200Ω
80
87
71
75
68
71
67
70
dBc
dBc
dBc
dBc
nV/√Hz
pA/√Hz
%
max
max
max
max
max
max
typ
B
B
B
B
B
B
C
C
C
RL ≥ 500Ω
3rd harmonic
RL = 200Ω
83
79
77
76
RL ≥ 500Ω
86
83
81
80
Input voltage noise
Input current noise
f > 100kHz
8.1
1.1
0.06
0.04
–68
9.1
1.4
10.1
1.7
11.1
2.0
f > 100kHz
Differential gain
G = +2V/V, VO = 1.4VPP, RL = 150Ω
G = +2V/V, VO = 1.4VPP, RL = 150Ω
f = 5MHz, Input-referred
Differential phase
°
typ
Channel-to-channel crosstalk
DC PERFORMANCE(4)
dB
typ
Open-loop voltage gain (AOL
)
VO = VS/2, RL = 100Ω
VCM = VS/2
60
±2
55
±5
54
±6.6
±35
±1.9
±5
52
±7.1
±35
±2.1
±6
dB
mV
min
max
max
max
max
max
max
A
A
B
A
B
A
B
Input offset voltage
Average offset voltage drift
Input bias current
Average input bias current drift
Input offset current
Average input offset current drift
VCM = VS/2
µV/°C
µA
VCM = VS/2
±0.1
±70
±1.7
VCM = VS/2
nA/°C
nA
VCM = VS/2
±400
±500
±2.5
±550
±2.5
VCM = VS/2
nA/°C
INPUT
Most positive input voltage(5)
Least positive input voltage(5)
Common-mode rejection ratio (CMRR)
Input impedance
+4
+1
65
+3.8
+1.2
59
+3.75
+1.2
56
+3.7
+1.3
55
V
V
min
max
min
A
A
A
VCM = VS/2, Input-referred
dB
Differential
VCM = VS/2
VCM = VS/2
190 || 0.6
3.2 || 0.9
kΩ || pF
MΩ || pF
typ
typ
C
C
Common-mode
OUTPUT
Most positive output voltage
No load
RL = 100Ω
+4.1
+3.9
+0.9
+1.1
±35
+3.9
+3.75
+1.1
+3.85
+3.7
+1.15
+1.4
±28
+3.8
+3.65
+1.2
V
V
min
min
max
max
min
typ
A
A
A
A
A
C
C
Least positive output voltage
No load
V
RL = 100Ω
+1.35
±30
+1.45
±25
V
Output current: sourcing, sinking
Short-circuit output current
VO = VS/2
mA
mA
Ω
Output shorted to ground
G = +2V/V, f = 100kHz
±65
Closed-loop output impedance
0.04
typ
(1) Test levels: (A) 100% tested at +25°C. Over temperature limits set by characterization and simulation. (B) Limits set by characterization
and simulation. (C) Typical value only for information.
(2) Junction temperature = ambient for +25°C tested specifications.
(3) Junction temperature = ambient at low temperature limit; junction temperature = ambient +2°C at high temperature limit for over
temperature specifications.
(4) Current is considered positive out-of-node. VCM is the input common-mode voltage.
(5) Tested < 3dB below minimum specified CMRR at ±CMIR limits
Copyright © 2007–2008, Texas Instruments Incorporated
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Product Folder Link(s): OPA2890
OPA2890
SBOS364B–DECEMBER 2007–REVISED MAY 2008.................................................................................................................................................... www.ti.com
ELECTRICAL CHARACTERISTICS: VS = +5V (continued)
At RF = 0Ω, G = +1V/V, and RL = 100Ω, unless otherwise noted.
OPA2890ID, IDGS
TYP
MIN/MAX OVER TEMPERATURE
0°C to
–40°C to
+85°C(3)
MIN/
MAX
TEST
PARAMETER
CONDITIONS
Disable low
+25°C
+25°C(2)
+70°C(3)
UNITS
LEVEL(1)
DISABLE (MSOP-10 ONLY)
Power-down supply current (+VS)
Disable time
VDIS = 0V, Both channels
VOUT = 1VDC
35
90
100
130
µA
ns
ns
dB
pF
V
max
typ
A
C
C
C
C
A
A
A
Enable time
VOUT = 1VDC
typ
Off isolation
G = +2V/V, f = 5MHz
typ
Output capacitance in disable
Enable voltage
typ
3.0
1.4
15
3.2
1.1
30
3.4
1.0
35
3.8
0.8
40
min
max
max
Disable voltage
V
Control pin input bias current (VDIS
POWER SUPPLY
)
VDIS = 0V, Each channel
µA
Specified operating voltage
Minimum operating voltage
Maximum operating voltage
Maximum quiescent current
Minimum quiescent current
Power-supply rejection ratio
THERMAL CHARACTERISTICS
+5
+3
V
V
typ
typ
C
C
A
A
A
C
+12
2.35
1.85
+12
2.4
1.8
+12
2.45
1.75
V
max
max
min
typ
VS = +5V, Both channels
VS = +5V, Both channels
+VS = 4.5V to 5.5V
2.1
2.1
65
mA
mA
dB
(+PSRR)
Specified operating range: D and DGS packages
–40 to +85
°C
typ
C
Thermal resistance, θJA
Junction-to-ambient
D
SO-8
100
135
°C/W
°C/W
typ
typ
C
C
DGS MSOP-10
6
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Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Link(s): OPA2890
OPA2890
www.ti.com.................................................................................................................................................... SBOS364B–DECEMBER 2007–REVISED MAY 2008
TYPICAL CHARACTERISTICS: VS = ±5V
At TA = +25°C, G = +2V/V, RF = 750Ω, and RL = 200Ω, unless otherwise noted. See Figure 49.
SMALL-SIGNAL FREQUENCY RESPONSE
LARGE-SIGNAL FREQUENCY RESPONSE
9
6
3
0
G = +1V/V
RF = 0W
2VPP
-3
3
G = +10V/V
1VPP
4VPP
-6
0
-9
7VPP
-3
-6
-9
G = +5V/V
G = +2V/V
-12
-15
-18
RL = 200W
VO = 0.5VPP
G = +2V/V
1
10
100
400
1
10
100
600
Frequency (MHz)
Frequency (MHz)
Figure 1.
Figure 2.
SMALL-SIGNAL PULSE RESPONSE
LARGE-SIGNAL PULSE RESPONSE
VO = 5VPP
400
4
VO = 500mVPP
G = +2V/V
300
200
3
2
G = +2V/V
100
1
0
0
-100
-200
-300
-400
-1
-2
-3
-4
Time (10ns/div)
Time (10ns/div)
Figure 3.
Figure 4.
VIDEO DIFFERENTIAL GAIN/DIFFERENTIAL PHASE
0.40
-dP
CHANNEL-TO-CHANNEL CROSSTALK
0.20
0.18
0.16
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0
-40
-45
-50
-55
-60
-65
-70
-75
-80
Input-Referred
0.36
0.32
-dG
0.28
0.24
0.20
+dG
0.16
+dP
0.12
0.08
0.04
0
1
2
3
4
1
10
100
Video Loads
Frequency (MHz)
Figure 6.
Figure 5.
Copyright © 2007–2008, Texas Instruments Incorporated
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Product Folder Link(s): OPA2890
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SBOS364B–DECEMBER 2007–REVISED MAY 2008.................................................................................................................................................... www.ti.com
TYPICAL CHARACTERISTICS: VS = ±5V (continued)
At TA = +25°C, G = +2V/V, RF = 750Ω, and RL = 200Ω, unless otherwise noted. See Figure 49.
HARMONIC DISTORTION vs LOAD RESISTANCE
1MHz HARMONIC DISTORTION vs SUPPLY VOLTAGE
-75
-70
-75
-80
-85
-90
-95
VO = 2VPP
RL = 200W
G = +2V/V
VO = 2VPP
f = 1MHz
G = +2V/V
-80
-85
-90
-95
2nd Harmonic
2nd Harmonic
3rd Harmonic
3rd Harmonic
100
1k
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Resistance (W)
Supply Voltage (±VS)
Figure 7.
Figure 8.
HARMONIC DISTORTION vs FREQUENCY
HARMONIC DISTORTION vs OUTPUT VOLTAGE
-75
-80
-85
-90
-95
-50
-60
RL = 200W
f = 1MHz
VO = 2VPP
RL = 200W
G = +2V/V
G = +2V/V
-70
2nd Harmonic
-80
2nd Harmonic
3rd Harmonic
-90
-100
-110
3rd Harmonic
0.1
1
10
0.1
1
10
Output Voltage Swing (VPP
Figure 10.
)
Frequency (MHz)
Figure 9.
HARMONIC DISTORTION vs NONINVERTING GAIN
HARMONIC DISTORTION vs INVERTING GAIN
-70
-75
-80
-85
-90
-95
-65
-70
-75
-80
-85
-90
VO = 2VPP
VO = 2VPP
2nd Harmonic
RL = 200W
2nd Harmonic
RL = 200W
f = 1MHz
f = 1MHz
3rd Harmonic
3rd Harmonic
1
10
20
-1
-10
-20
Gain (V/V)
Gain (V/V)
Figure 11.
Figure 12.
8
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TYPICAL CHARACTERISTICS: VS = ±5V (continued)
At TA = +25°C, G = +2V/V, RF = 750Ω, and RL = 200Ω, unless otherwise noted. See Figure 49.
LOW-FREQUENCY INVERTING HARMONIC DISTORTION
-90
TWO-TONE, 3RD-ORDER INTERMODULATION SPURIOUS
-30
Load power at matched 50W load.
VO = 2VPP
RL = 500W
-40
10MHz
-95
-100
-105
-110
-115
G = -1V/V
-50
-60
5MHz
-70
-80
2nd Harmonic
3rd Harmonic
-90
1MHz
-100
-110
1k
10k
100k
1M
-8
-6
-4
-2
0
2
4
6
8
Frequency (Hz)
Single-Tone Load Power (dBm)
Figure 13.
Figure 14.
RECOMMENDED RS vs CAPACITIVE LOAD
FREQUENCY RESPONSE vs CAPACITIVE LOAD
100
10
1
9
6
G = +2V/V
CL = 10pF
3
CL = 22pF
CL = 47pF
0
CL = 100pF
-3
-6
-9
RS
VIN
1/2
OPA2890
VOUT
1kW(1)
CL
750W
NOTE: (1) 1kW is optional.
750W
1
10
Capacitive Load (pF)
Figure 15.
100
1000
0
20
40
60
80 100 120 140 160 180 200
Frequency (MHz)
Figure 16.
COMMON-MODE REJECTION RATIO AND POWER-SUPPLY
REJECTION RATIO vs FREQUENCY
INPUT VOLTAGE AND CURRENT NOISE
80
100
10
1
-PSRR
70
CMRR
60
Voltage Noise (8nV/ÖHz)
Current Noise (1pA/ÖHz)
+PSRR
50
40
30
20
10
0
0.1
1k
10k
100k
1M
10M
100M
1
10
100
1k
10k
100k
1M
Frequency (Hz)
Frequency (Hz)
Figure 18.
Figure 17.
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TYPICAL CHARACTERISTICS: VS = ±5V (continued)
At TA = +25°C, G = +2V/V, RF = 750Ω, and RL = 200Ω, unless otherwise noted. See Figure 49.
SUPPLY AND OUTPUT CURRENT vs TEMPERATURE
2.36
Sinking Output Current
TYPICAL DC DRIFT OVER TEMPERATURE
44.0
43.5
43.0
42.5
42.0
41.5
41.0
40.5
40.0
150
100
50
0.2
Input Offset Current (IOS
)
2.32
0
2.28
-0.2
-0.4
-0.6
-0.8
-1.0
-1.2
Input Bias Current (IB)
Sourcing Output Current
2.24
0
2.20
-50
-100
-150
-200
Quiescent Supply Current
2.16
2.12
2.08
2.04
Input Offset Voltage (VOS
)
-40
-20
0
20
40 60 80 100
120
-40
-20
0
20
40
60
80
100
120
Ambient Temperature (°C)
Ambient Temperature (°C)
Figure 19.
Figure 20.
LARGE-SIGNAL DISABLE/ENABLE RESPONSE
NONINVERTING OVERDRIVE RECOVERY
8
6
4
6
4
3
2
4
2
Output Voltage
Left Scale
0
2
1
-2
0
0
3
2
Input Voltage
Right Scale
-2
-4
-6
-8
-1
-2
-3
-4
1
0
-1
Time (5ns/div)
Time (10ns/div)
Figure 21.
Figure 22.
CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY
100
OPEN-LOOP GAIN AND PHASE
Open-Loop Gain
80
70
60
50
40
30
20
10
0
180
160
140
120
100
80
1/2
ZO
OPA2890
10
1
374W
750W
750W
Open-Loop Phase
0.1
0.01
60
40
20
0.001
-10
0
1k
10k
100k
1M
10M
100M
100
1k
10k
100k
1M
10M
100M
1G
Frequency (Hz)
Frequency (Hz)
Figure 23.
Figure 24.
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TYPICAL CHARACTERISTICS: VS = ±5V (continued)
At TA = +25°C, G = +2V/V, RF = 750Ω, and RL = 200Ω, unless otherwise noted. See Figure 49.
DISABLE FEEDTHROUGH
-70
VDIS = 0
-75
-80
-85
-90
-95
-100
-105
-110
-115
-120
1
10
100
Frequency (MHz)
Figure 25.
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TYPICAL CHARACTERISTICS: VS = ±5V, Differential
At TA = +25°C, Differential Gain = +2V/V, and RL = 400Ω, unless otherwise noted. See Figure 52.
DIFFERENTIAL SMALL-SIGNAL FREQUENCY RESPONSE
DIFFERENTIAL LARGE-SIGNAL FREQUENCY RESPONSE
3
9
GD = 1V/V
0
6
VO = 5VPP
GD = 2V/V
-3
3
-6
-9
0
VO = 8VPP
-3
VO = 14VPP
GD = 10V/V
-12
-6
GD = 5V/V
-15
-18
-9
RF = 750W
RL = 400W
RL = 400W
GD = 2V/V
-12
1M
10M
Frequency (Hz)
Figure 26.
100M
400M
1
10
100
200
Frequency (MHz)
Figure 27.
DIFFERENTIAL DISTORTION vs LOAD RESISTANCE
DIFFERENTIAL DISTORTION vs FREQUENCY
-60
-30
-40
-50
-60
-70
-80
-90
-100
VO = 4VPP
RL = 400W
GD = 2V/V
2nd Harmonic
-65
-70
-75
-80
-85
-90
2nd Harmonic
3rd Harmonic
3rd Harmonic
VO = 4VPP
f = 1MHz
GD = 2V/V
100
1k
1
10
Frequency (MHz)
Figure 29.
20
Resistance (W)
Figure 28.
DIFFERENTIAL DISTORTION vs OUTPUT VOLTAGE
DIFFERENTIAL DISTORTION vs FREQUENCY
-65
-90
-100
-110
-120
-130
-140
-150
RL_DIFF = 1kW
GD = -1V/V
VO = 4VPP
2nd Harmonic
-70
-75
-80
-85
-90
3rd Harmonic
RL = 400W
f = 1MHz
GD = 2V/V
2nd Harmonic
3rd Harmonic
1
10
1k
10k
100k
Frequency (Hz)
Figure 31.
1M
Output Voltage (VPP
)
Figure 30.
12
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TYPICAL CHARACTERISTICS: VS = +5V
At TA = +25°C, G = +2V/V, RF = 750Ω, and RL = 200Ω, unless otherwise noted. See Figure 49.
NONINVERTING
SMALL-SIGNAL FREQUENCY RESPONSE
NONINVERTING
LARGE-SIGNAL FREQUENCY RESPONSE
3
0
9
6
RL = 200W
G = +2V/V
G = +1V/V
RF = 0W
1VPP
2VPP
-3
3
-6
G = +10V/V
0
-9
-3
-6
-9
-12
-15
-18
G = +5V/V
G = +2V/V
3VPP
100
VO = 500mVPP
1
10
100
500
1
10
300
Frequency (MHz)
Frequency (MHz)
Figure 33.
Figure 32.
SMALL-SIGNAL PULSE RESPONSE
LARGE-SIGNAL PULSE RESPONSE
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
4.1
3.7
3.3
2.9
2.5
2.1
1.7
1.3
0.9
VO = 0.5VPP
G = +2V/V
VO = 2VPP
G = +2V/V
Time (10ns/div)
Time (10ns/div)
Figure 34.
Figure 35.
RECOMMENDED RS vs CAPACITIVE LOAD
FREQUENCY RESPONSE vs CAPACITIVE LOAD
100
10
1
9
6
CL = 10pF
3
CL = 22pF
CL = 100pF
0
-3
-6
-9
-12
-15
CL = 47pF
RS
VIN
1/2
OPA2890
VOUT
1kW(1)
CL
750W
NOTE: (1) 1kW is optional.
750W
1
10
Capacitive Load (pF)
Figure 36.
100
1000
0
20
40
60
80 100 120 140 160 180 200
Frequency (MHz)
Figure 37.
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TYPICAL CHARACTERISTICS: VS = +5V (continued)
At TA = +25°C, G = +2V/V, RF = 750Ω, and RL = 200Ω, unless otherwise noted. See Figure 49.
NONINVERTING OVERDRIVE RECOVERY
HARMONIC DISTORTION vs LOAD RESISTANCE
-70
-75
-80
-85
-90
-95
6.5
5.5
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
VO = 2VPP
f = 1MHz
G = +2V/V
4.5
2nd Harmonic
3.5
Output Voltage
Left Scale
2.5
Input Voltage
Right Scale
1.5
3rd Harmonic
0.5
-0.5
-1.5
100
1k
Time (10ns/div)
Resistance (W)
Figure 38.
Figure 39.
HARMONIC DISTORTION vs FREQUENCY
HARMONIC DISTORTION vs OUTPUT VOLTAGE
-75
-80
-85
-90
-50
-60
-70
-80
-90
RL = 200W to VS/2
f = 1MHz
VO = 2VPP
RL = 200W to VS/2
G = +2V/V
G = +2V/V
2nd Harmonic
2nd Harmonic
3rd Harmonic
3rd Harmonic
-100
0.1
1
10
0.1
1
10
Output Voltage Swing (VPP
Figure 41.
)
Frequency (MHz)
Figure 40.
TWO-TONE, 3RD-ORDER INTERMODULATION SPURIOUS
-30
Load Power at Matched 50W Load
-40
10MHz
-50
-60
5MHz
-70
-80
1MHz
-90
-100
-8
-7
-6
-5
-4
-3
-2
-1
0
1
2
Single-Tone Load Power (dB)
Figure 42.
14
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TYPICAL CHARACTERISTICS: VS = +5V, Differential
At TA = +25°C, Differential Gain = +2V/V, and RL = 400Ω, unless otherwise noted. See Figure 58.
DIFFERENTIAL SMALL-SIGNAL FREQUENCY RESPONSE
DIFFERENTIAL LARGE-SIGNAL FREQUENCY RESPONSE
3
9
GD = 1V/V, RF = 0W
VO = 4VPP
0
6
GD = 2V/V
-3
3
-6
-9
VO = 1VPP
0
GD = 10V/V
-3
-12
GD = 5V/V
RF = 750W
-6
RL = 400W
-15
-18
RF = 750W
RL = 400W
GD = +2V/V
-9
1
10
100
300
1
10
100
200
Frequency (MHz)
Figure 43.
Frequency (MHz)
Figure 44.
DIFFERENTIAL DISTORTION vs LOAD RESISTANCE
DIFFERENTIAL DISTORTION vs FREQUENCY
-60
-30
-40
-50
-60
-70
-80
-90
-100
VO = 4VPP
RL = 400W
GD = 2V/V
2nd Harmonic
-65
-70
-75
-80
-85
VO = 4VPP
2nd Harmonic
3rd Harmonic
f = 1MHz
GD = 2V/V
3rd Harmonic
100
1k
0.1
1
10
20
Resistance (W)
Frequency (MHz)
Figure 46.
Figure 45.
DIFFERENTIAL DISTORTION vs OUTPUT VOLTAGE
DIFFERENTIAL DISTORTION vs FREQUENCY
-60
-80
-85
RL = 400W
RL_DIFF = 1kW
f = 1MHz
GD = 2V/V
GD = 1V/V
2nd Harmonic
VO = 4VPP
3rd Harmonic
-90
-70
-80
-90
-100
-110
-120
-130
2nd Harmonic
3rd Harmonic
Shift Phase 180° of Input Signal
0.1
1
10
1
10
100
1000
Output Voltage (VPP
)
Frequency (Hz)
Figure 47.
Figure 48.
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APPLICATIONS INFORMATION
+5V
WIDEBAND VOLTAGE-FEEDBACK
OPERATION
+VS
0.1mF
6.8mF
+
The OPA2890 provides an exceptional combination
of high output power capability in a dual, wideband,
unity-gain stable, voltage-feedback op amp using a
new high slew rate input stage. Typical differential
input stages used for voltage-feedback op amps are
50W Source
350W
DIS
100W Load
VD
VI
VO 100W
designed to steer
a
fixed-bias current to the
limit to the
50W
1/2
OPA2890
compensation capacitor, setting
a
achievable slew rate. The OPA2890 uses a new input
stage that places the transconductance element
between two input buffers, using the output currents
as the forward signal. As the error voltage increases
across the two inputs, an increasing current is
delivered to the compensation capacitor. This
configuration provides high slew rate (400V/µs) while
0.1mF
RF
750W
RG
750W
consuming
relatively
low
quiescent
current
6.8mF
0.1mF
+
(1.12mA/ch). This exceptional full-power performance
comes at the price of a slightly higher input noise
voltage than alternative architectures; however, the
8nV/√Hz input voltage noise for the OPA2890 is
exceptionally low for this type of input stage.
-VS
-5V
Figure 49. DC-Coupled, G = +2V/V, Bipolar
Supply, Specification and Test Circuit
Figure 49 shows the DC-coupled, gain of +2V/V, dual
power-supply circuit configuration used as the basis
of the ±5V Electrical Characteristics and Typical
Characteristics. This illustration is for one channel;
the other channel is connected similarly. For test
purposes, the input impedance is set to 50Ω with a
resistor to ground and the output impedance is set to
200Ω. Voltage swings reported in the Electrical
Characteristics are taken directly at the input and
output pins, while output powers (dBm) are at the
matched 50Ω load. For the circuit of Figure 49, the
total effective load is 200Ω || 1.5kΩ. The disable
control line (MSOP-10 package only) is typically left
open for normal amplifier operation. Two optional
components are included in Figure 49. First, an
additional resistor (350Ω) is included in series with
the noninverting input. Combined with the 25Ω dc
source resistance looking back towards the signal
generator, this resistor gives an input bias current
cancelling resistance that matches the 750Ω source
resistance seen at the inverting input (see the DC
Accuracy and Offset Control section). In addition to
the usual power-supply decoupling capacitors to
ground, a 0.1µF capacitor is also included between
the two power-supply pins. In practical printed circuit
board (PCB) layouts, this optional capacitor typically
improves the 2nd-harmonic distortion performance by
3dB to 6dB.
Figure 50 illustrates the ac-coupled, gain of +2V/V,
single-supply circuit configuration used as the basis
of the +5V Electrical Characteristics and Typical
Characteristics. Though not a rail-to-rail design, the
OPA2890 requires minimal input and output voltage
headroom compared to other very wideband
voltage-feedback op amps. It delivers a 3VPP output
swing on a single +5V supply with greater than
80MHz bandwidth. The key requirement of
broadband single-supply operation is to maintain
input and output signal swings within the usable
voltage ranges at both the input and the output. The
circuit of Figure 50 establishes an input midpoint bias
using a simple resistive divider from the +5V supply
(two 698Ω resistors). Separate bias networks would
be required at each input. The input signal is then
ac-coupled into the midpoint voltage bias. The input
voltage can swing to within 1.5V of either supply pin,
giving a 2VPP input signal range centered between
the supply pins. The input impedance matching
resistor (59Ω) used for testing is adjusted to give a
50Ω input load when the parallel combination of the
biasing divider network is included.
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+5V
+VS
+5V
RF
GD
=
RG
1/2
OPA2830
+
0.1mF
6.8mF
698W
50W
RG
RF
RF
0.1mF
59W
DIS
200W
RL
VOUT
VIN
VD
VI
RG
VO
698W
1/2
OPA2890
VS/2
RF
750W
1/2
OPA2830
RG
-5V
750W
0.1mF
Figure 51. Differential Inverting Specification and
Test Circuit
Figure 50. DC-Coupled, G = +2V/V, Single-Supply,
Specification and Test Circuit
+5V
2RF
RG
GD = 1 +
1/2
Again, an additional resistor (50Ω in this case) is
included directly in series with the noninverting input.
This minimum recommended value provides part of
the dc source resistance matching for the
noninverting input bias current. It is also used to form
a simple parasitic pole to roll off the frequency
response at very high frequencies ( > 500MHz) using
the input parasitic capacitance. The gain resistor (RG)
is AC-coupled, giving the circuit a dc gain of +1V/V,
which puts the input dc bias voltage (2.5V) on the
output as well. The output voltage can swing to within
1V of either supply pin while delivering greater than
40mA output current.
OPA2830
RF
RL
VIN
RG
RF
1/2
OPA2830
-5V
Figure 52. Differential Noninverting Specification
and Test Circuit
DIFFERENTIAL OPERATION
Figure 51 shows the inverting differential
configuration used as the basis for the ±5V and +5V
Typical Characteristics. This circuit offers
a
combination of excellent distortion with low quiescent
current for frequencies below 100kHz.
The other possibility is to use the OPA2890 in a
differential configuration as shown in Figure 52. This
figure illustrates the differential noninverting
configuration that has the advantage of showing a
high input impedance to any prior stage.
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HIGH-PERFORMANCE DAC
WIDEBAND VIDEO MULTIPLEXING
TRANSIMPEDANCE AMPLIFIER
One common application for video speed amplifiers
that include a disable pin is to wire multiple amplifier
outputs together, then select one of several possible
video inputs to source onto a single line. This simple
wired-OR video multiplexer can be easily
implemented using the OP2890IDGS (MSOP-10
package only), as shown in Figure 54.
High-frequency DDS digital-to-analog converters
(DACs) require a low distortion output amplifier to
retain SFDR performance into real-world loads.
Figure 53 shows
a single-ended output drive
implementation. The diagram shows the signal output
current(s) connected into the virtual ground summing
junction(s) of the OPA2890, which is set up as a
transimpedance stage or I-V converter. If the DAC
requires that its outputs terminate to a compliance
voltage other than ground for operation, the
appropriate voltage level may be applied to the
noninverting input of the OPA2890. The dc gain for
this circuit is equal to RF. At high frequencies, the
DAC output capacitance (CD in Figure 53) produces a
zero in the noise gain for the OPA2890 that may
cause peaking in the closed-loop frequency
response. CF is added across RF to compensate for
50W
1/2
OPA2890
VO = IO RF
High-Speed
DAC
RF1
CF1
IO
CD1
this noise gain peaking. To achieve
a
flat
RF2
transimpedance frequency response, the pole in each
feedback network should be set to:
CF2
1
2pRFCF
GBP
4pRFCD
=
CD2
-IO
(1)
1/2
OPA2890
which gives a cutoff frequency f–3dB of approximately:
-VO = -IO RF
GBP
2pRFCD
f-3dB
=
GBP ® Gain Bandwidth
Product (Hz) for the OPA2890
50W
Figure 53. DAC Transimpedance Amplifier
+5V
2kW
VDIS
+5V
305W
DISA
1/2
Video 1
OPA2890
75W
82.5W
634W
750W
-5V
75W Cable
634W
750W
RG-59
75W Load
+5V
82.5W
1/2
305W
OPA2890
DISB
Video 2
75W
-5V
2kW
Figure 54. 2-Channel Video Multiplexer (MSOP-10 package only)
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Typically, channel switching is performed either on
sync or retrace time in the video signal. The two
inputs are approximately equal at this point. The
make-before-break disable characteristic of the
OPA2890 ensures that there is always one amplifier
controlling the line when using a wired-OR circuit
such as that shown in Figure 54. Because both inputs
may be on for a short period during the transition
between channels, the outputs are combined through
the output impedance matching resistors (82.5Ω in
this case). When one channel is disabled, its
feedback network forms part of the output impedance
and slightly attenuates the signal in getting out onto
the cable. The gain and output matching resistor are
slightly increased to get a signal gain of +1V/V at the
matched load and provide a 75Ω output impedance
to the cable. The video multiplexer connection (see
Figure 54) also ensures that the maximum differential
voltage across the inputs of the unselected channel
does not exceed the rated ±1.2V maximum for
standard video signal levels.
HIGH-SPEED DELAY CIRCUIT
The OPA2890 makes an ideal amplifier for a variety
of active filter designs. Figure 55 illustrates a circuit
that uses the two amplifiers within the dual OPA2890
to design a two-stage analog delay circuit. For
simplicity, the circuit uses
a dual-supply (±5V)
operation, but it can also be modified to operate on a
signal supply. The input to the first filter stage is
driven by the OPA890 as a gain of +2V/V to isolate
the signal input from the filter network.
Each of the two filter stages is a 1st-order filter with a
voltage gain of +1V/V. The delay time through one
filter is given by Equation 2.
tGR0 = 2RC
(2)
For a more accurate analysis of the circuit, consider
the group delay for the amplifiers. For example, in the
case of the OPA2890, the group delay in the
bandwidth from 1MHz to 100MHz is approximately
1.0ns. To account for this delay, modify the transfer
function, which now comes out to be:
See the Disable Operation section for the turn-on and
turn-off switching glitches using a 0V input for a
single channel is typically less than ±50mV. Where
two outputs are switched (see Figure 54), the output
line is always under the control of one amplifier or the
other as a result of the make-before-break disable
timing. In this case, the switching glitches for two 0V
inputs drops to less than 20mV.
tGR = 2 (2RC + TD)
(3)
with TD = (1/360) × (dφ/df) = delay of the op amp
itself. The values of resistors RF and RG should be
equal and low to avoid parasitic effects. If the all-pass
filter is designed for very low delay times, include
parasitic board capacitances to calculate the correct
delay time. Simulating this application using the
PSpice model of the OPA2890 allows this design to
be tuned to the desired performance.
C
VIN
OPA890
C
1/2
OPA2890
1/2
R
VOUT
OPA2890
750W
R
RG
402W
RF
750W
RG
RF
402W
402W
402W
Figure 55. Two-Stage, All-Pass Network
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DIFFERENTIAL RECEIVER/DRIVER
SINGLE-SUPPLY MFB DIFFERENTIAL
ACTIVE FILTER: 2MHz BUTTERWORTH
CONFIGURATION
A very versatile application for a dual operational
amplifier is the differential amplifier configuration
shown in Figure 56. With both amplifiers of the
OPA2890 connected for noninverting operation, the
circuit provides a high input impedance, while the
gain can easily be set by just one resistor, RG. When
operated in low gains, the output swing may be
limited as a result of the common-mode input swing
limits of the amplifier itself. An interesting modification
of this circuit is to place a capacitor in series with RG.
Now the dc gain for each side is reduced to +1V/V;
the ac gain follows the standard transfer function of G
The active filter circuit illustrated in Figure 58 can be
easily implemented using the OPA2890. In this
configuration, each amplifier of the OPA2890
operates as an integrator. For this reason, this type of
application is also called an infinite gain filter
implementation.
A
Butterworth filter can be
implemented using the following component ratios:
1
fO =
2 ´ p ´ R ´ C
R1 = R2 = 0.65 ´ R
R3 = 0.375 ´ R
C1 = C
=
1
+
2RF/RG. This configuration might be
advantageous for applications processing only a
frequency band that excludes dc or very low
frequencies. An input dc voltage resulting from input
bias currents is not amplified by the ac gain and can
be kept low. This circuit can be used as a differential
line receiver, driver, or as an interface to a differential
input ADC.
C2 = 2 ´ C
The frequency response for a 2MHz Butterworth filter
is shown in Figure 57. One advantage for using this
type of filter is the independent setting of ωo and Q. Q
can be easily adjusted by changing the R3A,
resistors without affecting ωo.
B
50W
VI
RO
1/2
OPA2890
3
RF
0
-3
750W
2RF
RG
VDIFF = 1 +
VI - (-VI)
RF
RG
750W
-6
RO
1/2
-9
50W
OPA2890
-VI
-12
10k
100k
Frequency (Hz)
1M
10M
Figure 56. High-Speed Differential Receiver
Figure 57. Multiple Feedback Filter Frequency
Response
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+12V
6kW
50W
VCM
1/2
OPA2890
1000pF
6kW
R3A
C1A
R1A
128.7pF
232W
402W
R2A
402W
C2
R2B
VIN
VOUT
257.4pF
402W
C1B
R1B
R3B
128.7pF
402W
232W
1/2
OPA2890
50W
VCM
Figure 58. Single-Supply, MFB Active Filter, 2MHz LP Butterworth
MACROMODELS
DESIGN-IN TOOLS
Computer simulation of circuit performance using
SPICE is often useful when analyzing the
performance of analog circuits and systems. This
principle is particularly true for video and RF amplifier
circuits where parasitic capacitance and inductance
can have a major effect on circuit performance. A
SPICE model for the OPA2890 (use two OPA890
SPICE models) is available through the Texas
Instruments web page (www.ti.com). This model does
a good job of predicting small-signal ac and transient
DEMONSTRATION FIXTURES
Two printed circuit boards (PCBs) are available to
assist in the initial evaluation of circuit performance
using the OPA2890 in its two package options. Both
of these are offered free of charge as unpopulated
PCBs, delivered with a user’s guide. The summary
information for these fixtures is shown in Table 1.
Table 1. Demonstration Fixtures by Package
performance under
a wide variety of operating
LITERATURE
conditions. It does not do as well in predicting the
harmonic distortion or dG/dP characteristics. This
model does not attempt to distinguish between the
package types in small-signal ac performance.
PRODUCT
PACKAGE
SO-8
ORDERING NUMBER
DEM-OPA-SO-2A
NUMBER
SBOU003
SBOU040
OPA2890ID
OPA2890IDG
S
MSOP-10
DEM-OPA-MSOP-2B
The demonstration fixtures can be requested at the
Texas Instruments web site (www.ti.com) through the
OPA2890 product folder.
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OPERATING RECOMMENDATIONS
bandwidth to more closely approach the predicted
value of (GBP/NG). At a gain of +10V/V, the 12MHz
bandwidth shown in the Electrical Characteristics
agrees with that predicted using the simple formula
and the typical GBP of 120MHz.
OPTIMIZING RESISTOR VALUES
Because the OPA2890 is
a unity-gain stable,
voltage-feedback op amp, a wide range of resistor
values may be used for the feedback and gain setting
resistors. The primary limits on these values are set
by dynamic range (noise and distortion) and parasitic
The frequency response in a gain of +2V/V may be
modified to achieve exceptional flatness simply by
increasing the noise gain to 2.5V/V. One way to
modify the response without affecting the +2V/V
signal gain, is to add an 1.5kΩ resistor across the two
inputs, as illustrated in the circuit of Figure 49. A
similar technique may be used to reduce peaking in
unity-gain (voltage follower) applications. For
example, by using a 750Ω feedback resistor along
with a 750Ω resistor across the two op amp inputs,
the voltage follower response is similar to the gain of
+2V/V response of Figure 50. Reducing the value of
the resistor across the op amp inputs further limits the
frequency response due to increased noise gain.
capacitance considerations. For
a
noninverting
unity-gain follower application, the feedback
connection should be made with a 25Ω resistor, not a
direct short. This feedback resistor isolates the
inverting input capacitance from the output pin and
improve the frequency response flatness. Usually, the
feedback resistor value should be between 200Ω and
1.5kΩ. Below 200Ω, the feedback network presents
additional output loading that can degrade the
harmonic distortion performance of the OPA2890.
Above 1.5kΩ, the typical parasitic capacitance
(approximately 0.2pF) across the feedback resistor
can cause unintentional band-limiting in the amplifier
response.
The OPA2890 exhibits minimal bandwidth reduction
going to single-supply (+5V) operation as compared
with ±5V. This feature arises because the internal
bias control circuitry retains nearly constant quiescent
current as the total supply voltage between the
supply pins changes.
A good rule of thumb is to target the parallel
combination of RF and RG (see Figure 49) to be less
than approximately 400Ω. The combined impedance
RF || RG interacts with the inverting input capacitance,
placing an additional pole in the feedback network
and thus, a zero in the forward response. Assuming a
2pF total parasitic on the inverting node, holding RF ||
RG < 400Ω keeps this pole above 160MHz. By itself,
this constraint implies that the feedback resistor RF
can increase to several kΩ at high gains. This
increase in resistor size is acceptable as long as the
pole formed by RF and any parasitic capacitance
appearing in parallel is kept out of the frequency
range of interest.
INVERTING AMPLIFIER OPERATION
The OPA2890 is
a general-purpose, wideband,
voltage-feedback op amp; therefore, all of the familiar
op amp application circuits are available to the
designer. Inverting operation is one of the more
common
requirements
and
offers
several
performance benefits. See Figure 59 for a typical
inverting configuration where the I/O impedances and
signal gain from Figure 49 are retained in an inverting
circuit configuration.
BANDWIDTH vs GAIN: NONINVERTING
OPERATION
In the inverting configuration, three key design
considerations must be noted. The first is that the
gain resistor (RG) becomes part of the signal channel
input impedance. If input impedance matching is
desired (which is beneficial whenever the signal is
coupled through a cable, twisted-pair, long PCB
trace, or other transmission line conductor), RG may
be set equal to the required termination value and RF
adjusted to give the desired gain. This consideration
is the simplest approach and results in optimum
bandwidth and noise performance. However, at low
inverting gains, the resultant feedback resistor value
can present a significant load to the amplifier output.
For an inverting gain of –2V/V, setting RG to 50Ω for
input matching eliminates the need for RM but
requires a 100Ω feedback resistor. This consideration
has the interesting advantage that the noise gain
Voltage-feedback op amps exhibit decreasing
closed-loop bandwidth as the signal gain increases.
In theory, this relationship is described by the Gain
Bandwidth Product (GBP) shown in the Electrical
Characteristics. Ideally, dividing GBP by the
noninverting signal gain (also called the Noise Gain,
or NG) predicts the closed-loop bandwidth. In
practice, this principle only holds true when the phase
margin approaches 90°, as it does in high gain
configurations. At low gains (increased feedback
factors), most amplifiers exhibit a more complex
response with lower phase margin. The OPA2890 is
compensated to give a slightly peaked response in a
noninverting gain of 2V/V (see Figure 49). This
compensation results in a typical gain of +2V/V
bandwidth of 100MHz, far exceeding that predicted
by dividing the 60MHz GBP by 2. Increasing the gain
causes the phase margin to approach 90° and the
becomes equal to 2V/V for
a
50Ω source
impedance—the same as the noninverting circuits
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discussed in the previous section. The amplifier
output, however, now sees the 100Ω feedback
resistor in parallel with the external load. In general,
the feedback resistor should be limited to the 200Ω to
1.5kΩ range. In this case, it is preferable to increase
both the RF and RG values (see Figure 56), and then
achieve the input matching impedance with a third
resistor (RM) to ground. The total input impedance
becomes the parallel combination of RG and RM.
Combining this resistance in parallel with the
feedback resistor gives the RB = 261Ω used in this
example. To reduce the additional high-frequency
noise introduced by this resistor, it is sometimes
bypassed with a capacitor. As long as RB < 350Ω, the
capacitor is not required because the total noise
contribution of all other terms is less than that of the
op amp input noise voltage. As a minimum, the
OPA2890 requires an RB value of 50Ω to damp out
parasitic-induced peaking—a direct short to ground
on the noninverting input runs the risk of a very
high-frequency instability in the input stage.
+5V
+
0.1mF
6.8mF
DRIVING CAPACITIVE LOADS
One of the most demanding and yet very common
load conditions for an op amp is capacitive loading.
Often, the capacitive load is the input of an
ADC—including additional external capacitance that
may be recommended to improve ADC linearity. A
high-speed, high open-loop gain amplifier such as the
OPA2890 can be very susceptible to decreased
stability and closed-loop response peaking when a
capacitive load is placed directly on the output pin.
When the open-loop output resistance of the amplifier
is considered, this capacitive load introduces an
additional pole in the signal path that can decrease
the phase margin. Several external solutions to this
problem have been suggested. When the primary
considerations are frequency response flatness,
pulse response fidelity, and/or distortion, the simplest
and most effective solution is to isolate the capacitive
0.1mF
RO
50W
VO
1/2
OPA2890
RB
261W
50W Load
VO
= -2V/V
50W
Source
VI
VI
RG
375W
RF
750W
RM
57.6W
0.1mF
6.8mF
+
-5V
Figure 59. Gain of –2V/V Example Circuit
load from the feedback loop by inserting
a
series-isolation resistor between the amplifier output
and the capacitive load. This solution does not
eliminate the pole from the loop response, but rather
shifts it and adds a zero at a higher frequency. The
additional zero acts to cancel the phase lag from the
capacitive load pole, thus increasing the phase
margin and improving stability.
The second major consideration, touched on in the
previous paragraph, is that the signal source
impedance becomes part of the noise gain equation
and influences the bandwidth. For the example in
Figure 59, the RM value combined in parallel with the
external 50Ω source impedance yields an effective
driving impedance of 50Ω || 57.6Ω = 26.7Ω. This
impedance is added in series with RG for calculating
the noise gain (NG). The resultant NG is 2.86V/V for
Figure 59, as opposed to only 2V/V if RM could be
eliminated as discussed above. Therefore, the
bandwidth is slightly lower for the gain of –2V/V
circuit of Figure 59 than for the gain of +2V/V circuit
of Figure 49.
The Typical Characteristics show the recommended
RS versus capacitive load (see Figure 15 and
Figure 36) and the resulting frequency response at
the load. Parasitic capacitive loads greater than 2pF
can begin to degrade the performance of the
OPA2890. Long PCB traces, unmatched cables, and
connections to multiple devices can easily exceed
this value. Always consider this effect carefully, and
add the recommended series resistor as close as
possible to the OPA2890 output pin (see the Board
Layout Guidelines section).
The third important consideration in inverting amplifier
design is setting the bias current cancellation resistor
on the noninverting input (RB). If this resistor is set
equal to the total dc resistance looking out of the
inverting node, the output dc error (as a result of the
input bias currents) is reduced to [(Input Offset
Current) × RF]. If the 50Ω source impedance is
DC-coupled in Figure 57, the total resistance to
ground on the inverting input is 402Ω.
DISTORTION PERFORMANCE
The OPA2890 provides good distortion performance
into a 100Ω load on ±5V supplies. Relative to
alternative solutions, it provides exceptional
performance into lighter loads and/or operating on a
single +5V supply. Generally, until the fundamental
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signal reaches very high frequency or power levels,
ENI
the 2nd harmonic dominates the distortion with a
negligible 3rd harmonic component. Focusing then on
the 2nd harmonic, increasing the load impedance
improves distortion directly. Remember that the total
1/2
EO
OPA2890
RS
IBN
load includes the feedback network; in the
noninverting configuration (see Figure 49), this value
is the sum of RF + RG, while in the inverting
ERS
RF
Ö4kTRS
configuration it is only RF. Also, providing an
additional supply-decoupling capacitor (0.1µF)
between the supply pins (for bipolar operation)
Ö4kTRF
IBI
RG
improves the 2nd-order distortion slightly (3dB to
6dB). Operating differentially also lowers
4kT
RG
4kT = 1.6E - 20J
at 290°K
2nd-harmonic distortion terms (see the plot on the
front page).
Figure 60. Op Amp Noise Analysis Model
In most op amps, increasing the output voltage swing
increases harmonic distortion directly. The output
stage used in the OPA2890 holds the difference
between fundamental power and the 2nd- and
3rd-harmonic powers relatively constant with
increasing output power until very large output swings
are required ( > 4VPP). This also shows up in the
two-tone, 3rd-order intermodulation spurious (IM3)
response curves. The 3rd-order spurious levels are
extremely low at low output power levels. The output
stage continues to hold them low even as the
fundamental power reaches very high levels. As the
The total output spot noise voltage can be computed
as the square root of the sum of all squared output
noise voltage contributors. Equation 4 shows the
general form for the output noise voltage using the
terms shown in Figure 60.
[EN2 I + (IBNRS)2 + 4kTRS]NG2 + (IBIRF)2 + 4kTRFNG
EO
=
(4)
Dividing this expression by the noise gain (NG = (1 +
RF/RG)) gives the equivalent input-referred spot noise
voltage at the noninverting input, as shown in
Typical
Characteristics
show,
the
spurious
intermodulation powers do not increase as predicted
by a traditional intercept model. As the fundamental
power level increases, the dynamic range does not
decrease significantly. For two tones centered at
10MHz, with 4dBm/tone into a matched 50Ω load
(that is, 1VPP for each tone at the load, which requires
4VPP for the overall two-tone envelope at the output
pin), the Typical Characteristics show a 38dBc
difference between the test tone powers and the
3rd-order intermodulation spurious powers. This
exceptional performance for all 22.5mW internal
power dissipation parts improves further when
operating at lower frequencies or powers.
Equation 5.
2
IBIRF
( NG )
4kTRF
NG
EN2 I + (IBNRS)2 + 4kTRS +
EN =
+
(5)
Evaluating these two equations for the OPA2890
circuit and component values (see Figure 49) gives a
total output spot noise voltage of 17.5nV/√Hz and a
total equivalent input spot noise voltage of 8.7nV/√Hz.
This result includes the noise added by the bias
current cancellation resistor (350Ω) on the
noninverting input. This total input-referred spot noise
voltage is only slightly higher than the 8nV/√Hz
specification for the op amp voltage noise alone. This
result is the case as long as the impedances
appearing at each op amp input are limited to the
previously recommend maximum value of 400Ω.
Keeping both (RF || RG) and the noninverting input
source impedance less than 400Ω satisfies both
NOISE PERFORMANCE
High slew rate, unity-gain stable, voltage-feedback op
amps usually achieve the slew rate at the expense of
a higher input noise voltage. However, the 8nV/√Hz
input voltage noise for the OPA2890 is much lower
than that of comparable amplifiers. The input-referred
voltage noise, and the two input-referred current
noise terms, combine to give low output noise under
a wide variety of operating conditions. Figure 60
shows the op amp noise analysis model with all the
noise terms included. In this model, all noise terms
are taken to be noise voltage or current density terms
in either nV/√Hz or pA/√Hz.
noise
and
frequency
response
flatness
considerations. Because the resistor-induced noise is
relatively negligible, additional capacitive decoupling
across the bias current cancellation resistor (RB) for
the inverting op amp configuration of Figure 59 is not
required.
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DC ACCURACY AND OFFSET CONTROL
+5V
Power-supply
The balanced input stage of
a
wideband
decoupling not shown.
voltage-feedback op amp allows good output dc
accuracy in a wide variety of applications. The
power-supply current trim for the OPA2890 gives
even tighter control than comparable amplifiers.
Although the high-speed input stage does require
relatively high input bias current (typically 5µA out of
each input terminal), the close matching between
them may be used to reduce the output dc error
caused by this current. The total output offset voltage
may be considerably reduced by matching the dc
source resistances appearing at the two inputs. This
matching reduces the output dc error resulting from
the input bias currents to the offset current times the
feedback resistor. Evaluating the configuration of
Figure 49, and using worst-case +25°C input offset
voltage and current specifications, gives a worst-case
output offset voltage equal to:
1/2
OPA2890
VO
0.1mF
261W
-5V
RG
RF
+5V
375W
750W
VI
5kW
5kW
±200mV Output Adjustment
20kW
10kW
0.1mF
V
RF
O = -
VI
= -2
RG
-5V
±(NG ´ VOS(MAX)) ± (RF ´ IOS(MAX)
)
Figure 61. DC-Coupled, Inverting Gain of –2, with
Offset Adjustment
= ±(2 ´ 5mV) ± (750W ´ 1.6mA)
= ±11.2mV with -(NG = noninverting signal gain)
DISABLE OPERATION (MSOP-10 Package
Only)
A fine-scale output offset null, or dc operating point
adjustment, is often required. Numerous techniques
are available for introducing dc offset control into an
op amp circuit. Most of these techniques eventually
reduce to adding a dc current through the feedback
resistor. In selecting an offset trim method, one key
consideration is the impact on the desired signal path
frequency response. If the signal path is intended to
be noninverting, the offset control is best applied as
an inverting summing signal to avoid interaction with
the signal source. If the signal path is intended to be
inverting, applying the offset control to the
noninverting input may be considered. However, the
dc offset voltage on the summing junction sets up a
dc current back into the source that must be
considered. Applying an offset adjustment to the
inverting op amp input can change the noise gain and
The OPA2890IDGS provides an optional disable
feature that can be used either to reduce system
power or to implement a simple channel multiplexing
operation. If the DIS control pin is left unconnected,
the OPA2890IDGS operates normally. To disable, the
control pin must be asserted LOW. Figure 62 shows
a simplified internal circuit for the disable control
feature.
+VS
50kW
frequency response flatness. For
a DC-coupled
inverting amplifier, Figure 61 shows one example of
an offset adjustment technique that has minimal
impact on the signal frequency response. In this
case, the dc offsetting current is brought into the
inverting input node through resistor values that are
much larger than the signal path resistors. This
configuration ensures that the adjustment circuit has
minimal effect on the loop gain and thus, the
frequency response.
Q1
200kW
2MW
IS
VDIS
Control
-VS
Figure 62. Simplified Disable Control Circuit
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In normal operation, base current to Q1 is provided
through the 2MΩ resistor, while the emitter current
through the 50kΩ resistor sets up a voltage drop that
is inadequate to turn on the two diodes in the Q1
emitter. As VDIS is pulled LOW, additional current is
pulled through the 50kΩ resistor, eventually turning
on those two diodes (≈30µA). At this point, any
further current pulled out of VDIS goes through those
diodes holding the emitter-base voltage of Q1 at
approximately 0V. This current shuts off the collector
current out of Q1, turning the amplifier off. The supply
currents in the disable mode are only those required
to operate the circuit of Figure 62. Additional circuitry
ensures that turn-on time occurs faster than turn-off
time (make-before-break).
Operating junction temperature (TJ) is given by TA +
PD × θJA. The total internal power dissipation (PD) is
the sum of quiescent power (PDQ) and additional
power dissipated in the output stage (PDL) to deliver
load power. Quiescent power is simply the specified
no-load supply current times the total supply voltage
across the part. PDL depends on the required output
signal and load; for a grounded resistive load, PDL is
at a maximum when the output is fixed at a voltage
equal to 1/2 of either supply voltage (for equal bipolar
2
supplies). Under this condition, PDL = VS /(4 × RL),
where RL includes feedback network loading.
Note that it is the power in the output stage and not
into the load that determines internal power
dissipation.
When disabled, the output and input nodes go to a
high-impedance state. If the OPA2890 is operating at
a gain of +1V/V, the device shows a very high
impedance at the output and exceptional signal
isolation. If operating at a gain greater than +1V/V,
the total feedback network resistance (RF + RG)
appears as the impedance looking back into the
output, but the circuit still shows very high forward
and reverse isolation. If configured as an inverting
amplifier, the input and output are connected through
the feedback network resistance (RF + RG) and the
isolation is very poor as a result.
As a worst-case example, compute the maximum TJ
using an OPA2890ID (SO-8 package) in the circuit of
Figure 49 operating at the maximum specified
ambient temperature of +85°C and with both outputs
driving a grounded 20Ω load to +2.5V.
PD = 10V ´ 2.5mA + 2[52/(4 ´ (75W || 1.5kW))] = 200mW
Maximum TJ = +85°C + (0.2W ´ 125°C/W) = 110°C
This absolute worst-case condition does not exceed
the specified maximum junction temperature. Actual
PDL is normally less than that considered here.
Carefully consider maximum TJ in your application.
THERMAL ANALYSIS
Maximum desired junction temperature sets the
maximum allowed internal power dissipation as
described below. In no case should the maximum
junction temperature be allowed to exceed +150°C.
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BOARD LAYOUT GUIDELINES
can add a pole and/or zero below 500MHz that can
effect circuit operation. Keep resistor values as low
as possible consistent with load driving
considerations. The 750Ω feedback used in the
Electrical Characteristics is a good starting point for
design. Note that a 0Ω feedback resistor is suggested
for the unity-gain follower application.
Achieving
optimum
performance
with
a
high-frequency amplifier such as the OPA2890
requires careful attention to board layout parasitics
and external component types. Recommendations
that optimize performance include:
a) Minimize parasitic capacitance to any ac ground
for all of the signal I/O pins. Parasitic capacitance on
the output and inverting input pins can cause
instability: on the noninverting input, it can react with
the source impedance to cause unintentional
bandlimiting. To reduce unwanted capacitance, a
window around the signal I/O pins should be opened
in all of the ground and power planes around those
pins. Otherwise, ground and power planes should be
unbroken elsewhere on the board.
d) Connections to other wideband devices on the
board may be made with short, direct traces or
through onboard transmission lines. For short
connections, consider the trace and the input to the
next device as a lumped capacitive load. Relatively
wide traces (50mils to 100mils, or 1.27mm to
2.54mm) should be used, preferably with ground and
power planes opened up around them. Estimate the
total capacitive load and set RS from the plots of
Figure 15 and Figure 36. Low parasitic capacitive
loads (< 3pF) may not need an RS because the
OPA2890 is nominally compensated to operate with a
2pF parasitic load. Higher parasitic capacitive loads
without an RS are allowed as the signal gain
increases (increasing the unloaded phase margin;
see Figure 61). If a long trace is required, and the
6dB signal loss intrinsic to a doubly-terminated
transmission line is acceptable, implement a matched
impedance transmission line using microstrip or
stripline techniques (consult an ECL design handbook
for microstrip and stripline layout techniques). A 50Ω
environment is normally not necessary on board, and
in fact, a higher impedance environment improves
distortion as shown in the distortion versus load plots.
With a characteristic board trace impedance defined
(based on board material and trace dimensions), a
matching series resistor into the trace from the output
of the OPA2890 is used as well as a terminating
shunt resistor at the input of the destination device.
Remember also that the terminating impedance is the
parallel combination of the shunt resistor and the
input impedance of the destination device; this total
effective impedance should be set to match the trace
impedance.
b) Minimize the distance (< 0.25in, or 6.35mm) from
the power-supply pins to high-frequency 0.1µF
decoupling capacitors. At the device pins, the ground
and power-plane layout should not be in close
proximity to the signal I/O pins. Avoid narrow power
and ground traces to minimize inductance between
the pins and the decoupling capacitors. The
power-supply connections should always be
decoupled with these capacitors. An optional supply
decoupling capacitor (0.1µF) across the two power
supplies
(for
bipolar
operation)
improves
2nd-harmonic distortion performance. Larger (2.2µF
to 6.8µF) decoupling capacitors, effective at lower
frequencies, should also be used on the main supply
pins. These capacitors may be placed somewhat
farther from the device and may be shared among
several devices in the same area of the printed circuit
board (PCB).
c) Careful selection and placement of external
components
preserves
the
high-frequency
performance of the OPA2890. Resistors should be
a very low reactance type. Surface-mount resistors
work best and allow a tighter overall layout. Metal film
or carbon composition axially-leaded resistors can
also provide good high-frequency performance.
Again, keep the leads and PCB traces as short as
possible. Never use wirewound type resistors in a
high-frequency application. Because the output pin
and inverting input pin are the most sensitive to
parasitic capacitance, always position the feedback
and series output resistor, if any, as close as possible
to the output pin. Other network components, such as
noninverting input termination resistors, should also
be placed close to the package. Even with a low
parasitic capacitance shunting the external resistors,
excessively high resistor values can create significant
time constants that can degrade performance. Good
axial metal film or surface-mount resistors have
approximately 0.2pF in shunt with the resistor. For
resistor values > 1.5kΩ, this parasitic capacitance
e) Socketing a high-speed part such as the
OPA2890 is not recommended. The additional lead
length and pin-to-pin capacitance introduced by the
socket can create an extremely troublesome parasitic
network that can make it almost impossible to
achieve a smooth, stable frequency response. Best
results are obtained by soldering the OPA2890 onto
the board.
Copyright © 2007–2008, Texas Instruments Incorporated
Submit Documentation Feedback
27
Product Folder Link(s): OPA2890
OPA2890
SBOS364B–DECEMBER 2007–REVISED MAY 2008.................................................................................................................................................... www.ti.com
INPUT AND ESD PROTECTION
+VCC
The OPA2890 is built using a very high-speed
complementary bipolar process. The internal junction
breakdown voltages are relatively low for these very
small geometry devices. These breakdowns are
reflected in the Absolute Maximum Ratings table. All
device pins are protected with internal ESD protection
diodes to the power supplies, as shown in Figure 63.
External
Pin
Internal
Circuitry
-VCC
Figure 63. Internal ESD Protection
These diodes provide moderate protection to input
overdrive voltages above the supplies as well. The
protection diodes can typically support 30mA
continuous current. Where higher currents are
possible (for example, in systems with ±15V supply
parts driving into the OPA2890), current-limiting
series resistors should be added into the two inputs.
Keep these resistor values as low as possible since
high values degrade both noise performance and
frequency response.
28
Submit Documentation Feedback
Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Link(s): OPA2890
OPA2890
www.ti.com.................................................................................................................................................... SBOS364B–DECEMBER 2007–REVISED MAY 2008
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (December 2007) to Revision B ........................................................................................... Page
•
•
Changed storage temperature range rating in Absolute Maximum Ratings table from –40°C to +125°C to –65°C to
+125°C................................................................................................................................................................................... 2
Changed typical specification from 15 to ±15 in minimum operating voltage parameter of Power Supply section of
±5V Electrical Characteristics ................................................................................................................................................ 3
Changes from Original (December, 2007) to Revision A ............................................................................................... Page
Corrected CMRR characteristic values.................................................................................................................................. 3
•
Copyright © 2007–2008, Texas Instruments Incorporated
Submit Documentation Feedback
29
Product Folder Link(s): OPA2890
PACKAGE OPTION ADDENDUM
www.ti.com
19-May-2008
PACKAGING INFORMATION
Orderable Device
OPA2890ID
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
8
75 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
OPA2890IDG4
SOIC
MSOP
MSOP
MSOP
MSOP
SOIC
D
8
75 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
OPA2890IDGSR
OPA2890IDGSRG4
OPA2890IDGST
OPA2890IDGSTG4
OPA2890IDR
DGS
DGS
DGS
DGS
D
10
10
10
10
8
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
OPA2890IDRG4
SOIC
D
8
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Nov-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
OPA2890IDGSR
OPA2890IDGST
OPA2890IDR
MSOP
MSOP
SOIC
DGS
DGS
D
10
10
8
2500
250
330.0
180.0
330.0
12.4
12.4
12.4
5.3
5.3
6.4
3.4
3.4
5.2
1.4
1.4
2.1
8.0
8.0
8.0
12.0
12.0
12.0
Q1
Q1
Q1
2500
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Nov-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA2890IDGSR
OPA2890IDGST
OPA2890IDR
MSOP
MSOP
SOIC
DGS
DGS
D
10
10
8
2500
250
346.0
190.5
346.0
346.0
212.7
346.0
29.0
31.8
29.0
2500
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
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TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
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