OPA322 [TI]
20-MHz, Low-Noise, 1.8-V, RRI/O, CMOS Operational Amplifier with Shutdown; 20兆赫，低噪声， 1.8 -V ， RRI / O， CMOS运算与关断放大器
| 型号： | OPA322 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 20-MHz, Low-Noise, 1.8-V, RRI/O, CMOS Operational Amplifier with Shutdown |
| 文件： | 总36页 (文件大小：1684K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OPA322, OPA322S
OPA2322, OPA2322S
OPA4322, OPA4322S
www.ti.com
SBOS538E –JANUARY 2011–REVISED JUNE 2012
20-MHz, Low-Noise, 1.8-V, RRI/O,
CMOS Operational Amplifier with Shutdown
Check for Samples: OPA322, OPA322S, OPA2322, OPA2322S, OPA4322, OPA4322S
1
FEATURES
DESCRIPTION
The OPA322 series consists of single, dual, and
23
•
Gain Bandwidth: 20 MHz
Low Noise: 8.5 nV/√Hz at 1 kHz
Slew Rate: 10 V/μs
quad-channel CMOS operational amplifiers featuring
low noise and rail-to-rail inputs/outputs optimized for
low-power, single-supply applications. Specified over
a wide supply range of 1.8 V to 5.5 V, the low
quiescent current of only 1.5 mA per channel makes
these devices well-suited for power-sensitive
applications.
•
•
•
•
•
•
•
Low THD+N: 0.0005%
Rail-to-Rail I/O
Offset Voltage: 2 mV (max)
Supply Voltage: 1.8 V to 5.5 V
Supply Current: 1.5 mA/ch
The combination of very low noise (8.5 nV/√Hz at
1 kHz), high gain-bandwidth (20 MHz), and fast slew
rate (10 V/μs) make the OPA322 family ideal for a
wide range of applications, including signal
conditioning and sensor amplification requiring high
gains. Featuring low THD+N, the OPA322 series is
also excellent for consumer audio applications,
particularly for single-supply systems.
–
Shutdown: 0.1 μA/ch
•
•
Unity-Gain Stable
Small Packages:
–
SOT23, DFN, MSOP, TSSOP
APPLICATIONS
The OPAx322S models include a shutdown mode
allowing the amplifiers to be switched from normal
operation to a standby current that is typically less
than 0.1 μA.
•
•
•
•
•
•
•
Sensor Signal Conditioning
Consumer Audio
Multi-Pole Active Filters
Control-Loop Amplifiers
Communications
Security
The OPA322 (single version) is available in SOT23-5
and SOT23-6, while the OPA2322 (dual version) is
offered in MSOP-8, MSOP-10, SO-8, and DFN-8
packages. The quad versions OPA4322 come in
TSSOP-14 and TSSOP-16 packages. All versions are
specified for operation from –40°C to +125°C.
Scanners
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
FilterPro is a trademark of Texas Instruments Incorporated.
All other trademarks are the property of their respective owners.
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2012, Texas Instruments Incorporated
OPA322, OPA322S
OPA2322, OPA2322S
OPA4322, OPA4322S
SBOS538E –JANUARY 2011–REVISED JUNE 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION(1)
PACKAGE
PRODUCT
OPA322
PACKAGE-LEAD
SOT23-5
SOT23-6
SO-8
DESIGNATOR
PACKAGE MARKING
DBV
DBV
D
RAD
RAF
OPA322S
O2322A
OOZI
OPA2322
MSOP-8
DGK
DRG
DGS
PW
DFN-8
OPCI
OPA2322S
OPA4322
MSOP-10
TSSOP-14
TSSOP-16
OPBI
O4322
O4322SA
OPA4322S
PW
(1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or visit
the device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range, unless otherwise noted.
OPA322, OPA322S, OPA2322,
OPA2322S, OPA4322, OPA4322S
UNIT
V
Supply voltage, VS = (V+) – (V–)
6
(V–) – 0.5 to (V+) + 0.5
±10
Voltage(2)
Current(2)
V
Signal input pins
mA
mA
°C
°C
°C
V
Output short-circuit current(3)
Operating temperature, TA
Storage temperature, Tstg
Junction temperature, TJ
Continuous
–40 to +150
–65 to +150
+150
Human body model (HBM)
4000
ESD ratings
Charged device model (CDM)
Machine model (MM)
1000
V
200
V
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails should
be current limited to 10 mA or less.
(3) Short-circuit to ground, one amplifier per package.
2
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Product Folder Link(s): OPA322 OPA322S OPA2322 OPA2322S OPA4322 OPA4322S
OPA322, OPA322S
OPA2322, OPA2322S
OPA4322, OPA4322S
www.ti.com
SBOS538E –JANUARY 2011–REVISED JUNE 2012
ELECTRICAL CHARACTERISTICS: VS = +1.8 V to +5.5 V, or ±0.9 V to ±2.75 V
Boldface limits apply over the specified temperature range, TA = –40°C to +125°C.
At TA = +25°C, RL = 10 kΩ connected to VS/2, VCM = VS/2, VOUT = VS/2, and SHDN_x = VS+, unless otherwise noted.
OPA322, OPA322S, OPA2322,
OPA2322S, OPA4322, OPA4322S
PARAMETER
OFFSET VOLTAGE
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Input offset voltage
vs Temperature
VOS
dVOS/dT
PSR
0.5
1.8
10
2
6
mV
μV/°C
μV/V
μV/V
dB
VS = +5.5 V
VS = +1.8 V to +5.5 V
VS = +1.8 V to +5.5 V
At 1 kHz
vs Power supply
50
65
Over temperature
20
Channel separation
INPUT VOLTAGE
130
Common-mode voltage range
Common-mode rejection ratio
Over temperature
VCM
(V–) – 0.1
(V+) + 0.1
V
CMRR
(V–) – 0.1 V < VCM < (V+) + 0.1 V
90
100
dB
dB
90
INPUT BIAS CURRENT
Input bias current
IB
±0.2
±10
±50
pA
pA
pA
pA
pA
pA
pA
pA
TA = –40°C to +85°C
OPA322, OPA322S, TA = –40°C to +125°C
OPA2322, OPA2322S, TA = –40°C to +125°C
OPA4322, OPA4322S, TA = –40°C to +125°C
±800
±400
±400
±10
Over temperature
Input offset current
IOS
±0.2
TA = –40°C to +85°C
TA = –40°C to +125°C
±50
Over temperature
±400
NOISE
Input voltage noise
f = 0.1 Hz to 10 Hz
f = 1 kHz
2.8
8.5
7
μVPP
nV/√Hz
nV/√Hz
fA/√Hz
Input voltage noise density
en
in
f = 10 kHz
Input current noise density
INPUT CAPACITANCE
Differential
f = 1 kHz
0.6
5
4
pF
pF
Common-mode
OPEN-LOOP GAIN
0.1 V < VO < (V+) – 0.1 V, RL = 10 kΩ
0.1 V < VO < (V+) – 0.1 V, RL = 10 kΩ
VS = 5 V, CL = 50 pF
100
130
47
dB
dB
Open-loop voltage gain
AOL
PM
94
Phase margin
Degrees
FREQUENCY RESPONSE
Gain bandwidth product
Slew rate
VS = 5.0 V, CL = 50 pF
GBP
SR
Unity gain
20
10
MHz
V/μs
μs
G = +1
To 0.1%, 2-V step, G = +1
To 0.01%, 2-V step, G = +1
VIN × G > VS
0.25
0.32
100
Settling time
tS
μs
Overload recovery time
ns
VO = 4 VPP, G = +1, f = 10 kHz, RL = 10 kΩ
VO = 2 VPP, G = +1, f = 10 kHz, RL = 600 Ω
0.0005
0.0011
%
Total harmonic distortion +
noise(1)
THD+N
%
(1) Third-order filter; bandwidth = 80 kHz at –3 dB.
Copyright © 2011–2012, Texas Instruments Incorporated
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OPA322, OPA322S
OPA2322, OPA2322S
OPA4322, OPA4322S
SBOS538E –JANUARY 2011–REVISED JUNE 2012
www.ti.com
ELECTRICAL CHARACTERISTICS: VS = +1.8 V to +5.5 V, or ±0.9 V to ±2.75 V (continued)
Boldface limits apply over the specified temperature range, TA = –40°C to +125°C.
At TA = +25°C, RL = 10 kΩ connected to VS/2, VCM = VS/2, VOUT = VS/2, and SHDN_x = VS+, unless otherwise noted.
OPA322, OPA322S, OPA2322,
OPA2322S, OPA4322, OPA4322S
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
Voltage output swing from
both rails
VO
RL = 10 kΩ
10
20
mV
Over temperature
Short-circuit current
RL = 10 kΩ
30
mV
ISC
CL
RO
VS = 5.5 V
±65
mA
Capacitive load drive
Open-loop output resistance
POWER SUPPLY
See Typical Characteristics
90
IO = 0 mA, f = 1 MHz
Ω
Specified voltage range
Quiescent current per amplifier
OPA322, OPA322S
Over temperature
VS
IQ
1.8
5.5
V
IO = 0 mA, VS = +5.5 V
IO = 0 mA, VS = +5.5 V
IO = 0 mA, VS = +5.5 V
IO = 0 mA, VS = +5.5 V
IO = 0 mA, VS = +5.5 V
IO = 0 mA, VS = +5.5 V
IO = 0 mA, VS = +5.5 V
VS+ = 0 V to 5 V, to 90% IQ level
VS = 1.8 V to 5.5 V
1.6
1.5
1.4
28
1.9
2
mA
mA
mA
mA
mA
mA
μs
OPA2322, OPA2322S
Over temperature
1.75
1.85
1.65
1.75
OPA4322, OPA4322S
Over temperature
Power-on time
SHUTDOWN(2)
Quiescent current, per amplifier
High voltage (enabled)
Low voltage (disabled)
IQSD
VIH
VIL
All amplifiers disabled, SHDN = VS–
Amplifier enabled
0.1
0.5
µA
V
(V+) - 0.1
Amplifier disabled
(V-) + 0.1
V
Amplifier enable time (full
shutdown)(3)
(4)
tON
Full shutdown; G = 1, VOUT = 0.9 × VS/2
10
6
µs
µs
Amplifier enable time (partial
(4)
tON Partial shutdown; G = 1, VOUT = 0.9 × VS/2
(3)
shutdown)
Amplifier disable time(3)
tOFF
G = 1, VOUT = 0.1 × VS/2
VIH = 5.0 V
3
µs
µA
µA
0.13
0.04
SHDN pin input bias current (per pin)
VIL = 0 V
TEMPERATURE
Specified range
Operating range
–40
–40
+125
+150
°C
°C
(2) Ensured by design and characterization; not production tested.
(3) Disable time (tOFF) and enable time (tON) are defined as the time interval between the 50% point of the signal applied to the SHDN pin
and the point at which the output voltage reaches the 10% (disable) or 90% (enable) level.
(4) Full shutdown refers to the dual OPA2322S having both channels A and B disabled (SHDN_A = SHDN_B = VS–) and the quad
OPA4322S having all channels A to D disabled (SHDN_A/B = SHDN_C/D = VS–). For partial shutdown, only one SHDN pin is exercised;
in this mode, the internal biasing and oscillator remain operational and the enable time is shorter.
4
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Product Folder Link(s): OPA322 OPA322S OPA2322 OPA2322S OPA4322 OPA4322S
OPA322, OPA322S
OPA2322, OPA2322S
OPA4322, OPA4322S
www.ti.com
SBOS538E –JANUARY 2011–REVISED JUNE 2012
THERMAL INFORMATION: OPA322
OPA322
OPA322S
DBV
THERMAL METRIC(1)
DBV
5 PINS
219.3
107.5
57.5
UNITS
6 PINS
177.5
108.9
27.4
θJA
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
θJC(top)
θJB
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
7.4
13.3
ψJB
56.9
26.9
θJC(bottom)
n/a
n/a
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
THERMAL INFORMATION: OPA2322
OPA2322
DRG
8 PINS
50.6
OPA2322S
DGS
THERMAL METRIC(1)
D
8 PINS
122.6
67.1
64.0
13.2
63.4
n/a
DGK
8 PINS
174.8
43.9
95.0
2.0
10 PINS
171.5
43.0
UNITS
θJA
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
θJC(top)
θJB
54.9
25.2
91.4
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
0.6
1.9
ψJB
25.3
93.5
n/a
89.9
θJC(bottom)
5.7
n/a
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
THERMAL INFORMATION: OPA4322
OPA4322
PW
OPA4322S
PW
THERMAL METRIC(1)
14 PINS
109.8
34.9
16 PINS
105.9
28.1
UNITS
θJA
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
θJC(top)
θJB
52.5
51.1
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
2.2
0.8
ψJB
51.8
50.4
θJC(bottom)
n/a
n/a
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2011–2012, Texas Instruments Incorporated
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Product Folder Link(s): OPA322 OPA322S OPA2322 OPA2322S OPA4322 OPA4322S
OPA322, OPA322S
OPA2322, OPA2322S
OPA4322, OPA4322S
SBOS538E –JANUARY 2011–REVISED JUNE 2012
www.ti.com
PIN CONFIGURATIONS
DBV PACKAGE
SOT23-5
(TOP VIEW)
DRG PACKAGE(1)(2)
DFN-8
(TOP VIEW)
V+
OUT
V-
1
2
3
5
4
8
V+
OUT A
-IN A
+IN A
V-
1
2
3
4
Exposed
Thermal
Die Pad
on
7
OUT B
-IN B
+IN B
-IN
+IN
6
5
Underside
DBV PACKAGE
SOT23-6
(TOP VIEW)
PW PACKAGE
TSSOP-14
(TOP VIEW)
VOUT
V-
1
6
5
4
V+
2
3
SHDN
OUT A
-IN A
1
14 OUT D
13 -IN D
12 +IN D
11 V-
+IN
-IN
A
D
2
3
4
5
6
7
+IN A
V+
DGS PACKAGE
MSOP-10
+IN B
-IN B
OUT B
10
9
+IN C
-IN C
OUT C
(TOP VIEW)
B
C
V+
VOUT A
1
2
3
4
5
10
9
8
VOUT B
-IN B
-IN A
+IN A
A
8
B
PW PACKAGE
TSSOP-16
(TOP VIEW)
+IN B
SHDN B
V-
7
SHDN A
6
OUT A
-IN A
1
2
3
4
5
6
7
8
16 OUT D
15 -IN D
14 +IN D
13 V-
A
D
D, DGK PACKAGES
SO-8, MSOP-8
(TOP VIEW)
+IN A
V+
OUT A
-IN A
+IN A
V-
1
8
V+
+IN B
12
+IN C
A
2
3
4
7
6
5
OUT B
-IN B
+IN B
-IN B
11 -IN C
B
C
B
OUT B
SHDN A/B
10 OUT C
9
SHDN C/D
(1) Connect thermal pad to V–.
(2) Pad size: 2mm × 1.2mm.
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Product Folder Link(s): OPA322 OPA322S OPA2322 OPA2322S OPA4322 OPA4322S
OPA322, OPA322S
OPA2322, OPA2322S
OPA4322, OPA4322S
www.ti.com
SBOS538E –JANUARY 2011–REVISED JUNE 2012
TYPICAL CHARACTERISTICS
At TA = +25°C, VCM = VOUT = mid-supply, and RL = 10 kΩ, unless otherwise noted.
OPEN-LOOP GAIN/PHASE vs FREQUENCY
OPEN-LOOP GAIN vs TEMPERATURE
125
120
115
110
105
100
95
140
120
100
80
-20
RL = 10 kW, 50 pF
VS = ±2.5 V
-40
10 kW Load
-60
-80
2 kW Load
60
-100
-120
-140
-160
-180
40
20
Gain
0
90
Phase
-20
85
1
10
100
1k
10k 100k
1M
10M 100M
-50
-25
0
25
50
75
100
125
150
Frequency (Hz)
Temperature (°C)
Figure 1.
Figure 2.
INPUT BIAS CURRENT vs SUPPLY VOLTAGE
INPUT BIAS CURRENT vs COMMON-MODE VOLTAGE
1
0.8
6
5
4
0.6
3
0.4
2
0.2
1
0
0
-1
-2
-0.2
-0.4
-0.6
-0.8
-1
-3
IB+
-4
IB-
IB-
-5
-6
IB+
IOS
0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9
-3 -2.5 -2 -1.5 -1 -0.5
0
0.5
1
1.5
2
2.5
3
Supply Voltage (±V)
Common-Mode Voltage (V)
Figure 3.
Figure 4.
INPUT BIAS CURRENT vs TEMPERATURE
QUIESCENT CURRENT vs SUPPLY VOLTAGE
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
1.6
1.55
1.5
IOS
IB+
IB-
1.45
1.4
+125°C
+85°C
+25°C
-40°C
IB
1.35
1.3
IOS
-100
-50
-25
0
25
50
75
100
125
150
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Temperature (°C)
Supply Voltage (V)
Figure 5.
Figure 6.
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OPA322, OPA322S
OPA2322, OPA2322S
OPA4322, OPA4322S
SBOS538E –JANUARY 2011–REVISED JUNE 2012
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VCM = VOUT = mid-supply, and RL = 10 kΩ, unless otherwise noted.
OFFSET VOLTAGE PRODUCTION HISTOGRAM
OFFSET VOLTAGE vs COMMON-MODE VOLTAGE
1
14
12
10
8
0.8
0.6
0.4
0.2
0
6
-0.2
-0.4
-0.6
-0.8
-1
4
2
Representative Units
VS = ±2.75 V
0
-3
-2
-1
0
1
2
3
Common-Mode Voltage (V)
Offset Voltage (mV)
Figure 7.
Figure 8.
INPUT VOLTAGE NOISE SPECTRAL DENSITY vs
FREQUENCY
0.1 Hz TO 10 Hz INPUT VOLTAGE NOISE
1000
100
10
6
5
VS = 1.8 V to 5.5 V
4
3
2
1
0
-1
-2
-3
-4
1
10
100
1 k
10 k
100 k
1 M
0
1
2
3
4
5
6
7
8
9
10
Frequency (Hz)
Time (s)
Figure 9.
Figure 10.
CLOSED-LOOP GAIN vs FREQUENCY
CLOSED-LOOP GAIN vs FREQUENCY
60
40
20
0
60
40
20
0
VS = +1.8 V
VS = +5.5 V
RL = 10 kW
RL = 10 kW
G = +100 V/V
G = +100 V/V
CL = 50 pF
CL = 50 pF
G = +10 V/V
G = +1 V/V
G = +10 V/V
G = +1 V/V
-20
-20
10 k
100 k
1 M
10 M
100 M
10 k
100 k
1 M
10 M
100 M
Frequency (Hz)
Frequency (Hz)
Figure 11.
Figure 12.
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OPA4322, OPA4322S
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SBOS538E –JANUARY 2011–REVISED JUNE 2012
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VCM = VOUT = mid-supply, and RL = 10 kΩ, unless otherwise noted.
MAXIMUM OUTPUT VOLTAGE vs FREQUENCY
OUTPUT VOLTAGE SWING vs OUTPUT CURRENT
6
5
4
3
2
1
0
3
5.5 VS
2
1
3.3 VS
-40°C
+25°C
+125°C
0
-1
-2
-3
1.8 VS
RL = 10 kW
CL = 50 pF
VS = ±2.75 V
60
70 80
10 k
100 k
Frequency (Hz)
1 M
10 M
0
10
20
30
40
50
Output Current (mA)
Figure 13.
Figure 14.
OPEN-LOOP OUTPUT IMPEDANCE vs FREQUENCY
SMALL-SIGNAL OVERSHOOT vs LOAD CAPACITANCE
1000
70
G = 1, VS = 1.8 V
VS = ±±2.7 V
60
50
40
30
20
10
0
G = 1, VS = 5.5 V
G = 10, VS = 1.8 V
G = 10, VS = 5.5 V
100
10
1
10
100
1 k
10 k 100 k 1 M 10 M 100 M
0
500
1000
1500
2000
2500
3000
Frequency (Hz)
Capacitive Load (pF)
Figure 15.
Figure 16.
THD+N vs AMPLITUDE
THD+N vs FREQUENCY
0.1
0.1
Frequency = 10 kHz
VIN = 2 VPP
VS = ±2.5 V
G = +1 V/V
0.01
0.001
0.01
0.001
Load = 600 W
Load = 600 W
Frequency = 10 kHz
VS = ±2.5 V
Load = 10 kW
Load = 10 kW
G = +1 V/V
0.0001
0.0001
10
100
1 k
10 k
100 k
0.01
0.1
1
10
Frequency (Hz)
VIN (VPP
)
Figure 17.
Figure 18.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VCM = VOUT = mid-supply, and RL = 10 kΩ, unless otherwise noted.
THD+N vs FREQUENCY
CHANNEL SEPARATION vs FREQUENCY (for Dual)
0.1
0
Frequency = 10 kHz
VS = ±2.75 V
VIN = 4 VPP
VS = ±2.5 V
G = +1 V/V
-20
-40
0.01
-60
Load = 600 W
-80
0.001
0.0001
-100
-120
-140
Load = 10 kW
10
100
1 k
10 k
100 k
1 k
10 k
100 k
1 M
10 M
100 M
Frequency (Hz)
Frequency (Hz)
Figure 19.
Figure 20.
SLEW RATE vs SUPPLY VOLTAGE
SMALL-SIGNAL STEP RESPONSE
12
11.5
11
0.1
Gain = +1
VS = ±2.75 V
CL = 50 pF
0.075
0.05
VIN = 100 mVPP
0.025
0
Rise
10.5
10
Fall
-0.025
-0.05
-0.075
-0.1
9.5
9
VOUT
VIN
1.6
2
2.4 2.8 3.2 3.6
4
4.4 4.8 5.2 5.6
-0.8
-0.4
0
0.4
0.8
1.2
1.6
Supply Voltage (V)
Time (ms)
Figure 21.
Figure 22.
SMALL-SIGNAL STEP RESPONSE
LARGE-SIGNAL STEP RESPONSE vs TIME
0.1
1.5
1
Gain = +1
VS = ±2.75 V
0.075
0.05
VIN = 2 VPP
VIN
0.5
0
Gain = -1
0.025
0
VOUT
VS = ±2.75 V
VIN = 100 mVPP
-0.025
-0.05
-0.075
-0.1
-0.5
-1
VOUT
VIN
-1.5
-1.6
-1.2
-0.8
-0.4
0
0.4
0.8
-0.4
0
0.4
0.8
1.2
1.6
Time (ms)
Time (ms)
Figure 23.
Figure 24.
10
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SBOS538E –JANUARY 2011–REVISED JUNE 2012
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VCM = VOUT = mid-supply, and RL = 10 kΩ, unless otherwise noted.
CMRR AND PSRR vs FREQUENCY
TURN-OFF TRANSIENT
120
100
80
60
40
20
0
3
2.4
Shutdown Signal
Output Signal
1.8
1.2
0.6
0
−0.6
−1.2
−1.8
−2.4
−3
PSRR
CMRR
0
2
4
6
8
10
Time (µs)
12
14
16
18
20
100
1k
10k
100k
1M
G000
Frequency (Hz)
Figure 25.
Figure 26.
TURN-ON AND TURN-OFF TRANSIENT 5.5V
(High Supply)
TURN-ON TRANSIENT
3
2.4
5
4.5
4
Shutdown Signal
Output Signal
3.5
3
1.8
2.5
2
1.2
1.5
1
0.6
0.5
0
0
−0.5
−1
−0.6
−1.2
−1.8
−2.4
−3
−1.5
−2
−2.5
−3
−3.5
−4
Shutdown Signal
Output Signal
−4.5
−5
0
2
4
6
8
10
12
14
16
18
20
0
200 400 600 800 1000 1200 1400 1600 1800 2000
Time (µs)
Time (µs)
G000
G000
Figure 27.
Figure 28.
TURN-ON AND TURN-OFF TRANSIENT 1.8V
(Low Supply)
2
1.5
1
0.5
0
−0.5
−1
Shutdown Signal
Output Signal
−1.5
−2
0
200 400 600 800 1000 1200 1400 1600 1800 2000
Time (µs)
G000
Figure 29.
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APPLICATION INFORMATION
OPERATING VOLTAGE
The OPA322 series op amps are unity-gain stable and can operate on a single-supply voltage (1.8 V to 5.5 V), or
a split-supply voltage (±0.9 V to ±2.75 V), making them highly versatile and easy to use. The power-supply pins
should have local bypass ceramic capacitors (typically 0.001 μF to 0.1 μF). These amplifiers are fully specified
from +1.8 V to +5.5 V and over the extended temperature range of –40°C to +125°C. Parameters that can exhibit
variance with regard to operating voltage or temperature are presented in the Typical Characteristics.
INPUT AND ESD PROTECTION
The OPA322 incorporates internal electrostatic discharge (ESD) protection circuits on all pins. In the case of
input and output pins, this protection primarily consists of current-steering diodes connected between the input
and power-supply pins. These ESD protection diodes also provide in-circuit input overdrive protection, as long as
the current is limited to 10 mA as stated in the Absolute Maximum Ratings table. Many input signals are
inherently current-limited to less than 10 mA; therefore, a limiting resistor is not required. Figure 30 shows how a
series input resistor (RS) may be added to the driven input to limit the input current. The added resistor
contributes thermal noise at the amplifier input and the value should be kept to the minimum in noise-sensitive
applications.
V+
IOVERLOAD
10 mA, Max
VOUT
OPA322
VIN
RS
Figure 30. Input Current Protection
PHASE REVERSAL
The OPA322 op amps are designed to be immune to phase reversal when the input pins exceed the supply
voltages, therefore providing further in-system stability and predictability. Figure 31 shows the input voltage
exceeding the supply voltage without any phase reversal.
4
VIN
VS = ±2.5 V
3
2
VOUT
1
0
-1
-2
-3
-4
-500
-250
0
250
500
750
1000
Time (ms)
Figure 31. No Phase Reversal
12
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OPA4322, OPA4322S
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SBOS538E –JANUARY 2011–REVISED JUNE 2012
FEEDBACK CAPACITOR IMPROVES RESPONSE
For optimum settling time and stability with high-impedance feedback networks, it may be necessary to add a
feedback capacitor across the feedback resistor, RF, as shown in Figure 32. This capacitor compensates for the
zero created by the feedback network impedance and the OPA322 input capacitance (and any parasitic layout
capacitance). The effect becomes more significant with higher impedance networks.
CF
RIN
RF
V+
VIN
CIN
R
IN ´ CIN = RF ´ CF
VOUT
OPA322
CL
CIN
NOTE: Where CIN is equal to the OPA322 input capacitance (approximately 9 pF) plus any parasitic layout capacitance.
Figure 32. Feedback Capacitor Improves Dynamic Performance
It is suggested that a variable capacitor be used for the feedback capacitor because input capacitance may vary
between op amps and layout capacitance is difficult to determine. For the circuit shown in Figure 32, the value of
the variable feedback capacitor should be chosen so that the input resistance times the input capacitance of the
OPA322 (typically 9 pF) plus the estimated parasitic layout capacitance equals the feedback capacitor times the
feedback resistor:
RIN × CIN = RF × CF
Where:
CIN is equal to the OPA322 input capacitance (sum of differential and common-mode) plus the layout
capacitance.
The capacitor value can be adjusted until optimum performance is obtained.
EMI SUSCEPTIBILITY AND INPUT FILTERING
Operational amplifiers vary in susceptibility to electromagnetic interference (EMI). If conducted EMI enters the
device, the dc offset observed at the amplifier output may shift from the nominal value while EMI is present. This
shift is a result of signal rectification associated with the internal semiconductor junctions. While all operational
amplifier pin functions can be affected by EMI, the input pins are likely to be the most susceptible. The OPA322
operational amplifier family incorporates an internal input low-pass filter that reduces the amplifier response to
EMI. Both common-mode and differential mode filtering are provided by the input filter. The filter is designed for a
cutoff frequency of approximately 580 MHz (–3 dB), with a roll-off of 20 dB per decade.
OUTPUT IMPEDANCE
The open-loop output impedance of the OPA322 common-source output stage is approximately 90 Ω. When the
op amp is connected with feedback, this value is reduced significantly by the loop gain. For each decade rise in
the closed-loop gain, the loop gain is reduced by the same amount, which results in a ten-fold increase in
effective output impedance. While the OPA322 output impedance remains very flat over a wide frequency range,
at higher frequencies the output impedance rises as the open-loop gain of the op amp drops. However, at these
frequencies the output also becomes capacitive as a result of parasitic capacitance. This characteristic, in turn,
prevents the output impedance from becoming too high, which can cause stability problems when driving large
capacitive loads. As mentioned previously, the OPA322 has excellent capacitive load drive capability for an op
amp with its bandwidth.
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OPA4322, OPA4322S
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CAPACITIVE LOAD AND STABILITY
The OPA322 is designed to be used in applications where driving a capacitive load is required. As with all op
amps, there may be specific instances where the OPA322 can become unstable. The particular op amp circuit
configuration, layout, gain, and output loading are some of the factors to consider when establishing whether an
amplifier is stable in operation. An op amp in the unity-gain (+1 V/V) buffer configuration and driving a capacitive
load exhibits a greater tendency to become unstable than an amplifier operated at a higher noise gain. The
capacitive load, in conjunction with the op amp output resistance, creates a pole within the feedback loop that
degrades the phase margin. The degradation of the phase margin increases as the capacitive loading increases.
When operating in the unity-gain configuration, the OPA322 remains stable with a pure capacitive load up to
approximately 1 nF.
The equivalent series resistance (ESR) of some very large capacitors (CL > 1 µF) is sufficient to alter the phase
characteristics in the feedback loop such that the amplifier remains stable. Increasing the amplifier closed-loop
gain allows the amplifier to drive increasingly larger capacitance. This increased capability is evident when
observing the overshoot response of the amplifier at higher voltage gains, as shown in Figure 33. One technique
for increasing the capacitive load drive capability of the amplifier operating in unity gain is to insert a small
resistor (RS), typically 10 Ω to 20 Ω, in series with the output, as shown in Figure 34.
This resistor significantly reduces the overshoot and ringing associated with large capacitive loads. A possible
problem with this technique is that a voltage divider is created with the added series resistor and any resistor
connected in parallel with the capacitive load. The voltage divider introduces a gain error at the output that
reduces the output swing. The error contributed by the voltage divider, however, may be insignificant. For
instance, with a load resistance, RL = 10 kΩ and RS = 20 Ω, the gain error is only about 0.2%. However, when RL
is decreased to 600 Ω, which the OPA322 is able to drive, the error increases to 7.5%.
70
G = 1, VS = 1.8 V
60
50
40
30
20
10
0
G = 1, VS = 5.5 V
G = 10, VS = 1.8 V
G = 10, VS = 5.5 V
0
500
1000
1500
2000
2500
3000
Capacitive Load (pF)
Figure 33. Small-Signal Overshoot versus Capacitive Load (100-mVPP output step)
V+
RS
VOUT
OPA322
VIN
10 W to
20 W
RL
CL
Figure 34. Improving Capacitive Load Drive
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OPA4322, OPA4322S
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SBOS538E –JANUARY 2011–REVISED JUNE 2012
OVERLOAD RECOVERY TIME
Overload recovery time is the time required for the output of the amplifier to come out of saturation and recover
to the linear region. Overload recovery is particularly important in applications where small signals must be
amplified in the presence of large transients. Figure 35 and Figure 36 show the positive and negative overload
recovery times of the OPA322, respectively. In both cases, the time elapsed before the OPA322 comes out of
saturation is less than 100 ns. In addition, the symmetry between the positive and negative recovery times allows
excellent signal rectification without distortion of the output signal.
3
2.5
2
1
0.5
0
VS = ±2.75 V
G = -10
Output
Input
1.5
1
-0.5
-1
0.5
0
-1.5
-2
Input
Output
10.25
VS = ±2.75 V
G = -10
-0.5
-2.5
-1
9.75
-3
9.75
10
10.25
10.5
10.75
11
10
10.5
10.75
11
Time (250 ns/div)
Time (250 ns/div)
Figure 35. Positive Recovery Time
Figure 36. Negative Recovery Time
SHUTDOWN FUNCTION
The SHDN (enable) pin function of the OPAx322S is referenced to the negative supply voltage of the operational
amplifier. A logic level high enables the op amp. A valid logic high is defined as voltage [(V+) – 0.1 V], up to (V+),
applied to the SHDN pin. A valid logic low is defined as [(V–) + 0.1 V], down to (V–), applied to the enable pin.
The maximum allowed voltage applied to SHDN is 5.5 V with respect to the negative supply, independent of the
positive supply voltage. This pin should either be connected to a valid high or a low voltage or driven, and not left
as an open circuit.
The logic input is a high-impedance CMOS input. Dual op amp versions are independently controlled and quad
op amp versions are controlled in pairs with logic inputs. For battery-operated applications, this feature may be
used to greatly reduce the average current and extend battery life. The enable time is 10 µs for full shutdown of
all channels; disable time is 3 μs. When disabled, the output assumes a high-impedance state. This architecture
allows the OPAx322S to be operated as a gated amplifier (or to have the device output multiplexed onto a
common analog output bus). Shutdown time (tOFF) depends on loading conditions and increases with increased
load resistance. To ensure shutdown (disable) within a specific shutdown time, the specified 10-kΩ load to mid-
supply (VS / 2) is required. If using the OPAx322S without a load, the resulting turn-off time is significantly
increased.
GENERAL LAYOUT GUIDELINES
The OPA322 is a wideband amplifier. To realize the full operational performance of the device, follow good high-
frequency printed circuit board (PCB) layout practices. The bypass capacitors must be connected between each
supply pin and ground as close to the device as possible. The bypass capacitor traces should be designed for
minimum inductance.
LEADLESS DFN PACKAGE
The OPA2322 uses the DFN style package (also known as SON), which is a QFN with contacts on only two
sides of the package bottom. This leadless package maximizes PCB space and offers enhanced thermal and
electrical characteristics through an exposed pad. One of the primary advantages of the DFN package is its low
height (0,8 mm).
DFN packages are physically small, and have a smaller routing area. Additionally, they offer improved thermal
performance, reduced electrical parasitics, and a pinout scheme that is consistent with other commonly-used
packages (such as SO and MSOP). The absence of external leads also eliminates bent-lead issues.
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The DFN package can easily be mounted using standard PCB assembly techniques. See the application reports,
QFN/SON PCB Attachment (SLUA271) and Quad Flatpack No-Lead Logic Packages (SCBA017), both available
for download at www.ti.com. The exposed leadframe die pad on the bottom of the DFN package should be
connected to the most negative potential (V–). The dimension of the exposed thermal die pad is 2 mm ×
1,2 mm and is centered.
APPLICATION EXAMPLES
ACTIVE FILTER
The OPA322 is well-suited for active filter applications that require a wide bandwidth, fast slew rate, low-noise,
single-supply operational amplifier. Figure 37 shows a 500-kHz, second-order, low-pass filter using the multiple-
feedback (MFB) topology. The components have been selected to provide a maximally-flat Butterworth response.
Beyond the cutoff frequency, roll-off is –40 dB/dec. The Butterworth response is ideal for applications that require
predictable gain characteristics, such as the anti-aliasing filter used in front of an ADC.
One point to observe when considering the MFB filter is that the output is inverted, relative to the input. If this
inversion is not required, or not desired, a noninverting output can be achieved through one of these options:
1. adding an inverting amplifier;
2. adding an additional second-order MFB stage; or
3. using a noninverting filter topology, such as the Sallen-Key (shown in Figure 38).
MFB and Sallen-Key, low-pass and high-pass filter synthesis is quickly accomplished using TI’s FilterPro™
program. This software is available as a free download at www.ti.com.
R3
549 W
C2
150 pF
V+
R1
R2
549 W
1.24 kW
VIN
VOUT
OPA322
C1
1 nF
V-
Figure 37. Second-Order Butterworth 500-kHz Low-Pass Filter
220 pF
V+
19.5 kW
150 kW
1.8 kW
VIN = 1 VRMS
VOUT
OPA322
3.3 nF
47 pF
V-
Figure 38. OPA322 Configured as a Three-Pole, 20-kHz, Sallen-Key Filter
16
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OPA4322, OPA4322S
www.ti.com
SBOS538E –JANUARY 2011–REVISED JUNE 2012
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (March 2012) to Revision E
Page
•
•
•
•
Changed product status from Production Data to Mixed Status .......................................................................................... 1
Updated D, DGK pinout drawing .......................................................................................................................................... 6
Added Figure 26 to Figure 29 ............................................................................................................................................. 11
Added Shutdown Function section ..................................................................................................................................... 15
Changes from Revision C (November 2011) to Revision D
Page
•
•
•
Changed product status from Mixed Status to Production Data .......................................................................................... 1
Deleted shading and footnote 2 from Package/Ordering Information table ......................................................................... 2
Added OPA4322, OPA4322S to the Input Bias Current, Input bias current, Over temperature parameter in Electrical
Characteristics table ............................................................................................................................................................. 3
•
Changed Power Supply, OPA4322, OPA4322S Over temperature parameter maximum specification in the Electrical
Characteristics table ............................................................................................................................................................. 4
Changes from Revision B (July 2011) to Revision C
Page
•
Changed status of OPA2322 SO-8 (D) to production data from product preview ................................................................ 2
Changes from Revision A (May 2011) to Revision B
Page
•
Updated OPA322 SOT23-5 device status from product preview to production data in Package/Ordering Information
table ...................................................................................................................................................................................... 2
•
•
Changed Input Bias Current Input bias current, Over temperature parameter in Electrical Characteristics table ............... 3
Changed Open-Loop Gain, Open-loop voltage gain parameter typical specification in the Electrical Characteristics
table ...................................................................................................................................................................................... 3
•
•
•
Changed Open-Loop Gain, Phase margin parameter test conditions in the Electrical Characteristics table ...................... 3
Added test conditions to Power Supply section in Electrical Characteristics table .............................................................. 4
Changed Power Supply, Quiescent current per amplifier OPA322/S parameter maximum specification in the
Electrical Characteristics ....................................................................................................................................................... 4
•
•
•
Changed Power Supply, OPA322 Over temperature parameter maximum specification in the Electrical
Characteristics table ............................................................................................................................................................. 4
Changed Power Supply, Quiescent current per amplifier OPA4322/S parameter typical specification in the Electrical
Characteristics ...................................................................................................................................................................... 4
Changed Shutdown, Quiescent current, per amplifier parameter maximum specification in Electrical Characteristics
table ...................................................................................................................................................................................... 4
•
•
•
•
•
•
Added OPA322S thermal information to Thermal Information: OPA322 table ..................................................................... 5
Added OPA2322S thermal information to Thermal Information: OPA2322 table ................................................................. 5
Added OPA4322S thermal information to Thermal Information: OPA4322 table ................................................................. 5
Updated Figure 1 .................................................................................................................................................................. 7
Added Figure 25 ................................................................................................................................................................. 11
Changed Overload Recovery Time section ........................................................................................................................ 15
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PACKAGE OPTION ADDENDUM
www.ti.com
16-Aug-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
OPA2322AID
OPA2322AIDGKR
OPA2322AIDGKT
OPA2322AIDR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PREVIEW
PREVIEW
ACTIVE
ACTIVE
PREVIEW
PREVIEW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
VSSOP
VSSOP
SOIC
D
8
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
DGK
DGK
D
2500
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
8
Green (RoHS
& no Sb/Br)
8
2500
3000
250
Green (RoHS
& no Sb/Br)
OPA2322AIDRGR
OPA2322AIDRGT
OPA2322SAIDGSR
OPA2322SAIDGST
OPA322AIDBVR
OPA322AIDBVT
OPA322SAIDBVR
OPA322SAIDBVT
OPA4322AIPW
SON
DRG
DRG
DGS
DGS
DBV
DBV
DBV
DBV
PW
8
Green (RoHS
& no Sb/Br)
SON
8
Green (RoHS
& no Sb/Br)
MSOP
MSOP
SOT-23
SOT-23
SOT-23
SOT-23
TSSOP
TSSOP
TSSOP
TSSOP
10
10
5
2500
80
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
3000
250
Green (RoHS
& no Sb/Br)
5
Green (RoHS
& no Sb/Br)
6
3000
250
Green (RoHS
& no Sb/Br)
6
Green (RoHS
& no Sb/Br)
14
14
16
16
90
Green (RoHS
& no Sb/Br)
OPA4322AIPWR
OPA4322SAIPW
OPA4322SAIPWR
PW
2000
90
Green (RoHS
& no Sb/Br)
PW
Green (RoHS
& no Sb/Br)
PW
2000
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
16-Aug-2012
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Aug-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA2322AIDGKR
OPA2322AIDGKT
OPA2322AIDR
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
2500
250
330.0
180.0
330.0
330.0
180.0
180.0
330.0
330.0
12.4
12.4
12.4
12.4
8.4
5.3
5.3
6.4
3.3
3.2
3.2
6.9
6.9
3.4
3.4
5.2
3.3
3.1
3.1
5.6
5.6
1.4
1.4
8.0
8.0
8.0
8.0
4.0
4.0
8.0
8.0
12.0
12.0
12.0
12.0
8.0
Q1
Q1
Q1
Q2
Q3
Q3
Q1
Q1
8
2500
3000
3000
250
2.1
OPA2322AIDRGR
OPA322AIDBVR
OPA322AIDBVT
OPA4322AIPWR
OPA4322SAIPWR
SON
DRG
DBV
DBV
PW
8
1.1
SOT-23
SOT-23
TSSOP
TSSOP
5
1.39
1.39
1.6
5
8.4
8.0
14
16
2000
2000
12.4
12.4
12.0
12.0
PW
1.6
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Aug-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA2322AIDGKR
OPA2322AIDGKT
OPA2322AIDR
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
2500
250
367.0
210.0
367.0
367.0
210.0
210.0
367.0
367.0
367.0
185.0
367.0
367.0
185.0
185.0
367.0
367.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
8
2500
3000
3000
250
OPA2322AIDRGR
OPA322AIDBVR
OPA322AIDBVT
OPA4322AIPWR
OPA4322SAIPWR
SON
DRG
DBV
DBV
PW
8
SOT-23
SOT-23
TSSOP
TSSOP
5
5
14
16
2000
2000
PW
Pack Materials-Page 2
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