OPA355QDBVRQ1 [TI]
汽车 2.5V；200MHz GBW；具有关断状态的 CMOS 单路运算放大器 | DBV | 6 | -40 to 125;
| 型号： | OPA355QDBVRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车 2.5V；200MHz GBW；具有关断状态的 CMOS 单路运算放大器 | DBV | 6 | -40 to 125 放大器 光电二极管 运算放大器 |
| 文件： | 总28页 (文件大小：1248K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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OPA355-Q1
SLOS868C –DECEMBER 2013–REVISED MAY 2018
OPA355-Q1 200-MHz CMOS Operational Amplifier With Shutdown
1 Features
3 Description
The OPA355-Q1 device is a high-speed, voltage-
1
•
•
Qualified for Automotive Applications
feedback CMOS operational amplifier designed for
applications requiring wide bandwidth. The OPA355-
Q1 device is unity-gain stable and can drive large
output currents. In addition, the OPA355-Q1 device
has a digital shutdown (enable) function. This feature
provides power saving during idle periods and places
the output in a high-impedance state to support
output multiplexing. The differential gain is 0.02% and
the differential phase is 0.05°. The quiescent current
is 8.3 mA per channel.
AEC-Q100 Qualified With the Following Results
–
Device Temperature Grade 1: –40°C to
+125°C Ambient Operating Temperature
–
–
Device HBM ESD Classification Level 2
Device CDM ESD Classification Level C4B
•
•
•
•
•
Unity-Gain Bandwidth: 450 MHz
Wide Bandwidth: 200 MHz GBW
High Slew Rate: 360 V/μs
The OPA355-Q1 device is optimized for operation on
single supply or dual supplies as low as 2.5 V (±1.25
V) and up to 5.5 V (±2.75 V). The common-mode
input range for the OPA355-Q1 device extends 100
mV below ground and up to 1.5 V from V+. The
output swing is within 100 mV of the rails, supporting
wide dynamic range.
Low Noise: 5.8 nV/√Hz
Excellent Video Performance:
–
–
–
Differential Gain: 0.02%
Differential Phase: 0.05° (0.1 dB)
Gain Flatness: 75 MHz
•
•
•
•
•
•
•
•
Input Range Includes Ground
Rail-to-Rail Output (Within 100 mV)
Low Input Bias Current: 3 pA
The OPA355-Q1 device is available in a single SOT-
23-6 package and is specified over the extended
–40°C to +125°C temperature range.
Low Shutdown Current: 3.4 μA
Enable and Disable Time: 100 ns and 30 ns
Thermal Shutdown
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
OPA355-Q1
SOT-23 (6)
2.90 mm × 1.60 mm
Single-Supply Operating Range: 2.5 V to 5.5 V
MicroSIZE Packages
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
•
•
•
•
Automotive
Active Filters
High-Speed Integrators
Analog-to-Digital Converter (ADC) Input Buffers
Digital-to-Analog Converter (DAC) Output
Amplifiers
V+
œVIN
OPA355-Q1
Out
+VIN
Vœ Enable
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA355-Q1
SLOS868C –DECEMBER 2013–REVISED MAY 2018
www.ti.com
Table of Contents
8.2 Functional Block Diagram ....................................... 12
8.3 Feature Description................................................. 12
8.4 Device Functional Modes........................................ 13
Application and Implementation ........................ 14
9.1 Application Information............................................ 14
9.2 Typical Applications ................................................ 14
1
2
3
4
5
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Device Comparison Table..................................... 3
5.1 Device Comparison Table......................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 4
7.5 Electrical Characteristics........................................... 5
7.6 Typical Characteristics.............................................. 7
Detailed Description ............................................ 12
8.1 Overview ................................................................. 12
9
10 Power Supply Recommendations ..................... 19
11 Layout................................................................... 19
11.1 Layout Guidelines ................................................. 19
11.2 Layout Example .................................................... 19
12 Device and Documentation Support ................. 20
12.1 Trademarks........................................................... 20
12.2 Electrostatic Discharge Caution............................ 20
12.3 Glossary................................................................ 20
6
7
13 Mechanical, Packaging, and Orderable
8
Information ........................................................... 20
4 Revision History
Changes from Revision B (June 2014) to Revision C
Page
•
•
•
•
•
•
•
Deleted "C55" marking on pinout drawing in Pin Configuration and Functions section ........................................................ 3
Added Pin Functions table to Pin Configuration and Functions section ............................................................................... 3
Deleted storage temperature range from ESD Ratings table and moved to Absolute Maximum Ratings table ................... 4
Changed title of Handling Ratings table to ESD Ratings table ............................................................................................. 4
Added Recommended Operating Conditions table ............................................................................................................... 4
Added Functional Block Diagram ........................................................................................................................................ 12
Deleted "Independent enable pins are available for each channel, which provide maximum design flexibility" from
Enable Function section ....................................................................................................................................................... 12
•
•
•
•
•
•
•
•
•
Deleted Input and ESD Protection subsection in Feature Description section .................................................................... 13
Added Device Functional Modes section ............................................................................................................................. 13
Added Typical Applications section to Application and Implementation section ................................................................. 14
Added Design Requirements subsection to Typical Applications section ........................................................................... 14
Added Detailed Design Procedure subsection to Typical Application section .................................................................... 14
Added application curves to the Typical Application section ............................................................................................... 16
Added High-Impedance Sensor Interface, Driving ADCs, and Active Filter subsections to Typical Application section..... 16
Added Power Supply Recommendations section ............................................................................................................... 19
Added layout example image to Layout section................................................................................................................... 19
Changes from Revision A (December 2013) to Revision B
Page
•
Changed device status from Product Preview to Production Data ....................................................................................... 1
2
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SLOS868C –DECEMBER 2013–REVISED MAY 2018
5 Device Comparison Table
5.1 Device Comparison Table
OPA355-Q1 RELATED
PRODUCTS
FEATURES
OPA356
OPAx350
OPAx631
OPAx634
THS412x
200-MHz, Rail-to-Rail Output, CMOS, No Shutdown
38-MHz, Rail-to-Rail Input and Output, CMOS
75-MHz, Rail-to-Rail Output
150-MHz, Rail-to-Rail Output
Differential Input and Output, 3.3-V Supply
6 Pin Configuration and Functions
DBV Package
6-Pin SOT-23
Top View
1
2
3
6
5
4
V+
OUT
Vœ
ENABLE
+IN
œIN
Pin 1 of the SOT-23-6 is determined by orienting the package marking as indicated in the diagram.
Pin Functions
PIN
I/O
DESCRIPTION
NAME
ENABLE
IN+
NO.
5
—
I
Amplifier power down. Low = disabled, high = normal operation (pin must be driven) .
3
Noninverting input pin
Inverting input pin
Output pin
IN–
4
I
OUT
V+
1
O
—
—
6
Positive power supply
Negative power supply
V–
2
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
7.5
UNIT
V
Supply voltage
V+ to V–
Voltage
Current
(V–) – 0.5
(V+) + 0.5
10
V
Signal input terminals
mA
Output short circuit(2)
Operating temperature
Junction temperature
Continuous
–55
–65
150
160
300
150
°C
°C
°C
°C
Lead temperature (soldering, 10 seconds)
Storage temperature range, Tstg
(1) Stresses above Absolute Maximum Ratings may cause permanent damage. Exposure to absolute maximum conditions for extended
periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other
conditions beyond those specified is not implied.
(2) Short-circuit to ground, one amplifier per package.
7.2 ESD Ratings
MIN
MAX
UNIT
Human body model (HBM), per AEC Q100-002(1)
2000
Corner pins (1, 3, 4, and
6)
V(ESD)
Electrostatic discharge
750
500
V
Charged device model (CDM), per
AEC Q100-011
Other pins
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.7
NOM
MAX
5.5
UNIT
VS Total supply voltage
TA Ambient temperature
V
–40
25
125
°C
7.4 Thermal Information
OPA355-Q1
THERMAL METRIC(1)
DBV (SOT-23)
6 PINS
187.3
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
126.5
32.6
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
24.1
ψJB
32.1
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
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SLOS868C –DECEMBER 2013–REVISED MAY 2018
7.5 Electrical Characteristics
VS = 2.7 V to 5.5 V (single-supply). At TA = 25°C, RF = 604 Ω, RL = 150 Ω, and connected to VS / 2, (unless otherwise noted)
PARAMETER
OFFSET VOLTAGE
TEST CONDITIONS
MIN
TYP
MAX UNIT
TA = 25°C
±2
±9
mV
±15
VOS
Input offset voltage
VS = 5 V
TA = –40°C to +125°C
TA = 25°C
DVOS/d Input offset voltage vs
µV/°C
T
temperature
TA = –40°C to +125°C
±7
TA = 25°C
±80
±350
µV/V
Input offset voltage vs power VS = 2.7 to 5.5 V,
PSRR
supply
VCM = VS / 2 – 0.15 V
TA = –40°C to +125°C
INPUT BIAS CURRENT
TA = 25°C
3
±50
pA
IB
Input bias current
Input offset current
TA = –40°C to +125°C
TA = 25°C
±50
±1
IOS
pA
TA = –40°C to +125°C
NOISE
en
TA = 25°C
5.8
50
nV/√H
z
Input noise voltage density
Current noise density
ƒ = 1 MHz
ƒ = 1 MHz
TA = –40°C to +125°C
TA = 25°C
in
fA/√Hz
TA = –40°C to +125°C
INPUT VOLTAGE RANGE
Common-mode voltage
TA = 25°C
(V–) – 0.1
(V+) – 1.5
VCM
V
range
TA = –40°C to +125°C
TA = 25°C
66
66
80
VS = 5.5 V
–0.1 V < VCM < 4 V
CMRR Common-mode rejection ratio
INPUT IMPEDANCE
dB
TA = –40°C to +125°C
TA = 25°C
1013 || 1.5
1013 || 1.5
Differential
Ω || pF
Ω || pF
TA = –40°C to +125°C
TA = 25°C
Common-mode
OPEN-LOOP GAIN
TA = –40°C to +125°C
TA = 25°C
84
80
92
VS = 5 V
0.3 V < VO < 4.7 V
Open-loop gain
dB
TA = –40°C to +125°C
FREQUENCY RESPONSE
G = 1, VO = 100 mVp-p, RF = 0 Ω, TA = 25°C
G = 2, VO = 100 mVp-p, RL = 50 Ω, TA = 25°C
G = 2, VO = 100 mVp-p, RL = 150 Ω, TA = 25°C
G = 2, VO = 100 mVp-p, RL = 1 kΩ, TA = 25°C
G = 10, RL = 1 kΩ, TA = 25°C
450
100
170
200
200
MHz
MHz
MHz
MHz
MHz
ƒ–3dB
Small-signal bandwidth
Gain-bandwidth product
GBW
ƒ0.1 dB
SR
Bandwidth for 0.1-db gain
flatness
G = 2, VO = 100 mVp-p, RF = 560 Ω, TA = 25°C
75
300 / –360
2.4
MHz
V/µs
ns
Slew rate
VS = 5 V, G = 2, 4-V output step, TA = 25°C
G = 2, VO = 200 mVp-p, 10% to 90%
TA = 25°C
Rise and fall time
G = 2, VO = 2 Vp-p, 10% to 90%
TA = 25°C
8
ns
ns
VS = 5 V, G = 2, 2-V output step, 0.1%
TA = 25°C
30
Settling time
VS = 5 V, G = 2, 2-V output step, 0.01%
TA = 25°C
120
8
ns
ns
Overload recovery time
VI × G = VS, TA = 25°C
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Electrical Characteristics (continued)
VS = 2.7 V to 5.5 V (single-supply). At TA = 25°C, RF = 604 Ω, RL = 150 Ω, and connected to VS / 2, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
G = 2, ƒ = 1 MHz, VO = 2 Vp-p, RL = 200 Ω
TA = 25°C (second harmonic)
–81
dBc
Harmonic distortion
G = 2, ƒ = 1 MHz, VO = 2 Vp-p, RL = 200 Ω
–93
dBc
°
TA = 25°C (third harmonic)
Differential gain error
Differential phase error
NTSC, RL = 150 Ω, TA = 25°C
NTSC, RL = 150 Ω, TA = 25°C
0.02%
0.05
OUTPUT
VS = 5 V, RL = 150 Ω, AOL > 84 dB
VS = 5 V, RL = 1 kΩ
0.2
0.1
0.3
V
V
Voltage output swing from
rail
Output current (continuous)
±60
mA
mA
Ω
(1)
IO
VS = 5 V, TA = 25°C
VS = 3 V, TA = 25°C
±100
±80
(1)
Output current (peak)
Closed-loop output
impedance
ƒ < 100 kHz
0.02
POWER SUPPLY
VS Specified voltage range
TA = 25°C
TA = 25°C
2.7
5.5
V
V
Operating voltage range
2.5 to 5.5
8.3
TA = 25°C
11
14
Quiescent current (per
amplifier)
VS = 5 V, enabled;
IO = 0
IQ
mA
TA = –40°C to +125°C
SHUTDOWN
Logic-LOW threshold(2)
TA = 25°C
TA = 25°C
0.8
V
V
(disabled)
Logic-HIGH threshold(2)
(enabled)
2
Enable time
Disable time
TA = 25°C
TA = 25°C
100
30
ns
ns
Shutdown current (per
amplifier)
VS = 5 V, disabled, TA = 25°C
3.4
µA
THERMAL SHUTDOWN
Shutdown, TA = 25°C
Reset from shutdown, TA = 25°C
TA = 25°C
160
140
°C
°C
°C
°C
°C
Junction temperature
Specified range
Operating range
Storage range
–40
–55
–65
125
150
150
TA = 25°C
TA = 25°C
(1) See the Output Voltage Swing vs Output Current (Figure 21 and Figure 23) in the Typical Characteristics section.
(2) Logic LOW and HIGH levels are CMOS logic compatible. They are referenced to V–.
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SLOS868C –DECEMBER 2013–REVISED MAY 2018
7.6 Typical Characteristics
TA = 25°C, VS = 5 V, G = 2, RF = 604 Ω, and RL = 150 Ω connected to VS / 2, (unless otherwise noted)
6
3
3
0
G = 1
RF = 0
G = –1
G = –2
0
–3
–6
–9
–12
G = –5
–3
–6
–9
G = 2
G = 5
G = –10
G = 10
–12
–15
100k
1M
10M
100M
1G
100k
1M
10M
Frequency (Hz)
100M
1G
Frequency (Hz)
VO = 0.1 VP-P
VO = 0.1 VP-P
Figure 1. Noninverting Small-Signal Frequency Response
Figure 2. Inverting Small-Signal Frequency Response
Time (20 ns/div)
Time (20 ns/div)
G = 2
G = 2
Figure 3. Noninverting Small-Signal Step Response
Figure 4. Noninverting Large-Signal Step Response
0.5
Enabled
4.5
0.4
fIN = 5 MHz
RF = 604
0.3
0.2
0.1
0
3.5
2.5
1.5
–0.1
RF = 560
–0.2
–0.3
RF = 500
VO
–0.4
Disabled
0.5
–0.5
1
10
100
Time (200 ns/div)
Frequency (MHz)
CL = 0 pF
VO = 0.1 VP-P
Figure 5. Large-Signal Disable and Enable Response
Figure 6. 0.1-dB Gain Flatness for Various RF Values?
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Typical Characteristics (continued)
TA = 25°C, VS = 5 V, G = 2, RF = 604 Ω, and RL = 150 Ω connected to VS / 2, (unless otherwise noted)
–50
–50
–60
–60
–70
–70
2nd-Harmonic
2nd Harmonic
–80
–80
3rd-Harmonic
3rd Harmonic
–90
–90
–100
–100
0
1
2
3
4
1
10
Output Voltage (Vp-p)
Gain (V/V)
RL = 200
ƒ = 1 MHz
RL = 200
VO = 2 VP-P
ƒ = 1 MHz
Figure 7. Harmonic Distortion vs Output Voltage
Figure 8. Harmonic Distortion vs Noninverting Gain
–50
–60
–50
–60
–70
2nd-Harmonic
–70
2nd-Harmonic
3rd-Harmonic
–80
–80
3rd-Harmonic
–90
–90
–100
–100
1
10
100k
1M
10M
Gain (V/V)
Frequency (Hz)
RL = 200
VO = 2 VP-P
ƒ = 1 MHz
RL = 200
VO = 2 VP-P
Figure 9. Harmonic Distortion vs Inverting Gain
Figure 10. Harmonic Distortion vs Frequency
–50
–60
10k
1k
Current Noise
Voltage Noise
–70
100
10
1
–80
2nd-Harmonic
–90
3rd-Harmonic
–100
100
1k
10
100
1k
10k
100k
1M
10M
100M
RL (Ω)
Frequency (Hz)
ƒ = 1 MHz
VO = 2 VP-P
Figure 12. Input Voltage and Current Noise Spectral Density
vs Frequency
Figure 11. Harmonic Distortion vs Load Resistance
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Typical Characteristics (continued)
TA = 25°C, VS = 5 V, G = 2, RF = 604 Ω, and RL = 150 Ω connected to VS / 2, (unless otherwise noted)
3
0
9
CL = 100 pF
CL = 47 pF
RL = 10k
6
3
–3
0
RL = 50
–6
–3
–6
–9
–12
–15
CL = 5.6 pF
RL = 150
–9
RL = 1k
–12
–15
100k
1M
10M
100M
1G
100k
1M
10M
100M
1G
Frequency (Hz)
VO = 0.1 VP-P
Frequency (Hz)
VO = 0.1 VP-P
CL = 0 pF
RS = 0
Figure 13. Frequency Response for Various RL Values
Figure 14. Frequency Response for Various CL Values?
120
3
100
80
60
40
20
0
0
CL = 5.6 pF
RS = 80
CL = 100 pF
RS = 24
D3
D6
VI
RS
OPA355-Q1
604
VO
VI
RS
CL = 47 pF
RS = 36
VO
OPA355-Q1
604
CL
1k
D9
CL
1k
(1k is
Optional)
(1k is
Optional)
D12
D15
604
604
1
10
100
1M
10M
100M
1G
Capacitive Load (pF)
Frequency (Hz)
Figure 15. Recommended RS Values vs Capacitive Load
Figure 16. Frequency Response vs Capacitive Load
100
180
90
160
140
120
100
80
DPSRR
80
70
+PSRR
Phase
Gain
60
CMRR
50
40
30
20
10
0
60
40
20
RL = 1 kW
0
RL = 150 kW
–20
10k
100k
1M
10M
100M
1G
1k
10k
100k
1M
10M
100M
1G
Frequency (Hz)
Frequency (Hz)
Figure 17. Common-Mode Rejection Ratio and Power-
Supply Rejection Ratio vs Frequency
Figure 18. Open-Loop Gain and Phase
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Typical Characteristics (continued)
TA = 25°C, VS = 5 V, G = 2, RF = 604 Ω, and RL = 150 Ω connected to VS / 2, (unless otherwise noted)
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
10n
1n
100
10
1
dP
dG
–55 –35 –15
5
25
45
65
85 105 125 135
1
2
3
4
Temperature (°C)
Number of 150 Loads
Figure 19. Composite Video Differential Gain and Phase
Figure 20. Input Bias Current vs Temperature
14
12
10
8
3
25°C
VS = 5.5 V
–55°C
2
125°C
6
125°C
VS = 2.5 V
VS = 3 V
1
4
VS = 5 V
–55°C
25°C
2
0
0
0
30
60
90
120
150
–55 –35 –15
5
25
45
65
85 105 125 135
Output Current (mA)
Temperature (°C)
Continuous currents above 60 mA are not recommended
VS = 3 V
Figure 21. Output Voltage Swing vs Output Current
Figure 22. Supply Current vs Temperature
5
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
VS = 5.5 V
25°C
–55°C
4
VS = 5 V
125°C
3
2
125°C
VS = 3 V
VS = 2.5 V
1
–55°C
25°C
0
0
50
100
150
200
250
–55 –35 –15
5
25
45
65
85 105 125 135
Output Current (mA)
Temperature (°C)
Continuous currents above 60 mA are not recommended
VS = 5 V
Figure 23. Output Voltage Swing vs Output Current
Figure 24. Shutdown Current vs Temperature
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Typical Characteristics (continued)
TA = 25°C, VS = 5 V, G = 2, RF = 604 Ω, and RL = 150 Ω connected to VS / 2, (unless otherwise noted)
6
5
4
3
2
1
0
100
VS = 5.5 V
10
1
OPA355-Q1
604
VS = 2.7 V
0.1
ZO
0.01
0.001
604
10k
100k
1M
10M
100M
1G
1
10
100
Frequency (Hz)
Frequency (MHz)
Maximum output voltage without slew-rate induced distortion
Figure 25. Closed-Loop Output Impedance vs Frequency
Figure 26. Maximum Output Voltage vs Frequency
0.2
110
RL = 1k
0.1
0
100
90
RL = 150
–0.1
–0.2
–0.3
–0.4
80
70
60
0
5
10
15 20 25
Time (ns)
30
35
40
45 50
–55 –35 –15
5
25
45
65
85 105 125 135
Temperature (°C)
VO = 2 VP-P
Figure 27. Output Settling Time to 0.1%
Figure 28. Open-Loop Gain vs Temperature
20
18
16
14
12
10
8
100
90
80
70
60
50
Power-Supply Rejection Ratio
Common-Mode Rejection Ratio
6
4
2
0
–9 –8 –7 –6 –5 –4 –3 –2 –1 0
1
2
3
4
5
6
7
8
9
–55 –35 –15
5
25
45
65
85 105 125 135
Offset Voltage (mV)
Temperature (°C)
Figure 29. Offset Voltage Production Distribution
Figure 30. Common-Mode Rejection Ratio and Power-
Supply Rejection Ratio vs Temperature
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8 Detailed Description
8.1 Overview
The OPA355-Q1 operational amplifier is a high-speed, 300-V/μs, amplifier, making the device a great option for
transimpedance applications. The device is unity-gain stable and can operate on a single-supply voltage (2.7 V
to 5.5 V), or a split-supply voltage (±1.35 V to ±2.75 V), making the device highly versatile and simple to use.
The OPA355-Q1 amplifier is specified from 2.7 V to 5.5 V and over the automotive temperature range of –40°C
to +125°C.
8.2 Functional Block Diagram
V+
Reference
Current
VIN+
œ
VIN
VBIAS1
Class AB
Control
VO
Circuitry
VBIAS2
œ
V
(Ground)
8.3 Feature Description
8.3.1 Operating Voltage
The OPA355-Q1 device is specified over a power-supply range of 2.7 V to 5.5 V (±1.35 to ±2.75 V). However,
the supply voltage ranges from 2.5 to 5.5 V (±1.25 to ±2.75 V). Supply voltages higher than 7.5 V (absolute
maximum) can permanently damage the amplifier.
Parameters that vary significantly over supply voltage or temperature are shown in the Typical Characteristics
section of this data sheet.
8.3.2 Enable Function
The OPA355-Q1 device is enabled by applying a TTL high-voltage level to the enable pin. Conversely, a TTL low
-voltage level disables the amplifier, which reduces the supply current from 8.3 mA to 3.4 μA per amplifier. This
pin voltage is referenced to a single-supply ground. When using a split-supply, such as ±2.5 V, the enable and
disable voltage levels are referenced to V–. For portable battery-operated applications, this feature is used to
greatly reduce the average current and as a result, extend battery life.
The enable input is modeled as a CMOS input gate with a 100-kΩ pullup resistor to V+. The enable pin assumes
a logic high and the amplifier turns on if the enable pin is left open.
The enable time is 100 ns and the disable time is 30 ns, which allows the OPA355-Q1 device to operate as a
gated amplifier, or to have the output multiplexed onto a common output bus. When disabled, the output
assumes a high-impedance state.
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Feature Description (continued)
8.3.3 Output Drive
The output stage supplies a high short-circuit current (typically over 200 mA). Therefore, an on-chip thermal
shutdown circuit is provided to protect the OPA355-Q1 device from dangerously-high junction temperatures. At
160°C, the protection circuit shuts down the amplifier. Normal operation resumes when the junction temperature
cools to below 140°C.
NOTE
Running a continuous DC current in excess of ±60 mA is not recommended. See the
Output Voltage Swing vs Output Current graphs (Figure 21 and Figure 22) in the Typical
Characteristics section.
8.4 Device Functional Modes
The OPA355-Q1 device is powered on when the supply is connected. The device can operate as a single supply
operational amplifier or dual supply amplifier depending on the application. The device can also be used with
asymmetrical supplies as long as the differential voltage (V– to V+) is at least 1.8 V and no greater than 5.5 V
(example: V– set to –3.5 V and V+ set to 1.5 V).
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9 Application and Implementation
9.1 Application Information
The OPA355-Q1 device is a CMOS, high-speed, voltage-feedback, operational amplifier (op-amp) designed for
general-purpose applications.
The amplifier features a 200-MHz gain bandwidth and 300-V/μs slew rate, but the device is unity-gain stable and
operates as a 1-V/V voltage follower.
The input common-mode voltage range of the device includes ground, which allows the OPA355-Q1 to be used
in virtually any single-supply application up to a supply voltage of 5.5 V.
9.2 Typical Applications
9.2.1 Transimpedance Amplifier
Wide gain bandwidth, low input bias current, low input voltage, and current noise make the OPA355-Q1 device a
preferred wideband photodiode transimpedance amplifier. Low-voltage noise is important because photodiode
capacitance causes the effective noise gain of the circuit to increase at high frequency.
The key elements to a transimpedance design, as shown in Figure 31, are the expected diode capacitance
(C(D)), which must include the parasitic input common-mode and differential-mode input capacitance (4 pF + 5
pF), the desired transimpedance gain (R(FB)), and the gain-bandwidth (GBW) for the OPA355-Q1 device (20
MHz). With these three variables set, the feedback capacitor value (C(FB)) is set to control the frequency
response. C(FB) includes the stray capacitance of R(FB), which is 0.2 pF for a typical surface-mount resistor.
(1)
C(F)
< 1 pF
R(F)
10 Mꢀ
V
(V+)
l
VO
C(D)
OPA355-Q1
V(Vœ)
(1) C(FB) is optional to prevent gain peaking. C(FB) includes the stray capacitance of R(FB)
.
Figure 31. Dual-Supply Transimpedance Amplifier
9.2.1.1 Design Requirements
PARAMETER
VALUE
2.5 V
Supply voltage V(V+)
Supply voltage V(V–)
–2.5 V
9.2.1.2 Detailed Design Procedure
To achieve a maximally-flat, second-order Butterworth frequency response, the feedback pole must be set to:
1
GBW
=
2 ´ p ´ R(FB) ´ C(FB)
4 ´ p ´ R(FB) ´ C(D)
(1)
Use Equation 2 to calculate the bandwidth.
GBW
ƒ(–3 dB)
=
2 ´ p ´ R(FB) ´ C(D)
(2)
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For other transimpedance bandwidths, consider the high-speed CMOS OPA380 (90-MHz GBW), OPA354 (100-
MHz GBW), OPA300 (180-MHz GBW), OPA355 (200-MHz GBW), or OPA656 and OPA657 (400-MHz GBW).
For single-supply applications, the +INx input can be biased with a positive DC voltage to allow the output to
reach true zero when the photodiode is not exposed to any light, and respond without the added delay that
results from coming out of the negative rail; this configuration is shown in Figure 32. This bias voltage appears
across the photodiode, providing a reverse bias for faster operation.
0.5 pF
100 kꢀ
œ
OPA355-Q1
VOUT
+
13.7 kꢀ
SFH213
5 V
1 ꢁF
280 ꢀ
Figure 32. Single-Supply Transimpedance Amplifier
For additional information, see the Compensate Transimpedance Amplifiers Intuitively application bulletin.
9.2.1.2.1 Optimizing The Transimpedance Circuit
To achieve the best performance, select components according to the following guidelines:
1. For lowest noise, select R(FB) to create the total required gain. Using a lower value for R(FB) and adding gain
after the transimpedance amplifier generally produces poorer noise performance. The noise produced by
R(FB) increases with the square-root of R(FB), whereas the signal increases linearly. Therefore, signal-to-noise
ratio improves when all the required gain is placed in the transimpedance stage.
2. Minimize photodiode capacitance and stray capacitance at the summing junction (inverting input). This
capacitance causes the voltage noise of the op amp to amplify (increasing amplification at high frequency).
Using a low-noise voltage source to reverse-bias a photodiode can significantly reduce the capacitance.
Smaller photodiodes have lower capacitance. Use optics to concentrate light on a small photodiode.
3. Noise increases with increased bandwidth. Limit the circuit bandwidth to only that required. Use a capacitor
across the R(FB) to limit bandwidth, even if not required for stability.
4. Circuit board leakage can degrade the performance of an otherwise well-designed amplifier. Clean the circuit
board carefully. A circuit board guard trace that encircles the summing junction and is driven at the same
voltage can help control leakage.
For additional information, see the Noise Analysis of FET Transimpedance Amplifiers and Noise Analysis for
High-Speed Op Amps application bulletins).
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9.2.1.3 Application Curve
105
100
95
90
85
80
75
70
65
60
1000
10000
100000
1000000
1E+7
5E+7
Frequency (Hz)
D001
–3 dB bandwidth is 4.56 MHz
Figure 33. AC Transfer Function
9.2.2 High-Impedance Sensor Interface
Many sensors have high source impedances that may range up to 10 MΩ, or even higher. The output signal of
sensors often must be amplified or otherwise conditioned by means of an amplifier. The input bias current of this
amplifier can load the sensor output and cause a voltage drop across the source resistance, as shown in
Figure 34, where (V(+INx) = VS – I(BIAS) × R(S)). The last term, I(BIAS) × R(S), shows the voltage drop across R(S). To
prevent errors introduced to the system as a result of this voltage, an op amp with very low input bias current
must be used with high impedance sensors. This low current keeps the error contribution by I(BIAS) × R(S) less
than the input voltage noise of the amplifier, so that it does not become the dominant noise factor. The OPA355-
Q1 op amp features very low input bias current (typically 200 fA), and is therefore a preferred choice for such
applications.
R(S)
IIB
100 kΩ
V(+INx)
V(V+)
VO
R(F)
Device
V(V–)
R(G)
Figure 34. Noise as a Result of I(BIAS)
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9.2.3 Driving ADCs
The OPA355-Q1 op amps are designed for driving sampling analog-to-digital converters (ADCs) with sampling
speeds up to 1 MSPS. The zero-crossover distortion input stage topology allows the OPA355-Q1 device to drive
ADCs without degradation of differential linearity and THD.
The OPA355-Q1 device can be used to buffer the ADC switched input capacitance and resulting charge injection
while providing signal gain. Figure 35 shows the OPA355-Q1 device configured to drive the ADS8326.
5 V
C1
100 nF
5 V
(1)
R1
100 ꢀ
V(V+)
+INx
OPA355-Q1
ADS8326
16-Bit
(1)
C3
1 nF
V(Vœ)
250kSPS
œINx
VI
0 to 4.096 V
REF IN
(2)
5 V
Optional
R2
50 kꢀ
SD1
BAS40
REF3240
4.096 V
œ5 V
C2
100 nF
C4
100 nF
(1) Suggested value; may require adjustment based on specific application.
(2) Single-supply applications lose a small number of ADC codes near ground as a result of op amp output swing limitation. If a negative
power supply is available, this simple circuit creates a –0.3-V supply to allow output swing to true ground potential.
Figure 35. Driving the ADS8326
9.2.4 Active Filter
The OPA355-Q1 device is designed for active filter applications that require a wide bandwidth, fast slew rate,
low-noise, single-supply operational amplifier. Figure 36 shows a 500 kHz, second-order, low-pass filter using the
multiple-feedback (MFB) topology. The components are selected to provide a maximally-flat Butterworth
response. Beyond the cutoff frequency, roll-off is –40 dB/dec. The Butterworth response is preferred for
applications requiring predictable gain characteristics, such as the anti-aliasing filter used in front of an ADC.
One point to observe when considering the MFB filter is that the output is inverted, relative to the input. If this
inversion is not required, or not desired, a noninverting output can be achieved through one of the following
options:
1. Adding an inverting amplifier
2. Adding an additional second-order MFB stage
3. Using a noninverting filter topology, such as the Sallen-Key (see Figure 37).
MFB and Sallen-Key, low-pass and high-pass filter synthesis is quickly accomplished using TI’s FilterPro™
program. This software is available as a free download at www.ti.com.
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R3
549 Ω
C2
150 pF
V(V+)
R1
549 Ω
R2
1.24 kΩ
VI
VO
Device
C1
1 nF
V(V–)
Figure 36. Second-Order Butterworth 500-kHz Low-Pass Filter
220 pF
V(V+)
19.5 kΩ
150 kΩ
1.8 kΩ
VI = 1 VRMS
VO
Device
3.3 nF
47 pF
V(V–)
Figure 37. OPA355-Q1 Configured as a Three-Pole, 20-kHz, Sallen-Key Filter
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10 Power Supply Recommendations
The OPA355-Q1 device is specified for operation from 2.7 to 5.5 V (±1.35 to ±2.75 V); many specifications apply
from –40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are shown in theTypical Characteristics section.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, see the Layout
Guidelines section.
Power dissipation depends on power-supply voltage, signal and load conditions. With DC signals, power
dissipation is equal to the product of output current times the voltage across the conducting output transistor,
VS – VO. Minimize power dissipation by using the lowest possible power-supply voltage required to ensure the
required output voltage swing.
For resistive loads, the maximum power dissipation occurs at a DC output voltage of one-half the power-supply
voltage. Dissipation with AC signals is lower. Application bulletin AB-039, Power Amplifier Stress and Power
Handling Limitations explains how to calculate or measure power dissipation with unusual signals and loads, and
is available on www.ti.com.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heat sink. For reliable operation, limit junction temperature to 150°C maximum. To estimate the margin of safety
in a complete design, increase the ambient temperature to trigger the thermal protection at 160°C. The thermal
protection must trigger more than 35°C above the maximum expected ambient condition of the application.
11 Layout
11.1 Layout Guidelines
Good high-frequency printed-circuit board (PCB) layout techniques must be used for the OPA355-Q1. Generous
use of ground planes, short direct-signal traces, and a preferred bypass capacitor located at the V+ pin ensures
clean and stable operation. Large areas of copper help dissipate heat generated within the amplifier in normal
operation.
Sockets are not recommended for use with any high-speed amplifier.
A 10-nF ceramic bypass capacitor is the minimum recommended value; adding a 1-μF or larger tantalum
capacitor in parallel is beneficial when driving a low-resistance load. Providing adequate bypass capacitance is
essential to achieving very low harmonic and intermodulation distortion.
11.2 Layout Example
Ground and power plane exist on
inner layers
Ground and power plane removed
Place output resistors close
to output pins to minimize
parasitic capacitance
from inner layers
1
2
3
6
5
4
Place bypass capacitors
close to power pins
Place bypass capacitors
close to power pins
Power control (disable) pin
Must be driven
Place input resistor close to pin 4
to minimize stray capacitance
Noninverting input
terminated in 50 Ω
Place feedback resistor on the bottom
of PCB between pins 4 and 6
Remove GND and Power plane
under pins 1 and 4 to minimize
stray PCB capacitance
Figure 38. Layout Example
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12 Device and Documentation Support
12.1 Trademarks
FilterPro is a trademark of Texas Instruments Incorporated.
All other trademarks are the property of their respective owners.
12.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA355QDBVRQ1
ACTIVE
SOT-23
DBV
6
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
SLN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF OPA355-Q1 :
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Catalog: OPA355
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA355QDBVRQ1
SOT-23
DBV
6
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOT-23 DBV
SPQ
Length (mm) Width (mm) Height (mm)
445.0 220.0 345.0
OPA355QDBVRQ1
6
3000
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0006A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
B
1.45 MAX
A
PIN 1
INDEX AREA
1
2
6
5
2X 0.95
1.9
3.05
2.75
4
3
0.50
6X
0.25
C A B
0.15
0.00
0.2
(1.1)
TYP
0.25
GAGE PLANE
0.22
0.08
TYP
8
TYP
0
0.6
0.3
TYP
SEATING PLANE
4214840/C 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
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EXAMPLE BOARD LAYOUT
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214840/C 06/2021
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/C 06/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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