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OPA3684IDBQ [TI]

Low-Power, Triple Current Feedback Operational Amplifier with Disable 16-SSOP -40 to 85;
OPA3684IDBQ
型号： OPA3684IDBQ
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

Low-Power, Triple Current Feedback Operational Amplifier with Disable 16-SSOP -40 to 85

放大器 光电二极管
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OPA3684  
O
P
A
3
6
8
4
www.ti.com  
SBOS241C – MAY 2002 – REVISED JULY 2008  
Low-Power, Triple Current-Feedback  
OPERATIONAL AMPLIFIER With Disable  
FEATURES  
APPLICATIONS  
● MINIMAL BANDWIDTH CHANGE VERSUS GAIN  
● 170MHz BANDWIDTH: G = +2  
● RGB LINE DRIVERS  
● LOW-POWER BROADCAST VIDEO DRIVERS  
● EQUALIZING FILTERS  
● MULTICHANNEL SUMMING AMPLIFIERS  
● PROFESSIONAL CAMERAS  
● ADC INPUT DRIVERS  
● > 120MHz BANDWIDTH TO GAIN > +10  
● LOW DISTORTION: < –82dBc at 5MHz  
● HIGH OUTPUT CURRENT: 120mA  
● SINGLE +5V TO +12V SUPPLY OPERATION  
● DUAL ±2.5V TO ±6.0V SUPPLY OPERATION  
● LOW SUPPLY CURRENT: 1.7mA/ch  
● LOW SHUTDOWN CURRENT: 100µA/ch  
have greater bandwidth, and low-power line drivers to meet the  
demanding requirements of studio cameras and broadcast video.  
DESCRIPTION  
The OPA3684 provides a new level of performance in low-power,  
wideband, current-feedback (CFB) amplifiers. This CFBPLUS am-  
plifier among the first to use an internally closed-loop input buffer  
stage that enhances performance significantly over earlier low-  
power CFB amplifiers. While retaining the benefits of very low  
power operation, this new architecture provides many of the  
benefits of a more ideal CFB amplifier. The closed-loop input stage  
buffer gives a very low and linearized impedance path at the  
inverting input to sense the feedback error current. This improved  
inverting input impedance retains exceptional bandwidth to much  
higher gains and improves harmonic distortion over earlier solu-  
tions limited by inverting input linearity. Beyond simple high-gain  
applications, the OPA3684 CFBPLUS amplifier permits the gain  
setting element to be set with considerable freedom from amplifier  
bandwidth interaction. This allows frequency response peaking  
elements to be added, multiple input inverting summing circuits to  
The output capability of the OPA3684 also sets a new mark in  
performance for low-power current-feedback amplifiers. Delivering  
a full ±4Vp-p swing on ±5V supplies, the OPA3684 also has the  
output current to support > ±3Vp-p into 50Ω. This minimal output  
headroom requirement is complemented by a similar 1.2V input  
stage headroom giving exceptional capability for single +5V opera-  
tion.  
The OPA3684’s low 1.7mA/ch supply current is precisely trimmed  
at 25°C. This trim, along with low shift over temperature and supply  
voltage, gives a very robust design over a wide range of operating  
conditions. System power may be further reduced by using the  
optional disable control pin. Leaving this disable pin open, or holding  
it HIGH, gives normal operation. If pulled LOW, the OPA3684 supply  
current drops to less than 100µA/ch while the I/O pins go to a high  
impedance state.  
BW (MHz) vs GAIN  
1 of 3 Channels  
6
G = 1  
V+  
3
G = 2  
0
–3  
+
G = 5  
VO  
–6  
–9  
Z(S) IERR  
V–  
–12  
G = 10  
G = 20  
G = 50  
G = 100  
–15  
–18  
–21  
–24  
IERR  
RF  
RF = 800Ω  
10  
100  
200  
RG  
Low-Power  
Patent Pending  
Amplifier  
MHz  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
All trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
Copyright © 2002-2008, Texas Instruments Incorporated  
www.ti.com  
ABSOLUTE MAXIMUM RATINGS(1)  
ELECTROSTATIC  
DISCHARGE SENSITIVITY  
This integrated circuit can be damaged by ESD. Texas Instru-  
ments recommends that all integrated circuits be handled with  
appropriate precautions. Failure to observe proper handling  
and installation procedures can cause damage.  
Power Supply ............................................................................... ±6.5VDC  
Internal Power Dissipation................................. See Thermal Information  
Differential Input Voltage .................................................................. ±1.2V  
Input Voltage Range............................................................................ ±VS  
Storage Temperature Range: ID, IDBQ.........................–65°C to +125°C  
Lead Temperature (soldering, 10s) .............................................. +300°C  
Junction Temperature (TJ ) ........................................................... +175°C  
ESD Rating: HBM............................................................................ 1900V  
CDM ........................................................................... 1500V  
ESD damage can range from subtle performance degradation to  
complete device failure. Precision integrated circuits may be more  
susceptible to damage because very small parametric changes  
could cause the device not to meet its published specifications.  
NOTE: (1) Stresses above these ratings may cause permanent damage.  
Exposure to absolute maximum conditions for extended periods may degrade  
device reliability.  
OPA3684 RELATED PRODUCTS  
SINGLES  
DUALS  
TRIPLES  
QUADS  
FEATURES  
OPA684  
OPA691  
OPA2684  
OPA2691  
—
OPA4684  
Low-Power CFBplus  
High Slew Rate CFB  
OPA3691  
—
OPA685  
OPA692  
—
—
—
—
—
> 500MHz CFB  
Fixed-Gain Video Buffers  
OPA3692  
PACKAGE/ORDERING INFORMATION(1)  
SPECIFIED  
TEMPERATURE  
RANGE  
PACKAGE  
DESIGNATOR  
PACKAGE  
MARKING  
ORDERING  
NUMBER  
TRANSPORT  
MEDIA, QUANTITY  
PRODUCT  
PACKAGE-LEAD  
OPA3684  
SO-14  
D
"
–40°C to +85°C  
OPA3684  
OPA3684ID  
OPA3684IDR  
Rails, 58  
"
OPA3684  
"
"
"
"
Tape and Reel, 2500  
Tape and Reel, 250  
Tape and Reel, 2500  
SSOP-16  
DBQ  
–40°C to +85°C  
OPA3684  
OPA3684IDBQT  
OPA3684IDBQR  
"
"
"
"
NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at  
www.ti.com.  
PIN CONFIGURATION  
Top View  
SSOP  
Top View  
SO  
DIS A  
DIS B  
DIS C  
+VS  
DIS A  
DIS B  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
Output C  
–Input C  
+Input C  
–VS  
1
2
3
4
5
6
7
14 Output C  
13 –Input C  
12 +Input C  
11 –VS  
C
C
DIS C  
+VS  
+Input A  
–Input A  
Output A  
NC  
+Input A  
–Input A  
Output A  
+Input B  
–Input B  
Output B  
NC  
10 +Input B  
A
B
A
B
9
8
–Input B  
Output B  
OPA3684  
2
SBOS241C  
www.ti.com  
ELECTRICAL CHARACTERISTICS: VS = ±5V  
Boldface limits are tested at +25°C.  
RF = 800Ω, RL = 100Ω, and G = +2, unless otherwise noted.  
OPA3684ID, IDBQ  
TYP  
MIN/MAX OVER TEMPERATURE  
0
°
C to  
–40  
°
C to  
MIN/  
TEST  
MAX LEVEL(3)  
PARAMETER  
CONDITIONS  
+25°C  
+25°C(1)  
70°C(2)  
+85°C(2)  
UNITS  
AC PERFORMANCE (see Figure 1)  
Small-Signal Bandwidth (VO = 0.5VPP  
)
G = +1, RF = 800Ω  
G = +2, RF = 800Ω  
G = +5, RF = 800Ω  
250  
170  
138  
120  
95  
19  
1.4  
90  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
dB  
MHz  
V/µs  
V/µs  
ns  
typ  
min  
typ  
typ  
typ  
min  
max  
typ  
min  
min  
typ  
C
B
C
C
C
B
B
C
B
B
C
C
120  
118  
117  
G = +10, RF = 800Ω  
G = +20, RF = 800Ω  
G = +2, VO = 0.5VPP, RF = 800Ω  
RF = 800Ω, VO = 0.5VPP  
G = +2, VO = 4VPP  
G = –1, VO = 4V Step  
G = +2,VO = 4V Step  
G = +2, VO = 0.5V Step  
G = +2, VO = 4VStep  
G = +2, f = 5MHz, VO = 2VPP  
RL = 100Ω  
Bandwidth for 0.1dB Gain Flatness  
Peaking at a Gain of +1  
Large-Signal Bandwidth  
Slew Rate  
16  
4.8  
14  
5.9  
14  
6.3  
780  
750  
3
675  
680  
650  
660  
575  
650  
Rise-and-Fall Time  
6.8  
ns  
typ  
Harmonic Distortion  
2nd-Harmonic  
–67  
–82  
–70  
–84  
3.7  
9.4  
17  
0.04  
0.02  
70  
–59  
–66  
–66  
–82  
4.1  
11  
–59  
–65  
–65  
–81  
4.2  
–58  
–65  
–65  
–81  
4.4  
dBc  
dBc  
dBc  
max  
max  
max  
max  
max  
max  
max  
typ  
B
B
B
B
B
B
B
C
C
C
R
L ≥ 1kΩ  
RL = 100Ω  
L ≥ 1kΩ  
3rd-Harmonic  
R
dBc  
Input Voltage Noise  
f > 1MHz  
f > 1MHz  
f > 1MHz  
nV/√Hz  
pA/√Hz  
pA/√Hz  
%
deg  
dB  
Noninverting Input Current Noise  
Inverting Input Current Noise  
Differential Gain  
Differential Phase  
All Hostile Crosstalk  
12  
18.5  
12.5  
19  
18  
G = +2, NTSC, VO = 1.4VP, RL = 150Ω  
G = +2, NTSC, VO = 1.4VP, RL = 150Ω  
2 Channels, f = 5MHz  
3rd-Channel Measured  
typ  
typ  
DC PERFORMANCE(4)  
Open-Loop Transimpedance Gain (ZOL  
Input Offset Voltage  
Average Offset Voltage Drift  
Noninverting Input Bias Current  
Average Noninverting Input Bias Current Drift  
Inverting Input Bias Current  
)
VO = 0V, RL = 1kΩ  
VCM = 0V  
355  
±1.5  
160  
±3.9  
155  
±4.5  
±12  
±13.5  
±25  
153  
±4.7  
±12  
±14  
±30  
kΩ  
mV  
µV/°C  
µA  
nA/°C  
µA  
nA°/C  
min  
max  
max  
max  
max  
max  
max  
A
A
B
A
B
A
B
VCM = 0V  
VCM = 0V  
±5.0  
±5.0  
±12  
±17  
V
CM = 0V  
VCM = 0V  
VCM = 0V  
±18.5  
±35  
±19.5  
±40  
Average Inverting Input Bias Current Drift  
INPUT  
Common-Mode Input Range(5) (CMIR)  
Common-Mode Rejection Ratio (CMRR)  
Noninverting Input Impedance  
±3.75  
60  
50 || 2  
4.0  
±3.65  
53  
±3.65  
52  
±3.6  
52  
V
dB  
kΩ || pF  
Ω
min  
min  
typ  
A
A
C
C
VCM = 0V  
Inverting Input Resistance  
(RI)  
Open-Loop, DC  
typ  
OUTPUT  
Voltage Output Swing  
Current Output, Sourcing  
Current Output, Sinking  
1kΩ Load  
VO = 0  
VO = 0  
±4.1  
160  
–120  
0.006  
±3.9  
120  
–100  
±3.9  
115  
–95  
±3.8  
110  
–90  
V
min  
min  
min  
typ  
A
A
A
C
mA  
mA  
Ω
Closed-Loop Output Impedance  
G = +2, f = 100kHz  
DISABLE (Disabled LOW)  
Power-Down Supply Current (+VS)  
Disable Time  
Enable Time  
Off Isolation  
Output Capacitance in Disable  
Enable Voltage  
Disable Voltage  
VDIS = 0 (all channels)  
VIN = +1V, G = +2  
VIN = +1V, G = +2  
G = +2, 5MHz  
–300  
4
40  
–500  
–580  
–600  
µA  
ms  
ns  
dB  
pF  
V
max  
typ  
typ  
typ  
typ  
min  
max  
max  
A
C
C
C
C
A
A
A
70  
1.7  
3.4  
1.8  
80  
3.5  
1.7  
120  
3.6  
1.6  
130  
3.7  
1.5  
135  
V
µA  
Control Pin Input Bias Current (DIS)  
V
DIS = 0V/Channel  
POWER SUPPLY  
Specified Operating Voltage  
Maximum Operating Voltage Range  
Minimum Operating Voltage Range  
Max Quiescent Current  
Min Quiescent Current  
Power-Supply Rejection Ratio (–PSRR)  
±5  
V
V
V
mA  
mA  
dB  
typ  
max  
min  
max  
min  
typ  
C
A
C
A
A
A
±6  
±6  
±6  
±1.4  
1.7  
1.7  
60  
V
S = ±5V/per Channel  
1.8  
1.6  
54  
1.85  
1.55  
53  
1.85  
1.45  
53  
VS = ±5V/per Channel  
Input Referred  
TEMPERATURE RANGE  
Specification: D, DBQ  
–40 to +85  
°C  
typ  
C
Thermal Resistance, θJA  
Junction-to-Ambient  
D
SO-14  
100  
100  
°C/W  
°C/W  
typ  
typ  
C
C
DBQ SSOP-16  
NOTES:(1)Junctiontemperature=ambientfor+25°Ctestedspecifications. (2)Junctiontemperature=ambientatlowtemperaturelimit, junctiontemperature=ambient  
+2°C at high temperature limit for over temperature tested specifications. (3) Test levels: (A) 100% tested at +25°C. Over-temperature limits by characterization and  
simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out-of-node. VCM is the input  
common-mode voltage. (5) Tested < 3dB below minimum specified CMR at ± CMIR limits.  
OPA3684  
SBOS241C  
3
www.ti.com  
ELECTRICAL CHARACTERISTICS: VS = +5V  
Boldface limits are tested at +25°C.  
RF = 1.0kΩ, RL = 100Ω, and G = +2, unless otherwise noted.  
OPA3684ID, IDBQ  
TYP  
MIN/MAX OVER TEMPERATURE  
0
°
C to  
–40  
°
C to  
MIN/  
TEST  
MAX LEVEL(3)  
PARAMETER  
CONDITIONS  
+25°C  
+25°C(1)  
70°C(2)  
+85°C(2)  
UNITS  
AC PERFORMANCE (see Figure 3)  
Small-Signal Bandwidth (VO = 0.5VPP  
)
G = +1, RF = 1.0kΩ  
G = +2, RF = 1.0kΩ  
G = +5, RF = 1.0kΩ  
G = +10, RF = 1.0kΩ  
G = +20, RF = 1.0kΩ  
140  
110  
100  
90  
75  
21  
0.5  
86  
380  
4.3  
4.8  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
dB  
MHz  
V/µs  
ns  
typ  
min  
min  
typ  
C
B
C
C
C
B
B
C
B
C
C
86  
85  
82  
typ  
Bandwidth for 0.1dB Gain Flatness  
Peaking at a Gain of +1  
Large-Signal Bandwidth  
Slew Rate  
G = +2, VO < 0.5VPP, RF = 1.0kΩ  
12  
2.6  
11  
3.4  
10  
3.7  
min  
max  
typ  
min  
typ  
R
F = 1.0kΩ, VO < 0.5VPP  
G = 2, VO = 2VPP  
G = 2, VO = 2V Step  
G = 2, VO = 0.5V Step  
G = 2, VO = 2VStep  
300  
290  
285  
Rise-and-Fall Time  
ns  
typ  
Harmonic Distortion  
2nd-Harmonic  
G = 2, f = 5MHz, VO = 2VPP  
RL = 100Ω to VS/2  
–65  
–84  
–65  
–74  
3.7  
9.4  
17  
0.04  
0.07  
–60  
–62  
–64  
–70  
4.1  
11  
–59  
–61  
–63  
–70  
4.2  
–59  
–61  
–63  
–69  
4.4  
dBc  
dBc  
dBc  
max  
max  
max  
max  
max  
max  
max  
typ  
B
B
B
B
B
B
B
C
C
RL ≥ 1kΩ to VS/2  
3rd-Harmonic  
RL = 100Ω to VS/2  
RL ≥ 1kΩ to VS/2  
dBc  
Input Voltage Noise  
f > 1MHz  
f > 1MHz  
f > 1MHz  
nV/√Hz  
pA/√Hz  
pA/√Hz  
%
Noninverting Input Current Noise  
Inverting Input Current Noise  
Differential Gain  
12  
18.5  
12.5  
19  
18  
G = +2, NTSC, VO = 1.4VP, RL = 150Ω  
G = +2, NTSC, VO = 1.4VP, RL = 150Ω  
Differential Phase  
deg  
typ  
All Hostile Crosstalk  
2 Channels, f = 5MHz  
3rd-Channel Measured  
70  
dB  
typ  
C
DC PERFORMANCE(4)  
Open-Loop Transimpedance Gain (ZOL  
Input Offset Voltage  
Average Offset Voltage Drift  
Noninverting Input Bias Current  
Average Noninverting Input Bias Current Drift  
Inverting Input Bias Current  
)
VO = VS/2, RL = 100Ω to VS/2  
VCM = VS/2  
355  
±1.0  
160  
±3.4  
155  
±4.0  
±12  
±13.5  
±25  
153  
±4.2  
±12  
±14  
±30  
±16  
±30  
kΩ  
mV  
µV/°C  
µA  
nA/°C  
µA  
nA°/C  
min  
max  
max  
max  
max  
max  
max  
A
A
B
A
B
A
B
VCM = VS/2  
V
CM = VS/2  
±5  
±5  
±12  
±13  
VCM = VS/2  
VCM = VS/2  
VCM = VS/2  
±14.5  
±25  
Average Inverting Input Bias Current Drift  
INPUT  
Least Positive Input Voltage(5)  
Most Positive Input Voltage(5)  
Common-Mode Refection Ratio (CMRR)  
Noninverting Input Impedance  
Inverting Input Resistance (RI)  
1.25  
3.75  
58  
50 || 1  
4.5  
1.32  
3.68  
51  
1.35  
3.65  
50  
1.38  
3.62  
50  
V
V
dB  
kΩ || pF  
Ω
max  
min  
min  
typ  
A
A
A
C
C
VCM = VS/2  
Open-Loop  
typ  
OUTPUT  
Most Positive Output Voltage  
Least Positive Output Voltage  
Current Output, Sourcing  
Current Output, Sinking  
Closed-Loop Output Impedance  
RL = 1kΩ to VS/2  
RL = 1kΩ to VS/2  
VO = VS/2  
4.10  
0.9  
80  
3.9  
1.1  
65  
3.9  
1.1  
60  
3.8  
1.2  
55  
V
V
mA  
mA  
Ω
min  
max  
min  
min  
typ  
A
A
A
A
C
VO = VS/2  
70  
55  
50  
45  
G = +2, f = 100kHz  
DISABLE (Disabled LOW)  
Power-Down Supply Current (+VS)  
Off Isolation  
Output Capacitance in Disable  
Turn-On Glitch  
Turn-Off Glitch  
Enable Voltage  
Disable Voltage  
Control Pin Input Bias Current (DIS)  
VDIS = 0 (all channels)  
F = 5.0MHz  
–300  
70  
1.7  
µA  
dB  
pF  
mV  
mV  
V
typ  
typ  
typ  
typ  
typ  
min  
max  
max  
C
C
C
C
C
A
A
A
G = +2, RL = 150Ω, VIN = VS/2  
G = +2, RL = 150Ω, VIN = VS/2  
3.4  
1.8  
80  
3.5  
1.7  
120  
3.6  
1.6  
130  
3.7  
1.5  
135  
V
µA  
VDIS = 0V/Channel  
POWER SUPPLY  
Specified Single-Supply Operating Voltage  
Max Single-Supply Operating Voltage Range  
Min Single-Supply Operating Voltage Range  
Max Quiescent Current  
Min Quiescent Current  
Power-Supply Rejection Ratio (+PSRR)  
5
V
V
V
mA  
mA  
dB  
typ  
max  
min  
max  
min  
typ  
C
A
C
A
A
C
12  
12  
12  
2.8  
1.44  
1.44  
65  
VS = +5V/per Channel  
VS = +5V/per Channel  
Input Referred  
1.55  
1.30  
1.55  
1.20  
1.55  
1.15  
TEMPERATURE RANGE  
Specification: D, DBQ  
–40 to +85  
°C  
typ  
C
Thermal Resistance, θJA Junction-to-Ambient  
D
SO-14  
100  
100  
°C/W  
°C/W  
typ  
typ  
C
C
DBQ SSOP-16  
NOTES:(1)Junctiontemperature=ambientfor+25°Ctestedspecifications. (2)Junctiontemperature=ambientatlowtemperaturelimit, junctiontemperature=ambient  
+1°C at high temperature limit for over temperature tested specifications. (3) Test levels: (A) 100% tested at +25°C. Over-temperature limits by characterization and  
simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out-of-node. VCM is the input  
common-mode voltage. (5) Tested < 3dB below minimum specified CMR at ± CMIR limits.  
OPA3684  
4
SBOS241C  
www.ti.com  
TYPICAL CHARACTERISTICS: VS = ±5V  
At TA = +25°C, G = +2, RF = 800Ω, and RL = 100Ω, unless otherwise noted.  
NONINVERTING SMALL-SIGNAL  
FREQUENCY RESPONSE  
INVERTING SMALL-SIGNAL FREQUENCY RESPONSE  
VO = 0.5Vp-p  
6
3
3
0
VO = 0.5Vp-p  
RF = 800Ω  
RF = 800Ω  
G = 1  
G = 2  
0
–3  
–3  
–6  
–9  
–12  
–6  
G = 5  
G = 10  
–9  
G = 20  
G = –1  
G = –2  
G = –5  
G = –10  
G = –16  
–12  
–15  
–18  
G = 50  
See Figure 1  
G = 100  
See Figure 2  
1
10  
Frequency (MHz)  
100  
200  
1
10  
Frequency (MHz)  
100  
200  
NONINVERTING LARGE-SIGNAL  
FREQUENCY RESPONSE  
INVERTING LARGE-SIGNAL FREQUENCY RESPONSE  
9
6
3
0
G = +2  
RL = 100Ω  
G = –1  
L = 100Ω  
VO = 0.5Vp-p  
R
VO = 0.5Vp-p  
1Vp-p  
–3  
–6  
–9  
–12  
VO = 1Vp-p  
2Vp-p  
5Vp-p  
3
VO = 2Vp-p  
VO = 5Vp-p  
0
See Figure 1  
See Figure 2  
–3  
1
10  
100  
200  
1
10  
100  
200  
Frequency (MHz)  
Frequency (MHz)  
NONINVERTING PULSE RESPONSE  
G = +2  
INVERTING PULSE RESPONSE  
0.8  
0.6  
1.6  
0.8  
0.6  
1.6  
G = –1  
1.2  
1.2  
0.4  
0.8  
0.4  
0.8  
Large-Signal Right Scale  
Small-Signal Left Scale  
0.2  
0.4  
0.2  
0.4  
0
0
0
0
Small-Signal Left Scale  
Large-Signal Right Scale  
–0.2  
–0.4  
–0.6  
–0.8  
–0.4  
–0.8  
–1.2  
–1.6  
–0.2  
–0.4  
–0.6  
–0.8  
–0.4  
–0.8  
–1.2  
–1.6  
See Figure 1  
See Figure 2  
Time (10ns/div)  
Time (10ns/div)  
OPA3684  
SBOS241C  
5
www.ti.com  
TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)  
At TA = +25°C, G = +2, RF = 800Ω, and RL = 100Ω, unless otherwise noted.  
HARMONIC DISTORTION vs LOAD RESISTANCE  
HARMONIC DISTORTION vs FREQUENCY  
VO = 2Vp-p  
–50  
–55  
–60  
–65  
–70  
–75  
–80  
–85  
–90  
–50  
–60  
–70  
–80  
–90  
VO = 2Vp-p  
f = 5MHz  
G = +2  
RL = 100Ω  
2nd-Harmonic  
2nd-Harmonic  
3rd-Harmonic  
3rd-Harmonic  
See Figure 1  
See Figure 1  
0.1  
1
10  
20  
100  
0.5  
1
1k  
Load Resistance (Ω)  
Frequency (MHz)  
HARMONIC DISTORTION vs OUTPUT VOLTAGE  
f = 5MHz  
5MHz HARMONIC DISTORTION vs SUPPLY VOLTAGE  
VO = 2Vp-p  
–50  
–60  
–70  
–80  
–90  
–50  
–60  
–70  
–80  
–90  
RL = 100Ω  
R
L = 100Ω  
2nd-Harmonic  
2nd-Harmonic  
3rd-Harmonic  
3rd-Harmonic  
1
5
±2.5  
±3  
±3.5  
±4  
±4.5  
±5  
±5.5  
±6  
Output Voltage (Vp-p)  
Supply Voltage (±V)  
HARMONIC DISTORTION vs NONINVERTING GAIN  
2nd-Harmonic  
HARMONIC DISTORTION vs INVERTING GAIN  
2nd-Harmonic  
–50  
–55  
–60  
–65  
–70  
–75  
–80  
–85  
–90  
–50  
–55  
–60  
–65  
–70  
–75  
–80  
–85  
–90  
3rd-Harmonic  
3rd-Harmonic  
1
10  
20  
10  
20  
Inverting Gain (V/V)  
Noninverting Gain (V/V)  
OPA3684  
6
SBOS241C  
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TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)  
At TA = +25°C, G = +2, RF = 800Ω, and RL = 100Ω, unless otherwise noted.  
2-TONE, 3RD-ORDER  
INTERMODULATION DISTORTION  
INPUT VOLTAGE AND CURRENT NOISE DENSITY  
Inverting Current Noise  
–50  
–60  
–70  
–80  
–90  
100  
10  
1
20MHz  
17pA/√Hz  
Noninverting Current Noise  
+5V  
PI  
50Ω  
9.4pA/√Hz  
PO  
OPA3684  
50Ω  
50Ω  
10MHz  
–5V  
800Ω  
800Ω  
5MHz  
1MHz  
Voltage Noise  
3.7nV/√Hz  
100  
1k  
10k  
100k  
1M  
10M  
–8 –7 –6 –5 –4 –3 –2 –1  
0
1
2
3
4
5
6
7
8
Frequency (Hz)  
Power at Load (each tone, dBm)  
DISABLED FEEDTHROUGH  
DISABLE TIME  
–40  
–50  
–60  
–70  
–80  
–90  
–100  
6
5
4
3
2
1
0
G = +2  
DIS = 0  
V
VDIS  
VIN = 1VDC  
See Figure 1  
VOUT  
See Figure 1  
0.1  
1
10  
100  
0
2
4
6
8
10  
12  
14  
16  
Frequency (MHz)  
Time (ms)  
SMALL-SIGNAL BANDWIDTH vs CLOAD  
12pF  
RS vs CLOAD  
50  
40  
30  
20  
10  
0
9
6
5pF  
0.5dB Peaking  
100pF  
75pF  
3
+5V  
RS  
VI  
VO  
OPA3684  
50Ω  
0
CL  
1kΩ  
50pF  
33pF  
–5V  
800Ω  
–3  
–6  
800Ω  
20pF  
100  
1
10  
100  
1
10  
Frequency (MHz)  
300  
CLOAD (pF)  
OPA3684  
SBOS241C  
7
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TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)  
At TA = +25°C, G = +2, RF = 800Ω, and RL = 100Ω, unless otherwise noted.  
OPEN-LOOP TRANSIMPEDANCE GAIN AND PHASE  
vs FREQUENCY  
CMRR and PSRR vs FREQUENCY  
CMRR  
120  
100  
80  
60  
40  
20  
0
0
70  
60  
50  
40  
30  
20  
10  
0
20log (ZOL  
)
–30  
–60  
–90  
–120  
–150  
–180  
+PSRR  
–PSRR  
ZOL  
102  
103  
104  
105  
106  
107  
108  
109  
102  
103  
104  
105  
106  
107  
108  
Frequency (Hz)  
Frequency (Hz)  
COMPOSITE VIDEO DIFFERENTIAL GAIN/PHASE  
OUTPUT CURRENT AND VOLTAGE LIMITATIONS  
5
4
0.10  
0.09  
0.08  
0.07  
0.06  
0.05  
0.04  
0.03  
0.02  
0.01  
0
1W Power  
Limit  
Gain = +2  
NTSC, Positive Video  
3
2
1
dG  
0
–1  
–2  
–3  
–4  
–5  
dP  
Each  
Channel  
1W Power  
Limit  
1
2
3
4
–150  
–100  
–50  
0
50  
100  
150  
Number of 150Ω Video Loads  
I
O (MA)  
SUPPLY AND OUTPUT CURRENT  
vs AMBIENT TEMPERATURE  
TYPICAL DC DRIFT OVER AMBIENT TEMPERATURE  
4
3
1.9  
1.8  
1.7  
1.6  
1.5  
200  
175  
150  
125  
100  
Sourcing Output Current  
2
1
Noninverting Input Bias Current  
Input Offset Voltage  
Supply Current  
0
–1  
–2  
–3  
–4  
Sinking Output Current  
Inverting Input Bias Current  
–50  
–25  
0
25  
50  
75  
100  
125  
–25  
0
25  
50  
75  
100  
125  
Ambient Temperature (°C)  
Ambient Temperature (°C)  
OPA3684  
8
SBOS241C  
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TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)  
At TA = +25°C, G = +2, RF = 800Ω, and RL = 100Ω, unless otherwise noted.  
ALL HOSTILE CROSSTALK  
SETTLING TIME  
–20  
–25  
–30  
–35  
–40  
–45  
–50  
–55  
–60  
–65  
–70  
0.05  
0.04  
0.03  
0.02  
0.01  
0
2V Step  
See Figure 1  
1Vp-p Output  
2-Channels, 100Ω Load  
–0.01  
–0.02  
–0.03  
–0.04  
–0.05  
0.1  
1
10  
100  
0
10  
20  
30  
40  
50  
60  
Time (ns)  
Frequency (MHz)  
NONINVERTING OVERDRIVE RECOVERY  
INVERTING OVERDRIVE RECOVERY  
4.0  
3.2  
8.0  
8.0  
6.4  
8.0  
6.4  
6.4  
2.4  
4.8  
4.8  
4.8  
1.6  
3.2  
3.2  
3.2  
Output Voltage  
Right Scale  
0.8  
1.6  
1.6  
1.6  
0
0
0
0
Output Voltage  
–0.8  
–1.6  
–2.4  
–3.2  
–4.0  
–1.6  
–3.2  
–4.8  
–6.4  
–8.0  
–1.6  
–3.2  
–4.8  
–6.4  
–8.0  
–1.6  
–3.2  
–4.8  
–6.4  
–8.0  
Right Scale  
See Figure 1  
Input Voltage  
Left Scale  
Input Voltage  
Left Scale  
See Figure 2  
Time (100ns/div)  
Time (100ns/div)  
INPUT AND OUTPUT VOLTAGE RANGE  
vs SUPPLY VOLTAGE  
CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY  
6
5
100  
10  
1/3  
OPA3684  
4
3
ZO  
800Ω  
2
1
Input  
Voltage  
Range  
Output  
Voltage  
Range  
800Ω  
0
1
–1  
–2  
–3  
–4  
–5  
–6  
0.01  
0.001  
± 2  
± 3  
± 4  
Supply Voltage (±V)  
± 5  
± 6  
100  
1k  
10k  
100k  
1M  
10M  
100M  
Frequency (Hz)  
OPA3684  
SBOS241C  
9
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TYPICAL CHARACTERISTICS: VS = +5V  
At TA = +25°C, G = +2, RF = 1kΩ, and RL = 100Ω, unless otherwise noted.  
NONINVERTING SMALL-SIGNAL  
FREQUENCY RESPONSE  
INVERTING SMALL-SIGNAL FREQUENCY RESPONSE  
6
3
3
0
G = 50  
RF = 1kΩ  
RF = 1.0kΩ  
G = 100  
G = 1  
G = 2  
0
–3  
–3  
–6  
–9  
–12  
–6  
G = 20  
G = 10  
–9  
G = –1  
G = –2  
G = –5  
G = –10  
–12  
–15  
–18  
G = 5  
G = –20  
See Figure 3  
See Figure 4  
1
10  
Frequency (MHz)  
100  
200  
1
10  
100  
200  
Frequency (MHz)  
NONINVERTING LARGE-SIGNAL  
FREQUENCY RESPONSE  
INVERTING LARGE-SIGNAL FREQUENCY RESPONSE  
9
6
3
0
VO = 0.2Vp-p  
VO = 0.5Vp-p  
0.2Vp-p  
0.5Vp-p  
VO = 1Vp-p  
VO = 2Vp-p  
1Vp-p  
2Vp-p  
–3  
–6  
–9  
–12  
3
0
–3  
1
10  
Frequency (MHz)  
100  
200  
1
10  
100  
200  
Frequency (MHz)  
NONINVERTING PULSE RESPONSE  
INVERTING PULSE RESPONSE  
0.4  
0.3  
1.6  
0.4  
0.3  
1.6  
1.2  
1.2  
0.2  
0.8  
0.2  
0.8  
Large-Signal Right Scale  
Small-Signal Left Scale  
0.1  
0.4  
0.1  
0.4  
0
0
0
0
Small-Signal Left Scale  
Large-Signal Right Scale  
–0.1  
–0.2  
–0.3  
–0.4  
–0.4  
–0.8  
–1.2  
–1.6  
–0.1  
–0.2  
–0.3  
–0.4  
–0.4  
–0.8  
–1.2  
–1.6  
See Figure 3.  
See Figure 4  
Time (10ns/div)  
Time (10ns/div)  
OPA3684  
10  
SBOS241C  
www.ti.com  
TYPICAL CHARACTERISTICS: VS = +5V (Cont.)  
At TA = +25°C, G = +2, RF = 1kΩ, and RL = 100Ω, unless otherwise noted.  
HARMONIC DISTORTION vs LOAD RESISTANCE  
HARMONIC DISTORTION vs FREQUENCY  
VO = 2Vp-p  
–50  
–55  
–60  
–65  
–70  
–75  
–80  
–85  
–90  
–50  
–60  
–70  
–80  
–90  
VO = 2Vp-p  
f = 5MHz  
RL = 100Ω  
3rd-Harmonic  
2nd-Harmonic  
3rd-Harmonic  
2nd-Harmonic  
See Figure 3  
See Figure 3  
0.1  
1
10  
20  
100  
1k  
Load Resistance (Ω)  
Frequency (MHz)  
2-TONE, 3RD-ORDER  
HARMONIC DISTORTION vs OUTPUT VOLTAGE  
2nd-Harmonic  
INTERMODULATION DISTORTION  
–50  
–60  
–70  
–80  
–90  
–50  
–60  
–70  
–80  
–90  
20MHz  
10MHz  
5MHz  
3rd-Harmonic  
See Figure 3  
See Figure 3  
0.5  
1
2
3
–15 –14 –13 –12 –11 –10 –9 –8 –7 –6 –5 –4 –3  
Output Voltage (Vp-p)  
Power at Load (each tone, dBm)  
SUPPLY AND OUTPUT CURRENT  
vs AMBIENT TEMPERATURE  
COMPOSITE VIDEO DIFFERENTIAL GAIN/PHASE  
100  
90  
80  
70  
60  
50  
1.5  
1.4  
1.3  
1.2  
1.1  
1.0  
0.16  
0.14  
0.12  
0.10  
0.08  
0.06  
0.04  
0.02  
0
G = +2  
NTSC, Positive Video  
Right-Scale  
Supply Current  
Left-Scale  
Sourcing Output Current  
dP  
Left-Scale  
Sinking Output Current  
dG  
1
2
3
4
–50  
–25  
0
25  
50  
75  
100  
125  
Number of 150Ω Video Loads  
Ambient Temperature (°C)  
OPA3684  
SBOS241C  
11  
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mode signal across the input stage, the slew rate for inverting  
operation is typically higher and the distortion performance is  
slightly improved. An additional input resistor, RM, is included  
in Figure 2 to set the input impedance equal to 50Ω. The  
parallel combination of RM and RG set the input impedance.  
As the desired gain increases for the inverting configuration,  
APPLICATIONS INFORMATION  
LOW-POWER, CURRENT-FEEDBACK OPERATION  
The triple-channel OPA3684 gives a new level of perfor-  
mance in low-power, current-feedback op amps. Using a  
new input stage buffer architecture, the OPA3684 CFBPLUS  
amplifier holds nearly constant AC performance over a wide  
gain range. This closed-loop internal buffer gives a very low  
and linearized impedance at the inverting node, isolating the  
amplifier’s AC performance from gain element variations.  
This allows both the bandwidth and distortion to remain  
nearly constant over gain, moving closer to the ideal current-  
feedback performance of gain bandwidth independence.  
This low-power amplifier also delivers exceptional output  
power—it’s ±4V swing on ±5V supplies with > 100mA output  
drive gives excellent performance into standard video loads  
or doubly-terminated 50Ω cables. Single +5V supply opera-  
tion is also supported with similar bandwidths but with re-  
duced output power capability. For lower quiescent power in  
a CFBPLUS amplifier, consider the OPA683 family; while for  
higher output power, consider the OPA691 family.  
RG is adjusted to achieved the desired gain, while RM is also  
adjusted to hold a 50Ω input match. A point will be reached  
where RG will equal 50Ω, RM is removed, and the input match  
is set by RG only. With RG fixed to achieve an input match to  
50Ω, increasing RF will increase the gain. This will, however,  
quickly reduce the achievable bandwidth as the feedback  
resistor increases from its recommended value of 800Ω. If  
the source does not require an input match to 50Ω, either  
adjust RM to get the desired load, or remove it and let the RG  
resistor alone provide the input load.  
+5V  
+
0.1µF  
6.8µF  
50Ω  
Figure 1 shows the DC-coupled, gain of +2, dual power-  
supply circuit used as the basis of the ±5V Electrical and  
Typical Characteristics for each channel. For test purposes,  
the input impedance is set to 50Ω with a resistor to ground  
and the output impedance is set to 50Ω with a series output  
resistor. Voltage swings reported in the Electrical Character-  
istics are taken directly at the input and output pins while load  
powers (dBm) are defined at a matched 50Ω load. For  
the circuit of Figure 1, the total effective load will be  
100Ω || 1600Ω = 94Ω. Gain changes are most easily accom-  
plished by simply resetting the RG value, holding RF constant  
at its recommended value of 800Ω.  
DIS  
1/3  
OPA3684  
50Ω Load  
RG  
RF  
50Ω Source  
800Ω  
800Ω  
VI  
RM  
53.6Ω  
0.1µF  
6.8µF  
+
–5V  
FIGURE 2. DC-Coupled, G = –1V/V, Bipolar Supply Specifi-  
+5V  
cations and Test Circuit.  
+
These circuits show ±5V operation. The same circuits can be  
applied with bipolar supplies from ±2.5V to ±6V. Internal  
supply independent biasing gives nearly the same perfor-  
mance for the OPA3684 over this wide range of supplies.  
Generally, the optimum feedback resistor value (for nomi-  
nally flat frequency response at G = +2) will increase in value  
as the total supply voltage across the OPA3684 is reduced.  
0.1µF  
6.8µF  
50Ω  
VI  
DIS  
50Ω Source  
RM  
1/3  
50Ω  
OPA3684  
50Ω Load  
RF  
800Ω  
See Figure 3 for the AC-coupled, single +5V supply, gain of  
+2V/V circuit configuration used as a basis for the +5V only  
Electrical and Typical Characteristics for each channel. The  
key requirement of broadband single-supply operation is to  
maintain input and output signal swings within the usable  
voltage ranges at both the input and the output. The circuit  
of Figure 3 establishes an input midpoint bias using a simple  
resistive divider from the +5V supply (two 10kΩ resistors) to  
the noninverting input. The input signal is then AC-coupled  
into this midpoint voltage bias. The input voltage can swing  
to within 1.25V of either supply pin, giving a 2.5Vp-p input  
signal range centered between the supply pins. The input  
impedance of Figure 3 is set to give a 50Ω input match. If the  
source does not require a 50Ω match, remove this and drive  
RG  
800Ω  
0.1µF  
6.8µF  
+
–5V  
FIGURE 1. DC-Coupled, G = +2V/V, Bipolar Supply Speci-  
fications and Test Circuit.  
Figure 2 shows the DC-coupled, gain of –1V/V, dual power-  
supply circuit used as the basis of the Inverting Typical  
Characteristics for each channel. Inverting operation offers  
several performance benefits. Since there is no common-  
OPA3684  
12  
SBOS241C  
www.ti.com  
directly into the blocking capacitor. The source will then see  
the 5kΩ load of the biasing network as a load. The gain  
resistor (RG) is AC-coupled, giving the circuit a DC gain of +1,  
which puts the noninverting input DC bias voltage (2.5V) on  
the output as well. The feedback resistor value has been  
adjusted from the bipolar ±5V supply condition to re-optimize  
for a flat frequency response in +5V only, gain of +2,  
operation. On a single +5V supply, the output voltage can  
swing to within 1.0V of either supply pin while delivering more  
than 70mA output current—easily giving a 3Vp-p output  
swing into 100Ω (8dBm maximum at the matched 50Ω load).  
The circuit of Figure 3 shows a blocking capacitor driving into  
a 50Ω output resistor, then into a 50Ω load. Alternatively, the  
blocking capacitor could be removed if the load is tied to a  
supply midpoint or to ground if the DC current then required  
by the load is acceptable.  
The circuits of Figure 3 and 4 show single-supply operation  
at +5V. These same circuits may be used up to single  
supplies of +12V with minimal change in the performance of  
the OPA3684.  
+5V  
+
0.1µF  
6.8µF  
10kΩ  
10kΩ  
DIS  
0.1µF  
50Ω  
50Ω Load  
1/3  
OPA3684  
0.1µF  
RG  
1.0kΩ  
RF  
1.0kΩ  
50Ω Source  
0.1µF  
VI  
RM  
52.3Ω  
+5V  
FIGURE 4. AC-Coupled, G = –1V/V, Single-Supply Specifi-  
+
0.1µF  
6.8µF  
0.1µF  
cations and Test Circuit.  
10kΩ  
10kΩ  
50Ω Source  
0.1µF  
DIS  
VI  
LOW-POWER, VIDEO LINE DRIVER APPLICATIONS  
50Ω  
50Ω Load  
1/3  
RM  
50Ω  
For low-power, video line driving, the OPA3684 provides the  
output current and linearity to support 3 channels of either  
single video lines, or up to 4 video lines in parallel on each  
output. Figure 5 shows a typical ±5V supply video line driver  
application where only one channel is shown and only a  
single line is being driven. The improved 2nd-harmonic  
distortion of the CFBPLUS architecture, along with the  
OPA3684’s high output current and voltage, gives excep-  
tional differential gain and phase performance for a low-  
power solution. As the Typical Characteristics show, a single  
video load shows a dG/dP of 0.04%/0.02°. Multiple loads  
may be driven on each output, with minimal x-talk, while the  
dG/dP is still < 0.1%/0.1° for up to 4 parallel video loads. The  
slew rate and gain of 2 bandwidth are also suitable to  
moderate resolution RGB applications.  
OPA3684  
RF  
1kΩ  
RG  
1kΩ  
0.1µF  
FIGURE 3. AC-Coupled, G = +2V/V, Single-Supply Specifi-  
cations and Test Circuit.  
Figure 4 shows the AC-coupled, single +5V supply, gain of  
–1V/V circuit configuration used as a basis for the inverting  
+5V only Typical Characteristics for each channel. In this  
case, the midpoint DC bias on the noninverting input is also  
decoupled with an additional 0.1µF capacitor. This reduces  
the source impedance at higher frequencies for the  
noninverting input bias current noise. This 2.5V bias on the  
noninverting input pin appears on the inverting input pin and,  
since RG is DC-blocked by the input capacitor, will also  
appear at the output pin. One advantage to inverting opera-  
tion is that since there is no signal swing across the input  
stage, higher slew rates and operation to even lower supply  
voltages is possible. To retain a 1Vp-p output capability,  
operation down to a 3V supply is allowed. At a +3V supply,  
the input stage is saturated, but for the inverting configuration  
of a current-feedback amplifier, wideband operation is re-  
tained even under this condition.  
+5V  
VIDEOIN  
DIS  
Supply decoupling not shown.  
75Ω  
Coax  
75Ω Load  
75Ω  
OPA3684  
1kΩ  
1kΩ  
–5V  
FIGURE 5. Noninverting Differential I/O Amplifier.  
OPA3684  
SBOS241C  
13  
www.ti.com  
LOW-POWER RGB MUX/LINE DRIVER  
When one channel is shutdown, the feedback network is still  
present, slightly attenuating the signal and combining in  
parallel with the 78.7Ω to give a 75Ω source impedance.  
Using the shutdown feature, two OPA3684s can provide an  
easy low-power way to select one of two possible RGB  
sources for moderate resolution monitors. Figure 6 shows a  
recommended circuit where each of the color outputs are  
combined in a way that provides a net gain of 1 to the  
matched 75Ω load with a 75Ω output impedance. This brings  
the two outputs for each color together through a 78.7Ω  
resistor with a slightly > 2 gain provided by the amplifiers.  
Since the OPA3684 does not disable quickly, this approach  
is not suitable for pixel-by-pixel multiplexing—however, it  
does provide an easy way to switch between two possible  
RGB sources. The output swing provided by the active  
channel will divide back through the inactive channel feed-  
back to appear at the inverting input of the OFF channel. To  
retain good pulse fidelity, or low distortion, this divided down  
output signal at the inverting inputs of the OFF channels, plus  
the OFF channel input signals, should not exceed 0.7Vp-p.  
As the signal across the buffers of the inactive channels  
exceeds 0.7Vp-p, diodes across the inputs begin to turn on  
causing a nonlinear load to the active channel. This will  
degrade signal purity under those conditions.  
+5V  
VDIS  
+5V  
Power Supply  
De-Coupling Not Shown  
U1  
R1  
G1  
B1  
78.7Ω  
78.7Ω  
78.7Ω  
1/3  
OPA3684  
75Ω  
VOUT Red  
LOW-POWER, FLEXIBLE GAIN, DIFFERENTIAL  
RECEIVER  
75Ω Line  
681Ω  
806Ω  
The 3 channels available in the OPA3684 can be applied to  
a very flexible differential to single-ended receiver. Since the  
bandwidth does not depend on the gain setting, the gain  
setting element of Figure 7 (RG) can be adjusted over a wide  
range with minimal impact on resulting bandwidth. Fre-  
quency-response shaping elements may be included in RG  
as well to provide line equalization or filtering in the final  
output signal.  
1/3  
OPA3684  
75Ω  
VOUT Green  
75Ω Line  
681Ω  
806Ω  
1/3  
OPA3684  
75Ω  
VOUT Blue  
+5  
75Ω Line  
V1  
1/3  
OPA3684  
681Ω  
806Ω  
402Ω  
–5V  
+5  
–5  
806Ω  
+5V  
(1 + 2(806Ω)/RG) (V1 – V2)  
1/3  
OPA3684  
402Ω  
U2  
R2  
G2  
B2  
RG  
78.7Ω  
78.7Ω  
78.7Ω  
1/3  
OPA3684  
–5  
806Ω  
75Ω  
806Ω  
+5  
681Ω  
806Ω  
806Ω  
1/3  
OPA3684  
V2  
High-Speed INA (>120MHz)  
1/3  
OPA3684  
–5  
75Ω  
FIGURE 7. Low-Power, Wide Gain Range, Differential Receiver.  
681Ω  
806Ω  
The first two amplifiers provide the differential gain function  
with a common-mode gain of 1. The second amplifier per-  
forms the differencing function to remove the common-mode  
(referencing the output to ground if the 402Ω resistor is  
grounded) and providing a differential gain of 1. The resistors  
have been scaled to provide the same output loading on  
each first stage amplifier. Typical bandwidths for the circuit of  
Figure 7 exceed 120MHz.  
1/3  
OPA3684  
75Ω  
681Ω  
806Ω  
–5V  
FIGURE 6. Wideband 2x1 RGB Multiplexer.  
14  
OPA3684  
SBOS241C  
www.ti.com  
WIDEBAND PGA FOR ADC DRIVING  
0.7Vp-p, diodes across the inputs begin to turn on causing a  
nonlinear load to the active channel. This will degrade signal  
fidelity under those conditions.  
Using the 3 channels of the OPA3684, and the shutdown  
feature, can give an easy to use PGA function—which can  
be applied to driving an ADC. Since the bandwidth does not  
vary with gain for the CFBPLUS OPA3684, each channel can  
be set up to a desired gain setting, with each of the  
noninverting inputs driven with the same input signal. Select-  
ing one of the 3 channels passes on the input with the gain  
setting provided by the selected channel. Figure 8 shows an  
example where the channels are set to gains of 2, 5, and 10.  
Again, the output signal will be divided down back to the  
inverting inputs of the inactive channels. To retain good pulse  
fidelity, or low distortion, this divided down output signal at  
the inverting inputs of the OFF channels, plus the OFF  
channel input signals, should not exceed 0.7Vp-p. As the  
signal across the buffers of the inactive channels exceeds  
VIDEO DAC RECONSTRUCTION FILTER  
Wideband current-feedback op amps make ideal elements  
for implementing high-speed active filters where the amplifier  
is used as a fixed gain block inside a passive RC circuit  
network. The triple channel OPA3684 can be used as a very  
effective video Digital-to-Analog Converter (DAC) recon-  
struction filter and line driver. Figure 9 shows an example of  
this where the delay-equalized filter compensates for the  
DAC’s sin(x)/x response, and minimizes aliasing artifacts. It  
is shown here as a single +5V design expecting a 13.5MSPS  
DAC sampling rate, and giving a 5.5MHz cutoff frequency.  
+5V  
74HC238  
+5V  
Power-supply  
Y0  
decoupling not shown.  
D1  
D2  
Y1  
Y2  
20Ω  
G = +2  
1/3  
OPA3684  
0.1µF  
100Ω  
100Ω  
100Ω  
4.99kΩ  
4.99kΩ  
806Ω  
200Ω  
806Ω  
0.1µF  
REFT  
+3.5V  
REFB  
+1.5V  
G = +5  
VIN  
0.1µF  
1/3  
OPA3684  
+In  
50Ω  
ADS826  
10-Bit  
60MSPS  
100pF  
200Ω  
20Ω  
806Ω  
–In  
CM  
0.1µF  
G = +10  
1/3  
OPA3684  
90.9Ω  
806Ω  
–5V  
FIGURE 8. Wideband PGA for ADC Driving.  
100pF  
100pF  
+5V  
Video  
In  
100µF  
402Ω  
806Ω  
806Ω  
97.6Ω  
237Ω  
+5V  
82.5Ω  
243Ω  
412Ω  
1/3  
220pF  
56pF  
OPA3684  
75.5Ω  
+5V  
1/3  
OPA3684  
VO  
220pF  
56pF  
1/3  
OPA3684  
806Ω  
120pF  
806Ω  
806Ω  
953Ω  
+5V  
100µF  
953Ω  
FIGURE 9. Composite Video Filter.  
OPA3684  
SBOS241C  
15  
www.ti.com  
The first stage buffers the video DAC output to the first  
3rd-order filter section. This stage also provides group delay  
equalization while the 2nd and 3rd stages each give a 3rd-  
order low-pass response with sin(x)/x equalization. Figure 10  
shows the frequency response for the filter of Figure 9.  
OPERATING SUGGESTIONS  
SETTING RESISTOR VALUES TO OPTIMIZE BANDWIDTH  
Any current-feedback op amp like the OPA3684 can hold  
high bandwidth over signal-gain settings with the proper  
adjustment of the external resistor values. A low-power part  
like the OPA3684 typically shows a larger change in band-  
width due to the significant contribution of the inverting input  
impedance to loop-gain changes as the signal gain is changed.  
Figure 11 shows a simplified analysis circuit for any current-  
feedback amplifier.  
20  
10  
f–3dB  
0
–10  
–20  
–30  
–40  
–50  
VI  
α
VO  
RI  
0
1
10  
100  
Z(S) iERR  
Frequency (MHz)  
iERR  
RF  
FIGURE 10. Video Filter Frequency Response.  
RG  
DESIGN-IN TOOLS  
DEMONSTRATION FIXTURES  
Two printed circuit boards (PCBs) are available to assist in  
the initial evaluation of circuit performance using the OPA3684  
in its two package options. Both of these are offered free of  
charge as unpopulated PCBs, delivered with a user's guide.  
The summary information for these fixtures is shown in  
Table I.  
FIGURE 11. Current-Feedback Transfer Function Analysis  
Circuit.  
The key elements of this current-feedback op amp model  
are:  
α
RI  
Buffer gain from the noninverting input to the inverting input  
Buffer output impedance  
ORDERING  
NUMBER  
LITERATURE  
NUMBER  
PRODUCT  
PACKAGE  
iERR  
Z(S)  
Feedback error current signal  
OPA3684ID  
OPA3684IDBQ  
SO-14  
SSOP-16  
DEM-OPA-SO-3B  
DEM-OPA-SSOP-3B  
SBOU018  
SBOU019  
Frequency-dependent open-loop transimpedance gain  
from iERR to VO  
TABLE I. Demonstration Fixtures by Package.  
The buffer gain is typically very close to 1.00 and is normally  
neglected from signal gain considerations. It will, however,  
The demonstration fixtures can be requested at the Texas  
Instruments web site (www.ti.com) through the OPA3684  
product folder.  
set the CMRR for  
a single op amp differential  
amplifier configuration. For the buffer gain α < 1.0 and  
CMRR = –20 • log(1 – α). The closed-loop input stage buffer  
used in the OPA3684 gives a buffer gain more closely  
approaching 1.00 and this shows up in a slightly higher  
CMRR than previous current-feedback op amps.  
MACROMODELS  
Computer simulation of circuit performance using SPICE is  
often useful in predicting the performance of analog circuits  
and systems. This is particularly true for Video and RF  
amplifier circuits where parasitic capacitance and inductance  
can have a major effect on circuit performance. Check the TI  
web site (www.ti.com) for SPICE macromodels within the  
OPA3684 product folder. These models do a good job of  
predicting small-signal AC and transient performance under  
a wide variety of operating conditions. They do not do as well  
in predicting distortion or dG/dP characteristics. Most of  
these models do not attempt to distinguish between the  
package types in their small-signal AC performance.  
RI, the buffer output impedance, is a critical portion of the  
bandwidth control equation. The OPA3684 reduces this  
element to approximately 4.0Ω using the local loop gain of  
the input buffer stage. This significant reduction in output  
impedance, on very low power, contributes significantly to  
extending the bandwidth at higher gains.  
A current-feedback op amp senses an error current in the  
inverting node (as opposed to a differential input error volt-  
age for a voltage-feedback op amp) and passes this on to  
the output through an internal frequency-dependent  
OPA3684  
16  
SBOS241C  
www.ti.com  
transimpedance gain. The Typical Characteristics show this  
open-loop transimpedance response. This is analogous to  
the open-loop voltage gain curve for a voltage-feedback op  
amp. Developing the transfer function for the circuit of Figure 14  
gives Equation 1:  
inverting node voltage. While it is always important to keep  
the inverting node capacitance low for any current-feedback  
op amp, it is critically important for the OPA3684. External  
layout capacitance in excess of 2pF will start to peak the  
frequency response. This peaking can be easily reduced by  
increasing the feedback resistor value—but it is preferable,  
from a noise and dynamic range standpoint, to keep that  
capacitance low, allowing a close to nominal 800Ω feedback  
resistor for flat frequency response. Very high parasitic  
capacitance values on the inverting node (> 5pF) can possi-  
bly cause input stage oscillation that cannot be filtered by a  
feedback element adjustment.  
(1)  
RF  
α 1+  
RG  
RF + RI 1+  
Z(S)  
VO  
α NG  
RF + RI NG  
=
=
V
RF  
I
1+  
Z(S)  
RG  
1+  
At very high gains, 2nd-order effects in the inverting output  
impedance cause the overall response to peak up. If desired,  
it is possible to retain a flat frequency response at higher  
gains by adjusting the feedback resistor to higher values as  
the gain is increased. Since the exact value of feedback that  
will give a flat frequency response depends strongly in  
inverting and output node parasitic capacitance values, it is  
best to experiment in the specific board with increasing  
values until the desired flatness (or pulse response shape) is  
obtained. In general, increasing RF (and adjusting RG to the  
desired gain) will move towards flattening the response,  
while decreasing it will extend the bandwidth at the cost of  
some peaking.  
RF  
NG = 1+  
RG  
This is written in a loop-gain analysis format where the errors  
arising from a non-infinite open-loop gain are shown in the  
denominator. If Z(S) were infinite over all frequencies, the  
denominator of Equation 1 would reduce to 1 and the ideal  
desired signal gain shown in the numerator would be achieved.  
The fraction in the denominator of Equation 1 determines the  
frequency response. Equation 2 shows this as the loop-gain  
equation.  
Z(S)  
(2)  
= Loop Gain  
RF + RI NG  
OUTPUT CURRENT AND VOLTAGE  
The OPA3684 provides output voltage and current capabili-  
ties that can support the needs of driving doubly-terminated  
50Ω lines. For a 100Ω load at the gain of +2 (see Figure 1),  
the total load is the parallel combination of the 100Ω load and  
the 1.6kΩ total feedback network impedance. This 94Ω load  
will require no more than 40mA output current to support  
the ±3.8V minimum output voltage swing specified for  
100Ω loads. This is well under the specified minimum  
+110mA/–90mA output current specifications over the full  
temperature range.  
If 20 • log(RF + NG • RI) were drawn on top of the open-loop  
transimpedance plot, the difference between the two would  
be the loop gain at a given frequency. Eventually, Z(S) rolls off  
to equal the denominator of Equation 2 at which point the  
loop gain has reduced to 1 (and the curves have intersected).  
This point of equality is where the amplifier’s closed-loop  
frequency response given by Equation 1 will start to roll off,  
and is exactly analogous to the frequency at which the noise  
gain equals the open-loop voltage gain for a voltage-feed-  
back op amp. The difference here is that the total impedance  
in the denominator of Equation 2 may be controlled some-  
what separately from the desired signal gain (or NG).  
The specifications described above, though familiar in the  
industry, consider voltage and current limits separately. In  
many applications, it is the voltage • current, or V-I product,  
which is more relevant to circuit operation. Refer to the  
Output Voltage and Current Limitations curve in the Typical  
Characteristics. The X- and Y-axes of this graph show the  
zero-voltage output current limit and the zero-current output  
voltage limit, respectively. The four quadrants give a more  
detailed view of the OPA3684’s output drive capabilities.  
Superimposing resistor load lines onto the plot shows the  
available output voltage and current for specific loads.  
The OPA3684 is internally compensated to give a maximally  
flat frequency response for RF = 800Ω at NG = 2 on ±5V  
supplies. That optimum value goes to 1.0kΩ on a single +5V  
supply. Normally, with a current-feedback amplifier, it is  
possible to adjust the feedback resistor to hold this band-  
width up as the gain is increased. The CFBPLUS architecture  
has reduced the contribution of the inverting input impedance  
to provide exceptional bandwidth to higher gains without  
adjusting the feedback resistor value. The Typical Character-  
istics show the small-signal bandwidth over gain with a fixed  
feedback resistor.  
The minimum specified output voltage and current over  
temperature are set by worst-case simulations at the cold  
temperature extreme. Only at cold startup will the output  
current and voltage decrease to the numbers shown in the  
Electrical Characteristic tables. As the output transistors  
deliver power, their junction temperatures will increase,  
decreasing their VBE’s (increasing the available output  
voltage swing) and increasing their current gains (increasing  
the available output current). In steady-state operation, the  
Putting a closed-loop buffer between the noninverting and  
inverting inputs does bring some added considerations. Since  
the voltage at the inverting output node is now the output of  
a locally closed-loop buffer, parasitic external capacitance on  
this node can cause frequency response peaking for the  
transfer function from the noninverting input voltage to the  
OPA3684  
SBOS241C  
17  
www.ti.com  
available output voltage and current will always be greater  
than that shown in the over temperature specifications since  
the output stage junction temperatures will be higher than the  
minimum specified operating ambient.  
add the recommended series resistor as close as possible to  
the OPA3684 output pin (see Board Layout Guidelines).  
DISTORTION PERFORMANCE  
To maintain maximum output stage linearity, no output short-  
circuit protection is provided. This will not normally be a  
problem since most applications include a series-matching  
resistor at the output that will limit the internal power dissipa-  
tion if the output side of this resistor is shorted to ground.  
However, shorting the output pin directly to a power-supply  
pin will, in most cases, destroy the amplifier. If additional  
short-circuit protection is required, consider a small-series  
resistor in the power-supply leads. This will, under heavy  
output loads, reduce the available output voltage swing. A 5Ω  
series resistor in each power-supply lead will limit the internal  
power dissipation to less than 1W for an output short-circuit  
while decreasing the available output voltage swing only  
0.25V for up to 50mA desired load currents. This slight drop  
in available swing is more if multiple channels are driving  
heavy loads simultaneously. Always place the 0.1µF power-  
supply decoupling capacitors after these supply current lim-  
iting resistors directly on the supply pins. An alternative  
approach is to place the 5Ω inside the loop at each output of  
the amplifiers. This will provide some short-circuit protection,  
but hurts the phase margin under capacitive load conditions.  
The OPA3684 provides very low distortion in a low-power  
part. The CFBPLUS architecture also gives two significant  
areas of distortion improvement. First, in operating regions  
where the 2nd-harmonic distortion due to output stage  
nonlinearities is very low (frequencies < 1MHz, low output  
swings into light loads) the linearization at the inverting node  
provided by the CFBPLUS design gives 2nd-harmonic distor-  
tions that extend into the –90dBc region. Previous current-  
feedback amplifiers have been limited to approximately  
–85dBc due to the nonlinearities at the inverting input. The  
second area of distortion improvement comes in a distortion  
performance that is largely gain independent. To the extent  
that the distortion at a particular output power is output-stage  
dependent, 3rd-harmonics particularly (and to a lesser ex-  
tend 2nd-harmonic distortion) are constant as the gain is  
increased. This is due to the constant loop-gain versus signal  
gain provided by the CFBPLUS design. As shown in the  
Typical Characteristic curves, while the 3rd-harmonic is con-  
stant with gain, the 2nd-harmonic degrades at higher gains.  
This is largely due to board parasitic issues. Slightly  
imbalanced load return currents through the ground plane  
will couple into the gain resistor to cause a portion of the 2nd-  
harmonic distortion. At high gains, this imbalance has more  
gain to the output giving reduced 2nd-harmonic distortion.  
Differential stages using two of the channels together can  
reduce this 2nd-harmonic issue enormously by getting back  
to an essentially gain independent distortion.  
DRIVING CAPACITIVE LOADS  
One of the most demanding, and yet very common load  
conditions, for an op amp is capacitive loading. Often, the  
capacitive load is the input of an ADC—including additional  
external capacitance which may be recommended to im-  
prove ADC linearity. A high-speed, high open-loop gain  
amplifier like the OPA3684 can be very susceptible to de-  
creased stability and closed-loop response peaking when a  
capacitive load is placed directly on the output pin. When the  
amplifier’s open-loop output resistance is considered, this  
capacitive load introduces an additional pole in the signal  
path that can decrease the phase margin. Several external  
solutions to this problem have been suggested. When the  
primary considerations are frequency response flatness, pulse  
response fidelity, and/or distortion, the simplest and most  
effective solution is to isolate the capacitive load from the  
feedback loop by inserting a series isolation resistor between  
the amplifier output and the capacitive load. This does not  
eliminate the pole from the loop response, but rather shifts it  
and adds a zero at a higher frequency. The additional zero  
acts to cancel the phase lag from the capacitive load pole,  
thus increasing the phase margin and improving stability.  
Relative to alternative amplifiers with < 2mA/ch supply cur-  
rent, the OPA3684 holds much lower distortion at higher  
frequencies (> 5MHz) and to higher gains. Generally, until  
the fundamental signal reaches very high frequency or power  
levels, the 2nd-harmonic will dominate the distortion with a  
lower 3rd-harmonic component. Focusing then on the 2nd-  
harmonic, increasing the load impedance improves distortion  
directly. Remember that the total load includes the feedback  
network—in the noninverting configuration (see Figure 1) this  
is the sum of RF + RG, while in the inverting configuration it  
is just RF. Also, providing an additional supply decoupling  
capacitor (0.1µF) between the supply pins (for bipolar opera-  
tion) improves the 2nd-order distortion slightly (3dB to 6dB).  
In most op amps, increasing the output voltage swing in-  
creases harmonic distortion directly. A low-power part like  
the OPA3684 includes quiescent boost circuits to provide the  
large-signal bandwidth in the Electrical Characteristics. These  
act to increase the bias in a very linear fashion only when  
high slew rate or output power is required. This also acts to  
actually reduce the distortion slightly at higher output power  
levels. The Typical Characteristic curves show the 2nd-  
harmonic holding constant from 500mVp-p to 5Vp-p outputs  
while the 3rd-harmonics actually decrease with increasing  
output power.  
The Typical Characteristics show the recommended RS vs  
CLOAD and the resulting frequency response at the load. The  
1kΩ resistor shown in parallel with the load capacitor is a  
measurement path and may be omitted. Parasitic capacitive  
loads greater than 5pF can begin to degrade the perfor-  
mance of the OPA3684. Long PCB traces, unmatched cables,  
and connections to multiple devices can easily cause this  
value to be exceeded. Always consider this effect carefully, and  
OPA3684  
18  
SBOS241C  
www.ti.com  
The OPA3684 has an extremely low 3rd-order harmonic  
distortion, particularly for light loads and at lower frequen-  
cies. This also gives low 2-tone, 3rd-order intermodulation  
distortion as shown in the Typical Characteristic curves.  
Since the OPA3684 includes internal power boost circuits to  
retain good full-power performance at high frequencies and  
outputs, it does not show a classical 2-tone, 3rd-order  
intermodulation intercept characteristic. Instead, it holds rela-  
tively low and constant 3rd-order intermodulation spurious  
levels over power. The Typical Characteristic curves show  
this spurious level as a dBc below the carrier at fixed center  
frequencies swept over single-tone power at a matched 50Ω  
load. These spurious levels drop significantly (> 12dB) for  
lighter loads than the 100Ω used in the 2-Tone, 3rd-Order  
Intermodulation Distortion curve. Converter inputs for in-  
stance will see < –82dBc 3rd-order spurious to 10MHz for  
full-scale inputs. For even lower 3rd-order intermodulation  
distortion to much higher frequencies, consider the OPA3691  
triple or OPA691 and OPA685 single-channel current-feed-  
back amplifiers.  
The total output spot noise voltage can be computed as the  
square root of the sum of all squared output noise voltage  
contributors. Equation 3 shows the general form for the  
output noise voltage using the terms presented in Figure 12.  
(3)  
2
2
2
EO  
=
ENI + IBNRS + 4kTRS NG2 + I R  
+ 4kTRFNG  
(
)
(
)
BI  
F
Dividing this expression by the noise gain (NG = (1+RF/RG))  
will give the equivalent input referred spot noise voltage at  
the noninverting input, as shown in Equation 4.  
(4)  
2
IBIRF  
NG  
4kTRF  
NG  
2
2
EN  
=
ENI + IBNRS + 4kTRS  
+
+
(
)
Evaluating these two equations for the OPA3684 circuit and  
component values presented in Figure 1 will give a total  
output spot noise voltage of 16.3nV/√Hz and a total equiva-  
lent input spot noise voltage of 8.1nV/√Hz. This total input  
referred spot noise voltage is higher than the 3.7nV/√Hz  
specification for the op amp voltage noise alone. This reflects  
the noise added to the output by the inverting current noise  
times the feedback resistor. As the gain is increased, this  
fixed output noise power term contributes less to the total  
output noise and the total input referred voltage noise given  
by Equation 3 will approach just the 3.7nV/√Hz of the op amp  
itself. For example, going to a gain of +20 in the circuit of  
Figure 1, adjusting only the gain resistor to 42.1Ω, will give  
a total input referred noise of 3.9nV/√Hz. A more complete  
description of op amp noise analysis can be found in the  
Texas Instruments application note, AB-103, Noise Analysis  
for High-Speed Op Amps (SBOA066), located at www.ti.com.  
NOISE PERFORMANCE  
Wideband current-feedback op amps generally have a higher  
output noise than comparable voltage-feedback op amps.  
The OPA3684 offers an excellent balance between voltage  
and current noise terms to achieve low output noise in a low-  
power amplifier. The inverting current noise (17pA/√Hz) is  
comparable to most other current-feedback op amps while  
the input voltage noise (3.7nV/√Hz) is lower than any unity-  
gain stable, comparable slew rate, voltage-feedback op amp.  
This low input voltage noise was achieved at the price of  
higher noninverting input current noise (9.4pA/√Hz). As long  
as the AC source impedance looking out of the noninverting  
node is less than 200Ω, this current noise will not contribute  
significantly to the total output noise. The op amp input  
voltage noise and the two input current noise terms combine  
to give low output noise under a wide variety of operating  
conditions. Figure 12 shows the op amp noise analysis  
model with all the noise terms included. In this model, all  
noise terms are taken to be noise voltage or current density  
DC ACCURACY AND OFFSET CONTROL  
A current-feedback op amp like the OPA3684 provides  
exceptional bandwidth in high gains, giving fast pulse settling  
but only moderate DC accuracy. The Electrical Specifica-  
tions show an input offset voltage comparable to high slew  
rate voltage-feedback amplifiers. The two input bias currents,  
however, are somewhat higher and are unmatched. Whereas  
bias current cancellation techniques are very effective with  
most voltage-feedback op amps, they do not generally re-  
duce the output DC offset for wideband current-feedback op  
amps. Since the two input bias currents are unrelated in both  
magnitude and polarity, matching the source impedance  
looking out of each input to reduce their error contribution to  
the output is ineffective. Evaluating the configuration of  
Figure 1, using worst-case +25°C input offset voltage and the  
two input bias currents, gives a worst-case output offset  
range equal to:  
terms in either nV/√Hz or pA/√Hz  
.
ENI  
1/3  
OPA3684  
EO  
RS  
IBN  
RF  
ERS  
√4kTRS  
√4kTRF  
IBI  
RG  
4kT  
RG  
4kT = 1.6E –20J  
at 290°K  
±(NG • VOS(MAX)) + (IBN • RS/2 • NG) ± (IBI • RF)  
where NG = noninverting signal gain  
= ±(2 • 3.9mV) ± (12µA • 25Ω • 2) ± (800Ω • 17µA)  
= ±7.8mV + 0.6mV ± 13.6mV  
FIGURE 12. Op Amp Noise Analysis Model.  
= ±22mV  
OPA3684  
SBOS241C  
19  
www.ti.com  
While the last term, the inverting bias current error, is  
dominant in this low-gain circuit, the input offset voltage will  
become the dominant DC error term as the gain exceeds  
5V/V. Where improved DC precision is required in a high-  
speed amplifier, consider the OPA656 unity gain stable and  
OPA657 high-gain bandwidth JFET input op amps.  
appear as the impedance looking back into the output, but  
the circuit will still show very high forward and reverse  
isolation. If configured as an inverting amplifier, the input and  
output will be connected through the feedback network  
resistance (RF + RG) giving relatively poor input to output  
isolation.  
Each channel of the OPA3684 provides very high power gain  
on low quiescent current levels. When disabled, internal high  
impedance nodes discharge slowly which, with the excep-  
tional power gain provided, give a self powering characteris-  
tic that leads to a slow turn off characteristic. Typical full turn-  
off times to rated 100µA disabled supply current are 4ms.  
Turn-on times are very fast—less than 40ns.  
DISABLE OPERATION  
The OPA3684 provides an optional disable feature on each  
channel that may be used to reduce system power when  
channel operation is not required. If the VDIS control pin is  
left unconnected, each channel of the OPA3684 will operate  
normally. To disable, the control pin must be asserted low.  
Figure 13 shows a simplified internal circuit for the disable  
control feature.  
The circuit of Figure 13 will control the disable feature using  
standard 5V CMOS or TTL level signals when the OPA3684  
is operated on ±5V or single +5V supplies. Since this circuit  
is really a current mode control, disable operation for a single  
+12V supply should be implemented using an open collector  
+VS  
logic family.  
THERMAL ANALYSIS  
40kΩ  
The OPA3684 will not require external heatsinking for most  
applications. Maximum desired junction temperature will set  
the maximum allowed internal power dissipation as de-  
scribed below. In no case should the maximum junction  
temperature be allowed to exceed 175°C.  
Q1  
Operating junction temperature (TJ) is given by TA + PD • θJA  
.
The total internal power dissipation (PD) is the sum of  
quiescent power (PDQ) and additional power dissipated in the  
output stage (PDL) to deliver load power. Quiescent power is  
simply the specified no-load supply current times the total  
supply voltage across the part. PDL will depend on the  
required output signal and load but would, for a grounded  
resistive load, be at a maximum when the output is fixed at  
a voltage equal to 1/2 either supply voltage (for equal bipolar  
supplies). Under this condition PDL = VS2/(4 • RL) where RL  
includes feedback network loading.  
25kΩ  
250kΩ  
IS  
VDIS  
Control  
–VS  
FIGURE 13. Simplified Disable Control Circuit.  
In normal operation, base current to Q1 is provided through  
the 250kΩ resistor while the emitter current through the 40kΩ  
resistor sets up a voltage drop that is inadequate to turn on  
the two diodes in Q1’s emitter. As VDIS is pulled low,  
additional current is pulled through the 40kΩ resistor eventu-  
ally turning on these two diodes (≈ 30µA). At this point, any  
further current pulled out of VDIS goes through those diodes  
holding the emitter-base voltage of Q1 at approximately 0V.  
This shuts off the collector current out of Q1, turning the  
amplifier off. The supply current in the disable mode are only  
those required to operate the circuit of Figure 13.  
Note that it is the power in the output stage and not into the  
load that determines internal power dissipation.  
As an absolute worst-case example, compute the maximum  
TJ using an OPA3684IDBQ (SSOP-16 package) in the circuit  
of Figure 1 operating at the maximum specified ambient  
temperature of +85°C with all channels driving a grounded  
100Ω load.  
PD = 10V • 5.6mA + 3 • (52 /(4 • (100Ω 1.6kΩ))) = 255mW  
Maximum TJ = +85°C + (0.255W • 100°C/W) = 111°C.  
When disabled, the output and input nodes go to a high  
impedance state. If the OPA3684 is operating in a gain of +1  
(with a 800Ω feedback resistor still required for stability), this  
will show a very high impedance (1.7pF || 1MΩ) at the output  
and exceptional signal isolation. If operating at a gain greater  
than +1, the total feedback network resistance (RF + RG) will  
This maximum operating junction temperature is well below  
most system level targets. Most applications will be lower  
than this since an absolute worst-case output stage power  
was assumed in this calculation with all 3 channels running  
maximum output power simultaneously.  
OPA3684  
20  
SBOS241C  
www.ti.com  
BOARD LAYOUT GUIDELINES  
design. Note that a 800Ω feedback resistor, rather than  
a direct short, is required for the unity-gain follower  
application. A current-feedback op amp requires a feed-  
back resistor even in the unity-gain follower configura-  
tion to control stability.  
Achieving optimum performance with a high-frequency am-  
plifier like the OPA3684 requires careful attention to board  
layout parasitics and external component types. Recommen-  
dations that will optimize performance include:  
d) Connections to other wideband devices on the board  
may be made with short direct traces or through onboard  
transmission lines. For short connections, consider the  
trace and the input to the next device as a lumped  
capacitive load. Relatively wide traces (50mils to 100mils)  
should be used, preferably with ground and power  
planes opened up around them. Estimate the total ca-  
pacitive load and set RS from the plot of recommended  
a) Minimize parasitic capacitance to any AC ground for  
all of the signal I/O pins. Parasitic capacitance on the  
output and inverting input pins can cause instability; on  
the noninverting input, it can react with the source  
impedance to cause unintentional bandlimiting. To re-  
duce unwanted capacitance, a window around the sig-  
nal I/O pins should be opened in all of the ground and  
power planes around those pins. Otherwise, ground and  
power planes should be unbroken elsewhere on the  
board.  
RS vs CLOAD  
. Low parasitic capacitive loads  
(< 5pF) may not need an RS since the OPA3684 is  
nominally compensated to operate with a 2pF parasitic  
load. If a long trace is required, and the 6dB signal loss  
intrinsic to a doubly-terminated transmission line is ac-  
ceptable, implement a matched impedance transmis-  
sion line using microstrip or stripline techniques (consult  
an ECL design handbook for microstrip and stripline  
layout techniques). A 50Ω environment is normally not  
necessary on board, and in fact a higher impedance  
environment will improve distortion, see the distortion  
versus load plots. With a characteristic board trace  
impedance defined based on board material and trace  
dimensions, a matching series resistor into the trace  
from the output of the OPA3684 is used, as well as a  
terminating shunt resistor at the input of the destination  
device. Remember also that the terminating impedance  
will be the parallel combination of the shunt resistor and  
the input impedance of the destination device; this total  
effective impedance should be set to match the trace  
impedance. The high output voltage and current capabil-  
ity of the OPA3684 allows multiple destination devices to  
be handled as separate transmission lines, each with  
their own series and shunt terminations. If the 6dB  
attenuation of a doubly-terminated transmission line is  
unacceptable, a long trace can be series-terminated at  
the source end only. Treat the trace as a capacitive load  
in this case and set the series resistor value as shown  
in the plot of RS vs CLOAD. This will not preserve signal  
integrity as well as a doubly-terminated line. If the input  
impedance of the destination device is LOW, there will  
be some signal attenuation due to the voltage divider  
formed by the series output into the terminating imped-  
ance.  
b) Minimize the distance (< 0.25") from the power-supply  
pins to high-frequency 0.1µF decoupling capacitors. At  
the device pins, the ground and power-plane layout  
should not be in close proximity to the signal I/O pins.  
Avoid narrow power and ground traces to minimize  
inductance between the pins and the decoupling capaci-  
tors. The power-supply connections should always be  
decoupled with these capacitors. An optional supply de-  
coupling capacitor (0.01µF) across the two power sup-  
plies (for bipolar operation) will improve 2nd-harmonic  
distortion performance. Larger (2.2µF to 6.8µF)  
decoupling capacitors, effective at lower frequencies,  
should also be used on the main supply pins. These may  
be placed somewhat farther from the device and may be  
shared among several devices in the same area of the  
PCB.  
c) Careful selection and placement of external compo-  
nents will preserve the high-frequency performance  
of the OPA3684. Resistors should be a very low reac-  
tance type. Surface-mount resistors work best and allow  
a tighter overall layout. Metal film and carbon composi-  
tion axially-leaded resistors can also provide good high-  
frequency performance. Again, keep their leads and  
PCB trace length as short as possible. Never use  
wirewound type resistors in a high-frequency applica-  
tion. Since the output pin and inverting input pin are the  
most sensitive to parasitic capacitance, always position  
the feedback and series output resistor, if any, as close  
as possible to the output pin. The quad amplifier pinout  
allows each output and inverting input to be connected  
by the feedback element with virtually no trace length.  
Other network components, such as noninverting input  
termination resistors, should also be placed close to the  
package. The frequency response is primarily deter-  
mined by the feedback resistor value as described  
previously. Increasing its value will reduce the peaking  
at higher gains, while decreasing it will give a more  
peaked frequency response at lower gains. The 800Ω  
feedback resistor used in the Typical Characteristics at  
a gain of +2 on ±5V supplies is a good starting point for  
e) Socketing a high-speed part like the OPA3684 is not  
recommended. The additional lead length and pin-to-  
pin capacitance introduced by the socket can create an  
extremely troublesome parasitic network which can make  
it almost impossible to achieve a smooth, stable fre-  
quency response. Best results are obtained by soldering  
the OPA3684 onto the board.  
OPA3684  
SBOS241C  
21  
www.ti.com  
INPUT AND ESD PROTECTION  
The OPA3684 is built using a very high-speed complemen-  
tary bipolar process. The internal junction breakdown volt-  
ages are relatively low for these very small geometry devices.  
These breakdowns are reflected in the Absolute Maximum  
Ratings table where an absolute maximum 13V across the  
supply pins is reported. All device pins have limited ESD  
protection using internal diodes to the power supplies, as  
shown in Figure 14.  
+VCC  
External  
Pin  
Internal  
Circuitry  
These diodes provide moderate protection to input overdrive  
voltages above the supplies as well. The protection diodes  
can typically support 30mA continuous current. Where higher  
currents are possible (for example, in systems with ±15V  
supply parts driving into the OPA3684), current-limiting se-  
ries resistors should be added into the two inputs. Keep  
these resistor values as low as possible since high values  
degrade both noise performance and frequency response.  
–VCC  
FIGURE 14. Internal ESD Protection.  
OPA3684  
22  
SBOS241C  
www.ti.com  
Revision History  
DATE  
REVISION PAGE  
SECTION  
DESCRIPTION  
Changed Storage Temperature Range from −40°C to +125C to  
−65°C to +125C.  
2
Abs Max Ratings  
7/08  
C
3, 4  
Electrical Characteristics, Added minimum supply voltage.  
Power Supply  
6/06  
B
16  
23  
Design-In Tools  
Demonstration fixture numbers changed.  
Applications Information Added Revision History table.  
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.  
OPA3684  
SBOS241C  
23  
www.ti.com  
PACKAGE OPTION ADDENDUM  
www.ti.com  
16-Aug-2012  
PACKAGING INFORMATION  
Status (1)  
Eco Plan (2)  
MSL Peak Temp (3)  
Samples  
Orderable Device  
Package Type Package  
Drawing  
Pins  
Package Qty  
Lead/  
Ball Finish  
(Requires Login)  
OPA3684ID  
ACTIVE  
SOIC  
D
14  
50  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU Level-2-260C-1 YEAR  
OPA3684IDBQ  
OPA3684IDBQT  
PREVIEW  
ACTIVE  
SSOP  
SSOP  
DBQ  
DBQ  
16  
16  
TBD  
Call TI  
Call TI  
250  
250  
50  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU Level-2-260C-1 YEAR  
CU NIPDAU Level-2-260C-1 YEAR  
CU NIPDAU Level-2-260C-1 YEAR  
CU NIPDAU Level-2-260C-1 YEAR  
CU NIPDAU Level-2-260C-1 YEAR  
OPA3684IDBQTG4  
OPA3684IDG4  
OPA3684IDR  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
SSOP  
SOIC  
SOIC  
SOIC  
DBQ  
D
16  
14  
14  
14  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
D
2500  
2500  
Green (RoHS  
& no Sb/Br)  
OPA3684IDRG4  
D
Green (RoHS  
& no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
16-Aug-2012  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
16-Aug-2012  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
OPA3684IDBQT  
OPA3684IDR  
SSOP  
SOIC  
DBQ  
D
16  
14  
250  
180.0  
330.0  
12.4  
16.4  
6.4  
6.5  
5.2  
9.0  
2.1  
2.1  
8.0  
8.0  
12.0  
16.0  
Q1  
Q1  
2500  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
16-Aug-2012  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
OPA3684IDBQT  
OPA3684IDR  
SSOP  
SOIC  
DBQ  
D
16  
14  
250  
210.0  
367.0  
185.0  
367.0  
35.0  
38.0  
2500  
Pack Materials-Page 2  
IMPORTANT NOTICE  
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