OPA388ID [TI]
单路、10MHz、CMOS、零漂移、零交叉、真 RRIO 精密运算放大器 | D | 8 | -40 to 125;
| 型号： | OPA388ID |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 单路、10MHz、CMOS、零漂移、零交叉、真 RRIO 精密运算放大器 | D | 8 | -40 to 125 放大器 运算放大器 |
| 文件： | 总46页 (文件大小：3275K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OPA388,OPA2388,OPA4388
ZHCSFU1D – DECEMBER 2016 – REVISED JULY 2020
OPAx388 精密、零漂移、零交叉、真正的轨至轨输入/输出运算放大器
1 特性
3 说明
•
•
•
•
•
•
•
•
•
•
超低失调电压：±0.25µV
零漂移：±0.005µV/°C
OPAx388（OPA388、OPA2388 和 OPA4388）系列精
密运算放大器是超低噪声、快速稳定、零漂移、零交叉
器件，可实现轨至轨输入和输出运行。这些特性及出色
的交流性能与仅为 0.25µV 的失调电压以及
0.005µV/°C 的温漂相结合，使得 OPAx388 成为驱动
高精密模数转换器 (ADC) 或缓冲高分辨率数模转换器
(DAC) 输出的理想选择。该设计在驱动模数转换器
(ADC) 时具有出色的性能，而不会降低线性度。
OPA388（单通道版本）提供 VSSOP-8、SOT23-5 和
SOIC-8 三种封装。OPA2388（双通道版本）提供
VSSOP-8 和 SO-8 两种封装。OPA4388（四通道版
本）提供 TSSOP-14 和 SO-14 两种封装。所有版本的
额定工作温度范围均为 -40°C 至 +125°C。
零交叉：140dB CMRR 真正 RRIO
低噪声：7.0nV√Hz （1kHz 时）
无 1/f 噪声：140nVPP（0.1Hz 至 10Hz）
快速稳定：2µs（1V，0.01%）
增益带宽：10MHz
单电源：2.5V 至 5.5V
双电源：±1.25V 至 ±2.75V
真正的轨至轨输入和输出
• EMI/RFI 滤波输入
•
行业标准封装：
– 单通道电源版本采用 SOIC-8、SOT-23-5 和
VSSOP-8 封装
器件信息
封装(1)
封装尺寸（标称值）
4.90mm × 3.90mm
2.90mm × 1.60mm
3.00mm × 3.00mm
4.90mm × 3.90mm
3.00mm × 3.00mm
8.65mm x 3.90mm
5.00mm x 4.40mm
器件型号
– 双通道电源版本采用 SOIC-8 和 VSSOP-8 封装
– 四通道电源版本采用 SOIC-14 和 TSSOP-14 封
装
SOIC (8)
OPA388
SOT-23 (5)
VSSOP (8)
SOIC (8)
2 应用
OPA2388
OPA4388
VSSOP (8)
SOIC (14)
TSSOP (14)
•
•
•
•
•
•
•
商用网络和服务器 PSU
笔记本电脑电源适配器设计
称重计
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
实验室和现场仪表
电池测试
电子温度计
温度变送器
R3
2.53
2.52
2.51
2.5
3
25 kꢀ
2
R4
100 kꢀ
5 V
REF5025
1
RG
R4
R2
0
100 kꢀ
25 kꢀ
5 V
5 V
5 V
2.49
2.48
2.47
-1
-2
-3
+SENSE
œ
œ
OPA388
VOUT
OPA388
+
+
RG = 1 kΩ
œ100 œ80 œ60 œ40 œ20
R2
GND
GND
10 kꢀ
0
20 40 60 80 100
œSENSE
200 kΩ
Load Cell
ûR/R (ppm)
C001
G = 5 +
GND
RG
GND
OPA388 支持高精度、低误差测量
高 CMRR 仪表放大器应用中的 OPA388
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOS777
OPA388, OPA2388, OPA4388
ZHCSFU1D – DECEMBER 2016 – REVISED JULY 2020
www.ti.com.cn
Table of Contents
7.4 Device Functional Modes..........................................20
8 Application and Implementation..................................21
8.1 Application Information............................................. 21
8.2 Typical Applications.................................................. 21
9 Power Supply Recommendations................................25
10 Layout...........................................................................26
10.1 Layout Guidelines................................................... 26
10.2 Layout Example...................................................... 26
11 Device and Documentation Support..........................27
11.1 Device Support........................................................27
11.2 Documentation Support.......................................... 27
11.3 Related Links.......................................................... 27
11.4 Receiving Notification of Documentation Updates..28
11.5 Support Resources................................................. 28
11.6 Trademarks............................................................. 28
11.7 Electrostatic Discharge Caution..............................28
11.8 Glossary..................................................................28
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................4
6 Specifications.................................................................. 6
6.1 Absolute Maximum Ratings........................................ 6
6.2 ESD Ratings............................................................... 6
6.3 Recommended Operating Conditions.........................6
6.4 Thermal Information: OPA388.................................... 6
6.5 Thermal Information: OPA2388.................................. 7
6.6 Thermal Information: OPA4388.................................. 7
6.7 Electrical Characteristics: VS = ±1.25 V to ±2.75
V (VS = 2.5 to 5.5 V)..................................................... 7
6.8 Typical Characteristics..............................................10
7 Detailed Description......................................................18
7.1 Overview...................................................................18
7.2 Functional Block Diagram.........................................18
7.3 Feature Description...................................................19
Information.................................................................... 28
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision C (May 2019) to Revision D (July 2020)
Page
将 OPA2388 SOIC-8 (D) 封装从“预告信息（预发布）”更改为“生产数据（正在供货）”............................1
更改了典型应用原理图，以显示引用标识符的正确位置..................................................................................... 1
•
•
• Changed Figure 8-5 to show correct locations for reference designators ....................................................... 25
Changes from Revision B (January 2019) to Revision C (May 2019)
Page
•
将 OPA4388 从“预告信息（预发布）”更改为“生产数据（正在供货）”......................................................1
• Added VOS specifications for OPA4388.............................................................................................................7
• Added dVOS/dT specifications for OPA4388......................................................................................................7
• Added PSRR specifications for OPA4388.......................................................................................................... 7
• Added IB specifications for OPA4388.................................................................................................................7
• Added IOS specifications for OPA4388..............................................................................................................7
• Added CMRR specifications for OPA4388..........................................................................................................7
• Added AOL specifications for OPA4388.............................................................................................................7
Changes from Revision A (July 2018) to Revision B (January 2019)
Page
•
将 OPA388 DBV (SOT-23) 封装从“预发布”更改为“生产数据”....................................................................1
• Deleted redundant temperature specification in EC table.................................................................................. 7
• Added Figure 6, Offset Voltage vs Supply Voltage: OPA4388 .........................................................................10
• Added Figure 7, Offset Voltage Long Term Drift ..............................................................................................10
• Changed Figure 50, OPA388 Layout Example; updated for accuracy............................................................. 26
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Changes from Revision * (December 2016) to Revision A (July 2018)
Page
•
•
•
将器件状态从“生产数据”更改为“生产数据/混合状态”.................................................................................1
添加了 TI 参考设计的顶部导航链接.................................................................................................................... 1
在器件信息 表中，向 5 引脚 SOT-23 (OPA388)、8 引脚 SOIC (OPA2388)、14 引脚 SOIC 和 14 引脚 TSSOP
(OPA4388) 封装添加了预发布说明..................................................................................................................... 1
• Added package preview notes to Pin Configuration and Functions section.......................................................4
• AOL test condition changed to 0.15 V from 0.1 V...............................................................................................7
• AOL test condition changed to 0.15 V from 0.1 V...............................................................................................7
• AOL test condition changed to 0.25 V from 0.2 V...............................................................................................7
• AOL test condition changed to 0.3 V from 0.25 V...............................................................................................7
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5 Pin Configuration and Functions
NC
œIN
+IN
Vœ
1
2
3
4
8
7
6
5
NC
V+
OUT
Vœ
1
2
3
5
V+
œ
OUT
NC
+
+IN
4
œIN
Not to scale
Not to scale
图 5-1. OPA388 DBV Package, 5-Pin SOT-23, Top
图 5-2. OPA388 D and DGK Packages, 8-Pin SOIC
View
and VSSOP, Top View
Pin Functions: OPA388
PIN
OPA388
I/O
DESCRIPTION
NAME
D (SOIC),
DGK (VSSOP)
DBV (SOT-23)
2
4
3
I
I
Inverting input
–IN
+IN
NC
3
Noninverting input
1, 5, 8
No internal connection (can be left floating)
Output
—
—
OUT
V–
V+
6
4
7
1
O
2
5
Negative (lowest) power supply
Positive (highest) power supply
—
—
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OUT A
1
2
3
4
8
7
6
5
V+
OUT A
œIN A
+IN A
V+
1
2
3
4
5
6
7
14
13
12
11
10
9
OUT D
œIN D
+IN D
Vœ
œIN A
+IN A
Vœ
OUT B
œIN B
+IN B
+IN B
œIN B
OUT B
+IN C
œIN C
OUT C
Not to scale
图 5-3. OPA2388 8-Pin SOIC (D) Package and 8-Pin
8
VSSOP (DGK) Package, Top View
Not to scale
图 5-4. OPA4388 14-Pin SOIC (D) and TSSOP-14
(PW) Packages, Top View
Pin Functions: OPA2388 and OPA4388
PIN
OPA2388
OPA4388
I/O
DESCRIPTION
NAME
D (SOIC),
D (SOIC),
DGK (VSSOP)
PW (TSSOP)
2
6
2
6
I
I
Inverting input, channel A
Inverting input, channel B
Inverting input, channel C
Inverting input, channel D
Noninverting input, channel A
Noninverting input, channel B
Noninverting input, channel C
Noninverting input, channel D
Output, channel A
–IN A
–IN B
–IN C
–IN D
+IN A
+IN B
+IN C
+IN D
OUT A
OUT B
OUT C
OUT D
V–
9
I
—
13
3
I
—
3
I
5
5
I
10
12
1
I
—
—
1
I
O
O
O
O
7
7
Output, channel B
8
Output, channel C
—
—
4
14
11
4
Output, channel D
Negative (lowest) power supply
Positive (highest) power supply
—
—
V+
8
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
Single-supply
6
±3
Supply voltage
V
VS = (V+) – (V–)
Dual-supply
Common-mode
Differential
(V+) + 0.5
(V–) – 0.5
Voltage
Current
V
Signal input pins
Output short circuit(2)
Temperature
(V+) – (V–) + 0.2
±10
Continuous
150
mA
Continuous
Operating, TA
Junction, TJ
Storage, Tstg
–55
150
°C
150
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
±4000
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.5
NOM
MAX
5.5
UNIT
Single-supply
Dual-supply
V
Supply voltage, VS = (V+) – (V–)
±1.25
–40
±2.75
125
Specified temperature
°C
6.4 Thermal Information: OPA388
OPA388
DBV (SOT-23)
5 PINS
145.7
THERMAL METRIC(1)
D (SOIC)
8 PINS
116
DGK (VSSOP)
UNIT
5 PINS
177
69
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
60
94.8
RθJB
ΨJT
Junction-to-board thermal resistance
56
43.4
100
9.9
Junction-to-top characterization parameter
Junction-to-board characterization parameter
12.8
55.9
N/A
24.7
43.1
98.3
n/a
ΨJB
RθJC(bot) Junction-to-case (bottom) thermal resistance
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Thermal Information: OPA2388
OPA2388
THERMAL METRIC(1)
D (SOIC)
8 PINS
120.0
52.3
DGK (VSSOP)
UNIT
8 PINS
165
53
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
65.6
87
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
9.6
4.9
ΨJT
64.4
85
ΨJB
RθJC(bot)
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.6 Thermal Information: OPA4388
OPA4388
THERMAL METRIC(1)
D (SOIC)
14 PINS
86.4
PW (TSSOP)
14 PINS
109.6
27.4
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
46.3
41.0
56.1
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
11.3
1.5
ΨJT
40.7
54.9
ΨJB
RθJC(bot)
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.7 Electrical Characteristics: VS = ±1.25 V to ±2.75 V (VS = 2.5 to 5.5 V)
at TA = 25°C, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
OPA388, OPA2388
±0.25
±2.25
±5
±8
VS = 5.5 V
OPA4388
VOS
Input offset voltage
µV
OPA388, OPA2388
OPA4388
±7.5
±10.5
±0.05
±0.05
±1
TA = –40°C to +125°C
TA = –40°C to +125°C, VS = 5.5 V
TA = –40°C to +125°C
TA = –40°C to +125°C, VS = 5.5 V
OPA388, OPA2388
OPA4388
±0.005
±0.005
±0.1
dVOS/dT Input offset voltage drift
µV/°C
µV/V
OPA388, OPA2388
OPA4388
Power-supply rejection
PSRR
ratio
TA = –40°C to +125°C
±1.25
±3.5
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at TA = 25°C, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT BIAS CURRENT
±30
±350
±400
TA = 0°C to +85°C
RIN = 100 kΩ, OPA388, OPA2388
RIN = 100 kΩ, OPA4388
TA = –40°C to
+125°C
±700
IB
Input bias current
±30
±500
±600
TA = 0°C to +85°C
TA = –40°C to
±800
+125°C
pA
±700
±800
TA = 0°C to +85°C
RIN = 100 kΩ, OPA388, OPA2388
RIN = 100 kΩ, OPA4388
TA = –40°C to
+125°C
±800
IOS
Input offset current
Input voltage noise
±1000
±1100
TA = 0°C to +85°C
TA = –40°C to
±1100
+125°C
NOISE
EN
f = 0.1 Hz to 10 Hz
f = 10 Hz
0.14
µVPP
7
7
7
7
f = 100 Hz
Input voltage noise
density
eN
nV/√Hz
f = 1 kHz
f = 10 kHz
Input current noise
density
IN
f = 1 kHz
100
fA/√Hz
INPUT VOLTAGE
Common-mode voltage
range
(V–) –
VCM
(V+) + 0.1
V
0.1
VS = ±1.25 V
OPA388, OPA2388
124
138
(V–) – 0.1 V < VCM < (V+) + 0.1
V
VS = ±1.25 V
OPA4388
102
124
114
110
140
134
VS = ±2.75 V
Common-mode
rejection ratio
CMRR
dB
VS = ±1.25 V
OPA388, OPA2388
(V–) < VCM < (V+) + 0.1 V,
TA = –40°C to +125°C
VS = ±1.25 V
OPA4388
102
124
107
140
(V–) – 0.05 V < VCM < (V+) + 0.1
V, TA = –40°C to +125°C
VS = ±2.75 V
INPUT IMPEDANCE
Differential input
impedance
zid
zic
100 || 2
60 || 4.5
MΩ || pF
TΩ || pF
Common-mode input
impedance
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at TA = 25°C, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OPEN-LOOP GAIN
126
120
148
126
(V–) + 0.15 V < VO < (V+) – 0.15 V, RLOAD = 10 kΩ
(V–) + 0.15 V < VO < (V+) – 0.15
OPA388, OPA2388
V, RLOAD = 10 kΩ,
TA = –40°C to +125°C
(V–) + 0.15 V < VO < (V+) – 0.15
V, RLOAD = 10 kΩ, VS = 5.5 V
TA = –40°C to +125°C
OPA4388
120
126
AOL
Open-loop voltage gain
dB
126
120
148
148
(V–) + 0.25 V < VO < (V+) – 0.25 V, RLOAD = 2 kΩ
(V–) + 0.30 V < VO < (V+) – 0.30
OPA388, OPA2388
V, RLOAD = 2 kΩ
(V–) + 0.30 V < VO < (V+) – 0.30
OPA4388
120
126
V, RLOAD = 2 kΩ, VS = 5.5 V
TA = –40°C to +125°C
FREQUENCY RESPONSE
GBW
SR
Unity-gain bandwidth
Slew rate
10
5
MHz
V/µs
G = 1, 4-V step
Total harmonic
distortion + noise
THD+N
G = 1, f = 1 kHz, VO = 1 VRMS
0.0005%
0.75
VS = ±2.5 V, G = 1,
1-V step
To 0.1%
µs
tS
Settling time
VS = ±2.5 V, G = 1,
1-V step
To 0.01%
2
µs
µs
tOR
Overload recovery time VIN × G = VS
10
OUTPUT
No load
1
5
15
20
50
15
20
60
25
Positive rail
RLOAD = 10 kΩ
RLOAD = 2 kΩ
No load
20
5
Voltage output swing
from rail
VO
mV
10
40
10
±60
±30
Negative rail
RLOAD = 10 kΩ
RLOAD = 2 kΩ
TA = –40°C to +125°C, both rails, RLOAD = 10 kΩ
VS = 5.5 V
VS = 2.5 V
See 图 6-26
mA
mA
ISC
CLOAD
ZO
Short-circuit current
Capacitive load drive
Open-loop output
impedance
100
f = 1 MHz, IO = 0 A, see 图 6-25
Ω
POWER SUPPLY
IO = 0 A
1.7
1.7
1.9
1.9
2.4
2.4
2.6
2.6
VS = ±1.25 V (VS = 2.5 V)
VS = ±2.75 V (VS = 5.5 V)
TA = –40°C to
+125°C, IO = 0 A
Quiescent current per
amplifier
IQ
mA
IO = 0 A
TA = –40°C to
+125°C, IO = 0 A
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6.8 Typical Characteristics
Table 6-1. Table of Graphs
DESCRIPTION
FIGURE
图 6-1
Offset Voltage Production Distribution
Offset Voltage Drift Distribution From –40°C to +125°C
Offset Voltage vs Temperature
图 6-2
图 6-3
Offset Voltage vs Common-Mode Voltage
Offset Voltage vs Power Supply: OPA388 and OPA2388
Offset Voltage vs Power Supply: OPA4388
Offset Voltage Long Term Drift
图 6-4
图 6-5
图 6-6
图 6-7
Open-Loop Gain and Phase vs Frequency
Closed-Loop Gain and Phase vs Frequency
Input Bias Current vs Common-Mode Voltage
Input Bias Current vs Temperature
Output Voltage Swing vs Output Current (Maximum Supply)
CMRR and PSRR vs Frequency
图 6-8
图 6-9
图 6-10
图 6-11
图 6-12
图 6-13
CMRR vs Temperature
图 6-14
PSRR vs Temperature
图 6-15
0.1-Hz to 10-Hz Noise
图 6-16
Input Voltage Noise Spectral Density vs Frequency
THD+N Ratio vs Frequency
图 6-17
图 6-18
THD+N vs Output Amplitude
图 6-19
Spectral Content
图 6-20, 图 6-21
图 6-22
Quiescent Current vs Supply Voltage
Quiescent Current vs Temperature
Open-Loop Gain vs Temperature
Open-Loop Output Impedance vs Frequency
Small-Signal Overshoot vs Capacitive Load (10-mV Step)
No Phase Reversal
图 6-23
图 6-24
图 6-25
图 6-26
图 6-27
Positive Overload Recovery
图 6-28
Negative Overload Recovery
图 6-29
Small-Signal Step Response (10-mV Step)
Large-Signal Step Response (4-V Step)
Settling Time
图 6-30, 图 6-31
图 6-32 , 图 6-33
图 6-34, 图 6-35
图 6-36
Short-Circuit Current vs Temperature
Maximum Output Voltage vs Frequency
EMIRR vs Frequency
图 6-37
图 6-38
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at TA = 25°C, VS = ±2.5 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise
noted)
15
10
5
50
45
40
35
30
25
20
15
10
5
0
0
Input Offset Voltage (µV)
Input Offset Voltage Drift (µV/°C)
C002
C001
图 6-1. Offset Voltage Production Distribution
图 6-2. Offset Voltage Drift Distribution From –
40°C to +125°C
5
4
5
4
3
3
2
2
1
1
0
0
œ1
œ2
œ3
œ4
œ5
œ1
œ2
œ3
œ4
œ5
VCM = œ2.85 V
VCM = 2.85 V
0
25
50
75
100 125 150
0
1
2
3
œ75 œ50 œ25
œ3
œ2
œ1
Temperature (°C)
Input Common-mode Voltage (V)
C001
C003
图 6-3. Offset Voltage vs Temperature
图 6-4. Offset Voltage vs Common-Mode Voltage
8
5
4
3
6
4
2
2
1
0
0
œ1
œ2
œ3
œ4
œ5
-2
-4
-6
VS
=
1.25 V
VS
=
2.75 V
VS = ê 1.25 V
VS = ê 2.75 V
-8
1.2
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
1.4
1.6
1.8 2.2
Supply Voltage (V)
2
2.4
2.6
2.8
Supply Voltage (V)
C001
C308
图 6-6. Offset Voltage vs Supply Voltage: OPA4388
图 6-5. Offset Voltage vs Supply Voltage: OPA388
and OPA2388
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20
15
10
5
160
140
1±0
100
80
180
Open-Loop Gain
135
Open-Loop Phase
90
45
0
60
0
40
-5
±0
-10
-15
-20
0
±±0
±40
-45
1
10
100
1k 10k 100k 1M 10M
Frequency (Hz)
0
20
40
60
80
Days
100
120
140
160
C0±1
C309
3 typical units
图 6-8. Open-Loop Gain and Phase vs Frequency
图 6-7. Offset Voltage Long Term Drift
1500
60
G = +1
G= +10
G= +100
1000
500
0
40
20
0
-20
œ500
100
1k
10k
100k
1M
10M
0
1
2
3
œ3
œ2
œ1
Frequency (Hz)
Input Common-mode Voltage (V)
C004
C001
图 6-9. Closed-Loop Gain and Phase vs Frequency
图 6-10. Input Bias Current vs Common-Mode
Voltage
1.5
1.3
1.0
0.8
0.5
3
2.5
2
1.5
25°C
1
0.5
0
-0.5
-1
125°C
œ40°C
-1.5
-2
0.3
ios
-2.5
-3
0.0
0
25
50
75
100 125 150
0
10
20
30
40
50
60
70
80
90 100
œ75 œ50 œ25
Temperature (°C)
Output Current (mA)
C001
C001
图 6-11. Input Bias Current vs Temperature
图 6-12. Output Voltage Swing vs Output Current
(Maximum Supply)
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180
160
140
120
100
0.001
0.01
0.1
1
160
140
120
100
80
60
CMRR
+PSRR
œPSRR
40
20
0
1
10
10
100
1k
10k
100k
1M
10M
0
25
50
75 100 125 150
œ75 œ50 œ25
Frequency (Hz)
Temperature (°C)
C004
C001
图 6-13. CMRR and PSRR vs Frequency
图 6-14. CMRR vs Temperature
180
0.001
160
140
120
100
0.01
0.1
1
10
Time (1 s/div)
0
25
50
75 100 125 150
œ75 œ50 œ25
Temperature (°C)
C001
C017
图 6-15. PSRR vs Temperature
图 6-16. 0.1-Hz to 10-Hz Noise
1000
0.01
-80
G = -1, 10k-ꢀ Load
G = -1, 2k-ꢀ Load
G = -1, 600-ꢀ Load
G = +1, 10k-ꢀ Load
G = +1, 2k-ꢀ Load
G = +1, 600-ꢀ Load
100
10
1
0.001
-100
0.0001
-120
20k
1
10
100
1k
10k
100k
20
200
2k
Frequency (Hz)
Frequency (Hz)
C002
C004
图 6-17. Input Voltage Noise Spectral Density vs
图 6-18. THD+N Ratio vs Frequency
Frequency
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0
œ20
0.1
-60
œ40
œ60
0.01
-80
œ80
œ100
œ120
œ140
œ160
œ180
G = -1, 600-ꢀ Load
0.001
-100
-120
G = -1, 2k-ꢀ Load
G = -1, 10k-ꢀ Load
G = +1, 600-ꢀ Load
G = +1, 2k-ꢀ Load
G = +1, 10k-ꢀ Load
0.0001
0.001
0.01
0.1
1
100
1k
10k
100k
Output Amplitude (VRMS
)
Frequency (Hz)
C004
C004
G = +1, f = 1 kHz, VO = 4.5 VPP, RL = 10 kΩ, BW = 90 kHz
图 6-19. THD+N vs Output Amplitude
图 6-20. Spectral Content (With 10-kΩ Load)
0
2.5
œ20
2
1.5
1
œ40
œ60
œ80
œ100
œ120
œ140
œ160
œ180
0.5
0
100
1k
10k
100k
0
0.5
1
1.5
2
2.5
3
Frequency (Hz)
Supply Voltage (V)
C004
C001
G = +1, f = 1 kHz, VO = 4.5 VPP, RL = 2 kΩ, BW = 90 kHz
图 6-22. Quiescent Current vs Supply Voltage
图 6-21. Spectral Content (With 2-kΩ Load)
2.5
180
160
140
120
100
0.001
0.01
0.1
1
VS
=
2.75 V
2
1.5
1
VS
=
1.1 V
0.5
0
10
0
25
50
75
100 125 150
0
25
50
75 100 125 150
œ75 œ50 œ25
œ75 œ50 œ25
Temperature (°C)
Temperature (°C)
C001
C001
图 6-23. Quiescent Current vs Temperature
图 6-24. Open-Loop Gain vs Temperature
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1k
100
90
80
70
60
50
40
30
20
10
G = -1
100
10
1
100m
G = +1
10m
100
1k
10k
100k
1M
10M
100M
10
100
1000
Frequency (Hz)
Capacitive Load (pF)
C003
C004
图 6-25. Open-Loop Output Impedance vs
图 6-26. Small-Signal Overshoot vs Capacitive
Frequency
Load (10-mV Step)
VIN
VOUT
VIN
VOUT
Time (45 ms/div)
Time (200 ns/div)
C017
C017
图 6-27. No Phase Reversal
图 6-28. Positive Overload Recovery
VOUT
VIN
VIN
VOUT
Time (200 ns/div)
Time (2.5 µs/div)
C017
C017
G = +1
图 6-29. Negative Overload Recovery
图 6-30. Small-Signal Step Response (10-mV Step)
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VOUT
VIN
VOUT
VIN
Time (2.5 µs/div)
Time (500 ns/div)
C017
C017
Falling output
G = –1
图 6-32. Large-Signal Step Response (4-V Step)
图 6-31. Small-Signal Step Response (10-mV Step)
VOUT
VIN
0.01% Settling = ±100µV
Time (500 ns/div)
Time (500 ns/div)
C017
C017
Rising output
0.01% settling = ±100 µV
图 6-33. Large-Signal Step Response (4-V Step)
图 6-34. Settling Time (1-V Positive Step)
100
0.01% Settling = ±200µV
ISC, Sink
90
80
70
60
50
40
30
20
10
0
ISC, Source
Time (500 ns/div)
0
25
50
75
100 125 150
œ75 œ50 œ25
Temperature (°C)
C017
C001
0.01% settling = ±200 µV
图 6-35. Settling Time (1-V Negative Step)
图 6-36. Short-Circuit Current vs Temperature
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7
6
160
140
120
100
80
Maximum output voltage without
slew-rate induced distortion.
VS
=
=
2.5V
0.9V
5
4
3
60
VS
2
40
1
20
0
0
100
1k
10k
100k
1M
10M
10M
100M
Frequency (Hz)
1000M
Frequency (Hz)
C001
C004
PRF = –10 dBm
图 6-37. Maximum Output Voltage vs Frequency
图 6-38. EMIRR vs Frequency
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7 Detailed Description
7.1 Overview
The OPAx388 family of zero-drift amplifiers is engineered with the unique combination of a proprietary precision
auto-calibration technique paired with a low-noise, low-ripple, input charge pump. These amplifiers offer ultra-low
input offset voltage and drift and achieve excellent input and output dynamic linearity. The OPAx388 operate
from 2.5 V to 5.5 V, is unity-gain stable, and are designed for a wide range of general-purpose and precision
applications. The integrated, low-noise charge pump allows true rail-to-rail input common-mode operation
without distortion associated with complementary rail-to-rail input topologies (input crossover distortion). The
OPAx388 strengths also include 10-MHz bandwidth, 7-nV/√ Hz noise spectral density, and no 1/f noise, making
the OPAx388 optimal for interfacing with sensor modules and buffering high-fidelity, digital-to-analog converters
(DACs).
7.2 Functional Block Diagram
Low-noise
Charge-pump
GM_FF
CCOMP
CLK
CLK
+IN
OUT
œIN
GM1
GM2
GM3
CCOMP
Ripple Reduction
Technology
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7.3 Feature Description
7.3.1 Operating Voltage
The OPAx388 family of operational amplifiers can be used with single or dual supplies from an operating range
of VS = 2.5 V (±1.25 V) up to 5.5 V (±2.75 V). Supply voltages greater than 7 V can permanently damage the
device (see the Absolute Maximum Ratings table). Key parameters that vary over the supply voltage or
temperature range are shown in the Typical Characteristics section.
7.3.2 Input Voltage and Zero-Crossover Functionality
The OPAx388 input common-mode voltage range extends 0.1 V beyond the supply rails. This amplifier family is
designed to cover the full range without the troublesome transition region found in some other rail-to-rail
amplifiers. Operating a complementary rail-to-rail input amplifier with signals traversing the transition region
results in unwanted non-linear behavior and polluted spectral content. 图 7-1 and 图 7-2 contrast the
performance of a traditional complementary rail-to-rail input stage amplifier with the performance of the zero-
crossover OPA388. Significant harmonic content and distortion is generated during the differential pair transition
(such a transition does not exist in the OPA388). Crossover distortion is eliminated through the use of a single
differential pair coupled with an internal low-noise charge pump. The OPAx388 maintains noise, bandwidth, and
offset performance throughout the input common-mode range, thus reducing printed circuit board (PCB) and bill
of materials (BOM) complexity through the reduction of power-supply rails.
20
15
0
œ20
Complementary Input Stage
OPA388 Zero-Crossover Input Stage
10
œ40
5
œ60
Traditional Rail-to-Rail
Input Stage
0
œ80
œ5
œ100
œ120
œ140
œ10
œ15
œ20
VCM = œ2.85 V
VCM = 2.85 V
OPA388 Zero-Crossover Input Stage
0
1
2
3
10
100
1k
10k
œ3
œ2
œ1
Input Common-mode Voltage (V)
Frequency (Hz)
C003
C004
图 7-1. Input Crossover Distortion Nonlinearity
图 7-2. Input Crossover Distortion Spectral Content
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Typically, input bias current is approximately ±30 pA. Input voltages exceeding the power supplies, however, can
cause excessive current to flow into or out of the input pins. Momentary voltages greater than the power supply
can be tolerated if the input current is limited to 10 mA. This limitation is easily accomplished with an input
resistor, as shown in 图 7-3.
Current-limiting resistor
required if input voltage
exceeds supply rails by
> 0.3V.
+5V
IOVERLOAD
10 mA max
VOUT
VIN
5 kΩ
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图 7-3. Input Current Protection
7.3.3 Input Differential Voltage
The typical input bias current of the OPAx388 during normal operation is approximately 30 pA. In overdriven
conditions, the bias current can increase significantly. The most common cause of an overdriven condition
occurs when the operational amplifier is outside of the linear range of operation. When the output of the
operational amplifier is driven to one of the supply rails, the feedback loop requirements cannot be satisfied and
a differential input voltage develops across the input pins. This differential input voltage results in activation of
parasitic diodes inside the front-end input chopping switches that combine with 10-kΩ electromagnetic
interference (EMI) filter resistors to create the equivalent circuit shown in 图 7-4. Notice that the input bias
current remains within specification in the linear region.
100 W
Clamp
+In
-In
CORE
100 W
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图 7-4. Equivalent Input Circuit
7.3.4 Internal Offset Correction
The OPA388 family of operational amplifiers uses an auto-calibration technique with a time-continuous, 200-kHz
operational amplifier in the signal path. This amplifier is zero-corrected every 5 µs using a proprietary technique.
At power-up, the amplifier requires approximately 1 ms to achieve the specified VOS accuracy. This design has
no aliasing or flicker noise.
7.3.5 EMI Susceptibility and Input Filtering
Operational amplifiers vary in susceptibility to EMI. If conducted EMI enters the operational amplifier, the dc
offset at the amplifier output can shift from its nominal value when EMI is present. This shift is a result of signal
rectification associated with the internal semiconductor junctions. Although all operational amplifier pin functions
can be affected by EMI, the input pins are likely to be the most susceptible. The OPAx388 operational amplifier
family incorporates an internal input low-pass filter that reduces the amplifier response to EMI. Both common-
mode and differential-mode filtering are provided by the input filter. The filter is designed for a cutoff frequency of
approximately 20 MHz (–3 dB), with a rolloff of 20 dB per decade.
7.4 Device Functional Modes
The OPA388 has a single functional mode and is operational when the power-supply voltage is greater than
2.5 V (±1.25 V). The maximum specified power-supply voltage for the OPAx388 is 5.5 V (±2.75 V).
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
The OPAx388 is a unity-gain stable, precision operational amplifier family free from unexpected output and
phase reversal. The use of proprietary zero-drift circuitry gives the benefit of low input offset voltage over time
and temperature, as well as lowering the 1/f noise component. As a result of the high PSRR, these devices work
well in applications that run directly from battery power without regulation. The OPAx388 family is optimized for
full rail-to-rail input, allowing for low-voltage, single-supply operation or split-supply use. These miniature, high-
precision, low-noise amplifiers offer high-impedance inputs that have a common-mode range 100 mV beyond
the supplies without input crossover distortion and a rail-to-rail output that swings within 5 mV of the supplies
under normal test conditions. The OPAx388 series of precision amplifiers is designed for upstream analog signal
chain applications in low or high gains, as well as downstream signal chain functions such as DAC buffering.
8.2 Typical Applications
8.2.1 Bidirectional Current-Sensing
This single-supply, low-side, bidirectional current-sensing solution detects load currents from –1 A to +1 A. The
single-ended output spans from 110 mV to 3.19 V. This design uses the OPAx388 because of its low offset
voltage and rail-to-rail input and output. One of the amplifiers is configured as a difference amplifier and the other
amplifier provides the reference voltage.
图 8-1 shows the solution.
VCC
VREF
VCC
R5
+
U1B
ILOAD
R6
R2
+
R1
+
VBUS
+
œ
VSHUNT
RSHUNT
VOUT
U1A
VCC
R4
R3
œ
RL
图 8-1. Bidirectional Current-Sensing Schematic
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8.2.1.1 Design Requirements
This solution has the following requirements:
• Supply voltage: 3.3 V
• Input: –1 A to 1 A
• Output: 1.65 V ±1.54 V (110 mV to 3.19 V)
8.2.1.2 Detailed Design Procedure
The load current, ILOAD, flows through the shunt resistor (RSHUNT) to develop the shunt voltage, VSHUNT. The
shunt voltage is then amplified by the difference amplifier consisting of U1A and R1 through R4. The gain of the
difference amplifier is set by the ratio of R4 to R3. To minimize errors, set R2 = R4 and R1 = R3. The reference
voltage, VREF, is supplied by buffering a resistor divider using U1B. The transfer function is given by 方程式 1.
VOUT = VSHUNT ´ GainDiff_Amp + VREF
(1)
where
VSHUNT = ILOAD ´ RSHUNT
•
R4
GainDiff_Amp
=
R3
•
R6
R5 + R6
VREF = VCC
´
•
There are two types of errors in this design: offset and gain. Gain errors are introduced by the tolerance of the
shunt resistor and the ratios of R4 to R3 and, similarly, R2 to R1. Offset errors are introduced by the voltage
divider (R5 and R6) and how closely the ratio of R4 / R3 matches R2 / R1. The latter value affects the CMRR of
the difference amplifier, ultimately translating to an offset error.
The value of VSHUNT is the ground potential for the system load because VSHUNT is a low-side measurement.
Therefore, a maximum value must be placed on VSHUNT. In this design, the maximum value for VSHUNT is set to
100 mV. Equation 2 calculates the maximum value of the shunt resistor given a maximum shunt voltage of
100 mV and maximum load current of 1 A.
VSHUNT(Max)
100 mV
= 100 mW
RSHUNT(Max)
=
=
ILOAD(Max)
1 A
(2)
The tolerance of RSHUNT is directly proportional to cost. For this design, a shunt resistor with a tolerance of 0.5%
was selected. If greater accuracy is required, select a 0.1% resistor or better.
The load current is bidirectional; therefore, the shunt voltage range is –100 mV to 100 mV. This voltage is
divided down by R1 and R2 before reaching the operational amplifier, U1A. Make sure that the voltage present at
the noninverting node of U1A is within the common-mode range of the device. Therefore, use an operational
amplifier, such as the OPA388, that has a common-mode range that extends below the negative supply voltage.
Finally, to minimize offset error, note that the OPA388 has a typical offset voltage of merely ±0.25 µV (±5 µV
maximum).
Given a symmetric load current of –1 A to 1 A, the voltage divider resistors (R5 and R6) must be equal. To be
consistent with the shunt resistor, a tolerance of 0.5% was selected. To minimize power consumption,
10-kΩ resistors were used.
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To set the gain of the difference amplifier, the common-mode range and output swing of the OPA388 must be
considered. Equation 3 and Equation 4 depict the typical common-mode range and maximum output swing,
respectively, of the OPA388 given a 3.3-V supply.
–100 mV < VCM < 3.4 V
(3)
(4)
100 mV < VOUT < 3.2 V
The gain of the difference amplifier can now be calculated as shown in Equation 5.
V
OUT_Max - VOUT_Min
3.2 V - 100 mV
100 mW ´ [1 A - (- 1A)]
V
V
= 15.5
=
GainDiff_Amp
=
R
SHUNT ´ (IMAX - IMIN
)
(5)
The resistor value selected for R1 and R3 was 1 kΩ. 15.4 kΩ was selected for R2 and R4 because this number
is the nearest standard value. Therefore, the ideal gain of the difference amplifier is 15.4 V/V.
The gain error of the circuit primarily depends on R1 through R4. As a result of this dependence, 0.1% resistors
were selected. This configuration reduces the likelihood that the design requires a two-point calibration. A simple
one-point calibration, if desired, removes the offset errors introduced by the 0.5% resistors.
8.2.1.3 Application Curve
3.30
1.65
0
-1.0
-0.5
0
0.5
1.0
Input Current (A)
图 8-2. Bidirectional Current-Sensing Circuit Performance: Output Voltage vs Input Current
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8.2.2 Single Operational Amplifier Bridge Amplifier
图 8-3 shows the basic configuration for a bridge amplifier.
VEX
R1
R
R
R
R
+5V
VOUT
VREF
Copyright © 2016, Texas Instruments Incorporated
图 8-3. Single Operational Amplifier Bridge Amplifier Schematic
8.2.3 Precision, Low-Noise, DAC Buffer
The OPA388 can be used for a precision DAC buffer, as shown in 图 8-4, in conjunction with the DAC8830.
The OPA388 provides an ultra-low drift, precision output buffer for the DAC. A wide range of DAC codes can be
used in the linear region because the OPA388 employs zero-crossover technology. A precise reference is
essential for maximum accuracy because the DAC8830 is a 16-bit converter.
VDD VREF
RFB
œ
INV
OPA388
Serial Interface
DAC8830
+
VOUT
DGND
AGND
Copyright © 2016, Texas Instruments Incorporated
图 8-4. Precision DAC Buffer
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OPA388, OPA2388, OPA4388
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8.2.4 Load Cell Measurement
图 8-5 shows the OPA388 in a high-CMRR dual-op amp instrumentation amplifier with a trim resistor and 6-wire
load cell for precision measurement. 图 8-6 illustrates the output voltage as a function of load cell resistance
change, along with the nonlinearity of the system.
R3
25 kꢀ
R4
100 kꢀ
5 V
REF5025
RG
R4
R2
100 kꢀ
25 kꢀ
5 V
5 V
5 V
+SENSE
œ
œ
OPA388
VOUT
OPA388
+
+
R2
GND
GND
10 kꢀ
œSENSE
200 kΩ
Load Cell
G = 5 +
GND
RG
GND
图 8-5. Load Cell Measurement Schematic
2.53
3
2.52
2.51
2.5
2
1
0
2.49
2.48
2.47
-1
-2
-3
RG = 1 kΩ
œ100 œ80 œ60 œ40 œ20
0
20 40 60 80 100
ûR/R (ppm)
C001
图 8-6. Load Cell Measurement Output
9 Power Supply Recommendations
The OPAx388 family of devices is specified for operation from 2.5 V to 5.5 V (±1.25 V to ±2.75 V). Parameters
that can exhibit significant variance with regard to operating voltage are presented in the Typical Characteristics
section.
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10 Layout
10.1 Layout Guidelines
Paying attention to good layout practice is always recommended. Keep traces short and, when possible, use a
printed-circuit board (PCB) ground plane with surface-mount components placed as close to the device pins as
possible. Place a 0.1-µF capacitor closely across the supply pins. These guidelines must be applied throughout
the analog circuit to improve performance and provide benefits such as reducing the electromagnetic
interference (EMI) susceptibility.
For lowest offset voltage and precision performance, circuit layout and mechanical conditions must be optimized.
Avoid temperature gradients that create thermoelectric (Seebeck) effects in the thermocouple junctions formed
from connecting dissimilar conductors. These thermally-generated potentials can be made to cancel by assuring
they are equal on both input terminals. Other layout and design considerations include:
• Use low thermoelectric-coefficient conditions (avoid dissimilar metals).
• Thermally isolate components from power supplies or other heat sources.
• Shield operational amplifier and input circuitry from air currents, such as cooling fans.
Following these guidelines reduces the likelihood of junctions being at different temperatures, which can cause
thermoelectric voltage drift of 0.1 µV/°C or higher, depending on materials used.
10.2 Layout Example
VIN
+
VOUT
RG
RF
图 10-1. Schematic Representation
Place components close
to device and to each
other to reduce parasitic
errors
Run the input traces
as far away from
the supply lines
as possible
RF
VS+
N/C
N/C
RG
GND
œIN
+IN
Vœ
V+
OUTPUT
N/C
VIN
GND
GND
VOUT
Ground (GND) plane on another layer
Use low-ESR,
ceramic bypass
capacitors
图 10-2. OPA388 Layout Example
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 TINA-TI™ (Free Software Download)
TINA-TI™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI
™ is a free, fully-functional version of the TINA™ software, preloaded with a library of macromodels in addition to
a range of both passive and active models. TINA-TI™ provides all the conventional dc, transient, and frequency
domain analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI™ offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
Note
These files require that either the TINA software (from DesignSoft™) or TINA-TI™ software be
installed. Download the free TINA-TI™ software from the TINA-TI™ folder.
11.1.1.2 TI Precision Designs
The OPAx388 family is featured on TI Precision Designs, available online at www.ti.com/ww/en/analog/precision-
designs/. TI Precision Designs are analog solutions created by TI’s precision analog applications experts and
offer the theory of operation, component selection, simulation, complete PCB schematic and layout, bill of
materials, and measured performance of many useful circuits.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Circuit board layout techniques
• Texas Instruments, DAC883x 16-Bit, Ultra-Low Power, Voltage-Output Digital-to-Analog Converters data
sheet
11.3 Related Links
表 11-1 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 11-1. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
SAMPLE & BUY
OPA388
OPA2388
OPA4388
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
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11.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.5 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.6 Trademarks
TINA-TI™ are trademarks of TI.
TINA™ and DesignSoft™ are trademarks of DesignSoft, Inc.
TI E2E™ is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.8 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2020 Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
www.ti.com
4-Jul-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA2388ID
OPA2388IDGKR
OPA2388IDGKT
OPA2388IDR
OPA388ID
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
VSSOP
VSSOP
SOIC
D
DGK
DGK
D
8
8
75
RoHS & Green
SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
OP2388
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
2500 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
75 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
50 RoHS & Green
2500 RoHS & Green
90 RoHS & Green
2000 RoHS & Green
NIPDAUAG | SN
NIPDAUAG | SN
SN
1D36
8
1D36
8
OP2388
OPA388
14KV
SOIC
D
8
NIPDAU
OPA388IDBVR
OPA388IDBVT
OPA388IDGKR
OPA388IDGKT
OPA388IDR
SOT-23
SOT-23
VSSOP
VSSOP
SOIC
DBV
DBV
DGK
DGK
D
5
NIPDAU
5
NIPDAU
14KV
8
NIPDAUAG
NIPDAUAG
NIPDAU
14LV
8
14LV
8
OPA388
OPA4388
OPA4388
OPA4388
OPA4388
OPA4388ID
SOIC
D
14
14
14
14
NIPDAU
OPA4388IDR
OPA4388IPW
OPA4388IPWR
SOIC
D
NIPDAU
TSSOP
TSSOP
PW
PW
NIPDAU
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
4-Jul-2023
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF OPA2388, OPA388 :
Automotive : OPA2388-Q1, OPA388-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Jul-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA2388IDGKR
OPA2388IDGKR
OPA2388IDGKT
OPA2388IDGKT
OPA2388IDR
VSSOP
VSSOP
VSSOP
VSSOP
SOIC
DGK
DGK
DGK
DGK
D
8
8
2500
2500
250
330.0
330.0
330.0
330.0
330.0
180.0
180.0
330.0
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
12.8
8.4
5.3
5.3
5.3
5.3
6.4
3.23
3.23
5.3
5.3
6.4
6.5
6.9
3.4
3.4
3.4
3.4
5.2
3.17
3.17
3.4
3.4
5.2
9.0
5.6
1.4
1.4
1.4
1.4
2.1
1.37
1.37
1.4
1.4
2.1
2.1
1.6
8.0
8.0
8.0
8.0
8.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
8.0
Q1
Q1
Q1
Q1
Q1
Q3
Q3
Q1
Q1
Q1
Q1
Q1
8
8
250
8
2500
3000
250
OPA388IDBVR
OPA388IDBVT
OPA388IDGKR
OPA388IDGKT
OPA388IDR
SOT-23
SOT-23
VSSOP
VSSOP
SOIC
DBV
DBV
DGK
DGK
D
5
5
8.4
8.0
8
2500
250
12.4
12.4
12.4
16.4
12.4
12.0
12.0
12.0
16.0
12.0
8
8
2500
2500
2000
OPA4388IDR
SOIC
D
14
14
OPA4388IPWR
TSSOP
PW
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Jul-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA2388IDGKR
OPA2388IDGKR
OPA2388IDGKT
OPA2388IDGKT
OPA2388IDR
VSSOP
VSSOP
VSSOP
VSSOP
SOIC
DGK
DGK
DGK
DGK
D
8
8
2500
2500
250
366.0
366.0
366.0
366.0
366.0
213.0
213.0
366.0
366.0
356.0
356.0
356.0
364.0
364.0
364.0
364.0
364.0
191.0
191.0
364.0
364.0
356.0
356.0
356.0
50.0
50.0
50.0
50.0
50.0
35.0
35.0
50.0
50.0
35.0
35.0
35.0
8
8
250
8
2500
3000
250
OPA388IDBVR
OPA388IDBVT
OPA388IDGKR
OPA388IDGKT
OPA388IDR
SOT-23
SOT-23
VSSOP
VSSOP
SOIC
DBV
DBV
DGK
DGK
D
5
5
8
2500
250
8
8
2500
2500
2000
OPA4388IDR
SOIC
D
14
14
OPA4388IPWR
TSSOP
PW
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Jul-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
OPA2388ID
OPA388ID
D
D
SOIC
SOIC
8
8
75
75
50
90
517
506.6
506.6
530
7.87
8
635
4.25
4.32
4.32
3.5
3940
3940
3600
OPA4388ID
OPA4388IPW
D
SOIC
14
14
8
PW
TSSOP
10.2
Pack Materials-Page 3
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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