OPA4171-Q1 [TI]
汽车级、四路、36V、3MHz、低功耗运算放大器;
| 型号： | OPA4171-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车级、四路、36V、3MHz、低功耗运算放大器 放大器 运算放大器 |
| 文件： | 总41页 (文件大小：1778K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OPA171-Q1, OPA2171-Q1, OPA4171-Q1
SBOS556D – JUNE 2011 – REVISED AUGUST 2020
OPAx171-Q1 36-V, Single-Supply, General-Purpose
Operational Amplifier
1 Features
2 Applications
•
•
Qualified for automotive applications
AEC-Q100 test guidance with the following results:
– Temperature grade 1:
–40°C to +125°C ambient operating
temperature
– Device HBM ESD classification level:
•
•
•
•
•
•
•
•
•
Tracking amplifier in power modules
Merchant power supplies
Transducer amplifiers
Bridge amplifiers
Temperature measurements
Strain gauge amplifiers
Precision integrators
Battery-powered instruments
Test equipment
•
•
Level 3A for OPA171-Q1
Level 2 for OPA4171-Q1
– Device CDM ESD classification level
•
•
•
Level C4A for OPA171-Q1 TLV171-Q1
Level C6 for OPA2171-Q1
Level C6 for OPA4171-Q1
3 Description
The OPA171-Q1 family of devices is a 36-V, single-
supply, low-noise operational amplifier (op amp) with
the ability to operate on supplies ranging from 2.7 V
(±1.35 V) to 36 V (±18 V). This series is available in
multiple packages and offers low offset, drift, and low
quiescent current. The single, dual, and quad versions
all have identical specifications for maximum design
flexibility.
•
Supply range:
– Single-supply: 2.7 V to 36 V
– Dual-supply ±1.35 V to ±18 V
Low noise: 14 nV/√Hz at 1 kHz
Low offset drift: ±0.3 µV/°C (typical)
Input range includes negative supply
Input range operates to positive supply with
reduced performance
•
•
•
•
Unlike most op amps, which are specified at only one
supply voltage, the OPAx171-Q1 family of devices is
specified from 2.7 V to 36 V. Input signals beyond the
supply rails do not cause phase reversal.
•
•
•
•
•
•
Rail-to-rail output
Gain bandwidth: 3 MHz
Low quiescent current: 475 µA per amplifier
High Common-mode rejection: 120 dB (typical)
Low input bias current: 10 pA
Industry-Standard Package:
– 5-Pin Small-Outline Transistor SOT-23 (DBV)
Package
The OPAx171-Q1 family of devices is stable with
capacitive loads up to 300 pF. The input can operate
100 mV below the negative rail and within 2 V of the
top rail during normal operation. The device can
operate with full rail-to-rail input 100 mV beyond the
top rail, but with reduced performance within 2 V of
the top rail.
1000
10 Typical Units Shown
800
The OPAx171-Q1 op amp family is specified from –
40°C to +125°C.
600
400
200
0
Device Information
PART NUMBER
PACKAGE(1)
BODY SIZE (NOM)
2.90 mm × 1.60 mm
4.90 mm × 3.91 mm
3.00 mm × 3.00 mm
8.65 mm × 3.91 mm
5.00 mm × 4.40 mm
-200
-400
-600
OPA171-Q1
SOT-23 (5)
SOIC (8)
OPA2171-Q1
OPA4171-Q1
-800
VCM = -18.1 V
VSSOP (8)
SOIC (14)
TSSOP (14)
-1000
-20
-15
-10
-5
0
5
10
15
20
VCM (V)
Offset Voltage vs Common-Mode Voltage:
VSUPPLY = ±18 V
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA171-Q1, OPA2171-Q1, OPA4171-Q1
SBOS556D – JUNE 2011 – REVISED AUGUST 2020
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
Pin Functions : OPA171-Q1 and OPA2171-Q1.................3
Pin Functions : OPA4171-Q1............................................4
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information — OPA171-Q1 and
OPA2171-Q1.................................................................6
6.5 Thermal Information — OPA4171-Q1.........................6
6.6 Electrical Characteristics.............................................7
6.7 Typical Characteristics................................................9
7 Detailed Description......................................................16
7.1 Overview...................................................................16
7.2 Functional Block Diagram.........................................16
7.3 Feature Description...................................................16
7.4 Device Functional Modes..........................................18
8 Application and Implementation..................................19
8.1 Application Information............................................. 19
8.2 Typical Application.................................................... 21
9 Power Supply Recommendations................................23
10 Layout...........................................................................24
10.1 Layout Guidelines................................................... 24
10.2 Layout Example...................................................... 24
11 Device and Documentation Support..........................25
11.1 Documentation Support.......................................... 25
11.2 Related Links.......................................................... 25
11.3 Receiving Notification of Documentation Updates..25
11.4 Support Resources................................................. 25
11.5 Trademarks............................................................. 25
11.6 Electrostatic Discharge Caution..............................25
11.7 Glossary..................................................................25
12 Mechanical, Packaging, and Orderable
Information.................................................................... 25
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (December 2015) to Revision D (August 2020)
Page
•
•
•
Updated the numbering format for tables, figures, and cross-references throughout the document..................1
Changed OPA2171-Q1 V+ pinout table value to correctly reflect pinout image................................................. 3
Rewrote Electrical Overstress section to match with TLV171 commercial data sheet..................................... 19
Changes from Revision B (December 2014) to Revision C (December 2015)
Page
•
•
•
Changed the ESD classification levels for HBM and CDM in the Features list ................................................. 1
Added the 8-pin VSSOP (DGK) package option for the OPA2171-Q1 device .................................................. 1
Clarified the ESD values for each device in the ESD Ratings table .................................................................. 5
Changes from Revision A (September 2012) to Revision B (December 2014)
Page
•
Added the Handling Ratings table, Feature Description section, Device Functional Modes section, Application
and Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................. 1
Added the OPA2171-Q1 and OPA4171-Q1 devices to the data sheet ..............................................................1
•
Changes from Revision * (June, 2011) to Revision A (September, 2012)
Page
•
Added second bullet to Features: AEC-Q100 Test Guidance With the Following Results: –Device
Temperature Grade1: -40°C to 125°C Ambient Operating Temperature Range –Device HBM ESD
Classification Level H2 –Device CDM ESD Classification Level C3A................................................................1
Added classification levels to ESD ratings in Absolute Maximum Ratings table................................................ 5
Added row to Absolute Maximum Ratings table: Latch-up per JESD78D with Class 1 value............................5
•
•
Copyright © 2020 Texas Instruments Incorporated
2
Submit Document Feedback
Product Folder Links: OPA171-Q1 OPA2171-Q1 OPA4171-Q1
OPA171-Q1, OPA2171-Q1, OPA4171-Q1
SBOS556D – JUNE 2011 – REVISED AUGUST 2020
www.ti.com
5 Pin Configuration and Functions
OUT A
–IN A
+IN A
V–
1
2
3
4
8
7
6
5
V+
V+
OUT
V-
1
2
3
5
4
OUT B
–IN B
+IN B
-IN
+IN
Figure 5-1. OPA171-Q1 DBV Package
5-Pin SOT-23
Figure 5-2. OPA2171-Q1 D or DGK Package
8-Pin SOIC and VSSOP
Top View
Top View
Pin Functions : OPA171-Q1 and OPA2171-Q1
PIN
OPA2171-Q1
SOIC AND
VSSOP
I/O
DESCRIPTION
OPA171-Q1
SOT-23
NAME
+IN
3
—
—
4
—
3
I
I
Noninverting input
+IN A
+IN B
–IN
Noninverting input, channel A
Noninverting input, channel B
Inverting input
5
I
—
2
I
–IN A
–IN B
OUT
OUT A
OUT B
V+
—
—
1
I
Inverting input, channel A
Inverting input, channel B
Output
6
I
—
1
O
O
O
—
—
—
—
5
Output, channel A
7
Output, channel B
8
Positive (highest) power supply
Negative (lowest) power supply
V–
2
4
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
3
Product Folder Links: OPA171-Q1 OPA2171-Q1 OPA4171-Q1
OPA171-Q1, OPA2171-Q1, OPA4171-Q1
SBOS556D – JUNE 2011 – REVISED AUGUST 2020
www.ti.com
OUT A
-IN A
+IN A
V+
1
2
3
4
5
6
7
14 OUT D
13 -IN D
12 +IN D
11 V-
+IN B
-IN B
OUT B
10 +IN C
9
8
-IN C
OUT C
Figure 5-3. OPA4171-Q1 D and PW Packages
14-Pin SOIC and TSSOP
Top View
Pin Functions : OPA4171-Q1
PIN
I/O
DESCRIPTION
NAME
+IN A
+IN B
+IN C
+IN D
–IN A
–IN B
–IN C
–IN D
OUT A
OUT B
OUT C
OUT D
V+
NO.
3
I
I
Noninverting input, channel A
Noninverting input, channel B
Noninverting input, channel C
Noninverting input, channel D
Inverting input, channel A
Inverting input, channel B
Inverting input, channel C
Inverting input, channel D
Output, channel A
5
10
12
2
I
I
I
6
I
9
I
13
1
I
O
O
O
O
—
—
7
Output, channel B
8
Output, channel C
14
4
Output, channel D
Positive (highest) power supply
Negative (lowest) power supply
V–
11
Copyright © 2020 Texas Instruments Incorporated
4
Submit Document Feedback
Product Folder Links: OPA171-Q1 OPA2171-Q1 OPA4171-Q1
OPA171-Q1, OPA2171-Q1, OPA4171-Q1
SBOS556D – JUNE 2011 – REVISED AUGUST 2020
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
40
UNIT
V
Supply voltage, VS
Voltage
Signal input terminals
Current
(V–) – 0.5
(V+) + 0.5
±10
V
mA
Output short circuit(2)
Continuous
Junction temperature, TJ
Latch-up per JESD78D
Storage temperature, Tstg
150
150
°C
°C
Class 1
–65
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2) Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
UNIT
OPA171-Q1
Human body model (HBM), per AEC Q100-002(1)
Charged device model (CDM), per AEC Q100-011
±4000
±500
V(ESD)
Electrostatic discharge
V
OPA2171-Q1
Human body model (HBM), per AEC Q100-002(1)
Charged device model (CDM), per AEC Q100-011
±4000
±1000
V(ESD)
Electrostatic discharge
V
V
OPA4171-Q1
Human body model (HBM), per AEC Q100-002(1)
Charged device model (CDM), per AEC Q100-011
±2000
±1000
V(ESD)
Electrostatic discharge
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5 (±2.25)
–40
NOM
MAX
36 (±18)
125
UNIT
Supply voltage (V+ – V–)
V
Specified operating temperature
°C
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
5
Product Folder Links: OPA171-Q1 OPA2171-Q1 OPA4171-Q1
OPA171-Q1, OPA2171-Q1, OPA4171-Q1
SBOS556D – JUNE 2011 – REVISED AUGUST 2020
www.ti.com
6.4 Thermal Information — OPA171-Q1 and OPA2171-Q1
OPA171-Q1
OPA2171-Q1
THERMAL METRIC(1)
DBV (SOT-23)
5 PINS
277.3
D (SOIC)
DGK (VSSOP)
8 PINS
186.5
UNIT
8 PINS
116.1
69.8
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
193.3
78
121.2
56.6
107.8
Junction-to-top characterization parameter
Junction-to-board characterization parameter
51.8
22.5
15.6
ψJB
109.5
56.1
106.2
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Thermal Information — OPA4171-Q1
OPA4171-Q1
THERMAL METRIC(1)
D (SOIC)
14 PINS
93.2
PW (TSSOP)
14 PINS
106.9
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
51.8
24.4
49.4
59.3
Junction-to-top characterization parameter
Junction-to-board characterization parameter
13.5
0.6
ψJB
42.2
54.3
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Copyright © 2020 Texas Instruments Incorporated
6
Submit Document Feedback
Product Folder Links: OPA171-Q1 OPA2171-Q1 OPA4171-Q1
OPA171-Q1, OPA2171-Q1, OPA4171-Q1
SBOS556D – JUNE 2011 – REVISED AUGUST 2020
www.ti.com
6.6 Electrical Characteristics
at TA = 25°C, VS = 2.7 V to 36 V, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2 (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
0.25
0.3
±1.8
±2
mV
mV
Input offset voltage over temperature TA = –40°C to 125°C
Input offset voltage drift
TA = –40°C to 125°C
(over temperature)
dVOS/dT
PSRR
0.3
±2 (2)
±3
µV/°C
Input offset voltage over temperature
VS = 4.5 V to 36 V
120
5
µV/V
µV/V
vs power supply
Channel separation, DC
INPUT BIAS CURRENT
IB
Input bias current
±8
±4
±15
pA
nA
pA
nA
Input bias current over temperature
Input offset current
±3.5
IOS
Input offset current over temperature
±3.5
NOISE
Input voltage noise
f = 0.1 Hz to 10 Hz
f = 100 Hz
3
25
14
µVPP
nV/√ Hz
nV/√ Hz
en
Input voltage noise density
f = 1 kHz
INPUT VOLTAGE
VCM
Common-mode voltage range(1)
(V–) – 0.1
90
(V+) – 2
V
VS = ±2.25 V
(V–) – 0.1 V < VCM < (V+) – 2 V
104
120
dB
Common-mode rejection ratio (over
temperature)
CMRR
VS = ±18 V
(V–) – 0.1 V < VCM < (V+) – 2 V
104
dB
INPUT IMPEDANCE
Differential
100 || 3
6 || 3
MΩ || pF
Common-mode
OPEN-LOOP GAIN
Open-loop voltage gain (over
1012Ω || pF
VS = 4.5 V to 36 V
(V–) + 0.35 V < VO < (V+) – 0.35 V
AOL
110
130
dB
temperature)
FREQUENCY RESPONSE
GBP
SR
Gain bandwidth product
3
MHz
V/µs
Slew rate
G = 1
1.5
To 0.1%, VS = ±18 V
G = 1, 10-V step
6
µs
tS
Settling time
To 0.01% (12 bit), VS = ±18 V
G = 1, 10-V step
10
2
µs
µs
Overload recovery time
V±IN × Gain > VS
G = 1, f = 1 kHz
VO = 3 VRMS
THD+N Total harmonic distortion + noise
OUTPUT
0.0002%
Voltage output swing from rail (over
temperature)
RL = 10 kΩ
AOL ≥ 110 dB
VO
(V–) + 0.35
(V+) – 0.35
V
Sourcing
Sinking
25
ISC
Short-circuit current
mA
–37
CLOAD
RO
Capacitive load drive
See Section 6.7
pF
Ω
Open-loop output resistance
f = 1 MHz, IO = 0 A
150
POWER SUPPLY
VS
Specified voltage range
TA = –40°C to 125°C
4.5
36
V
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
7
Product Folder Links: OPA171-Q1 OPA2171-Q1 OPA4171-Q1
OPA171-Q1, OPA2171-Q1, OPA4171-Q1
SBOS556D – JUNE 2011 – REVISED AUGUST 2020
www.ti.com
at TA = 25°C, VS = 2.7 V to 36 V, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2 (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IQ
Quiescent current per amplifier
IO = 0 A, TA = –40°C to 125°C
475
595
µA
(1) The input range can be extended beyond (V+) – 2 V up to V+ at reduced performance. See Section 6.7 and Section 7 for additional
information.
(2) Not production tested.
Copyright © 2020 Texas Instruments Incorporated
8
Submit Document Feedback
Product Folder Links: OPA171-Q1 OPA2171-Q1 OPA4171-Q1
OPA171-Q1, OPA2171-Q1, OPA4171-Q1
SBOS556D – JUNE 2011 – REVISED AUGUST 2020
www.ti.com
6.7 Typical Characteristics
VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
Table 6-1. Characteristic Performance Measurements
DESCRIPTION
Offset Voltage Production Distribution
Offset Voltage Drift Distribution
FIGURE
Figure 6-1
Figure 6-2
Offset Voltage vs Temperature
Figure 6-3
Offset Voltage vs Common-Mode Voltage
Offset Voltage vs Common-Mode Voltage (Upper Stage)
Offset Voltage vs Power Supply
Figure 6-4
Figure 6-5
Figure 6-6
IB and IOS vs Common-Mode Voltage
Input Bias Current vs Temperature
Output Voltage Swing vs Output Current (Maximum Supply)
CMRR and PSRR vs Frequency (Referred-to Input)
CMRR vs Temperature
Figure 6-7
Figure 6-8
Figure 6-9
Figure 6-10
Figure 6-11
Figure 6-12
Figure 6-13
Figure 6-14
Figure 6-15
Figure 6-16
Figure 6-17
Figure 6-18
Figure 6-19
Figure 6-20
Figure 6-21
Figure 6-22
Figure 6-23, Figure 6-24
Figure 6-25
Figure 6-26
Figure 6-27
Figure 6-28, Figure 6-29
Figure 6-30, Figure 6-31
Figure 6-32
Figure 6-33
Figure 6-34
Figure 6-35
Figure 6-36
PSRR vs Temperature
0.1Hz to 10Hz Noise
Input Voltage Noise Spectral Density vs Frequency
THD+N Ratio vs Frequency
THD+N vs Output Amplitude
Quiescent Current vs Temperature
Quiescent Current vs Supply Voltage
Open-Loop Gain and Phase vs Frequency
Closed-Loop Gain vs Frequency
Open-Loop Gain vs Temperature
Open-Loop Output Impedance vs Frequency
Small-Signal Overshoot vs Capacitive Load (100-mV Output Step)
No Phase Reversal
Positive Overload Recovery
Negative Overload Recovery
Small-Signal Step Response (100 mV)
Large-Signal Step Response
Large-Signal Settling Time (10-V Positive Step)
Large-Signal Settling Time (10-V Negative Step)
Short-Circuit Current vs Temperature
Maximum Output Voltage vs Frequency
Channel Separation vs Frequency
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
9
Product Folder Links: OPA171-Q1 OPA2171-Q1 OPA4171-Q1
OPA171-Q1, OPA2171-Q1, OPA4171-Q1
SBOS556D – JUNE 2011 – REVISED AUGUST 2020
www.ti.com
6.7.1 Typical Characteristics
16
25
20
15
10
5
Distribution Taken From 3500 Amplifiers
Distribution Taken From 110 Amplifiers
14
12
10
8
6
4
2
0
0
Offset Voltage Drift (mV/°C)
Offset Voltage (mV)
Figure 6-2. Offset Voltage Drift Distribution
Figure 6-1. Offset Voltage Production Distribution
1000
600
10 Typical Units Shown
5 Typical Units Shown
800
400
200
600
400
200
0
0
-200
-400
-600
-800
-200
-400
-600
-800
VCM = -18.1 V
-1000
-20
-15
-10
-5
0
5
10
15
20
-75 -50 -25
0
25
50
75
100 125 150
VCM (V)
Temperature (°C)
Figure 6-4. Offset Voltage vs Common-Mode
Voltage: VSUPPLY (V) = ±18 V
Figure 6-3. Offset Voltage vs Temperature
10000
350
10 Typical Units Shown
VSUPPLY = 2ꢀ25 V ꢁt 18 V
10 Typical Uniꢁs Shtwn
8000
6000
4000
2000
0
250
150
50
-50
-2000
Normal
Operation
-4000
-6000
-150
-250
-350
VCM = 18.1 V
-8000
-10000
15.5
16
16.5
17
17.5
18
18.5
0
2
4
6
8
10
12
14
16
18
20
VCM (V)
VSUPPLY (V)
Figure 6-5. Offset Voltage vs Common-Mode
Voltage: VSUPPLY (V) = ±18 V
(Upper Stage)
Figure 6-6. Offset Voltage vs Power Supply
Copyright © 2020 Texas Instruments Incorporated
10
Submit Document Feedback
Product Folder Links: OPA171-Q1 OPA2171-Q1 OPA4171-Q1
OPA171-Q1, OPA2171-Q1, OPA4171-Q1
SBOS556D – JUNE 2011 – REVISED AUGUST 2020
www.ti.com
10000
1000
100
10
15
14
13
12
11
10
9
IB+
IB-
-IB
+IB
IB
IOS
-IOS
8
7
6
IOS
5
4
1
3
VCM = -18.1V
VCM = 16V
2
1
0
0
-40 -25
0
25
50
75
100
125
-20
-18
-12
-6
0
6
12
18
20
Temperature (°C)
VCM (V)
Figure 6-8. Input Bias Current vs Temperature
Figure 6-7. IB and IOSvs Common-Mode Voltage
18
17
16
140
120
100
80
15
14.5
-14.5
60
-15
-16
-17
-18
-40°C
+25°C
+85°C
+125°C
40
+PSRR
20
0
-PSRR
CMRR
1
10
100
1k
10k
100k
1M
10M
0
2
4
6
8
10
12
14
16
Frequency (Hz)
Output Current (mA)
Figure 6-10. CMRR and PSRR vs Frequency
(Referred-to Input)
Figure 6-9. Output Voltage Swing vs Output
Current (Maximum Supply)
30
20
10
0
3
2
1
0
-10
-1
VS = 2.7V
-20
-2
-3
VS = 2.7V to 36V
VS = 4V to 36V
VS = 4V
VS = 36V
-30
-75 -50 -25
0
25
50
75
100 125 150
-75 -50 -25
0
25
50
75
100 125 150
Temperature (°C)
Temperature (°C)
Figure 6-11. CMRR vs Temperature
Figure 6-12. PSRR vs Temperature
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
11
Product Folder Links: OPA171-Q1 OPA2171-Q1 OPA4171-Q1
OPA171-Q1, OPA2171-Q1, OPA4171-Q1
SBOS556D – JUNE 2011 – REVISED AUGUST 2020
www.ti.com
1000
100
10
1
1
10
100
1k
10k
100k
1M
Frequency (Hz)
Time (1s/div)
Figure 6-14. Input Voltage Noise Spectral Density
vs Frequency
Figure 6-13. 0.1- to 10-Hz Noise
0.1
-80
0.01
-80
VOUT = 3VRMS
BW = 80kHz
BW = 80kHz
0.01
-100
-120
-140
-100
-120
-140
0.001
0.001
0.0001
0.0001
0.00001
G = +1, RL = 10kW
G = -1, RL = 2kW
G = +1, RL = 10kW
G = -1, RL = 2kW
0.00001
0.01
0.1
1
10 20
10
100
1k
10k 20k
Output Amplitude (VRMS
)
Frequency (Hz)
Figure 6-15. THD+N Ratio vs Frequency
Figure 6-16. THD+N vs Output Amplitude
0.6
0.65
0.55
0.5
0.6
0.55
0.5
0.45
0.4
0.45
0.4
0.35
0.3
Specified Supply-Voltage Range
0.25
0.35
-75 -50 -25
0
25
50
75
100 125 150
0
4
8
12
16
20
24
28
32
36
Temperature (°C)
Supply Voltage (V)
Figure 6-18. Quiescent Current vs Supply Voltage
Figure 6-17. Quiescent Current vs Temperature
Copyright © 2020 Texas Instruments Incorporated
12
Submit Document Feedback
Product Folder Links: OPA171-Q1 OPA2171-Q1 OPA4171-Q1
OPA171-Q1, OPA2171-Q1, OPA4171-Q1
SBOS556D – JUNE 2011 – REVISED AUGUST 2020
www.ti.com
180
180
135
90
25
20
15
10
5
Gain
135
90
45
0
Phase
45
0
-5
0
-10
-15
-20
G = 10
G = 1
-45
-45
G = -1
1
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
10k
100k
1M
10M
100M
Frequency (Hz)
Figure 6-19. Open-Loop Gain and Phase vs
Frequency
Figure 6-20. Closed-Loop Gain vs Frequency
3
1M
100k
10k
1k
5 Typical Units Shown
VS = 2.7 V
VS = 4 V
VS = 36 V
2.5
2
1.5
1
100
10
0.5
0
1
1m
-40 -25
0
25
50
75
100
125
1
10
100
1k
10k
100k
1M
10M
Temperature (°C)
Frequency (Hz)
Figure 6-21. Open-Loop Gain vs Temperature
Figure 6-22. Open-Loop Output Impedance vs
Frequency
50
45
40
35
30
25
20
50
ROUT = 0 W
45
ROUT = 25 W
40
ROUT = 50 W
35
30
25
20
G = 1
18 V
RF = 10 kW
18 V
RI = 10 kW
G = -1
ROUT = 0 Ω
15
15
10
5
ROUT
TLV171-Q1
ROUT = 25 Ω
ROUT = 50 Ω
ROUT
10
RL
CL
-18 V
TLV171-Q1
-18 V
CL
5
0
0
0
100 200 300 400 500 600 700 800 900 1000
Capacitive Load (pF)
0
100 200 300 400 500 600 700 800 900 1000
Capacitive Load (pF)
Figure 6-23. Small-Signal Overshoot vs Capacitive Figure 6-24. Small-Signal Overshoot vs Capacitive
Load
Load
(100-mV Output Step)
(100-mV Output Step)
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
13
Product Folder Links: OPA171-Q1 OPA2171-Q1 OPA4171-Q1
OPA171-Q1, OPA2171-Q1, OPA4171-Q1
SBOS556D – JUNE 2011 – REVISED AUGUST 2020
www.ti.com
18 V
VOUT
TLV171-Q1
Output
-18 V
37 VPP
Sine Wave
18ꢀ5 V)
(
VIN
20kW
+18V
2kW
VOUT
OPA171
Output
VIN
-18V
G = -10
Time (5ms/div)
Time (100ms/div)
Figure 6-25. No Phase Reversal
Figure 6-26. Positive Overload Recovery
RL = 10kW
G = +1
+18V
OPA171
-18V
CL = 100pF
RL
CL
VIN
20kW
+18V
2kW
VOUT
OPA171
VIN
VOUT
-18V
G = -10
Time (5ms/div)
Time (1ms/div)
Figure 6-27. Negative Overload Recovery
Figure 6-28. Small-Signal Step Response (100 mV)
CL = 100pF
RI = 2kW RF = 2kW
+18V
OPA171
CL
-18V
G = -1
Time (5ms/div)
Time (20ms/div)
G = 1
RL = 10 kΩ
CL = 100 pF
Figure 6-29. Small-Signal Step Response (100 mV)
Figure 6-30. Large-Signal Step Response
Copyright © 2020 Texas Instruments Incorporated
14
Submit Document Feedback
Product Folder Links: OPA171-Q1 OPA2171-Q1 OPA4171-Q1
OPA171-Q1, OPA2171-Q1, OPA4171-Q1
SBOS556D – JUNE 2011 – REVISED AUGUST 2020
www.ti.com
10
8
6
4
12-Bit Settling
2
0
-2
-4
-6
-8
-10
( 1ꢀ2ꢁSB ꢂ 0.024%)
Time (4ms/div)
0
4
8
12
16
20
24
28
32
36
Time (ms)
G = –1
RL = 10 kΩ
CL = 100 pF
G = –1
Figure 6-31. Large-Signal Step Response
Figure 6-32. Large-Signal Settling Time (10-V
Positive Step)
10
8
50
45
40
6
4
35
30
25
20
15
10
5
ISC, Sink
12-Bit Settling
2
0
-2
ISC, Source
( 1ꢀ2ꢁSB ꢂ 0.024%)
-4
-6
-8
-10
0
0
4
8
12
16
20
24
28
32
36
-40
-25
0
25
50
75
100
125
Time (ms)
Temperature (°C)
Figure 6-34. Short-Circuit Current vs Temperature
G = –1
Figure 6-33. Large-Signal Settling Time (10-V
Negative Step)
15
-60
-70
VS
=
15 V
12.5
10
7.5
5
Maximum output voltage without
slew-rate induced distortion.
-80
-90
VS
= 5 V
-100
-110
-120
2.5
0
10
100
1k
10k
100k
10k
100k
Frequency (Hz)
1M
10M
Frequency (Hz)
Figure 6-35. Maximum Output Voltage vs
Frequency
Figure 6-36. Channel Separation vs Frequency
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
15
Product Folder Links: OPA171-Q1 OPA2171-Q1 OPA4171-Q1
OPA171-Q1, OPA2171-Q1, OPA4171-Q1
SBOS556D – JUNE 2011 – REVISED AUGUST 2020
www.ti.com
7 Detailed Description
7.1 Overview
The OPAx171-Q1 family of operational amplifiers provides high overall performance, making them ideal for many
general-purpose applications. The excellent offset drift of only 1.5 μV/°C (maximum) provides excellent stability
over the entire temperature range. In addition, the device offers very good overall performance with high CMRR,
PSRR, AOL, and superior THD.
7.2 Functional Block Diagram
OPA171-Q1
+
PCH
FF Stage
œ
Ca
Cb
+
+IN
+
+
PCH
Input Stage
2nd Stage
OUT
Output
Stage
œ
œIN
œ
œ
+
NCH
Input Stage
œ
7.3 Feature Description
7.3.1 Operating Characteristics
The OPAx171-Q1 family of devices is specified for operation from 2.7 V to 36 V (±1.35 V to ±18 V). Many of the
specifications apply from –40°C to +125°C. Parameters that can exhibit significant variance with regard to
operating voltage or temperature are shown in Section 6.7.
7.3.2 Phase-Reversal Protection
The OPAx171-Q1 family of devices has an internal phase-reversal protection. Many op amps exhibit a phase
reversal when the input is driven beyond the linear common-mode range. This condition is most often
encountered in noninverting circuits when the input is driven beyond the specified common-mode voltage range,
causing the output to reverse into the opposite rail. The input of the OPAx171-Q1 family of devices prevents
phase reversal with excessive common-mode voltage. Instead, the output limits into the appropriate rail. Figure
7-1 shows this performance.
Copyright © 2020 Texas Instruments Incorporated
16
Submit Document Feedback
Product Folder Links: OPA171-Q1 OPA2171-Q1 OPA4171-Q1
OPA171-Q1, OPA2171-Q1, OPA4171-Q1
SBOS556D – JUNE 2011 – REVISED AUGUST 2020
www.ti.com
18 V
TLV171-Q1
Output
-18 V
37 VPP
Sine Wave
18ꢀ5 V)
(
Output
Time (100ms/div)
Figure 7-1. No Phase Reversal
7.3.3 Capacitive Load and Stability
The dynamic characteristics of the OPAx171-Q1 family of devices are optimized for commonly encountered
operating conditions. The combination of low closed-loop gain and high capacitive loads decreases the phase
margin of the amplifier and can lead to gain peaking or oscillations. As a result, heavier capacitive loads must be
isolated from the output. The simplest way to achieve this isolation is to add a small resistor (for example, ROUT
equal to 50 Ω) in series with the output. Figure 7-2 and Figure 7-3 shows small-signal overshoot versus
capacitive load for several values of ROUT. For details of analysis techniques and application circuits, see
Applications Bulletin AB-028, available for download from TI.com.
50
45
40
35
30
25
20
15
10
5
50
45
40
35
30
25
20
15
10
5
ROUT = 0 W
ROUT = 25 W
ROUT = 50 W
G = 1
18 V
TLV171-Q1
-18 V
RF = 10 kW
18 V
RI = 10 kW
G = -1
ROUT = 0 Ω
ROUT = 25 Ω
ROUT = 50 Ω
ROUT
ROUT
RL
CL
TLV171-Q1
-18 V
CL
0
0
0
100 200 300 400 500 600 700 800 900 1000
Capacitive Load (pF)
0
100 200 300 400 500 600 700 800 900 1000
Capacitive Load (pF)
Figure 7-2. Small-Signal Overshoot versus
Capacitive Load (100-mV Output Step)
Figure 7-3. Small-Signal Overshoot versus
Capacitive Load (100-mV Output Step)
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
17
Product Folder Links: OPA171-Q1 OPA2171-Q1 OPA4171-Q1
OPA171-Q1, OPA2171-Q1, OPA4171-Q1
SBOS556D – JUNE 2011 – REVISED AUGUST 2020
www.ti.com
7.4 Device Functional Modes
7.4.1 Common-Mode Voltage Range
The input common-mode voltage range of the OPAx171-Q1 family of devices extends 100 mV below the
negative rail and within 2 V of the top rail for normal operation.
This device can operate with full rail-to-rail input 100 mV beyond the top rail, but with reduced performance
within 2 V of the top rail. The typical performance in this range is listed in Table 7-1.
Table 7-1. Typical Performance Range
PARAMETER
Input common-mode voltage
Offset voltage
MIN
TYP
MAX
UNIT
V
(V+) – 2
(V+) + 0.1
7
mV
Offset voltage vs temperature
Common-mode rejection
Open-loop gain
12
65
60
0.7
0.7
30
µV/°C
dB
dB
GBW
MHz
V/µs
nV/√ Hz
Slew rate
Noise at f = 1kHz
Copyright © 2020 Texas Instruments Incorporated
18
Submit Document Feedback
Product Folder Links: OPA171-Q1 OPA2171-Q1 OPA4171-Q1
OPA171-Q1, OPA2171-Q1, OPA4171-Q1
SBOS556D – JUNE 2011 – REVISED AUGUST 2020
www.ti.com
8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
The OPAx171-Q1 operational amplifier family provides high overall performance, making the device ideal for
many general-purpose applications. The excellent offset drift of only 2 µV/°C provides excellent stability over the
entire temperature range. In addition, the device offers very good overall performance with high CMRR, PSRR,
and AOL. As with all amplifiers, applications with noisy or high-impedance power supplies require decoupling
capacitors close to the device pins. In most cases, 0.1-µF capacitors are adequate.
8.1.1 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but can involve the supply voltage pins or even the output
pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits for protection from
accidental ESD events both before and during product assembly.
A good understanding of this basic ESD circuitry and the relevance to an electrical overstress event is helpful.
illustrates the ESD circuits contained in the (indicated by the dashed line area). The ESD protection circuitry
involves several current-steering diodes connected from the input and output pins and routed back to the internal
power-supply lines, where the diodes meet at an absorption device internal to the operational amplifier. This
protection circuitry is intended to remain inactive during normal circuit operation.
TVS
R
F
+V
S
R
1
2.5 kΩ
INœ
2.5 kΩ
R
S
IN+
+
Power-Supply
ESD Cell
I
D
R
L
+
V
IN
œ
œV
S
TVS
Figure 8-1. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
An ESD event produces a short-duration, high-voltage pulse that is transformed into a short-duration, high-
current pulse when discharging through a semiconductor device. The ESD protection circuits are designed to
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
19
Product Folder Links: OPA171-Q1 OPA2171-Q1 OPA4171-Q1
OPA171-Q1, OPA2171-Q1, OPA4171-Q1
SBOS556D – JUNE 2011 – REVISED AUGUST 2020
www.ti.com
provide a current path around the operational amplifier core to prevent damage. The energy absorbed by the
protection circuitry is then dissipated as heat.
When an ESD voltage develops across two or more amplifier device pins, current flows through one or more
steering diodes. Depending on the path that the current takes, the absorption device can activate. The
absorption device has a trigger, or threshold voltage, that is above the normal operating voltage of the OPAx171-
Q1 but below the device breakdown voltage level. When this threshold is exceeded, the absorption device
quickly activates and clamps the voltage across the supply rails to a safe level.
When the operational amplifier connects into a circuit (as shown in ), the ESD protection components are
intended to remain inactive and do not become involved in the application circuit operation. However,
circumstances may arise where an applied voltage exceeds the operating voltage range of a given pin. If this
condition occurs, there is a risk that some internal ESD protection circuits can turn on and conduct current. Any
such current flow occurs through steering-diode paths and rarely involves the absorption device.
shows a specific example where the input voltage (VIN) exceeds the positive supply voltage (V+) by 500 mV or
more. Much of what happens in the circuit depends on the supply characteristics. If V+ can sink the current, one
of the upper input steering diodes conducts and directs current to V+. Excessively high current levels can flow
with increasingly higher VIN. As a result, the data sheet specifications recommend that applications limit the input
current to 10 mA.
If the supply is not capable of sinking the current, VIN can begin sourcing current to the operational amplifier and
then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise to
levels that exceed the operational amplifier absolute maximum ratings.
Another common question involves what happens to the amplifier if an input signal is applied to the input when
the power supplies (V+ or V–) are at 0 V. Again, this question depends on the supply characteristic when at 0 V,
or at a level below the input signal amplitude. If the supplies appear as high impedance, then the input source
supplies the operational amplifier current through the current-steering diodes. This state is not a normal bias
condition; most likely, the amplifier does not operate normally. If the supplies are low impedance, then the
current through the steering diodes can become quite high. The current level depends on the ability of the input
source to deliver current, and any resistance in the input path.
If there is any uncertainty about the ability of the supply to absorb this current, add external Zener diodes to the
supply pins; see . Select the Zener voltage so that the diode does not turn on during normal operation. However,
the Zener voltage must be low enough so that the Zener diode conducts if the supply pin begins to rise above
the safe-operating, supply-voltage level.
The OPAx171-Q1 input pins are protected from excessive differential voltage with back-to-back diodes; see . In
most circuit applications, the input protection circuitry has no effect. However, in low-gain or G = 1 circuits, fast-
ramping input signals can forward-bias these diodes because the output of the amplifier cannot respond rapidly
enough to the input ramp. If the input signal is fast enough to create this forward-bias condition, limit the input
signal current to 10 mA or less. If the input signal current is not inherently limited, an input series resistor can be
used to limit the input signal current. This input series resistor degrades the low-noise performance of the
OPAx171-Q1. illustrates an example configuration that implements a current-limiting feedback resistor.
Copyright © 2020 Texas Instruments Incorporated
20
Submit Document Feedback
Product Folder Links: OPA171-Q1 OPA2171-Q1 OPA4171-Q1
OPA171-Q1, OPA2171-Q1, OPA4171-Q1
SBOS556D – JUNE 2011 – REVISED AUGUST 2020
www.ti.com
8.2 Typical Application
8.2.1 Capacitive Load Drive Solution Using an Isolation Resistor
The OPAx171-Q1 device can be used capacitive loads such as cable shields, reference buffers, MOSFET gates,
and diodes. The circuit uses an isolation resistor (RISO) to stabilize the output of an op amp. RISO modifies the
open loop gain of the system to ensure the circuit has sufficient phase margin.
+VS
VOUT
RISO
+
CLOAD
+
VIN
-VS
œ
Figure 8-2. Unity-Gain Buffer with RISO Stability Compensation
8.2.1.1 Design Requirements
The design requirements are:
•
Supply voltage: 30 V (±15 V)
•
•
Capacitive loads: 100 pF, 1000 pF, 0.01 μF, 0.1 μF, and 1 μF
Phase margin: 45° and 60°
8.2.1.2 Detailed Design Procedure
Figure 8-3 shows a unity-gain buffer driving a capacitive load. Equation 1 shows the transfer function for the
circuit in Figure 8-3. Not shown in Figure 8-3 is the open-loop output resistance of the op amp, Ro.
1 + CLOAD × RISO × s
T(s) =
1 + R + R
× C
× s
o
ISO
LOAD
(1)
The transfer function in Equation 1 has a pole and a zero. The frequency of the pole (fp) is determined by (Ro +
RISO) and CLOAD. Components RISO and CLOAD determine the frequency of the zero (fz). A stable system is
obtained by selecting RISO such that the rate of closure (ROC) between the open-loop gain (AOL) and 1/β is 20
dB/decade. Figure 8-3 shows the concept. The 1/β curve for a unity-gain buffer is 0 dB.
120
AOL
100
1
fp
=
2 ì Œ ì
R
+ Ro ì C
(
)
ISO
LOAD
80
60
40
20
0
40 dB
1
fz
=
2 ì Œ ì RISO ì CLOAD
1 dec
1/ꢀ
20 dB
dec
ROC =
100M
10M
10
100
1k
10k
100k
1M
Frequency (Hz)
Figure 8-3. Unity-Gain Amplifier with RISO Compensation
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
21
Product Folder Links: OPA171-Q1 OPA2171-Q1 OPA4171-Q1
OPA171-Q1, OPA2171-Q1, OPA4171-Q1
SBOS556D – JUNE 2011 – REVISED AUGUST 2020
www.ti.com
ROC stability analysis is typically simulated. The validity of the analysis depends on multiple factors, especially
the accurate modeling of Ro. In addition to simulating the ROC, a robust stability analysis includes a
measurement of overshoot percentage and AC gain peaking of the circuit using a function generator,
oscilloscope, and gain and phase analyzer. Phase margin is then calculated from these measurements. Table
8-1 lists the overshoot percentage and AC gain peaking that correspond to phase margins of 45° and 60°. For
more details on this design and other alternative devices that can be used in place of the OPA171-Q1 , see
Capacitive Load Drive Solution using an Isolation Resistor.
Table 8-1. Phase Margin versus Overshoot and AC Gain Peaking
PHASE MARGIN
OVERSHOOT
AC GAIN PEAKING
45°
60°
23.3%
2.35 dB
8.8%
0.28 dB
8.2.1.3 Application Curve
The OPAx171-Q1 series meets the supply voltage requirements of 30 V. The OPAx171-Q1 device was tested for
various capacitive loads and RISO was adjusted to achieve an overshoot corresponding to Table 8-1. Figure 8-4
shows the test results.
10000
45è Phase Margin
60è Phase Margin
1000
100
10
1
0.01
0.1
1
10
Capacitive Load (nF)
100
1000
D001
Figure 8-4. RISO vs CLOAD
Copyright © 2020 Texas Instruments Incorporated
22
Submit Document Feedback
Product Folder Links: OPA171-Q1 OPA2171-Q1 OPA4171-Q1
OPA171-Q1, OPA2171-Q1, OPA4171-Q1
SBOS556D – JUNE 2011 – REVISED AUGUST 2020
www.ti.com
9 Power Supply Recommendations
The OPAx171-Q1 family of devices is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many
specifications apply from –40°C to +125°C. Parameters that can exhibit significant variance with regard to
operating voltage or temperature are presented in Section 6.7.
CAUTION
Supply voltages larger than 40 V can permanently damage the device; see the Section 6.1 table.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For detailed information on bypass capacitor placement, see Section 10.
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
23
Product Folder Links: OPA171-Q1 OPA2171-Q1 OPA4171-Q1
OPA171-Q1, OPA2171-Q1, OPA4171-Q1
SBOS556D – JUNE 2011 – REVISED AUGUST 2020
www.ti.com
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
•
Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp itself.
Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to
the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
•
•
Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds paying attention to the flow of the ground current.
In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If it is not possible to keep them separate, it is much better to cross the sensitive trace
perpendicular as opposed to in parallel with the noisy trace.
•
•
•
Place the external components as close to the device as possible. As shown in Figure 10-1, keeping RF and
RG close to the inverting input minimizes parasitic capacitance.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
10.2 Layout Example
Place components close
to device and to each
other to reduce parasitic
errors
Run the input traces
as far away from
the supply lines
as possible
VS+
RF
NC
NC
Use a low-ESR,
ceramic bypass
capacitor
RG
GND
œIN
+IN
Vœ
V+
OUTPUT
NC
VIN
GND
GND
VSœ
VOUT
Ground (GND) plane on another layer
Use low-ESR,
ceramic bypass
capacitor
Figure 10-1. Operational Amplifier Board Layout for Noninverting Configuration
Copyright © 2020 Texas Instruments Incorporated
24
Submit Document Feedback
Product Folder Links: OPA171-Q1 OPA2171-Q1 OPA4171-Q1
OPA171-Q1, OPA2171-Q1, OPA4171-Q1
SBOS556D – JUNE 2011 – REVISED AUGUST 2020
www.ti.com
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
•
•
Applications Bulletin AB-028
Capacitive Load Drive Solution Using an Isolation Resistor
11.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 11-1. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
SAMPLE & BUY
OPA171-Q1
OPA2171-Q1
OPA4171-Q1
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
25
Product Folder Links: OPA171-Q1 OPA2171-Q1 OPA4171-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA171AQDBVRQ1
OPA2171AQDGKRQ1
OPA2171AQDRQ1
OPA4171AQDRQ1
OPA4171AQPWRQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
VSSOP
SOIC
DBV
DGK
D
5
8
3000 RoHS & Green
2500 RoHS & Green
2500 RoHS & Green
2500 RoHS & Green
2000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
OULQ
NIPDAUAG
NIPDAU
NIPDAU
NIPDAU
2171
8
2171AQ
OPA4171Q1
O4171Q1
SOIC
D
14
14
TSSOP
PW
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF OPA171-Q1, OPA2171-Q1, OPA4171-Q1 :
Catalog: OPA171, OPA2171, OPA4171
•
Enhanced Product: OPA2171-EP
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Enhanced Product - Supports Defense, Aerospace and Medical Applications
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA171AQDBVRQ1
OPA2171AQDGKRQ1
OPA2171AQDRQ1
OPA4171AQDRQ1
OPA4171AQPWRQ1
SOT-23
VSSOP
SOIC
DBV
DGK
D
5
8
3000
2500
2500
2500
2000
180.0
330.0
330.0
330.0
330.0
8.4
3.23
5.3
6.4
6.5
6.9
3.17
3.4
5.2
9.0
5.6
1.37
1.4
2.1
2.1
1.6
4.0
8.0
8.0
8.0
8.0
8.0
Q3
Q1
Q1
Q1
Q1
12.4
12.4
16.4
12.4
12.0
12.0
16.0
12.0
8
SOIC
D
14
14
TSSOP
PW
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA171AQDBVRQ1
OPA2171AQDGKRQ1
OPA2171AQDRQ1
OPA4171AQDRQ1
OPA4171AQPWRQ1
SOT-23
VSSOP
SOIC
DBV
DGK
D
5
8
3000
2500
2500
2500
2000
202.0
366.0
356.0
356.0
356.0
201.0
364.0
356.0
356.0
356.0
28.0
50.0
35.0
35.0
35.0
8
SOIC
D
14
14
TSSOP
PW
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明