OPA4354-Q1 [TI]
汽车类 250MHz 轨到轨 I/O CMOS 四路运算放大器;
| 型号： | OPA4354-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类 250MHz 轨到轨 I/O CMOS 四路运算放大器 放大器 运算放大器 |
| 文件： | 总41页 (文件大小：1407K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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OPA354A-Q1, OPA2354A-Q1, OPA4354-Q1
ZHCSI77F –JUNE 2009–REVISED MAY 2018
OPAx354-Q1 250MHz、轨至轨 I/O CMOS 运算放大器
1 特性
3 说明
1
•
•
符合汽车类应用的 要求
具有符合 AEC Q100 标准的下列结果：
OPAx354-Q1 系列高速电压反馈 CMOS 运算放大器专
为视频应用和其他需要宽带宽的 应用 而设计。这些器
件具有单位增益稳定性，可以驱动大型输出电流。差分
增益为 0.02%，而差分相位为 0.09°。静态电流仅为每
通道 4.9mA。
–
器件温度等级：环境运行温度范围为 -40°C 至
+125°C
–
–
器件 HBM ESD 分类等级 2
器件 CDM ESD 分类等级：
OPAx354-Q1 系列运算放大器针对低至 2.5V (±1.25V)
和高达 5.5V (±2.75V) 的单电源或双电源供电运行进行
了优化。共模输入范围超出电源供电范围。电源轨的输
出摆幅在 100mV 以内，从而支持宽动态范围。
–
–
OPA354A-Q1 和 OPA2354A-Q1 为 C6
OPA4354-Q1 为 C3
•
•
•
•
•
•
•
单位增益带宽：250MHz
高带宽：100MHz GBW 产品
高压摆率：150V/μs
低噪声：6.5nV/√Hz
轨至轨 I/O
单电源版本 (OPA354A-Q1) 可提供微型 SOT–23-5
(DBV) 封装。双电源版本 (OPA2354A-Q1) 可提供微型
VSSOP-8 (DGK) 封装并 采用 完全独立的电路，可将
串扰降到最低并彻底消除相互干扰。双电源版本
(OPA4354-Q1) 可提供 TSSOP-14 (PW) 封装。该器件
的规格支持在 –40°C 至 +125°C 的汽车温度范围内运
行。
高输出电流：> 100mA
出色的视频性能
–
–
–
差动增益误差：0.02%
差动相位误差：0.09°
0.1dB 增益平坦度：40MHz
器件信息(1)
•
•
•
•
低输入偏置电流：3pA
静态电流：4.9mA
热关断
器件型号
OPA354A-Q1
OPA2354A-Q1
OPA4354-Q1
封装（引脚）
SOT-23 (5)
封装尺寸（标称值）
2.90mm × 1.60mm
3.00mm × 3.00mm
5.00mm × 4.40mm
VSSOP (8)
TSSOP (14)
电源范围：2.5V 至 5.5V
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
2 应用
•
•
•
•
•
•
•
•
•
•
•
•
•
导航和雷达系统
简化原理图
盲点监测系统
V+
短程到中程雷达添加了项目符号
视频处理
-
In
OPA354-Q1
VOUT
超声波
+In
光网络、可调激光器
光电二极管互阻放大器
有源滤波器
-
V
高速积分器
模数转换器 (ADC) 输入缓冲器
数模转换器 (DAC) 输出放大器
条形码扫描器
通信
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOS492
OPA354A-Q1, OPA2354A-Q1, OPA4354-Q1
ZHCSI77F –JUNE 2009–REVISED MAY 2018
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 20
Application and Implementation ........................ 21
8.1 Application Information............................................ 21
8.2 Typical Applications ................................................ 21
Power Supply Recommendations...................... 25
9.1 Power Dissipation ................................................... 26
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 6
6.1 Absolute Maximum Ratings ...................................... 6
6.2 ESD Ratings.............................................................. 6
6.3 Recommended Operating Conditions....................... 6
6.4 Thermal Information: OPA354A-Q1 ......................... 6
6.5 Thermal Information: OPA2354A-Q1 ....................... 7
6.6 Thermal Information: OPA4354A-Q1 ....................... 7
6.7 Electrical Characteristics........................................... 8
6.8 Typical Characteristics............................................ 10
Detailed Description ............................................ 15
7.1 Overview ................................................................. 15
7.2 Functional Block Diagram ....................................... 15
7.3 Feature Description................................................. 15
8
9
10 Layout................................................................... 26
10.1 Layout Guidelines ................................................. 26
10.2 Layout Example .................................................... 27
11 器件和文档支持 ..................................................... 28
11.1 文档支持 ............................................................... 28
11.2 相关链接................................................................ 28
11.3 接收文档更新通知 ................................................. 28
11.4 社区资源................................................................ 28
11.5 商标....................................................................... 28
11.6 静电放电警告......................................................... 28
11.7 术语表 ................................................................... 29
12 机械、封装和可订购信息....................................... 29
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision E (August 2016) to Revision F
Page
•
Deleted table note about input terminals and input signals from Absolute Maximum Ratings table .................................... 6
Changes from Revision D (July 2016) to Revision E
Page
•
Changed the gain-bandwidth product typical value from 10 MHz back to 100 MHz in the Electrical Characteristics table .. 8
Changes from Revision C (June 2016) to Revision D
Page
•
•
Changed the gain-bandwidth product typical value from 100 MHz to 10 MHz in the Electrical Characteristics table........... 8
已添加 添加了接收文档更新通知 和社区资源 部分............................................................................................................... 28
Changes from Revision B (December 2014) to Revision C
Page
•
•
已添加 将 3 个额外的 应用 添加至应用 部分 .......................................................................................................................... 1
Updated ESD Ratings table to show CDM value for OPA354A-Q1 and OPA2354A-Q1 ...................................................... 6
Changes from Revision A (August 2009) to Revision B
Page
•
•
已添加 处理额定值表，特性 说明 部分、器件功能模式、应用和实施 部分、电源建议 部分、布局 部分、器件和文档
支持 部分以及机械、封装和可订购信息 部分 ......................................................................................................................... 1
已添加 在产品说明书中添加了 OPA4354-Q1 器件................................................................................................................. 1
2
Copyright © 2009–2018, Texas Instruments Incorporated
OPA354A-Q1, OPA2354A-Q1, OPA4354-Q1
www.ti.com.cn
ZHCSI77F –JUNE 2009–REVISED MAY 2018
5 Pin Configuration and Functions
OPA354A-Q1 DBV Package
5-Pin SOT-23
Top View
OUT
1
2
3
5
4
V+
Vœ
+IN
œIN
Pin Functions: OPA354A-Q1
PIN
I/O
DESCRIPTION
NAME
+IN
NO.
3
I
Noninverting input
Inverting input
–IN
4
I
OUT
V+
1
O
—
—
Output
5
Positive (highest) supply
Negative (lowest) supply
V–
2
Copyright © 2009–2018, Texas Instruments Incorporated
3
OPA354A-Q1, OPA2354A-Q1, OPA4354-Q1
ZHCSI77F –JUNE 2009–REVISED MAY 2018
www.ti.com.cn
OPA2354A-Q1 DGK Package
8-Pin VSSOP
Top View
OUT A
œIN A
+IN A
Vœ
1
2
3
4
8
7
6
5
V+
OUT B
œIN B
+IN B
A
+
B
+
Pin Functions: OPA2354A-Q1
PIN
I/O
DESCRIPTION
NAME
+IN A
+IN B
–IN A
–IN B
OUT A
OUT B
V+
NO.
3
I
I
Noninverting input, channel A
Noninverting input, channel B
Inverting input, channel A
Inverting input, channel B
Output, channel A
5
2
I
6
I
1
O
O
—
—
7
Output, channel B
5
Positive (highest) supply
Negative (lowest) supply
V–
2
4
Copyright © 2009–2018, Texas Instruments Incorporated
OPA354A-Q1, OPA2354A-Q1, OPA4354-Q1
www.ti.com.cn
ZHCSI77F –JUNE 2009–REVISED MAY 2018
OPA4354-Q1 PW Package
14-Pin TSSOP
Top View
OUT A
œIN A
+IN A
1
2
3
14 OUT D
13 œIN D
œ
œ
A
B
D
C
+
+
12 +IN D
V+
4
5
11 Vœ
+IN B
10 +IN C
œ
œ
œIN B
6
7
9
8
œIN C
OUT B
OUT C
Pin Functions: OPA4354-Q1
PIN
I/O
DESCRIPTION
NAME
+IN A
+IN B
+IN C
+IN D
–IN A
–IN B
–IN C
–IN D
OUT A
OUT B
OUT C
OUT D
V+
NO.
3
I
I
Noninverting input, channel A
Noninverting input, channel B
Noninverting input, channel C
Noninverting input, channel D
Inverting input, channel A
Inverting input, channel B
Inverting input, channel C
Inverting input, channel D
Output, channel A
5
10
12
2
I
I
I
6
I
9
I
13
1
I
O
O
O
O
—
—
7
Output, channel B
1
Output, channel C
7
Output, channel D
5
Positive (highest) supply
Negative (lowest) supply
V–
2
Copyright © 2009–2018, Texas Instruments Incorporated
5
OPA354A-Q1, OPA2354A-Q1, OPA4354-Q1
ZHCSI77F –JUNE 2009–REVISED MAY 2018
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
7.5
UNIT
V
Supply voltage, V+ to V–, VS
Signal input terminals voltage, VIN
Output short-circuit duration(2)
Operating temperature, TA
Junction temperature, TJ
(V–) – 0.5
(V+) + 0.5
V
Continuous
–55
150
150
150
°C
°C
°C
Storage temperature, Tstg
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Short circuit to ground, one amplifier per package
6.2 ESD Ratings
VALUE
UNIT
OPA354A-Q1 IN DBV (SOT-23) PACKAGE AND OPA2354A-Q1 IN DGK (VSSOP) PACKAGE
Human body model (HBM), per AEC Q100-002(1)
±2000
±1000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per AEC Q100-011
OPA4354-Q1 IN PW (TSSOP) PACKAGE
Human body model (HBM), per AEC Q100-002(1)
Charged device model (CDM), per AEC Q100-011
±2000
±250
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
V
VS
TA
Supply voltage, V– to V+
2.5
5.5
Operating free-air temperature
–40
125
°C
6.4 Thermal Information: OPA354A-Q1
OPA354A-Q1
DBV (SOT-23)
5 PINS
216.3
OPA2354A-Q1
DGK (VSSOP)
8 PINS
175.9
OPA4354-Q1
PW (TSSOP)
14 PINS
92.6
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
84.3
67.8
27.5
43.1
97.1
33.6
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
3.8
9.3
1.9
ψJB
42.3
95.5
33.1
RθJC(bot)
N/A
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6
Copyright © 2009–2018, Texas Instruments Incorporated
OPA354A-Q1, OPA2354A-Q1, OPA4354-Q1
www.ti.com.cn
ZHCSI77F –JUNE 2009–REVISED MAY 2018
6.5 Thermal Information: OPA2354A-Q1
OPA2354A-Q1
THERMAL METRIC(1)
DGK (VSSOP)
8 PINS
175.9
67.8
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
97.1
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
9.3
ψJB
95.5
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.6 Thermal Information: OPA4354A-Q1
OPA4354-Q1
THERMAL METRIC(1)
PW (TSSOP)
14 PINS
92.6
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
27.5
33.6
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.9
ψJB
33.1
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2009–2018, Texas Instruments Incorporated
7
OPA354A-Q1, OPA2354A-Q1, OPA4354-Q1
ZHCSI77F –JUNE 2009–REVISED MAY 2018
www.ti.com.cn
6.7 Electrical Characteristics
VS = 2.5 V to 5.5 V, RF (feedback resistor) = 0 Ω, RL (load resistor) = 1 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TA = 25°C
±2
±8
VS = 5 V
VCM = (V–) + 0.8 V
VOS
Input offset voltage
mV
TA = Full range
±10
ΔVOS
ΔT
/
Offset voltage drift over
temperature
TA = Full range
±4
μV/°C
μV/V
TA = 25°C
±200
±800
±900
±50
Offset voltage drift vs power
supply
VS = 2.7 V to 5.5 V,
VCM = VS / 2 – 0.15 V
PSRR
TA = Full range
IB
Input bias current
TA = 25°C
3
±1
pA
pA
IOS
Vn
In
Input offset current
TA = 25°C
±50
Input voltage noise density
Input current noise density
f = 1 MHz, TA = 25°C
f = 1 MHz, TA = 25°C
6.5
50
nV/√Hz
fA/√Hz
Input common-mode voltage
range
VCM
TA = 25°C
(V–) – 0.1
(V+) + 0.1
V
TA = 25°C
66
64
56
55
80
68
VS = 5.5 V
–0.1 V < VCM < 3.5 V
TA = Full range
TA = 25°C
Input common-mode rejection
ratio
CMRR
dB
VS = 5.5 V
–0.1 V < VCM < 5.6 V
TA = Full range
1013 || 2
1013 || 2
ZID
Differential input impedance
TA = 25°C
TA = 25°C
Ω || pF
Ω || pF
Common-mode input
impedance
ZICM
VS = 5 V, 0.3 V < VO < 4.7 V
TA = 25°C
94
90
110
AOL
Open-loop gain
dB
VS = 5 V, 0.4 V < VO < 4.6 V
TA = Full range
G = 1, VO = 100 mVp-p, RF = 25 Ω, TA = 25°C
250
90
f–3dB
Small-signal bandwidth
Gain-bandwidth product
MHz
G = 2, VO = 100 mVp-p, TA = 25°C
G = 10
TA = 25°C
GBW
f0.1dB
100
40
MHz
MHz
Bandwidth for 0.1-dB gain
flatness
G = 2, VO = 100 mVp-p, TA = 25°C
VS = 5 V, G = 1, 4-V step, TA = 25°C
VS = 5 V, G = 1, 2-V step
150
130
110
2
SR
Slew rate
V/μs
VS = 3 V, G = 1, 2-V step
G = 1, VO = 200 mVp-p, 10% to 90%, TA = 25°C
G = 1, VO = 2 Vp-p, 10% to 90%, TA = 25°C
trf
Rise-and-fall time
ns
11
0.1%
30
VS = 5 V, G = +1, 2-V output
step, TA = 25°C
tsettle
Settling time
ns
ns
0.01%
60
VIN × Gain = VS
TA = 25°C
Overload recovery time
5
G = 1, f = 1 MHz, VO = 2 Vp-p,
RL = 200 Ω, VCM = 1.5 V
TA = 25°C
Second-order harmonic
distortion
–75
dBc
dBc
G = 1, f = 1 MHz, VO = 2 Vp-p
Third-order harmonic distortion RL = 200 Ω, VCM = 1.5 V
–83
TA = 25°C
Differential gain error
Differential phase error
NTSC, RL = 150 Ω, TA = 25°C
NTSC, RL = 150 Ω, TA = 25°C
0.02%
0.09
°
8
Copyright © 2009–2018, Texas Instruments Incorporated
OPA354A-Q1, OPA2354A-Q1, OPA4354-Q1
www.ti.com.cn
ZHCSI77F –JUNE 2009–REVISED MAY 2018
Electrical Characteristics (continued)
VS = 2.5 V to 5.5 V, RF (feedback resistor) = 0 Ω, RL (load resistor) = 1 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Channel-to-channel crosstalk
(OPA2354A-Q1) (OPA4354-
Q1)
f = 5 MHz, TA = 25°C
–100
dB
VS = 5 V, RL = 1 kΩ, AOL > 94 dB
TA = 25°C
0.1
0.3
0.4
Voltage output swing from rail
V
VS = 5 V, RL = 1 kΩ
AOL > 90 dB, TA = Full range
VS = 5 V
100
IO
Output current(1)(2)
mA
VS = 3 V
50
0.05
35
Closed-loop output impedance
Open-loop output resistance
f < 100 kHz
Ω
Ω
RO
IQ
TA = 25°C
4.9
6
Quiescent current
(per amplifier)
VS = 5 V, IO = 0, enabled
mA
°C
TA = Full range
7.5
Shutdown
160
140
Thermal shutdown junction
temperature
Reset from shutdown
(1) See typical characteristic graph Output Voltage Swing vs Output Current (图 20).
(2) Not production tested
版权 © 2009–2018, Texas Instruments Incorporated
9
OPA354A-Q1, OPA2354A-Q1, OPA4354-Q1
ZHCSI77F –JUNE 2009–REVISED MAY 2018
www.ti.com.cn
6.8 Typical Characteristics
TA = 25°C, VS = 5 V, RF = 0 Ω, RL = 1 kΩ connected to VS / 2 (unless otherwise noted)
3
0
3
6
9
3
0
3
6
9
G = 1,
RF = 25
W
VO = 0.1VPP, RF = 604
VO = 0.1VPP
W
W
W
G = +2, RF = 604
-
-
-
-
-
-
-
G =
1
G = +5, RF = 604
W
G = +10, RF = 604
-
-
2
G =
5
G =
-
G = 10
-
-
-
-
12
15
12
15
100k
1M
10M
Frequency (Hz)
100M
1G
100k
1M
10M
100M
1G
Frequency (Hz)
图 1. Noninverting Small-Signal Frequency Response
图 2. Inverting Small-Signal Frequency Response
Time (20ns/div)
Time (20ns/div)
图 3. Noninverting Small-Signal Step Response
图 4. Noninverting Large-Signal Step Response
-
-
-
-
-
50
60
70
80
90
0.5
VO = 0.1VPP
0.4
0.3
0.2
0.1
0
-
G =
1
f = 1MHz
G = +1
W
RL = 200
W
RF = 25
2nd−Harmonic
-
-
-
-
-
0.1
0.2
0.3
0.4
0.5
G = +2
W
RF = 604
3rd−Harmonic
3
-
100
0
1
2
4
100k
1M
10M
100M
1G
Output Voltage (VPP
)
Frequency (Hz)
图 5. 0.1-dB Gain Flatness
图 6. Harmonic Distortion vs Output Voltage
10
版权 © 2009–2018, Texas Instruments Incorporated
OPA354A-Q1, OPA2354A-Q1, OPA4354-Q1
www.ti.com.cn
ZHCSI77F –JUNE 2009–REVISED MAY 2018
Typical Characteristics (接下页)
TA = 25°C, VS = 5 V, RF = 0 Ω, RL = 1 kΩ connected to VS / 2 (unless otherwise noted)
-
-
-
-
-
-
-
-
-
-
50
60
70
80
90
50
60
70
80
90
VO = 2VPP
f = 1MHz
W
VO = 2VPP
f = 1MHz
W
RL = 200
RL = 200
2nd−Harmonic
2nd−Harmonic
3rd−Harmonic
3rd−Harmonic
-
-
100
100
1
10
1
10
Gain (V/V)
Gain (V/V)
图 7. Harmonic Distortion vs Noninverting Gain
图 8. Harmonic Distortion vs Inverting Gain
-
-
50
50
60
70
80
90
G = +1
G = +1
VO = 2VPP
f = 1MHz
VCM = 1.5V
VO = 2VPP
-
-
60
W
RL = 200
VCM = 1.5V
-
-
-
-
70
2nd−Harmonic
3rd−Harmonic
2nd−Harmonic
3rd−Harmonic
-
80
-
90
-
100
-
100
100k
100
1k
1M
Frequency (Hz)
10M
RL (W)
图 9. Harmonic Distortion vs Frequency
图 10. Harmonic Distortion vs Load Resistance
3
0
10k
W
RL = 10k
G = +1
1k
100
10
W
RF = 0
VO = 0.1VPP
-
3
Current Noise
Voltage Noise
W
RL = 1k
CL = 0pF
-
6
W
RL = 100
-
9
W
RL = 50
-
12
-
1
15
100k
1M
10M
100M
1G
10
100
1k
10k
100k
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
图 12. Frequency Response for Various RL Values
图 11. Input Voltage and Current Noise Spectral Density vs
Frequency
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Typical Characteristics (接下页)
TA = 25°C, VS = 5 V, RF = 0 Ω, RL = 1 kΩ connected to VS / 2 (unless otherwise noted)
160
140
120
100
80
9
6
3
0
3
6
9
G = +1
For 0.1dB
Flatness
VO = 0.1VPP
W
CL = 100pF
RS = 0
-
-
-
CL = 47pF
60
VIN
RS
VO
OPA354-Q1
40
CL = 5.6pF
CL
1k
W
-
-
12
20
15
0
100k
1M
10M
Frequency (Hz)
100M
1G
1
1k
10
100
Capacitive Load (pF)
图 13. Frequency Response for Various CL Values
图 14. Recommended RS vs Capacitive Load
3
0
100
80
60
40
20
0
G = +1
W
CL = 5.6pF, RS = 0
VO = 0.1VPP
CMRR
W
CL = 47pF, RS = 140
-
3
6
9
PSRR+
W
CL = 100pF, RS = 120
-
-
PSRR
VIN
-
RS
VO
OPA354-Q1
CL
1k
W
-
-
12
15
100k
1G
10k
100k
1M
10M
100M
1G
1M
10M
Frequency (Hz)
100M
Frequency (Hz)
图 15. Frequency Response vs Capacitive Load
图 16. Common-Mode Rejection Ratio and Power-Supply
Rejection Ratio vs Frequency
180
160
140
120
100
80
0.8
0.7
0.6
0.5
Phase
dP
0.4
60
0.3
0.2
40
Gain
20
0
0.1
-
20
dG
-
40
0
1
2
3
4
10
100
1k
10k 100k
1M
10M 100M 1G
Frequency (Hz)
W
Number of 150 Loads
图 18. Composite Video Differential Gain and Phase
图 17. Open-Loop Gain and Phase
12
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Typical Characteristics (接下页)
TA = 25°C, VS = 5 V, RF = 0 Ω, RL = 1 kΩ connected to VS / 2 (unless otherwise noted)
10k
3
2
1
0
1k
100
10
125°C
25°C
–55°C
1
-
-
-
0
20
40
60
80
100
120
55
35
15
5
25
45
65
85 105 125 135
Temperature (°C)
Output Current (mA)
VS = 3 V
图 19. Input Bias Current vs Temperature
图 20. Output Voltage Swing vs Output Current
5
4
3
2
1
0
7
6
5
4
3
2
1
0
VS = 5V
25°C
125°C
-
55°C
VS = 2.5V
-
-
-
0
25
50
75
100
125
150
175
200
55
35
15
5
25
45
65
85 105 125 135
Temperature (°C)
Output Current (mA)
VS = 5 V
图 21. Supply Current vs Temperature
图 22. Output Voltage Swing vs Output Current
100
10
6
5
4
3
2
1
0
VS = 5.5V
Maximum Output
Voltage Without
Slew−Rate
Induced Distortion
1
VS = 2.7V
0.1
0.01
OPA354-Q1
ZO
1
10
100
100k
1M
10M
100M
1G
Frequency (Hz)
Frequency (MHz)
图 23. Closed-Loop Output Impedance vs Frequency
图 24. Maximum Output Voltage vs Frequency
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Typical Characteristics (接下页)
TA = 25°C, VS = 5 V, RF = 0 Ω, RL = 1 kΩ connected to VS / 2 (unless otherwise noted)
0.5
0.4
0.3
0.2
0.1
0
120
110
100
90
W
RL = 1k
VO = 2VPP
-
-
-
-
-
0.1
0.2
0.3
0.4
0.5
80
70
0
10
20
30
40
50
60 70
80
90 100
-
-
-
15
55
35
5
25
45
65
85 105 125 135
Time (ns)
Temperature (°C)
图 25. Output Settling Time to 0.1%
图 26. Open-Loop Gain vs Temperature
100
90
80
70
60
50
Common−Mode Rejection Ratio
Power−Supply Rejection Ratio
-
-
-
-
-
-
-
-
8
7
6
5
4
3
2
1
0
1
2
3
4
5
6
7 8
-
-
-
55
35
15
5
25
45
65
85 105 125 135
Offset Voltage (mV)
Temperature (°C)
图 27. Offset Voltage Production Distribution
图 28. Common-Mode Rejection Ratio and Power-Supply
Rejection Ratio vs Temperature
0
-
20
-
40
-
60
OPA2354-Q1
-
80
-
100
-
120
100k
1M
10M
100M
1G
Frequency (Hz)
图 29. Channel-to-Channel Crosstalk (OPAx354-Q1)
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7 Detailed Description
7.1 Overview
The OPAx354-Q1 operational amplifiers are high-speed,150-V/μs, amplifiers making them excellent choices for
transimpedance applications. The devices are unity-gain stable and can operate on a single-supply voltage (2.5
V to 5.5 V), or a split-supply voltage (±1.25 V to ±2.75 V), making them highly versatile and easy to use. The
OPAx354A-Q1 amplifiers are specified from 2.5 V to 5.5 V and over the automotive temperature range of –40°C
to +125°C.
表 1. OPAx354-Q1 Related Products
FEATURES
PRODUCT
OPAx357
OPAx355
OPAx356
OPAx350/3
OPAx631
OPAx634
THS412x
Shutdown Version of OPA354 Family
200-MHz GBW, Rail-to-Rail Output, CMOS, Shutdown
200-MHz GBW, Rail-to-Rail Output, CMOS
38-MHz GBW, Rail-to-Rail Input/Output, CMOS
75-MHz BW, G = 2, Rail-to-Rail Output
150-MHz BW, G = 2, Rail-to-Rail Output
100-MHz BW, Differential Input/Output, 3.3-V Supply
7.2 Functional Block Diagram
V+
Reference
Current
VIN+
œ
VIN
VBIAS1
Class AB
Control
VO
Circuitry
VBIAS2
œ
V
(Ground)
7.3 Feature Description
7.3.1 Operating Voltage
The specifications of the OPAx354-Q1 family of devices apply over a power-supply range of 2.5 V to 5.5 V
(±1.25 V to ±2.75 V). Supply voltages higher than 7.5 V (absolute maximum) can permanently damage the
amplifier.
The Typical Characteristics section of this data sheet shows the parameters that vary over supply voltage or
temperature.
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Feature Description (接下页)
7.3.2 Rail-to-Rail Input
The specified input common-mode voltage range of the OPAx354-Q1 family of devices extends 100 mV beyond
the supply rails. A complementary input stage (an N-channel input differential pair in parallel with a P-channel
differential pair) achieves this extension. The N-channel pair is active for input voltages close to the positive rail,
typically (V+) – 1.2 V to 100 mV above the positive supply, while the P-channel pair is on for inputs from 100 mV
below the negative supply to approximately (V+) – 1.2 V. A small transition region exists, typically (V+) – 1.5 V to
(V+) – 0.9 V, in which both pairs are on. This 600-mV transition region can vary ±500 mV with process variation.
As a result, the transition region (both input stages on) range from (V+) – 2 V to (V+) – 1.5 V on the low end, up
to (V+) – 0.9 V to (V+) – 0.4 V on the high end.
A double-folded cascode adds the signal from the two input pairs and presents a differential signal to the class-
AB output stage.
7.3.3 Rail-to-Rail Output
The device uses a class-AB output stage with common-source transistors to achieve rail-to-rail output. For high-
impedance loads (> 200 Ω), the output voltage swing is typically 100 mV from the supply rails. With 10-Ω loads,
a user can achieve a useful output swing while maintaining high open-loop gain; see 图 20 (Output Voltage
Swing vs Output Current).
7.3.4 Output Drive
The OPAx354-Q1 output stage supplies a continuous output current of ±100 mA and still provide approximately
2.7-V output swing on a 5-V supply, as shown in 图 30.
R2
+
1 kΩ
V1
5 V
-
C1
50 pF
1 µF
R1
V+
10 kΩ
OPA354-Q1
-
R3
V
RSHUNT
10 kΩ
VIN
+
1 Ω
1 V In = 100 mA
Out as shown
R4
-
1 kΩ
Laser Diode
图 30. Laser Diode Driver
For maximum reliability, TI does not recommend running a continuous DC current greater than ±100 mA; see 图
20 (Output Voltage Swing vs Output Current). Operate the OPAx354-Q1 family of devices in parallel to supply
continuous output currents greater than ±100 mA, as shown in 图 31.
16
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Feature Description (接下页)
R2
10kW
C1
200pF
+5V
1mF
R1
100kW
R5
1W
OPA2354-Q1
R3
100kW
+
-
R6
1W
RSHUNT
1W
2V In = 200mA
Out, as Shown
OPA2354-Q1
R4
10kW
Laser Diode
图 31. Parallel Operation
The OPAx354-Q1 family of devices provides peak currents up to 200 mA, which correspond to the typical short-
circuit current. Therefore, an on-chip thermal shutdown circuit protects the OPAx354-Q1 family of devices from
dangerously high junction temperatures. At 160°C, the protection circuit shuts down the amplifier. Normal
operation resumes when the junction temperature cools below 140°C.
7.3.5 Video
The OPAx354-Q1 output stage is capable of driving standard back-terminated 75-Ω video cables (see 图 32). A
back-terminated transmission line does not exhibit a capacitive load to the driver. A properly back-terminated 75-
Ω cable does not appear as capacitance; the cable presents a 150-Ω resistive load to the OPAx354-Q1 output.
5 V
Video
75 Ω
In
Video
Output
OPA354-Q1
75 Ω
2.5 V
604 Ω
604 Ω
2.5 V
图 32. Single-Supply Video Line Driver
This series of amplifiers can be used as an amplifier for RGB graphic signals, which have a voltage of zero at the
video black level by offsetting and AC-coupling the signal (see 图 33).
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Feature Description (接下页)
604 Ω
3 V
+
10 nF
1 µF
V+
604 Ω
75 Ω
1/2
Red
75 Ω
R1
R2
OPA2354-Q1
Red(1)
V+
R1
R2
Green(1)
75 Ω
1/2
Green
75 Ω
OPA2354-Q1
604 Ω
604 Ω
604 Ω
3 V
+
1 µF
10 nF
V+
604 Ω
75 Ω
Blue
R1
R2
OPA354-Q1
Blue(1)
75 Ω
(1) Source video signal offset 300 mV above ground to accommodate op amp swing to ground capability.
图 33. RGB Cable Driver
7.3.6 Driving Analog-to-Digital Converters
The OPAx354-Q1 family of op-amps offers a 60-ns settling time to 0.01%, which makes the devices a viable
option for driving high- and medium-speed sampling ADCs and reference circuits. The OPAx354-Q1 family of
devices provides an effective means of buffering the input capacitance and resulting charge injection of the ADC
while providing signal gain. The OPAx354-Q1 family of devices is designed for applications requiring high DC
accuracy.
图 34 shows the OPAx354-Q1 family of devices driving an ADC. With the OPAx354-Q1 family of devices in an
inverting configuration, using a capacitor across the feedback resistor can filter high-frequency noise in the
signal.
18
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Feature Description (接下页)
+5V
330pF
W
W
5k
5k
VIN
VREF
V+
ADS7816, ADS7861,
or ADS7864
+In
OPA354-Q1
12−Bit A/D Converter
+2.5V
-
In
GND
-
VIN = 0V to 5V for 0V to 5V output.
NOTE: A/D Converter Input = 0V to VREF
图 34. OPA354A-Q1 Inverting Configuration Driving the ADS7816
7.3.7 Capacitive Load and Stability
The OPAx354-Q1 family op amps can drive a wide range of capacitive loads. However, all op-amps under
certain conditions can become unstable. Op amp configuration, gain, and load value are a few of the factors to
consider when determining stability. An op amp in unity-gain configuration is most susceptible to the effects of
capacitive loading. The capacitive load reacts with the output resistance of the op amp, along with any additional
load resistance, to create a pole in the small-signal response that degrades the phase margin. For details, see 图
15 (Frequency Response vs Capacitive Load.)
The OPAx354-Q1 topology enhances the ability of the device to drive capacitive loads. In unity gain, these op-
amps perform well with large capacitive loads. For details see 图 14, Recommended RS vs Capacitive Load, and
图 15, Frequency Response vs Capacitive Load.
Insert a 10-Ω to 20-Ω resistor in series with the output to improve capacitive laod drive in the unity-gain
configuration, as shown in 图 35. This configuration significantly reduces ringing with large capacitive loads; see
图 15 (Frequency Response vs Capacitive Load.) However, if a resistive load is in parallel with the capacitive
load, RS creates a voltage divider. This configuration introduces a DC error at the output and slightly reduces
output swing. This error may be insignificant. For example, if RL = 10 kΩ and RS = 20 Ω, the error at the output is
approximately 0.2%.
V+
RS
OPA354-Q1
VOUT
VIN
RL
CL
图 35. Series Resistor in Unity-Gain Configuration Improves Capacitive Load Drive
7.3.8 Wideband Transimpedance Amplifier
Wide bandwidth, low-input bias current, and low input voltage and current noise make the OPAx354-Q1 family of
devices is designed as a wideband photodiode transimpedance amplifier for low-voltage single-supply
applications. Low-voltage noise is important because photodiode capacitance causes the effective noise gain of
the circuit to increase at high frequency.
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Feature Description (接下页)
The key elements to a transimpedance design, as shown in 图 36, are the expected diode capacitance [including
the parasitic input common-mode and differential-mode input capacitance (2 + 2) pF for the OPAx354-Q1], the
desired transimpedance gain (RF), and the gain-bandwidth product (GBW) for the OPAx354-Q1 family of devices
(100 MHz). With these three variables set, the feedback capacitor value (CF) is set to control the frequency
response.
CF
< 1 pF
(prevents gain peaking)
RF
10 MΩ
+V
l
CD OPA354-Q1
VOUT
图 36. Transimpedance Amplifier
To achieve a maximally flat second-order Butterworth frequency response, set the feedback pole as shown in 公
式 1.
GBP
4pRFCD
1
+
Ǹ
2pRFCF
(1)
Typical surface-mount resistors have a parasitic capacitance of approximately 0.2 pF that required deduction
from the calculated feedback capacitance value.
Use 公式 2 to calculate the bandwidth.
GBP
2pRFCD
f*3dB
+
Hz
Ǹ
(2)
For even higher transimpedance bandwidth, use the high-speed CMOS OPA355-Q1 (200-MHz GBW) or the
OPA655-Q1 (400-MHz GBW).
7.4 Device Functional Modes
The OPAx354-Q1 family of devices is powered on when the supply is connected. The devices operates as a
single-supply operational amplifier or dual-supply amplifier depending on the application. The devices are used
with asymmetrical supplies as long as the differential voltage (V– to V+) is at least 1.8 V and no greater than 5.5
V (example: V– set to –3.5 V and V+ set to 1.5 V).
20
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ZHCSI77F –JUNE 2009–REVISED MAY 2018
8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The OPAx354-Q1 family of devices is a CMOS, rail-to-rail I/O, high-speed, voltage-feedback operational amplifier
designed for video, high-speed, and other applications. The OPAx354-Q1 family of devices is available as a
single, dual, or quad op-amp.
The amplifier features a 100-MHz gain bandwidth, and 150 V/μs slew rate, but the device is unity-gain stable and
operates as a 1-V/V voltage follower.
8.2 Typical Applications
8.2.1 Transimpedance Amplifier
Wide gain bandwidth, low input bias current, low input voltage, and current noise make the OPAx354-Q1 family
of devices a preferred wideband photodiode transimpedance amplifier. Low-voltage noise is important because
photodiode capacitance causes the effective noise gain of the circuit to increase at high frequency.
The key elements to a transimpedance design, as shown in 图 37, are the expected diode capacitance (C(D)),
which must include the parasitic input common-mode and differential-mode input capacitance (4 pF + 5 pF); the
desired transimpedance gain (R(FB)); and the gain-bandwidth (GBW) for the OPAx354-Q1 family of devices (20
MHz). With these three variables set, the feedback capacitor value (C(FB)) is set to control the frequency
response. C(FB) includes the stray capacitance of R(FB), which is 0.2 pF for a typical surface-mount resistor.
(1)
C(F)
< 1 pF
R(F)
10 MΩ
V(V+)
l
VO
C(D)
OPA354-Q1
V(V–)
(1) C(FB) is optional to prevent gain peaking. C(FB) includes the stray capacitance of R(FB)
.
图 37. Dual-Supply Transimpedance Amplifier
8.2.1.1 Design Requirements
PARAMETER
VALUE
2.5 V
Supply voltage V(V+)
Supply voltage V(V–)
–2.5 V
8.2.1.2 Detailed Design Procedure
To achieve a maximally-flat, second-order Butterworth frequency response, the feedback pole must be set to:
1
GBW
=
2 ´ p ´ R(FB) ´ C(FB)
4 ´ p ´ R(FB) ´ C(D)
(3)
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Use 公式 4 to calculate the bandwidth.
GBW
ƒ(–3 dB)
=
2 ´ p ´ R(FB) ´ C(D)
(4)
For other transimpedance bandwidths, consider the high-speed CMOS OPA380 (90-MHz GBW), OPA354 (100-
MHz GBW), OPA300 (180-MHz GBW), OPA355 (200-MHz GBW), or OPA656 and OPA657 (400-MHz GBW).
For single-supply applications, the +INx input can be biased with a positive DC voltage to allow the output to
reach true zero when the photodiode is not exposed to any light, and respond without the added delay that
results from coming out of the negative rail; this configuration is shown in 图 38. This bias voltage appears
across the photodiode, providing a reverse bias for faster operation.
0.5 pF
100 kꢀ
œ
OPAx354-Q1
VOUT
+
13.7 kꢀ
SFH213
5 V
1 ꢁF
280 ꢀ
图 38. Single-Supply Transimpedance Amplifier
For additional information, see the Compensate Transimpedance Amplifiers Intuitively application bulletin.
8.2.1.2.1 Optimizing The Transimpedance Circuit
To achieve the best performance, components must be selected according to the following guidelines:
1. For lowest noise, select R(FB) to create the total required gain. Using a lower value for R(FB) and adding gain
after the transimpedance amplifier generally produces poorer noise performance. The noise produced by
R(FB) increases with the square-root of R(FB), whereas the signal increases linearly. Therefore, signal-to-noise
ratio improves when all the required gain is placed in the transimpedance stage.
2. Minimize photodiode capacitance and stray capacitance at the summing junction (inverting input). This
capacitance causes the voltage noise of the op amp to be amplified (increasing amplification at high
frequency). Using a low-noise voltage source to reverse-bias a photodiode can significantly reduce the
capacitance. Smaller photodiodes have lower capacitance. Use optics to concentrate light on a small
photodiode.
3. Noise increases with increased bandwidth. Limit the circuit bandwidth to only that required. Use a capacitor
across the R(FB) to limit bandwidth, even if not required for stability.
4. Circuit board leakage can degrade the performance of an otherwise well-designed amplifier. Clean the circuit
board carefully. A circuit board guard trace that encircles the summing junction and is driven at the same
voltage can help control leakage.
For additional information, see the Noise Analysis of FET Transimpedance Amplifiers, and Noise Analysis for
High-Speed Op Amps) application bulletins.
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8.2.1.3 Application Curve
105
100
95
90
85
80
75
70
65
60
1000
10000
100000
1000000
1E+7
5E+7
Frequency (Hz)
D001
–3 dB bandwidth is 4.56 MHz
图 39. AC Transfer Function
8.2.2 High-Impedance Sensor Interface
Many sensors have high source impedances that may range up to 10 MΩ, or even higher. The output signal of
sensors often must be amplified or otherwise conditioned by an amplifier. The input bias current of this amplifier
can load the sensor output and cause a voltage drop across the source resistance, as shown in 图 40, where
(V(+INx) = VS – I(BIAS) × R(S)). The last term, I(BIAS) × R(S), shows the voltage drop across R(S). To prevent errors
introduced to the system as a result of this voltage, use an op amp with low input bias current and high-
impedance sensors. This low current keeps the error contribution by I(BIAS) × R(S) less than the input voltage
noise of the amplifier, so that the amplifier does not become the dominant noise factor. The OPAx354-Q1 family
of devices series of op amps feature low input bias current (typically 200 fA), and are therefore designed for such
applications.
R(S)
IIB
100 kΩ
V(+INx)
V(V+)
VO
R(F)
Device
V(V–)
R(G)
图 40. Noise as a Result of I(BIAS)
版权 © 2009–2018, Texas Instruments Incorporated
23
OPA354A-Q1, OPA2354A-Q1, OPA4354-Q1
ZHCSI77F –JUNE 2009–REVISED MAY 2018
www.ti.com.cn
8.2.3 Driving ADCs
The OPAx354-Q1 op amps are designed for driving sampling analog-to-digital converters (ADCs) with sampling
speeds up to 1 MSPS. The zero-crossover distortion input stage topology allows the OPAx354-Q1 family of
devices to drive ADCs without degradation of differential linearity and THD.
The OPAx354-Q1 family of devices can be used to buffer the ADC switched input capacitance and resulting
charge injection while providing signal gain. 图 41 shows the OPAx354-Q1 family of devices configured to drive
the ADS8326.
5 V
C1
100 nF
5 V
R1(1)
100 Ω
V(V+)
+INx
OPAx354-Q1
ADS8326
16-Bit
250kSPS
C3(1)
1 nF
V(V–)
–INx
VI
0 to 4.096 V
REF IN
Optional(2)
5 V
R2
50 kΩ
SD1
BAS40
REF3240
4.096 V
–5 V
C2
100 nF
C4
100 nF
(1) Suggested value; may require adjustment based on specific application.
(2) Single-supply applications lose a small number of ADC codes near ground as a result of op amp output swing limitation. If a negative
power supply is available, this simple circuit creates a –0.3-V supply to allow output swing to true ground potential.
图 41. Driving the ADS8326
8.2.4 Active Filter
The OPAx354-Q1 family of devices is designed for active filter applications that require a wide bandwidth, fast
slew rate, low-noise, single-supply operational amplifier. 图 42 shows a 500 kHz, second-order, low-pass filter
using the multiple-feedback (MFB) topology. The components are selected to provide a maximally-flat
Butterworth
response.
Beyond
the
cutoff
frequency,
roll-off
is
–40 dB/dec. The Butterworth response is designed for applications requiring predictable gain characteristics,
such as the anti-aliasing filter used in front of an ADC.
One point to observe when considering the MFB filter is that the output is inverted relative to the input. If this
inversion is not required, or not desired, a noninverting output can be achieved through one of the following
options:
1. Adding an inverting amplifier
2. Adding an additional second-order MFB stage
3. Using a noninverting filter topology, such as the Sallen-Key (see 图 43).
MFB and Sallen-Key, low-pass and high-pass filter synthesis is accomplished using TI’s FilterPro™ program.
This software is available as a free download on www.ti.com.
24
版权 © 2009–2018, Texas Instruments Incorporated
OPA354A-Q1, OPA2354A-Q1, OPA4354-Q1
www.ti.com.cn
ZHCSI77F –JUNE 2009–REVISED MAY 2018
R3
549 Ω
C2
150 pF
V(V+)
R1
549 Ω
R2
1.24 kΩ
VI
VO
Device
C1
1 nF
V(V–)
图 42. Second-Order Butterworth 500-kHz Low-Pass Filter
220 pF
V(V+)
19.5 kΩ
150 kΩ
1.8 kΩ
VI = 1 VRMS
VO
Device
3.3 nF
47 pF
V(V–)
图 43. OPAx354-Q1 Configured as a Three-Pole, 20-kHz, Sallen-Key Filter
9 Power Supply Recommendations
The OPAx354-Q1 family of devices is specified for operation from 2.5 to 5.5 V (±1.25 to ±2.75 V); many
specifications apply from –40°C to +125°C. Parameters that can exhibit significant variance with regard to
operating voltage or temperature are shown in the Typical Characteristics section.
CAUTION
Supply voltages larger than 7.5 V can permanently damage the device (see the
Absolute Maximum Ratings table).
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, see the Layout
Guidelines section.
版权 © 2009–2018, Texas Instruments Incorporated
25
OPA354A-Q1, OPA2354A-Q1, OPA4354-Q1
ZHCSI77F –JUNE 2009–REVISED MAY 2018
www.ti.com.cn
9.1 Power Dissipation
Power dissipation depends on power-supply voltage, signal and load conditions. With dc signals, power
dissipation is equal to the product of output current times the voltage across the conducting output transistor
(VS – VO). Minimize power dissipation by using the lowest possible power-supply voltage required to ensure the
required output voltage swing.
For resistive loads, the maximum power dissipation occurs at a DC output voltage of one-half the power-supply
voltage. Dissipation with AC signals is lower. The Power Amplifier Stress and Power Handling Limitations
application bulletin from www.ti.com explains how to calculate or measure power dissipation with unusual signals
and loads.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heat sink. For reliable operation, limit junction temperature to 150°C, maximum. To estimate the margin of safety
in a complete design, increase the ambient temperature to trigger the thermal protection at 160°C. The thermal
protection must trigger more than 35°C above the maximum expected ambient condition of the application.
10 Layout
10.1 Layout Guidelines
Use good high-frequency printed circuit board (PCB) layout techniques for the OPAx354-Q1 family of devices.
Generous use of ground planes, short and direct signal traces, and a suitable bypass capacitor located at the V+
pin ensure clean, stable operation. Large areas of copper provide a means of dissipating heat that is generated
in normal operation. Sockets are not recommended for use with any high-speed amplifier. A 10-nF ceramic
bypass capacitor is the minimum recommended value; adding a 1-μF or larger tantalum capacitor in parallel can
be beneficial when driving a low-resistance load. Providing adequate bypass capacitance is essential to
achieving very low harmonic and intermodulation distortion.
For best operational performance of the device, use good PCB layout practices, including:
•
Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the
operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low-
impedance power sources local to the analog circuitry.
–
Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
•
•
Separate grounding for analog and digital portions of the circuitry is one of the simplest and most
effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to
ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to
physically separate digital and analog grounds, paying attention to the flow of the ground current. For
more detailed information, see Circuit Board Layout Techniques.
To reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicularly is much
better than crossing in parallel with the noisy trace.
•
•
•
Place the external components as close to the device as possible. Keeping RF and RG close to the
inverting input minimizes parasitic capacitance, as shown in 图 44.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
26
版权 © 2009–2018, Texas Instruments Incorporated
OPA354A-Q1, OPA2354A-Q1, OPA4354-Q1
www.ti.com.cn
ZHCSI77F –JUNE 2009–REVISED MAY 2018
10.2 Layout Example
Place components close
to device and to each
other to reduce parasitic
errors
Run the input traces
as far away from
the supply lines
as possible
VS+
RF
NC
NC
Use a low-ESR,
ceramic bypass
capacitor
RG
GND
œIN
+IN
Vœ
V+
OUTPUT
NC
VIN
GND
GND
VSœ
VOUT
Ground (GND) plane on another layer
Use low-ESR,
ceramic bypass
capacitor
图 44. Operational Amplifier Board Layout for Noninverting Configuration
版权 © 2009–2018, Texas Instruments Incorporated
27
OPA354A-Q1, OPA2354A-Q1, OPA4354-Q1
ZHCSI77F –JUNE 2009–REVISED MAY 2018
www.ti.com.cn
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档
请参阅如下相关文档：
•
•
•
•
•
•
•
•
•
•
•
德州仪器 (TI)，《ADS8326 16 位高速 2.7V 至 5.5V 微功耗采样模数转换器》
德州仪器 (TI)，《电路板布局技巧》
德州仪器 (TI)，《用直观方式补偿跨阻放大器》
德州仪器 (TI)，《FilterPro™ 用户指南》
德州仪器 (TI)，《FET 跨阻放大器噪声分析》
德州仪器 (TI)，《高速运算放大器噪声分析》
德州仪器 (TI)，《OPA380 和 OPA2380 精密高速跨阻放大器》
德州仪器 (TI)，《OPA354、OPA2354 和 OPA4354 250MHz 轨至轨 I/O CMOS 运算放大器》
德州仪器 (TI)，《具有关断功能的 OPA355、OPA2355 和 OPA3355 200MHz CMOS 运算放大器》
德州仪器 (TI)，《OPA656 宽带单位增益稳定 FET 输入运算放大器》
德州仪器 (TI)，《功率放大器应力和功率处理限制》
11.2 相关链接
下表列出了快速访问链接。类别包括技术文档、支持与社区资源、工具和软件，以及申请样片或购买产品的快速链
接。
表 2. 相关链接
器件
产品文件夹
单击此处
单击此处
单击此处
立即订购
单击此处
单击此处
单击此处
技术文档
单击此处
单击此处
单击此处
工具与软件
单击此处
单击此处
单击此处
支持和社区
单击此处
单击此处
单击此处
OPA354A-Q1
OPA2354A-Q1
OPA4354-Q1
11.3 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.5 商标
E2E is a trademark of Texas Instruments.
FilterPro is a trademark of Texas Instruments Incorporated.
All other trademarks are the property of their respective owners.
11.6 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
28
版权 © 2009–2018, Texas Instruments Incorporated
OPA354A-Q1, OPA2354A-Q1, OPA4354-Q1
www.ti.com.cn
ZHCSI77F –JUNE 2009–REVISED MAY 2018
11.7 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此产品说明书的浏览器版本，请查阅左侧的导航栏。
版权 © 2009–2018, Texas Instruments Incorporated
29
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA2354AQDGKRQ1
OPA354AQDBVRQ1
OPA4354AQPWRQ1
ACTIVE
ACTIVE
ACTIVE
VSSOP
SOT-23
TSSOP
DGK
DBV
PW
8
5
2500 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
OSLQ
3000 RoHS & Green
2000 RoHS & Green
NIPDAU
NIPDAU
Level-2-260C-1 YEAR
Level-3-260C-168 HR
OSFQ
14
4354Q1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA354AQDBVRQ1
OPA4354AQPWRQ1
SOT-23
TSSOP
DBV
PW
5
3000
2000
179.0
330.0
8.4
3.2
6.9
3.2
5.6
1.4
1.6
4.0
8.0
8.0
Q3
Q1
14
12.4
12.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA354AQDBVRQ1
OPA4354AQPWRQ1
SOT-23
TSSOP
DBV
PW
5
3000
2000
213.0
356.0
191.0
356.0
35.0
35.0
14
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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