OPA4H199-SEP [TI]
航天增强型产品四路 40V 4.5MHz 轨到轨输入和输出运算放大器;
| 型号： | OPA4H199-SEP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 航天增强型产品四路 40V 4.5MHz 轨到轨输入和输出运算放大器 放大器 运算放大器 |
| 文件： | 总36页 (文件大小：2531K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OPA4H199-SEP
ZHCSOA0 –NOVEMBER 2022
OPA4H199-SEP 采用增强型航天塑料封装的40V、耐辐射、轨至轨输入/输出、
低失调电压、低噪声运算放大器
1 特性
2 应用
• 耐辐射
• 支持近地轨道航天应用
• 航天传感器和控制（遥测）
• 卫星电力系统(EPS)
• 飞行控制
• 卫星命令和数据处理
• 卫星有效载荷
– 单粒子闩锁(SEL) 在125°C 下的抗扰度可达
43MeV-cm2/mg
– 在高达30krad (Si) 的条件下无ELDRS
– 每个晶圆批次的RLAT 总电离剂量(TID) 高达
30krad (Si)
• 支持国防、航天和医疗应用
– 单受控基线
3 说明
OPA4H199-SEP 是一款适用于航天应用的高电压
(40V) 通用运算放大器。该器件具有出色的直流精度和
交流性能，包括轨至轨输入/输出、低失调电压（典型
值为 ±125µV）、低温漂（典型值为 ±0.3µV/°C）、低
噪声（10.8nV/√Hz 和1.8µVPP）和4.5MHz 带宽。
– 制造、组装和测试一体化基地
– 金线
– NiPdAu 铅涂层
– 支持军用（–55°C 至125°C）温度范围
– 延长了产品生命周期
– 延长了产品变更通知
– 产品可追溯性
– 采用增强型模塑化合物实现低释气
OPA4H199-SEP 具有独特功能，例如电源轨的差分和
共模输入电压范围、高输出电流 (±75mA)、高压摆率
(21V/µs) 和高容性负载驱动 (1nF)，是一款稳定可靠的
高性能运算放大器，适用于高电压航天应用。
• 低失调电压：±125µV
• 低噪声：1 kHz 时为10.8nV/√Hz
• 高共模抑制：130dB
• 低偏置电流：±10pA
• 轨至轨输入和输出
• 宽带宽：4.5MHz GBW
• 高压摆率：21V/µs
OPA4H199-SEP 采用小型、耐辐射塑料、14 引脚
SOT-23 (DYY) 封装。SOT-23 (DYY) 封装的封装尺寸
大小不足传统 14 引脚陶瓷封装尺寸的五分之一。
OPA4H199-SEP 额定运行温度为-55°C 至125°C。
器件信息
• 高容性负载驱动：1nF
器件型号(1)
封装尺寸（标称值）
封装
• 支持多路复用器/比较器的输入
• 低静态电流：每个放大器560µA
• 宽电源电压：±1.35V 至±20V，2.7V 至40V
• 强大的EMIRR 性能：输入引脚和电源引脚上采用
OPA4H199-SEP
SOT-23 (14)
4.20mm × 1.90mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
EMI/RFI 滤波器
Analog Inputs
REF3140
RC Filter
RC Filter
Bridge Sensor
Reference Driver
Gain Network
Gain Network
+
MUX509
Thermocouple
REF
VINP
+
Gain Network
+
Antialiasing
Filter
ADS8860
Current Sensing
VINM
Photo
Detector
LED
High-Voltage Multiplexed Input
High-Voltage Level Translation
VCM
Optical Sensor
高电压信号链中的OPA4H199-SEP
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOSA90
OPA4H199-SEP
ZHCSOA0 –NOVEMBER 2022
www.ti.com.cn
Table of Contents
7.4 Device Functional Modes..........................................23
8 Application and Implementation..................................24
8.1 Application Information............................................. 24
8.2 Typical Applications.................................................. 24
8.3 Power Supply Recommendations.............................26
8.4 Layout....................................................................... 26
9 Device and Documentation Support............................28
9.1 Device Support......................................................... 28
9.2 Documentation Support............................................ 28
9.3 接收文档更新通知..................................................... 28
9.4 支持资源....................................................................28
9.5 Trademarks...............................................................28
9.6 Electrostatic Discharge Caution................................28
9.7 术语表....................................................................... 29
10 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information for Quad Channel...................... 4
6.5 Electrical Characteristics.............................................5
6.6 Typical Characteristics................................................7
7 Detailed Description......................................................14
7.1 Overview...................................................................14
7.2 Functional Block Diagram.........................................14
7.3 Feature Description...................................................15
Information.................................................................... 30
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
November 2022
*
Initial Release
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5 Pin Configuration and Functions
OUT1
IN1œ
IN1+
V+
1
2
3
4
5
6
7
14
13
12
11
10
9
OUT4
IN4œ
IN4+
Vœ
IN2+
IN2œ
OUT2
IN3+
IN3œ
OUT3
8
Not to scale
图5-1. OPA4H199-SEP DYY Package
14-Pin SOT-23 (14)
Top View
表5-1. Pin Functions: OPA4H199-SEP
PIN
I/O
DESCRIPTION
NAME
NO.
3
IN1+
IN1–
IN2+
IN2–
IN3+
IN3–
IN4+
IN4–
OUT1
OUT2
OUT3
OUT4
V+
I
I
Noninverting input, channel 1
Inverting input, channel 1
Noninverting input, channel 2
Inverting input, channel 2
Noninverting input, channel 3
Inverting input, channel 3
Noninverting input, channel 4
Inverting input, channel 4
Output, channel 1
2
5
I
6
I
10
9
I
I
12
13
1
I
I
O
O
O
O
—
—
7
Output, channel 2
8
Output, channel 3
14
4
Output, channel 4
Positive (highest) power supply
Negative (lowest) power supply
11
V–
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6 Specifications
6.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted) (1)
MIN
0
MAX
UNIT
V
42
(V+) + 0.5
VS + 0.2
10
Supply voltage, VS = (V+) –(V–)
Common-mode voltage (3)
V
(V–) –0.5
Signal input pins
Differential voltage (3)
Current (3)
V
mA
–10
–55
–65
Output short-circuit (2)
Continuous
Operating ambient temperature, TA
Junction temperature, TJ
Storage temperature, Tstg
150
150
150
°C
°C
°C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) Short-circuit to ground, one amplifier per package. This device has been designed to limit electrical damage due to excessive output
current, but extended short-circuit current, especially with higher supply voltage, can cause excessive heating and eventual thermal
destruction. See the Thermal Protection section for more information.
(3) Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be
current limited to 10 mA or less.
6.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-C101 (2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
2.7
MAX
UNIT
VS
VI
40
(V+) + 0.1
125
V
V
Supply voltage, (V+) –(V–)
Input voltage range
(V–) –0.1
–55
TA
Specified ambient temperature
°C
6.4 Thermal Information for Quad Channel
OPA4H199-SEP
DYY
(SOT-23)
THERMAL METRIC (1)
UNIT
14 PINS
121.6
53.6
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
RθJC(top)
RθJB
°C/W
°C/W
°C/W
°C/W
°C/W
47.8
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
2.1
ψJT
47.6
ψJB
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
For VS = (V+) –(V–) = 2.7 V to 40 V (±1.35 V to ±20 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and
VO UT = VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
±125
±895
±925
VOS
Input offset voltage
µV
VCM = V–
TA = –-55°C to 125°C
dVOS/dT
PSRR
Input offset voltage drift
±0.3
±0.3
±1
TA = –-55°C to 125°C
µV/℃
µV/V
µV/V
±1
±5
VCM = V–, VS = 4 V to 40 V
VCM = V–, VS = 2.7 V to 40 V(2)
f = 0 Hz
Input offset voltage
versus power supply
TA = –-55°C to 125°C
Channel separation
5
INPUT BIAS CURRENT
IB
Input bias current
±10
±10
pA
pA
IOS
Input offset current
NOISE
1.8
0.3
µVPP
EN
Input voltage noise
f = 0.1 Hz to 10 Hz
µVRMS
f = 1 kHz
f = 10 kHz
f = 1 kHz
10.8
9.4
Input voltage noise
density
eN
iN
nV/√Hz
fA/√Hz
Input current noise
82
INPUT VOLTAGE RANGE
Common-mode voltage
range
VCM
(V+) + 0.1
V
(V–) –0.1
VS = 40 V, (V–) –0.1 V < VCM
(V+) –2 V (Main input pair)
<
107
130
100
95
VS = 4 V, (V–) –0.1 V < VCM < (V+)
–2 V (Main input pair)
82
75
Common-mode rejection
ratio
CMRR
dB
TA = –-55°C to 125°C
VS = 2.7 V, (V–) –0.1 V < VCM
(V+) –2 V (Main input pair)(2)
<
VS = 2.7 V to 40 V, (V+) –1 V < VCM
< (V+) + 0.1 V (Aux input pair)
85
INPUT CAPACITANCE
ZID
Differential
100 || 9
6 || 1
MΩ|| pF
TΩ|| pF
ZICM
Common-mode
OPEN-LOOP GAIN
120
104
101
145
142
130
125
120
118
VS = 40 V, VCM = V–
(V–) + 0.1 V < VO < (V+) – 0.1 V
TA = –-55°C to 125°C
TA = –-55°C to 125°C
TA = –-55°C to 125°C
VS = 4 V, VCM = V–
(V–) + 0.1 V < VO < (V+) – 0.1 V
AOL
Open-loop voltage gain
dB
VS = 2.7 V, VCM = V–
(V–) + 0.1 V < VO < (V+) – 0.1 V(2)
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6.5 Electrical Characteristics (continued)
For VS = (V+) –(V–) = 2.7 V to 40 V (±1.35 V to ±20 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and
VO UT = VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FREQUENCY RESPONSE
GBW
SR
Gain-bandwidth product
4.5
21
2.5
1.5
2
MHz
V/µs
Slew rate
VS = 40 V, G = +1, CL = 20 pF
To 0.01%, VS = 40 V, VSTEP = 10 V , G = +1, CL = 20 pF
To 0.01%, VS = 40 V, VSTEP = 2 V , G = +1, CL = 20 pF
To 0.1%, VS = 40 V, VSTEP = 10 V , G = +1, CL = 20 pF
To 0.1%, VS = 40 V, VSTEP = 2 V , G = +1, CL = 20 pF
G = +1, RL = 10 kΩ, CL = 20 pF
tS
Settling time
µs
1
Phase margin
60
400
°
Overload recovery time
VIN × gain > VS
ns
Total harmonic distortion
+ noise (1)
THD+N
VS = 40 V, VO = 3 VRMS, G = 1, f = 1 kHz
0.00021%
OUTPUT
VS = 40 V, RL = no load(2)
5
50
10
70
350
6
VS = 40 V, RL = 10 kΩ
VS = 40 V, RL = 2 kΩ
VS = 2.7 V, RL = no load(2)
VS = 2.7 V, RL = 10 kΩ
VS = 2.7 V, RL = 2 kΩ
300
1
Voltage output swing
from rail
Positive and negative rail headroom
mV
5
12
40
25
ISC
Short-circuit current
Capacitive load drive
±75
1000
mA
pF
CLOAD
Open-loop output
impedance
ZO
f = 1 MHz, IO = 0 A
525
Ω
POWER SUPPLY
560
685
750
Quiescent current per
amplifier
IQ
µA
VCM = V–, IO = 0 A
TA = –-55°C to 125°C
(1) Third-order filter; bandwidth = 80 kHz at –3 dB.
(2) Specified by characterization only.
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6.6 Typical Characteristics
at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩconnected to VS / 2, and CL = 10 pF (unless otherwise noted)
33
30
27
24
21
18
15
12
9
50
40
30
20
10
0
6
3
0
D001
D002
Offset Voltage Drift (µV/C)
Offset Voltage (µV)
Distribution from 60 amplifiers
Distribution from 15462 amplifiers, TA = 25°C
图6-2. Offset Voltage Drift Distribution
图6-1. Offset Voltage Production Distribution
900
400
300
200
100
0
700
500
300
100
-100
-300
-500
-700
-900
-100
-200
-300
-400
-40
-20
0
20
40
60
80
100 120 140
-40 -20
0
20
40
60
80
100 120 140
Temperature (°C)
Temperature (°C)
D004
D003
VCM = V+
图6-3. Offset Voltage vs Temperature
VCM = V–
图6-4. Offset Voltage vs Temperature
800
800
600
400
200
0
600
400
200
0
-200
-400
-600
-800
-200
-400
-600
-800
-20
-15
-10
-5
0
5
10
15
20
16
16.5
17
17.5
18
18.5
19
19.5
20
VCM
VCM
D005
D005
TA = 25°C
TA = 25°C
图6-5. Offset Voltage vs Common-Mode Voltage
图6-6. Offset Voltage vs Common-Mode Voltage (Transition
Region)
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6.6 Typical Characteristics (continued)
at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩconnected to VS / 2, and CL = 10 pF (unless otherwise noted)
800
600
400
200
0
800
600
400
200
0
-200
-400
-600
-800
-200
-400
-600
-800
-20
-15
-10
-5
0
5
10
15
20
-20
-15
-10
-5
0
5
10
15
20
VCM
VCM
D006
D007
TA = 125°C
图6-7. Offset Voltage vs Common-Mode Voltage
600
TA = –40°C
图6-8. Offset Voltage vs Common-Mode Voltage
100
90
80
70
60
50
40
30
20
10
0
200
175
150
125
100
75
Gain (dB)
Phase (ꢀ)
500
400
300
200
100
0
50
-100
-200
-300
-400
-500
-600
25
0
-25
-50
-75
-100
-10
-20
100
0
5
10
15
20
25
30
35
40
45
1k
10k
100k
Frequency (Hz)
1M
10M
Supply Voltage (V)
D008
C002
CL = 20 pF
图6-9. Offset Voltage vs Power Supply
图6-10. Open-Loop Gain and Phase vs Frequency
80
70
60
50
40
30
20
10
0
6
G = ꢀ1
G = 1
G = 10
G = 100
4.5
3
1.5
0
G = 1000
-1.5
-3
-4.5
-6
IBꢀ
IB+
IOS
-10
-20
-7.5
-20 -16 -12
-8
-4
0
4
8
12
16
20
100
1k
10k
100k
1M
10M
Common Mode Voltage (V)
Frequency (Hz)
D010
C001
图6-12. Input Bias Current vs Common-Mode Voltage
图6-11. Closed-Loop Gain vs Frequency
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6.6 Typical Characteristics (continued)
at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩconnected to VS / 2, and CL = 10 pF (unless otherwise noted)
150
125
100
75
V+
V+ ꢀ 1 V
V+ ꢀ 2 V
V+ ꢀ 3 V
V+ ꢀ 4 V
V+ ꢀ 5 V
V+ ꢀ 6 V
V+ ꢀ 7 V
V+ ꢀ 8 V
V+ ꢀ 9 V
V+ ꢀ 10 V
IBꢀ
IB+
IOS
50
25
0
-25
-50
-75
-100
-40°C
25°C
125°C
-40
-20
0
20
40
60
80
100 120 140
0
10
20
30
40
50
60
70
80
90 100
Temperature (°C)
D011
Output Current (mA)
D012
图6-13. Input Bias Current vs Temperature
图6-14. Output Voltage Swing vs Output Current (Sourcing)
Vꢀ + 8 V
Vꢀ + 7 V
Vꢀ + 6 V
Vꢀ + 5 V
Vꢀ + 4 V
Vꢀ + 3 V
Vꢀ + 2 V
Vꢀ + 1 V
Vꢀ
135
-40°C
25°C
125°C
CMRR
PSRR+
PSRRꢀ
120
105
90
75
60
45
30
15
0
0
10
20
30
40
50
60
70
80
90 100
Output Current (mA)
100
1k
10k
100k
1M
10M
D012
Frequency (Hz)
C003
图6-15. Output Voltage Swing vs Output Current (Sinking)
图6-16. CMRR and PSRR vs Frequency
135
130
125
120
170
165
160
155
150
145
140
115
PMOS (VCM ꢀ V+ ꢁ 1.5 V)
110
NMOS (VCM V+ ꢁ 1.5 V)
105
100
95
90
85
-40
-20
0
20
40
60
80
100 120 140
-40 -20
0
20
40
60
80
100 120 140
Temperature (°C)
Temperature (°C)
D015
D016
f = 0 Hz
f = 0 Hz
图6-17. CMRR vs Temperature (dB)
图6-18. PSRR vs Temperature (dB)
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6.6 Typical Characteristics (continued)
at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩconnected to VS / 2, and CL = 10 pF (unless otherwise noted)
1
0.8
0.6
0.4
0.2
0
200
100
10
-0.2
-0.4
-0.6
-0.8
-1
1
1
10
100
1k
10k
100k
Time (1s/div)
Frequency (Hz)
C017
C019
图6-20. Input Voltage Noise Spectral Density vs Frequency
图6-19. 0.1-Hz to 10-Hz Noise
-32
-40
-32
RL = 10 kꢀ
RL = 128 ꢀ
-40
RL = 2 kꢀ
RL = 604 ꢀ
RL = 128 ꢀ
RL = 604 ꢀ
RL = 2 kꢀ
RL = 10 kꢀ
-48
-48
-56
-56
-64
-64
-72
-72
-80
-80
-88
-88
-96
-96
-104
-112
-104
-112
100
1k
10k
0.001
0.01
0.1
1
10 20
Frequency (Hz)
Amplitude (Vrms)
C012
C023
BW = 80 kHz, VOUT = 1 VRMS
BW = 80 kHz, f = 1 kHz
图6-22. THD+N vs Output Amplitude
图6-21. THD+N Ratio vs Frequency
580
570
560
550
540
530
520
510
500
490
480
700
675
650
625
600
575
550
525
500
475
450
0
4
8
12
16
20
24
28
32
36
40
-40
-20
0
20
40
60
80
100 120 140
Supply Voltage (V)
Temperature (°C)
D021
D022
VCM = V–
图6-24. Quiescent Current vs Temperature
图6-23. Quiescent Current vs Supply Voltage
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6.6 Typical Characteristics (continued)
at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩconnected to VS / 2, and CL = 10 pF (unless otherwise noted)
140
135
130
125
120
115
700
650
600
550
500
450
400
350
300
250
200
150
VS = 4 V
VS = 40 V
-40 -20
0
20
40
60
80
100 120 140
100
1k
10k
100k
1M
10M
Temperature (°C)
Frequency (Hz)
D023
C013
图6-25. Open-Loop Voltage Gain vs Temperature (dB)
图6-26. Open-Loop Output Impedance vs Frequency
60
80
70
60
50
40
30
50
40
30
20
20
RISO = 0 ꢀ, Positive Overshoot
RISO = 0 ꢀ, Positive Overshoot
RISO = 0 ꢀ, Negative Overshoot
RISO = 50 ꢀ, Positive Overshoot
RISO = 50 ꢀ, Negative Overshoot
RISO = 0 ꢀ, Negative Overshoot
10
0
10
0
RISO = 50 ꢀ, Positive Overshoot
RISO = 50 ꢀ, Negative Overshoot
0
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
0
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Cap Load (pF)
Cap Load (pF)
C007
C008
G = 1, 10-mV output step
G = –1, 10-mV output step
图6-28. Small-Signal Overshoot vs Capacitive Load
图6-27. Small-Signal Overshoot vs Capacitive Load
60
Input
Output
50
40
30
20
10
Time (20us/div)
0
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Cap Load (pF)
C016
C009
VIN = ±20 V; VS = VOUT = ±17 V
图6-30. No Phase Reversal
图6-29. Phase Margin vs Capacitive Load
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6.6 Typical Characteristics (continued)
at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩconnected to VS / 2, and CL = 10 pF (unless otherwise noted)
Input
Input
Output
Output
Time (100ns/div)
Time (100ns/div)
C018
C018
C011
C005
G = –10
G = –10
图6-31. Positive Overload Recovery
图6-32. Negative Overload Recovery
Input
Output
Input
Output
Time (300ns/div)
Time (1µs/div)
C010
CL = 20 pF, G = -1, 20-mV step response
CL = 20 pF, G = 1, 20-mV step response
图6-34. Small-Signal Step Response
图6-33. Small-Signal Step Response, Rising
Input
Output
Input
Output
Time (300ns/div)
Time (300ns/div)
C005
CL = 20 pF, G = 1
CL = 20 pF, G = 1
图6-35. Large-Signal Step Response (Rising)
图6-36. Large-Signal Step Response (Falling)
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6.6 Typical Characteristics (continued)
at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩconnected to VS / 2, and CL = 10 pF (unless otherwise noted)
100
80
60
Input
Output
40
20
Sourcing
Sinking
0
-20
-40
-60
-80
-100
Time (2µs/div)
-40 -20
0
20
40
60
80
100 120 140
Temperature (°C)
C021
D014
CL = 20 pF, G = –1
图6-38. Short-Circuit Current vs Temperature
图6-37. Large-Signal Step Response
45
40
35
30
25
20
15
10
5
-50
-60
VS = 40 V
VS = 30 V
VS = 15 V
VS = 2.7 V
-70
-80
-90
-100
-110
-120
-130
0
1k
100
1k
10k
100k
1M
10M
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
C014
C020
图6-40. Channel Separation vs Frequency
图6-39. Maximum Output Voltage vs Frequency
110
100
90
80
70
60
50
40
1M
10M
100M
Frequency (Hz)
1G
C004
图6-41. EMIRR (Electromagnetic Interference Rejection Ratio) at Inputs vs Frequency
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7 Detailed Description
7.1 Overview
The OPA4H199-SEP is a new 40-V general purpose operational amplifier.
This device offers excellent DC precision and AC performance, including rail-to-rail input/output, low offset (±125
µV, typ), low offset drift (±0.3 µV/°C, typ), and 4.5-MHz bandwidth.
Unique features, such as differential and common-mode input-voltage range to the supply rail, high output
current (±75 mA) and high slew rate (21 V/µs), make the OPA4H199-SEP a robust, high-performance
operational amplifier for high-voltage space applications.
7.2 Functional Block Diagram
+
NCH Input
Stage
–
IN+
IN-
+
–
40-V
OUT
Output
Stage
Differential
MUX-Friendly
Front End
Slew
Boost
+
PCH Input
Stage
–
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7.3 Feature Description
7.3.1 Input Protection Circuitry
The OPA4H199-SEP uses a unique input architecture to eliminate the requirement for input protection diodes
but still provides robust input protection under transient conditions. 图 7-1 shows conventional input diode
protection schemes that are activated by fast transient step responses and introduce signal distortion and
settling time delays because of alternate current paths, as shown in 图 7-2. For low-gain circuits, these fast-
ramping input signals forward-bias back-to-back diodes, causing an increase in input current and resulting in
extended settling time.
V+
V+
VIN+
VIN+
VOUT
VOUT
~0.7 V
40 V
VINꢀ
VINꢀ
Vꢀ
Vꢀ
Provides Full 40-V
Differential Input Range
Conventional Input Protection
Limits Differential Input Range
图7-1. OPA4H199-SEP Input Protection Does Not Limit Differential Input Capability
1
Ron_mux
Vn = 10 V
RFILT
10 V
Sn
D
1
2
~œ9.3 V
10 V
CFILT
CS
CD
VINœ
2
Ron_mux
Sn+1
Vn+1 = œ10 V RFILT
œ10 V
~0.7 V
VOUT
CFILT
CS
Idiode_transient
VIN+
œ10 V
Input Low-Pass Filter
Simplified Mux Model
Buffer Amplifier
图7-2. Back-to-Back Diodes Create Settling Issues
The OPA4H199-SEP provides a true high-impedance differential input capability for high-voltage applications
using a patented input protection architecture that does not introduce additional signal distortion or delayed
settling time, making the device an excellent choice as op amp for multichannel, high-switched, input
applications. The OPA4H199-SEP tolerates a maximum differential swing (voltage between inverting and non-
inverting pins of the op amp) of up to 40 V, making the device good for use as a comparator or in applications
with fast-ramping input signals such as data-acquisition systems; see the TI TechNote MUX-Friendly Precision
Operational Amplifiers for more information.
7.3.2 EMI Rejection
The OPA4H199-SEP uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI
from sources such as wireless communications and densely-populated boards with a mix of analog signal chain
and digital components. EMI immunity can be improved with circuit design techniques; the OPA4H199-SEP
benefits from these design improvements. Texas Instruments has developed the ability to accurately measure
and quantify the immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to
6 GHz. 图 7-3 shows the results of this testing on the OPA4H199-SEP. 表 7-1 shows the EMIRR IN+ values for
the OPA4H199-SEP at particular frequencies commonly encountered in real-world applications. The EMI
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Rejection Ratio of Operational Amplifiers application report contains detailed information on the topic of EMIRR
performance as it relates to op amps and is available for download from www.ti.com.
110
100
90
80
70
60
50
40
1M
10M
100M
1G
Frequency (Hz)
C004
图7-3. EMIRR Testing
表7-1. OPA4H199-SEP EMIRR IN+ for Frequencies of Interest
FREQUENCY
APPLICATION OR ALLOCATION
EMIRR IN+
Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF)
applications
400 MHz
73.2 dB
Global system for mobile communications (GSM) applications, radio communication, navigation,
GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications
900 MHz
1.8 GHz
2.4 GHz
3.6 GHz
5 GHz
82.5 dB
89.7 dB
93.9 dB
95.7 dB
98.0 dB
GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz)
802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications, industrial, scientific and
medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)
Radiolocation, aero communication and navigation, satellite, mobile, S-band
802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite
operation, C-band (4 GHz to 8 GHz)
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7.3.3 Thermal Protection
The internal power dissipation of any amplifier causes the internal (junction) temperature to rise. This
phenomenon is called self heating. The absolute maximum junction temperature of the OPA4H199-SEP is
150°C. Exceeding this temperature causes damage to the device. The OPA4H199-SEP has a thermal protection
feature that reduces damage from self heating. The protection works by monitoring the temperature of the device
and turning off the op amp output drive for temperatures above 170°C. 图 7-4 shows an application example for
the OPA4H199-SEP that has significant self heating because of the power dissipation (0.81 W). Thermal
calculations indicate that for an ambient temperature of 65°C, the device junction temperature can reach 177°C.
The actual device, however, turns off the output drive to recover towards a safe junction temperature. 图 7-4
shows how the circuit behaves during thermal protection. During normal operation, the device acts as a buffer so
the output is 3 V. When self heating causes the device junction temperature to increase above the internal limit,
the thermal protection forces the output to a high-impedance state and the output is pulled to ground through
resistor RL. If the condition that caused excessive power dissipation is not removed, then the amplifier can
oscillate between a shutdown and enabled state until the output fault is corrected.
3 V
TA = 65°C
30 V
PD = 0.81W
JA = 138.7°C/W
0 V
TJ = 138.7°C/W × 0.81W + 65°C
TJ = 177.3°C (expected)
ꢀ
ꢁ
170ºC
IOUT = 30 mA
+
3 V
–
RL
100
+
–
VIN
3 V
图7-4. Thermal Protection
If the device continues to operate at high junction temperatures with high output power over a long period of
time, regardless if the device is or is not entering thermal shutdown, the thermal dissipation of the device can
slowly degrade performance of the device and eventually cause catastrophic destruction. Designers must be
careful to limit output power of the device at high temperatures, or control ambient and junction temperatures
under high output power conditions.
7.3.4 Capacitive Load and Stability
The OPA4H199-SEP features a resistive output stage capable of driving moderate capacitive loads, and by
leveraging an isolation resistor, the device can easily be configured to drive large capacitive loads. Increasing
the gain enhances the ability of the amplifier to drive greater capacitive loads; see 图 7-5 and 图 7-6. The
particular op amp circuit configuration, layout, gain, and output loading are some of the factors to consider when
establishing whether an amplifier can be stable in operation.
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80
70
60
50
40
30
20
10
0
60
50
40
30
20
10
0
RISO = 0 ꢀ, Positive Overshoot
RISO = 0 ꢀ, Negative Overshoot
RISO = 50 ꢀ, Positive Overshoot
RISO = 50 ꢀ, Negative Overshoot
RISO = 0 ꢀ, Positive Overshoot
RISO = 0 ꢀ, Negative Overshoot
RISO = 50 ꢀ, Positive Overshoot
RISO = 50 ꢀ, Negative Overshoot
0
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
0
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Cap Load (pF)
Cap Load (pF)
C008
C007
图7-5. Small-Signal Overshoot vs Capacitive Load 图7-6. Small-Signal Overshoot vs Capacitive Load
(10-mV Output Step, G = 1)
(10-mV Output Step, G = –1)
For additional drive capability in unity-gain configurations, improve capacitive load drive by inserting a small
resistor, RISO, in series with the output, as shown in 图 7-7. This resistor significantly reduces ringing and
maintains DC performance for purely capacitive loads. However, if a resistive load is in parallel with the
capacitive load, then a voltage divider is created, thus introducing a gain error at the output and slightly reducing
the output swing. The error introduced is proportional to the ratio RISO / RL, and is generally negligible at low
output levels. A high capacitive load drive makes the OPA4H199-SEP an excellent choice for applications such
as reference buffers, MOSFET gate drives, and cable-shield drives. The circuit shown in 图7-7 uses an isolation
resistor, RISO, to stabilize the output of an op amp. RISO modifies the open-loop gain of the system for increased
phase margin.
+Vs
Vout
Riso
+
Cload
+
Vin
-Vs
œ
图7-7. Extending Capacitive Load Drive With the OPA4H199-SEP
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7.3.5 Common-Mode Voltage Range
The OPA4H199-SEP is a 40-V, true rail-to-rail input operational amplifier with an input common-mode range that
extends 100 mV beyond either supply rail. This wide range is achieved with paralleled complementary N-channel
and P-channel differential input pairs, as shown in 图7-8. The N-channel pair is active for input voltages close to
the positive rail, typically (V+) –1 V to 100 mV above the positive supply. The P-channel pair is active for inputs
from 100 mV below the negative supply to approximately (V+) – 2 V. There is a small transition region, typically
(V+) – 2 V to (V+) – 1 V in which both input pairs are on. This transition region can vary modestly with process
variation, and within this region PSRR, CMRR, offset voltage, offset drift, noise, and THD performance can be
degraded compared to operation outside this region.
图6-5 shows this transition region for a typical device in terms of input voltage offset in more detail.
For more information on common-mode voltage range and PMOS/NMOS pair interaction, see Op Amps With
Complementary-Pair Input Stages application note.
V+
IN-
PMOS
PMOS
NMOS
IN+
NMOS
V-
图7-8. Rail-to-Rail Input Stage
7.3.6 Phase Reversal Protection
The OPA4H199-SEP family has internal phase-reversal protection. Many op amps exhibit phase reversal when
the input is driven beyond the linear common-mode range. This condition is most often encountered in non-
inverting circuits when the input is driven beyond the specified common-mode voltage range, causing the output
to reverse into the opposite rail. The OPA4H199-SEP is a rail-to-rail input op amp; therefore, the common-mode
range can extend beyond the rails. Input signals beyond the rails do not cause phase reversal; instead, the
output limits into the appropriate rail. This performance is shown in 图 7-9. For more information on phase
reversal, see Op Amps With Complementary-Pair Input Stages application note.
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Input
Output
Time (20us/div)
C016
图7-9. No Phase Reversal
7.3.7 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress
(EOS). These questions tend to focus on the device inputs, but can involve the supply voltage pins or even the
output pin. Each of these different pin functions have electrical stress limits determined by the voltage
breakdown characteristics of the particular semiconductor fabrication process and specific circuits connected to
the pin. Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them
from accidental ESD events both before and during product assembly.
Having a good understanding of this basic ESD circuitry and the relevance to an electrical overstress event is
helpful. 图 7-10 shows an illustration of the ESD circuits contained in the OPA4H199-SEP (indicated by the
dashed line area). The ESD protection circuitry involves several current-steering diodes connected from the
input and output pins and routed back to the internal power-supply lines, where the diodes meet at an absorption
device or the power-supply ESD cell, internal to the operational amplifier. This protection circuitry is intended to
remain inactive during normal circuit operation.
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TVS
RF
+VS
VDD
100
100
R1
RS
IN–
IN+
–
+
Power-Supply
ESD Cell
RL
ID
+
VIN
–
VSS
–VS
TVS
图7-10. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
An ESD event is very short in duration and very high voltage (for example; 1 kV, 100 ns), whereas an EOS event
is long duration and lower voltage (for example; 50 V, 100 ms). The ESD diodes are designed for out-of-circuit
ESD protection (that is, during assembly, test, and storage of the device before being soldered to the PCB).
During an ESD event, the ESD signal is passed through the ESD steering diodes to an absorption circuit
(labeled ESD power-supply circuit). The ESD absorption circuit clamps the supplies to a safe level.
Although this behavior is necessary for out-of-circuit protection, excessive current and damage is caused if
activated in-circuit. A transient voltage suppressors (TVS) can be used to prevent against damage caused by
turning on the ESD absorption circuit during an in-circuit ESD event. Using the appropriate current limiting
resistors and TVS diodes allows for the use of device ESD diodes to protect against EOS events.
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7.3.8 Overload Recovery
Overload recovery is defined as the time required for the op amp output to recover from a saturated state to a
linear state. The output devices of the op amp enter a saturation region when the output voltage exceeds the
rated operating voltage, either due to the high input voltage or the high gain. After the device enters the
saturation region, the charge carriers in the output devices require time to return back to the linear state. After
the charge carriers return back to the linear state, the device begins to slew at the specified slew rate. Thus, the
propagation delay in case of an overload condition is the sum of the overload recovery time and the slew time.
The overload recovery time for the OPA4H199-SEP is approximately 400 ns.
7.3.9 Typical Specifications and Distributions
Designers often have questions about a typical specification of an amplifier to design a more robust circuit. Due
to natural variation in process technology and manufacturing procedures, every specification of an amplifier
exhibits some amount of deviation from the proper value, like an input offset voltage of the amplifier. These
deviations often follow Gaussian (bell curve), or normal distributions, and circuit designers can leverage this
information to guardband their system, even when there is not a minimum or maximum specification in 节6.5.
0.00312% 0.13185%
0.13185% 0.00312%
0.00002%
0.00002%
2.145% 13.59% 34.13% 34.13% 13.59% 2.145%
1
1 1 1 1 1 1 1 1
1
1
1
ꢀ-61 ꢀ-51 ꢀ-41 ꢀ-31 ꢀ-21 ꢀ-1
ꢀ+1 ꢀ+21 ꢀ+31 ꢀ+41 ꢀ+51 ꢀ+61
ꢀ
图7-11. Ideal Gaussian Distribution
图 7-11 shows an example distribution, where µ, or mu, is the mean of the distribution, and where σ, or sigma,
is the standard deviation of a system. For a specification that exhibits this kind of distribution, approximately two-
thirds (68.26%) of all units can be expected to have a value within one standard deviation, or one sigma, of the
mean (from µ –σto µ + σ).
Depending on the specification, values listed in the typical column of the 节 6.5 are represented in different
ways. As a general rule of thumb, if a specification naturally has a nonzero mean (for example, like gain
bandwidth), then the typical value is equal to the mean (µ). However, if a specification naturally has a mean near
zero (like input offset voltage), then the typical value is equal to the mean plus one standard deviation (µ + σ) to
most accurately represent the typical value.
You can use this chart to calculate approximate probability of a specification in a unit; for example, for
OPA4H199-SEP, the typical input voltage offset is 125 µV, so 68.2% of all OPA4H199-SEP devices are expected
to have an offset from –125 µV to 125 µV. At 4 σ (±500 µV), 99.9937% of the distribution has an offset voltage
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less than ±500 µV, which means 0.0063% of the population is outside of these limits, which corresponds to
about 1 in 15,873 units.
TI verifes specifications with a value in the minimum or maximum column, and units outside these limits are
removed from production material. For example, the OPA4H199-SEP family has a maximum offset voltage of
895 µV at 25°C, and even though this corresponds to more than 5 σ (≈1 in 1.7 million units), which is
extremely unlikely, TI specifies that any unit with larger offset than 895 µV is removed from production material.
For specifications with no value in the minimum or maximum column, consider selecting a sigma value of
sufficient guardband for your application, and design worst-case conditions using this value. For example, the 6-
σvalue corresponds to about 1 in 500 million units, which is an extremely unlikely chance, and can be an option
as a wide guardband to design a system around. In this case, the OPA4H199-SEP family does not have a
maximum or minimum for offset voltage drift, but based on 图6-2 and the typical value of 0.3 µV/°C in the 节6.5,
the calcuation results in a 6-σ value for offset voltage drift is about 1.8 µV/°C. When designing for worst-case
system conditions, this value can be used to estimate the worst possible offset across temperature without
having an actual minimum or maximum value.
However, process variation and adjustments over time can shift typical means and standard deviations, and
unless there is a value in the minimum or maximum specification column, the performance of a device is not
verified. This information must be used only to estimate the performance of a device.
7.4 Device Functional Modes
The OPA4H199-SEP has a single functional mode and is operational when the power-supply voltage is greater
than 2.7 V (±1.35 V). The maximum power supply voltage for the OPA4H199-SEP is 40 V (±20 V).
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8 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The OPA4H199-SEP family offers excellent DC precision and AC performance. These devices operate up to 40-
V supply rails and offer true rail-to-rail input/output, low offset voltage and offset voltage drift, as well as 4.5-MHz
bandwidth and high output drive. These features make the OPA4H199-SEP a robust, high-performance
operational amplifier for high-voltage industrial applications.
8.2 Typical Applications
8.2.1 Low-Side Current Measurement
图 8-1 shows the OPA4H199-SEP configured in a low-side current sensing application. For a full analysis of the
circuit shown in 图 8-1 including theory, calculations, simulations, and measured data, see TI Precision Design
TIPD129, 0-A to 1-A Single-Supply Low-Side Current-Sensing Solution.
VCC
5 V
LOAD
+
VOUT
–
RSHUNT
ILOAD
100 m
LM7705
RF
360 k
RG
7.5 k
图8-1. OPA4H199-SEP in a Low-Side, Current-Sensing Application
8.2.1.1 Design Requirements
The design requirements for this design are:
• Load current: 0 A to 1 A
• Output voltage: 4.9 V
• Maximum shunt voltage: 100 mV
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8.2.1.2 Detailed Design Procedure
The transfer function of the circuit in 图8-1 is given in 方程式1.
VOUT = ILOAD × RSHUNT × Gain
(1)
The load current (ILOAD) produces a voltage drop across the shunt resistor (RSHUNT). The load current is set from
0 A to 1 A. To keep the shunt voltage below 100 mV at maximum load current, the largest shunt resistor is
defined using 方程式2.
V
SHUNT_MAX
100 mV
1 A
R
=
=
= 100 mΩ
(2)
SHUNT
I
LOAD_MAX
Using 方程式 2, RSHUNT is calculated to be 100 mΩ. The voltage drop produced by ILOAD and RSHUNT is
amplified by the OPA4H199-SEP to produce an output voltage of 0 V to 4.9 V. The gain needed by the
OPA4H199-SEP to produce the necessary output voltage is calculated using 方程式3.
V
− V
− V
OUT_MAX
OUT
MIN
Gain =
(3)
V
IN_MAX
IN_MIN
Using 方程式 3, the required gain is calculated to be 49 V/V, which is set with resistors RF and RG. 方程式 4 is
used to size the resistors, RF and RG, to set the gain of the OPA4H199-SEP to 49 V/V.
R
F
Gain = 1 +
(4)
R
G
Choosing RF as 360 kΩ, RG is calculated to be 7.5 kΩ. RF and RG were chosen as 360 kΩ and 7.5 kΩ
because they are standard value resistors that create a 49:1 ratio. Other resistors that create a 49:1 ratio can
also be used. 图8-2 shows the measured transfer function of the circuit shown in 图8-1.
8.2.1.3 Application Curve
5
4
3
2
1
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
ILOAD (A)
1
图8-2. Low-Side, Current-Sense, Transfer Function
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8.3 Power Supply Recommendations
The OPA4H199-SEP is specified for operation from 2.7 V to 40 V (±1.35 V to ±40 V); many specifications apply
from –55°C to 125°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in Typical Characteristics.
CAUTION
Supply voltages larger than 40 V can permanently damage the device; see 节6.1.
Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, refer to Layout.
8.4 Layout
8.4.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp itself.
Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to
the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds paying attention to the flow of the ground current.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed
to in parallel with the noisy trace.
• Place the external components as close to the device as possible. As illustrated in 图8-4, keeping RF and
RG close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
• Cleaning the PCB following board assembly is recommended for best performance.
• Any precision integrated circuit can experience performance shifts due to moisture ingress into the plastic
package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to
remove moisture introduced into the device packaging during the cleaning process. A low temperature, post
cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
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8.4.2 Layout Example
VIN
+
VOUT
RG
RF
图8-3. Schematic Representation
Place components
close to device and to
each other to reduce
parasitic errors.
OUT 1
Use low-ESR,
ceramic bypass
capacitor. Place as
close to the device
as possible.
VS+
GND
OUT1
V+
RF
RG
OUT 2
GND
IN1–
IN1+
V–
OUT2
RF
RG
IN2–
IN2+
GND
VIN 1
VIN 2
Keep input traces short
and run the input traces
as far away from
the supply lines
Use low-ESR,
ceramic bypass
capacitor. Place as
close to the device
as possible.
GND
VS–
Ground (GND) plane on another layer
as possible.
图8-4. Operational Amplifier Board Layout for Noninverting Configuration
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9 Device and Documentation Support
9.1 Device Support
9.1.1 Development Support
9.1.1.1 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a
free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range
of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain
analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
备注
These files require that either the TINA software (from DesignSoft™) or TINA-TI software be installed.
Download the free TINA-TI software from the TINA-TI folder.
9.2 Documentation Support
9.2.1 Related Documentation
For related documentation, see the following:
Texas Instruments, Analog Engineer's Circuit Cookbook: Amplifiers solution guide.
Texas Instruments, AN31 Amplifier Circuit Collection application note.
Texas Instruments, MUX-Friendly Precision Operational Amplifiers application brief.
Texas Instruments, EMI Rejection Ratio of Operational Amplifiers application report.
Texas Instruments, Op Amps With Complementary-Pair Input Stages application note.
9.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
9.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
9.5 Trademarks
TINA-TI™ is a trademark of Texas Instruments, Inc and DesignSoft, Inc.
TINA™ and DesignSoft™ are trademarks of DesignSoft, Inc.
TI E2E™ is a trademark of Texas Instruments.
Bluetooth® is a registered trademark of Bluetooth SIG, Inc.
所有商标均为其各自所有者的财产。
9.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
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9.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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21-Jul-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA4H199MDYYTSEP
V62/21615-02XE
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
DYY
DYY
14
14
250
250
RoHS & Green
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-55 to 125
4H199SEP
4H199SEP
Samples
Samples
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
21-Jul-2023
Addendum-Page 2
PACKAGE OUTLINE
SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE
DYY0014A
C
3.36
3.16
SEATING PLANE
PIN 1 INDEX
AREA
A
0.1 C
12X 0.5
14
1
4.3
4.1
NOTE 3
2X
3
7
8
0.31
0.11
14X
0.1
C A
B
1.1 MAX
2.1
1.9
B
0.2
0.08
TYP
SEE DETAIL A
0.25
GAUGE PLANE
0°- 8°
0.1
0.0
0.63
0.33
DETAIL A
TYP
4224643/B 07/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed
0.15 per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.50 per side.
5. Reference JEDEC Registration MO-345, Variation AB
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EXAMPLE BOARD LAYOUT
SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE
DYY0014A
SYMM
14X (1.05)
1
14
14X (0.3)
SYMM
12X (0.5)
8
7
(R0.05) TYP
(3)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
NON- SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4224643/B 07/2021
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE
DYY0014A
SYMM
14X (1.05)
1
14
14X (0.3)
SYMM
12X (0.5)
8
7
(R0.05) TYP
(3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 20X
4224643/B 07/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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