OPA521IRGWT [TI]
2.5A 窄带线路驱动器 | RGW | 20 | -40 to 125;
| 型号： | OPA521IRGWT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2.5A 窄带线路驱动器 | RGW | 20 | -40 to 125 驱动 驱动器 |
| 文件： | 总33页 (文件大小：2123K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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OPA521
ZHCSI51A –MAY 2018–REVISED JUNE 2018
OPA521 2.5A 窄带线路驱动器
1 特性
3 说明
1
•
•
•
支持：
OPA521 是一种线路驱动器功率放大器，符合
CENELEC 频带 A、B、C、D 和 ARIB STD-T84、
FCC 第 15 部分的电力线通信 (PLC) 传导发射要求。
此器件在高电流、低阻抗且具有无功负载的线路上最高
可提供 2.5A 电流。OPA521 具备优化的内部保护结
构，因此它只需极少的外部保护组件，实现具有经济效
益且节省空间的系统。
–
–
–
CENELEC 频带 A、B、C、D
ARIB STD-T84、FCC
FSK、SFSK 和 NB-OFDM
符合：
–
–
–
EN50065-1、-2、-3、-7
FCC 第 15 部分
ARIB STD-T84
OPA521 带宽为 3.8MHz，可提供 –7V/V 的闭环增
益。此单片集成型电路为电源线通信应用提供 高可靠
性。
标准：
–
G3、PRIME、P1901.2、ITU-G.hnem
•
•
具有集成式热保护和过流保护功能的线路驱动器
引脚可选静态电流消耗：
OPA521 线路驱动器由 7V 至 24V 电压的单电源供
电。在典型负载电流情况下（IOUT = 2.5A，最大值），
宽输出摆幅能够以 24V 的标称电源电压提供 10VPP 电
压。
–
–
待机模式时电流为 58 µA（典型值）
CENELEC 频带 A、B、C、D 的电流为 51mA
（典型值）
–
FCC、ARIB STD-T84 的电流为 78mA（典型
值）
此器件具有过热和短路保护。故障检测标志显示电流和
热限值。提供有一个关断引脚，利用该引脚可将器件置
于低功耗状态，消耗电流为 58µA（典型值）。
•
•
封装：5mm × 5mm 20 引脚 VQFN
工作结温范围：
TA = –40°C 至 +125°C
OPA521 可提供表面贴装式 5mm × 5mm 20 引脚
VQFN (RGW) 封装。此器件可在 -40°C 至 +125°C 的
扩展工业结温范围内正常运行。
2 应用
•
•
•
•
•
电能质量监测仪
器件信息(1)
商用网络和服务器 PSU
照明
器件编号
OPA521
封装
VQFN (20)
封装尺寸（标称值）
5.00mm × 5.00mm
太阳能电弧保护
中央逆变器
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
OPA521 方框图
V+
126 kꢀ
GAIN_SET
18 kꢀ
-IN
-
VOUT
+IN
+
Limits & Alarms
GND
IFLAG TFLAG EN
ILIM
IQSET
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SBOS872
OPA521
ZHCSI51A –MAY 2018–REVISED JUNE 2018
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 12
Application and Implementation ........................ 13
8.1 Application Information............................................ 13
8.2 Typical Application .................................................. 13
Power Supply Recommendations...................... 18
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics.......................................... 5
6.6 Electrical Characteristics: Digital.............................. 6
6.7 Electrical Characteristics: Power Supply ................. 6
6.8 Typical Characteristics.............................................. 7
Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagram ....................................... 11
7.3 Feature Description................................................. 11
8
9
10 Layout................................................................... 21
10.1 Layout Guidelines ................................................. 21
10.2 Layout Example .................................................... 23
11 器件和文档支持 ..................................................... 24
11.1 器件支持 ............................................................... 24
11.2 文档支持 ............................................................... 24
11.3 接收文档更新通知 ................................................. 24
11.4 社区资源................................................................ 24
11.5 商标....................................................................... 24
11.6 静电放电警告......................................................... 24
11.7 术语表 ................................................................... 24
12 "机械、封装和可订购信息..................................... 24
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (May 2018) to Revision A
Page
•
首次发布生产数据数据表 ....................................................................................................................................................... 1
2
Copyright © 2018, Texas Instruments Incorporated
OPA521
www.ti.com.cn
ZHCSI51A –MAY 2018–REVISED JUNE 2018
5 Pin Configuration and Functions
RGW Package
20-Pin VQFN With Exposed Thermal Pad
Top View
V+
NC
NC
NC
NC
1
2
3
4
5
15
14
13
12
11
IQSET
TFLAG
IFLAG
ILIM
Thermal
Pad
EN
Not to scale
NC - no internal connection
Pin Functions
PIN
I/O
DESCRIPTION
NAME
EN
NO.
11
I
I
Enables the amplifier (active high, high enables the OPA521)
Connect an external resistor to Gain_Set and -IN to increase the gain beyond -7 V/V
Ground
GAIN_SET
GND
IFLAG
ILIM
8
16, 17
13
—
O
I
Current limit warning flag (open-drain, active high, high signifies current limit condition)
Resistor programmable current limit
12
+IN
9
I
Non-inverting input (connect to a voltage equal to (V+)/2)
Inverting input for closed loop gain = –7 V/V
–IN
7
I
Quiescent current select (active high, high configures the OPA521 to operate in FCC/ARIB
bands, low configures the OPA521 to operate in CENELEC Bands A, B, C, D)
IQSET
NC
15
I
2, 3, 4, 5, 6,
10
—
No internal connection
TFLAG
V+
14
O
—
O
Thermal limit warning flag (open-drain, active high, high signifies thermal limit condition)
1, 20
18. 19
Positive power supply
VOUT
Output
Thermal pad
—
Must be soldered to PCB and connected to GND
Copyright © 2018, Texas Instruments Incorporated
3
OPA521
ZHCSI51A –MAY 2018–REVISED JUNE 2018
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
26
UNIT
Supply voltage, V+
Signal input pins
Pins 1, 20
V
Pins 7, 8, 9, 12
Pins 11, 15
–0.4
–0.4
(V+) + 0.4
3.3
Voltage(2)
Current(2)
Voltage
V
mA
V
Pins 7, 8, 9, 11, 12,
15
±10
Pins 18, 19
Pins 13, 14
–0.4
–0.4
(V+) + 0.4
3.3
Signal output terminals
Current; short-circuit
to GND
Pins 13, 14, 18, 19
Continuous
Operating junction temperature(3)
–40
–55
125
150
°C
°C
Storage temperature, Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.4 V beyond the supply rails should
be current limited to 10 mA or less.
(3) The device automatically goes into shutdown above +140℃ junction temperature
6.2 ESD Ratings
VALUE
±1500
±1000
UNIT
V
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
24
UNIT
Supply voltage, V+
Output current, DC(1)
7
V
A
1.9
Operating junction temperature
–40
125
°C
(1) Under safe operating conditions. See Power Amplifier Stress and Power Handling Limitations safe operating area (SOA) information.
6.4 Thermal Information
OPA521
THERMAL METRIC(1)
RGW (QFN)
20 PINS
33.0
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
24.4
12.7
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
ΨJB
12.7
RθJC(bot)
3.4
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2018, Texas Instruments Incorporated
OPA521
www.ti.com.cn
ZHCSI51A –MAY 2018–REVISED JUNE 2018
6.5 Electrical Characteristics
At TCASE = 25°C, V+ = 15 V, IN+ = (V+) / 2, RLOAD = 50 Ω unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
NOISE
CEN-A
35 kHz to 95 kHz
45
32
µVRMS
µVRMS
µVRMS
µVRMS
µVRMS
µVRMS
µVRMS
CEN-B
95 kHz to 125 kHz
125 kHz to 140 kHz
140 kHz to 148 kHz
35 kHz to 420 kHz
35 kHz to 125 kHz
150 kHz to 490 kHz
CEN-C
23
Integrated output
noise
CEN-D
16.5
114
55
ARIB STD-T84
FCC-LOW
G3-FCC
107
INPUT
(GND +
0.4)/7
(V+ –
0.4)/7
Input voltage range, IN-
Input impedance
For linear operation, +IN = V+/2
V
18
kΩ
FREQUENCY RESPONSE
BW
SR
Bandwidth
ILOAD = 0 mA
3.82
75
MHz
V/µs
kHz
Slew rate
V+ = 24 V, VOUT = 20-V step
V+ = 24 V, VOUT = 15 VPP
RTI, DC
Full-power bandwidth
800
94
80
PSRR
Power-supply rejection ratio
dB
RTI, DC to f = 50 kHz
See Typical Curves
OUTPUT
IO = 200-mA sourcing, 1-ms pulse
IO = 1.5-A sourcing, 1-ms pulse
IO = 200 mA sinking, 1-ms pulse
IO = 1.5-A sinking, 1-ms pulse
0.5
2.25
0.5
V
V
V
V
From V+
Voltage output
swing
VO
From GND
1.5
See Recommended Operating
Max continuous current, DC
ILIM (pin 12) connected to ground
A
Conditions
Output resistance
Disabled output impedance
Max output
IO = 1.9 A, f = 500 kHz
f = 100 kHz
0.1
Ω
145 || 125
kΩ || pF
Resistor-selectable
ILIM (pin 12) connected to ground
2.5
A
current
GAIN
G
Nominal gain
Gain error
VOUT/VIN
–7
V/V
GE
TJ = -40°C to +125°C
TJ = -40°C to +125°C
–2%
0.1%
±5
2%
Gain error drift
ppm/°C
THERMAL SHUTDOWN
Junction temperature at shutdown
140
10
°C
°C
°C
Hysteresis
Return to normal operation
130
Copyright © 2018, Texas Instruments Incorporated
5
OPA521
ZHCSI51A –MAY 2018–REVISED JUNE 2018
www.ti.com.cn
6.6 Electrical Characteristics: Digital
At TCASE = 25°C, V+ = 15 V, IN+ = (V+) / 2, RLOAD = 50 Ω unless otherwise noted.
PARAMETER
DIGITAL INPUTS (ENABLE, IQSET)
Leakage input current
TEST CONDITIONS
MIN
–1
TYP
MAX
UNIT
GND ≤ VIN ≤ 3.3
0.01
2
1
3.3
0.8
µA
V
VIH
VIL
High-level input voltage
Low-level input voltage
GND
V
EN pin high
2 < EN < 3.3
EN < 0.8
Device in normal operation
Device in shutdown
EN pin function
(active high)
EN pin low
IQSET pin high
IQSET pin low
IQSET > 2
IQSET < 0.8
Device in FCC/ARIB mode (IQ = 78 mA (typ))
Device in CENELEC mode (IQ = 51 mA (typ))
IQSET pin function
(active high)
DIGITAL OUTPUTS (TFLAG, IFLAG)
IOH
VOL
IOL
High-level output current
Low-level output voltage
Low-level output current
VOH = 3.3 V
1
µA
V
IOL = 4 mA
0.4
VOL = 400 mV
4
mA
TFLAG pin high
TFLAG pin low
IFLAG pin high
IFLAG pin low
TFLAG sink high < 1 µA
TFLAG < 0.4 V
IFLAG sink high < 1 µA
IFLAG < 0.4 V
Device is in thermal shutdown
Device is not in thermal shutdown
Device is in current limit
TFLAG (active high,
open-drain)
IFLAG (active high,
open-drain)
Device is not in current limit
SHUTDOWN MODE TIMING
Enable time
SD pin transitions from low to high
SD pin transitions from high to low
3
2
ms
ms
Disable time
6.7 Electrical Characteristics: Power Supply
At TCASE = 25°C, V+ = 15 V, IN+ = (V+) / 2, RLOAD = 50 Ω unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OPERATING SUPPLY RANGE
V+
Power amplifier
7
15
24
V
QUIESCENT CURRENT (ENABLE pin high)
FCC/ARIB mode
CENELEC mode
IO = 0 A, IQSET pin high
IO = 0 A, IQSET pin low
64
41
78
51
88
61
mA
mA
IQ
SHUTDOWN (ENABLE pin low)
EN Power amplifier
EN pin low
58
130
µA
6
版权 © 2018, Texas Instruments Incorporated
OPA521
www.ti.com.cn
ZHCSI51A –MAY 2018–REVISED JUNE 2018
6.8 Typical Characteristics
At TCASE = +25°C, V+ = 24 V, IN+ = (V+)/2, RLOAD = 50 Ω unless otherwise noted.
120
100
80
60
40
20
0
30
20
10
0
G = -7
-10
-20
100
1k
10k
100k
1M
10M
1
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
D004
D005
图 1. Closed Loop Gain vs Frequency
图 2. PSRR+ vs Frequency
0.1
-60
1
-40
FCC/ARIB 10KW
FCC/ARIB 50W
CENELEC 10KW
CENELEC 50W
0.1
-60
0.01
0.001
-80
0.01
-80
-100
FCC/ARIB 10KW
FCC/ARIB 50W
CENELEC 10KW
CENELEC 50W
0.001
-100
0.0001
-120
0.0001
-120
10
100
1k
10k
10m
100m
1
Frequency (Hz)
Output Amplitude (VRMS
)
D006
D007
VOUT = 7 VRMS
图 3. THD+N vs Frequency
ƒ = 1 kHz
图 4. THD+N vs Output Amplitude
100
10
1
10
1
0.1
0.1
100m
0.01
100m
1
10
100
1k
10k
100k
1M
1
10
100
1k
10k
100k
1M
Frequency (Hz)
Frequency (Hz)
D008
D009
图 5. Input Voltage Noise Spectral Density
图 6. Input Current Noise Density
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OPA521
ZHCSI51A –MAY 2018–REVISED JUNE 2018
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Typical Characteristics (接下页)
At TCASE = +25°C, V+ = 24 V, IN+ = (V+)/2, RLOAD = 50 Ω unless otherwise noted.
3
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
0
10
20
30
40
50
60
70
80
90 100
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
Rset (kW)
Output Current (A)
D018
D034
V+ = 15 V
图 7. Maximum Output Current Limit vs RSET
图 8. Output Swing from V+ vs Output Current (Sourcing)
2
1.8
1.6
1.4
1.2
1
35
Vs=24 V
Vs=15 V
Vs=7 V
30
25
20
15
10
5
0.8
0.6
0.4
0.2
0
0
0
0.25 0.5 0.75
1
1.25 1.5 1.75
2
2.25 2.5
1
10
100
1k
10k
100k
1M
10M
Output Current (A)
Frequency (Hz)
D033
D035
V+ = 15 V
图 9. Output Swing from GND vs Output Current (Sinking)
图 10. Maximum Output Voltage vs Frequency
Input
Input
Rload = 50W
Rload = 10KW
Rload = 50W
Rload = 10KW
Time (10 ms/div)
Time (10ms/div)
D020
D021
图 11. Small-Signal Step Response
图 12. Large-Signal Step Response
8
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OPA521
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ZHCSI51A –MAY 2018–REVISED JUNE 2018
Typical Characteristics (接下页)
At TCASE = +25°C, V+ = 24 V, IN+ = (V+)/2, RLOAD = 50 Ω unless otherwise noted.
0.055
25
20
15
10
5
RISO = 0
RISO = 25
RISO = 50
0.05
0.045
0.04
0.035
0.03
0.025
0.02
0.015
0
0.01
10
100
1000
-40 -25 -10
5
20 35 50 65 80 95 110 125
Capactiance (pF)
Temperature(èC)
D022
D023
V+ = 15 V
图 13. Small-Signal Overshoot vs Capacitive Load
图 14. Gain Error vs Temperature
120
1
120
110
100
90
1
110
100
90
10
10
80
100
20 35 50 65 80 95 110 125
Temperature (èC)
80
100
20 35 50 65 80 95 110 125
Temperature (èC)
-40 -25 -10
5
-40 -25 -10
5
D025
D025
V+ = 15 V
V+ = 15 V
图 15. CMRR vs Temperature
图 16. PSRR vs Temperature
90
80
70
60
50
40
30
20
10
0
90
80
70
60
50
40
30
20
10
0
FCC/ARIB
CENELEC
FCC/ARIB
CENELEC
8
10
12
14
16
18
20
22
24
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
Supply Voltage (V)
D027
D028
V+ = 15 V
V+ = 15 V
图 17. Iq vs Supply Voltage
图 18. Iq vs Temperature
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Typical Characteristics (接下页)
At TCASE = +25°C, V+ = 24 V, IN+ = (V+)/2, RLOAD = 50 Ω unless otherwise noted.
Time (1s/div)
D032
图 19. 0.1-Hz to 10-Hz Noise
10
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OPA521
www.ti.com.cn
ZHCSI51A –MAY 2018–REVISED JUNE 2018
7 Detailed Description
7.1 Overview
The OPA521 is a power amplifier (PA) designed for power-line communication (PLC) applications. The device
features a fixed gain of –7 V/V, low-pass filter response, excellent linearity and low distortion through the
bandwidth. The amplifier operates with 7-V to 24-V supplies, and can deliver up to ±1.9 A of continuous current
from –40°C to +125°C.
7.2 Functional Block Diagram
V+
126 kꢀ
GAIN_SET
18 kꢀ
-IN
-
VOUT
+IN
+
Limits & Alarms
GND
IFLAG TFLAG EN
ILIM
IQSET
7.3 Feature Description
The OPA521 offers an optional output current limit (ILIM), quiescent current (IQSET) selection pins, and a device
enable pin. The IFLAG output alarm pin indicates an output current warning and the TFLAG alarm triggers when
the internal temperature of the device forces the devices to shut down.
7.3.1 IQSET Pin
This pin sets the operating band of the amplifier by adjusting the quiescent current.
•
•
IQSET > 2 V sets the device to operate in the FCC or ARIB bands
IQSET < 0.8 V sets the device to operate in the CENELEC bands
7.3.2 EN Pin
When the transmitter is not in use, the output is disabled and placed in a high-impedance state when the EN pin
decreases. For typical operation, connect the EN pin to 3.3 V. In disabled mode, the entire device draws 58 μA
(typical) of current.
7.3.3 ILIM Pin Current Limiting
The ILIM pin (pin 12) provides a resistor-programmable output current limit. 图 6 shows the typical current limit
for a given external RSET resistor attached to this pin.
Several typical target values and the approximate corresponding RSET are provided in 表 1.
表 1. Typical Current Limit and RSET Values
CURRENT LIMIT (A)
RSET (approximate, kΩ)
Maximum Output
Grounded
1
10
25
0.5
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7.3.4 IFLAG and TFLAG Pins
The IFLAG and TFLAG pins are active-high, open-drain outputs that indicate if the OPA521 is in current or
thermal limit. Connect these pins to 3.3 V through pullup resistors (for example 10 kΩ).
The maximum output current from the power amplifier is programmed with the external ILIM resistor that is
connected between ILIM (pin 12) and ground. IFLAG is set if the amplifier goes to a current limit state if a fault
condition occurs. This causes the power amplifier to source or sink more current than the programmed limit
value. IFLAG exhibits transient pulses under typical operation. An IFLAG true state for greater than 100 ms is a
definite indication of a fault current condition.
The device contains internal thermal shutdown protection circuitry that automatically disables the output stage if
the junction temperature exceeds 140°C. The device thermal shutdown protection circuitry lets the amplifier
typical normal operation only when the junction temperature falls below 130°C. The TFLAG is active when the
device is in thermal shut down mode.
7.4 Device Functional Modes
The OPA521 operates from a single power rail from 7 V to 24 V. The gain is fixed at –7 V/V and can increase
with an external resistor that is connected to the GAIN_SET and –IN pins.
12
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The application circuit shown in 图 20 is an AC mains-line driver over 40-kHz-to-90-kHz utility band and is based
around the European standard (EN56065–1) describing utility and consumer applications. This example shows a
possible implementation for differential transmission on the mains line. This applications circuit is designed
around the requirements of a domestic electricity meter operating over a utility band of 40 kHz to 90 kHz.
8.2 Typical Application
The impedance of the mains network at these signaling frequencies is relatively low (< 1 Ω to 30 Ω). This circuit
has been designed to drive a 2-Ω mains line over the 40-kHz-to-90-kHz bandwidth. The signaling impedance of
the mains network fluctuates as different loads are switched on during the day or over a season and it is
influenced by many factors such as:
•
•
•
Localized loading from appliances connected to the mains supply near to the connection of the
communication equipment; for example, heavy loads such as cookers and immersion heaters and reactive
loads such as EMC filters and power factor corrections.
Distributed loading from consumers connected to the same mains cable, where their collective loading
reduces the mains signaling impedance during times of peak electricity consumption; for example, meal
times.
Network parameters; for example, transmission properties of cables and the impedance characteristics of
distribution transformers and other system elements.
With such a diversity of factors, the signaling environment fluctuates enormously, irregularly, and can differ
greatly from one installation to another. Design the signaling system for reliable communications over a wide
range of mains impedances and signaling conditions. Consequently, the transmitter must be able to drive
sufficient signal into the mains network under these loading conditions.
The OPA521 amplifier has 1.9-A output drive capability with short-circuit protection; hence, it adequately copes
with the high current demands required for implementing mains signaling systems.
V+
V+
-7 V/V Gain
HV
Cap
LV Cap
HV Inductor
Rload
MCU
Line
œ
+
V+
2
Neutral
图 20. OPA521 Interface to the AC Mains
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Typical Application (接下页)
8.2.1 Design Requirements
The primary subsystems of a power-line communication mains-line driver system include the line coupling circuit,
circuit protection, and power supply. The following sections detail the design of each.
8.2.2 Detailed Design Procedure
8.2.2.1 Interfacing the OPA521 to the AC Mains
The line coupling circuit is one of the most critical segments of a power-line modem. The line coupling circuit has
two primary functions: first, to prevent the high voltage, low frequency of the mains (commonly 50 Hz or 60 Hz)
from damaging the low-voltage modem circuitry; and second, as the name implies, to couple the modem signal
to and from the ac mains.
8.2.2.1.1 Low-Voltage Capacitor
The low-voltage capacitor (LV Cap) couples the time-varying components of the power amplifier output signal
into the line coupling transformer. The LV Cap must have a large enough capacitance to appear as a low
impedance throughout the signal band of interest; 10-μF is a common value for signals in the range of 35 kHz to
150 kHz. The voltage rating of the LV cap should be sufficient to withstand the clamping voltage of the TVS
diode (that is, the transient voltage suppressor (see Circuit Protection more information) operating under surge
conditions. Generally, this limit must be equal to the power amplifier supply voltage or slightly higher.
8.2.2.1.2 High-Voltage Capacitor
The high-voltage capacitor (HV Cap) blocks the low-frequency mains voltage by forming a voltage divider with
the winding inductance of the line coupling transformer. In many applications, a maximum reactive power (VA
limit) on the HV Cap may be required. To meet this requirement, the HV Cap value is calculated by 公式 1.
VALIMIT
HVCAP
=
VAC2 ì 2 p ì f
(1)
For a 240-VAC, 50-Hz application with a 10-VA limit, the maximum value for the HV Cap is shown in 公式 2.
10
HVCAP
Ç
= 550 nF
2402 ì 2 p ì f
(2)
A 470-nF capacitor is frequently used in these types of applications. A metallized polypropylene electromagnetic
interference and radio frequency interference (EMI/RFI) suppression capacitor is recommended because of the
low loss factor associated with the dielectric, which results in minimal internal self-heating. Operating the
capacitor at approximately 80% of its ac-rated voltage ensures a long component operating life. See Circuit
Protection of this document for additional discussion on selecting the correct HV Cap value to withstand impulses
on the mains.
8.2.2.1.3 Inductor
The inductor that is connected in series with the HV Cap is required when driving low line impedances and the
HV Cap is restricted to approximately 470 nF for the reasons previously stated. In applications that operate in the
CENELEC A band, the impedance of the 470-nF capacitance at 40 kHz is approximately 8.5 Ω. If the application
requires the ability to drive a 2-Ω load, for example, this series impedance is restrictive. Adding the series
inductor can mitigate this effect. To properly select the value of the inductance, the operating frequency range of
the system must be known. A common example would be the PRIME frequency band, which is approximately 40
kHz to 90 kHz. Selecting the HV Cap and inductor to have a resonant frequency in the center of the frequency
band is recommended, and results in a series inductor value of 12.8 μH and HV Cap value of 470 nF. The
inductor must be sized to be capable of withstanding the maximum load current without saturation, using this 公
式 3 as a guideline.
1
L =
2
HV
ì 2 p ì f
CAP
(3)
14
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Typical Application (接下页)
8.2.2.1.4 Line Coupling Transformer
Most power-line communication transformers are compact, with turns ratios between 1:1 and 4:1, low leakage
inductance, and approximately 1-mH of winding inductance. It is the voltage divider formed by the HV Cap and
winding inductance that divides down the ac mains voltage and reduces it to negligible levels at the modem
output. 图 21 shows the equivalent circuit formed with the HV Cap and the line coupling transformer.
Modem
Voltage
Mains
Voltage
Power
Amplifier
LV Capacitor
10 mF
HV Capacitor
470 nF
R1
L1
L3
R3
+
N1
+
N2
120 VAC to
240 VAC
50 Hz to 60 Hz
R2
L2
C2
图 21. Voltage Divider with HV Cap and Transformer Equivalent Circuit
Where:
1. R1 is the series dc resistance of the primary winding
2. R2 is the shunt resistance reflecting losses in the core
3. R3 is the series dc resistance of the secondary winding, reflected to the primary side
4. L1 is the primary leakage inductance
5. L2 is the open circuit inductance of the primary winding
6. L3 is the secondary leakage inductance reflected to the primary side
7. C1 is the self-capacitance of the primary winding
8. C2 is the self-capacitance of the secondary winding reflected to the primary side
For the purposes of analysis, this circuit can be simplified as shown in 图 22.
C
Modem
Voltage
Mains
Voltage
120 VAC to
240 VAC
50 Hz to 60 Hz
L2
HVCap reflected to the primary side
图 22. Simplified AC Mains Voltage Divider
Where:
1. L2 = OCL of the transformer primary
2. C = HV Cap reflected to the primary side
In a typical line coupling circuit the ac mains voltage injected into the modem is approximately 20 mVPP.
Determining the optimal turns ratio (N1/N2) for the power-line communication transformer is simple, and based
on the principle of using the maximum output swing capability of the power amplifier together with the maximum
output current capability of the power amplifier to achieve maximum power transfer efficiency into the load.
Assuming the power-supply voltage and target load impedance are known, the turns ratio is determined as
shown in Figure 17, and calculated with Equation 11 and Equation 12.
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Typical Application (接下页)
8.2.2.2 Circuit Protection
Power-line communications are often located in operating environments that are harsh for electrical components
connected to the ac line. Noise or surges from electrical anomalies (such as lightning, capacitor bank switching,
inductive switching, or other grid fault conditions) can damage high-performance integrated circuits if proper
protection is not provided. The OPA521, however, can survive even the harshest conditions by using a variety of
techniques to protect the device. Layout the protection circuitry in order to dissipate as much of the electrical
disturbance as possible with a multilayer approach using metal-oxide varistors (MOVs), transient voltage
suppression diodes (TVSs), Schottky diodes, and a Zener diode. These components dissipate the electrical
disturbance before the anomaly reaches the device. shows the recommended strategy for transient overvoltage
protection.
PA
Power Supply
D1
Device
Low-Voltage
Capacitor
High-Voltage
Capacitor
D2
D3
Phase
+
N1
+
N2
MOV
Power
Amplifier
Neutral
TVS
Copyright © 2017, Texas Instruments Incorporated
图 23. Transient Overvoltage Protection for OPA521
Note that the high-voltage coupling capacitor must be able to withstand pulses up to the clamping protection
provided by the MOV. A metalized polypropylene capacitor, such as the 474MKP275KA from Illinois Capacitor, is
rated for 50 Hz to 60 Hz and 250 VAC to 310 VAC, and can withstand 24 impulses of 2.5 kV. 表 2 lists several
recommended transient protection components.
表 2. Recommended Transient Protection Components
COMPONENT
D1
DESCRIPTION
Zener diode
MANUFACTURER
Diodes, Inc.
MFR PART NO (OR EQUIVALENT)
1SMB59xxB
D2, D3
Schottky diode
Diodes, Inc.
1N5819HW
Diodec
Semiconductor
TVS
Transient voltage suppressor
P6SMBJxxC
MOV
MOV
Varistor (for 120 VAC, 60 Hz)
Varistor (for 240 VAC, 50 Hz)
High-voltage capacitor
LittleFuse
LittleFuse
TMOV20RP140E
TMOV20RP300E
474MKP275KA
HV Cap
Illinois Capacitor, Inc
16
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8.2.3 Application Curves
120
100
80
120
110
100
90
80
70
60
60
50
40
40
30
20
20
0
200K
400K
600K
800K
1M
200K
400K
600K
800K
1M
Frequency (Hz)
Frequency (Hz)
D00113
D00113
图 24. Measured ARIB Emissions
图 25. Measured FCC Emissions
120
100
80
60
40
20
0
200K
400K
600K
800K
1M
Frequency (Hz)
D00114
图 26. Measured CENELEC Emissions
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9 Power Supply Recommendations
Determining the power-supply requirements requires only a straightforward analysis. The desired load voltage,
load impedance, and available power-supply voltage or desired transformer ratio are all the parameters that must
be known. In many power-line communication applications, such as PRIME, it is required to drive a 1-VRMS signal
into a 2-Ω load. Using 图 27, calculate the minimum power-supply voltage required by adding the peak-to-peak
load voltage; the voltage dropped across the HV Cap and inductor, V2; the voltage dropped across the LV Cap,
V1; and twice the output swing to rail limit of the power amplifier, VSWING. For FSK and SFSK systems, the
peak to average ratio is √2, while for OFDM systems this ratio is approximately 3:1.
+
VSWING
-
+
V1
-
+
V2 -
PA Supply
+
LV
Capacitor
Power
Amplifier
HV
Capacitor
L
+
Phase
+
+
N1
+
N2
+
VLoad
-
œ
RLoad
Neutral
图 27. Typical Line Coupling Circuit
These ratios must be considered when performing calculations that relate the RMS voltages and peak voltages
during an analysis. Choosing a large value for the LV Cap results in the voltage drop (V1) becoming negligible in
most circumstances. The losses in the transformer are also negligible, even at high load currents, if the proper
transformer with a low DCR is used. For FSK and SFSK systems, the voltage drop across the HV Cap and
inductor, V2, is also usually negligible; in OFDM systems, because of the wider operating bandwidth, voltage
drop V2 can be ignored and accounted for by using a 1.5× multiplier on the load voltage as an approximation.
注
This approximation is only valid with a load impedance of 2 Ω for PRIME and G3. Voltage
drop V2 becomes negligible with increasing load impedance. These assumptions greatly
simplify the analysis.
表 3. Power-Supply Requirements
PARAMETER
Frequency range
RLOAD
FSK OR SFSK
PRIME OR G3 OFDM
UNIT
kHz
Ω
63 to 74
2
35 to 95
2
1
VLOAD
1
VRMS
VPEAK
VPP
—
VLOAD
1.414
2.828
—
3
VLOAD
6
OFDM multiplier
VSWING
1.5
2
2
V
Turns ration, N1/N2
PA supply
1.5
1.5
17.5
—
8.25
V
表 3 summarizes the power-supply requirements for various power-line communication systems.
Example:
For PRIME or G3 using an OFDM signal with a 2-Ω load and 1-VRMSload voltage:
PASupply = VLOAD × OFDM Multiplier × Turns Ration + (2 × VSWING
PASupply = 6 V × 1.5 × 1.5 + (2 × 2 V)
PASupply = 17.5 V
)
Power consumption
18
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Calculating the power dissipation in the load and in OPA521 also requires some direct calculations. The desired
load voltage, load impedance, available power-supply voltage, and the transformer ratio are the only parameters
required. In many power-line communication applications, such as PRIME, it is required to drive a 1-VRMS signal
into a 2-Ω load. The power dissipation in the power amplifier is determined by calculating the RMS value of the
OPA521’s output current, and the voltage difference between the power amplifier supply and RMS value of the
output voltage. These two values are multiplied, and the quiescent power of the power amplifier is added.
The power in the load is given as 公式 4 shows.
PASUPPLY
N1
N2
PA output voltage (RMS) =
+ VLOAD_RMS ì
2
(4)
(5)
The power amplifier output current is given as calculated by 公式 5.
PA power dissipation = voltage drop across PA ì PAIOUT_RMS
Because the output of the power amplifier is always symmetric around PASupply/2, only the voltage difference
between the amplifier supply and the RMS values of the PA output must be considered. 图 28 illustrates this
concept for an OFDM signal. 表 4 shows example power dissipation values.
PA Supply
PA OutputPeak
PA
OutputRMS
PA Swing to Rail
PA Supply/2
Voltage Drop Across PA; for use in
Power Dissipation Analysis
Time (s)
图 28. Typical OFDM Output Waveforms
表 4. Power Dissipation
PARAMETER
Turns ration, N1/N2
RLOAD
FSK OR SFSK
PRIME OR G3 OFDM
UNITS
-
1.5
2
1.5
2
Ω
VLOAD
1
1
VRMS
ARMS
VRMS
VRMS
ARMS
V
ILOAD
0.5
6
0.5
10.75
6.25
0.333
17
PA output voltage
Voltage drop across PA
PA output current
PA supply
3
0.333
9
PA power dissipation
Load power dissipation
Total
1
2.1
0.5
2.6
W
0.5
1.5
W
W
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The power supply itself does not need to be designed to supply the peak power amplifier current continuously.
The peak demand for current is supplied by the power-supply bypass capacitance. The power-supply voltage is
shown in 图 29 on channel 2, along with the signal voltage at the 2-Ω load on channel 1.
TYPICAL POWER-SUPPLY RESPONSE
Load Voltage
Ch 1, RMS 1.47 V
Ch 2, Peak-to-Peak
190 mV
Power-Supply
Voltage
Time (20 ms/div)
图 29. Typical Power-Supply AC Response
Two power-supply pins and two ground pins are available to provide a path for the high currents associated with
driving the low impedance of the ac mains. Connecting the two supply pins together is recommended. Placing a
47-μF to 100-μF bypass capacitor in parallel with a 100-nF capacitor as close as possible to the device is also
recommended. Care must be taken when routing the high-current ground lines on the PCB to avoid creating
voltage drops in the PCB ground that may vary with changes in load current. /
20
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10 Layout
10.1 Layout Guidelines
10.1.1 Thermal Considerations
In a typical power line communications application, the device dissipates 2 W of power when transmitting to the
low-impedance AC line. This amount of power dissipation can increase the junction temperature, which can lead
to a thermal overload that results in signal transmission interruptions if the PCB thermal design is not
implemented properly. Proper management of heat flow from the device and good PCB design and construction
are required to ensure proper device temperature, maximize performance, and extend the operating life of the
device.
The device is assembled in a 5-mm × 5-mm, QFN-20 package. This QFN package has a large exposed thermal
pad on the underside that conducts heat away from the device and to the underlying PCB.
Some heat is conducted from the silicon die surface through the plastic packaging material and is transferred to
the ambient environment. However, this route is not the primary thermal path for heat flow because plastic is a
relatively poor conductor of heat. Heat flows across the silicon die surface to the bond pads through the wire
bonds to the package leads, to the top layer of the PCB. While these paths for heat flow are important, the
majority (nearly 80%) of the heat flows downward through the silicon die to the thermally-conductive die-attach
epoxy and to the exposed thermal pad on the underside of the package (as shown in 图 30). Minimizing the
thermal resistance of this downward path to the ambient environment maximizes the life and performance of the
device.
Less than 1%
~20%
~20%
~80%
图 30. Heat Flow in the QFN Package
The exposed thermal pad must be soldered to the PCB thermal pad. The thermal pad on the PCB must be the
same size as the exposed thermal pad on the underside of the QFN package. See QFN/SON PCB Attachment
for recommendations on attaching the thermal pad to the PCB. 图 31 shows the direction of heat spreading to
the PCB from the device.
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Layout Guidelines (接下页)
Device
图 31. Heat Spreading to PCB
The heat spreading to the PCB is maximized if the thermal path is uninterrupted. Best results are achieved if the
heat-spreading surfaces are filled with copper to the greatest extent possible, which maximizes the percentage of
area covered on each layer. As an example, a thermally robust, multilayer PCB design consists of four layers
with copper (Cu) coverage of 60% in the top layer, 85% and 90% in the inner layers (respectively), and 95% on
the bottom layer.
Increasing the number of layers in the PCB, using thicker copper, and increasing the PCB area are all factors
that improve the spread of heat. 图 32 through 图 34 show thermal resistance performance as a function of each
of these factors.
THERMAL RESISTANCE vs NUMBER OF PCB LAYERS
THERMAL RESISTANCE vs BOARD AREA
36
34
32
30
28
26
24
22
20
28
26
24
22
20
18
16
14
12
10
PCB Area = 3 in2, 2 oz Cu
(Results are from thermal
simulations)
Four-Layer PCB, 2 oz Cu
(Results are from thermal
simulations)
1
2
3
4
5
6
7
8
2
4
6
8
10
12
14
PCB Area (in2)
Number of Layers
图 32. Thermal Resistance as a Function of the
图 33. Thermal Resistance as a Function of PCB
Number of Layers in the PCB
Area
22
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OPA521
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ZHCSI51A –MAY 2018–REVISED JUNE 2018
35
33
31
29
27
25
23
21
19
17
15
Four-Layer PCB, PCB
Area = 4.32 in2, 2 oz Cu
(Results are from thermal
simulations)
0.5
1
1.5
Cu Thickness (oz)
2
2.5
图 34. Thermal Resistance as a Function of Copper Thickness
For additional information on thermal PCB design using exposed thermal pad packages, see PowerPAD™
Thermally-Enhanced Package (available for download at www.ti.com).
10.2 Layout Example
图 35. Recommended Layout for Typical Transformer Coupling Application
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11 器件和文档支持
11.1 器件支持
11.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类
产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
11.2 文档支持
11.2.1 相关文档
请参阅如下相关文档：
•
•
德州仪器 (TI)，《PowerPAD™ 热增强型封装》
德州仪器 (TI)《QFN/SON PCB 连接》
11.3 接收文档更新通知
要接收文档更新通知，请在 ti.com.cn 上查找器件产品文件夹。请单击右上角的通知我 进行注册，即可接收产品信
息更改每周摘要。有关更改的详细信息，请阅读任何已修订文档中包含的修订历史记录。
11.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.5 商标
《PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.7 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
12 "机械、封装和可订购信息
以下页面显示机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查看左侧的导航栏。
24
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PACKAGE OPTION ADDENDUM
www.ti.com
8-Jun-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA521IRGWR
OPA521IRGWT
ACTIVE
VQFN
VQFN
RGW
20
20
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
OPA
521
Samples
Samples
ACTIVE
RGW
NIPDAU
OPA
521
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jun-2022
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA521IRGWR
OPA521IRGWT
VQFN
VQFN
RGW
RGW
20
20
3000
250
330.0
180.0
12.4
12.4
5.3
5.3
5.3
5.3
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA521IRGWR
OPA521IRGWT
VQFN
VQFN
RGW
RGW
20
20
3000
250
367.0
210.0
367.0
185.0
35.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGW 20
5 x 5, 0.65 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4227157/A
www.ti.com
PACKAGE OUTLINE
VQFN - 1 mm max height
RGW0020A
PLASTIC QUAD FLATPACK-NO LEAD
5.1
4.9
B
PIN 1 INDEX AREA
5.1
4.9
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
3.15±0.1
2X 2.6
(0.1) TYP
10
6
16X 0.65
5
11
SYMM
21
2X
2.6
15
1
0.36
0.26
20X
PIN1 ID
(OPTIONAL)
0.1
C A B
C
20
16
0.05
SYMM
0.65
0.45
20X
4219039/A 06/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RGW0020A
PLASTIC QUAD FLATPACK-NO LEAD
(4.65)
3.15)
(2.6)
(
20
16
16X (0.65)
15
1
(1.325)
21
SYMM
(4.65) (2.6)
(R0.05) TYP
11
5
20X (0.31)
20X (0.75)
(Ø0.2) VIA
6
10
TYP
(1.325)
SYMM
LAND PATTERN EXAMPLE
SCALE: 15X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
EXPOSED METAL
METAL
EXPOSED METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219039/A 06/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RGW0020A
PLASTIC QUAD FLATPACK-NO LEAD
(4.65)
4X ( 1.37)
2X (0.785)
16
20
16X (0.65)
21
1
15
2X (0.785)
SYMM
(4.65) (2.6)
(R0.05) TYP
11
5
20X (0.31)
20X (0.75)
METAL
TYP
6
10
SYMM
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
75% PRINTED COVERAGE BY AREA
SCALE: 15X
4219039/A 06/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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