OPA627_07 [TI]
Precision High-Speed Difet OPERATIONAL AMPLIFIERS; 高速精密差动运算放大器
| 型号： | OPA627_07 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Precision High-Speed Difet OPERATIONAL AMPLIFIERS |
| 文件： | 总16页 (文件大小：267K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
OPA627
OPA637
OPA627
OPA627
Precision High-Speed
Difet ® OPERATIONAL AMPLIFIERS
APPLICATIONS
● PRECISION INSTRUMENTATION
FEATURES
● VERY LOW NOISE: 4.5nV/√Hz at 10kHz
● FAST DATA ACQUISITION
● FAST SETTLING TIME:
OPA627—550ns to 0.01%
OPA637—450ns to 0.01%
● DAC OUTPUT AMPLIFIER
● OPTOELECTRONICS
● LOW VOS: 100µV max
● SONAR, ULTRASOUND
● LOW DRIFT: 0.8µV/°C max
● LOW IB: 5pA max
● HIGH-IMPEDANCE SENSOR AMPS
● HIGH-PERFORMANCE AUDIO CIRCUITRY
● OPA627: Unity-Gain Stable
● OPA637: Stable in Gain ≥ 5
● ACTIVE FILTERS
High frequency complementary transistors allow in-
creased circuit bandwidth, attaining dynamic perform-
ance not possible with previous precision FET op
amps. The OPA627 is unity-gain stable. The OPA637
is stable in gains equal to or greater than five.
DESCRIPTION
The OPA627 and OPA637 Difet operational amplifi-
ers provide a new level of performance in a precision
FET op amp. When compared to the popular OPA111
op amp, the OPA627/637 has lower noise, lower offset
voltage, and much higher speed. It is useful in a broad
range of precision and high speed analog circuitry.
Difet fabrication achieves extremely low input bias
currents without compromising input voltage noise
performance. Low input bias current is maintained
over a wide input common-mode voltage range with
unique cascode circuitry.
The OPA627/637 is fabricated on a high-speed, dielec-
trically-isolated complementary NPN/PNP process. It
operates over a wide range of power supply voltage—
±4.5V to ±18V. Laser-trimmed Difet input circuitry
provides high accuracy and low-noise performance
comparable with the best bipolar-input op amps.
The OPA627/637 is available in plastic DIP, SOIC
and metal TO-99 packages. Industrial and military
temperature range models are available.
7
+VS
Trim
1
Trim
5
Output
6
+In
3
–In
2
Difet ®, Burr-Brown Corp.
–VS
4
International Airport Industrial Park
•
Mailing Address: PO Box 11400, Tucson, AZ 85734
FAXLine: (800) 548-6133 (US/Canada Only)
• Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/
•
•
Cable: BBRCORP
•
Telex: 066-6491
•
FAX: (520) 889-1510
•
Immediate Product Info: (800) 548-6132
©1989 Burr-Brown Corporation
PDS-998H
Printed in U.S.A. March, 1998
SBOS165
SPECIFICATIONS
ELECTRICAL
At TA = +25°C, and VS = ±15V, unless otherwise noted.
OPA627BM, BP, SM
OPA637BM, BP, SM
OPA627AM, AP, AU
OPA637AM, AP, AU
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
(1)
OFFSET VOLTAGE
Input Offset Voltage
AP, BP, AU Grades
Average Drift
AP, BP, AU Grades
Power Supply Rejection
40
100
0.4
0.8
120
100
250
0.8
2
130
280
1.2
2.5
116
250
500
2
µV
µV
µV/°C
µV/°C
dB
VS = ±4.5 to ±18V
106
100
INPUT BIAS CURRENT (2)
Input Bias Current
Over Specified Temperature
SM Grade
Over Common-Mode Voltage
Input Offset Current
Over Specified Temperature
SM Grade
VCM = 0V
VCM = 0V
VCM = 0V
VCM = ±10V
VCM = 0V
VCM = 0V
1
5
1
50
2
10
2
pA
nA
nA
pA
pA
nA
nA
1
0.5
2
1
5
1
50
10
2
NOISE
Input Voltage Noise
Noise Density: f = 10Hz
f = 100Hz
f = 1kHz
f = 10kHz
Voltage Noise, BW = 0.1Hz to 10Hz
Input Bias Current Noise
Noise Density, f = 100Hz
Current Noise, BW = 0.1Hz to 10Hz
15
8
5.2
4.5
0.6
40
20
8
6
1.6
20
10
5.6
4.8
0.8
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
µVp-p
1.6
30
2.5
60
2.5
48
fA/√Hz
fAp-p
INPUT IMPEDANCE
Differential
Common-Mode
1013 || 8
1013 || 7
*
*
Ω || pF
Ω || pF
INPUT VOLTAGE RANGE
Common-Mode Input Range
Over Specified Temperature
Common-Mode Rejection
±11
±10.5
106
±11.5
±11
116
*
*
*
*
V
V
dB
VCM = ±10.5V
100
110
OPEN-LOOP GAIN
Open-Loop Voltage Gain
Over Specified Temperature
SM Grade
V
O = ±10V, RL = 1kΩ
112
106
100
120
117
114
106
100
116
110
dB
dB
dB
VO = ±10V, RL = 1kΩ
VO = ±10V, RL = 1kΩ
FREQUENCY RESPONSE
Slew Rate: OPA627
OPA637
Settling Time: OPA627 0.01%
0.1%
G = –1, 10V Step
G = –4, 10V Step
G = –1, 10V Step
G = –1, 10V Step
G = –4, 10V Step
G = –4, 10V Step
G = 1
40
100
55
135
550
450
450
300
16
80
0.00003
*
*
*
*
*
*
*
*
*
*
*
V/µs
V/µs
ns
ns
ns
OPA637 0.01%
0.1%
ns
Gain-Bandwidth Product: OPA627
OPA637
Total Harmonic Distortion + Noise
MHz
MHz
%
G = 10
G = +1, f = 1kHz
POWER SUPPLY
Specified Operating Voltage
Operating Voltage Range
Current
±15
±7
*
*
V
V
mA
±4.5
±18
±7.5
*
*
*
OUTPUT
Voltage Output
Over Specified Temperature
Current Output
Short-Circuit Current
Output Impedance, Open-Loop
R
L = 1kΩ
±11.5
±11
±12.3
±11.5
±45
+70/–55
55
*
*
*
*
*
*
*
V
VO = ±10V
mA
mA
Ω
±35
±100
*
*
*
1MHz
TEMPERATURE RANGE
Specification: AP, BP, AM, BM, AU
–25
–55
–60
–40
+85
*
°C
°C
SM
Storage: AM, BM, SM
AP, BP, AU
+125
+150
+125
*
*
*
*
°C
°C
θJ-A: AM, BM, SM
AP, BP
200
100
160
*
*
°C/W
°C/W
°C/W
AU
* Specifications same as “B” grade.
NOTES: (1) Offset voltage measured fully warmed-up. (2) High-speed test at TJ = +25°C. See Typical Performance Curves for warmed-up performance.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
OPA627, 637
2
ABSOLUTE MAXIMUM RATINGS(1)
PIN CONFIGURATIONS
Supply Voltage .................................................................................. ±18V
Input Voltage Range .............................................. +VS + 2V to –VS – 2V
Differential Input Range....................................................... Total VS + 4V
Power Dissipation ........................................................................ 1000mW
Operating Temperature
M Package .................................................................. –55°C to +125°C
P, U Package ............................................................. –40°C to +125°C
Storage Temperature
Top View
DIP/SOIC
Offset Trim
–In
1
2
3
4
8
7
6
5
No Internal Connection
+VS
+In
Output
Offset Trim
M Package .................................................................. –65°C to +150°C
P, U Package ............................................................. –40°C to +125°C
Junction Temperature
–VS
M Package .................................................................................. +175°C
P, U Package ............................................................................. +150°C
Lead Temperature (soldering, 10s) ............................................... +300°C
SOlC (soldering, 3s) ................................................................... +260°C
NOTE: (1) Stresses above these ratings may cause permanent damage.
TO-99
Top View
No Internal Connection
8
PACKAGE/ORDERING INFORMATION
+VS
Offset Trim
PACKAGE DRAWING
NUMBER(1)
TEMPERATURE
RANGE
1
7
PRODUCT
PACKAGE
OPA627AP
OPA627BP
OPA627AU
OPA627AM
OPA627BM
OPA627SM
Plastic DIP
Plastic DIP
SOIC
TO-99 Metal
TO-99 Metal
TO-99 Metal
006
006
182
001
001
001
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
–55°C to +125°C
–In
2
Output
6
3
5
+In
OPA637AP
OPA637BP
OPA637AU
OPA637AM
OPA637BM
OPA637SM
Plastic DIP
Plastic DIP
SOIC
TO-99 Metal
TO-99 Metal
TO-99 Metal
006
006
182
001
001
001
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
–55°C to +125°C
4
Offset Trim
–VS
Case connected to –VS.
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
®
3
OPA627, 637
TYPICAL PERFORMANCE CURVES
At TA = +25°C, and VS = ±15V, unless otherwise noted.
TOTAL INPUT VOLTAGE NOISE vs BANDWIDTH
INPUT VOLTAGE NOISE SPECTRAL DENSITY
1k
100
10
1
p-p
Noise Bandwidth:
0.1Hz to indicated
frequency.
100
10
1
0.1
RMS
0.01
1
10
100
1k
10k
100k
1M
10M
1
10
100
1k
10k
100k
1M
10M
Bandwidth (Hz)
Frequency (Hz)
VOLTAGE NOISE vs SOURCE RESISTANCE
OPEN-LOOP GAIN vs FREQUENCY
1k
100
10
140
120
100
80
–
+
OPA637
RS
60
Comparison with
OPA27 Bipolar Op
Amp + Resistor
OPA627 + Resistor
40
OPA627
20
Spot Noise
at 10kHz
0
Resistor Noise Only
–20
1
100
1k
10k
100k
1M
10M
100M
1
10
100
1k
10k 100k 1M
10M 100M
Ω
)
Source Resistance (
Frequency (Hz)
OPA627 GAIN/PHASE vs FREQUENCY
OPA637 GAIN/PHASE vs FREQUENCY
30
20
10
0
30
–90
–90
20
10
–120
–150
–180
–210
–120
–150
–180
–210
Phase
Phase
Gain
75° Phase
Margin
Gain
0
–10
–10
1
10
100
1
10
100
Frequency (MHz)
Frequency (MHz)
®
OPA627, 637
4
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, and VS = ±15V, unless otherwise noted.
OPEN-LOOP GAIN vs TEMPERATURE
OPEN-LOOP OUTPUT IMPEDANCE vs FREQUENCY
125
120
115
110
105
100
80
60
40
20
0
2
20
200
2k
20k
200k
2M
20M
–75 –50
–25
0
25
50
75
100 125
Frequency (Hz)
Temperature (°C)
COMMON-MODE REJECTION vs
INPUT COMMON MODE VOLTAGE
COMMON-MODE REJECTION vs FREQUENCY
OPA637
130
120
110
100
90
140
120
100
80
OPA627
60
40
20
80
0
1
10
100
1k
10k
100k
1M
10M
–15
–10
–5
0
5
10
15
Common-Mode Voltage (V)
Frequency (Hz)
POWER-SUPPLY REJECTION AND COMMON-MODE
REJECTION vs TEMPERATURE
POWER-SUPPLY REJECTION vs FREQUENCY
125
120
115
110
105
140
120
100
80
PSR
–VS PSRR 627
and 637
CMR
60
+VS PSRR 627
637
40
20
0
–75
–50
–25
0
25
50
75
100
125
1
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Temperature (°C)
®
5
OPA627, 637
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, and VS = ±15V, unless otherwise noted.
SUPPLY CURRENT vs TEMPERATURE
OUTPUT CURRENT LIMIT vs TEMPERATURE
100
80
60
40
20
0
8
7.5
7
+IL at VO = 0V
+IL at VO = +10V
–IL at VO = 0V
6.5
6
–IL at VO = –10V
–75 –50
–25
0
25
50
75
100 125
–75 –50
–25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
OPA637 GAIN-BANDWIDTH AND SLEW RATE
vs TEMPERATURE
OPA627 GAIN-BANDWIDTH AND SLEW RATE
vs TEMPERATURE
120
100
80
160
24
20
16
12
8
60
55
50
Slew Rate
140
120
100
80
Slew Rate
GBW
GBW
60
40
–75
–50
–25
0
25
50
75
100
125
–75
–50
–25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
OPA627 TOTAL HARMONIC DISTORTION + NOISE
vs FREQUENCY
OPA637 TOTAL HARMONIC DISTORTION + NOISE
vs FREQUENCY
0.1
0.01
1
0.1
G = +1
G = +10
G = +10
G = +50
VI
VI
+
–
VO = ±10V
+
–
VO = ±10V
VI
VI
+
–
VO = ±10V
600
+
–
VO = ±10V
600
600 Ω
600Ω
5kΩ
100pF
100pF
Ω
Ω
5k
Ω
5kΩ
100pF
100pF
549Ω
549
Ω
102
Ω
Measurement BW: 80kHz
0.001
0.01
G = +50
Measurement BW: 80kHz
G = +10
0.0001
0.00001
0.001
0.0001
G = +1
G = +10
10k 20k
20
100
1k
10k 20k
20
100
1k
Frequency (Hz)
Frequency (Hz)
®
OPA627, 637
6
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, and VS = ±15V, unless otherwise noted.
INPUT BIAS CURRENT
vs POWER SUPPLY VOLTAGE
INPUT BIAS AND OFFSET CURRENT
vs JUNCTION TEMPERATURE
10k
1k
20
15
10
5
NOTE: Measured fully
warmed-up.
TO-99
Plastic
100
10
IB
DIP, SOIC
IOS
1
TO-99 with 0807HS Heat Sink
0.1
0
±4
±6
±8
±10
±12
±14
±16
±18
–50 –25
0
25
50
75
100
125 150
Supply Voltage (±VS)
Junction Temperature (°C)
INPUT BIAS CURRENT vs COMMON-MODE VOLTAGE
INPUT OFFSET VOLTAGE WARM-UP vs TIME
1.2
1.1
1
50
25
Beyond Linear
Common-Mode Range
0
0.9
0.8
–25
–50
Beyond Linear
Common-Mode Range
–15
–10
–5
0
5
10
15
0
1
2
3
4
5
6
Common-Mode Voltage (V)
Time From Power Turn-On (Min)
MAX OUTPUT VOLTAGE vs FREQUENCY
SETTLING TIME vs CLOSED-LOOP GAIN
100
30
20
10
0
Error Band: ±0.01%
OPA627
10
1
OPA637
OPA637
OPA627
0.1
100k
1M
10M
100M
–1
–10
–100
–1000
Frequency (Hz)
Closed-Loop Gain (V/V)
®
7
OPA627, 637
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, and VS = ±15V, unless otherwise noted.
SETTLING TIME vs ERROR BAND
SETTLING TIME vs LOAD CAPACITANCE
1500
1000
500
0
3
2
1
0
CF
+5V
–5V
OPA627 OPA637
RI
RF
OPA637
G = –4
–
+
RI 2kΩ
RF 2kΩ
CF 6pF
500Ω
2kΩ
4pF
Error Band:
±0.01%
2kΩ
OPA627
G = –1
OPA627
G = –1
OPA637
G = –4
0.001
0.01
0.1
Error Band (%)
1
10
0
150
200
300
400
500
Load Capacitance (pF)
APPLICATIONS INFORMATION
RF < 4RI
OPA627
The OPA627 is unity-gain stable. The OPA637 may be used
to achieve higher speed and bandwidth in circuits with noise
gain greater than five. Noise gain refers to the closed-loop
gain of a circuit as if the non-inverting op amp input were
being driven. For example, the OPA637 may be used in a
non-inverting amplifier with gain greater than five, or an
inverting amplifier of gain greater than four.
OPA627
–
–
+
+
Buffer
Non-Inverting Amp
G < 5
RI
RF < 4R
RI
When choosing between the OPA627 or OPA637, it is
important to consider the high frequency noise gain of your
circuit configuration. Circuits with a feedback capacitor
(Figure 1) place the op amp in unity noise-gain at high
frequency. These applications must use the OPA627 for
proper stability. An exception is the circuit in Figure 2,
where a small feedback capacitance is used to compensate
for the input capacitance at the op amp’s inverting input. In
this case, the closed-loop noise gain remains constant with
frequency, so if the closed-loop gain is equal to five or
greater, the OPA637 may be used.
OPA627
OPA627
–
–
+
+
Bandwidth
Limiting
Inverting Amp
G < |–4|
OPA627
OPA627
–
–
+
+
Filter
Integrator
FIGURE 1. Circuits with Noise Gain Less than Five Require
the OPA627 for Proper Stability.
®
OPA627, 637
8
OFFSET VOLTAGE ADJUSTMENT
amp contributes little additional noise. Below 1kΩ, op amp
noise dominates over the resistor noise, but compares
favorably with precision bipolar op amps.
The OPA627/637 is laser-trimmed for low offset voltage
and drift, so many circuits will not require external adjust-
ment. Figure 3 shows the optional connection of an external
potentiometer to adjust offset voltage. This adjustment should
not be used to compensate for offsets created elsewhere in a
system (such as in later amplification stages or in an A/D
converter) because this could introduce excessive tempera-
ture drift. Generally, the offset drift will change by approxi-
mately 4µV/°C for 1mV of change in the offset voltage due
to an offset adjustment (as shown on Figure 3).
CIRCUIT LAYOUT
As with any high speed, wide bandwidth circuit, careful
layout will ensure best performance. Make short, direct
interconnections and avoid stray wiring capacitance—espe-
cially at the input pins and feedback circuitry.
The case (TO-99 metal package only) is internally connected
to the negative power supply as it is with most common op
amps. Pin 8 of the plastic DIP, SOIC, and TO-99 packages
has no internal connection.
C2
Power supply connections should be bypassed with good
high frequency capacitors positioned close to the op amp
pins. In most cases 0.1µF ceramic capacitors are adequate.
The OPA627/637 is capable of high output current (in
excess of 45mA). Applications with low impedance loads or
capacitive loads with fast transient signals demand large
currents from the power supplies. Larger bypass capacitors
such as 1µF solid tantalum capacitors may improve dynamic
performance in these applications.
R2
C1
–
+
OPA637
R1
C1 = CIN + CSTRAY
R1 C1
C2
=
R2
FIGURE 2. Circuits with Noise Gain Equal to or Greater than
Five May Use the OPA637.
+VS
100kΩ
NOISE PERFORMANCE
7
10kΩ to 1MΩ
Potentiometer
(100kΩ preferred)
Some bipolar op amps may provide lower voltage noise
performance, but both voltage noise and bias current noise
contribute to the total noise of a system. The OPA627/637
is unique in providing very low voltage noise and very low
current noise. This provides optimum noise performance
over a wide range of sources, including reactive source
impedances. This can be seen in the performance curve
showing the noise of a source resistor combined with the
noise of an OPA627. Above a 2kΩ source resistance, the op
1
2
5
–
+
6
3
OPA627/637
4
±10mV Typical
Trim Range
–VS
FIGURE 3. Optional Offset Voltage Trim Circuit.
Non-inverting
Buffer
2
–
2
–
6
6
OPA627
Out
Out
3
3
In
In
+
+
OPA627
TO-99 Bottom View
Inverting
In
OPA627
4
3
2
3
–
+
5
6
Out
2
6
Board Layout for Input Guarding:
Guard top and bottom of board.
Alternate—use Teflon® standoff for sen-
sitive input pins.
7
No Internal Connection
1
8
Teflon® E.I. du Pont de Nemours & Co.
To Guard Drive
FIGURE 4. Connection of Input Guard for Lowest IB.
®
9
OPA627, 637
INPUT BIAS CURRENT
takes approximately 500ns. When the output is driven into
the positive limit, recovery takes approximately 6µs. Output
recovery of the OPA627 can be improved using the output
clamp circuit shown in Figure 5. Diodes at the inverting
input prevent degradation of input bias current.
Difet fabrication of the OPA627/637 provides very low
input bias current. Since the gate current of a FET doubles
approximately every 10°C, to achieve lowest input bias
current, the die temperature should be kept as low as pos-
sible. The high speed and therefore higher quiescent current
of the OPA627/637 can lead to higher chip temperature. A
simple press-on heat sink such as the Burr-Brown model
807HS (TO-99 metal package) can reduce chip temperature
by approximately 15°C, lowering the IB to one-third its
warmed-up value. The 807HS heat sink can also reduce low-
frequency voltage noise caused by air currents and thermo-
electric effects. See the data sheet on the 807HS for details.
+VS
5kΩ
(2)
HP 5082-2811
Diode Bridge
ZD1
Temperature rise in the plastic DIP and SOIC packages can
be minimized by soldering the device to the circuit board.
Wide copper traces will also help dissipate heat.
BB: PWS740-3
1kΩ
ZD1 : 10V IN961
5kΩ
The OPA627/637 may also be operated at reduced power
supply voltage to minimize power dissipation and tempera-
ture rise. Using ±5V power supplies reduces power dissipa-
tion to one-third of that at ±15V. This reduces the IB of TO-
99 metal package devices to approximately one-fourth the
value at ±15V.
RF
VI
–
–VS
VO
Clamps output
at VO = ±11.5V
RI
+
OPA627
Leakage currents between printed circuit board traces can
easily exceed the input bias current of the OPA627/637. A
circuit board “guard” pattern (Figure 4) reduces leakage
effects. By surrounding critical high impedance input cir-
cuitry with a low impedance circuit connection at the same
potential, leakage current will flow harmlessly to the low-
impedance node. The case (TO-99 metal package only) is
internally connected to –VS.
FIGURE 5. Clamp Circuit for Improved Overload Recovery.
CAPACITIVE LOADS
As with any high-speed op amp, best dynamic performance
can be achieved by minimizing the capacitive load. Since a
load capacitance presents a decreasing impedance at higher
frequency, a load capacitance which is easily driven by a
slow op amp can cause a high-speed op amp to perform
poorly. See the typical curves showing settling times as a
function of capacitive load. The lower bandwidth of the
OPA627 makes it the better choice for driving large capaci-
tive loads. Figure 6 shows a circuit for driving very large
load capacitance. This circuit’s two-pole response can also
be used to sharply limit system bandwidth. This is often
useful in reducing the noise of systems which do not require
the full bandwidth of the OPA627.
Input bias current may also be degraded by improper han-
dling or cleaning. Contamination from handling parts and
circuit boards may be removed with cleaning solvents and
deionized water. Each rinsing operation should be followed
by a 30-minute bake at 85°C.
Many FET-input op amps exhibit large changes in input
bias current with changes in input voltage. Input stage
cascode circuitry makes the input bias current of the
OPA627/637 virtually constant with wide common-mode
voltage changes. This is ideal for accurate high input-
impedance buffer applications.
RF
1kΩ
PHASE-REVERSAL PROTECTION
The OPA627/637 has internal phase-reversal protection.
Many FET-input op amps exhibit a phase reversal when the
input is driven beyond its linear common-mode range. This
is most often encountered in non-inverting circuits when the
input is driven below –12V, causing the output to reverse
into the positive rail. The input circuitry of the OPA627/637
does not induce phase reversal with excessive common-
mode voltage, so the output limits into the appropriate rail.
200pF
G = +1
BW ≥ 1MHz
CF
RO
20Ω
–
+
CL
5nF
OPA627
RF
R1
R1
G = 1+
For Approximate Butterworth Response:
Optional Gain
Gain > 1
2 RO CL
RF >> RO
CF
=
RF
OUTPUT OVERLOAD
1
When the inputs to the OPA627/637 are overdriven, the
output voltage of the OPA627/637 smoothly limits at ap-
proximately 2.5V from the positive and negative power
supplies. If driven to the negative swing limit, recovery
f–3dB
=
2π √ RF RO CF CL
FIGURE 6. Driving Large Capacitive Loads.
®
OPA627, 637
10
INPUT PROTECTION
Sometimes input protection is required on I/V converters of
inverting amplifiers (Figure 7b). Although in normal opera-
tion, the voltage at the summing junction will be near zero
(equal to the offset voltage of the amplifier), large input
transients may cause this node to exceed 2V beyond the
power supplies. In this case, the summing junction should
be protected with diode clamps connected to ground. Even
with the low voltage present at the summing junction,
common signal diodes may have excessive leakage current.
Since the reverse voltage on these diodes is clamped, a
diode-connected signal transistor can be used as an inexpen-
sive low leakage diode (Figure 7b).
The inputs of the OPA627/637 are protected for voltages
between +VS + 2V and –VS – 2V. If the input voltage can
exceed these limits, the amplifier should be protected. The
diode clamps shown in Figure 7a will prevent the input
voltage from exceeding one forward diode voltage drop
beyond the power supplies—well within the safe limits. If
the input source can deliver current in excess of the maxi-
mum forward current of the protection diodes, use a series
resistor, RS, to limit the current. Be aware that adding
resistance to the input will increase noise. The 4nV/√Hz
theoretical thermal noise of a 1kΩ resistor will add to the
4.5nV/√Hz noise of the OPA627/637 (by the square-root of
the sum of the squares), producing a total noise of 6nV/√Hz.
Resistors below 100Ω add negligible noise.
+VS
Leakage current in the protection diodes can increase the
total input bias current of the circuit. The specified maxi-
mum leakage current for commonly used diodes such as the
1N4148 is approximately 25nA—more than a thousand
times larger than the input bias current of the OPA627/637.
Leakage current of these diodes is typically much lower and
may be adequate in many applications. Light falling on the
junction of the protection diodes can dramatically increase
leakage current, so common glass-packaged diodes should
be shielded from ambient light. Very low leakage can be
achieved by using a diode-connected FET as shown. The
2N4117A is specified at 1pA and its metal case shields the
junction from light.
–
VO
D
+
OPA627
D
D: IN4148 — 25nA Leakage
2N4117A — 1pA Leakage
Siliconix
Optional RS
–VS
=
(a)
IIN
–
+
VO
D
D
OPA627
D: 2N3904
=
(b)
NC
FIGURE 7. Input Protection Circuits.
SMALL SIGNAL RESPONSE
LARGE SIGNAL RESPONSE
(A)
(B)
When used as a unity-gain buffer, large common-mode input voltage steps
produce transient variations in input-stage currents. This causes the rising
edge to be slower and falling edges to be faster than nominal slew rates
observed in higher-gain circuits.
G = 1
–
+
OPA627
FIGURE 8. OPA627 Dynamic Performance, G = +1.
®
11
OPA627, 637
LARGE SIGNAL RESPONSE
+10
0
+10
(C)
0
(D)
–10
–10
6pF(1)
NOTE: (1) Optimum value will
depend on circuit board lay-
out and stray capacitance at
the inverting input.
When driven with a very fast input step (left), common-mode
transients cause a slight variation in input stage currents which
will reduce output slew rate. If the input step slew rate is reduced
(right), output slew rate will increase slightly.
2kΩ
G = –1
VOUT
–
2kΩ
+
OPA627
FIGURE 9. OPA627 Dynamic Performance, G = –1.
OPA637
OPA637
LARGE SIGNAL RESPONSE
SMALL SIGNAL RESPONSE
+10
+100
0
0
(E)
(F)
–10
–100
4pF(1)
2kΩ
G = 5
VOUT
–
+
OPA637
500Ω
NOTE: (1) Optimum value will depend on circuit
board layout and capacitance at inverting input.
FIGURE 10. OPA637 Dynamic Response, G = 5.
®
OPA627, 637
12
Error Out
RI/
2kΩ
OPA627
OPA637
CF
RI, R1
CF
Error Band
(0.01%)
2kΩ
6pF
±0.5mV
500Ω
4pF
±0.2mV
HP-
5082-
2835
2kΩ
+15V
RI
High Quality
–
+
NOTE: CF is selected for best settling time performance
depending on test fixture layout. Once optimum value is
determined, a fixed capacitor may be used.
±5V
Out
Pulse Generator
51Ω
–15V
FIGURE 11. Settling Time and Slew Rate Test Circuit.
Gain = 100
≈
CMRR 116dB
OPA637
–In
+
–
≈
Bandwidth 1MHz
RF
5kΩ
25kΩ
25kΩ
5
6
2
3
Input Common-Mode
Range = ±5V
INA105
Differential
Amplifier
RG
101Ω
3pF
Output
–
+
RF
5kΩ
25kΩ
25kΩ
–
+
1
+In
OPA637
Differential Voltage Gain = 1 + 2RF/RG
FIGURE 12. High Speed Instrumentation Amplifier, Gain = 100.
Gain = 1000
≈
CMRR 116dB
OPA637
–In
+
–
≈
Bandwidth 400kHz
RF
5kΩ
10kΩ
100kΩ
5
6
2
3
Input Common-Mode
Range = ±10V
INA106
Differential
Amplifier
RG
101Ω
3pF
Output
–
+
RF
5kΩ
10kΩ
100kΩ
–
+
1
+In
OPA637
Differential Voltage Gain = (1 + 2RF/RG) • 10
FIGURE 13. High Speed Instrumentation Amplifier, Gain = 1000.
This composite amplifier uses the OPA603 current-feedback op amp to
provide extended bandwidth and slew rate at high closed-loop gain. The
feedback loop is closed around the composite amp, preserving the
precision input characteristics of the OPA627/637. Use separate power
supply bypass capacitors for each op amp.
R2
–
A1
+
–
*Minimize capacitance at this node.
VI
+
VO
GAIN
(V/V)
A1
OP AMP
R1
(Ω)
R2
(kΩ)
R3
R4
–3dB
SLEW RATE
OPA603
R
L ≥ 150Ω
for ±10V Out
(Ω)
(kΩ) (MHz)
(V/µs)
R1
100
1000
OPA627
OPA637
50.5(1) 4.99
49.9 4.99
20
12
1
1
15
11
700
500
*
R3
R4
NOTE: (1) Closest 1/2% value.
FIGURE 14. Composite Amplifier for Wide Bandwidth.
®
13
OPA627, 637
PACKAGE OPTION ADDENDUM
www.ti.com
15-Feb-2007
PACKAGING INFORMATION
Orderable Device
OPA627AM
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
NRND
TO-99
LMC
8
8
8
8
8
8
8
8
8
8
8
8
8
20 Green (RoHS &
no Sb/Br)
AU
N / A for Pkg Type
OPA627AP
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
NRND
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
TO-99
PDIP
PDIP
TO-99
TO-99
P
P
50 Green (RoHS & CU NIPDAU N / A for Pkg Type
no Sb/Br)
OPA627APG4
OPA627AU
50 Green (RoHS & CU NIPDAU N / A for Pkg Type
no Sb/Br)
D
100 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
OPA627AU/2K5
OPA627AU/2K5E4
OPA627AUE4
OPA627AUG4
OPA627BM
D
2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
D
100
Pb-Free
(RoHS)
CU NIPDAU Level-3-260C-168 HR
D
100 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
LMC
P
20 Green (RoHS &
no Sb/Br)
AU
N / A for Pkg Type
OPA627BP
ACTIVE
ACTIVE
NRND
50 Green (RoHS & CU NIPDAU N / A for Pkg Type
no Sb/Br)
OPA627BPG4
OPA627SM
P
50 Green (RoHS & CU NIPDAU N / A for Pkg Type
no Sb/Br)
LMC
LMC
20 Green (RoHS &
no Sb/Br)
Call TI
Call TI
Call TI
N / A for Pkg Type
N / A for Pkg Type
Call TI
OPA637AM
NRND
20 Green (RoHS &
no Sb/Br)
OPA637AM2
OPA637AP
OBSOLETE
ACTIVE
TO-99
PDIP
LMC
P
8
8
TBD
50 Green (RoHS & CU NIPDAU N / A for Pkg Type
no Sb/Br)
OPA637APG4
OPA637AU
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
NRND
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
TO-99
P
D
8
8
8
8
8
8
8
50 Green (RoHS & CU NIPDAU N / A for Pkg Type
no Sb/Br)
100 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
OPA637AU/2K5
OPA637AU/2K5E4
OPA637AUE4
OPA637AUG4
OPA637BM
D
2500
2500
100
Pb-Free
(RoHS)
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
D
Pb-Free
(RoHS)
D
Pb-Free
(RoHS)
D
100 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
LMC
20 Green (RoHS &
no Sb/Br)
Call TI
N / A for Pkg Type
OPA637BM1
OPA637BP
OBSOLETE
ACTIVE
TO-99
PDIP
LMC
P
8
8
TBD
Call TI
Call TI
50 Green (RoHS & CU NIPDAU N / A for Pkg Type
no Sb/Br)
OPA637BPG4
OPA637SM
ACTIVE
NRND
PDIP
P
8
8
50 Green (RoHS & CU NIPDAU N / A for Pkg Type
no Sb/Br)
TO-99
LMC
20 Green (RoHS &
Call TI
N / A for Pkg Type
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
15-Feb-2007
Orderable Device
Status (1)
Package Package
Type Drawing
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
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reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
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