OPA688MJD [TI]
UNITY-GAIN-STABLE WIDEBAND VOLTAGE LIMITING AMP LIFIER; 单位增益稳定的宽带电压限幅放大器真的现象
| 型号： | OPA688MJD |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | UNITY-GAIN-STABLE WIDEBAND VOLTAGE LIMITING AMP LIFIER |
| 文件： | 总23页 (文件大小：348K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀ ꢁꢂ ꢃꢄꢄ ꢅ
ꢆꢇꢈ ꢉ ꢊꢋꢌ ꢂꢈꢇ ꢋꢍꢉꢂꢎꢏ ꢐ ꢑꢈ ꢒ ꢐꢎ ꢂ ꢇꢒ
ꢓꢀ ꢏꢉꢂꢌ ꢐ ꢏ ꢈꢅ ꢈꢉ ꢈꢇ ꢌ ꢂꢅ ꢁ ꢏꢈ ꢔꢈ ꢐꢕ
SGLS144B − APRIL 2003 − DECEMBER 2006
D
D
D
D
IF Limiting Amplifiers
features
AM Signal Generation
D
D
D
D
D
D
D
High Linearity Near Limiting
Non−Linear Analog Signal Processing
High Speed Comparators
Fast Recovery from Overdrive: 2.4 ns
IiMiting Voltage Accuracy: 15 mV
−3dB Bandwidth (G = +1): 450 MHz
Slew Rate: 1000 V/µs
5-V and 5-V Supply Operation
Unity Gain Version of the OPA689
JD PACKAGE
(TOP VIEW)
NC
V
H
1
2
3
4
8
7
6
5
INVERTING INPUT
+VCC
OUTPUT
VL
NON-INVERTING INPUT
−VCC
applications
D
D
D
D
Fast Limiting ADC Input Buffers
CCD Pixel Clock Stripping
Video Sync Stripping
HF Mixers
NC - No internal connection
description
The OPA688 is a wideband, unity gain stable voltage-feedback op amp that offers bipolar output voltage limiting.
Two buffered limiting voltages take control of the output when it attempts to drive beyond these limits. This new
output limiting architecture holds the limiter offset error to 15 mV. The op amp operates linearly to within
30 mV of the output limit voltages.
The combination of narrow nonlinear range and low limiting offset allows the limiting voltages to be set within
100 mV of the desired linear output range. A fast 2.4-ns recovery from limiting ensures that overdrive signals
will be transparent to the signal channel. Implementing the limiting function at the output, as opposed to the
input, gives the specified limiting accuracy for any gain, and allows the OPA688 to be used in all standard op
amp applications.
Non-linear analog signal processing will benefit from the OPA688s sharp transition from linear operation to
output limiting. The quick recovery time supports high-speed applications.
The OPA688M is available in an industry standard pinout CDIP-8 package. For higher gain, or transimpedance
applications requiring output limiting with fast recovery, consider the OPA689M.
†
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
T
A
PACKAGE
−55°C to 125°C
CDIP - JD
Tube
OPA688MJD
OPA688MJD
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2006, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢆ ꢇꢈꢉ ꢊꢋꢌꢂ ꢈ ꢇ ꢋꢍꢉꢂꢎ ꢏꢐ ꢑ ꢈ ꢒꢐ ꢎꢂꢇ ꢒ
ꢓ ꢀꢏꢉꢂ ꢌꢐ ꢏ ꢈ ꢅꢈ ꢉ ꢈ ꢇꢌ ꢂꢅ ꢁꢏ ꢈ ꢔꢈ ꢐ ꢕ
SGLS144B − APRIL 2003 − DECEMBER 2006
DETAIL OF LIM ITED OUTPUT VOLTAG E
LIM ITE D O U TPU T R E SP O N S E
2 . 1 0
2 . 0 5
2 . 0 0
1 . 9 5
1 . 9 0
1 . 8 5
1 . 8 0
1 . 7 5
1 . 7 0
1 . 6 5
1 . 6 0
2 . 5
2 . 0
V
=
− V
= 2 . 0 V
= + 2
H
L
G
1 . 5
V
V
I
O
N
1 . 0
V
O
0 . 5
0
− 0 . 5
− 1 . 0
− 1 . 5
− 2 . 0
− 2 . 5
T im e (5 0 n s /d iv )
T im e (2 00 ns/div)
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 V
Common-mode input voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V
V
ID
CC
CC
Differential input voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ID
Limiter voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V − 0.7 V)
S
Operating free-air temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
Junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
J
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN NOM
MAX
6
UNIT
Split-Rail Operation
5
Operating voltage
V
Single-Supply Operation
5
12
Operating free-air temperature
−55
125
°C
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢄ ꢅ
ꢆꢇꢈ ꢉ ꢊꢋꢌ ꢂꢈꢇ ꢋꢍꢉꢂꢎꢏ ꢐ ꢑꢈ ꢒ ꢐꢎ ꢂ ꢇꢒ
ꢓꢀ ꢏꢉꢂꢌ ꢐ ꢏ ꢈꢅ ꢈꢉ ꢈꢇ ꢌ ꢂꢅ ꢁ ꢏꢈ ꢔꢈ ꢐꢕ
SGLS144B − APRIL 2003 − DECEMBER 2006
electrical characteristics, V
noted) (see Note 1)
= 5 V, V
= 0 V, R = 500 Ω, limiter pins open (unless otherwise
CC
ICM L
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC Performance (see Figure 1)
V
V
V
V
V
< 0.2 Vp-p,
< 0.2 Vp-p,
< 0.2 Vp-p,
< 0.2 Vp-p
= 0.2 V
G = +1,
G = +2
G = −1
R
R
= 25 Ω
450
215
215
250
30
O
O
O
O
O
F
F
Small signal bandwidth
MHz
Gain-bandwidth product (G w 5)
Bandwidth for 0.1 dB gain flatness
Gain peaking
MHz
MHz
dB
G = +1,
V
O
< 0.2 Vp-p,
= 25 Ω
11
Large signal bandwidth
Slew rate
V
= 4 Vp-p,
V
V
= −V = 2.5 V
145
1000
1.9
8
MHz
V/µs
ns
O
H
L
4 V step,
0.2 V step
2 V step
= −V = 2.5 V
L
H
Rise and fall time
Settling time to 0.05%
Spurious free dynamic range
Differential gain
ns
V
O
= 2 Vp-p,
= 500 Ω,
= 500 Ω,
f = 5 MHz
66
dB
R
R
NTSC, PAL
NTSC, PAL
0.02
0.01
6.3
2
%
L
L
Differential phase
°
Input noise, voltage noise density
Input noise, current noise density
DC Performance
f w 1 MHz
f w 1 MHz
nV/√Hz
pA/√Hz
T
= 25°C
46
43
52
2
A
Open-loop voltage gain (AVOL)
V
O
=
0.5 V
dB
mV
µA
µA
T
A
= Full range
= 25°C
T
A
8
11
12
20
2
Input offset voltage (V
IO
)
T
A
= Full range
= 25°C
T
A
6
Input bias current (I ) (See Note 2)
IB
T
A
= Full range
= 25°C
T
A
0.3
Input offset current (I
)
IO
T
A
= Full range
4
Input
T
= 25°C
50
47
57
A
Common-mode rejection ratio
(CMRR)
V
ICM
=
0.5 V,
Input referred
dB
V
T
A
= Full range
= 25°C
T
A
3.2
3.1
3.3
Common-mode input voltage range
(V
ICR
) (See Note 3)
T
A
= Full range
0.4
1
MΩ
Input impedance, differential mode
Input impedance, common mode
pF
1
1
MΩ
pF
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SGLS144B − APRIL 2003 − DECEMBER 2006
electrical characteristics, V
= 5 V, V
= 0 V, R = 500 Ω, limiter pins open (unless otherwise
CC
ICM L
noted) (see Note 1) (continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
4.1
MAX
UNIT
Output
T
= 25°C
3.9
3.7
90
A
Output voltage range (V
, V
)
V
H
V
H
V
H
= 4.3 V, V = −4.3 V,
L
R
L
R
L
R
L
500 Ω
= 20 Ω
V
OH OL
T
A
= Full range
= 25°C
T
A
105
−85
0.2
Current output, sourcing (I
OH
)
= 4.3 V, V = −4.3 V,
mA
L
T
A
= Full range
= 25°C
80
T
A
−70
−60
Current output, sinking (I
)
= 4.3 V, V = −4.3 V,
= 20 Ω
mA
OL
L
T
A
= Full range
Closed-loop output impedance
G = +1, R = 25 Ω, f < 100 kHz
Ω
F
Power Supply
Operating voltage (V
CC
)
5
6
17
20
V
T
= 25°C
14
11
58
55
15.8
A
Quiescent current (I
CC
)
mA
T
A
= Full range
= 25°C
T
A
70
dB
dB
Power supply rejection ratio (PSRR)
Input referred,
VS = 4.5 V to 5.5 V
T
A
= Full range
Output Voltage Limiters (pins 5 and 8)
T
= 25°C
3
3.3
A
Default output limited voltage
Limiter output offset voltage
Limiter pins open
(V − V ) or (V − V )
V
T
= Full range
= Full range
= 25°C
A
2.8
A
T
A
15
54
50
65
70
mV
µA
O
H
O
L
T
35
31
Limiter input bias current magnitude
(See Note 4)
V
O
= 0 V
T
A
= Full range
2
1
MΩ
pF
Limiter input impedance
Limiter feedthrough (See Note 5)
Maximum limiter voltage
f = 5 MHz
−60
dB
V
4.3
Minimum limiter voltage separation
400
mV
Op amp bias current shift
(See Note 2)
3
µA
Limiter small signal bandwidth
Limter slew rate (See Note 6)
Limiter step response, overshoot
V = 2 V, V < 0.02 Vp-p
450
100
250
2.4
30
MHz
V/µs
mV
ns
I
O
V = 2 V
I
Limiter step response, recovery time V = 2 V
I
Linearity guardband (See Note 7)
V
O
= 2 Vp-p,
f = 5 MHz
mV
NOTES: 1. All typical limits are at T = 25°C unless otherwise specified.
A
2. Current is considered positive out of node.
3. CMIR tested as < 3dB degradation from minimum CMRR at specified limits.
4. IVH (VH bias current) is positive, and IVL (VL bias current) is negative, under these conditions. See Note 3, Figure 30 and Figure 37.
5. Limiter feedthrough is the ratio of the output magnitude to the sinewave added to VH (or VL) when VIN = 0.
6. VH slew rate conditions are: VIN = +2 V, G = +2, VL = −2 V, VH = step between 2 V and 0 V. VL slew rate conditions are similar.
7. Linearity Guardband is defined for an output sinusoid (f = 5 MHz, VO = 0 VDC 1 VP-P) centered between the limiter levels (VH and
VL). It is the difference between the limiter level and the peak output voltage where SFDR decreases by 3dB (see Figure 38).
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢄ ꢅ
ꢆꢇꢈ ꢉ ꢊꢋꢌ ꢂꢈꢇ ꢋꢍꢉꢂꢎꢏ ꢐ ꢑꢈ ꢒ ꢐꢎ ꢂ ꢇꢒ
ꢓꢀ ꢏꢉꢂꢌ ꢐ ꢏ ꢈꢅ ꢈꢉ ꢈꢇ ꢌ ꢂꢅ ꢁ ꢏꢈ ꢔꢈ ꢐꢕ
SGLS144B − APRIL 2003 − DECEMBER 2006
electrical characteristics, V
noted) (see Note 1)
= 5 V, V
= 2.5 V, R = 500 Ω, limiter pins open (unless otherwise
CC
ICM L
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC Performance (see Figure 2)
V
V
V
V
V
V
V
< 0.2 Vp-p,
< 0.2 Vp-p,
< 0.2 Vp-p,
< 0.2 Vp-p
< 0.2 Vp-p,
< 0.2 Vp-p
< 2 Vp-p
G = +1,
G = +2
G = −1
R
R
= 25 Ω
= 25 Ω
375
200
190
230
10
O
O
O
O
O
O
O
F
F
Small signal bandwidth
MHz
Gain bandwidth product (G w +5)
Gain peaking
MHz
dB
G = +1,
Bandwidth for 0.1 dB gain flatness
Large signal bandwidth
Slew rate
30
MHz
MHz
V/µs
ns
200
820
2.3
12
2 V step
0.2 V step
1 V step
Rise and fall time
Settling time to 0.05%
ns
Spurious free dynamic range
Input noise, voltage noise density
Input noise, current noise density
DC Performance
V
= 2 Vp-p,
f = 5 MHz
64
dB
O
f > 1 MHz
f > 1 MHz
6.3
2
nV/√Hz
pA/√Hz
T
= 25°C
46
43
52
2
A
Open-loop voltage gain (AVOL)
V
O
=
0.4 V
dB
mV
µA
µA
T
A
= Full range
= 25°C
T
A
8
11
12
20
2
Input offset voltage (V
IO
)
T
A
= Full range
= 25°C
T
A
6
Input bias current (I
)
IB
T
A
= Full range
= 25°C
T
A
0.3
Input offset current (I
)
IO
T
A
= Full range
4
Input
T
= 25°C
48
45
55
A
Common-mode rejection ratio
(CMRR)
V
ICM
=
0.5 V,
Input referred
dB
V
T
A
= Full range
V
V
ICM
ICM
T
A
= 25°C
0.7 V
0.8 V
Common-mode input voltage range
(V
ICR
) (See Note 3)
V
ICM
0.6 V
T
A
= Full range
0.4
1
MΩ
pF
Input impedance, differential mode
1
1
MΩ
pF
Input impedance, common mode
Output
V
ICM
1.4 V
V
ICM
T
A
= 25°C
1.6 V
V
R
= V
w 500 Ω
+ 1.8 V, V = V
ICM
− 1.8 V,
H
L
ICM
L
Output voltage range (V
, V
OH OL
)
V
V
1.3 V
ICM
T
A
= Full range
T
= 25°C
60
50
70
−60
0.2
A
Current output, sourcing (I
OH
)
V
V
=
=
2.5 V,
2.5 V,
R
R
= 20 Ω
L
mA
CC
T
A
= Full range
= 25°C
T
A
−50
−40
Current output, sinking (I
)
= 20 Ω
mA
OL
CC
L
T
A
= Full range
Closed-loop output impedance
G = +1,
R
= 25 Ω,
f < 100 kHz
Ω
F
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SGLS144B − APRIL 2003 − DECEMBER 2006
electrical characteristics, V
= 5 V, V
= 2.5 V, R = 500 Ω, limiter pins open (unless otherwise
CC
ICM L
noted) (see Note 1) (continued)
PARAMETER
Power Supply
Operating voltage (V
TEST CONDITIONS
MIN
TYP
MAX
UNIT
)
5
12
15
V
CC
T
= 25°C
11
9
13
A
Quiescent current (I
CC
)
mA
dB
T
A
= Full range
= Full range
16.5
Power supply rejection ratio (PSRR)
Input referred,
VCC = 2 V to 3 V
T
A
55
70
Output Voltage Limiters (pins 5 and 8)
V
0.6 V
V
ICM
ICM
T
A
= 25°C
V
0.9 V
Default output limited voltage
Limiter output offset voltage
Limiter pins open
V
0.4 V
ICM
T
= Full range
V
A
(V − VH) or (V − VL)
T
A
= Full range
= 25°C
15
35
50
65
85
mV
O
O
T
A
0
0
Limiter input bias current magnitude
(See Note 4)
V
O
= 2.5 V
µA
T
A
= Full range
Limiter input bias current drift
Limiter input impedance
30
nA/°C
2
1
MΩ
pF
Limiter feedthrough (See Note 5)
Maximum limiter voltage
f = 5 MHz
−60
dB
V
V
ICM
1.8
Minimum limiter voltage separation
400
mV
µA
Output bias current shift
(See Note 2)
5
Limiter small signal bandwidth
Limiter slew rate (See Note 6)
Limiter step response, overshoot
V = V
1.2 V,
V < 0.02 Vp-p
O
300
20
MHz
V/µs
mV
ns
I
ICM
V = V
1.2 V
1.2 V
55
I
ICM
Limiter step response, recovery time V = V
15
I
ICM
Linearity guardband (See Note 7)
V
O
= 2 Vp-p,
f = 5 MHz
30
mV
NOTES: 1. All typical limits are at T = 25°C unless otherwise specified.
A
2. Current is considered positive out of node.
3. CMIR tested as < 3dB degradation from minimum CMRR at specified limits.
4. IVH (VH bias current) is positive, and IVL (VL bias current) is negative, under these conditions. See Note 3, Figure 31 and Figure 37.
5. Limiter feedthrough is the ratio of the output magnitude to the sinewave added to VH (or VL) when VIN = 0.
6.
V
H
slew rate conditions are: V = V
+ 0.4 V, G = +2, V = V
− 1.2 V, V = stepped between V
+ 1.2 V and V . V slew
IN ICM
L
ICM
H
ICM
ICM L
rate conditions are similar.
7. Linearity Guardband is defined for an output sinusoid (f = 5 MHz, VO = 0 VDC 1 VP-P) centered between the limiter levels (V and
H
V ). It is the difference between the limiter level and the peak output voltage where SFDR decreases by 3dB (see Figure 38).
L
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SGLS144B − APRIL 2003 − DECEMBER 2006
TYPICAL CHARACTERISTICS
FREQUENCY RESPONSE
FREQUENCY RESPONSE
6
12
9
G = −
1
∞ Ω
, R = 25
F
G = +1, R
=
C
V
= 0.2Vp−p
3
0
O
V
= 0.2Vp−p
O
6
Ω
∞
Ω
, R = 25
F
G = +1, R = 175
C
− 3
− 6
− 9
12
3
G = +2, R
=
C
0
R
S
− 3
− 6
− 9
12
15
18
150
Ω
G = −2
V
−
−
−
−
−
IN
V
O
15
R
C
G = −
5
R
F
18
−
−
−
R
G
21
∞
=
G = +5, R
C
24
1M
10M
100M
1G
1M
10M
100M
1G
Frequency (Hz)
Frequency (Hz)
Figure 1
Figure 2
LARGE−SIGNAL PULSE RESPONSE
SMALL−SIGNAL PULSE RESPONSE
2.5
2.0
1.5
1.0
0.5
0
0.25
0.20
0.15
0.10
0.05
V
= 4Vp−p
V
= 0.2Vp−p
O
O
V
= − V = 2.5V
L
H
0
−
−
−
−
−
0.5
−
−
−
−
−
0.05
0.10
0.15
0.20
0.25
1.0
1.5
2.0
2.5
Time (5ns/div)
Time (5ns/div)
Figure 3
Figure 4
V
Ñ LIMITED PULSE RESPONSE
V
−
LIMITED PULSE RESPONSE
L
H
2.5
2.0
1.5
1.0
0.5
0
2.5
2.0
1.5
1.0
0.5
0
G = +2
V
= −2 V
L
V
V
O
IN
− 0.5
− 1.0
− 1.5
− 2.0
− 2.5
− 0.5
− 1.0
− 1.5
− 2.0
− 2.5
V
V
IN
O
G
= +2
V
= +2V
H
Time (20ns/div)
Time (20ns/div)
Figure 5
Figure 6
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SGLS144B − APRIL 2003 − DECEMBER 2006
TYPICAL CHARACTERISTICS
HARMONIC DISTORTION NEAR LIMIT VOLTAGES
HARMONIC DISTORTION vs FREQUENCY
= 2 Vp-p
− 40
− 45
− 50
− 55
− 60
− 65
− 70
− 75
− 80
− 85
− 90
− 40
− 45
− 50
− 55
− 60
− 65
− 70
− 75
− 80
− 85
− 90
V
= 0V
1 Vp
DC
O
f
V
O
L
= 5 MHz
1
Ω
R
= 500
Ω
= 500
R
L
HD2
HD2
HD3
HD3
0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0
1M
10M
20M
Frequency (Hz)
Limit Voltage (V)
Figure 7
Figure 8
3RD HARMONIC DISTORTION vs OUTPUT SWING
2ND HARMONIC DISTORTION vs OUTPUT SWING
− 40
− 45
− 50
− 55
− 60
− 65
− 70
− 75
− 80
− 40
− 45
− 50
− 55
− 60
− 65
− 70
− 75
− 80
− 85
− 90
Ω
R
= 500
Ω
= 500
R
L
L
f
= 20MHz
1
f
= 10MHz
1
f
= 2MHz
1
f
= 5MHz
f
= 1MHz
1
1
f
= 10MHz
1
f
= 20MHz
1
f
= 5MHz
1
f
= 2MHz
1
f
= 1MHz
1
−
85
− 90
0.1
1.0
5.0
0.1
1.0
5.0
Output Swing (Vp−p)
Output Swing (Vp−p)
Figure 9
Figure 10
LARGE−SIGNAL FREQUENCY RESPONSE
HARMONIC DISTORTION vs LOAD RESISTANCE
V
− 40
− 45
− 50
− 55
− 60
− 65
− 70
− 75
− 80
− 85
− 90
12
9
≤
0.2Vp−p
G = +2
= 2 Vp-p
= 5MHz
O
f
1
6
HD2
HD3
3
2Vp−p
0
− 3
− 6
− 9
12
−
−
−
15
18
1M
10M
100M
1G
50
100
1000
Frequency (Hz)
Ω
Load Resistance (
)
Figure 11
Figure 12
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ꢓꢀ ꢏꢉꢂꢌ ꢐ ꢏ ꢈꢅ ꢈꢉ ꢈꢇ ꢌ ꢂꢅ ꢁ ꢏꢈ ꢔꢈ ꢐꢕ
ꢆ
SGLS144B − APRIL 2003 − DECEMBER 2006
TYPICAL CHARACTERISTICS
FREQUENCY RESPONSE vs CAPACITIVE LOAD
R
vs CAPACITIVE LOAD
S
12
9
80
70
60
50
40
30
20
10
0
C
= 0
L
V
= 0.2Vp−p
O
6
C
= 10pF
L
3
C
= 100pF
L
0
− 3
− 6
− 9
12
15
18
Ω
200
V
R
IN
S
V
L
OPA688
O
Ω
402
C
Ω
1k
−
−
−
Ω
402
Ω
1k
is optional
1M
10M
100M
1G
1
10
100
300
Frequency (Hz)
Capacitive Load (pF)
Figure 13
Figure 14
OPEN−LOOP FREQUENCY RESPONSE
100
10
1
60
50
0
−30
Gain
Phase
40
−60
Voltage Noise
30
−90
20
−120
−150
−180
−210
−240
√
6.3nV/
Hz
V
= 0.2Vp−p
Current Noise
O
10
0
√
2.0pA/
Hz
−10
−20
100
1k
10k
100k
1M
10M
10k
100k
1M
10M
100M
1G
Frequency (Hz)
Frequency (Hz)
Figure 15
Figure 16
LIMITER FEEDTHROUGH
LIMITER SMALL−SIGNAL FREQUENCY RESPONSE
−30
6
−35
−40
−45
−50
−55
−60
−65
−70
−75
−80
3
0
V
= 0.02Vp−p
O
− 3
− 6
− 9
12
V
= 0.02Vp−p + 2V
8
V
= 0.02Vp−p + 2.0V
H
DC
H
DC
200
Ω
200
Ω
2V
8
DC
V
V
O
−
−
−
−
−
O
15
402
Ω
402
Ω
18
402
Ω
402
Ω
21
24
1M
10M
50M
1M
10M
100M
1G
Frequency (Hz)
Frequency (Hz)
Figure 17
Figure 18
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SGLS144B − APRIL 2003 − DECEMBER 2006
TYPICAL CHARACTERISTICS
LIM ITER INP U T B IA S C U R R EN T vs B IAS V O LTAGE
M axim um O ver Temp erature
CLOSED−LOOP OUTPUT IMPEDANCE
1 0 0
7 5
100
10
1
G = +1
Ω
R
V
= 25
F
= 0.2Vp−p
5 0
O
2 5
M inim um O ver Tem perature
0
− 2 5
− 5 0
− 7 5
1 0 0
Lim it er H eadroom = +V
−
V
S
H
= V
−
(− V )
S
L
C urrent = I
or − I
VL
VH
0.1
−
0 . 0 0 . 5 1 . 0 1 . 5 2 .0 2 .5 3 . 0 3 . 5 4 . 0 4 . 5 5 . 0
1M
10M
100M
1G
L im ite r H e a d r o o m ( V )
Frequency (Hz)
Figure 19
Figure 20
PSR AND CMR vs TEMPERATURE
100
SUPPLY AND OUTPUT CURRENTS vs TEMPERATURE
Output Current, Sourcing
20
18
16
14
12
10
95
PSR−
90
85
80
PSRR
Supply Current
75
70
PSR+
| Output Current, Sinking
|
65
CMRR
60
55
50
70
100
−
50
−
25
0
25
50
75
100
− 50
−
25
0
25
50
75
Ambient Temperature ( C)
Ambient Temperature ( C)
°
°
Figure 21
Figure 22
VOLTAGE RANGES vs TEMPERATURE
5.0
V
= − V = 4.3V
L
H
4.5
4.0
3.5
3.0
Output Voltage Range
Common−Mode Input Range
−50
−25
0
25
50
75
100
Ambient Temperature ( C)
°
Figure 23
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SGLS144B − APRIL 2003 − DECEMBER 2006
TYPICAL CHARACTERISTICS
FREQUENCY RESPONSE
FREQUENCY RESPONSE
6
12
9
∞
Ω
G = +1, R
G = +1, R = 175
G = +2, R
=
, R
F
= 25
F
V
= 0.2Vp−p
G = − 1
C
O
3
0
V
= 0.2Vp−p
Ω
Ω
, R
= 25
O
C
6
G =
2
2
−
∞
=
C
− 3
− 6
− 9
12
3
G = − 5
0
−3
−6
−9
−12
−15
−18
R
Ω
150
−
−
−
−
−
V
IN
V
O
R
15
C
R
F
18
∞
=
G = +5, R
C
R
G
21
24
1M
10M
100M
1G
1M
1M
1M
10M
100M
1G
Frequency (Hz)
Frequency (Hz)
Figure 24
Figure 25
LARGE−SIGNAL FREQUENCY RESPONSE
V
AN D V − LIM ITED PU LSE RESPO N SE
L
H
12
9
5 . 0
4 . 5
4 . 0
3 . 5
3 . 0
2 . 5
2 . 0
1 . 5
1 . 0
0 . 5
0
G = +2
V
V
=
=
V
V
+ 1 .2 V
− 1 .2 V
H
L
C M
C M
6
≤
0.2Vp−p
3
V
V
O
IN
0
V
= 2 . 5 V
C M
−3
−6
−9
−12
−15
−18
2.0Vp−p
V
V
O
IN
10M
100M
1G
T im e ( 2 0 n s / d iv )
Frequency (Hz)
Figure 26
Figure 27
HARMONIC DISTORTION NEAR LIMIT VOLTAGES
HARMONIC DISTORTION vs FREQUENCY
= 2 Vp-p
−40
−40
−45
−50
−55
−60
−65
−70
−75
−80
−85
−90
V
= 2.5V
1Vp
O
f
V
−45
−50
−55
−60
−65
−70
−75
−80
−85
−90
O
L
= 5 MHz
1
Ω
= 500
Ω
R
= 500
R
L
HD2
HD2
HD3
HD3
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
10M
20M
| Limit Voltages − 2.5V
|
DC
Frequency (Hz)
Figure 28
Figure 29
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SGLS144B − APRIL 2003 − DECEMBER 2006
APPLICATION INFORMATION
dual-supply, non-inverting amplifier
Figure 30 shows a non-inverting gain amplifier for dual-supply operation. This circuit was used for AC
characterization of the OPA688, with a 50-Ω source, which it matches, and a 500-Ω load. The power-supply
bypass capacitors are shown explicitly in Figures 30 and 31, but will be assumed in the other figures. The limiter
voltages (V and V ) and their bias currents (I
and I ) have the polarities shown.
H
L
VH
VL
single-supply, non-inverting amplifier
Figure 31 shows an AC-coupled, non-inverting gain amplifier for single +5V supply operation. This circuit was
used for AC characterization of the OPA688, with a 50W source, which it matches, and a 500-Ω load. The
power-supply bypass capacitors are shown explicitly in Figures 30 and 31, but will be assumed in the other
figures. The limiter voltages (V and V ) and their bias currents (I and I ) have the polarities shown. Notice
H
L
VH
VL
that the single-supply circuit can use three resistors to set V and V , where the dual-supply circuit usually uses
H
L
four to reference the limit voltages to ground.
limited output, ADC input driver
Figure 32 shows a simple ADC (Analog-to-Digital Converter) driver that operates on a single supply, and gives
excellent distortion performance. The limit voltages track the input range of the converter, completely protecting
against input overdrive.
Ω
Ω
1.91k
3.01k
+V
= +5V
S
+
∝
0.1
F
∝
2.2
F
∝
0.1
F
V
= +2V
H
Ω
174
7
3
2
I
V
VH
6
IN
8
5
Ω
49.9
V
OPA688
O
Ω
I
500
VL
4
R
R
F
G
Ω
Ω
402
402
∝
∝
F
0.1
F
0.1
V
= − 2V
L
+
2.2
∝
F
Ω
Ω
1.91k
3.01k
−
V
=
−
5V
S
Figure 30. DC-Coupled, Dual Supply Amplifier
12
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ꢑ
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SGLS144B − APRIL 2003 − DECEMBER 2006
V
= +5V
S
+
∝
0.1
F
∝
2.2
F
Ω
523
∝
0.1
F
V
= 3.7V
H
Ω
806
806
∝
0.1
F
I
VH
6
7
3
Ω
∝
976
0.1
V
IN
8
F
Ω
Ω
57.6
V
O
OPA688
2
5
Ω
500
I
VL
4
R
F
Ω
402
∝
0.1
F
R
V
= 1.3V
G
L
Ω
402
Ω
523
∝
0.1
F
Figure 31. AC-Coupled, Single Supply Amplifier
V
= + 5 V
S
Ω
5 6 2
V
= + 3 . 6 V
H
V
= + 5 V
S
∝
0 . 1
F
Ω
1 0 2
+ 3 . 5 V
R E F T
Ω
7 1 5
V
= + 5 V
S
R S E L + V
S
∝
0 . 1
F
3
7
V
IN
Ω
2 4 . 9
A D S 8 2 2
8
5
1 0 −B it
D a t a
6
1 0 −B it
O P A 6 8 8
I N
4 0 M S P S
2
1 0 0 p F
4
Ω
7 1 5
R E F B
+ 1 . 5 V
IN T / E X TG N D
Ω
4 0 2
Ω
1 0 2
Ω
4 0 2
0 . 1
V
= + 1 . 4 V
L
∝
F
∝
0 . 1
F
Ω
5 6 2
Figure 32. Single Supply, Limiting ADC Input Driver
precision half wave rectifier
Figure 33 shows a half wave rectifier with outstanding precision and speed. V (pin 8) will default to a voltage
H
between 3.1 and 3.8 V if left open, while the negative limit is set to ground.
13
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SGLS144B − APRIL 2003 − DECEMBER 2006
+V
2
= +5V
7
S
Ω
200
NC
V
IN
8
6
V
OPA688
O
5
3
4
Ω
Ω
402
402
−
V
= − 5V
S
Figure 33. Precision Half Wave Rectifier
very high speed Schmitt trigger
Figure 34 shows a very high-speed Schmitt trigger. The output levels are precisely defined, and the switching
time is exceptional. The output voltage swings between 2V.
unity-gain buffer
Figure 35 shows a unity-gain voltage buffer using the OPA688. The feedback resistor (R ) isolates the output
F
from any board inductance between pins 2 and 6. We recommend that
R × 24.9W for unity-gain buffer applications. R is an optional compensation resistor that reduces the peaking
F
C
typically seen at G = +1. Choosing R = R + R gives a unity gain buffer with approximately the G = +2
C
S
F
frequency response.
DC restorer
Figure 36 shows a DC restorer using the OPA688 and OPA660. The OPA660’s OTA amplifier is used as a
Current Conveyor (CCII) in this circuit, with a current gain of 1.0.
When V tries to go below ground, CCII charges C through D , which restores the output back to ground. D
1
O
1
1
adds a propagation delay to the restoration process, which then has an exponential decay with time constant
R C /G (G = +2 = the OPA688 gain). When the signal is above ground, it decays to ground with a time constant
1 1
of R C . The OPA688 output recovers very quickly from overdrive.
2 1
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢄ ꢅ
ꢈ ꢉ ꢊꢋꢌ ꢂꢈꢇ ꢋꢍꢉꢂꢎꢏ ꢐ ꢑꢈ ꢒ ꢐꢎ ꢂ ꢇꢒ
ꢀ ꢏꢉꢂꢌ ꢐ ꢏ ꢈꢅ ꢈꢉ ꢈꢇ ꢌ ꢂꢅ ꢁ ꢏꢈ ꢔꢈ ꢐꢕ
ꢆ
ꢇ
ꢓ
SGLS144B − APRIL 2003 − DECEMBER 2006
Ω
Ω
3.01k
1.91k
+V
= +5V
S
∝
0.1
F
Ω
Ω
200
402
V
V
O
IN
7
3
2
8
6
OPA688
Ω
133
5
∝
0.1
F
4
Ω
Ω
3.01k
1.91k
− V
= − 5V
S
Figure 34. Very High Speed Schmitt Trigger
R
S
V
OPA688
V
O
S
R
C
R
F
Ω
24.9
Figure 35. Unity-Gain Buffer
C
U1
100pF
V
= +3V
8
Ω
Ω
H
200
20
5
6
+1
V
IN
D
D
1
1
2
R
V
O
OPA688
R
Ω
Q
Ω
100k
5
1k
V
= − 1V
L
Ω
(sets U1’s I )
Q
= 1N4148
R
D
= 1k
Q
1
Ω
402
, D
2
U1
C
E
Ω
R
402
Ω
20
Ω
40.2
CCII
3
B
2
Figure 36. DC Restorer
15
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ꢓ ꢀꢏꢉꢂ ꢌꢐ ꢏ ꢈ ꢅꢈ ꢉ ꢈ ꢇꢌ ꢂꢅ ꢁꢏ ꢈ ꢔꢈ ꢐ ꢕ
SGLS144B − APRIL 2003 − DECEMBER 2006
design-in tools
applications support
The Texas Instrments web site (http://www.ti.com) has the latest data sheets and other design aids.
theory of operation
The OPA688 is a voltage-feedback op amp that is unity-gain stable. The output voltage is limited to a range set
by the voltage on the limiter pins (5 and 8). When the input tries to overdrive the output, the limiters take control
of the output buffer. This avoids saturating any part of the signal path, giving quick overdrive recovery and
excellent limiter accuracy at any signal gain.
The limiters have a very sharp transition from the linear region of operation to output limiting. This allows the
limiter voltages to be set very near (< 100mV) the desired signal range. The distortion performance is also very
good near the limiter voltages.
circuit layout
Achieving optimum performance with the high-frequency OPA688 requires careful attention to layout design
and component selection. Recommended PCB layout techniques and component selection criteria are:
a)Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. Open a window in the ground
and power planes around the signal I/O pins, and leave the ground and power planes unbroken elsewhere.
b) Provide a high quality power supply. Use linear regulators, ground plane and power planes to provide
power. Place high-frequency 0.1 µF decoupling capacitors < 0.2” away from each power-supply pin. Use wide,
short traces to connect to these capacitors to the ground and power planes. Also use larger (2.2 µF to 6.8 µF)
high-frequency decoupling capacitors to bypass lower frequencies. They may be somewhat further from the
device, and be shared among several adjacent devices.
c) Place external components close to the OPA688. This minimizes inductance, ground loops, transmission
line effects and propagation delay problems. Be extra careful with the feedback (R ), input and output resistors.
F
d) Use high-frequency components to minimize parasitic elements. Resistors should be a very low reactance
type. Surface-mount resistors work best and allow a tighter layout. Metal film or carbon composition
axially-leaded resistors can also provide good performance when their leads are as short as possible. Never
use wirewound resistors for high-frequency applications. Remember that most potentiometers have large
parasitic capacitances and inductances.
Multilayer ceramic chip capacitors work best and take up little space. Monolithic ceramic capacitors also work
very well. Use RF type capacitors with low ESR and ESL. The large power pin bypass capacitors (2.2 µF to
6.8 µF) should be tantalum for better high-frequency and pulse performance.
e) Choose low resistor values to minimize the time constant set by the resistor and its parasitic parallel
capacitance. Good metal film or surface mount resistors have approximately 0.2 pF parasitic parallel
capacitance. For resistors > 1.5 kΩ, this adds a pole and/or zero below 500 MHz.
Make sure that the output loading is not too heavy. The recommended 402-Ω feedback resistor is a good starting
point in your design.
f) Use short direct traces to other wideband devices on the board. Short traces act as a lumped capacitive
load. Wide traces (50 to 100 mils) should be used. Estimate the total capacitive load at the output, and use the
series isolation resistor recommended in the typical performance curve ”R vs Capacitive Load”. Parasitic loads
S
< 2 pF may not need the isolation resistor.
16
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ꢓꢀ ꢏꢉꢂꢌ ꢐ ꢏ ꢈꢅ ꢈꢉ ꢈꢇ ꢌ ꢂꢅ ꢁ ꢏꢈ ꢔꢈ ꢐꢕ
SGLS144B − APRIL 2003 − DECEMBER 2006
g) When long traces are necessary, use transmission line design techniques (consult an ECL design
handbook for microstrip and stripline layout techniques). A 50-Ω transmission line is not required on board—a
higher characteristic impedance will help reduce output loading. Use a matching series resistor at the output
of the op amp to drive a transmission line, and a matched load resistor at the other end to make the line appear
as a resistor. If the 6 dB of attenuation that the matched load produces is not acceptable, and the line is not too
long, use the series resistor at the source only. This will isolate the source from the reactive load presented by
the line, but the frequency response will be degraded.
Multiple destination devices are best handled as separate transmission lines, each with its own series source
and shunt load terminations. Any parasitic impedances acting on the terminating resistors will alter the
transmission line match, and can cause unwanted signal reflections and reactive loading.
h) Do not use sockets for high-speed parts like the OPA688. The additional lead length and pin-to-pin
capacitance introduced by the socket creates an extremely troublesome parasitic network. Best results are
obtained by soldering the part onto the board.
power supplies
The OPA688 is nominally specified for operation using either 5-V supplies or a single +5-V supply. The
maximum specified total supply voltage of 12 V allows reasonable tolerances on the supplies. Higher supply
voltages can break down internal junctions, possibly leading to catastrophic failure. Single-supply operation is
possible as long as common mode voltage constraints are observed. The common mode input and output
voltage specifications can be interpreted as a required headroom to the supply voltage. Observing this input
and output headroom requirement will allow design of non-standard or single-supply operation circuits.
Figure 31 shows one approach to single-supply operation.
ESD protection
ESD damage has been known to damage MOSFET devices, but any semiconductor device is vulnerable to
ESD damage. This is particularly true for very high-speed, fine geometry processes.
ESD damage can cause subtle changes in amplifier input characteristics without necessarily destroying the
device. In precision operational amplifiers, this may cause a noticeable degradation of offset voltage and drift.
Therefore, ESD handling precautions are required when handling the OPA688.
output limiters
The output voltage is linearly dependent on the input(s) when it is between the limiter voltages V (pin 8) and
H
V (pin 5). When the output tries to exceed V or V , the corresponding limiter buffer takes control of the output
L
H
L
voltage and holds it at V or V .
H
L
Because the limiters act on the output, their accuracy does not change with gain. The transition from the linear
region of operation to output limiting is very sharp—the desired output signal can safely come to within 30 mV
of V or V with no onset of non-linearity.
H
L
The limiter voltages can be set to within 0.7 V of the supplies (V ≥ −V + 0.7 V, V ≤ +V − 0.7 V). They must
L
S
H
S
also be at least 400 mV apart (V − V ≥ 0.4V).
H
L
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢓ ꢀꢏꢉꢂ ꢌꢐ ꢏ ꢈ ꢅꢈ ꢉ ꢈ ꢇꢌ ꢂꢅ ꢁꢏ ꢈ ꢔꢈ ꢐ ꢕ
SGLS144B − APRIL 2003 − DECEMBER 2006
LIMITER INPUT BIAS CURRENT vs BIAS VOLTAGE
M axim um O ver Tem perature
1 0 0
7 5
5 0
2 5
M inim um O ver Tem perature
0
− 2 5
− 5 0
− 7 5
L im ite r H e a dro o m = + V
− V
H
S
= V
− (− V )
S
L
C u rre n t = I
or − I
VL
VH
−
1 0 0
0 . 0 0 . 5 1 . 0 1 . 5 2 .0 2 .5 3 . 0 3 . 5 4 . 0 4 . 5 5 . 0
L im ite r H e a d r o o m ( V )
Figure 37. Limiter Bias Current vs Bias Voltage
When pins 5 and 8 are left open, V and V go to the Default Voltage Limit; the minimum values are in the
H
L
Specifications. Looking at Figure 37 for the zero bias current case will show the expected range of (V _ default
s
limit voltages) = headroom.
When the limiter voltages are more than 2.1V from the supplies (V > −V + 2.1 V or V < +V − 2.1 V), you
L
S
H
S
can use simple resistor dividers to set V and V (see Figure 30). Make sure you include the Limiter Input Bias
H
L
Currents (Figure 37) in the calculations (i.e., I ≥ −50 µA out of pin 5, and I ≤ +50 µA out of pin 8). For good
VL
VH
limiter voltage accuracy, run at least 1-mA quiescent bias current through these resistors.
When the limiter voltages need to be within 2.1V of the supplies (V ≤ −V + 2.1 V or V ≥ +V − 2.1 V), consider
L
S
H
S
using low impedance buffers to set V and V to minimize errors due to bias current uncertainty. This will typically
H
L
be the case for single supply operation (V = +5V). Figure 31 runs 2.5 mA through the resistive divider that sets
S
V and V . This keeps errors due to I
and I < 1% of the target limit voltages.
H
L
VH
VL
The limiters’ DC accuracy depends on attention to detail. The two dominant error sources can be improved as
follows:
• Power supplies, when used to drive resistive dividers that set V and V , can contribute large errors (e.g.,
H
L
"5%). Using a more accurate source, and bypassing pins 5 and 8 with good capacitors, will improve limiter
PSRR.
• The resistor tolerances in the resistive divider can also dominate. Use 1% resistors.
Other error sources also contribute, but should have little impact on the limiters’ DC accuracy:
• Reduce offsets caused by the Limiter Input Bias Currents. Select the resistors in the resistive divider(s) as
described above.
• Consider the signal path DC errors as contributing to uncertainty in the useable output swing.
• The Limiter Offset Voltage only slightly degrades limiter accuracy.
Figure 38 shows how the limiters affect distortion performance. Virtually no degradation in linearity is observed
for output voltage swinging right up to the limiter voltages.
18
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ꢆꢇꢈ ꢉ ꢊꢋꢌ ꢂꢈꢇ ꢋꢍꢉꢂꢎꢏ ꢐ ꢑꢈ ꢒ ꢐꢎ ꢂ ꢇꢒ
ꢓꢀ ꢏꢉꢂꢌ ꢐ ꢏ ꢈꢅ ꢈꢉ ꢈꢇ ꢌ ꢂꢅ ꢁ ꢏꢈ ꢔꢈ ꢐꢕ
SGLS144B − APRIL 2003 − DECEMBER 2006
HARMONIC DISTORTION NEAR LIMIT VOLTAGES
−40
−45
−50
−55
−60
−65
−70
−75
−80
−85
−90
V
= 0V
1 Vp
O
DC
"
f
= 5 MHz
= 500
1
Ω
R
L
HD2
HD3
0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0
Limit Voltage (V)
"
Figure 38. Harmonic Distortion Near Limit Voltages
offset voltage adjustment
The circuit in Figure 39 allows offset adjustment without degrading offset drift with temperature. Use this circuit
with caution since power supply noise can inadvertently couple into the op amp.
R
+ V
2
S
R
T
R
I M
Ω
4 7 k
V
O P A 6 8 8
O
− V
∝
S
0 . 1
F
(1 )
R
1
(2 )
R
=
R
|| R
1 2
3
V
1
o r G r o u n d
I N
NOTES: (1) Set
R
<<
R
.
(2)
R
is optional and
TRIM
3
minimizes out ut poffset due to in ut bias cpurrents.
Figure 39. Offset Voltage Trim
Remember that additional offset errors can be created by the amplifier’s input bias currents. Whenever possible,
match the impedance seen by both DC input bias currents using R . This minimizes the output offset voltage
3
caused by the input bias currents.
output drive
The OPA688 has been optimized to drive 500-Ω loads, such as ADCs. It still performs very well driving 100-Ω
loads; the specifications are shown for the 500-Ω load. This makes the OPA688 an ideal choice for a wide range
of high-frequency applications.
Many high-speed applications, such as driving ADCs, require op amps with low output impedance. As shown
in the typical performance curve ”Output Impedance vs Frequency”, the OPA688 maintains very low closed-loop
output impedance over frequency. Closed-loop output impedance increases with frequency, since loop gain
decreases with frequency.
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃꢄ ꢄ ꢅ
ꢆ ꢇꢈꢉ ꢊꢋꢌꢂ ꢈ ꢇ ꢋꢍꢉꢂꢎ ꢏꢐ ꢑ ꢈ ꢒꢐ ꢎꢂꢇ ꢒ
ꢓ ꢀꢏꢉꢂ ꢌꢐ ꢏ ꢈ ꢅꢈ ꢉ ꢈ ꢇꢌ ꢂꢅ ꢁꢏ ꢈ ꢔꢈ ꢐ ꢕ
SGLS144B − APRIL 2003 − DECEMBER 2006
thermal considerations
The OPA688 will not require heat-sinking under most operating conditions. Maximum desired junction
temperature will set a maximum allowed internal power dissipation as described below. In no case should the
maximum junction temperature be allowed to exceed 150°C.
The total internal power dissipation (P ) is the sum of quiescent power (P ) and the additional power
D
DQ
dissipated in the output stage (P ) while delivering load power. P
is simply the specified no-load supply
DL
DQ
current times the total supply voltage across the part. P depends on the required output signals and loads.
DL
For a grounded resistive load, and equal bipolar supplies, it is at a maximum when the output is at 1/2 either
2
supply voltage. In this condition, P = V /(4R ) where R includes the feedback network loading. Note that
DL
S
L
L
it is the power in the output stage, and not in the load, that comprises P
.
DL
The operating junction temperature is: T = T + P
Θ
, where T is the ambient temperature.
J
A
D
JA A
For example, the maximum T for a OPA688M with G = +2, R = 402 Ω, R = 100 Ω, and V = 5 V at the
J
FB
L
S
maximum T = + 85°C is calculated as:
A
(
)
P
P
P
+ 10 V 20 mA + 200 mW
DQ
DL
2
(
)
5 V
+
+ 70 mW
ǒ
Ǔ
4 100 W ø 804 W
+ 200 mW ) 70 mW + 270 mW
D
T = 85°C + 270 mW × (119°C/W) = 117°C
J
capacitive loads
Capacitive loads, such as the input to ADCs, will decrease the amplifier’s phase margin, which may cause
high-frequency peaking or oscillations. Capacitive loads × 2 pF should be isolated by connecting a small resistor
in series with the output as shown in Figure 40. Increasing the gain from +2 will improve the capacitive drive
capabilities due to increased phase margin.
R
S
V
OPA688
O
R
C
L
L
R
L
is optional
Figure 40. Driving Capacitive Loads
In general, capacitive loads should be minimized for optimum high-frequency performance. The capacitance
of coax cable (29 pF/foot for RG-58) will not load the amplifier when the coaxial cable, or transmission line, is
terminated in its characteristic impedance.
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢓꢀ ꢏꢉꢂꢌ ꢐ ꢏ ꢈꢅ ꢈꢉ ꢈꢇ ꢌ ꢂꢅ ꢁ ꢏꢈ ꢔꢈ ꢐꢕ
SGLS144B − APRIL 2003 − DECEMBER 2006
frequency response compensation
The OPA688 is internally compensated to be unity-gain stable, and has a nominal phase margin of 60° at a gain
of +2. Phase margin and peaking improve at higher gains. Recall that an inverting gain of −1 is equivalent to
a gain of +2 for bandwidth purposes (i.e., noise gain = 2).
Standard external compensation techniques work with this device. For example, in the inverting configuration,
the bandwidth may be limited without modifying the inverting gain by placing a series RC network to ground on
the inverting node. This has the effect of increasing the noise gain at high frequencies, which limits the
bandwidth.
To maintain a wide bandwidth at high gains, cascade several op amps, or use the high gain optimized OPA689.
In applications where a large feedback resistor is required, such as photodiode transimpedance amplifier, the
parasitic capacitance from the inverting input to ground causes peaking or oscillations. To compensate for this
effect, connect a small capacitor in parallel with the feedback resistor. The bandwidth will be limited by the pole
that the feedback resistor and this capacitor create. In other high gain applications, use a three resistor ”Tee”
network to reduce the RC time constants set by the parasitic capacitances. Be careful to not increase the noise
generated by this feedback network too much.
pulse settling time
The OPA688 is capable of an extremely fast settling time in response to a pulse input. Frequency response
flatness and phase linearity are needed to obtain the best settling times. For capacitive loads, such as an ADC,
use the recommended R in the typical performance curve ”R vs Capacitive Load”. Extremely fine-scale
S
S
settling (0.01%) requires close attention to ground return current in the supply decoupling capacitors.
The pulse settling characteristics when recovering from overdrive are very good.
distortion
The OPA688’s distortion performance is specified for a 500-Ω load, such as an ADC. Driving loads with smaller
resistance will increase the distortion as illustrated in Figure 41. Remember to include the feedback network
in the load resistance calculations.
HARMONIC DISTORTION vs LOAD RESISTANCE
−40
V
f
= 2 Vp-p
= 5MHz
O
−45
−50
−55
−60
−65
−70
−75
−80
−85
−90
1
HD2
HD3
50
100
1000
Ω
Load Resistance (
)
Figure 41. 5 MHz Harmonic Distortion vs Load Resistance
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
1-Jul-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
OPA688MJD
NRND
CDIP SB
JD
8
1
TBD
POST-PLATE N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF OPA688M :
Catalog: OPA688
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 1
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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Amplifiers
Applications
Audio
Automotive
Broadband
Digital Control
Medical
Military
Optical Networking
Security
amplifier.ti.com
dataconverter.ti.com
www.dlp.com
www.ti.com/audio
Data Converters
DLP® Products
DSP
Clocks and Timers
Interface
www.ti.com/automotive
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/medical
www.ti.com/military
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
dsp.ti.com
www.ti.com/clocks
interface.ti.com
logic.ti.com
power.ti.com
microcontroller.ti.com
www.ti-rfid.com
Logic
Power Mgmt
Microcontrollers
RFID
Telephony
Video & Imaging
Wireless
RF/IF and ZigBee® Solutions www.ti.com/lprf
www.ti.com/wireless
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