OPA830-EP [TI]
低功耗单电源宽带运算放大器;
| 型号： | OPA830-EP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 低功耗单电源宽带运算放大器 放大器 运算放大器 |
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| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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OPA830-EP
SBOS655 –MARCH 2014
OPA830-EP Low-Power, Single-Supply, Wideband Operational Amplifier
1 Features
3 Description
The OPA830 is
a
low-power, single-supply,
1
•
High Bandwidth:
wideband, voltage-feedback amplifier designed to
operate on a single +5V supply. Operation on ±5V or
+10V supplies is also supported. The input range
extends below the negative supply and to within 1.7V
of the positive supply. Using complementary
common-emitter outputs provides an output swing to
within 25mV of either supply while driving 150Ω. High
output drive current (±80mA) and low differential gain
and phase errors also make them ideal for single-
supply consumer video products.
–
–
250MHz (G = +1)
110MHz (G = +2)
•
•
Low Supply Current:
3.9mA (VS = +5V)
Flexible Supply Range:
–
–
–
±1.4V to ±5.5V Dual Supply
+2.8V to +11V Single Supply
•
•
•
•
•
Input Range Includes Ground On Single Supply
4.88V Output Swing on +5V Supply
High Slew Rate: 550V/μs
Low distortion operation is ensured by the high gain
bandwidth product (110MHz) and slew rate
(550V/μs), making the OPA830 an ideal input buffer
stage to 3V and 5V CMOS ADCs. Unlike other low-
Low Input Voltage Noise: 9.2nV/√Hz
Pb-Free SOT23 Package
power,
single-supply
amplifiers,
distortion
performance improves as the signal swing is
decreased. A low 9.2nV/√Hz input voltage noise
supports wide dynamic range operation.
2 Applications
•
Single-supply Analog-to-Digital Converter (ADC)
Input Buffers
The OPA830 is available in an ultra-small SOT23-5
package.
•
•
•
•
•
Single-supply Video Line Drivers
CCD Imaging Channels
low-power Ultrasound
Device Information
ORDER NUMBER
PACKAGE
BODY SIZE
OPA830-EPDBV
SOT-23 (5)
2.9 mm x 1.6 mm
PLL Integrators
Portable Consumer Electronics
xxx
xxx
xxx
xxx
DC-Coupled, +3V ADC Driver
+5V
Ω
3.75k
+3V
374Ω
VIN
Ω
100
THS1040
10−Bit
OPA830
40MSPS
22pF
625Ω
750Ω
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA830-EP
SBOS655 –MARCH 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
Features.................................................................. 1
7
Detailed Description ............................................ 17
7.1 Overview ................................................................. 17
7.2 Functional Block Diagram ....................................... 17
7.3 Feature Description................................................. 17
Applications and Implementation ...................... 18
8.1 Application Information............................................ 18
8.2 Typical Applications ................................................ 18
Power Supply Recommendations...................... 28
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Terminal Configuration and Functions................ 3
Specifications......................................................... 3
6.1 Absolute Maximum Ratings ...................................... 3
6.2 Handling Ratings....................................................... 3
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics, VS = ±5V.......................... 4
6.6 Electrical Characteristics, VS = +5V.......................... 6
6.7 Typical Characteristics VS = ±5V .............................. 8
8
9
10 Layout................................................................... 28
10.1 Layout Guidelines ................................................. 28
10.2 Input and ESD Protection ..................................... 29
10.3 Layout Example .................................................... 30
11 Device and Documentation Support ................. 32
11.1 Trademarks........................................................... 32
11.2 Electrostatic Discharge Caution............................ 32
11.3 Glossary................................................................ 32
6.8 Typical Characteristics VS = ±5V, Differential
Configuration............................................................ 11
6.9 Typical Characteristics VS = +5V............................ 12
6.10 Typical Characteristics VS = +5V, Differential
Configuration............................................................ 16
12 Mechanical, Packaging, and Orderable
Information ........................................................... 32
4 Revision History
DATE
REVISION
NOTES
March 2014
*
Initial release
2
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SBOS655 –MARCH 2014
5 Terminal Configuration and Functions
1
2
3
5
Output
+VS
−
VS
SLM
4
Noninverting Input
Inverting Input
Terminal Orientation/Package Marking
SOT23−5
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
OUT
-VS
NO.
1
O
I
Amplifier Output
2
Negative Amplifier Power Supply Input
Non-inverting Amplifier Input
Inverting Amplifier Input
+IN
3
I
-IN
4
I
+VS
5
I
Positive Amplifier Power Supply Input
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
UNIT
Power Supply
12VDC
V
Internal Power Dissipation
Differential Input Voltage
See Thermal Analysis
±2.5
+VS + 0.3
300
V
Input Voltage Range (Single Supply)
Lead Temperature (soldering, 10s)
TJ Junction Temperature
–0.5
V
°C
°C
150
(1) These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those
indicated under Recommended Operating Conditions.
6.2 Handling Ratings
MIN
MAX
125
UNIT
°C
V
Tstg
Storage Temperature Range: D, DBV
Human Body Model (HBM)(2)
Charge Device Model (CDM)(3)
Machine Model (MM)
–65
2000
1500
200
ESD
V
Rating(1)
V
(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges in
to the device.
(2) Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows
safe manufacturing with a standard ESD control process.
(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM allows safe
manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
±5
MAX
±5.5
11
UNIT
V
Dual supply voltage
Single supply voltage
5
V
TJ
Operating junction temperature
-40
105
°C
6.4 Thermal Information
OPA830-EP
THERMAL METRIC(1)
UNIT
DBV (5 TERMINAL)
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
218.8
87.0
45.2
4.4
RθJCtop
RθJB
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
44.4
N/A
RθJCbot
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 Electrical Characteristics, VS = ±5V
At -40°C ≤ TJ ≤ 105°C, G = +2, RF = 750Ω, and RL = 150Ω to GND, unless otherwise noted (see Figure 52).
OPA830TDBV
PARAMETER
CONDITIONS
UNIT
MIN
TYP
MAX
AC PERFORMANCE (see Figure 52)(1)
G = +1, VO ≤ 0.2VPP
310
120
25
G = +2, VO ≤ 0.2VPP, -40°C to 85°C
G = +5, VO ≤ 0.2VPP, -40°C to 85°C
G = +10, VO ≤ 0.2VPP, -40°C to 85°C
G ≥ +10, -40°C to 85°C
65
15
6
Small-Signal Bandwidth
MHz
11
Gain-Bandwidth Product
Peaking at a Gain of +1
Slew Rate
80
110
6
MHz
dB
VO ≤ 0.2VPP
G = +2, 2V Step, -40°C to 85°C
0.5V Step, -40°C to 85°C
260
600
3.3
3.5
42
V/μs
ns
Rise Time
5.9
6
Fall Time
0.5V Step, -40°C to 85°C
ns
Settling Time to 0.1%
Harmonic Distortion
G = +2, 1V Step, -40°C to 85°C
VO = 2VPP, f = 5MHz, -40°C to 85°C
RL = 150Ω, -40°C to 85°C
66
ns
–67
–71
−56
−60
−48
−59
2nd-Harmonic
3rd-Harmonic
dBc
dBc
R
L ≥ 500Ω, -40°C to 85°C
RL = 150Ω, -40°C to 85°C
L ≥ 500Ω, -40°C to 85°C
–60
R
–77
Input Voltage Noise
f > 1MHz, -40°C to 85°C
f > 1MHz, -40°C to 85°C
9.5
11.5 nV/√Hz
5.7 pA/√Hz
Input Current Noise
3.7
NTSC Differential Gain
NTSC Differential Phase
0.07%
0.17
°
(1) Limits set by simulation based on −40°C to 85°C.
4
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SBOS655 –MARCH 2014
Electrical Characteristics, VS = ±5V (continued)
At -40°C ≤ TJ ≤ 105°C, G = +2, RF = 750Ω, and RL = 150Ω to GND, unless otherwise noted (see Figure 52).
OPA830TDBV
PARAMETER
CONDITIONS
UNIT
MIN
TYP
MAX
(2)
DC PERFORMANCE
RL = 150Ω
Open-Loop Voltage Gain
Input Offset Voltage
Average Offset Voltage Drift
Input Bias Current
64
74
dB
mV
±1.5
±8.6
±35
13
μV/°C
μA
VCM = 0V
VCM = 0V
5
Input Bias Current Drift
Input Offset Current
Input Offset Current Drift
INPUT
±12
nA/°C
μA
±0.1 ±1.49
±5
nA/°C
Negative Input Voltage(3)
Positive Input Voltage(3)
Common-Mode Rejection Ratio (CMRR)
Input Impedance
–5.5
3.2
80
–5.1
V
V
2.8
72
Input-Referred
dB
Differential Mode
10 || 2.1
kΩ || pF
kΩ || pF
Common-Mode
400 || 1.2
OUTPUT
G = +2, RL = 1kΩ to GND
G = +2, RL = 150Ω to GND
±4.84
±4.56
±55
±4.88
±4.64
±85
Output Voltage Swing
V
Current Output, Sinking and Sourcing
Short-Circuit Current
mA
mA
Ω
Output Shorted to Ground
150
Closed-Loop Output Impedance
POWER SUPPLY
G = +2, f ≤ 100kHz
0.06
Minimum Operating Voltage
Maximum Operating Voltage
Maximum Quiescent Current
Minimum Quiescent Current
Power-Supply Rejection Ratio (+PSRR)
±1.4
V
±5.5
5.9
V
VS = ±5V
4.25
4.25
66
mA
mA
dB
VS = ±5V
3.19
59
Input-Referred
(2) Current is considered positive out of terminal.
(3) Tested <3dB below minimum specified CMRR at ± CMIR limits.
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6.6 Electrical Characteristics, VS = +5V
At -40°C ≤ TJ ≤ 105°C, G = +2, RF = 750Ω, and RL = 150Ω to VS/2, unless otherwise noted (see Figure 51).
OPA830TDBV
PARAMETER
CONDITIONS
UNIT
MIN
TYP
MAX
AC PERFORMANCE (see Figure 51)(1)
G = +1, VO ≤ 0.2VPP
250
110
24
G = +2, VO ≤ 0.2VPP, -40°C to 85°C
G = +5, VO ≤ 0.2VPP, -40°C to 85°C
G = +10, VO ≤ 0.2VPP, -40°C to 85°C
G ≥ +10, -40°C to 85°C
68
15
6
Small-Signal Bandwidth
MHz
11
Gain-Bandwidth Product
Peaking at a Gain of +1
Slew Rate
79
110
5
MHz
dB
VO ≤ 0.2VPP, -40°C to 85°C
G = +2, 2V Step, -40°C to 85°C
0.5V Step, -40°C to 85°C
0.5V Step, -40°C to 85°C
G = +2, 1V Step, -40°C to 85°C
VO = 2VPP, f = 5MHz
260
550
3.3
3.3
43
V/μs
ns
Rise Time
5.9
5.9
67
Fall Time
ns
Settling Time to 0.1%
Harmonic Distortion
ns
RL = 150Ω, -40°C to 85°C
–62
–64
−53
−56
−48
−60
2nd-Harmonic
3rd-Harmonic
dBc
dBc
R
L ≥ 500Ω, -40°C to 85°C
RL = 150Ω, -40°C to 85°C
L ≥ 500Ω, -40°C to 85°C
–58
R
–84
Input Voltage Noise
f > 1MHz, -40°C to 85°C
f > 1MHz, -40°C to 85°C
9.2
11.2 nV/√Hz
5.5 pA/√Hz
Input Current Noise
3.5
NTSC Differential Gain
NTSC Differential Phase
DC PERFORMANCE(2)
Open-Loop Voltage Gain
Input Offset Voltage
Average Offset Voltage Drift
Input Bias Current
0.08%
0.09
°
RL = 150Ω
64
72
dB
±0.5
±6.7
±28
13
mV
μV/°C
μA
VCM =2.5V
VCM = 2.5V
+5
Input Bias Current Drift
Input Offset Current
Input Offset Current Drift
INPUT
±12
nA/°C
μA
±0.1 ±1.41
±5
nA/°C
Least Negative Input Voltage(3)
Most Positive Input Voltage(3)
Common-Mode Rejection Ratio (CMRR)
Input Impedance
–0.5
3.2
80
–0.2
V
V
2.75
72
Input-Referred
dB
Differential Mode
10 || 2.1
kΩ || pF
kΩ || pF
Common-Mode
400 || 1.2
OUTPUT
G = +5, RL = 1kΩ to 2.5V
G = +5, RL = 150Ω to 2.5V
G = +5, RL = 1kΩ to 2.5V
G = +5, RL = 150Ω to 2.5V
0.09
0.21
4.91
4.78
±80
0.13
0.26
Least Positive Output Voltage
Most Positive Output Voltage
V
V
4.87
4.72
±52
Current Output, Sinking and Sourcing
Short-Circuit Output Current
mA
mA
Ω
Output Shorted to Either Supply
140
Closed-Loop Output Impedance
G = +2, f ≤ 100kHz
0.06
(1) Limits set by simulation based on −40°C to 85°C.
(2) Current is considered positive out of terminal.
(3) Tested <3dB below minimum specified CMRR at ± CMIR limits.
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SBOS655 –MARCH 2014
Electrical Characteristics, VS = +5V (continued)
At -40°C ≤ TJ ≤ 105°C, G = +2, RF = 750Ω, and RL = 150Ω to VS/2, unless otherwise noted (see Figure 51).
OPA830TDBV
PARAMETER
CONDITIONS
UNIT
MIN
TYP
MAX
POWER SUPPLY
Minimum Operating Voltage
Maximum Operating Voltage
Maximum Quiescent Current
Minimum Quiescent Current
Power-Supply Rejection Ratio (+PSRR)
2.8
V
11
V
VS = ±5V
3.9
3.9
66
5.5
mA
mA
dB
VS = ±5V
3.05
59
Input-Referred
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6.7 Typical Characteristics VS = ±5V
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to GND, unless otherwise noted.
6
3
0
3
0
−
G = +1
G =
2
Ω
RF = 0
−
1
G =
−
3
6
9
G = +2
−
3
6
9
G = +5
−
−
−
5
G =
−
−
−
G = 10
G = +10
−
12
−
15
−
18
−
12
−
15
−
18
1
10
100
600
1
10
100
400
Frequency (MHz)
Frequency (MHz)
VO = 0.2VPP
RL = 150 Ω
See Figure 52
VO = 0.2VPP
RL = 150 Ω
Figure 1. Non-Inverting Small−Signal Frequency Response
Figure 2. Inverting Small−Signal Frequency Response
9
3
VO = 2VPP
6
3
0
VO = 1VPP
−
3
6
9
VO = 0.5VPP
0
−
−
VO = 1VPP
−
3
−
6
−
9
VO = 4VPP
VO = 2VPP
−
−
−
12
15
18
VO = 4VPP
VO = 0.5VPP
−
12
10
100
400
10
100
500
Frequency (MHz)
Frequency (MHz)
G = -1V/V
RL = 150 Ω
G = +2V/V
RL = 150 Ω
See Figure 52
Figure 4. Inverting Large−Signal Frequency Response
Figure 3. Non-Inverting Large−Signal Frequency Response
0.4
0.3
2.0
0.4
0.3
2.0
1.5
1.0
0.5
Large−Signal 1V
Right Scale
1.5
0.2
1.0
0.2
0.1
0.5
0.1
Small−Signal 100mV
Left Scale
Small−Signal 100mV
0
Left Scale
0
0
0
−0.1
−0.2
−0.3
−0.4
−0.5
−1.0
−1.5
−2.0
−0.1
−0.2
−0.3
−0.4
−0.5
−1.0
Large−Signal 1V
Right Scale
−1.5
−2.0
Time (10ns/div)
Time (10ns/div)
G = +2V/V
See Figure 52
G = -1V/V
Figure 5. Non-Inverting Pulse Response
Figure 6. Inverting Pulse Response
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Typical Characteristics VS = ±5V (continued)
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to GND, unless otherwise noted.
−
50
−
55
−
60
−
65
−
70
−
75
−
80
−
85
−
40
−
45
−
50
−
55
−
60
−
65
−
70
−
75
−
80
−
85
−
90
Input Limited for VCM = 0V
3rd−Harmonic
2nd−Harmonic
2nd−Harmonic
3rd−Harmonic
100
1000
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Ω
Resistance (
)
Supply Voltage ( VS)
f = 5MHz
See Figure 52
VO = 2VPP
G = +2V/V
VO = 2VPP
See Figure 52
RL = 500Ω
G = +2V/V
Figure 7. Harmonic Distortion vs Load Resistance
Figure 8. 5MHz Harmonic Distortion vs Supply Voltage
−
50
55
60
65
70
75
80
85
90
95
−
−
−
−
−
−
−
−
−
55
3rd−Harmonic
Ω
−
−
−
−
−
−
−
−
−
60
65
70
75
80
85
90
95
RL = 150
2nd−Harmonic
Ω
RL = 500
2nd−Harmonic
2nd−Harmonic
Ω
RL = 150
3rd−Harmonic
3rd−Harmonic
Ω
RL = 500
−
−
100
105
0.1
1
10
0.1
1
10
Frequency (MHz)
Output Voltage Swing (VPP
)
VO = 2VPP
G = +2V/V
See Figure 52
f = 5MHz
See Figure 52
RL = 500Ω
G = +2V/V
Figure 10. Harmonic Distortion vs Frequency
Figure 9. Harmonic Distortion vs Output Voltage
−
−
−
−
−
−
−
−
−
−
−
95
90
85
80
75
50
25
6.0
40
45
50
55
60
65
70
75
80
85
90
PI
PO
OPA830
Ω
50
20MHz
Ω
5.5
5.0
4.5
4.0
3.5
3.0
500
Ω
750
Ω
750
Source/Sink Output Current
Left Scale
10MHz
5MHz
Supply Current
Right Scale
−
−
25
−
26
−
20
−
14
−
−
2
50
0
25
50
75
100
125
8
6
Single−Tone Load Power (2dBm/div)
Ambient Temperature ( C)
Figure 11. Two−Tone, 3rd−Order Intermodulation Spurious
Figure 12. Supply and Output Current vs Temperature
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Typical Characteristics VS = ±5V (continued)
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to GND, unless otherwise noted.
8
7
6
5
4
3
2
1
0
120
110
100
90
CL = 10pF
CL = 100pF
CL = 1000pF
80
70
60
50
RS
VI
VO
(1)
OPA830
Ω
50
40
CL
Ω
1k
Ω
750
−
1
2
3
30
Ω
NOTE: (1) 1k is optional.
Ω
750
−
−
20
10
1
10
100
1k
1
10
Frequency (MHz)
100
200
Capacitive Load (pF)
0dB Peaking Targeted
Figure 14. Recommended RS vs Capacitive Load
Figure 13. Frequency Response vs Capacitive Load
6
6
5
4
3
2
1
0
1W Internal
5
4
3
2
1
0
Power Limit
Output
Current Limit
Ω
RL = 500
Ω
RL = 50
Ω
RL = 100
−
1
2
3
4
5
6
−
−
−
−
−
−
1
2
3
4
5
6
−
−
−
−
−
1W Internal
Power Limit
Output
Current Limit
10
100
1k
−
−
120
−
80
−
40
160
0
40
80
120
160
Ω
Resistance (
)
IO (mA)
G = +5V/V
VS = ±5V
Figure 15. Output Swing vs Load Resistance
Figure 16. Output Voltage and Current Limitations
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6.8 Typical Characteristics VS = ±5V, Differential Configuration
At TA = 25°C, G = +2, RF = 604Ω, and RL = 500Ω to GND, unless otherwise noted.
+5V
3
GD = 1
GD = 2
0
OPA830
−
3
−
6
−
9
−
5V
R G
Ω
Ω
60 4
GD = 5
60 4
V
RL
I
V O
Ω
500
+5V
GD = 10
R G
−
−
12
15
OPA830
Ω
604
=
RG
GD
1
10
100
200
−
5V
Frequency (MHz)
VO = 200mVPP
RL = 500Ω
Figure 18. Differential Small−Signal Frequency Response
Figure 17. Test Circuit
−
9
6
3
0
45
−
50
−
55
−
60
−
65
−
70
−
75
−
80
−
85
−
90
−
95
3rd−Harmonic
VO = 5VPP
VO = 2VPP
−
3
6
9
VO = 1VPP
VO = 200mVPP
−
−
2nd−Harmonic
−
100
100
1
10
100
200
150
200
250
300
350
400
450
500
Ω
Resistance (
)
Frequency (MHz)
VO = 4VPP
GD = 2
f = 5MHz
GD = 2
RL = 500Ω
Figure 20. Differential Distortion vs Load Resistance
Figure 19. Differential Large−Signal Frequency Response
−
−
−
−
−
−
−
−
−
55
60
−
40
−
50
−
60
−
70
−
80
−
90
65
3rd−Harmonic
70
75
80
3rd−Harmonic
85
2nd−Harmonic
90
95
−
−
100
110
−
100
105
2nd−Harmonic
−
1
10
0.1
1
10
100
Output Voltage Swing (VPP
)
Frequency (MHz)
GD = 2
VO = 4VPP
RL = 500Ω
GD = 2
RL = 500Ω
f = 5MHz
Figure 21. Differential Distortion vs Frequency
Figure 22. Differential Distortion vs Output Voltage
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6.9 Typical Characteristics VS = +5V
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS/2 and input VCM = 2.5V, unless otherwise noted.
6
3
0
3
0
G = +1
−
2
G =
Ω
RF = 0
−
1
G =
−
3
6
9
G = +2
−
3
6
9
G = +5
−
−
−
G =
5
−
−
−
G = 10
G = +10
−
12
−
15
−
18
−
12
−
15
−
18
1
10
100
500
1
10
100
400
Frequency (MHz)
Frequency (MHz)
VO = 0.2VPP
RL = 150Ω
See Figure 51
VO = 0.2VPP
RL = 150Ω
See Figure 56
Figure 23. Non-Inverting Small−Signal Frequency Response
Figure 24. Inverting Small−Signal Frequency Response
9
3
6
0
−
−
−
3
3
6
9
VO = 1VPP
VO = 0.5VPP
VO = 1VPP
0
VO = 0.5VPP
−
3
−
6
−
9
−
12
−
15
−
18
VO = 2VPP
VO = 2VPP
−
12
10
100
Frequency (MHz)
RL = 150Ω
500
10
100
500
Frequency (MHz)
G = +2V/V
See Figure 51
G = -1V/V
RL = 150Ω
See Figure 56
Figure 25. Non-Inverting Large−Signal Frequency Response
Figure 26. Inverting Large−Signal Frequency Response
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
2.9
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
Large−Signal 1V
Right Scale
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
Small−Signal 100mV
Left Scale
Small−Signal 100mV
Left Scale
Large−Signal 1V
Right Scale
Time (10ns/div)
Time (10ns/div)
G = +2V/V
See Figure 51
G = -1V/V
Figure 27. Non-Inverting Pulse Response
Figure 28. Inverting Pulse Response
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Typical Characteristics VS = +5V (continued)
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS/2 and input VCM = 2.5V, unless otherwise noted.
−
50
−
55
−
60
−
65
−
70
−
75
−
80
−
85
−
90
−
−
−
−
−
−
−
−
−
−
50
55
60
65
70
75
80
85
90
95
3rd−Harmonic
Ω
RL = 150
2nd−Harmonic
2nd−Harmonic
Ω
RL = 500
2nd−Harmonic
Ω
RL = 150
3rd−Harmonic
3rd−Harmonic
Ω
−
100
105
RL = 500
−
100
1000
0.1
1
10
Ω
Load Resistance (
)
Frequency (MHz)
f = 5MHz
See Figure 51
VO = 2VPP
G = +2V/V
G = +2V/V
VO = 2VPP
See Figure 51
Figure 29. Harmonic Distortion vs Load Resistance
Figure 30. Harmonic Distortion vs Frequency
−
−
−
−
−
−
−
−
−
−
−
−
55
60
65
70
75
80
85
90
45
50
55
60
65
70
75
80
85
90
95
−
Input Limited
2nd−Harmonic
−
−
−
−
−
−
2nd−Harmonic
3rd−Harmonic
3rd−Harmonic
−
100
1
10
0.1
1
10
Gain (V/V)
Output Voltage Swing (VPP
)
f = 5MHz
See Figure 51
RL = 500Ω
VO = 2VPP
f = 5MHz
See Figure 51
RL = 500Ω
G = +2V/V
Figure 32. Harmonic Distortion vs Non-nverting Gain
Figure 31. Harmonic Distortion vs Output Voltage
−
−
−
−
−
−
−
55
60
65
70
75
80
85
−
−
−
−
−
−
−
−
−
−
−
45
PI
50
55
60
65
70
75
80
85
90
95
PO
OPA830
Ω
50
20MHz
10MHz
Ω
500
Ω
750
2nd−Harmonic
Ω
750
3rd−Harmonic
5MHz
−
− − − − − − − −
26 24 22 20 18 16 14 12 10
−
8
−
6
−
−
2
1
10
4
Gain (V/V)
Single−Tone Load Power (dBm)
f = 5MHz
RL = 500Ω
VO = 2VPP
Figure 34. Two−Tone, 3rd−Order Intermodulation Spurious
Figure 33. Harmonic Distortion vs Inverting Gain
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Typical Characteristics VS = +5V (continued)
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS/2 and input VCM = 2.5V, unless otherwise noted.
100
10
1
100
10
Voltage Noise
√
(9.2nV/ Hz)
1
0.1
0.01
Current Noise
√
(3.5pA/ Hz)
10
100
1k
10k
100k
1M
10M
1k
10k
100k
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
Figure 36. Closed−Loop Output Impedance vs Frequency
Figure 35. Input Voltage and Current Noise Density
130
8
CL = 10pF
120
110
100
90
7
6
CL = 100pF
5
CL = 1000pF
4
80
3
2
1
70
60
RS
VI
50
VO
(1)
OPA830
50Ω
0
CL
1kΩ
40
Ω
750
−
1
2
3
30
750Ω
−
−
20
Ω
NOTE: (1) 1k is optional.
10
1
10
100
1k
1
10
100
300
Capacitive Load (pF)
Frequency (MHz)
0dB Peaking Targeted
Figure 37. Recommended RS vs Capacitive Load
Figure 38. Frequency Response vs Capacitive Load
80
70
60
50
40
30
20
10
0
0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
Most Positive Output Voltage
Most Positive Input Voltage
−
−
−
20
40
60
20 log (AOL
)
−80
−
−
−
−
−
−
100
120
140
160
180
200
∠ (AOL
)
Least Positive Output Voltage
−
10
20
−
−
0.5
1.0
Least Positive Input Voltage
−
−
50
0
50
110
100
1k
10k
100k
1M
10M
100M
1G
Ambient Temperature (10 C/div)
Frequency (Hz)
RL = 150Ω
RL = 150Ω
Figure 40. Voltage Ranges vs Temperature
Figure 39. Open−Loop Gain and Phase
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Typical Characteristics VS = +5V (continued)
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS/2 and input VCM = 2.5V, unless otherwise noted.
100
95
90
85
80
75
70
65
60
6.0
5.5
4
3
2
1
0
8
6
4
2
0
−
−
−
−
Input Bias Current (IB)
Quiescent Current
5.0
4.5
4.0
3.5
3.0
2.5
2.0
Output Current, Sinking
Output Current, Sourcing
×
10 Input Offset Current (IOS
)
−
1
2
3
8
2
4
6
8
−
−
−
Input Offset Voltage (VOS
)
−
50
−
25
0
25
50
75
100
125
−
−
25
50
0
25
50
75
100
125
Ambient Temperature (°C)
Ambient Temperature (°C)
RL = 150Ω
Figure 42. Supply and Output Current vs Temperature
Figure 41. Typical DC Drift Over Temperature
90
80
70
60
50
40
30
20
10
0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
CMRR
PSRR
−
0.5
1k
10k
100k
1M
10M
100M
10
100
1k
Ω
Frequency (Hz)
Load Resistance (
)
G = +5V/V
Figure 43. CMRR and PSRR vs Frequency
Figure 44. Output Swing vs Load Resistance
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6.10 Typical Characteristics VS = +5V, Differential Configuration
At TA = 25°C, G = +2, RF = 604Ω, and RL = 500Ω differential, unless otherwise noted.
+5V
3
GD = 1
GD = 2
Ω
1.2k
0
2.5V
0.1
1.2kΩ
µ
F
OPA830
−
3
6
9
R
Ω
−
−
604
G
G
D = 5
Ω
604
R
VO
L
GD = 10
VI
+5V
−
12
15
R
G
1.2kΩ
OPA830
−
2.5V
0.1µF
1
10
100
200
Ω
604
Ω
1.2k
GD
=
RG
Frequency (MHz)
VO = 200mVPP
RL = 500Ω
Figure 45. Test Circuit
Figure 46. Differential Small−Signal Frequency Response
−
−
−
−
−
40
45
50
55
60
9
6
3
0
3rd−Harmonic
VO = 3VPP
VO = 2VPP
−65
−
70
−
75
−
80
−
85
−
90
−
3
6
9
VO = 1VPP
VO = 0.2VPP
−
−
2nd−Harmonic
1
10
100
200
100
150
200
250
300
350
400
450
500
Ω
Resistance (
)
Frequency (MHz)
VO = 4VPP
GD = 2
f = 5MHz
GD = 2
RL = 500Ω
Figure 48. Differential Distortion vs Load Resistance
Figure 47. Differential Large−Signal Frequency Response
−
55
60
−
−
−
−
−
−
−
30
40
50
60
70
80
90
−
−
−
−
−
−
−
−
3rd−Harmonic
2nd−Harmonic
65
3rd−Harmonic
70
75
80
85
2nd−Harmonic
90
95
−
100
110
−
−
100
1
10
1
10
100
Output Voltage Swing (VPP
)
Frequency (MHz)
VO = 4VPP
GD = 2
RL = 500Ω
GD = 2
RL = 500Ω
f = 5MHz
Figure 49. Differential Distortion vs Frequency
Figure 50. Differential Distortion vs Output Voltage
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7 Detailed Description
7.1 Overview
The OPA830 is a unity-gain stable, very high-speed voltage-feedback op amp designed for single-supply
operation (+5V to +10V). The input stage supports input voltages below ground and to within 1.7V of the positive
supply. The complementary common-emitter output stage provides an output swing to within 25mV of ground
and the positive supply. The OPA830 is compensated to provide stable operation with a wide range of resistive
loads.
7.2 Functional Block Diagram
Vsupply+
Vin+
Vout
Vin-
Vsupply-
7.3 Feature Description
The OPA830 is a low-power, single-supply, wideband, voltage-feedback amplifier designed to operate on a
single +5V supply. Operation on ±5V or +10V supplies is also supported. The input range extends below the
negative supply and to within 1.7V of the positive supply. Using complementary common-emitter outputs
provides an output swing to within 25mV of either supply while driving 150Ω. High output drive current (±80mA)
and low differential gain and phase errors also make them ideal for single-supply consumer video products.
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8 Applications and Implementation
8.1 Application Information
The OPA830 is a unity-gain stable, very high-speed voltage-feedback operational amplifier designed for single-
supply operation (+5V to +10V). The input stage supports input voltages below ground and to within 1.7V of the
positive supply. The complementary common-emitter output stage provides an output swing to within 25mV of
ground and the positive supply. The OPA830 is compensated to provide stable operation with a wide range of
resistive loads.
8.2 Typical Applications
8.2.1 Wideband Voltage-Feedback Operation
Figure 51 shows the AC-coupled, gain of +2 configuration used for the +5V Specifications and Typical
Characteristic Curves. For test purposes, the input impedance is set to 50Ω with a resistor to ground. Voltage
swings reported in the Electrical Characteristics are taken directly at the input and output terminals. For the
circuit of Figure 51, the total effective load on the output at high frequencies is 150Ω || 1500Ω. The 1.5kΩ
resistors at the non-inverting input provide the common-mode bias voltage. Their parallel combination equals the
DC resistance at the inverting input (RF), reducing the DC output offset due to input bias current.
VS = +5V
µ
6.8 F
+
µ
0.1 F
Ω
1.50k
µ
0.1 F
2.5V
VIN
Ω
53.6
Ω
1.50k
VOUT
OPA830
RL
Ω
150
RG
RF
Ω
750
+VS
2
Ω
750
+VS/2
Figure 51. AC-Coupled, G = +2, +5V Single-Supply Specification and Test Circuit
Figure 52 shows the DC-coupled, gain of +2, dual power-supply circuit configuration used as the basis of the ±5V
Electrical Characteristics and Typical Characteristics. For test purposes, the input impedance is set to 50Ω with a
resistor to ground and the output impedance is set to 150Ω with a series output resistor. Voltage swings reported
in the specifications are taken directly at the input and output terminals. For the circuit of Figure 52, the total
effective load will be 150Ω || 1.5kΩ. Two optional components are included in Figure 52. An additional resistor
(348Ω) is included in series with the non-inverting input. Combined with the 25Ω DC source resistance looking
back towards the signal generator, this gives an input bias current cancelling resistance that matches the 375Ω
source resistance seen at the inverting input (see the DC Accuracy and Offset Control section). In addition to the
usual power-supply decoupling capacitors to ground, a 0.01μF capacitor is included between the two power-
supply terminals. In practical PC board layouts, this optional capacitor will typically improve the 2nd-harmonic
distortion performance by 3dB to 6dB.
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Typical Applications (continued)
+5V
µ
0.1 F
µ
6.8 F
+
Ω
50 Source
Ω
348
VIN
Ω
150
VO
Ω
50
OPA830
µ
0.01 F
RF
Ω
750
RG
Ω
750
µ
6.8 F
µ
0.1 F
+
−
5V
Figure 52. DC-Coupled, G = +2, Bipolar Supply Specification and Test Circuit
8.2.1.1 Single-Supply ADC Interface
The ADC interface on the front page shows a DC-coupled, single-supply ADC driver circuit. Its large input and
output voltage ranges and low distortion support converters such as the THS1040 shown in the figure on page 1.
The input level-shifting circuitry was designed so that VIN can be between 0V and 0.5V, while delivering an
output voltage of 1V to 2V for the THS1040.
8.2.1.2 DC Level-Shifting
Figure 53 shows a DC-coupled non-inverting amplifier that level-shifts the input up to accommodate the desired
output voltage range. Given the desired signal gain (G), and the amount VOUT needs to be shifted up (ΔVOUT
)
when VIN is at the center of its range, the following equations give the resistor values that produce the desired
performance. Assume that R4 is between 200Ω and 1.5kΩ.
NG = G + VOUT/VS
R1 = R4/G
(1)
(2)
(3)
(4)
R2 = R4/(NG − G)
R3 = R4/(NG −1)
Where:
NG = 1 + R4/R3
(5)
(6)
VOUT = (G)VIN + (NG − G)VS
Make sure that VIN and VOUT stay within the specified input and output voltage ranges.
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Typical Applications (continued)
+VS
R2
R1
VIN
VOUT
OPA830
R3
R4
Figure 53. DC Level-Shifting
The circuit on the front page is a good example of this type of application. It was designed to take VIN between
0V and 0.5V and produce VOUT between 1V and 2V when using a +5V supply. This means G = 2.00, and ΔVOUT
= 1.50V − G × 0.25V = 1.00V. Plugging these values into the above equations (with R4 = 750Ω) gives: NG = 2.2,
R1 = 375Ω, R2 = 3.75kΩ, and R3 = 625Ω. The resistors were changed to the nearest standard values for the front
page circuit.
8.2.1.3 AC-Coupled Output Video Line Driver
Low-power and low-cost video line drivers often buffer digital-to-analog converter (DAC) outputs with a gain of 2
into a doubly-terminated line. Those interfaces typically require a DC blocking capacitor. For a simple solution,
that interface often has used a very large value blocking capacitor (220μF) to limit tilt, or SAG, across the frames.
One approach to creating a very low high-pass pole location using much lower capacitor values is shown in
Figure 54. This circuit gives a voltage gain of 2 at the output terminal with a high-pass pole at 8Hz. Given the
150Ω load, a simple blocking capacitor approach would require a 133μF value. The two much lower valued
capacitors give this same low-pass pole using this simple SAG correction circuit of Figure 54.
+5V
Ω
1.87k
Video DAC
µ
47
F
Ω
75
VO
OPA830
Ω
78.7
Ω
75 Load
µ
22
F
Ω
845
Ω
Ω
325
528
Ω
650
Figure 54. Video Line Driver with SAG Correction
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Typical Applications (continued)
8.2.1.4 Design Requirements
For the non-inverting amplifier with reduced peaking design, the design parameters needed in Figure 59 with
noise gain = 2 are listed in Table 1.
Table 1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
RT
RF
RC
20 Ω
20 Ω
40.2 Ω
8.2.1.5 Detailed Design Procedure
8.2.1.5.1 Demonstration Boards
Two printed circuit boards (PCBs) are available to assist in the initial evaluation of circuit performance using the
OPA830 in its two package options. Both of these are offered free of charge as unpopulated PCBs, delivered
with a user’s guide. The summary information for these fixtures is shown in Table 2.
Table 2. Demonstration Fixtures by Package
PRODUCT
OPA830ID
PACKAGE
SO-8
ORDERING NUMBER
DEM-OPA-SO-1A
LITERATURE NUMBER
SBOU009
OPA830IDBV
SOT23-5
DEM-OPA-SOT-1A
SBOU010
The demonstration fixtures can be requested at the Texas Instruments web site (www.ti.com) through the
OPA830 product folder.
+5V
100pF
Ω
1.87k
µ
0.1
F
Ω
Ω
432
137
VI
4VI
OPA830
150pF
Ω
1.87k
1MHz, 2nd−Order
Butterworth Filter
Ω
1.5k
Ω
500
µ
0.1
F
Figure 55. Single-Supply, High-Frequency Active Filter
8.2.1.5.2 Macromodel and Applications Support
Computer simulation of circuit performance using SPICE is often a quick way to analyze the performance of the
OPA830 and its circuit designs. This is particularly true for video and RF amplifier circuits where parasitic
capacitance and inductance can play a major role on circuit performance. A SPICE model for the OPA830 is
available through the product folder on www.ti.com. The applications department is also available for design
assistance. These models predict typical small signal AC, transient steps, DC performance, and noise under a
wide variety of operating conditions. The models include the noise terms found in the electrical specifications of
the data sheet. These models do not attempt to distinguish between the package types in their small-signal AC
performance.
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8.2.1.5.3 Operating Suggestions
8.2.1.5.3.1 Optimizing Resistor Values
Since the OPA830 is a unity-gain stable, voltage-feedback op amp, a wide range of resistor values may be used
for the feedback and gain setting resistors. The primary limits on these values are set by dynamic range (noise
and distortion) and parasitic capacitance considerations. For a non-inverting unity-gain follower application, the
feedback connection should be made with a direct short.
Below 200Ω, the feedback network will present additional output loading which can degrade the harmonic
distortion performance of the OPA830. Above 1kΩ, the typical parasitic capacitance (approximately 0.2pF)
across the feedback resistor may cause unintentional band limiting in the amplifier response.
A good rule of thumb is to target the parallel combination of RF and RG (see Figure 52) to be less than about
400Ω. The combined impedance RF || RG interacts with the inverting input capacitance, placing an additional pole
in the feedback network, and thus a zero in the forward response. Assuming a 2pF total parasitic on the inverting
node, holding RF || RG < 400Ω will keep this pole above 200MHz. By itself, this constraint implies that the
feedback resistor RF can increase to several kΩ at high gains. This is acceptable as long as the pole formed by
RF and any parasitic capacitance appearing in parallel is kept out of the frequency range of interest.
In the inverting configuration, an additional design consideration must be noted. RG becomes the input resistor
and therefore the load impedance to the driving source. If impedance matching is desired, RG may be set equal
to the required termination value. However, at low inverting gains, the resultant feedback resistor value can
present a significant load to the amplifier output. For example, an inverting gain of 2 with a 50Ω input matching
resistor (RG) would require a 100Ω feedback resistor, which would contribute to output loading in parallel with the
external load. In such a case, it would be preferable to increase both the RF and RG values, and then achieve the
input matching impedance with a third resistor to ground (see Figure 56). The total input impedance becomes the
parallel combination of RG and the additional shunt resistor.
8.2.1.5.3.2 Bandwidth vs Gain: Non-Inverting Operation
Voltage-feedback op amps exhibit decreasing closed-loop bandwidth as the signal gain is increased. In theory,
this relationship is described by the Gain Bandwidth Product (GBP) shown in the specifications. Ideally, dividing
GBP by the non-inverting signal gain (also called the Noise Gain, or NG) will predict the closed-loop bandwidth.
In practice, this only holds true when the phase margin approaches 90°, as it does in high-gain configurations. At
low gains (increased feedback factors), most amplifiers will exhibit a more complex response with lower phase
margin. The OPA830 is compensated to give a slightly peaked response in a non-inverting gain of 2 (see
Figure 52). This results in a typical gain of +2 bandwidth of 110MHz, far exceeding that predicted by dividing the
110MHz GBP by 2. Increasing the gain will cause the phase margin to approach 90° and the bandwidth to more
closely approach the predicted value of (GBP/NG). At a gain of +10, the 11MHz bandwidth shown in the
Electrical Characteristics agrees with that predicted using the simple formula and the typical GBP of 110MHz.
Frequency response in a gain of +2 may be modified to achieve exceptional flatness simply by increasing the
noise gain to 3. One way to do this, without affecting the +2 signal gain, is to add an 2.55kΩ resistor across the
two inputs, as shown in Figure 59. A similar technique may be used to reduce peaking in unity-gain (voltage
follower) applications. For example, by using a 750Ω feedback resistor along with a 750Ω resistor across the two
op amp inputs, the voltage follower response will be similar to the gain of +2 response of . Further reducing the
value of the resistor across the op amp inputs will further dampen the frequency response due to increased noise
gain. The OPA830 exhibits minimal bandwidth reduction going to single-supply (+5V) operation as compared
with ±5V. This minimal reduction is because the internal bias control circuitry retains nearly constant quiescent
current as the total supply voltage between the supply terminals is changed.
8.2.1.5.3.3 Inverting Amplifier Operation
All of the familiar op amp application circuits are available with the OPA830 to the designer. See Figure 56 for a
typical inverting configuration where the I/O impedances and signal gain from Figure 51 are retained in an
inverting circuit configuration. Inverting operation is one of the more common requirements and offers several
performance benefits. It also allows the input to be biased at VS/2 without any headroom issues. The output
voltage can be independently moved to be within the output voltage range with coupling capacitors, or bias
adjustment resistors.
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+5V
+
µ
0.1 F
µ
6.8 F
2RT
1.5k
Ω
Ω
150
+VS
2
OPA830
2RT
µ
0.1 F
Ω
1.5k
Ω
50 Source
RG
RF
Ω
750
µ
0.1 F
Ω
374
RM
Ω
57.6
Figure 56. AC-Coupled, G = –2 Example Circuit
In the inverting configuration, three key design considerations must be noted. The first consideration is that the
gain resistor (RG) becomes part of the signal channel input impedance. If input impedance matching is desired
(which is beneficial whenever the signal is coupled through a cable, twisted pair, long PC board trace, or other
transmission line conductor), RG may be set equal to the required termination value and RF adjusted to give the
desired gain. This is the simplest approach and results in optimum bandwidth and noise performance.
However, at low inverting gains, the resulting feedback resistor value can present a significant load to the
amplifier output. For an inverting gain of 2, setting RG to 50Ω for input matching eliminates the need for RM but
requires a 100Ω feedback resistor. This configuration has the interesting advantage of the noise gain becoming
equal to 2 for a 50Ω source impedance—the same as the non-inverting circuits considered above. The amplifier
output will now see the 100Ω feedback resistor in parallel with the external load. In general, the feedback resistor
should be limited to the 200Ω to 1.5kΩ range. In this case, it is preferable to increase both the RF and RG values,
as shown in Figure 56, and then achieve the input matching impedance with a third resistor (RM) to ground. The
total input impedance becomes the parallel combination of RG and RM.
The second major consideration, touched on in the previous paragraph, is that the signal source impedance
becomes part of the noise gain equation and hence influences the bandwidth. For the example in Figure 56, the
RM value combines in parallel with the external 50Ω source impedance (at high frequencies), yielding an effective
driving impedance of 50Ω || 57.6Ω = 26.8Ω. This impedance is added in series with RG for calculating the noise
gain. The resulting noise gain is 2.87 for Figure 56, as opposed to only 2 if RM could be eliminated as discussed
above. The bandwidth will therefore be lower for the gain of −2 circuit of Figure 56 (NG = +2.87) than for the gain
of +2 circuit of Figure 51.
The third important consideration in inverting amplifier design is setting the bias current cancellation resistors on
the non-inverting input (a parallel combination of RT = 750Ω). If this resistor is set equal to the total DC
resistance looking out of the inverting node, the output DC error, due to the input bias currents, will be reduced to
(Input Offset Current) times RF. With the DC blocking capacitor in series with RG, the DC source impedance
looking out of the inverting mode is simply RF = 750Ω for Figure 56. To reduce the additional high-frequency
noise introduced by this resistor and power-supply feed-through, RT is bypassed with a capacitor.
8.2.1.5.3.4 Output Current and Voltages
The OPA830 provides outstanding output voltage capability. For the +5V supply, under no-load conditions at
+25°C, the output voltage typically swings closer than 90mV to either supply rail.
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The minimum specified output voltage and current specifications over temperature are set by worst-case
simulations at the cold temperature extreme. Only at cold startup will the output current and voltage decrease to
the numbers shown in the ensured tables. As the output transistors deliver power, their junction temperatures will
increase, decreasing their VBEs (increasing the available output voltage swing) and increasing their current gains
(increasing the available output current). In steady-state operation, the available output voltage and current will
always be greater than that shown in the over-temperature specifications, since the output stage junction
temperatures will be higher than the minimum specified operating ambient.
To maintain maximum output stage linearity, no output short-circuit protection is provided. This will not normally
be a problem, since most applications include a series matching resistor at the output that will limit the internal
power dissipation if the output side of this resistor is shorted to ground. However, shorting the output terminal
directly to the adjacent positive power-supply terminal (8-terminal packages) will, in most cases, destroy the
amplifier. If additional short-circuit protection is required, consider a small series resistor in the power-supply
leads. This will reduce the available output voltage swing under heavy output loads.
8.2.1.5.3.5 Driving Capacitive Loads
One of the most demanding and yet very common load conditions for an op amp is capacitive loading. Often, the
capacitive load is the input of an ADC—including additional external capacitance which may be recommended to
improve ADC linearity. A high-speed, high open-loop gain amplifier like the OPA830 can be very susceptible to
decreased stability and closed-loop response peaking when a capacitive load is placed directly on the output
terminal. When the primary considerations are frequency response flatness, pulse response fidelity, and/or
distortion, the simplest and most effective solution is to isolate the capacitive load from the feedback loop by
inserting a series isolation resistor between the amplifier output and the capacitive load
The Typical Characteristic curves show the recommended RS versus capacitive load and the resulting frequency
response at the load. Parasitic capacitive loads greater than 2pF can begin to degrade the performance of the
OPA830. Long PC board traces, unmatched cables, and connections to multiple devices can easily exceed this
value. Always consider this effect carefully, and add the recommended series resistor as close as possible to the
output terminal (see the Layout Guidelines section).
The criterion for setting this RS resistor is a maximum bandwidth, flat frequency response at the load. For a gain
of +2, the frequency response at the output terminal is already slightly peaked without the capacitive load,
requiring relatively high values of RS to flatten the response at the load. Increasing the noise gain will also reduce
the peaking (see Figure 59).
8.2.1.5.3.6 Distortion Performance
The OPA830 provides good distortion performance into a 150Ω load. Relative to alternative solutions, it provides
exceptional performance into lighter loads and/or operating on a single +5V supply. Generally, until the
fundamental signal reaches very high frequency or power levels, the 2nd-harmonic will dominate the distortion
with a negligible 3rd-harmonic component. Focusing then on the 2nd-harmonic, increasing the load impedance
improves distortion directly. Remember that the total load includes the feedback network; in the non-inverting
configuration (see Figure 52) this is sum of RF + RG, while in the inverting configuration, only RF needs to be
included in parallel with the actual load. Running differential suppresses the 2nd-harmonic, as shown in the
differential typical characteristic curves.
8.2.1.5.3.7 Noise Performance
High slew rate, unity-gain stable, voltage-feedback op amps usually achieve their slew rate at the expense of a
higher input noise voltage. The 9.2nV/√Hz input voltage noise for the OPA830 however, is much lower than
comparable amplifiers. The input-referred voltage noise and the two input-referred current noise terms
(2.8pA/√Hz) combine to give low output noise under a wide variety of operating conditions. Figure 57 shows the
op amp noise analysis model with all the noise terms included. In this model, all noise terms are taken to be
noise voltage or current density terms in either nV/√Hz or pA/√Hz.
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ENI
EO
OPA830
RS
IBN
ERS
RF
√
4kTRS
√
4kTRF
IBI
RG
4kT
RG
−
4kT = 1.6E 20J
at 290 K
Figure 57. Noise Analysis Model
The total output spot noise voltage can be computed as the square root of the sum of all squared output noise
voltage contributors. Equation 7 shows the general form for the output noise voltage using the terms shown in
Figure 57:
2
2
)
2
EO
=
ENI + IBNRS + 4kTRS NG2 + I R
+ 4kTR NG
F
(
(BI F )
)
(
(7)
Dividing this expression by the noise gain (NG = (1 + RF/RG)) will give the equivalent input-referred spot noise
voltage at the non-inverting input, as shown in Equation 8:
I R
æ
ö2
4kTRF
NG
2
)
2
BI F
NG
EN
=
ENI + IBNRS + 4kTR +
+
(
ç
ç
÷
÷
S
è
ø
(8)
Evaluating these two equations for the circuit and component values shown in Figure 51 will give a total output
spot noise voltage of 19.3nV/√Hz and a total equivalent input spot noise voltage of 9.65nV/√Hz. This is including
the noise added by the resistors. This total input-referred spot noise voltage is not much higher than the
9.2nV/√Hz specification for the op amp voltage noise alone.
8.2.1.5.4 DC Accuracy and Offset Control
The balanced input stage of a wideband voltage-feedback op amp allows good output DC accuracy in a wide
variety of applications. The power-supply current trim for the OPA830 gives even tighter control than comparable
products. Although the high-speed input stage does require relatively high input bias current (typically 5μA out of
each input terminal), the close matching between them may be used to reduce the output DC error caused by
this current. This is done by matching the DC source resistances appearing at the two inputs. Evaluating the
configuration of Figure 52 (which has matched DC input resistances), using worst-case +25°C input offset
voltage and current specifications, gives a worst-case output offset voltage equal to:
(NG = non-inverting signal gain at DC) ± (NG × VOS(MAX)) + (RF × IOS(MAX)) = ±(2 × 7mV) × (375Ω × 1μA) = ±14.38mV
(9)
A fine-scale output offset null, or DC operating point adjustment, is often required. Numerous techniques are
available for introducing DC offset control into an op amp circuit. Most of these techniques are based on adding a
DC current through the feedback resistor. In selecting an offset trim method, one key consideration is the impact
on the desired signal path frequency response. If the signal path is intended to be non-inverting, the offset
control is best applied as an inverting summing signal to avoid interaction with the signal source. If the signal
path is intended to be inverting, applying the offset control to the non-inverting input may be considered. Bring
the DC offsetting current into the inverting input node through resistor values that are much larger than the signal
path resistors. This will insure that the adjustment circuit has minimal effect on the loop gain and hence the
frequency response.
8.2.1.5.5 Thermal Analysis
Maximum desired junction temperature will set the maximum allowed internal power dissipation, as described
below. In no case should the maximum junction temperature be allowed to exceed 150°C.
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Operating junction temperature (TJ) is given by TA + PD × θJA. The total internal power dissipation (PD) is the sum
of quiescent power (PDQ) and additional power dissipated in the output stage (PDL) to deliver load power.
Quiescent power is simply the specified no-load supply current times the total supply voltage across the part. PDL
will depend on the required output signal and load; though, for resistive loads connected to mid-supply (VS/2),
PDL is at a maximum when the output is fixed at a voltage equal to VS/4 or 3VS/4. Under this condition,
2
PDL = VS /(16 × RL), where RL includes feedback network loading.
Note that it is the power in the output stage, and not into the load, that determines internal power dissipation.
As a worst-case example, compute the maximum TJ using an OPA830 (SOT23-5 package) in the circuit of
Figure 51 operating at the maximum specified ambient temperature of 105°C and driving a 150Ω load at mid-
supply.
PD = 11V × 5.5mA + 52/(16 × (150Ω || 750Ω)) = 73mW
(10)
(11)
Maximum TJ = 105°C + (73mW × 218.8°C/W) = 120.9°C
Although this is still well below the specified maximum junction temperature, system reliability considerations may
require lower ensured junction temperatures. The highest possible internal dissipation will occur if the load
requires current to be forced into the output at high output voltages or sourced from the output at low output
voltages. This puts a high current through a large internal voltage drop in the output transistors.
8.2.1.6 Application Curve
The input is shifted slightly positive in Figure 54 using the voltage divider from the positive supply. This gives
about a 200mV input DC offset that will show up at the output terminal as a 400mV DC offset when the DAC
output is at zero current during the sync tip portion of the video signal. This acts to hold the output in its linear
operating region. This will pass on any power-supply noise to the output with a gain of approximately −20dB, so
good supply decoupling is recommended on the power-supply terminal. Figure 58 shows the frequency response
for the circuit of Figure 54. This plot shows the 8Hz low-frequency high-pass pole and a high-end cutoff at
approximately 100MHz.
3
0
−
3
−
6
−
9
−
12
15
18
21
−
−
−
1
10
102 103 104 105 106 107 108 109
Frequency (Hz)
Figure 58. Video Line Driver Response to Matched Load
8.2.2 Non-Inverting Amplifier with Reduced Peaking
Figure 59 shows a non-inverting amplifier that reduces peaking at low gains. The resistor RC compensates the
OPA830 to have higher Noise Gain (NG), which reduces the AC response peaking (typically 5dB at G = +1
without RC) without changing the DC gain. VIN needs to be a low impedance source, such as an op amp. The
resistor values are low to reduce noise. Using both RT and RF helps minimize the impact of parasitic
impedances.
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+5V
RT
VIN
RC
VOUT
OPA830
RG
RF
Figure 59. Compensated Non-Inverting Amplifier
The Noise Gain can be calculated as follows:
RF
G1 = 1+
RG
(12)
R
F
RT +
G
1
G2 = 1+
RC
(13)
(14)
NG = G1 ´ G2
A unity-gain buffer can be designed by selecting RT = RF = 20.0Ω and RC = 40.2Ω (do not use RG). This gives a
noise gain of 2, so the response will be similar to the Characteristics Plots with G = +2. Decreasing RC to 20.0Ω
will increase the noise gain to 3, which typically gives a flat frequency response, but with less bandwidth.
The circuit in Figure 51 can be redesigned to have less peaking by increasing the noise gain to 3. This is
accomplished by adding RC = 2.55kΩ across the op amp inputs.
8.2.3 Single-Supply Active Filter
The OPA830, while operating on a single +5V supply, lends itself well to high-frequency active filter designs.
Again, the key additional requirement is to establish the DC operating point of the signal near the supply midpoint
for highest dynamic range. Figure 55 shows an example design of a 1MHz low-pass Butterworth filter using the
Sallen-Key topology.
Both the input signal and the gain setting resistor are AC-coupled using 0.1μF blocking capacitors (actually giving
bandpass response with the low-frequency pole set to 32kHz for the component values shown). As discussed for
Figure 51, this allows the midpoint bias formed by the two 1.87kΩ resistors to appear at both the input and output
terminals. The midband signal gain is set to +4 (12dB) in this case. The capacitor to ground on the non-inverting
input is intentionally set larger to dominate input parasitic terms. At a gain of +4, the OPA830 on a single supply
will show 30MHz small- and large-signal bandwidth. The resistor values have been slightly adjusted to account
for this limited bandwidth in the amplifier stage. Tests of this circuit show a precise 1MHz, −3dB point with a
maximally-flat passband (above the 32kHz AC-coupling corner), and a maximum stop band attenuation of 36dB
at the amplifier’s −3dB bandwidth of 30MHz.
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9 Power Supply Recommendations
Power supply decoupling is a critical aspect with a high-frequency amplifier design process. Careful decoupling
provides higher quality ac performance (most notably improved distortion performance). The following guidelines
ensure the highest level of performance.
1. Minimize the distance (< 0.25") from the power-supply terminals to high-frequency 0.1μF decoupling
capacitors.
2. At the device terminals, the ground and power-plane layout should not be in close proximity to the signal I/O
terminals.
3. Avoid narrow power and ground traces to minimize inductance between the terminals and the decoupling
capacitors.
4. Each powersupply connection should always be decoupled with one of these capacitors. An optional supply
decoupling capacitor (0.1μF) across the two power supplies (for bipolar operation) will improve 2nd-harmonic
distortion performance. Larger (2.2μF to 6.8μF) decoupling capacitors, effective at lower frequency, should
also be used on the main supply terminals. These may be placed somewhat farther from the device and may
be shared among several devices in the same area of the PC board.
10 Layout
10.1 Layout Guidelines
Achieving optimum performance with a high-frequency amplifier like the OPA830 requires careful attention to
board layout parasitics and external component types. Recommendations that will optimize performance include:
1. Minimize parasitic capacitance to any AC ground for all of the signal I/O terminals. Parasitic capacitance
on the output and inverting input terminals can cause instability: on the non-inverting input, it can react with
the source impedance to cause unintentional bandlimiting. To reduce unwanted capacitance, a window
around the signal I/O terminals should be opened in all of the ground and power planes around those
terminals. Otherwise, ground and power planes should be unbroken elsewhere on the board.
2. Minimize the distance (< 0.25") from the power-supply terminals to high-frequency 0.1μF decoupling
capacitors. At the device terminals, the ground and power-plane layout should not be in close proximity to
the signal I/O terminals. Avoid narrow power and ground traces to minimize inductance between the
terminals and the decoupling capacitors. Each power-supply connection should always be decoupled with
one of these capacitors. An optional supply decoupling capacitor (0.1μF) across the two power supplies (for
bipolar operation) will improve 2nd-harmonic distortion performance. Larger (2.2μF to 6.8μF) decoupling
capacitors, effective at lower frequency, should also be used on the main supply terminals. These may be
placed somewhat farther from the device and may be shared among several devices in the same area of the
PC board.
3. Careful selection and placement of external components will preserve the high-frequency
performance. Resistors should be a very low reactance type. Surface-mount resistors work best and allow a
tighter overall layout. Metal film or carbon composition axially-leaded resistors can also provide good high-
frequency performance. Again, keep their leads and PC board traces as short as possible. Never use wire-
wound type resistors in a high-frequency application. Since the output terminal and inverting input terminal
are the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if
any, as close as possible to the output terminal. Other network components, such as non-inverting input
termination resistors, should also be placed close to the package. Where double-side component mounting is
allowed, place the feedback resistor directly under the package on the other side of the board between the
output and inverting input terminals. Even with a low parasitic capacitance shunting the external resistors,
excessively high resistor values can create significant time constants that can degrade performance. Good
axial metal film or surface-mount resistors have approximately 0.2pF in shunt with the resistor. For resistor
values > 1.5kΩ, this parasitic capacitance can add a pole and/or zero below 500MHz that can effect circuit
operation. Keep resistor values as low as possible consistent with load driving considerations. The 750Ω
feedback used in the Typical Characteristics is a good starting point for design.
4. Connections to other wideband devices on the board may be made with short direct traces or through
onboard transmission lines. For short connections, consider the trace and the input to the next device as a
lumped capacitive load. Relatively wide traces (50mils to 100mils) should be used, preferably with ground
and power planes opened up around them. Estimate the total capacitive load and set RS from the typical
characteristic curve Recommended RS vs Capacitive Load. Low parasitic capacitive loads < 5pF) may not
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Layout Guidelines (continued)
need an RS since the OPA830 is nominally compensated to operate with a 2pF parasitic load. Higher
parasitic capacitive loads without an RS are allowed as the signal gain increases (increasing the unloaded
phase margin). If a long trace is required, and the 6dB signal loss intrinsic to a doubly-terminated
transmission line is acceptable, implement a matched impedance transmission line using microstrip or
stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50Ω
environment is normally not necessary onboard, and in fact, a higher impedance environment will improve
distortion as shown in the distortion versus load plots. With a characteristic board trace impedance defined
(based on board material and trace dimensions), a matching series resistor into the trace from the output of
the OPA830 is used as well as a terminating shunt resistor at the input of the destination device. Remember
also that the terminating impedance will be the parallel combination of the shunt resistor and the input
impedance of the destination device; this total effective impedance should be set to match the trace
impedance. If the 6dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can
be series-terminated at the source end only. Treat the trace as a capacitive load in this case and set the
series resistor value as shown in the typical characteristic curve Recommended RS vs Capacitive Load. This
will not preserve signal integrity as well as a doubly-terminated line. If the input impedance of the destination
device is low, there will be some signal attenuation due to the voltage divider formed by the series output into
the terminating impedance.
5. Socketing a high-speed part is not recommended. The additional lead length and terminal-to-terminal
capacitance introduced by the socket can create an extremely troublesome parasitic network which can
make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by
soldering the OPA830 onto the board.
10.2 Input and ESD Protection
The OPA830 is built using a very high-speed complementary bipolar process. The internal junction breakdown
voltages are relatively low for these very small geometry devices. These breakdowns are reflected in the
Absolute Maximum Ratings table. All device terminals are protected with internal ESD protection diodes to the
power supplies, as shown in Figure 60.
+VCC
External
Pin
Internal
Circuitry
−VCC
Figure 60. Internal ESD Protection
These diodes provide moderate protection to input overdrive voltages above the supplies as well. The protection
diodes can typically support 30mA continuous current. Where higher currents are possible (that is, in systems
with ±15V supply parts driving into the OPA830), current-limiting series resistors should be added into the two
inputs. Keep these resistor values as low as possible, since high values degrade both noise performance and
frequency response.
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10.3 Layout Example
This demonstration fixture is a two-layer PCB with the power traces on the bottom layer. Even though both sides
have a ground plane, a window has been opened up around the DUT and its surrounding components. The
purpose of this window is to reduce the parasitic capacitances between sensitive nodes and the ground planes.
The footprint of the SMA connectors were designed to use straight connectors in either a vertical or horizontal
mounting position. Note that the center conductor of the SMA must be on the top side of the board when
mounted horizontally.
Decoupling Capacitors
C1, C2, C3 & C4
DUT Area, U1.
Pin1 located on top right.
OUT
+IN
‐VS
‐IN
+VS
Figure 61. Decoupling Capacitors and DUT Area
Negative Power Supply
Positive Power Supply
Non‐Inverting Input, J1
Output, J2
Inverting Input, J3
Figure 62. Power Supply, Non-Inverting, Inverting Input and Output
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Layout Example (continued)
G = 2.
R3, R4, R7, C6 not assembled.
Figure 63. Schematics Diagram
Table 3. Component Descriptions
PART
C1, C4
C2, C3
DESCRIPTION
2.2μF, 16V, Size 3548
0.1μF, 50V, Size 1206
Feedback capacitor (optional); depends on application (not used on current feedback op
amps).
C6
R1, R2, R7
R4, R5, R6
JP1
Typically 50Ω
Depends on application
Power Connector (On-Shore Technology ED555/3DS)
SMA or SMB Connectors
J1 – J4
R3
Set to get R3 ∥ R4 = desired input impedance for inverting operation
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11 Device and Documentation Support
11.1 Trademarks
All trademarks are the property of their respective owners.
11.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA830TDBVREP
V62/14610-01XE
ACTIVE
ACTIVE
SOT-23
SOT-23
DBV
DBV
5
5
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 105
-40 to 105
SLM
SLM
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
OTHER QUALIFIED VERSIONS OF OPA830-EP :
Catalog: OPA830
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA830TDBVREP
SOT-23
DBV
5
3000
179.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOT-23 DBV
SPQ
Length (mm) Width (mm) Height (mm)
213.0 191.0 35.0
OPA830TDBVREP
5
3000
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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