OPA838IDCKT [TI]
1mA、300MHz 增益带宽、电压反馈运算放大器 | DCK | 5 | -40 to 125;
| 型号： | OPA838IDCKT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1mA、300MHz 增益带宽、电压反馈运算放大器 | DCK | 5 | -40 to 125 放大器 运算放大器 |
| 文件： | 总52页 (文件大小：3250K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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OPA838
ZHCSGM4B –AUGUST 2017–REVISED OCTOBER 2018
OPA838 1mA、300MHz 增益带宽、电压反馈运算放大器
1 特性
3 说明
1
•
增益带宽积：300MHz
极低（修整后）的电源电流：950µA
OPA838 解补偿电压反馈运算放大器只需 0.95mA 的
修整电源电流，即可以 1.8nV/√Hz 的输入噪声电压提
供高达 300MHz 的增益带宽积。这些 特性 相结合，可
为光电二极管跨阻设计和高电压增益级（它们在信号接
收器 应用中需要最低的输入电压噪声）提供极其省电
的解决方案。
•
•
•
•
•
•
•
•
•
•
带宽：90MHz (AV = 6V/V)
较高的全功率带宽：45MHz，4VPP
负轨输入，轨至轨输出
单电源工作电压范围：2.7V 至 5.4V
25°C 下的输入失调电压：±125µV（最大值）
输入失调电压漂移：< ±1.6µV/°C（最大值）
输入电压噪声：1.8nV/√Hz (> 200Hz)
输入电流噪声：1pA/√Hz (> 2000Hz)
以 6V/V 的最小建议同相增益运行时会产生 90MHz、–
3dB 带宽。极低的输入噪声和失调电压使得 OPA838
特别适合高增益。即使在 1000V/V 的直流耦合增益
下，也可获得 300kHz 的信号带宽，且最大输出失调电
压为 ±125mV。
关断电流小于 1µA，可节省电能 中的“关断电流小
于 5µA”更改成了“关断电流小于 1µA”
单通道 OPA838 采用 6 引脚 SOT-23 和 SC70 封装
（包含电源关断特性）以及 5 引脚 SC70 封装。
2 应用
•
•
•
•
•
低功耗跨阻放大器
器件信息(1)
低噪声高增益级
器件型号
封装
SOT-23 (6)
封装尺寸（标称值）
2.90mm × 1.60mm
2.00mm × 1.25mm
2.00mm × 1.25mm
12 位至 16 位低功耗 SAR ADC 驱动器
高增益有源滤波器设计
超声波流量计
OPA838
SC70 (5)
SC70 (6)
(1) 如需了解所有可用封装，请参阅产品说明书末尾的封装选项附
录。
空白
空白
3V 单电源，小于 3mW 的光电二极管放大器，具有
小于 1.1pA/√Hz 的总输入参考电流噪声，并具有总体 SSBW 为 1MHz 的 100kΩ 增益
1 pF
Large Area Photodetector
100 kꢀ
With 100-pF Capacitance
VCC = 3 V
œ
73.2 ꢀ
VOUT
2.2 nF
Diode
Current
Direction
+
1-MHz
Post Filter
-VBIAS
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOS867
OPA838
ZHCSGM4B –AUGUST 2017–REVISED OCTOBER 2018
www.ti.com.cn
目录
8.2 Functional Block Diagram ....................................... 20
8.3 Feature Description................................................. 20
8.4 Device Functional Modes........................................ 24
8.5 Power Shutdown Operation.................................... 27
Application and Implementation ........................ 28
9.1 Application Information............................................ 28
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 4
Pin Configuration and Functions......................... 4
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings.............................................................. 5
7.3 Recommended Operating Conditions....................... 5
7.4 Thermal Information.................................................. 5
7.5 Electrical Characteristics: VS = 5 V........................... 6
7.6 Electrical Characteristics: VS = 3 V........................... 8
7.7 Typical Characteristics: VS = 5 V............................ 10
7.8 Typical Characteristics: VS = 3 V............................ 13
7.9 Typical Characteristics: Over Supply Range .......... 16
Detailed Description ............................................ 20
8.1 Overview ................................................................. 20
9
10 Power Supply Recommendations ..................... 36
11 Layout................................................................... 37
11.1 Layout Guidelines ................................................. 37
11.2 Layout Example .................................................... 37
12 器件和文档支持 ..................................................... 38
12.1 器件支持 ............................................................... 38
12.2 文档支持................................................................ 38
12.3 商标....................................................................... 39
12.4 静电放电警告......................................................... 39
12.5 术语表 ................................................................... 39
13 机械、封装和可订购信息....................................... 39
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision A (February 2018) to Revision B
Page
•
•
已更改 将特性部分.................................................................................................................................................................. 1
Changed value of common-mode and differential-mode input impedance in Electrical Characterictics: VS = 5 V
and Electrical Characterictics: VS = 3 V tables....................................................................................................................... 7
•
Changed value of power-down quiescent current in Electrical Characteristics: VS = 5 V and Electrical
Characteristics: VS = 3 V tables.............................................................................................................................................. 7
•
•
•
已更改 5 µA to 1 µA in Overview section ............................................................................................................................ 20
已更改 standby current from 5 µA to 1 µA in Power-Down Operation section..................................................................... 21
已更改 common-mode input capacitance from 1.3 pF to 1 pF in Trade-Offs in Selecting The Feedback Resistor
Value section ........................................................................................................................................................................ 21
•
已更改 1 + 6.3 / 1.2 = 6.25 V/V, adding the 1.3-pF device common-mode capacitance to 1 + 6 / 1.2 = 6 V/V, adding
the 1-pF device common-mode capacitance in Trade-Offs in Selecting The Feedback Resistor Value section ................ 22
•
•
已更改 2 µA to 0.1 µA and 5 µA to 1 µA in last sentence of Power Shutdown Operation section ...................................... 27
已更改 Power Supply Recommendations and Thermal Notes title to Power Supply Recommendations ........................... 36
Changes from Original (August 2017) to Revision A
Page
•
•
•
•
•
•
•
•
Added OPA837 to the Device Comparison table ................................................................................................................... 4
Changed Device Comparison table note................................................................................................................................ 4
Changed format of pin names in pinout drawings in Pin Configuration and Functions section ............................................ 4
Added DCK to pinout description in 6-pin SOT-23 and SC70 pinout drawing....................................................................... 4
Changed I/O column header to "TYPE" in Pin Configuration and Functions section ........................................................... 4
Added table note to table to define pin types in Pin Configuration and Functions section ................................................... 4
Added table note to Absolute Maximum Ratings table ......................................................................................................... 5
Changed bandwidth for 0.1-dB flatness test condition from VOUT = 2 VPP and G = 10 to VOUT = 200 mVPP and G = 6
in the Electrical Characteristics: VS = 5 V table...................................................................................................................... 6
•
Added values for VOH and VOL parameters at TA = -40 to +125°C in Electrical Characteristics: VS = 5 V table.................... 7
2
版权 © 2017–2018, Texas Instruments Incorporated
OPA838
www.ti.com.cn
ZHCSGM4B –AUGUST 2017–REVISED OCTOBER 2018
•
•
Changed typical bandwidth for 0.1-dB flatness from 5 MHz to 9 MHz in Electrical Characteristics: VS = 3 V table ............. 8
Changed bandwidth for 0.1-dB flatness test conditions from VOUT = 2 VPP and G = 10 to VOUT = 200 mVPP and G = 6
in Electrical Characteristics: VS = 3 V table .......................................................................................................................... 8
•
•
•
•
Added values for VOH and VOL parameters at TA = -40 to +125°C in Electrical Characteristics: VS = 3 V table ................... 9
Changed VO test condition from 20 mV to 200 mV in 图 5 .................................................................................................. 10
Changed VO test condition from 20 mV to 200 mV in 图 6 .................................................................................................. 10
已更改 test conditions from VOUT = 2 VPP, RF = 0 Ω, G = 1 V/V to RF = 1 kΩ, RG = 200 Ω, RL = 2 kΩ, G = 6 V/V in
Typical Characteristics: VS = 3 V section ............................................................................................................................. 13
•
•
•
•
•
•
•
•
•
•
•
•
Changed VO test condition from 20 mV to 200 mV in 图 23 ................................................................................................ 13
Changed VO test condition from 20 mV to 200 mV in 图 24 ................................................................................................ 13
已添加 condition statement to Typical Characteristics: Over Supply Range ....................................................................... 16
已更改 Y-axis label from "Disable and Vo (Bipolar supplies)" to "Disable and VOUT (Bipolar Supplies, Volts)" in 图 51 ..... 17
已更改 Y-axis label from "PD and Output Voltages" to " Disable and VOUT (Bipolar Supplies, Volts)" in 图 52................... 17
Deleted 5-V supply and changed the Y-axis label of 图 57 ................................................................................................. 18
已更改 specification load value from 1-kΩ to 2-kΩ in Output Voltage Range section.......................................................... 21
已更改 first paragraph to correct power down logic in Power-Down Operation section....................................................... 21
已更改 image references in Power-Down Operation section ............................................................................................... 21
已更改 V1 value from 2.5 Ω to 2.5 V in 图 64....................................................................................................................... 22
已更改 V2 value from 2.5 Ω to –2.5 V in 图 64..................................................................................................................... 22
Changed V1 value from 2.5 Ω to 2.5 V, changed V2 value from 2.5 Ω to –2.5 V, and changed ROUT to RLOAD in 图
66 ........................................................................................................................................................................................ 23
•
•
•
•
•
•
•
已更改 VOUT input signal from ±.035 VOUT to ±0.35 VIN in 图 68........................................................................................... 24
Changed V1 value from 4.5 Ω to 4.5 V in 图 70................................................................................................................... 25
已更改 VEE to ground in 图 70 ............................................................................................................................................. 25
Changed V1 value from 3 Ω to 3 V in 图 72......................................................................................................................... 26
Updated Single-Supply Op Amp Design Techniques application report link in Device Functional Modes section ............. 27
已更改 "Cs" and "Cf" to "CS" and "CF" in Application Information section............................................................................ 33
Updated Transimpedance Considerations for High-Speed Amplifiers application report link in Detailed Design
Procedure section................................................................................................................................................................. 35
•
已更改 EVM guide link in Layout Guidelines section............................................................................................................ 37
Copyright © 2017–2018, Texas Instruments Incorporated
3
OPA838
ZHCSGM4B –AUGUST 2017–REVISED OCTOBER 2018
www.ti.com.cn
5
Device Comparison Table(1)
5-V IQ
(mA, MAXIMUM
25°C)
INPUT NOISE
VOLTAGE
(nV/√Hz)
2-VPP THD
(dBc, 100 kHz)
RAIL-TO-RAIL
INPUT/OUTPUT
PART NUMBER
GBP (MHz)
DUALS
OPA838
OPA837
OPA835
OPA836
LMP7717
OPA830
THS4281
300
50
0.99
0.625
0.35
1
1.9
4.7
9.3
4.8
5.8
9.5
12.5
–110
–120
–100
–115
—
Negative in/out
Negative in/out
Negative in/out
Negative in/out
Negative in/out
Negative in/out
In/out
None
OPA2837
OPA2835
OPA2836
LMP7718
OPA2830
None
30
110
88
1.4
100
38
4.7
–105
12.5
0.93
(1) For a complete selection of TI high-speed amplifiers, visit www.ti.com
6 Pin Configuration and Functions
DBV and DCK Package
6-Pin SOT-23 and SC70
Top View
DCK Package
5-Pin SC70
Top View
VOUT
VS-
VS+
1
2
3
6
5
VOUT
VS-
VS+
VIN-
1
5
4
PD
2
3
VIN-
VIN+
4
VIN+
Pin Functions
PIN
TYPE(1)
DESCRIPTION
SOT-23 and
SC70
NAME
SC70
Amplifier power down.
Low = disabled, high = normal operation (pin must be driven).
PD
5
—
I/O
VIN–
VIN+
VOUT
VS–
4
3
1
2
6
4
3
1
2
5
I/O
I/O
I/O
P
Inverting input pin
Noninverting input pin
Output pin
Negative power-supply pin
Positive power-supply input
VS+
P
(1) I = input, O = output, and P = power.
4
Copyright © 2017–2018, Texas Instruments Incorporated
OPA838
www.ti.com.cn
ZHCSGM4B –AUGUST 2017–REVISED OCTOBER 2018
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
5.5
UNIT
V
Supply voltage
VS– to VS+
Supply turnon, off maximum dV/dT(2)
1
V/µs
V
VI
VID
II
Input voltage
VS– – 0.5
VS+ + 0.5
±1
Differential input voltage
Continuous input current
Continuous output current(3)
Continuous power dissipation
Maximum junction temperature
Operating free-air temperature
Storage temperature
V
±10
mA
mA
IO
±20
See Thermal Information
TJ
150
°C
°C
°C
TA
–40
–65
125
150
Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Staying below this ± supply turn-on edge rate prevents the edge-triggered ESD absorption device across the supply pins from turning
on.
(3) Long-term continuous output current for electromigration limits.
7.2 ESD Ratings
VALUE
±1500
±1000
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.7
NOM
5
MAX
5.4
UNIT
VS+
TA
Single-supply voltage
Ambient temperature
V
–40
25
125
°C
7.4 Thermal Information
OPA838
DBV
(SOT-23)
DCK
(SC70)
DCKS
THERMAL METRIC(1)
UNIT
(SC70)
6 PINS
189
6 PINS
194
129
39
5 PINS
203
152
76
RθJA
RθJCtop
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
150
79
Junction-to-top characterization parameter
Junction-to-board characterization parameter
26
58
61
ψJB
39
76
79
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2017–2018, Texas Instruments Incorporated
5
OPA838
ZHCSGM4B –AUGUST 2017–REVISED OCTOBER 2018
www.ti.com.cn
7.5 Electrical Characteristics: VS = 5 V
at VS+ = 5 V, VS– = 0 V, RF = 1 kΩ, RG = 200 Ω, RL = 2 kΩ, G = 6 V/V, input and output referenced to midsupply, and TA ≈
25°C, (unless otherwise noted)
TEST
PARAMETER
AC PERFORMANCE
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LEVEL(1)
VOUT = 20 mVPP, G = 6, (peaking < 4 dB)
VOUT = 20 mVPP, G = 10, RF = 1.6 kΩ
VOUT = 20 mVPP, G = 100, RF = 16.9 kΩ
VOUT = 20 mVPP, G = 100
75
90
50
C
C
C
C
C
C
C
C
SSBW
Small-signal bandwidth
MHz
3
GBP
Gain-bandwidth product
Large-signal bandwidth
Bandwidth for 0.1-dB flatness
Slew rate
240
250
300
45
MHz
MHz
MHz
V/µs
LSBW
VOUT = 2 VPP, G = 6
VOUT = 200 mVPP, G = 6
From LSBW(2)
10
SR
350
1%
Overshoot, undershoot
VOUT = 2-V step, G = 6, input tR = 12 ns
2%
13
VOUT = 2-V step, G = 6, RL = 2 kΩ,
input tR = 12 ns
tR, tF
Rise, fall time
12.5
ns
C
Settling time to 0.1%
Settling time to 0.01%
VOUT = 2-V step, G = 6, input tR = 12 ns
VOUT = 2-V step, G = 6, input tR = 12 ns
30
40
ns
ns
C
C
C
C
C
C
C
C
C
C
HD2
HD3
Second-order harmonic distortion f = 100 kHz, VO = 4 VPP, G = 6 (see 图 74)
–110
–120
1.8
100
1
dBc
dBc
nV/√Hz
Hz
Third-order harmonic distortion
Input voltage noise
f = 100 kHz, VO = 4 VPP, G = 6 (see 图 74)
f > 1 kHz
Voltage noise 1/f corner frequency
Input current noise
f > 100 kHz
pA/√Hz
kHz
ns
Current noise 1/f corner frequency
Overdrive recovery time
7
G = 6, 2x output overdrive, DC-coupled
f = 1 MHz, G = 6
50
Closed-loop output impedance
0.3
Ω
DC PERFORMANCE
AOL Open-loop voltage gain
VO = ±2 V, RL = 2 kΩ
120
–125
–165
–230
–230
–1.6
0.7
125
±15
±15
±15
±15
±0.4
1.5
dB
µV
A
A
B
B
B
B
A
B
B
B
B
A
B
B
B
B
TA ≈ 25°C
125
200
220
285
1.6
2.8
3.5
3.7
4.4
17
TA = 0°C to 70°C
Input-referred offset voltage
Input offset voltage drift(3)
Input bias current(5)
TA = –40°C to 85°C
TA = –40°C to 125°C
TA = –40°C to 125°C(4)
µV/°C
µA
TA ≈ 25°C
TA = 0°C to 70°C
.2
1.5
TA = –40°C to 85°C
TA = –40°C to 125°C
TA = –40°C to 125°C
.2
1.5
.2
1.5
Input bias current drift(3)
Input offset current
4.5
7.8
nA/°C
nA
TA ≈ 25°C
–70
–83
–105
–105
–500
±20
±20
±20
±20
±40
70
TA = 0°C to 70°C
93
TA = –40°C to 85°C
TA = –40°C to 125°C
TA = –40°C to 125°C
100
120
500
Input offset current drift(3)
pA/°C
(1) Test levels (all values set by characterization and simulation): (A) 100% tested at 25°C, overtemperature limits by characterization and
simulation; (B) Not tested in production, limits set by characterization and simulation; (C) Typical value only for information.
(2) This slew rate is the average of the rising and falling time estimated from the large-signal bandwidth as: (0.8 × VPEAK / √2) × 2π × f–3dB
where this f–3dB is the typical measured 4-VPP bandwidth at gains of 6 V/V.
(3) Input offset voltage drift, input bias current drift, and input offset current drift are average values calculated by taking data at the end
points, computing the difference, and dividing by the temperature range.
(4) Input offset voltage drift, input bias current drift, and input offset current drift typical specifications are mean ± 1σ characterized by the full
temperature range end-point data. Maximum drift specifications are set by the min, max packaged test range on the wafer-level
screened drift. Drift is not specified by the final automated test equipment (ATE) or by QA sample testing.
(5) Current is considered positive out of the pin.
6
Copyright © 2017–2018, Texas Instruments Incorporated
OPA838
www.ti.com.cn
ZHCSGM4B –AUGUST 2017–REVISED OCTOBER 2018
Electrical Characteristics: VS = 5 V (continued)
at VS+ = 5 V, VS– = 0 V, RF = 1 kΩ, RG = 200 Ω, RL = 2 kΩ, G = 6 V/V, input and output referenced to midsupply, and TA ≈
25°C, (unless otherwise noted)
TEST
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LEVEL(1)
INPUT
T
A ≈ 25°C, CMRR > 92 dB
TA = –40°C to 125°C, CMRR > 92 dB
A ≈ 25°C, CMRR > 92 dB
TA = –40°C to 125°C, CMRR > 92 dB
VS– – 0.2
VS– – 0
VS+ – 1.2
VS+ – 1.3
105
VS– – 0
A
B
A
B
A
C
C
Common-mode input range, low
Common-mode input range, high
V
V
T
VS+ – 1.3
95
CMRR
Common-mode rejection ratio
Input impedance common-mode
Input impedance differential mode
dB
35 || 1
MΩ || pF
kΩ || pF
30 || 1.3
OUTPUT
T
A ≈ 25°C, G = 6
TA = –40°C to 125°C, G = 6
A ≈ 25°C, G = 6
TA = –40°C to 125°C, G = 6
VS– + 0.05
VS– + 0.05
VS– + 0.1
VS– + 0.1
A
B
A
B
VOL
Output voltage, low
Output voltage, high
V
T
VS+ – 0.1 VS+ – 0.05
VOH
V
VS+ – 0.2
±35
VS+ – 0.1
±40
Maximum current into a resistive
load
T
A ≈ 25°C, ±1.53 V into 41.3 Ω, VIO < 2 mV
A ≈ 25°C, ±1.81 V into 70.6 Ω, AOL > 80 dB
mA
A
A
B
C
T
±25
±28
Linear current into a resistive load
mA
TA = –40°C to 125°C, ±1.58 V into 70.6 Ω, AOL
> 80 dB
±22
±25
DC output impedance
G = 6
0.02
Ω
POWER SUPPLY
Specified operating voltage
2.7
913
700
5
960
960
5.4
993
V
B
A
B
(6)
T
A ≈ 25°C
Quiescent operating current
µA
TA = –40°C to 125°C
TA = –40°C to 125°C
1330
Quiescent current temperature
coefficient
dIq/dT
2.6
98
93
3
110
105
3.4
µA/°C
dB
B
A
A
Positive power-supply rejection
ratio
+PSRR
–PSRR
Negative power-supply rejection
ratio
dB
POWER DOWN (Pin Must be Driven, SOT23-6 and SC70-6)
Enable voltage threshold
Disable voltage threshold
Disable pin bias current
Specified on above VS–+ 1.5 V
1.5
V
V
A
A
A
A
Specified off below VS–+ 0.55 V
PD = VS– to VS+
0.55
50
1
–50
20
nA
µA
Power-down quiescent current
PD = 0.55 V
0.1
Time from PD = high to VOUT = 90% of final
value
Turnon time delay
Turnoff time delay
1.7
usec
ns
C
C
Time from PD = low to VOUT = 10% of original
value
100
(6) The typical specification is at 25°C TJ. The minimum and maximum limits are expanded for the ATE to account for an ambient range
from 22°C to 32°C with a 4-µA/°C temperature coefficient on the supply current.
Copyright © 2017–2018, Texas Instruments Incorporated
7
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7.6 Electrical Characteristics: VS = 3 V
at VS+ = 3 V, VS– = 0 V, RF = 1 kΩ, RG = 200 Ω, RL = 2 kΩ, G = 6 V/V, input and output referenced to midsupply, and TA ≈
25°C, (unless otherwise noted)
TEST
PARAMETER
AC PERFORMANCE
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LEVEL(1)
VOUT = 20 mVPP, G = 6 (peaking < 4 dB)
VOUT = 20 mVPP, G = 10, RF = 1.6 kΩ
VOUT = 20 mVPP, G = 100, RF = 16.9 kΩ
VOUT = 20 mVPP, G = 100
70
86
50
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
SSBW
Small-signal bandwidth
MHz
3
GBP
Gain-bandwidth product
Large-signal bandwidth
Bandwidth for 0.1-dB flatness
Slew rate
240
250
300
45
MHz
MHz
MHz
V/µs
LSBW
VOUT = 2 VPP, G = 6
VOUT = 200 mVPP, G = 6
From LSBW(2)
9
SR
350
2%
6.3
30
Overshoot, undershoot
Rise, fall time
VOUT = 1-V step, G = 6, input tR = 6 ns
VOUT = 1-V step, G = 6, input tR = 6 ns
VOUT = 1-V step, G = 6, input tR = 6 ns
VOUT = 1-V step, G = 6, input tR = 6 ns
4%
7
tR, tF
ns
ns
Settling time to 0.1%
Settling time to 0.01%
40
ns
HD2
HD3
Second-order harmonic distortion f = 100 kHz, VO = 2 VPP, G = 6 (see 图 74)
–108
–125
1.8
100
1.0
7
dBc
dBc
nV/√Hz
Hz
Third-order harmonic distortion
Input voltage noise
f = 100 kHz, VO = 2 VPP, G = 6 (see 图 74)
f > 1 kHz
Voltage noise 1/f corner frequency
Input current noise
f > 100 kHz
pA/√Hz
kHz
ns
Current noise 1/f corner frequency
Overdrive recovery time
G = 6, 2x output overdrive, DC-coupled
f = 1 MHz, G = 6
50
Closed-loop output impedance
0.3
Ω
DC PERFORMANCE
AOL Open-loop voltage gain
VO = ±1 V, RL = 2 kΩ
110
–125
–165
–230
–230
–1.6
.7
125
±15
±15
±15
±15
±0.4
1.5
dB
µV
A
A
B
B
B
B
A
B
B
B
B
A
B
B
B
B
TA ≈ 25°C
125
200
220
285
1.6
2.8
3.5
3.7
4.4
17
TA = 0°C to 70°C
Input-referred offset voltage
Input offset voltage drift(3)
Input bias current(5)
TA = –40°C to 85°C
TA = –40°C to 125°C
TA = –40°C to 125°C
(4)
µV/°C
µA
TA ≈ 25°C
TA = 0°C to 70°C
.2
1.5
TA = –40°C to 85°C
TA = –40°C to 125°C
TA = –40°C to 125°C
.2
1.5
.2
1.5
Input bias current drift(3)
Input offset current
4.5
7.8
nA/°C
nA
TA ≈ 25°C
–70
–83
–105
–105
–500
±20
±20
±20
±13
±20
70
TA = 0°C to 70°C
93
TA = –40°C to 85°C
TA = –40°C to 125°C
TA = –40°C to 125°C
100
120
500
Input offset current drift(3)
pA/°C
(1) Test levels (all values set by characterization and simulation): (A) 100% tested at 25°C, overtemperature limits by characterization and
simulation; (B) Not tested in production, limits set by characterization and simulation; (C) Typical value only for information.
(2) This slew rate is the average of the rising and falling time estimated from the large-signal bandwidth as: (0.8 × VPEAK / √2) × 2π × f–3dB
where this f–3dB is the typical measured 2-VPP bandwidth at gains of 6 V/V.
(3) Input offset voltage drift, input bias current drift, and input offset current drift are average values calculated by taking data at the end
points, computing the difference, and dividing by the temperature range.
(4) Input offset voltage drift, input bias current drift, and input offset current drift typical specifications are mean ± 1σ characterized by the full
temperature range end-point data. Maximum drift specifications are set by the min, max packaged test range on the wafer-level
screened drift. Drift is not specified by the final automated test equipment (ATE) or by QA sample testing.
(5) Current is considered positive out of the pin.
8
Copyright © 2017–2018, Texas Instruments Incorporated
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ZHCSGM4B –AUGUST 2017–REVISED OCTOBER 2018
Electrical Characteristics: VS = 3 V (continued)
at VS+ = 3 V, VS– = 0 V, RF = 1 kΩ, RG = 200 Ω, RL = 2 kΩ, G = 6 V/V, input and output referenced to midsupply, and TA ≈
25°C, (unless otherwise noted)
TEST
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LEVEL(1)
INPUT
T
A ≈ 25°C, CMRR > 92 dB
TA = –40°C to 125°C, CMRR > 92 dB
A ≈ 25°C, CMRR > 92 dB
TA = –40°C to 125°C, CMRR > 92 dB
VS– – 0.2
VS– – 0
VS+ – 1.2
VS+ – 1.3
105
VS– – 0
A
B
A
B
A
C
C
Common-mode input range, low
Common-mode input range, high
V
V
T
VS+ – 1.3
95
CMRR
Common-mode rejection ratio
Input impedance common-mode
Input impedance differential mode
dB
55 || 1.1
30 || 1.3
MΩ || pF
kΩ || pF
OUTPUT
T
A ≈ 25°C, G = 6
TA = –40°C to 125°C, G = 6
A ≈ 25°C, G = 6
TA = –40°C to 125°C, G = 6
VS– + 0.05
VS– + 0.1
VS– + 0.1
VS– + 0.2
A
B
A
B
VOL
Output voltage, low
Output voltage, high
V
T
VS+ – 0.1 VS+ – 0.05
VOH
V
VS+ – 0.2
±28
VS+ – 0.1
±30
Maximum current into a resistive
load
T
A ≈ 25°C, ±0.77 V into 26.7 Ω, VIO < 2 mV
A ≈ 25°C, ±0.88 V into 37 Ω, AOL > 70 dB
mA
A
A
B
C
T
±23
±25
Linear current into a resistive load
mA
TA = –40°C to 125°C, ±0.76 V into 37 Ω,
AOL > 70 dB
±20
±23
DC output impedance
G = 6
0.02
Ω
POWER SUPPLY
Specified operating voltage
2.7
890
680
5
930
930
5.4
970
V
B
A
B
T
A ≈ 25°C(6)
Quiescent operating current
µA
TA = –40°C to 125°C
TA = –40°C to 125°C
1290
Quiescent current temperature
coefficient
dIq/dT
2.2
95
90
2.7
110
105
3.2
µA/°C
dB
B
A
A
Positive power-supply rejection
ratio
+PSRR
–PSRR
Negative power-supply rejection
ratio
dB
POWER DOWN (Pin Must be Driven, SOT23-6 and SC70-6)
Enable voltage threshold
Disable voltage threshold
Disable pin bias current
Specified on above VS– + 1.5 V
1.5
V
V
A
A
A
A
Specified off below VS– + 0.55 V
PD = VS– to VS+
0.55
50
1
–50
20
nA
µA
Power-down quiescent current
PD = 0.55 V
0.1
Time from PD = high to VOUT = 90% of final
value
Turnon time delay
Turnoff time delay
3.5
usec
ns
C
C
Time from PD = low to VOUT = 10% of original
value
100
(6) The typical specification is at 25°C TJ. The minimum and maximum limits are expanded for the ATE to account for an ambient range
from 22°C to 32°C with a 4-µA/°C temperature coefficient on the supply current.
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7.7 Typical Characteristics: VS = 5 V
VS+ = 5 V, VS– = 0 V, RF = 1 kΩ, RG = 200 Ω, RL = 2 kΩ, G = 6 V/V, input and output referenced to midsupply, TA ≈ 25°C
(unless otherwise noted)
3
0
6
3
0
-3
-3
-6
-6
-9
-9
Gain = 6 V/V
Gain = 10 V/V
Gain = 20 V/V
Gain = 50 V/V
Gain = -6 V/V
Gain = -10 V/V
Gain = -20 V/V
Gain = -50 V/V
-12
-12
-15
-15
100m
1
10
100
100m
1
10
100
Frequency (MHz)
Frequency (MHz)
D001
See 图 75 and 表 2 (VO = 20 mVPP, R LOAD= 2 kΩ)
See 图 74 and 表 1 (VO = 20 mVPP, R LOAD = 2 kΩ)
图 2. Inverting Small-Signal Frequency Response vs Gain
图 1. Noninverting Small-Signal Frequency Response
vs Gain
18
18
15
12
9
15
12
9
6
6
VO = 200 mVPP
VO = 500 mVPP
VO = 1 VPP
VO = 2 VPP
VO = 4 VPP
VO = 200 mVPP
VO = 500 mVPP
VO = 1 VPP
VO = 2 VPP
VO = 4 VPP
3
3
0
0
100m
1
10
100
100m
1
10
100
Frequency (MHz)
Frequency (MHz)
Gain = 6 V/V, R LOAD = 2 kΩ
Gain = –6 V/V, R LOAD = 2 kΩ
图 3. Noninverting Large-Signal Bandwidth vs VOPP
图 4. Inverting Large-Signal Bandwidth vs VOPP
1.2
1
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-1.2
-1.4
-1.6
-0.2
-0.4
-0.6
-0.8
-1
Gain = 6 V/V
Gain = 10 V/V
Gain = 20 V/V
Gain = -6 V/V
Gain = -10 V/V
Gain = -20 V/V
-1.2
100m
1
10
100
100m
1
10
100
Frequency (MHz)
Frequency (MHz)
D005
See 图 75 and 表 2 (VO = 200 mVPP; R LOAD = 2 kΩ)
See 图 74 and 表 1 (VO = 200 mVPP, R LOAD = 2 kΩ)
图 5. Noninverting Response Flatness vs Gain
图 6. Inverting Response Flatness vs Gain
10
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www.ti.com.cn
ZHCSGM4B –AUGUST 2017–REVISED OCTOBER 2018
Typical Characteristics: VS = 5 V (接下页)
VS+ = 5 V, VS– = 0 V, RF = 1 kΩ, RG = 200 Ω, RL = 2 kΩ, G = 6 V/V, input and output referenced to midsupply, TA ≈ 25°C
(unless otherwise noted)
2.25
2.25
1.75
VO = ê0.25 V
VO = ê0.5 V
VO = ê1 V
VO = ê0.25 V
VO = ê0.50 V
VO = ê1 V
1.75
1.25
1.25
VO = ê2 V
VO = ê2 V
0.75
0.75
0.25
0.25
-0.25
-0.75
-1.25
-1.75
-2.25
-0.25
-0.75
-1.25
-1.75
-2.25
20
70
120
170
220
260
20
70
120
170
220
260
Time (nsec)
Time (nsec)
See 图 74 (gain of 6 V/V)
图 7. Noninverting Step Response vs VOPP
See 图 75 (gain of –6 V/V)
图 8. Inverting Step Response vs VOPP
0.02
0.018
0.016
0.014
0.012
0.01
0.008
0.006
0.004
0.002
0
-0.002
-0.004
-0.006
-0.008
-0.01
-0.012
0.02
0.018
0.016
0.014
0.012
0.01
AV = 6, 500-mV Step, TR = 3 ns
AV = 6, 2-V Step, TR = 12 ns
AV = 10, 500-mV Step, TR = 3 ns
AV = 10, 2-V Step, TR = 12 ns
AV = -6, 500-mV Step, TR = 3 ns
AV = -6 , 2-V Step, TR = 12 ns
AV = -10 , 500-mV Step, TR = 3 ns
AV = -10 , 2-V Step, TR = 12 ns
0.008
0.006
0.004
0.002
0
-0.002
-0.004
-0.006
0
10
20
30
40
50
60
70
80
90 100
0
20
40
60
80
100
Time from Input Step (nsec)
Time from Input Step (nsec)
See 图 74 and 表 1
See 图 75 and 表 2
图 9. Simulated Noninverting Settling Time
图 10. Simulated Inverting Settling Time
5
4
5
4
VIN ì 10 gain
VOUT (AV = 10)
VIN ì 6 gain
3
3
VOUT (AV = 6)
2
2
1
1
0
0
-1
-2
-3
-4
-1
-2
-3
-4
VIN ì -10 gain
VOUT (AV = -10)
VIN ì -6 gain
VOUT (AV = -6)
-5
-5
50
250
450
650
850
1050
1250
1450
50
250
450
650
850
1050
1250
1450
Time (nsec)
Time (nsec)
D011
D012
See 图 74 and 表 1
图 11. Noninverting Overdrive Recovery
See 图 75 and 表 2
图 12. Inverting Overdrive Recovery
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Typical Characteristics: VS = 5 V (接下页)
VS+ = 5 V, VS– = 0 V, RF = 1 kΩ, RG = 200 Ω, RL = 2 kΩ, G = 6 V/V, input and output referenced to midsupply, TA ≈ 25°C
(unless otherwise noted)
-80
-90
-85
-90
HD2, 100 kHz, G = 6 V/V
HD3, 100 kHz, G = 6 V/V
HD2, 100 kHz, G = -6 V/V
HD3, 100 kHz, G = -6 V/V
-95
-100
-110
-120
-130
-140
-150
-100
-105
-110
-115
-120
-125
-130
HD2, G = 6 V/V
HD3, G = 6 V/V
HD2, G = -6 V/V
HD3, G = -6 V/V
10k
100k
1M
100
1k
Frequency (Hz)
RLOAD (W)
See 图 74, 图 75, 表 1, and 表 2
See 图 74, 图 75, 表 1, and 表 2
(VO = 2 VPP, F = 100 kHz)
图 14. Harmonic Distortion vs RLOAD
图 13. Harmonic Distortion vs Frequency
-95
-100
-105
-110
-115
-120
-125
-130
-135
-100
-105
-110
-115
-120
-125
-130
HD2, 100 kHz, G = 6 V/V
HD3, 100 kHz, G = 6 V/V
HD2, 100 kHz, G = -6 V/V
HD3, 100 kHz, G = -6 V/V
HD2, 100 kHz, +Gain
HD3, 100 kHz, +Gain
HD2, 100 kHz, -Gain
HD3, 100 kHz, -Gain
0.5
1
1.5
2
2.5
3
3.5
4
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
Gain Magnitude (V/V)
VOPP (V)
See 图 74, 图 75, 表 1, and 表 2
(F = 100 kHz, RLOAD = 2 kΩ)
See 图 74, 图 75, 表 1, and 表 2
(VO = 2 VPP, RLOAD = 2 kΩ, F = 100 kHz)
图 15. Harmonic Distortion vs Output Swing
图 16. Harmonic Distortion vs Gain
-105
-105
-110
-115
-120
-125
-130
-110
-115
-120
-125
-130
HD2, 100 kHz, G = 6 V/V
HD3, 100 kHz, G = 6 V/V
HD2, 100 kHz, G = 10 V/V
HD3, 100 kHz, G = 10 V/V
HD2, 100 kHz, G = -6 V/V
HD3, 100 kHz, G = -6 V/V
HD2, 100 kHz, G = -10 V/V
HD3, 100 kHz, G = -10 V/V
1.5
2
2.5
3
3.5
1.5
2
2.5
VOCM (V)
3
3.5
VOCM (V)
D017
See 图 75 and 表 2
See 图 74 and 表 1
(VO = 2 VPP, F = 100 kHz, RLOAD = 2 kΩ)
(VO = 2 VPP, F = 100 kHz, RLOAD = 2 kΩ)
图 18. Inverting Distortion vs
图 17. Noninverting Distortion vs
Output Common-Mode Voltage
Output Common-Mode Voltage
12
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ZHCSGM4B –AUGUST 2017–REVISED OCTOBER 2018
7.8 Typical Characteristics: VS = 3 V
VS+ = 3 V, VS– = 0 V, RF = 1 kΩ, RG = 200 Ω, RL = 2 kΩ, G = 6 V/V, input and output referenced to midsupply. TA = 25°C
(unless otherwise noted)
6
3
6
3
0
0
-3
-3
-6
-6
-9
-9
Gain = 6 V/V
Gain = 10 V/V
Gain = 20 V/V
Gain = 50 V/V
Gain = -6 V/V
Gain = -10 V/V
Gain = -20 V/V
Gain = -50 V/V
-12
-15
-12
-15
0.1
1
10
100
0.1
1
10
100
Frequency (MHz)
Frequency (MHz)
D019
See 图 75 and 表 2
See 图 74 and 表 1
图 20. Inverting Small-Signal Response vs Gain
图 19. Noninverting Small-Signal Response vs Gain
18
18
15
12
9
15
12
9
6
6
VO = 200 mVPP
VO = 500 mVPP
VO = 1 VPP
VO = 200 mVPP
VO = 500 mVPP
VO = 1 VPP
3
3
VO = 2 VPP
VO = 2 VPP
0
0
0.1
1
10
100
0.1
1
10
100
Frequency (MHz)
Frequency (MHz)
See 图 74 (AV = 6 V/V)
See 图 75 (AV = –6 V/V)
图 21. Noninverting Large-Signal Bandwidth vs VOPP
图 22. Inverting Large-Signal Bandwidth vs VOPP
1.4
1.8
1.4
1
1.2
1
0.8
0.6
0.4
0.2
0
0.6
0.2
-0.2
-0.6
-1
-0.2
-0.4
-0.6
-0.8
-1
Gain = 6 V/V
Gain = 10 V/V
Gain = 20 V/V
Gain = -6 V/V
Gain = -10 V/V
Gain = -20 V/V
-1.4
-1.8
-1.2
-1.4
0.1
1
10
100
0.1
1
10
100
Frequency (MHz)
Frequency (MHz)
D023
See 图 75 and 表 2 (VO = 200 mVPP, R LOAD = 2 kΩ)
See 图 74 and 表 1 (VO = 200 mVPP, R LOAD = 2 kΩ)
图 23. Noninverting Response Flatness vs Gain
图 24. Inverting Response Flatness vs Gain
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Typical Characteristics: VS = 3 V (接下页)
VS+ = 3 V, VS– = 0 V, RF = 1 kΩ, RG = 200 Ω, RL = 2 kΩ, G = 6 V/V, input and output referenced to midsupply. TA = 25°C
(unless otherwise noted)
1.5
1.5
1
VO = ±0.25 V
VO = ±0.5 V
VO = ±1 V
VO = ±0.25 V
VO = ±0.5 V
VO = ±1 V
1
0.5
0
0.5
0
-0.5
-1
-0.5
-1
-1.5
-1.5
20
70
120
170
220
260
20
70
120
170
220
260
Time (nsec)
Time (nsec)
See 图 74 and 表 1
图 25. Noninverting Step Response vs V OPP
See 图 75 and 表 2
图 26. Inverting Step Response vs VOPP
0.01
0.008
0.006
0.004
0.002
0
0.02
0.018
0.016
0.014
0.012
0.01
AV = 6, 500-mV Step, TR = 3 ns
AV = 6, 1-V Step, TR = 6 ns
AV = 10, 500-mV Step, TR = 3 ns
AV = 10, 1-V Step, TR = 6 ns
AV = -6, 500-mV Step, TR = 3 ns
AV = -6, 1-V Step, TR = 6 ns
AV = -10, 500-mV Step, TR = 3 ns
AV = -10, 1-V Step, TR = 6 ns
0.008
0.006
0.004
0.002
0
-0.002
-0.004
-0.006
-0.008
-0.01
-0.002
-0.004
0
10
20
30
40
50
60
70
80
90 100
0
10
20
30
40
50
60
70
80
90 100
Time from Input Step (nsec)
Time from Input Step (nsec)
See 图 74 and 表 1
See 图 75 and 表 2
图 27. Noninverting Settling Time
图 28. Inverting Settling Time
3
2
3
2
VIN ì 10 gain
VIN ì -10 gain
VOUT (AV = -10)
VIN ì -6 gain
VOUT (AV = 10)
VIN ì 6 gain
VOUT (AV = 6)
VOUT (AV = -6)
1
1
0
0
-1
-2
-1
-2
-3
-3
50
250
450
650
850
1050
1250
1450
50
250
450
650
850
1050
1250
1450
Time (nsec)
Time (nsec)
D029
D030
See 图 74 and 表 1
图 29. Noninverting Overdrive Recovery
See 图 75 and 表 2
图 30. Inverting Overdrive Recovery
14
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ZHCSGM4B –AUGUST 2017–REVISED OCTOBER 2018
Typical Characteristics: VS = 3 V (接下页)
VS+ = 3 V, VS– = 0 V, RF = 1 kΩ, RG = 200 Ω, RL = 2 kΩ, G = 6 V/V, input and output referenced to midsupply. TA = 25°C
(unless otherwise noted)
-80
-85
-90
HD2, G = 6 V/V
HD3, G = 6 V/V
HD2, G = -6 V/V
HD3, G = -6 V/V
HD2, 100 kHz, G = 6 V/V
HD3, 100 kHz, G = 6 V/V
HD2, 100 kHz, G = -6 V/V
HD3, 100 kHz, G = -6 V/V
-90
-95
-100
-110
-120
-130
-140
-100
-105
-110
-115
-120
-125
-130
10k
100k
1M
100
1k
Frequency (Hz)
RLOAD (W)
See 图 74, 图 75, 表 1, and 表 2
See 图 74, 图 75, 表 1, and 表 2
图 31. Harmonic Distortion vs Frequency
图 32. Harmonic Distortion vs Load
-105
-110
-115
-120
-125
-130
-105
-110
-115
-120
-125
-130
HD2, 100 kHz, +Gain
HD3, 100 kHz, +Gain
HD2, 100 kHz, -Gain
HD3, 100 kHz, -Gain
HD2, 100 kHz, G = 6 V/V
HD3, 100 kHz, G = 6 V/V
HD2, 100 kHz, G = -6 V/V
HD3, 100 kHz, G = -6 V/V
0.5
0.7
0.9
1.1
1.3
VOPP (V)
1.5
1.7
1.9
2
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
Gain Magnitude (V/V)
See 图 74, 图 75, 表 1, and 表 2
See 图 74, 图 75, 表 1, and 表 2 (2-kΩ load, 2 VPP
)
图 33. Harmonic Distortion vs Output Swing
图 34. Harmonic Distortion vs Gain
-90
-95
-105
-110
-115
-120
-125
-130
HD2, 100 kHz, G = 6 V/V
HD3, 100 kHz, G = 6 V/V
HD2, 100 kHz, G = 10 V/V
HD3, 100 kHz, G = 10 V/V
-100
-105
-110
-115
-120
-125
-130
-135
HD2, 100 kHz, G = -6 V/V
HD3, 100 kHz, G = -6 V/V
HD2, 100 kHz, G = -10 V/V
HD3, 100 kHz, G = -10 V/V
0.5
0.7
0.9
1.1
1.3
VOCM (V)
1.5
1.7
1.9
2.1
0.8 0.9
1
1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9
VOCM (V)
See 图 74 and 表 1 (VO = 1 VPP
)
See 图 75 and 表 2 (VO = 1 VPP)
图 35. Noninverting Harmonic Distortion vs Output
图 36. Inverting Harmonic Distortion vs Output Common-
Common-Mode Voltage
Mode Voltage
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7.9 Typical Characteristics: Over Supply Range
PD = VS+ and TA = 25°C (unless otherwise noted)
100
50
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
-10
10
20
0
-20
-40
-60
-80
-100
-120
-140
-160
-180
-200
-220
-240
-260
-280
AV = 6, 5-V supply
AV = 10, 5-V supply
AV = 20, 5-V supply
AV = 6, 3-V supply
AV = 10, 3-V supply
AV = 20, 3-V supply
5-V Gain
5-V Phase
3-V Gain
3-V Phase
20
10
5
2
1
0.5
0.2
0.1
0.05
0.02
0.01
0.005
0.002
0.001
0.01
0.1
1
10
100
1k
10k
100k
1M
10M 100M 1G
Frequency (MHz)
Frequency (Hz)
D038
No load, simulation
See 图 74 and 表 1 (simulation)
图 38. Closed-Loop Output Impedance
图 37. Open-Loop Gain and Phase
100
80
5-V supply
3-V supply
5 V En
3 V En
5 V In
3 V In
60
40
10
20
0
-20
-40
-60
-80
1
10
0
1
2
3
4
5
6
7
8
9
10
100
1k
10k
100k
1M
10M
Time (sec)
Frequency (Hz)
Input referred
图 40. Low-Frequency Voltage Noise
图 39. Input Spot Noise Density
-65
-70
120
110
100
90
-75
-80
-85
80
-90
70
5-V PSRR
-5-V PSRR
5-V CMRR
3-V PSRR
-3-V PSRR
3-V CMRR
-95
60
5 V, 200 mVPP
5 V, 1 VPP
3 V, 200 mVPP
3 V, 1 VPP
-100
-105
-110
50
40
0.1
1
10
1
10
100
1k
10k
100k
1M
10M
Frequency (MHz)
Frequency (Hz)
D042
Simulated results
Measured, AV = 6 V/V, 100-Ω load
图 42. Disabled Isolation Noninverting Input to Output
图 41. PSRR and CMRR
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Typical Characteristics: Over Supply Range (接下页)
PD = VS+ and TA = 25°C (unless otherwise noted)
300
240
220
200
180
160
140
120
100
80
5-V Supply
3-V Supply
5-V Supply
3-V Supply
275
250
225
200
175
150
125
100
75
60
50
40
25
20
0
0
-125 -100 -75 -50 -25
0
25 50 75 100 125
-70 -60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70
Input offset Voltage (µV)
Input Offset Current (nA)
600 units at each supply voltage
600 units at each supply voltage
图 43. Input Offset Voltage Distribution
图 44. Input Offset Current Distribution
100
80
25
20
15
10
5
60
40
20
0
0
-20
-40
-60
-80
-100
-5
-10
-15
-20
-25
-40 -25 -10
5
20 35 50 65 80 95 110 125
Ambient Temperature (°C)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Ambient Temperature (°C)
D045
D046
51 units at 5-V and 3-V supply
51 units at 5-V and 3-V supply
图 45. Input Offset Voltage vs Temperature
图 46. Input Offset Current vs Temperature
27
16
5-V supply
3-V supply
5-V drift
3-V drift
24
21
18
15
12
9
14
12
10
8
6
4
6
2
3
0
0
1
0
1
0
0
5 00 50 00 50 00 50 00 50 00
-
0.5
1.5
-50
1
1
2
2
3
3
4
4
5
-1.5
-0.5
-0.25
0.25
0.75
1.25
-500-450-400-350-300-250-200-150-100
-0.7I5nput offset voltage drift (uV/°C)
Input offset current drift (pA/°C)
-1.25
More
51 units at each supply
51 units at each supply
图 47. Input Offset Voltage Drift Distribution
图 48. Input Offset Current Drift Distribution
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Typical Characteristics: Over Supply Range (接下页)
PD = VS+ and TA = 25°C (unless otherwise noted)
220
33
30
27
24
21
18
15
12
9
AV = 6 V/V
AV = 10 V/V
AV = 20 V/V
200
180
160
140
120
100
80
AV = 6, CLOAD = 100 pF
AV = 10, CLOAD = 100 pF
AV = 20, CLOAD = 100 pF
AV = 6, CLOAD = 1 nF
AV = 10, CLOAD = 1 nF
AV = 20, CLOAD = 1 nF
6
60
3
40
0
20
-3
-6
0
1
10
100
1k
10k
10k
100k
1M
10M
100M
CLOAD (pF)
Frequency (Hz)
D049
D050
See 图 66 and 表 1
See 图 66 and 表 1
(small signal, targeting 30° phase margin)
(2-kΩ parallel load to C LOAD)
图 49. Output Resistor vs CLOAD
图 50. Small-Signal Response Shapes vs CLOAD With
Recommended ROUT
2.5
2
2.5
2
PD Voltage (5 V)
Output Voltage (5 V)
PD Voltage (3 V)
1.5
1
1.5
1
Output Voltage (3 V)
0.5
0
0.5
0
-0.5
-1
-0.5
-1
PD Voltage (5 V)
-1.5
-2
Output Voltage (5 V)
PD Voltage (3 V)
Output Voltage (3 V)
-1.5
-2
-2.5
-2.5
4.5
5
5.5
6
6.5
7
7.5
8
8.5
9
9.5
1.8 1.84 1.88 1.92 1.96
2
2.04 2.08 2.12 2.16 2.2
Time (ms)
Time (ms)
D051
D052
图 51. Turnon Time to Sinusoidal Input
图 52. Turnoff Time to Sinusoidal Input
6
5.5
5
0.007
0.006
0.005
0.004
0.003
0.002
0.001
0
6
0.007
5 V Disable V
5 V VOUT
5 V %Err
3 V Disable V
3 V VOUT
3 V %Err
5 V Disable V
5 V VOUT
5 V %Err
3 V Disable V
3 V VOUT
3 V %Err
5.5
5
0.006
0.005
0.004
0.003
0.002
0.001
0
4.5
4
4.5
4
3.5
3
3.5
3
2.5
2
2.5
2
-0.001
-0.002
-0.003
-0.004
-0.005
-0.001
-0.002
-0.003
-0.004
-0.005
1.5
1
1.5
1
0.5
0
0.5
0
0
0.5
1
1.5
2
2.5
3
3.5
4
0
0.5
1
1.5
2
2.5
3
3.5
4
Time from turn on (ms)
Time from turn on (ms)
Single-supply, DC input to produce midscale output (simulation)
Single-supply, DC input to produce midscale output (simulation)
图 53. Gain of 6-V/V Turnon Time to Final DC Value at
图 54. Gain of 10-V/V Turnon Time to Final DC Value at
Midscale
Midscale
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Typical Characteristics: Over Supply Range (接下页)
PD = VS+ and TA = 25°C (unless otherwise noted)
2.5
2.5
2
2
1.5
1
1.5
1
0.5
0.5
0
+VCC 2.5 V
1.5 V
+VCC
-VCC -2.5 V
-VCC -1.5 V
+VCC 2.5 V
1.5 V
+VCC
-VCC -2.5 V
-VCC -1.5 V
0
-0.5
-1
-0.5
-1
-1.5
-2
-1.5
-2
-2.5
-2.5
100
1k
0.1
1
IOUT (mA)
10
RLOAD to Ground ( )
Ω
图 55. Output Voltage Swing vs Load Resistor
图 56. Output Saturation Voltage vs Load Current
1300
1200
1000
800
600
400
200
0
1200
1100
1000
900
IQ 5 V
IQ 3 V
800
700
-200
-40
-20
0
20
40
60
80
100
120
0.5
0.75
1
1.25
PD Voltage Above -VS Supply (V)
1.5
Ambient Temperature (èC)
D058
图 58. Supply Current vs Power-Down Voltage:
图 57. Quiescent Current vs Temperature
Turnon Higher Than Turnoff
100
80
1700
8
5 V IB-
5 V IB+
5 V IOS
3 V IB-
3 V IB+
3 V IOS
1650
1600
1550
1500
1450
1400
1350
1300
1250
1200
1150
1100
1050
1000
6
4
60
2
0
40
-2
20
-4
0
-6
-8
-20
-40
-60
-80
-100
-10
-12
-14
-16
-18
-20
-2.7 -2.3 -1.9 -1.5 -1.1 -0.7 -0.3 0.1 0.5 0.9 1.3 1.7
Input Common-Mode Voltage (Split Supplies, Volts)
-0.4
0
0.4 0.8 1.2 1.6
2
2.4 2.8 3.2 3.6
4
Input Common-Mode Voltage (V)
5 units, 3-V and 5-V supplies
Measured single device
图 59. Input Offset Voltage vs Input Common-Mode Voltage
图 60. Input Bias and Offset Current vs VICM
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8 Detailed Description
8.1 Overview
The OPA838 is a power efficient, decompensated, voltage feedback amplifier (VFA). Combining a negative rail
input stage and a rail-to-rail output (RRO) stage, the device provides a flexible solution where higher gain or
transimpedance designs are required. This 300-MHz gain bandwidth product (GBP) amplifier requires less than
1 mA of supply current over a 2.7 to 5.4-V total supply operating range. A shutdown feature on the 6-pin package
versions provides power savings where the system requires less than 1 µA when shut down. A decompensated
amplifier operating at low gains (less than 6 V/V) may experience a low phase margin that may risk oscillation.
The TINA model for the OPA838 predicts those conditions.
8.2 Functional Block Diagram
The OPA838 is a standard voltage feedback op amp with two high-impedance inputs and a low-impedance
output. Standard applications circuits are supported; see 图 61 and 图 62. These application circuits are shown
with a DC VREF on the inputs that set the DC operating points for single-supply designs. The VREF is often
ground, especially for split-supply applications.
VSIG
VS+
VREF
VIN
VOUT
OPA838
RG
GVSIG
VREF
VREF
VS-
RF
图 61. Noninverting Amplifier
VS+
VREF
VSIG
VREF
VOUT
OPA838
RG
GVSIG
V
IN
VREF
VS-
RF
图 62. Inverting Amplifier
8.3 Feature Description
8.3.1 Input Common-Mode Voltage Range
When the primary design goal is a linear amplifier with high CMRR, the input pins must stay within the input
operating range (VICR.) These are referenced off of each supply as an input headroom requirement. Ensured
operation at 25°C is maintained to the negative supply voltage and to within 1.3 V of the positive supply voltage.
The common-mode input range specifications in the table data use CMRR to set the limit. The limits are selected
to ensure CMRR does not degrade more than 3 dB below the minimum CMRR value if the input voltage is within
the specified range.
Assuming the op amp is in linear operation, the voltage difference between the input pins is small (0 V) and the
input common-mode voltage is analyzed at either input pin, assuming the other input pin is at the same potential.
The voltage at VIN+ is simple to evaluate. In noninverting configuration (see 图 61), the input signal (VIN) must not
violate the VICR. In inverting configuration (see 图 62), the reference voltage (VREF), must be within the VICR
.
20
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Feature Description (接下页)
The input voltage limits have fixed headroom to the power rails and track the power supply voltages. For a single
5-V supply, the linear 25°C minimum input voltage ranges from 0 V to 3.7 V, and 0 V to 1.4 V for a single 2.7-V
supply. The delta headroom from each power supply rail is the same in each case (0 V and 1.3 V).
8.3.2 Output Voltage Range
The OPA838 device is a rail-to-rail output op amp. Rail-to-rail output typically means that the output voltage
swings to within 100 mV of the supply rails. There are different ways to specify this: one is with the output still in
linear operation and another is with the output saturated. Saturated output voltages are closer to the power
supply rails than linear outputs, but the signal is not a linear representation of the input. Saturation and linear
operation limits are affected by the output current, where higher currents lead to more voltage loss in the output
transistors; see 图 56.
The specification tables show saturated output voltage specifications with a 2-kΩ load. 图 11 and 图 43 illustrate
saturated voltage-swing limits versus output load resistance, and 图 12 and 图 44 illustrate the output saturation
voltage versus load current. With a light load, the output voltage limits have constant headroom to the power rails
and track the power supply voltages. For example, with a 1-kΩ load and a single 5-V supply, the linear output
voltage ranges from 0.12 V to 4.88 V and ranges from 0.12 V to 2.58 V for a 2.7-V supply. The delta from each
power supply rail is the same in each case: 0.12 V.
With devices like the OPA838 where the input range is lower than the output range, the input limits the available
signal swing at low gains. Because the OPA838 is intended for higher gains, the smaller input swing range does
not limit operation and full rail-to-rail output is available. Inverting voltage gain and transimpedance configurations
are typically limited by the output voltage limits of the op amp if the noninverting input pin is biased in range.
8.3.3 Power-Down Operation
The OPA838 includes a power-down feature. Under logic control, the amplifier can switch from normal operation
to a standby current of less than 1 µA. When the PD pin is connected high (greater than or equal to 1.5 V above
the negative supply), the amplifier is active. Connecting the PD pin low (less than or equal to 0.55 V above the
negative supply) disables the amplifier. To protect the input stage of the amplifier, the device uses internal, back-
to-back diodes (two in series each way) between the inverting and noninverting input pins. If the differential
voltage in shutdown exceeds 1.2 V, those diodes turn on.
The PD pin must be actively driven high or low and must not be left floating. If the power-down mode is not used,
PD may be tied to the positive supply rail.
When the op amp is powered from a single-supply and ground, with PD driven from logic devices with similar
VDD voltages to the op amp, no special considerations are required. When the op amp is powered from a split-
supply with VS– below ground, an open-collector type of interface with a pullup resistor is more appropriate.
Pullup resistor values must be lower than 100 kΩ. Recovery from power down is illustrated in 图 53 and 图 54 for
several gains. In single-supply mode with the gain resistor at ground, the output approaches the positive supply
on initial power up until the internal nodes charge then recover to the target output voltage; see 图 51 and 图 52.
8.3.4 Trade-Offs in Selecting The Feedback Resistor Value
The OPA838 is specified using a 1-kΩ feedback resistor with a 200-Ω gain resistor to ground in a noninverting
gain of 6 V/V configuration. These values give a good compromise, keeping the noise contribution of the
resistors well below that of the amplifier noise terms and minimal power in the feedback network as the output
voltage swing creates load current back into the feedback network. Decreasing these values improves the noise
at the cost of more power dissipated in the feedback network. Low values increase the harmonic distortion as the
feedback load decreases. Increasing the RF value at a particular gain increases the output noise contribution of
those resistors possibly becoming dominant. As the feedback resistor values continue to increase (and the RG at
a fixed target gain), there is a loss of phase margin as the impedance that drives the inverting input capacitance
brings in an added loop pole at lower frequencies. 图 63 shows this at a gain of 6 V/V with increasing RF values.
This noninverting test shows more peaking as the RF values increase due to the 1-pF
common-mode input capacitance at the inverting input. The TINA simulation model gives excellent prediction of
these effects.
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Feature Description (接下页)
27
24
21
18
15
12
RF = 1 k
RF = 2 k
RF = 5 k
RF = 10 k
RF = 20 k
9
10k
100k
1M
10M
100M
Frequency (Hz)
D063
图 63. Frequency Response With Various Feedback Resistor Values
Operating the OPA838 in inverting mode with higher RF values increases response peaking due to the loss of
phase margin effect. In the inverting case, a pair of capacitors can flatten the response at the cost of lower
closed-loop bandwidth. 图 64 shows an example with a 20-kΩ RF value at an inverting gain of –5 V/V (noise gain
= 6 V/V) with optional capacitors (CF and CG). 图 64 shows optional bias current cancellation elements on the
noninverting input. The total resistance value matches the parallel combination of RG || RF, which reduces the DC
output error term due to bias current to IOS × RF. The 10-nF capacitor is added across the larger part of this bias
current canceling resistance to filter noise and the 20 Ω is split out to isolate the capacitor self resonance from
the noninverting input. 图 65 illustrates the small-signal response shape with and without these capacitors. The
feedback capacitor (CF), is selected to set a desired closed-loop bandwidth with RF. CG is added to ground to
shape the noise gain up over frequency to be greater than or equal to 6 V/V at higher frequencies. In this
example, that higher frequency noise gain is 1 + 6 / 1.2 = 6 V/V, adding the 1-pF device common-mode
capacitance to the external 5 pF. Using the capacitors to set the feedback ratio removes the pole produced in the
feedback driving from purely resistive source to the inverting parasitic capacitance.
CF 1.2 pF
RG 4.02 kΩ
RF 20 kΩ
Input
CG 5 pF
VEE
œ
Inverting with
High Rf values
RG 4.02 Ω
+
+
+
PD
V
C1 10n
RM 3.24 kΩ
VOUT
VCC
VCC
VEE
+
Bias current
+
cancellation with
resistor noise
filtering
V1 2.5 V
V2 œ2.5 V
图 64. G = –5 V/V With Optional Compensation
22
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Feature Description (接下页)
18
15
12
9
6
3
0
-3
-6
-9
-12
-15
No caps
With caps
10k
100k
1M
10M
100M
Frequency (Hz)
D070
图 65. Inverting Response With and Without Compensation
8.3.5 Driving Capacitive Loads
The OPA838 can drive small capacitive loads directly without oscillation (less than 6 pF). When driving capacitive
loads greater than 6 pF, 图 49 illustrates the recommended ROUT vs capacitor load parametric on gains. At higher
gains, the amplifier starts with greater phase margin into a resistive load and can operate with lower ROUT for a
given capacitive load. Without ROUT, output capacitance interacts with the output impedance of the amplifier,
which causes phase shift in the loop gain of the amplifier that reduces the phase margin. This causes peaking in
the frequency response with overshoot and ringing in the pulse response. 图 49 targets a 30° phase margin for
the OPA838. A 30° phase margin produces a 5.7-dB peaking in the frequency response at the amplifier output
pin that is rolled off by the output RC pole; see 图 67. This peaking can cause clipping for large signals driving a
capacitive load. Increasing the ROUT value can reduce the peaking at the cost of a more band-limited overall
response.
RG 200 Ω
RF 1 kΩ
VEE
œ
ROUT 68.1 Ω
+
+
+
PD
+
V
VG1
VOUT
VCC
VCC
VEE
+
+
V1 2.5 V
V2 œ2.5 V
图 66. ROUT versus CL Test Circuit
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Feature Description (接下页)
25
22
19
16
13
10
7
At capacitive load
At output pin
4
1
-2
-5
10k
100k
1M
Frequency (Hz)
10M
100M
CapL
图 67. Frequency Response to Output Pin and Capacitive Load
8.4 Device Functional Modes
8.4.1 Split-Supply Operation (±1.35 V to ±2.7 V)
To facilitate testing with common lab equipment, the OPA838 EVM (see EVM board link) is built to allow split-
supply operation. This configuration eases lab testing because the midpoint between the power rails is ground,
and most signal generators, network analyzers, oscilloscopes, spectrum analyzers, and other lab equipment
have inputs and outputs with a ground reference. This simplifies characterization by removing the requirement for
blocking capacitors.
图 68 shows a simple noninverting configuration analogous to 图 61 with a ±2.5-V supply and VREF equal to
ground. The input and output swing symmetrically around ground. For ease of use, split-supplies are preferred in
systems where signals swing around ground. Using bipolar (or split) supplies shifts the thresholds for the
shutdown control. The disable control is referenced from the negative supply. Typically, this is ground in a single-
supply application, but using a negative supply requires that the pin is set to within 0.55 V above the negative
supply to disable. If disable is not required, connecting that pin to the positive supply ensures correct operation,
even for split-supply applications. This disable pin cannot be floated but must be asserted to a voltage.
RG 200 Ω
RF 1 kΩ
VEE
±2.1 VOUT
Ground
Centered
U1 OPA838
œ
R2 165 Ω
+
+
+
PD
V
±0.35 VIN
20 nsec edge
2 MHz input
VM1
Input
Signal
VCC
VCC
VEE
+
+
V1 2.5 V
V2 œ2.5 V
图 68. Split-Supply Operation
24
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Device Functional Modes (接下页)
2.5
2
Input
Output
1.5
1
0.5
0
-0.5
-1
-1.5
-2
-2.5
200
300
400
500
600
700
800
Time (nsec)
D068
图 69. Bipolar-Supply Step Response
8.4.2 Single-Supply Operation (2.7 V to 5.4 V)
Most newer systems use a single power supply to improve efficiency and to simplify power supply design. The
OPA838 can be used with single-supply power (ground for the negative supply) with no change in performance
from split supply, as long as the input and output pins are biased within the linear operating region of the device.
The outputs nominally swing rail-to-rail with approximately a 100-mV headroom required for linear operation. The
inputs can swing below the negative rail (typically ground) and to within 1.3 V of the positive supply. For DC-
coupled single-supply operation, the higher gain operating applications typical of a decompensated op amp keep
the input swings below the input swing limit to the positive supply. Typically, the 1.3-V input headroom required
to the positive supply does not limit operation.
图 70 shows an example design taking a 0 V to 0.5 V input range, level shifting the output up to 0.15 V for a 0-V
input using the 4.5-V reference voltage common for 5-V SAR ADCs, and sets the gain to produce a 4.1-V output
swing for the 0.5-V input swing. This example is assuming a 0-Ω source that is required to sink the 39 µA
required to bias the positive input pin to produce the 0.15-V output for 0-V input. The RF and RG values are
scaled down slightly to provide bias current cancellation by matching the parallel combination of the two bias set-
up resistors on the noninverting input. 图 71 illustrates an example step response for this circuit that produces an
output from 0.15 V for a 0-V input to 4.35 V for a 0.5-V input.
RG 56.2 Ω
RF 1 kΩ
VREF
+
V1 4.5 V
œ
VOUT
RB2 49.9 Ω
+
+
PD
+
VG1
0 V to 0.5 V
Input Swing
VCC
VCC
VREF
+
VCC 5 V
图 70. DC-Coupled, Single-Supply, Noninverting Interface With Output Level Shift
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Device Functional Modes (接下页)
4.5
4
3.5
3
2.5
2
Input
Output
1.5
1
0.5
0
0
0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2
Time (µsec)
D065
图 71. Unipolar Input to Level Shifted Output Step Response
If AC-coupling is acceptable, a simple way to operate single-supply is to run inverting. 图 72 shows a low-power,
high-gain example. In this example, a gain of –20 V/V is implemented (inverting usually does not matter for AC-
coupled channels) where the V+ input is biased midscale. This example is showing an optional bias current
cancellation setup, which may not be necessary unless the output DC level requires good accuracy. The parallel
combination of the divider resistors plus the 80.7-Ω isolating resistor match the feedback resistor value. With the
blocking capacitor at the inverting input, the feedback resistor impedance must be matched to achieve bias
current cancellation. In this 3-V supply example, the two inputs and the output are biased at 1.5 V. This places
the input pins in range and centers the output for maximum V
available. 图 73 illustrates the small-signal
PP
response for this example showing a F-3dB range from a low-end cutoff of 887 Hz set by the input capacitor value
to a 17.5-MHz high-frequency cutoff.
C2 1µF
RG 178 Ω
RF 3.57 kΩ
VG1
+
887 Hz to
17.5 Mhz gain
of -20 V/V
U1 OPA838
œ
Riso 80.6
+
+
+
PD
VCC
1.5 V
DC Out
V
RB1 6.98 kΩ
VM1
C1 1 µF
VCC
+
V1 3 V
图 72. Single-Supply Inverting Gain Stage With AC-Coupled Input
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Device Functional Modes (接下页)
27
24
21
18
15
Output
12
100
1k
10k
100k
Frequency (Hz)
1M
10M
100M
D069
图 73. Inverting Single-Supply Response With AC-Coupled Input
These are only two of the many ways a single-supply design may be implemented. Many others exist where
using a DC reference voltage or AC-coupling are common. A good compilation of options can be found in Single-
Supply Op Amp Design Techniques.
8.5 Power Shutdown Operation
As noted, the 6-pin packages that offer a power shutdown feature must have that pin asserted. To retain the
lowest possible shutdown power, no internal pullup resistors are present in the OPA838. The control threshold is
referenced off the negative supply with a nominal internal threshold near 1 V above the negative supply. Worst-
case tolerances dictate the required low-level voltage to ensure shutdown of 0.55 V or less above the negative
supply and 1.5 V or greater above the negative supply to ensure enabled operation. The required control pin
current is less than ±50 nA. For SOT-23-6 applications that do not require a shutdown functionality, connect the
disable control pin to the positive supply. For SC70 package applications that do not require a shutdown, use the
5-pin package where the control pad is internally connected to the positive supply. When disabled, the output
nominally goes to a high impedance. However, the feedback network provides a path for discharge for off state
voltage condition. 图 51 illustrates the turnon time with a sinusoidal input that is relatively slow, while 图 52
illustrates the turnoff time is fast. 图 53 and 图 54 illustrate the single-supply operation with a DC input to produce
a midsupply output at gains of 6 V/V and 10 V/V. In all cases, the output voltage transitions to a point close to
the positive supply voltage and then moves to the desired output voltage 0.5 µs to 1.5 µs after the disable control
line goes high. The supply current in shutdown is a low 0.1 µA nominally with a maximum 1 µA.
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9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 Noninverting Amplifier
The OPA838 can be used as noninverting amplifier with signal input to the noninverting input (VIN+). 图 61
illustrates a basic block diagram of the circuit. VREF is often ground when split supplies are used.
If VIN = VREF + VSIG, and the gain setting resistor (RG) is DC referenced to VREF, use 公式 1 to calculate the
output of the amplifier.
æ
ö
÷
ø
RF
V
OUT
= VSIG 1 +
+ VREF
ç
RG
è
(1)
RF
G = 1 +
RG
The noninverting signal gain (also called the noise gain) of the circuit is set by:
VREF provides a reference around which the input and output signals swing. Output signals are in-phase with the
input signals within the flat portion of the frequency response. For a high-speed, low-noise device like the
OPA838, the values selected for RF (and the RG for the desired gain) can strongly influence the operation of the
circuit. For the characteristic curves, the noninverting circuit of 图 74 shows the test configuration. 表 1 lists the
recommended resistor values over gain.
RG 200 Ω
RF 1 kΩ
„ 50 Ω source
VEE
50 Ω
Cable
Network
Analyzer
50 Ω
Cable
œ
R3 1.96 kΩ
‰ 2 kΩ load
RS 50 Ω
+
+
PD
+
V
+
R6 51.1 Ω RLOAD 50 Ω
VM1
RT 50 Ω
Network
Analyzer
VCC
VCC
VEE
+
+
V2 -2.5 V
V1 2.5 V
图 74. Noninverting Characterization Circuit
28
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Application Information (接下页)
表 1 lists the recommended resistor values from target gains of 6 V/V to 20 V/V. This table controls the RF and
RG values to set the resistor noise contribution at approximately 40% of the total output noise power. This
increases the spot noise at the output over what the op amp voltage noise produces by 20%. Lower values
reduce the output noise of any design at the cost of more power in the feedback circuit. Using the TINA model
and simulation tool shows the impact of different resistor value choices on response shape and noise.
表 1. Noninverting Recommended Resistor Values
TARGET
AVERAGE
RF (OHMS)
RG (OHMS)
ACTUAL GAIN (V/V)
GAIN (dB)
6
1000
1180
1370
1540
1690
1870
2050
2210
2370
2550
2740
2870
3090
3240
3400
3570
200
196
196
191
187
187
187
182
182
182
182
178
182
178
178
178
6
15.56
16.93
18.05
19.15
20.03
20.83
21.56
22.37
22.94
23.53
24.11
24.67
25.09
25.67
26.06
26.47
7
7.02
8
7.99
9
9.06
10
11
12
13
14
15
16
17
18
19
20
21
10.04
11
11.96
13.14
14.02
15.01
16.05
17.12
17.98
19.20
20.1
21.06
9.1.2 Inverting Amplifier
The OPA838 can be used as an inverting amplifier with signal input to the inverting input (VIN–) through the gain-
setting resistor (RG.) 图 62 illustrates a basic block diagram of the circuit.
If VIN = VREF + VSIG, and the noninverting input is DC biased to VREF, the output of the amplifier may be
calculated according to 公式 2.
æ
SIG ç
è
ö
÷
ø
-RF
V
= V
+ V
REF
OUT
RG
(2)
-RF
G =
RG
The signal gain of the circuit
and VREF provides a reference point around which the input and output
signals swing. For bipolar-supply operation, VREF is often GND. The output signal is 180˚ out-of-phase with the
input signal in the passband of the application. 图 75 illustrates the 50-Ω input matched configuration used for the
inverting characterization plots. In this case, an added termination resistor is placed in parallel with the input RG
resistor to provide an impedance match to 50-Ω test equipment. 表 2 lists the suggested values for RF, RG, and
RT for inverting gains from –6 V/V to –20 V/V.
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50 Ω input
matching
RG 50 Ω RG 187 Ω
RF 1.87 kΩ
+
Gain of -10 V/V
VSOURCE
VEE
œ
VOUT
RB 191 Ω
+
+
PD
VCC
VCC
VEE
+
+
V3 2.5 V
V4 -2.5 V
图 75. Inverting With Input Impedance Matching
表 2. Inverting Recommended Resistor Values
RG
(OHMS)
AVERAGE
RF (OHMS)
EXACT RT
STANDARD RT
INPUT ZI
ACTUAL (V/V)
GAIN (dB)
–6
1180
1370
1540
1690
1870
2050
2210
2370
2550
2740
2870
3090
3240
3400
3570
196
196
191
187
187
187
182
182
182
182
178
182
178
178
178
67.1
67.1
67.7
68.2
68.2
68.2
68.9
68.9
68.9
68.9
69.5
68.9
69.5
69.5
69.5
66.5
66.5
68.1
68.1
68.1
68.1
68.1
68.1
68.1
68.1
69.8
69.8
69.8
69.8
69.8
49.7
49.7
50.2
49.9
49.9
49.9
49.6
49.6
49.6
49.6
50.1
50.5
50.1
50.1
50.1
–6.02
–6.99
15.59
16.89
18.13
19.12
20
–7
–8
–8.06
–9
–9.04
–10
–11
–12
–13
–14
–15
–16
–17
–18
–19
–20
–10
–10.96
–12.14
–13.02
–14.01
–15.05
–16.12
–16.98
–18.20
–19.10
–20.06
20.80
21.69
22.29
22.93
23.55
24.15
24.6
25.2
25.62
26.04
9.1.3 Output DC Error Calculations
The OPA838 can provide excellent DC signal accuracy due to high open-loop gain, high common-mode
rejection, high power-supply rejection, and low input offset voltage and bias current offset errors. To take full
advantage of this low input offset voltage, pay careful attention to input bias current cancellation. The low-noise
input stage for the OPA838 has a relatively high input bias current (1.6 µA typical out the pins) but with a close
match between the two input currents. This is a negative rail input device using PNP input devices where the
base current flows out of the device pins. A large resistor to ground on the V+ input shifts positively because of
the input bias current. The mismatch between the two input bias currents is very low, typically only ±20 nA of
input offset current. Match the DC source impedances out of the two inputs to reduce the total output offset
voltage. For example, one way to add bias current cancellation to the circuit in 图 68 is to insert a 165-Ω series
resistor into the noninverting input to match the parallel combination of RF and RG for this basic gain of 6 V/V
30
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noninverting gain circuit. These same calculations apply to the output offset drift. Analyzing the simple circuit of
图 68, the noise gain for the input offset voltage drift is 1 + 1k / 200 = 6 V/V. This results in an output drift term of
±1.6 µV/°C × 6 = ±9.6 µV/°C. Because the two impedances out of the inputs are matched, the residual error due
to the maximum ±500 pA/°C offset current drift is exactly that number times the 1-kΩ feedback resistor value, or
±50 µV/°C. The total output DC error drift band is ±59 µV/°C.
9.1.4 Output Noise Calculations
The decompensated voltage feedback of the OPA838 op amp offers among the lowest input voltage and current
noise terms for any device with a supply current less than 1 mA. 图 76 shows the op amp noise analysis model
that includes all noise terms. In this model, all the noise terms are shown as noise voltage or current density
terms in nV/√Hz or pA/√Hz.
E
NI
+
OPA838
E
O
R
S
I
BN
E
RS
R
F
4kTRS
4kTRF
R
G
I
BI
4kT
RG
4kT = 1.6E œ 20J
at 290°K
图 76. Op Amp Noise Analysis Model
The total output spot noise voltage is computed as the square root of the squared contributing terms to the
output noise voltage. This computation is adding all the contributing noise powers at the output by superposition,
then taking the square root to return to a spot noise voltage. 公式 3 shows the general form for this output noise
voltage using the terms presented in 图 76.
ENI + I R + 4kTR NG + I R 2 + 4kTRFNG
» ÿ
BN S S BI F
2
2
EO
=
(
)
(
)
⁄
(3)
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Dividing this expression by the noise gain (NG = 1 + RF / RG) gives the equivalent input referred spot noise
voltage at the noninverting input, as shown in 公式 4.
2
I R
4kTRF
NG
≈
’
2
EN = EN2I + IBNRS + 4kTRS +
+
BI
F
(
)
∆
«
÷
◊
NG
(4)
Using the resistor values shown in 表 1 with RS = 0 Ω results in a constant input referred voltage noise of 2.86nV
/ √Hz. Reducing the resistor values brings this number closer to the intrinsic 1.9 nV / √Hz of the OPA838. Adding
RS for bias current cancellation in noninverting mode adds the noise from RS to the total output noise, as shown
in 公式 3. In inverting mode, the RS bias current cancellation resistor must be bypassed with a capacitor for the
best noise performance.
9.1.5 High-Gain Differential I/O Designs
A high-gain differential-to-differential I/O circuit can be used to drive a second-stage FDA or a differential-to-
single-ended stage. This circuit is frequently used in applications where high input impedance is required (for
example, if the source cannot be loaded). 图 76 illustrates an example design where the differential gain is
41 V/V. An added element between the two RG resistors increases the noise gain for the common-mode
feedback. It is important to provision for the added element because a decompensated VFA (like the OPA838)
often oscillates without it in this circuit. With only the RG elements in the differential I/O design, the common-
mode feedback is unity-gain and often causes high-frequency, common-mode oscillations. To resolve this issue,
split the RG elements in half and add a low-impedance path such as a capacitor or a DC reference between the
two RG values.
VCC
PD
+
OPA838
œ
VEE
RG1 88.7 Ω
RF 3.57 kΩ
CCM
R1 500 Ω
Vindiff
Vodiff
VCM
10nF
R2 500 Ω
RF 3.57 kΩ
RG1 88.7 Ω
VCC
PD
OPA838
œ
High Gain
Differential
I/O
+
VEE
图 77. High-Gain Differential I/O Stage
Integrated results are available, but the OPA838 device provides a low-power, high-frequency result. For best
CMRR performance, resistors must be matched. A good rule is CMRR ≈ the resistor tolerance; so 0.1%
tolerance provides approximately 60-dB CMRR.
9.1.5.1 Differential I/O Design Requirements
As an example design, start with the circuit in 图 77.
•
•
Set the target gain and split the RG element in half. For this example, target a gain of 41 V/V.
Assess the DC common-mode biasing on the noninverting inputs. The DC biasing must be in range and have
a gain of 1 to the output. This is not illustrated in 图 76.
•
If a DC reference is used as the mid-R bias, setting the reference equal to the noninverting input bias
voltage sets the output common-mode to that voltage. Using a capacitor as illustrated in 图 76 accomplishes
G
the same results.
9.1.5.2 Detailed Design Procedure
•
Set the total R value near the high gain values using 表 1. This 178-Ω total must be split for a center tap to
increase the common-mode noise gain, as shown by the 88.7-Ω value in 图 77.
G
•
Set RF using a standard value near the calculated from solving 公式 1 using half of the total RG value.
32
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•
Simulate the common-mode noise with different elements on the RG center tap, as shown in 图 78. Decide
which is most appropriate to the application.
The common-mode loop instability without the RG center tap is not often apparent in the closed-loop differential
simulations. It can often be detected in a common-mode output noise simulation as 图 78 shows. Grounding the
inputs 图 77 and running a output noise simulation for the common-mode tap point in 图 76 shows a peaking in
the noise at high frequency. This peaking indicates low-phase margin for the common-mode loop. 图 78 shows
this peaking in the lowest noise curve, with two options for improving phase margin. The first option used in 图
77 is a capacitor to ground set to increase the common-mode noise gain only at higher frequencies. This can be
seen by the peaking in the common-mode noise of 图 78. Another alternative is to provide a DC voltage
reference on the RG center tap. This raises the common-mode noise gain from DC on up in frequency. Neither of
these latter two show any evidence of low phase margin peaking. They do increase the output common-mode
noise significantly at lower frequencies. Typically, an increase in output common-mode noise is more acceptable
than low-phase margin as the next stage (FDA, ADC, differential to single stage) rejects common-mode noise.
180
No center tap
10 nF
Ground
160
140
120
100
80
60
40
20
0
10k
100k
1M
10M
100M
Frequency (Hz)
Diff
图 78. Common-Mode Output Noise for Differential I/O Design
Using the 10-nF center tap capacitor, 图 79 shows the differential I/O small-signal response showing the
expected 300 MHz / 41 ≈ 7.3 MHz closed-loop bandwidth. The capacitor to ground between the RG elements
does not impact the differential frequency response.
33
30
27
24
21
18
15
12
1
10
100
Frequency (MHz)
D074
图 79. Differential Small-Signal Frequency Response
9.1.6 Transimpedance Amplifiers
A common application for a high gain bandwidth voltage feedback op amp is to amplify a small photo-diode
current from a capacitive detector. Figure 80 shows the front page transimpedance circuit with more detail. Here,
a fixed –0.23 negative voltage generator (LM7705) is used on the negative supply to ensure the output has
adequate headroom when it is at 0 V. The transimpedance stage is designed here for a 2.4Mhz flat (Butterworth)
response while a simple RC post-filter band-limits the broadband noise and sets the overall bandwidth to 1MHz.
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The requirements for a high dynamic range transimpedance (or charge) amplifier include the very low input
voltage noise intrinsic to a decompensated device like the OPA838. The noise gain over frequency for this type
of circuit starts out at unity gain then begins to peak with a single zero response due to the pole formed in the
feedback by the feedback resistor and the total capacitance on the inverting input. That noise gain response is
flattened out at higher frequencies by the feedback capacitor value to be the 1 + CS/CF capacitor ratio. This is
normally a very high noise gain allowing the decompensated OPA838 to be applied to this application. Since the
noise gain is intentionally peaked to a high value in this application, the very low input voltage noise (1.8 nV/√Hz)
of the OPA838 improves dynamic range.
CF1.0 pF
RF100 kꢀ
IDIODE
2.4-Mhz
Butterworth
1-MHz
Low Pass
VEE
U1 OPA838
œ
R2 73.2 ꢀ
R1 20 ꢀ
+
+
PD
VOUT
Bias Current
Cancellation
and R-noise
filtering
VM1
VCC
VCC
VEE
+
+
V1 3 V
LM7805 œ 230 mV
图 80. 100-kΩ Wide Bandwidth Transimpedance Design
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9.1.7 Design Requirements
To implement a controlled frequency response transimpedance design, set the transimpedance stage amplifier
bandwidth higher than a controlled post RC filter. This allows variation in the source capacitance and amplifier
gain bandwidth product with less overall bandwidth variation to the final output. In this example design:
•
Assume a nominal source capacitance value of 100 pF. This normally comes from the capacitance versus
reverse bias plot for the photodiode. No reverse bias is illustrated in 图 81, but the current source is typically
a back biased diode with a negative supply on the anode and the cathode connected to the op amp inverting
input. In this polarity, the signal current sinks into the diode and raises the op amp output voltage above
ground.
•
For the best DC precision, add a matching resistor on the noninverting input to reduce the input bias current
error to IOS × RF . This resistor adds to the input voltage noise; TI recommends bypassing that resistor with as
large as a capacitor as required to roll off resistor noise. This capacitor has a relatively low frequency self
resonance that interacts with the input stage and might impair stability. Add a small series 20-Ω resistor from
the capacitor into the noninverting input to de-Q the resonant source impedance without adding too much
noise.
•
•
Set the feedback capacitor to achieve the desired frequency response shape.
Add a post RC filter to control the overall bandwidth to 1 MHz. In this example, a 2.2-nF capacitor allows a
low 73.2-Ω series resistor. When driving a sampling ADC (like a SAR), this combination helps reduce the
sampling glitch and speed settling time.
9.1.7.1 Detailed Design Procedure
The primary design requirement is to set the achievable transimpedance gain and compensate the operational
amplifier with CF for the desired response shape. A detailed transimpedance design methodology is available in
Transimpedance Considerations for High-Speed Amplifiers. With a source capacitance set and the amplifier
selected to provide a particular gain bandwidth product, the achievable transimpedance gain and resulting
Butterworth bandwidth are tightly coupled as 公式 5 illustrates. Use 公式 6 to solve for a maximum RF value.
When the RF is selected, the feedback pole is set by 公式 7 to be at .707 of the characteristic frequency. At that
compensation point, the closed-loop bandwidth is that characteristic frequency with a Butterworth response.
•
•
•
With the 100-pF source capacitance, 300-MHz gain bandwidth product, and the 2.2-MHz closed-loop
bandwidth target in the transimpedance stage, solve 公式 6 for a maximum gain of 100 kΩ.
Set the feedback pole at 0.707 times that 2.2-MHz Butterworth bandwidth. This sets the target 1 / (2π × R
×
F
CF) = 1.55 MHz. Solving for CF sets the target to 1 pF
If DC precision is desired, add a 100-kΩ resistor to ground on the noninverting input. If DC precision is not
required, ground the noninverting input
•
•
•
Add a resistor noise filtering capacitor in parallel with the 100-kΩ resistor.
Add a small series resistor isolating this capacitor from the noninverting input.
Select a final filter capacitor for the load. (In this example, a value of 2.2 nF is used as a typical SAR input
capacitor.)
•
•
Add a series resistor to the final filter capacitor to form a 1-MHz pole. In this example, that is 73.2 Ω.
Confirm this resistor is greater than the minimum recommended value illustrated in 图 49.
GBP
F-3dB
ö
2pRƒCS
(5)
(6)
GBP
F-23dB2pCS
Rƒmax
ö
1
GBP
= 0.707ì
2pRƒCƒ
2pRƒCS
(7)
Implementing this design and simulating the performance using the TINA model for the response to the output
pin and to the final capacitive load shows the expected results of 图 81. Here the exact 2.2-MHz flat Butterworth
response to the output pin is shown with the final single pole rolloff at 1 MHz at the final 2.2-nF capacitor.
版权 © 2017–2018, Texas Instruments Incorporated
35
OPA838
ZHCSGM4B –AUGUST 2017–REVISED OCTOBER 2018
www.ti.com.cn
103
100
97
94
91
88
85
82
79
76
Gain output pin
Gain Load (dB)
73
0.001
0.01
0.1
1
10
Frequency (MHz)
D075
图 81. Small-Signal Response for 100-kΩ Transimpedance Gain
10 Power Supply Recommendations
The OPA838 device is intended to work in a supply range of 2.7 V to 5.4 V. Good power-supply bypassing is
required. Minimize the distance (less than 0.1 inch) from the power-supply pins to high-frequency, 0.1-μF
decoupling capacitors. A larger capacitor (2.2 µF is typical) is used with a high-frequency, 0.1-µF supply-
decoupling capacitor at the device supply pins. For single-supply operation, only the positive supply has these
capacitors. When a split-supply is used, use these capacitors for each supply to ground. If necessary, place the
larger capacitors further from the device and share these capacitors among several devices in the same area of
the PCB. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling
capacitors. An optional 0.1-µF supply decoupling capacitor across the two power supplies (for bipolar operation)
reduces second harmonic distortion.
The OPA838 has a positive supply current temperature coefficient; see 图 57. This helps improve the input offset
voltage drift. Supply current requirements in system design must account for this effect using the maximum
intended ambient and 图 57 to size the supply required. The very low power dissipation for the OPA838 typically
does not require any special thermal design considerations. For the extreme case of 125°C operating ambient,
use the approximate maximum 200°C/W for the three packages, and a maximum internal power of
5.4-V supply × 1.25-mA 125°C supply current from 图 57 gives a maximum internal power of 6.75 mW. This only
gives a 1.35°C rise from ambient to junction temperature which is well below the maximum 150°C junction
temperature. Load power adds to this, but also increases the junction temperature only slightly over ambient
temperature.
36
版权 © 2017–2018, Texas Instruments Incorporated
OPA838
www.ti.com.cn
ZHCSGM4B –AUGUST 2017–REVISED OCTOBER 2018
11 Layout
11.1 Layout Guidelines
The OPA838 EVM can be used as a reference when designing the circuit board. TI recommends following the
EVM layout of the external components near to the amplifier, ground plane construction, and power routing as
closely as possible. General guidelines are listed below:
1. Signal routing must be direct and as short as possible into and out of the op amp.
2. The feedback path must be short and direct avoiding vias if possible.
3. Ground or power planes must be removed from directly under the negative input and output pins of the
amplifier.
4. TI recommends placing a series output resistor as close to the output pin as possible when driving capacitive
or matched loads.
5. A 2.2-µF power-supply decoupling capacitor must be placed within two inches of the device and can be
shared with other op amps. For split-supply operation, a capacitor is required for both supplies.
6. A 0.1-µF power-supply decoupling capacitor must be placed as close to the supply pins as possible,
preferably within 0.1 inch. For split-supply operation, a capacitor is required for both supplies.
7. The PD pin uses logic levels referenced off the negative supply. If the pin is not used, the pin must tie to the
positive supply to enable the amplifier. If the pin is used, the pin must be actively driven. A bypass capacitor
is not necessary, but is used for EMI rejection in noisy environments.
11.2 Layout Example
Ground and power plane exist on
inner layers
Ground and power plane removed
Place output resistors close
to output pins to minimize
parasitic capacitance
from inner layers
1
2
3
6
5
4
Place bypass capacitors
close to power pins
Place bypass capacitors
close to power pins
Power control (disable) pin
Must be driven
Place input resistor close to pin 4
to minimize stray capacitance
Non-inverting input
terminated in 50 Ω
Place feedback resistor on the bottom
of PCB between pins 4 and 6
Remove GND and Power plane
under pins 1 and 4 to minimize
stray PCB capacitance
图 82. EVM Layout Example
版权 © 2017–2018, Texas Instruments Incorporated
37
OPA838
ZHCSGM4B –AUGUST 2017–REVISED OCTOBER 2018
www.ti.com.cn
12 器件和文档支持
12.1 器件支持
12.1.1 器件支持
12.1.1.1 TINA-TI™仿真模型 特性
您可以从 www.ti.com 产品文件夹内的典型应用电路文件中获取器件模型。此模型包含多种 功能， 旨在帮助设计人
员加快设计过程，从而满足各类应用需求。下面列出了模型中所包含的性能参数：
•
采用任意外部电路时的小信号响应波形：
–
–
–
差分开环增益和相位
寄生输入电容
开环差分输出阻抗
•
•
对于噪声仿真：
–
–
输入差分点电压噪声和 100Hz 1/f 转角频率
每个输入端上的输入电流噪声与 6kHz 1/f 转角频率
对于时域阶跃响应仿真：
–
–
–
差分转换率
用于预测削波的 I/O 余量模型
用于预测过驱限制的输入级二极管
•
精密的直流精度术语
–
–
–
–
–
电源抑制比 (PSRR)
共模抑制比 (CMRR)
标称输入失调电压
标称输入偏移电流
标称输入偏置电流
典型特性 表提供了比宏模型所能提供的更多细节。其中一些未建模的 特性 包括：
•
•
•
•
谐波失真
直流误差中的温度漂移（VIO 和 IOS
过驱恢复时间
）
使用断电特性时的导通和关断时间
12.2 文档支持
12.2.1 相关文档
请参阅如下相关文档：
德州仪器 (TI)，OPA835DBV、OPA836DBV EVM用户指南
12.2.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
38
版权 © 2017–2018, Texas Instruments Incorporated
OPA838
www.ti.com.cn
ZHCSGM4B –AUGUST 2017–REVISED OCTOBER 2018
文档支持 (接下页)
12.2.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
12.3 商标
TINA-TI, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.5 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2017–2018, Texas Instruments Incorporated
39
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA838IDBVR
OPA838IDBVT
OPA838IDCKR
OPA838IDCKT
OPA838SIDCKR
OPA838SIDCKT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SOT-23
SC70
DBV
DBV
DCK
DCK
DCK
DCK
6
6
5
5
6
6
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
1C3F
1C3F
17Q
17Q
19C
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
SC70
SC70
SC70
19C
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA838IDBVR
OPA838IDBVT
OPA838IDCKR
OPA838IDCKT
OPA838SIDCKR
OPA838SIDCKT
SOT-23
SOT-23
SC70
DBV
DBV
DCK
DCK
DCK
DCK
6
6
5
5
6
6
3000
250
178.0
178.0
178.0
178.0
178.0
178.0
9.0
9.0
9.0
9.0
9.0
9.0
3.23
3.23
2.4
3.17
3.17
2.5
1.37
1.37
1.2
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q3
Q3
Q3
3000
250
SC70
2.4
2.5
1.2
SC70
3000
250
2.4
2.5
1.2
SC70
2.4
2.5
1.2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA838IDBVR
OPA838IDBVT
OPA838IDCKR
OPA838IDCKT
OPA838SIDCKR
OPA838SIDCKT
SOT-23
SOT-23
SC70
DBV
DBV
DCK
DCK
DCK
DCK
6
6
5
5
6
6
3000
250
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
18.0
18.0
18.0
18.0
18.0
18.0
3000
250
SC70
SC70
3000
250
SC70
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0006A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
B
1.45 MAX
A
PIN 1
INDEX AREA
1
2
6
5
2X 0.95
1.9
3.05
2.75
4
3
0.50
6X
0.25
C A B
0.15
0.00
0.2
(1.1)
TYP
0.25
GAGE PLANE
0.22
0.08
TYP
8
TYP
0
0.6
0.3
TYP
SEATING PLANE
4214840/C 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214840/C 06/2021
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/C 06/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DCK0005A
SOT - 1.1 max height
S
C
A
L
E
5
.
6
0
0
SMALL OUTLINE TRANSISTOR
C
2.4
1.8
0.1 C
1.4
1.1
B
1.1 MAX
A
PIN 1
INDEX AREA
1
2
5
NOTE 4
(0.15)
(0.1)
2X 0.65
1.3
2.15
1.85
1.3
4
3
0.33
5X
0.23
0.1
0.0
(0.9)
TYP
0.1
C A B
0.15
0.22
0.08
GAGE PLANE
TYP
0.46
0.26
8
0
TYP
TYP
SEATING PLANE
4214834/C 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-203.
4. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X (0.65)
4
(R0.05) TYP
(2.2)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214834/C 03/2023
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X(0.65)
4
(R0.05) TYP
(2.2)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:18X
4214834/C 03/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
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