OPA860ID [TI]
高带宽运算跨导放大器和缓冲器 | D | 8 | -40 to 85;
| 型号： | OPA860ID |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 高带宽运算跨导放大器和缓冲器 | D | 8 | -40 to 85 放大器 PC 光电二极管 |
| 文件： | 总36页 (文件大小：722K) |
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OPA860
www.ti.com ....................................................................................................................................................... SBOS331C–JUNE 2005–REVISED AUGUST 2008
Wide Bandwidth
OPERATIONAL TRANSCONDUCTANCE
AMPLIFIER (OTA) and BUFFER
1
OTA FEATURES
DESCRIPTION
2
•
Wide Bandwidth (80MHz, Open-Loop, G = +5)
The OPA860 is a versatile monolithic component
designed for wide-bandwidth systems, including high
performance video, RF and IF circuitry. It includes a
wideband, bipolar operational transconductance
amplifier (OTA), and voltage buffer amplifier.
•
•
•
High Slew Rate (900V/µs)
High Transconductance (95mA/V)
External IQ-Control
The OTA or voltage-controlled current source can be
viewed as an ideal transistor. Like a transistor, it has
three terminals—a high impedance input (base), a
low-impedance input/output (emitter), and the current
output (collector). The OTA, however, is self-biased
and bipolar. The output collector current is zero for a
zero base-emitter voltage. AC inputs centered about
zero produce an output current, which is bipolar and
centered about zero. The transconductance of the
OTA can be adjusted with an external resistor,
allowing bandwidth, quiescent current, and gain
trade-offs to be optimized.
BUFFER FEATURES
•
•
•
•
Closed-Loop Buffer
Wide Bandwidth (1600MHz, VO = 1VPP
High Slew Rate (4000V/µs)
60mA Output Current
)
OPA860 FEATURES
•
Low Quiescent Current (11.2mA)
•
Versatile Circuit Function
APPLICATIONS
Also included in the OPA860 is an uncommited
closed-loop, unity-gain buffer. This provides
1600MHz bandwidth and 4000V/µs slew rate.
•
•
•
•
•
•
•
•
•
Baseline Restore Circuits
Video/Broadcast Equipment
Communications Equipment
High-Speed Data Acquisition
Wideband LED Driver
AGC-Multiplier
ns-Pulse Integrator
Control Loop Amplifier
OPA660 Upgrade
Used as
a basic building block, the OPA860
simplifies the design of AGC amplifiers, LED driver
circuits for fiber optic transmission, integrators for fast
pulses, fast control loop amplifiers and control
amplifiers for capacitive sensors and active filters.
The OPA860 is available in an SO-8 surface-mount
package.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2008, Texas Instruments Incorporated
OPA860
SBOS331C–JUNE 2005–REVISED AUGUST 2008 ....................................................................................................................................................... www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
SPECIFIED
PACKAGE
DESIGNATOR
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT MEDIA,
QUANTITY
PRODUCT
PACKAGE
OPA860ID
Rails, 75
OPA860
SO-8
D
–45°C to +85°C
OPA860
OPA860IDR
Tape and Reel, 2500
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Power Supply
±6.5VDC
Internal Power Dissipation
Differential Input Voltage
Input Common-Mode Voltage Range
Storage Temperature Range: D
Lead Temperature (soldering, 10s)
Junction Temperature (TJ)
ESD Rating:
See Thermal Information
±1.2V
±VS
–65°C to +125°C
+300°C
+150°C
Human Body Model (HBM)(2)
1500V
1000V
Charge Device Model (CDM)
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress Ratings only, and functional operations of the device at these and any other conditions
beyond those specified is not supported.
(2) Pin 2 > 500V HBM.
PIN CONFIGURATION
Top View
SO
1
2
3
4
8
7
6
5
IQ Adjust
C
E
B
V+ = +5V
+1
Out
In
−
−
5V
V
=
2
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Product Folder Link(s): OPA860
OPA860
www.ti.com ....................................................................................................................................................... SBOS331C–JUNE 2005–REVISED AUGUST 2008
ELECTRICAL CHARACTERISTICS: VS = ±5V
RL = 500Ω and RADJ = 250Ω, unless otherwise noted.
OPA860ID
TYP
MIN/MAX OVER TEMPERATURE
0°C to
70°C(3)
–40°C to
MIN/
MAX
TEST
PARAMETER
CONDITIONS
+25°C
+25°C(2)
+85°C(3)
UNITS
LEVEL(1)
Closed Loop OTA + BUFFER (see Figure 53)
AC PERFORMANCE
Bandwidth
G = +2, See Figure 53
VO = 200mVPP
VO = 1VPP
470
470
350
42
380
375
370
MHz
MHz
MHz
MHz
V/µs
ns
min
typ
typ
typ
typ
typ
B
C
C
C
C
C
VO = 5VPP
Bandwidth for 0.1dB Gain Flatness
Slew Rate
VO = 200mVPP
VO = 5V Step
VO = 1V Step
G = +2, VO = 2VPP, 5MHz
RL = 100Ω
3500
0.7
3000
2800
2700
Rise Time and Fall Time
Harmonic Distortion
2nd-Harmonic
–54
–77
–66
–79
dBc
dBc
dBc
dBc
typ
typ
typ
typ
C
C
C
C
RL = 500Ω
3rd-Harmonic
RL = 100Ω
RL = 500Ω
OTA - Open-Loop (see Figure 48)
AC PERFORMANCE
G = +5, VO = 200mVPP
,
Bandwidth
80
77
75
74
MHz
min
B
RL = 500Ω
G = +5, VO = 1VPP
G = +5, VO = 5VPP
G = +5, VO = 5V Step
VO = 1V Step
80
80
MHz
MHz
V/µs
ns
typ
typ
min
typ
C
C
B
C
Slew Rate
900
4.4
860
850
840
Rise Time and Fall Time
Harmonic Distortion
G = +5, VO = 2VPP, 5MHz
RL = 500Ω
2nd-Harmonic
–68
–57
2.4
–55
–52
3.0
–54
–51
3.3
–53
–49
3.4
dB
max
max
max
max
max
B
B
B
B
B
3rd-Harmonic
RL = 500Ω
dB
Base Input Voltage Noise
Base Input Current Noise
Emitter Input Current Noise
OTA DC PERFORMANCE(4) (see Figure 48)
Min OTA Transconductance
Max OTA Transconductance
B-Input Offset Voltage
f > 100kHz
nV/√Hz
pA/√Hz
pA/√Hz
f > 100kHz
1.65
5.2
2.4
2.45
16.6
2.5
f > 100kHz
15.3
17.5
VO = ±10mV, RC = 0Ω, RE = 0Ω
VO = ±10mV, RC = 0Ω, RE = 0Ω
VB = 0V, RC = 0Ω, RE = 100Ω
VB = 0V, RC = 0Ω, RE = 100Ω
VB = 0V, RC = 0Ω, RE = 100Ω
VB = 0V, RC = 0Ω, RE = 100Ω
VB = 0V, VC = 0V
95
95
±3
±3
±1
80
77
155
±15
±67
±6
75
mA/V
mA/V
mV
min
min
A
A
A
B
A
B
A
B
A
B
150
±12
160
±20
max
max
max
max
max
max
max
max
Average B-Input Offset Voltage Drift
B-Input Bias Current
±120
±6.6
±25
µV/°C
µA
±5
Average B-Input Bias Current Drift
E-Input Bias Current
±20
±125
±500
±30
±250
nA/°C
µA
±30
±5
±100
±18
±140
±600
±38
Average E-Input Bias Current Drift
C-Output Bias Current
VB = 0V, VC = 0V
nA/°C
µA
VB = 0V, VC = 0V
Average C-Output Bias Current Drift
OTA INPUT (see Figure 48)
B-Input Voltage Range
VB = 0V, VC = 0V
±300
nA/°C
±4.2
455 || 2.1
10.5
±3.7
±3.6
±3.6
V
kΩ || pF
Ω
min
typ
B
C
B
B
B-Input Impedance
Min E-Input Input Resistance
Max E-Input Input Resistance
12.5
6.7
13.0
6.5
13.3
6.3
min
max
10.5
Ω
(1) Test levels: (A) 100% tested at +25°C. Over temperature limits set by characterization and simulation. (B) Limits set by characterization
and simulation. (C) Typical value only for information.
(2) Junction temperature = ambient for +25°C specifications.
(3) Junction temperature = ambient at low temperature limit; junction temperature = ambient + 8°C at high temperature limit for over
temperature specifications.
(4) Current is considered positive out of node. VCM is the input common-mode voltage.
Copyright © 2005–2008, Texas Instruments Incorporated
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OPA860
SBOS331C–JUNE 2005–REVISED AUGUST 2008 ....................................................................................................................................................... www.ti.com
ELECTRICAL CHARACTERISTICS: VS = ±5V (continued)
RL = 500Ω and RADJ = 250Ω, unless otherwise noted.
OPA860ID
TYP
MIN/MAX OVER TEMPERATURE
0°C to
70°C(3)
–40°C to
MIN/
MAX
TEST
PARAMETER
CONDITIONS
+25°C
+25°C(2)
+85°C(3)
UNITS
LEVEL(1)
OTA OUTPUT
E-Output Voltage Compliance
E-Output Current, Sinking/Sourcing
C-Output Voltage Compliance
C-Output Current, Sinking/Sourcing
C-Output Impedance
IE = ±1mA
VE = 0
±4.2
±15
±3.7
±10
±4.0
±10
±3.6
±9
±3.6
±9
V
mA
min
min
min
min
typ
A
A
A
A
C
IC = ±1mA
VC = 0
±4.7
±15
±3.9
±9
±3.9
±9
V
mA
54 || 2
kΩ || pF
BUFFER (see Figure Figure 45)
AC PERFORMANCE
Bandwidth
VO = 200mVPP
VO = 1VPP
1200
1600
1000
4000
0.4
750
720
700
MHz
MHz
MHz
V/µs
ns
min
typ
typ
min
typ
typ
B
C
C
B
C
C
VO = 5VPP
Slew Rate
VO = 5V Step
VO = 1V Step
VO = 1V Step
VO = 2VPP, 5MHz
RL = 100Ω
3500
3200
3000
Rise Time and Fall Time
Settling Time to 0.05%
Harmonic Distortion
2nd-Harmonic
6
ns
–52
–72
–67
–96
4.8
–47
–65
–63
–86
5.1
–46
–63
–63
–85
5.6
–44
–61
–62
–83
6.0
dBc
dBc
max
max
max
max
max
max
typ
B
B
B
B
B
B
C
C
R
L ≥ 500Ω
RL = 100Ω
L ≥ 500Ω
3rd-Harmonic
dBc
R
dBc
Input Voltage Noise
Input Current Noise
Differential Gain
f > 100kHz
f > 100kHz
NTSC, PAL
NTSC, PAL
nV/√Hz
pA/√Hz
%
2.1
2.6
2.7
2.8
0.06
0.02
Differential Phase
BUFFER DC PERFORMANCE
Gain
Degrees
typ
RL = 500Ω
RL = 500Ω
1
1
0.98
1
0.98
1
0.98
1
V/V
V/V
min
max
max
max
max
max
A
A
A
B
A
B
Input Offset Voltage
±16
±30
±36
±125
±8
±38
±125
±8.5
±20
mV
Average Input Offset Voltage Drift
Input Bias Current
µV/°C
µA
±3
±7
Average Input Bias Current Drift
BUFFER INPUT
±20
nA/°C
Input Impedance
1.0 || 2.1
MΩ || pF
typ
C
BUFFER OUTPUT
Output Voltage Swing
RL = 500Ω
VO = 0
±4.0
±60
1.4
±3.8
±50
±3.8
±49
±3.8
±48
V
mA
Ω
min
min
typ
A
A
C
Output Current
Closed-Loop Output Impedance
POWER SUPPLY (OTA + BUFFER)
Specified Operating Voltage
Maximum Operating Voltage
Minimum Operating Voltage
Maximum Quiescent Current
Minimum Quiescent Current
f ≤ 100kHz
±5
V
V
typ
max
min
max
min
C
A
B
A
A
±6.5
±2.5
12
±6.5
±2.5
13.5
9.5
±6.5
±2.5
14.5
7.9
V
RADJ = 250Ω
RADJ = 250Ω
11.2
11.2
mA
mA
10.5
OTA Power-Supply Rejection Ratio
(+PSRR)
ΔIC/ΔVS
±20
54
±50
48
±60
46
±65
45
µA/V
dB
max
min
A
A
Buffer Power-Supply Rejection Ratio
(–PSRR)
ΔVO/ΔVS
THERMAL CHARACTERISTICS
Specification: ID
–40 to +85
125
°C
typ
typ
C
C
Thermal Resistance θJA
D
SO-8
Junction-to-Ambient
°C/W
4
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Product Folder Link(s): OPA860
OPA860
www.ti.com ....................................................................................................................................................... SBOS331C–JUNE 2005–REVISED AUGUST 2008
TYPICAL CHARACTERISTICS: VS = ±5V
At TA = +25°C, IQ = 11.2mA, and RL = 500Ω, unless otherwise noted. (See Figure 53.)
OTA + BUF Performance
SMALL-SIGNAL FREQUENCY RESPONSE
LARGE-SIGNAL FREQUENCY RESPONSE
9
6
3
0
3
6
9
9
6
3
0
3
6
9
G = +2V/V
G = +2V/V
Ω
RL = 500
Ω
RL = 500
VOUT = 0.5VPP
VOUT = 0.2VPP
VOUT = 1VPP
−
−
−
−
−
−
VOUT = 2VPP
VOUT = 5VPP
1M
10M
100M
1G 2G
1M
10M
100M
1G 2G
Frequency (Hz)
Frequency (Hz)
Figure 1.
Figure 2.
SMALL-SIGNAL FREQUENCY RESPONSE
vs QUIESCENT CURRENT
GAIN FLATNESS vs QUIESCENT CURRENT
9
6.5
6.4
6.3
6.2
6.1
6.0
5.9
5.8
5.7
5.6
5.5
G = +2V/V
Ω
RL = 500
VO = 0.2VPP
6
3
0
IQ = 12mA
IQ = 11.2mA
IQ = 8mA
IQ = 8mA
−
3
6
9
IQ = 9mA
G = +2V/V
−
IQ = 12mA
IQ = 9mA
Ω
RL = 500
IQ = 11.2mA
VO = 0.2VPP
−
1M
10M
100M
1G 2G
1
10
100
Frequency (Hz)
Frequency (MHz)
Figure 3.
Figure 4.
SMALL-SIGNAL PULSE RESPONSE
LARGE-SIGNAL PULSE RESPONSE
150
100
50
1.5
1.0
0.5
0
0
−
−
−
−
50
0.5
1.0
1.5
G = +2V/V
VIN = 0.125VPP
fIN = 20MHz
G = +2V/V
VIN = 1.25VPP
fIN = 20MHz
−
−
100
150
Time (5ns/div)
Time (5ns/div)
Figure 5.
Figure 6.
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SBOS331C–JUNE 2005–REVISED AUGUST 2008 ....................................................................................................................................................... www.ti.com
TYPICAL CHARACTERISTICS: VS = ±5V (continued)
At TA = +25°C, IQ = 11.2mA, and RL = 500Ω, unless otherwise noted. (See Figure 53.)
HARMONIC DISTORTION vs FREQUENCY
HARMONIC DISTORTION vs OUTPUT RESISTANCE
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
55
60
65
70
75
80
85
90
50
G = +2V/V
Ω
RL = 500
O = 2VPP
See Figure 53
55
60
65
70
75
80
85
2nd−Harmonic
V
2nd−Harmonic
3rd−Harmonic
G = +2V/V
VO = 2VPP
f = 5MHz
3rd−Harmonic
See Figure 53
0.1
1
10
20
100
1k
Ω
Output Resistance ( )
Frequency (MHz)
Figure 7.
Figure 8.
HARMONIC DISTORTION vs OUTPUT VOLTAGE
HARMONIC DISTORTION vs SUPPLY VOLTAGE
−
−
−
−
−
−
−
−
65
70
75
80
85
90
95
60
65
70
75
80
85
90
G = +2V/V
G = +2V/V
Ω
RL = 500
−
Ω
RL = 500
VO = 2VPP
f = 5MHz
See Figure 53
f = 5MHz
See Figure 53
−
−
−
−
−
3rd−Harmonic
2nd−Harmonic
2nd−Harmonic
3rd−Harmonic
−
100
0.1
1
10
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
±
±
Output Voltage (VPP
)
Supply Voltage ( VS)
Figure 9.
Figure 10.
HARMONIC DISTORTION vs QUIESCENT CURRENT
QUIESCENT CURRENT vs RADJ
−
50
13
12
11
10
9
−
−
−
−
−
−
−
−
55
60
65
70
75
80
2nd−Harmonic
8
G = +2V/V
+IQ
Ω
RL = 500
VO = 2VPP
85 f = 5MHz
See Figure 53
7
3rd−Harmonic
6
−
IQ
90
5
8.0
8.5
9.0
9.5
10.0 10.5 11.0 11.5 12.0
Q (mA)
0.1
1
10
100
1k
10k
100k
Ω
RADJ ( )
I
Figure 11.
Figure 12.
6
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Product Folder Link(s): OPA860
OPA860
www.ti.com ....................................................................................................................................................... SBOS331C–JUNE 2005–REVISED AUGUST 2008
TYPICAL CHARACTERISTICS: VS = ±5V
At TA = +25°C, IQ = 11.2mA, and RL = 500Ω, unless otherwise noted.
OTA Performance
OTA TRANSCONDUCTANCE vs FREQUENCY
OTA TRANSCONDUCTANCE vs QUIESCENT CURRENT
1000
100
10
150
IQ = 12.5mA (117mA/V)
IQ = 11.2mA (102mA/V)
VIN = 100mVPP
120
90
IQ = 9mA (79mA/V)
IOUT
IQ = 7.5mA (51mA/V)
60
VIN
IOU T
Ω
50
VIN
Ω
50
30
0
Ω
50
Ω
RL = 50
50Ω
VIN = 10mVPP
1M
10M
100M
1G
6
7
8
9
10
11
12
13
Frequency (Hz)
Quiescent Current (mA)
Figure 13.
Figure 14.
OTA TRANSCONDUCTANCE vs INPUT VOLTAGE
OTA TRANSFER CHARACTERISTICS
160
140
120
100
80
8
6
4
2
0
IQ = 12mA
IQ = 12mA
IQ = 11.2mA
IQ = 11.2mA
IQ = 9mA
IQ = 9mA
IQ = 7mA
IOUT
−
60
2
4
6
8
IQ = 7mA
VIN
−
−
−
40
Ω
50
Ω
50
20
Small signal around input voltage.
0
−
−
−
−
−
−
−
−
−
−
−
40
30
20
10
0
10
20
30
40
70 60 50 40 30 20 10
0
10 20 30 40 50 60 70
Input Voltage (mV)
OTA Input Voltage (mV)
Figure 15.
Figure 16.
OTA SMALL-SIGNAL PULSE RESPONSE
OTA LARGE-SIGNAL PULSE RESPONSE
0.8
0.6
0.4
0.2
0
3
2
1
0
1
2
3
−
−
−
−
0.2
0.4
0.6
0.8
G = +5V/V
G = +5V/V
−
Ω
RL = 500
Ω
RL = 500
VIN = 1VPP
fIN = 20MHz
See Figure 48
VIN = 0.25VPP
fIN = 20MHz
See Figure 48
−
−
Time (10ns/div)
Time (10ns/div)
Figure 17.
Figure 18.
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TYPICAL CHARACTERISTICS: VS = ±5V (continued)
At TA = +25°C, IQ = 11.2mA, and RL = 500Ω, unless otherwise noted.
B-INPUT RESISTANCE vs QUIESCENT CURRENT
C-OUTPUT RESISTANCE vs QUIESCENT CURRENT
500
490
480
470
460
450
440
430
120
110
100
90
80
70
60
50
40
7
8
9
10
11
12
13
7
8
9
10
11
12
13
Quiescent Current (mA)
Quiescent Current (mA)
Figure 19.
Figure 20.
E-OUTPUT RESISTANCE vs QUIESCENT CURRENT
INPUT VOLTAGE AND CURRENT NOISE DENSITY
60
50
40
30
20
10
0
100
√
E−Input Current Noise (5.2pA/ Hz)
10
√
B−Input Voltage Noise (2.4nV/ Hz)
√
B−Input Current Noise (1.65pA/ Hz)
1
7
8
9
10
11
12
13
100
1k
10k 100k 1M 10M
Quiescent Current (mA)
Frequency (Hz)
Figure 21.
Figure 22.
1MHz OTA VOLTAGE AND CURRENT NOISE DENSITY
vs QUIESCENT CURRENT ADJUST RESISTOR
16
√
E−Input Current Noise (pA/ Hz)
14
12
10
8
√
B−Input Voltage Noise (nV/ Hz)
6
√
B−Input Current Noise (pA/ Hz)
4
2
0
0
200 400 600 800 1000 1200 1400 1600 1800 2000
Ω
Quiescent Current Adjust Resistor (
)
Figure 23.
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TYPICAL CHARACTERISTICS: VS = ±5V
At TA = +25°C, IQ = 11.2mA, and RL = 500Ω, unless otherwise noted.
BUF Performance
BUFFER BANDWIDTH vs OUTPUT VOLTAGE
BUFFER BANDWIDTH vs LOAD RESISTANCE
6
3
0
6
3
0
Ω
RL = 1k
Ω
RL = 500
VO = 0.2VPP
VO = 0.6VPP
VO = 5VPP
−
−
3
6
9
3
6
9
VO = 2.8VPP
VO = 1.4VPP
Ω
RL = 500
−
−
−
−
VO = 0.2VPP
Ω
RL = 100
1M
10M
100M
1G 2G
1M
10M
100M
1G 2G
Frequency (Hz)
Frequency (Hz)
Figure 24.
Figure 25.
BUFFER GAIN FLATNESS
BUFFER SMALL-SIGNAL PULSE RESPONSE
0.20
0.15
0.10
0.05
0
0.5
0.4
0.3
0.2
0.1
0
Ω
RL = 500
VIN = 0.2VPP
fIN = 20MHz
Output
Voltage
Input
Voltage
−
−
−
−
−
0.1
0.2
0.3
0.4
0.5
−
−
−
−
0.05
0.10
0.15
0.20
1
10
100
400
Time (10ns/div)
Frequency (MHz)
Figure 26.
Figure 27.
BUFFER LARGE-SIGNAL PULSE RESPONSE
HARMONIC DISTORTION vs FREQUENCY
−
3
2
1
0
40
50
60
70
80
90
Ω
RL = 500
Ω
RL = 500
VO = 2VPP
VIN = 3VPP
fIN = 20MHz
−
2nd−Harmonic
−
−
−
−
Input
Voltage
Output
Voltage
−
−
−
1
2
3
3rd−Harmonic
−
100
1
10
100
Time (10ns/div)
Frequency (MHz)
Figure 28.
Figure 29.
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TYPICAL CHARACTERISTICS: VS = ±5V (continued)
At TA = +25°C, IQ = 11.2mA, and RL = 500Ω, unless otherwise noted.
5MHz HARMONIC DISTORTION vs LOAD RESISTANCE
HARMONIC DISTORTION vs OUTPUT VOLTAGE
−
−
−
−
−
40
50
60
70
80
90
60
70
80
90
Ω
RL = 500
Ω
RL = 500
VO = 2VPP
2nd−Harmonic
f = 5MHz
−
−
−
−
−
2nd−Harmonic
3rd−Harmonic
3rd−Harmonic
−
−
100
110
−
100
100
1k
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Ω
Load Resistance (
)
Output Voltage (VPP)
Figure 30.
Figure 31.
BUFFER TRANSFER FUNCTION
5MHz HARMONIC DISTORTION vs SUPPLY VOLTAGE
−
60
5
4
3
2
1
0
Ω
RL = 500
V
−
−
−
−
−
−
−
65
70
75
80
85
90
95
O = 2VPP
2nd−Harmonic
−
−
−
−
−
1
2
3
4
5
3rd−Harmonic
−
100
−
−
−
−
−
1
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
5
4
3
2
0
1
2
3
4
5
±
±
Supply Voltage ( VS)
Input Voltage (V)
Figure 32.
Figure 33.
INPUT VOLTAGE AND CURRENT NOISE DENSITY
BUFFER OUTPUT IMPEDANCE
100
10
1
100
10
1
√
Input Current Noise (2.1pA/ Hz)
√
Input Voltage Noise (4.8nV/ Hz)
100
1k
10k 100k 1M
10M
10k
100k
1M
10M
100M
1G
Frequency (Hz)
Frequency (Hz)
Figure 34.
Figure 35.
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TYPICAL CHARACTERISTICS: VS = ±5V (continued)
At TA = +25°C, IQ = 11.2mA, and RL = 500Ω, unless otherwise noted.
BUFFER GROUP DELAY TIME vs FREQUENCY
BUFFER OUTPUT VOLTAGE AND CURRENT LIMITATIONS
1.2
1.0
0.8
0.6
0.4
0.2
0
5
1W Internal
Power Limit
4
Ω
100
3
2
1
0
1
2
3
4
5
Load Line
Ω
25 Load Line
Ω
50 Load Line
−
−
−
−
−
1W Internal
Power Limit
−
0.2
0
100 200 300 400 500 600 700 800 900 1000
Frequency (MHz)
Output Current (mA)
Figure 36.
Figure 37.
QUIESCENT CURRENT vs TEMPERATURE
POWER-SUPPLY REJECTION RATIO vs FREQUENCY
16
15
14
13
12
11
10
9
50
45
40
35
30
25
20
15
10
5
+PSRR
−
PSRR
8
7
6
−
0
−
20
40
0
20
40
60
80
100
120
10k
100k
1M
10M
100M
_
Ambient Temperature ( C)
Frequency (Hz)
Figure 38.
Figure 39.
VOLTAGE RANGE vs TEMPERATURE
OUTPUT CURRENT vs TEMPERATURE
4.10
4.05
4.00
3.95
3.90
56.0
55.8
55.6
55.4
55.2
55.0
54.8
54.6
54.4
54.2
54.0
+VO
Output Current Sinking, Sourcing
−
VO
−
−
−
−
20
40
20
0
20
40
60
80
100
120
40
0
20
40
60
80
100
120
_
_
Ambient Temperature ( C)
Temperature ( C)
Figure 40.
Figure 41.
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TYPICAL CHARACTERISTICS: VS = ±5V (continued)
At TA = +25°C, IQ = 11.2mA, and RL = 500Ω, unless otherwise noted.
DC DRIFT vs TEMPERATURE
C-OUTPUT BIAS CURRENT vs TEMPERATURE
30
25
20
15
10
5
6
5
4
3
2
1
0
40
30
20
10
0
Five Representative Units
Buffer Input Offset Voltage (VOS
)
Buffer Input Bias Current (IB)
−
10
20
30
40
−
−
−
0
−
−
20
40
0
20
40
60
80
100
120
−
−
20
40
0
20
40
60
80
100
120
_
Ambient Temperature ( C)
_
Ambient Temperature ( C)
Figure 42.
Figure 43.
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APPLICATION INFORMATION
The OPA860 combines a high-performance buffer
BUFFER SECTION—AN OVERVIEW
with
a
transconductance
section.
This
transconductance section is discussed in the OTA
(Operational Transconductance Amplifier) section of
this data sheet. Over the years and depending on the
writer, the OTA section of an op amp has been
The buffer section of the OPA860 is an 1600MHz,
4000V/µs closed-loop buffer that can be used as a
building block for AGC amplifiers, LED driver circuit,
integrator for fast pulse, fast control loop amplifiers,
and control amplifiers for capacitive sensors and
active filters. The Buffer section does not share the
bias circuit of the OTA section; thus, it is not affected
by changes in the IQ adjust resistor (RADJ).
referred
to
as
a
Diamond
Transistor,
Voltage-Controlled Current source, Transconductor,
Macro Transistor, or positive second-generation
current conveyor (CCII+). Corresponding symbols for
these terms are shown in Figure 44.
TRANSCONDUCTANCE (OTA) SECTION—AN
OVERVIEW
3
C
VIN1
1
B
The symbol for the OTA section is similar to a
transistor (see Figure 44). Applications circuits for the
OTA look and operate much like transistor
circuits—the transistor is also a voltage-controlled
current source. Not only does this characteristic
simplify the understanding of application circuits, it
aids the circuit optimization process as well. Many of
the same intuitive techniques used with transistor
designs apply to OTA circuits. The three terminals of
the OTA are labeled B, E, and C. This labeling calls
attention to its similarity to a transistor, yet draws
distinction for clarity. While the OTA is similar to a
transistor, one essential difference is the sense of the
C-output current: it flows out the C terminal for
positive B-to-E input voltage and in the C terminal for
negative B-to-E input voltage. The OTA offers many
advantages over a discrete transistor. The OTA is
self-biased, simplifying the design process and
reducing component count. In addition, the OTA is far
more linear than a transistor. Transconductance of
the OTA is constant over a wide range of collector
IOUT
VIN2
2
E
Diamond Transistor
Voltage−Controlled Current Source
Transconductor
Macro Transistor
Current Conveyor II+
C
E
VIN1
VIN2
B
Z
IOUT
CCII+
Figure 44. Symbols and Terms
Regardless of its depiction, the OTA section has a
high-input impedance (B input), a low-input/output
impedance (E input), and a high impedance current
source output (C output).
currents—this feature implies
improvement of linearity.
a
fundamental
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BASIC CONNECTIONS
It is also possible to vary the quiescent current with a
control signal. The control loop in Figure 45 shows
1/2 of a REF200 current source used to develop
100mV on R1. The loop forces 125mV to appear on
R2. Total quiescent current of the OPA860 is
approximately 37 × I1, where I1 is the current made to
flow out of pin 1.
Figure 46 shows basic connections required for
operation. These connections are not shown in
subsequent circuit diagrams. Power-supply bypass
capacitors should be located as close as possible to
the device pins. Solid tantalum capacitors are
generally best.
QUIESCENT CURRENT CONTROL PIN
V+
The quiescent current of the transconductance
OPA860
portion of the OPA860 is set with a resistor, RADJ
,
1/2 REF200
µ
100
A
connected from pin 1 to –VS. It affects only the
operating currents of OTA sections. The bias circuitry
of the Buffer section is independent of the bias
circuitry for the OTA section; therefore, the quiescent
current cannot go below 5.8mA. The maximum
quiescent current is 12.7mA. RADJ should be set
between 50Ω and 1kΩ for optimal performance of the
OTA section. This range corresponds to the 12.5mA
I
Q Adjust
R1
1
I1
Ω
1.25k
R2
Ω
425
TLV2262
quiescent current for RADJ = 50Ω, and 9mA for RADJ
=
1kΩ. If the IQ adjust pin is connected to the negative
supply, the quiescent current will be set by the 250Ω
internal resistor.
Figure 45. Optional Control Loop for Setting
Quiescent Current
Reducing or increasing the quiescent current for the
OTA section controls the bandwidth and AC behavior
as well as the transconductance. With RADJ = 250Ω,
this sets approximately 11.2mA total quiescent
current at 25°C. It may be appropriate in some
applications to trim this resistor to achieve the desired
quiescent current or AC performance.
Applications circuits generally do not show the
resistor RQ, but it is required for proper operation.
With
a
fixed RADJ resistor, quiescent current
increases with temperature (see Figure 43 in the
Typical Characteristics section). This variation of
current with temperature holds the transconductance,
gm, of the OTA relatively constant with temperature
(another advantage over a transistor).
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Ω
RQ = 250 , roughly sets IQ = 11.2mA.
+5V(1)
1
2
3
4
8
7
6
5
µ
0.1 F
+VS
RADJ
RS
Ω
250
+
Ω
Ω
(25 to 200 )
µ
2.2 F
+1
Solid Tantalum
49.9
−
VS
(1)
−
5V
Ω
µ
0.1 F
VO
VI
RS
µ
2.2 F
+
Ω
Ω
(25 to 200 )
Solid
Tantalum
Ω
49.9
±
= 6.5V absolute maximum.
NOTE: (1) VS
Figure 46. Basic Connections
With this control loop, quiescent current will be nearly
constant with temperature. Since this differs from the
temperature-dependent behavior of the internal
Common-E Amplifier or Forward Amplifier
Figure 47 compares the common-emitter
current
source,
other
temperature-dependent
configuration for a BJT with the common-E amplifier
for the OTA section. There are several advantages in
using the OTA section in place of a BJT in this
configuration. Notably, the OTA does not require any
biasing, and the transconductance gain remains
constant over temperature. The output offset voltage
is close to 0, compared with several volts for the
common-emitter amplifier.
behavior may differ from that shown in the Typical
Characteristics. The circuit of Figure 45 will control
the IQ of the OTA section of the OPA860 somewhat
more accurately than with a fixed external resistor,
RQ. Otherwise, there is no fundamental advantage to
using this more complex biasing circuitry. It does,
however,
demonstrate
the
possibility
of
signal-controlled quiescent current. This capability
may suggest other possibilities such as AGC,
dynamic control of AC behavior, or VCO.
The gain is set in a similar manner as for the BJT
equivalent with Equation 1:
RL
G +
1
g
BASIC APPLICATIONS CIRCUITS
m ) RE
(1)
Most applications circuits for the OTA section consist
of a few basic types, which are best understood by
analogy to a transistor. Used in voltage-mode, the
OTA section can operate in three basic operating
states—common emitter, common base, and
common collector. In the current-mode, the OTA can
be useful for analog computation such as current
amplifier, current differentiator, current integrator, and
current summer.
Just as transistor circuits often use emitter
degeneration, OTA circuits may also use
degeneration. This option can be used to reduce the
effects that offset voltage and offset current might
otherwise have on the DC operating point of the OTA.
The E-degeneration resistor may be bypassed with a
large capacitor to maintain high AC gain. Other
circumstances may suggest a smaller value capacitor
used to extend or optimize high-frequency
performance.
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The forward amplifier shown in Figure 48 and
Figure 49 corresponds to one of the basic circuits
used to characterize the OPA860. Extended
characterization of this topology appears in the
V+
Typical Characteristics section of this data sheet.
RS
RL
VO
VO
8
R1
Ω
160
RC
500
VI
C
Inverting Gain
VOS = Several Volts
Ω
3
B
OTA
VI
RS
RE
E
2
G = 5V/V
IQ = 11.2mA
RE
−
V
Ω
78
(a) Common−Emitter Amplifier
Transconductance varies over temperature.
Figure 48. Forward Amplifier Configuration and
Test Circuit
8
VO
C
Ω
100
3
B
RL
OTA
VI
E
2
RL1
VO
Network
Noninverting Gain
VOS = 0V
RE
8
Analyzer
3
RIN
OTA
50W
(b) Common−E Amplifier
Transconductance remains constant over temperature.
R1
RL2
rE
100W
2
VI
RL = RL1 + RL2 || RIN
RE
Figure 47. Common-Emitter vs Common-E
Amplifier
The transconductance of the OTA with degeneration
can be calculated by Equation 2:
RL
1
rE
=
=
G =
gm
RE + rE
1
gm_deg
+
1
g
m ) RE
1
At IQ = 11.2mA
rE
= 8W
(2)
102mA/V
A positive voltage at the B-input, pin 3, causes a
positive current to flow out of the C-input, pin 8.
Figure 47b shows an amplifier connection of the
OTA, the equivalent of a common-emitter transistor
amplifier. Input and output can be ground-referenced
without any biasing. The amplifier is noninverting
because of the sense of the output current.
RL
G =
at IQ = 11.2mA
RE + 8W
Figure 49. Forward Amplifier Design Equations
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Common-C Amplifier
RL
RL
RE
G +
[ *
1
RE ) gm
Figure 50b shows the OTA connected as an
E-follower—a voltage buffer. It is interesting to notice
that the larger the RE resistor, the closer to unity gain
the buffer will be. If the OTA section is to be used as
a buffer, use RE ≥ 500Ω for best results. For the OTA
section used as a buffer, the gain is given by
Equation 3:
(4)
This low impedance can be converted to a high
impedance by inserting the buffer amplifier in series.
Current-Mode Analog Computations
As mentioned earlier, the OTA section of the OPA860
can be used advantageously for analog computation.
Among the application possibilities are functionality
as a current amplifier, current differentiator, current
integrator, current summer, and weighted current
summer. Table 1 lists these different uses with the
associated transfer functions.
1
G +
[ 1
1
R
1 ) gm
E
(3)
V+
G = 1
VOS = 0.7V
These functions can easily be combined to form
active filters. Some examples using these
current-mode functions are shown later in this
document.
VI
VO
RE
−
V
OPA860 APPLICATIONS
(a) Common−Collector Amplifier
(Emitter Follower)
The OPA860 is comprised of both the OTA section
and the Buffer section. This applications information
focuses more on using both sections together to form
various useful amplifiers. A more thorough description
of the OTA section in filter applications can be found
in the OPA861 data sheet, available for download at
www.ti.com.
1
G +
+ 1
1
R
1 ) gm
E
1
RO +
gm
8
C
Ω
100
3
B
G = 1
VO = 0V
V+
OTA
VI
E
2
RL
RE
VO
VO
Noninverting Gain
VOS = Several Volts
(b) Common−C Amplifier
(Buffer)
R1
VIN
RE
Figure 50. Common-Collector vs Common-C
Amplifier
V-
(a) Common-Base Amplifier
A low value resistor in series with the B OTA and
buffer inputs is recommended. This resistor helps
isolate trace parasitic from the inputs, reduces any
tendency to oscillate, and controls frequency
response peaking. Typical resistor values are from
25Ω to 200Ω.
RL
RL
RE
G =
= -
1
RE +
gm
8
VO
C
100W
3
B
Inverting Gain
VOS = 0V
OTA
E
2
Common-B Amplifier
RL
Figure 51 shows the Common-B amplifier. This
configuration produces an inverting gain and a low
impedance input. Equation 4 shows the gain for this
configuration.
RE
VIN
(b) Common-B Amplifier
Figure 51. Common-Base Transistor vs
Common-B OTA
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Direct Feedback Amplifier
The gain for this topology is given by Equation 5:
R
3 ) R5
The direct feedback amplifier (shown in Figure 53)
topology has been used to characterize the OPA860.
Extended characterization of this topology appears in
the Typical Characteristics section of this data sheet.
This topology is obtained by closing the loop between
the C-output and the E-input of the common-E
topology, and then buffered.
R3
2R5
2
G +
[ 1 )
1
R5 ) 2 g
m
(5)
Table 1. Current-Mode Analog Computation Using the OTA Section
FUNCTIONAL ELEMENT
TRANSFER FUNCTION
IMPLEMENTATION WITH THE OTA SECTION
IOUT
IIN
R1
R2
R1
Current Amplifier
IOUT
+
IIN
R2
IOUT
IIN
1
IOUT
+
C
Current Integrator
R
ŕ
C R IINdt
IOUT
n
Current Summer
ȍ
j+1
I
OUT + *
Ij
I1
I2
In
IOUT
n
Rj
R
Weighted Current Summer
ȍ
j+1
I
OUT + *
Ij
R1
Rn
R
R
I1
In
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Current-Feedback Amplifier
Building current-feedback amplifier with the
loop amplifiers show an integrator behavior from DC
to the frequency, represented by the RC time
constant of the network from the C-output to GND.
Above this frequency, they operate as an amp with
constant gain. The series connection increases the
overall gain to about 110dB and thus minimizes the
control loop deviation. The differential configuration at
the inputs enables one to apply the measured output
signal and the reference voltage to two identical
high-impedance inputs. The output buffer decouples
the C-output of the second OTA in order to insure the
AC performance and to drive subsequent output
stages.
a
OPA860 is extremely simple. One advantage of
building current-feedback amplifier with the
a
OPA860 instead of getting an off-the-shelf
current-feedback amplifier is the control gained on the
bandwidth though the use of external capacitors.
Figure 54 shows a typical circuit for the OPA860 in a
noninverting current-feedback amplifier configuration.
Input and output parasitic capacitances are shown.
R1 is the output impedance of the C-output of the
OTA section. C1 is the output parasitic capacitance
on the C-output pin of the OTA-section. C2 is the
input parasitic capacitance for the input of the Buffer
section. As shown in Equation 6, the poles formed by
R1, C1, R2, and C2 control the frequency response.
The frequency response in this configuration is shown
in Figure 52. Setting an external capacitor on the
C-output to ground allows adjusting the bandwidth.
9
6
3
0
R
aǒ1 ) FǓ
R
VOUT
G
+
R
VIN
1
R
1 ) ǒ FǓ
2
[
(
)
]
1 ) RG
1 ) s R1C1 ) R1C2 ) R2C2 ) s R1C1C2
g
m
1
−
−
−
3
6
9
(6)
Note that both peaking and bandwidth can be
adjusted by changing the feedback resistance, RF.
G = +2V/V
Ω
RL = 500
VO = 2VPP
−
12
Control-Loop Amplifier
1M
10M
100M
Frequency (Hz)
1G
A new type of control loop amplifier for fast and
precise control circuits can be designed with the
OPA860. The circuit of Figure 55 shows a series
connection of two voltage control current sources that
have an integral (and at higher frequencies, a
proportional) behavior versus frequency. The control
Figure 52. Current-Feedback Architecture
Frequency Response
R2
80.6
R4
Ω
453
Network
Analyzer
+5V
Ω
VO
5
6
+1
Ω
50
7
8
Source
R1
RIN
C
Ω
100
Ω
50
3
B
R3
OTA
VI
Ω
301
G = +2V/V
IQ = 20mA
E
2
Ω
50
1
4
RQ
Ω
250
R5
Ω
133
−
5V
Figure 53. Direct Feedback Amplifier Specification and Test Circuit
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OPA860
R2
Ω
50
VOUT
Ω
200
+1
VIN
C1
R1
C2
Ω
500
Ω
50
rE
RF
Ω
259
RG
Ω
249
Figure 54. OPA860 Used in a Noninverting Current-Feedback Architecture
6
8
5
+1
VOUT
3
8
2
Ω
Ω
180
2
10pF
10pF
VREF
3
Ω
Ω
33
Ω
Ω
10
10
33
180
6
5
VIN
+1
Figure 55. Control-Loop Amplifier Using Two OPA860s
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DC-Restore Circuit
Comparator
The OPA860 can be used advantageously with an
An interesting and also cost-effective circuit solution
using the OPA860 as a low-jitter comparator is shown
in Figure 57. At the same time, this circuit uses a
positive and negative feedback. The input is
connected to the inverting E-input. The output signal
operational amplifier, here the OPA820, as
a
DC-restore circuit. Figure 56 illustrates this design.
Depending on the collector current of the
transconductance amplifier (OTA) of the OPA860, a
switching function is realized with the diodes D1 and
D2.
is applied in
a direct feedback over the two
antiparallel, connected gallium-arsenide diodes back
to the emitter. A second feedback path over the RC
When the C-output is sourcing current, the capacitor
C1 is being charged. When the C-output is sinking
current, D1 is turned off and D2 is turned on, letting
the voltage across C1 be discharged through R2.
combination to the base, which is
a positive
feedback, accelerates the output voltage change
when the input voltage crosses the threshold voltage.
The output voltage is limited to the threshold voltage
of the back-to-back diodes.
The condition to charge C1 is set by the voltage
difference between VREF and VOUT. For the OTA
C-output to source current, VREF has to be greater
than VOUT. The rate of charge of C1 is set by both R1
and C1. The discharge rate is given by R2 and C1.
C1
100pF
Ω
Ω
20
150
5
6
VIN
+1
VOUT
OPA656
R2
100k
D1
D2
Ω
Ω
20
D1, D2 = 1N4148
Ω
RQ = 1k
R1
CCII
Ω
40.2
E
2
8
C
The OTA amplifier works as a current conveyor (CCII) in this circuit, with a current gain of 1.
R1 and C1 set the DC restoration time constant.
B
3
D1 adds a propogation delay to the DC restoration.
R2 and C1 set the decay time constant.
R2
Ω
100
VREF
Figure 56. DC Restorer Circuit
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C3
2.2pF
…
0.5pF 2.5pF
Offset
Trim
+5V
R5
R8
Ω
47k
Ω
27k
R2
Ω
10k
+5V
+5V
1
C3
C3
µ
2.2 F
−
µ
5V
6
2.2 F
R1
100k
RC5
Ω
150
Ω
RC5
RS
Ω
47
3
2
7
Ω
150
RC5
150
8
1
4
VOUT
OTA
BUF602
Ω
5
VIN
+1
C3
4
5
µ
2.2 F
RQ
C3
Ω
250
R2
µ
2.2 F
Ω
100k
−
5V
−
5V
D1
D2
DMF3068A
Figure 57. Comparator (Low Jitter)
T
gm
C
Integrator for ns-Pulse
ŕ
O
VO +
VBE dt
One very interesting application using the OPA860 in
physical measurement technology is an open-loop
ns-integrator (shown in Figure 58) which can process
pulses with an amplitude of ±2.5V, have a rise/fall
time of as little as 2ns, and also have a pulse width of
more than 8ns. The voltage-controlled current source
charges the integration capacitor linearly according to
Equation 7:
(8)
Where:
•
•
•
VO = Output Voltage
T = Integration Time
C = Integration Capacitance
t
C
VC + VBE gm
(7)
200W
5
6
VO
+1
Where:
8
27pF
C
•
•
•
•
•
VC = Voltage At Pin 8
VBE = Base-Emitter Voltage
gm = Transconductance
t = Time
780W
50W
3
B
OTA
VI
E
2
620W
820W
C = Integration Capacitance
1mF
kW
50
The output voltage is the time integral of the input
voltage. It can be calculated from Equation 8:
-5V
+5V
Figure 58. Integrator for ns-Pulses
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Video Luminance Matrix
The inverting amplifier in Figure 59 amplifies the
three input voltages that correspond to the luminance
section of the RGB color signal. Different feedback
VIN
VOUT
resistances weight the voltages differently, resulting
in an output voltage consisting of 30% of the red,
59% of the green, and 11% of the blue section of the
input voltage. The way in which the signal is weighted
corresponds to the transformation equation for
converting RGB pictures into B/W pictures. The
output signal is the black/white replay. It might drive a
monochrome control monitor or an analog printer
(hardcopy output).
Figure 60. State Variable Filter Block Diagram
C
E
Ω
200
E
C
B
5
6
VLUMINANCE
+1
8
C1
C1
B
C
Ω
150
3
B
OTA
R2
x1
E
2
x1
R3
R1
(1)
Ω
665
Ω
200
VRED
RV
VIN
VOUT
Ω
(1)
RQ = 250
Ω
340
(IQ = 11.2mA)
VGREEN
Figure 61. State Variable Filter Using the OPA860
NOTE: (1) Resistors shown are 1% values
that produce 30%/59%/11% R/G/B mix.
(1)
Ω
1820
VBLUE
The transfer function is then:
a0
R1
RV
1
( )
H s +
+ *
s2 ) C1s ) C0
R
R
Figure 59. Video Luminance Matrix
1
1 ) sC2
2 ) s2C1C2R1R2
R
3
(9)
State-Variable Filters
1
w0 +
Ǹ
The ability of the OPA860 to easily drive a capacitor
can be put to good use in implementing state-variable
filters. A state-variable filter, or KHN filter, can be
represented with integrators and coefficients. For
example, the filter represented in the block diagram
of Figure 60 can easily be implemented with two
OPA860s, as shown in Figure 61.
C1C2R1R2
(10)
C1
C2
R3
Q + Ǹ
Ǹ
R1R2
(11)
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DESIGN-IN TOOLS
The total output spot noise voltage can be computed
as the square root of the sum of all squared output
noise voltage contributors. Equation 12 shows the
general form for the output noise voltage using the
terms shown in Figure 62.
DEMONSTRATION BOARDS
A printed circuit board (PCB) is available to assist in
the initial evaluation of circuit performance using the
OPA860. This module is available free, as an
unpopulated PCB delivered with descriptive
documentation. The summary information for the
board is shown below:
2
2
2
RL
L
2
ǒ
bnǓ
ǒ
Ǔ
ƪ
ƫ
) ƪ
ƫR
g
eO
+
en ) R i ) 4kTRS ƪ ƫ RGibi ) 4kTRG
RG
g
m
Ǹ
S
1
1
)
m
(12)
For the buffer, the noise model is shown in Figure 63.
Equation 13 shows the general form for the output
noise voltage using the terms shown in Figure 63.
LITERATURE
REQUEST
NUMBER
BOARD PART
NUMBER
PRODUCT
PACKAGE
OPA860ID
SO-8
DEM-OTA-SO-1A
SBOU035A
The board can be requested on Texas Instruments
web site (www.ti.com).
en
VO
MACROMODELS AND APPLICATIONS
SUPPORT
RS
in
Computer simulation of circuit performance using
SPICE is often useful when analyzing the
performance of analog circuits and systems. This
principle is particularly true for Video and RF amplifier
circuits where parasitic capacitance and inductance
can have a major effect on circuit performance. A
SPICE model for the OPA860 is available through the
Texas Instruments web page (www.ti.com). These
models do a good job of predicting small-signal AC
and transient performance under a wide variety of
operating conditions. They do not do as well in
predicting the harmonic distortion. These models do
not attempt to distinguish between the package types
in their small-signal AC performance.
√
4kTRS
Figure 63. Buffer Noise Analysis Model
2
2
Ǹ
ǒ
SǓ
eO + en ) inR ) 4kTRS
(13)
THERMAL ANALYSIS
Due to the high output power capability of the
OPA860, heatsinking or forced airflow may be
required under extreme operating conditions.
Maximum desired junction temperature will set the
maximum allowed internal power dissipation as
described below. In no case should the maximum
junction temperature be allowed to exceed +150°C.
NOISE PERFORMANCE
The OTA noise model consists of three elements: a
voltage noise on the B-input; a current noise on the
B-input; and a current noise on the E-input. Figure 62
shows the OTA noise analysis model with all the
noise terms included. In this model, all noise terms
are taken to be noise voltage or current density terms
in either nV/√Hz or pA/√Hz.
Operating junction temperature (TJ) is given by
TA + PD
(PD) is the sum of quiescent power (PDQ) and
additional power dissipated in the output stage (PDL
× θJA. The total internal power dissipation
)
to deliver load power. Quiescent power is simply the
specified no-load supply current times the total supply
voltage across the part. PDL will depend on the
required output signal and load but would, for a
grounded resistive load, be at a maximum when the
output is fixed at a voltage equal to 1/2 of either
supply voltage (for equal bipolar supplies). Under this
en
VO
RL
RS
RG
ibn
ibi
2
condition, PDL = VS /(4 × RL) where RL includes
feedback network loading.
√
√
4kTRS
4kTRS
Note that it is the power in the output stage and not
into the load that determines internal power
dissipation.
Figure 62. OTA Noise Analysis Model
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As a worst-case example, compute the maximum TJ
using an OPA860ID in the circuit of Figure 53
operating at the maximum specified ambient
temperature of +85°C and driving a grounded 20Ω
load.
supplies (for bipolar operation) will improve
2nd-harmonic distortion performance. Larger (2.2µF
to 6.8µF) decoupling capacitors, effective at lower
frequency, should also be used on the main supply
pins. These may be placed somewhat farther from
the device and may be shared among several
devices in the same area of the PC board.
PD = 10V × 11.2mA + 52/(4 × 20Ω) = 424mW
Maximum TJ = +85°C + (0.43W × 125°C/W) = 139°C.
c) Careful selection and placement of external
components will preserve the high-frequency
performance of the OPA860. Resistors should be a
very low reactance type. Surface-mount resistors
work best and allow a tighter overall layout. Metal film
or carbon composition, axially-leaded resistors can
also provide good high-frequency performance.
Again, keep their leads and PC board traces as short
as possible. Never use wirewound type resistors in a
high-frequency application.
Although this is still well below the specified
maximum junction temperature, system reliability
considerations may require lower tested junction
temperatures. The highest possible internal
dissipation will occur if the load requires current to be
forced into the output for positive output voltages or
sourced from the output for negative output voltages.
This puts a high current through a large internal
voltage drop in the output transistors. The output V-I
plot shown in the Typical Characteristics includes a
boundary for 1W maximum internal power dissipation
under these conditions.
d) Connections to other wideband devices on the
board may be made with short, direct traces or
through onboard transmission lines. For short
connections, consider the trace and the input to the
next device as a lumped capacitive load. Relatively
wide traces (50mils to 100mils) should be used,
preferably with ground and power planes opened up
around them. If a long trace is required at the buffer
output, and the 6dB signal loss intrinsic to a
doubly-terminated transmission line is acceptable,
implement a matched impedance transmission line
using microstrip or stripline techniques (consult an
ECL design handbook for microstrip and stripline
layout techniques). A 50Ω environment is normally
not necessary on board, and in fact, a higher
impedance environment will improve distortion as
shown in the distortion versus load plots.
BOARD LAYOUT GUIDELINES
Achieving
optimum
performance
with
a
high-frequency amplifier like the OPA860 requires
careful attention to board layout parasitics and
external component types. Recommendations that
will optimize performance include:
a) Minimize parasitic capacitance to any AC ground
for all of the signal I/O pins. Parasitic capacitance on
the output and inverting input pins can cause
instability: on the noninverting input, it can react with
the source impedance to cause unintentional
bandlimiting. To reduce unwanted capacitance, a
window around the signal I/O pins should be opened
in all of the ground and power planes around those
pins. Otherwise, ground and power planes should be
unbroken elsewhere on the board.
e) Socketing a high-speed part like the OPA860 is
not recommended. The additional lead length and
pin-to-pin capacitance introduced by the socket can
create an extremely troublesome parasitic network
that makes it almost impossible to achieve a smooth,
stable frequency response. Best results are obtained
by soldering the OPA860 onto the board.
b) Minimize the distance (< 0.25") from the
power-supply
pins
to
high-frequency
0.1µF
decoupling capacitors. At the device pins, the ground
and power-plane layout should not be in close
proximity to the signal I/O pins. Avoid narrow power
and ground traces to minimize inductance between
the pins and the decoupling capacitors. The
power-supply connections should always be
decoupled with these capacitors. An optional supply
decoupling capacitor (0.1µF) across the two power
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INPUT AND ESD PROTECTION
These diodes provide moderate protection to input
overdrive voltages above the supplies as well. The
protection diodes can typically support 30mA
continuous current. Where higher currents are
possible (for example, in systems with ±15V supply
parts driving into the OPA860), current-limiting series
resistors should be added into the two inputs. Keep
these resistor values as low as possible since high
values degrade both noise performance and
frequency response.
The OPA860 is built using
a very high-speed
complementary bipolar process. The internal junction
breakdown voltages are relatively low for these very
small geometry devices. These breakdowns are
reflected in the Absolute Maximum Ratings table. All
device pins are protected with internal ESD protection
diodes to the power supplies as shown in Figure 64.
+VCC
External
Pin
Internal
Circuitry
−
VCC
Figure 64. Internal ESD Protection
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Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (June 2006) to Revision C .................................................................................................... Page
•
Changed storage temperature range rating in Absolute Maximum Ratings table from –40°C to +125°C to –65°C to
+125°C................................................................................................................................................................................... 2
Changes from Revision A (January 2006) to Revision B ............................................................................................... Page
•
•
Changed Figure 49—corrected equations........................................................................................................................... 16
Changed Figure 58—corrected resistor value .................................................................................................................... 22
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PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA860ID
ACTIVE
SOIC
SOIC
D
D
8
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
OPA
860
Samples
Samples
OPA860IDR
ACTIVE
2500 RoHS & Green
NIPDAU
OPA
860
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA860IDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC
SPQ
Length (mm) Width (mm) Height (mm)
356.0 356.0 35.0
OPA860IDR
D
8
2500
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
SOIC
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
OPA860ID
D
8
75
506.6
8
3940
4.32
Pack Materials-Page 3
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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