OPA928 [TI]
具有 RRIO 的高电压、毫微微安输入偏置精密 e-trim™ 运算放大器;
| 型号： | OPA928 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 RRIO 的高电压、毫微微安输入偏置精密 e-trim™ 运算放大器 放大器 运算放大器 |
| 文件： | 总25页 (文件大小：1646K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OPA928
ZHCSNI6 –MARCH 2023
OPA928 16V、毫微微安输入偏置、精密、轨到轨输入/输出、e-trim™ 运算放大
器
1 特性
3 说明
• 超低输入偏置电流：
– 25ºC 和85ºC 时为20fA（测试最大值）
• 低噪声：
– 0.1 Hz 时为0.05fA/√Hz
– 1 kHz 时为15nV/√Hz
• 高直流精度
OPA928 是新一代 16V、毫微微安输入偏置 e-trim™ 运
算放大器。该器件在 25ºC 和85ºC 时提供 20fA（最大
值）的超低输入偏置电流。OPA928 输入偏置性能在两
种温度下均进行了量产测试。
该器件具有接近零的输入偏置以及出色的直流精度和交
流性能，包括轨到轨输入/输出、低失调电压（±5µV，
典型值）、低温漂（±0.1µV/°C，典型值）和低电流噪
声（ 0.1Hz 时为 0.05fA/ √Hz ） 。这些特性使得
OPA928 成为低光光电二极管和高源阻抗应用的理想选
择。
– ±5µV 输入失调电压
– ±0.1µV/°C 失调电压漂移
• 宽带宽：2.5MHz GBW
• 低静态电流：275µA
• EMI 和RFI 已滤除的输入
OPA928 具有内部高精度保护缓冲器，可在敏感应用中
保护高阻抗输入布线免受不良电流泄漏的影响。
OPA928 封装和引脚排列旨在支持低泄漏电路设计。
• 高精度保护缓冲器
• 宽电源电压：±2.25 V 至±8 V，4.5 V 至16 V
• 轨到轨输入和输出
OPA928 的额定工作温度范围为-40°C 至+125°C。
• 高容性负载驱动能力：1nF
• 工作温度范围：–40ºC 至+125ºC
• 行业标准封装：
封装信息
器件型号
封装(1)
封装尺寸（标称值）
– 8 引脚SOIC
OPA928
D（SOIC，8） 4.90mm × 3.90mm
2 应用
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 电化学仪表- pH 计
• 实验室和现场仪表
• 质谱仪
• 离子色谱分析(IC) 仪器
• 分光光度计
1000
10 G
IBꢁ
IB−
100
Guard
–
OPA928
VOUT
10
1
+
GND
GND
高增益跨阻放大器
0.1
0.01
0.001
25 30 35 40 45 50 55 60 65 70 75 80 85
Temperature [ꢀC]
输入偏置电流与温度间的关系
（VS = 16V、VCM = 1/2 Vs）
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOSA77
OPA928
ZHCSNI6 –MARCH 2023
www.ti.com.cn
Table of Contents
8 Application and Implementation..................................10
8.1 Application Information............................................. 10
8.2 Typical Applications.................................................. 12
8.3 Power-Supply Recommendations.............................16
8.4 Layout....................................................................... 17
9 Device and Documentation Support............................19
9.1 Device Support......................................................... 19
9.2 Documentation Support............................................ 19
9.3 接收文档更新通知..................................................... 19
9.4 支持资源....................................................................19
9.5 Trademarks...............................................................20
9.6 静电放电警告............................................................ 20
9.7 术语表....................................................................... 20
10 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
Thermal Information..........................................................4
6.4 Electrical Characteristics.............................................5
7 Detailed Description........................................................7
7.1 Overview.....................................................................7
7.2 Functional Block Diagram...........................................7
7.3 Feature Description.....................................................8
7.4 Device Functional Modes............................................9
Information.................................................................... 20
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
March 2023
*
Initial release.
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5 Pin Configuration and Functions
IN+
GRD
NC
IN–
GRD
Out
V+
1
2
3
4
8
7
6
5
V–
Not to scale
图5-1. D Package, 8-Pin SOIC (Top View)
表5-1. Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
2, 7
1
GRD
IN+
Guard buffer
—
Input
Noninverting input
8
Input
Inverting input
IN–
DNC
OUT
V+
3
Do not connect (leave floating)
Output
—
6
Output
Power
5
Positive (highest) power supply
Negative (lowest) power supply
4
Power
V–
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
Dual supply
±20
40
VS
Supply voltage
V
Single supply
Common-mode
Differential(2)
(V+) + 0.5
±0.5
(V–) –0.5
Signal input pin voltage
V
Signal input pin current
Output short circuit(3)
Junction temperature
Storage temperature
±10
mA
ISC
TJ
Continuous
150
150
°C
Tstg
–65
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) Input pins are diode-clamped to the power-supply rails. Current limit input signals that can swing more than 0.5 V beyond the supply
rails to 10 mA or less.
(3) Short-circuit to ground.
6.2 ESD Ratings
VALUE
±3000
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001((1))
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002((2))
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
±2.25
4.5
NOM
MAX
±8
UNIT
Dual supply
VS
V
Supply voltage, VS = (V+) –(V–)
Single supply
16
RH
TA
Relative humidity
50
%
Ambient temperature
125
°C
–40
Thermal Information
OPA928
D (SOIC)
8 PINS
113.9
51.4
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
58.0
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
9.0
ψJT
57.1
ψJB
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.4 Electrical Characteristics
at TA = 25°C, VS = 4.5 V to 16 V, VCM = VOUT = VS / 2, and RL = 10 kΩconnected to VS/2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT BIAS CURRENT
±1
±20
±20
±20
±20
IB
Input bias current
fA
fA
TA = –40°C to +85°C
TA = –40°C to +85°C
±1
IOS
Input offset current
OFFSET VOLTAGE
±5
±8
±25
±75
TA = –40°C to +125°C
VCM = (V+) –1.5 V
µV
±10
±25
±50
VOS
Input offset voltage
±150
TA = –40°C to +125°C
VCM = (V+) –1.5 V
See Typical Characteristics
(V+) –3 V < VCM < (V+) –1.5 V
TA = –40°C to +125°C
±0.1
±0.5
±0.8
±1.0
Input offset voltage
drift
dVOS/dT
µV/°C
µV/V
Power-supply
rejection ratio
PSRR
±0.3
TA = –40°C to +125°C
NOISE
1.4
7
(V–) –0.1 V < VCM < (V+) –3 V
Input voltage noise
f = 0.1 Hz to 10 Hz
µVPP
(V+) –1.5 V < VCM < (V+) + 0.1 V
f = 100 Hz
f = 1 kHz
f = 100 Hz
f = 1 kHz
18
15
53
24
(V–) –0.1 V < VCM < (V+) –3 V
Input voltage noise
density
en
nV/√Hz
(V+) –1.5 V < VCM < (V+) + 0.1 V
Input current noise
density
in
f = 0.1 Hz
0.05
fA/√Hz
INPUT VOLTAGE
Common-mode
voltage
(V–) –
VCM
(V+) + 0.1
V
0.1
120
114
96
140
126
120
100
(V–) –0.1 V < VCM < (V+) –3 V
TA = –40°C to +125°C
TA = –40°C to +125°C
dB
Common-mode
rejection ratio
CMRR
(V+) –1.5 V < VCM < (V+)
86
See Typical Characteristics
(V+) –3 V < VCM < (V+) –1.5 V
INPUT IMPEDANCE
ZID
ZIC
Differential
100 || 1.6
1 || 6.4
MΩ|| pF
1013Ω|| pF
Common-mode
OPEN-LOOP GAIN
124
114
126
120
134
126
140
134
(V–) + 0.6 V < VO < (V+) –0.6 V,
RL = 2 kΩ
TA = –40°C to +125°C
TA = –40°C to +125°C
Open-loop voltage
gain
AOL
dB
(V–) + 0.3 V < VO < (V+) –0.3 V,
RL = 10 kΩ
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6.4 Electrical Characteristics (continued)
at TA = 25°C, VS = 4.5 V to 16 V, VCM = VOUT = VS / 2, and RL = 10 kΩconnected to VS/2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FREQUENCY RESPONSE
GBW
Unity gain bandwidth
2.5
7.5
5.5
0.7
1
MHz
V/µs
Falling
Rising
SR
Slew rate
Gain = 1, 10-V step
To 0.01%, CL = 20 pF
To 0.001%, CL = 20 pF
Gain = 1, 2-V step
Gain = 1, 5-V step
ts
Settling time
µs
µs
Gain = 1, 2-V step
1.8
3.7
0.4
1
Gain = 1, 5-V step
From overload to negative rail
From overload to positive rail
Overload recovery
time
tOR
VIN × gain = VS
Total harmonic
distortion + noise
THD+N
Gain = 1, f = 1 kHz, VO = 3.5 VRMS
0.0012%
OUTPUT
No load
5
50
15
110
500
15
Positive rail
RL = 10 kΩ
RL = 2 kΩ
No load
200
5
Voltage output swing
from rail
VO
mV
50
110
500
Negative rail
VS = ±18 V
RL = 10 kΩ
RL = 2 kΩ
200
±65
ISC
CL
Short-circuit current
Capacitive load drive
mA
See Typical Characteristics
Open-loop output
impedance
ZO
f = 1 MHz, IO = 0 A
700
Ω
POWER SUPPLY
275
400
500
Quiescent current per
amplifier
IQ
IO = 0 A
µA
TA = –40°C to +125°C
TEMPERATURE
Thermal protection
180
30
°C
°C
Thermal hysteresis
INTERNAL GUARD BUFFER
±5
±8
±25
±75
Guard input offset
voltage
VOSG
µV
TA = –40°C to +125°C
TA = –40°C to +125°C
±0.1
±0.5
2.5
±0.8
Guard input offset
dVOSG/dT
µV/°C
voltage drift
VCM = (V+) –1.5 V
BW
Bandwidth
MHz
Guard output
impedance
IO = 0 A
1
kΩ
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7 Detailed Description
7.1 Overview
The OPA928 op amp is an ultra-low input bias current, high-precision, low-power, e-trim operational amplifier.
This op amp provides extremely low input bias current (< 20 fA) across the entire industrial temperature range of
−40ºC to 85ºC. In addition, the OPA928 operates from 4.5 V to 16 V, is unity-gain stable, and post-package
trimmed to achieve very low offset and offset drift performance.
The amplifier features state-of-the art CMOS technology and advanced design features to achieve extremely low
input bias current across a wide temperature range, wide input and output voltage ranges, high loop gain, and
low, flat output impedance. The OPA928 strengths include a wide bandwidth of 2.5 MHz, low noise spectral
density of 15 nV/√Hz, low 1/f noise of 1.4 μVPP, and low quiescent current of 400 μA. This combination of
features make the OPA928 an excellent choice for interfacing very high impedance sensors, and photodiodes.
7.2 Functional Block Diagram
V+
OPA928
–
NCH Input
Stage
IN+
+
GRD
1 k
High
Capacitive Load
Compensation
Output
Stage
Slew
Boost
OUT
e-trim™
GRD
IN–
+
PCH Input
Stage
–
V−
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7.3 Feature Description
7.3.1 Guard Buffer
The OPA928 uses input protection diodes to limit the input differential voltage range and protect the device
against transient currents. The back-to-back, or antiparallel, input protection diodes can be activated by fast
transient step responses and cause relatively large amounts of current to flow through the inputs. The inrush
current is routed through the antiparallel diodes and to the power supplies to avoid internal damage to the
OPA928.
To achieve a femtoampere-level input bias current, the OPA928 uses an internal, high-precision, rail-to-rail guard
buffer connected to the noninverting input. The guard buffer drives the voltage at the input of the OPA928 to the
guard pins (pins 2 and 7) and sets a 0-V differential voltage across the antiparallel diodes, greatly reducing
leakage current though the diodes. The guard buffer is isolated from large capacitive loads at the guard pins by a
nominal 1-kΩ resistor. Use the guard pins to guard external components and input traces from possible current
leakage paths. For more on guarding, see 节8.1.2.
7.3.2 Thermal Protection
The internal power dissipation of any amplifier causes the junction temperature (TJ) to rise. This phenomenon is
called self heating. To prevent damage from overheating, the OPA928 has a thermal protection feature.
This thermal protection works by monitoring the temperature of the output stage and turning off the op amp
output drive for temperatures above approximately 180°C. Thermal protection forces the output to a high-
impedance state. The OPA928 is also designed with approximately 30°C of thermal hysteresis. The OPA928
returns to normal operation when the output stage temperature reaches a safe operating temperature of
approximately 150°C.
CAUTION
The absolute maximum TJ of the OPA928 is 150°C. Exceeding the limits shown in the Absolute
Maximum Ratings can cause damage to the device. Thermal protection triggers at approximately
180°C and does not interfere with device operation up to the absolute maximum ratings. This
thermal protection is not designed to prevent this device from exceeding absolute maximum ratings,
but rather from excessive thermal overload.
7.3.3 Capacitive Load and Stability
The OPA928 features a patented output stage capable of driving large capacitive loads, and in a unity-gain
configuration, directly drives up to 1 nF of pure capacitive load. Increasing the gain enhances the ability of the
amplifier to drive greater capacitive loads; see 图 7-1. The particular op-amp circuit configuration, layout, gain,
and output loading are some of the factors to consider when establishing whether an amplifier will be stable in
operation.
G = +1 V/V
Time (2 ms/Div)
图7-1. Transient Response With a Purely Capacitive Load of 1 nF
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For additional drive capability in unity-gain configurations, improve capacitive load drive by inserting a small,
10‑Ω to 20‑Ω isolation resistor (RISO) in series with the output; 图 7-2 shows this resistor. This resistor
significantly reduces ringing while maintaining dc performance for purely capacitive loads. However, if there is a
resistive load in parallel with the capacitive load, a voltage divider is created, introducing a gain error at the
output and slightly reducing the output swing. The error introduced is proportional to the ratio RISO / RL, and is
generally negligible at low output levels. RISO modifies the open-loop gain of the system for increased phase
margin.
+Vs
Vout
Riso
+
Cload
+
Vin
-Vs
œ
图7-2. Extending Capacitive Load Drive With the OPA928
7.3.4 EMI Rejection
The OPA928 uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from
sources such as wireless communications and densely-populated boards with a mix of analog signal chain and
digital components. The OPA928 features improved design techniques to enhance EMI immunity.
7.3.5 Common-Mode Voltage Range
The OPA928 is a 16-V, true rail-to-rail input/output operational amplifier with an input common-mode range that
extends 100 mV beyond either supply rail. This wide range is achieved with paralleled complementary N-channel
and P-channel differential input pairs. The N-channel pair is active for input voltages close to the positive rail,
typically (V+) – 3 V to 100 mV above the positive supply. The P-channel pair is active for inputs from 100 mV
below the negative supply to approximately (V+) – 1.5 V. There is a small transition region, typically (V+) –3 V
to (V+) –1.5 V in which both input pairs are active. This transition region varies modestly with process variation.
Within this region PSRR, CMRR, offset voltage, offset drift, noise, and THD performance are degraded
compared to operation outside this region.
The OPA928 uses a precision trim for both the N-channel and P-channel regions enabling significantly lower
levels of offset than previous-generation devices. In inverting configurations, such as with a transimpedance
amplifier, the common-mode voltage is constant and set by the voltage at the noninverting pin. Therefore, in
inverting configurations, the transition region can be easily avoided and is typically not a problem. In noninverting
configurations, such as with a buffer, the common-mode voltage can vary widely; take care to avoid the transition
region when possible.
The OPA928 guard buffer features the same complementary input stage. The input bias performance of the
OPA928 is sensitive to small shifts in offset voltage. The shift in offset in the transition region is presented across
the internal protection diodes and causes increased leakage. The increase in leakage can be significant and
degrade the input bias performance of the OPA928. Avoid operating in the transistion region when possible to
achieve specified input bias current performance.
7.4 Device Functional Modes
The OPA928 has a single functional mode and is operational when the power-supply voltage is greater than
4.5 V (±2.25 V). The maximum power supply voltage for the OPA928 is 16 V (±8 V).
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The OPA928 offers femtoampere level input bias current, and excellent dc precision and ac performance. This
device provides 2.5‑MHz bandwidth and very low noise, 15 nV/√Hz and 0.05 fA/√Hz. The OPA928 can operate
with a 16‑V supply and offers true rail-to-rail input/output performance to allow for a wide linear output voltage
swing. The ultra-low input bias, low noise and wide output voltage swing capability make this device an excellent
choice for low-light photodiode applications.
8.1.1 Contamination Considerations
Applications requiring femtoampere-level performance are extremely sensitive to contamination. Contaminants
in the form of solder flux, salts, oils, organic acids, and more can form conductive paths over PCB traces and
allow small currents to leak into input traces or other sensitive nodes, severely degrading performance. Proper
handling and cleaning is required to achieve femtoampere level input bias performance in a PCB featuring the
OPA928.
The following list of best practices helps prevent a PCB from contamination:
• Always wear a pair of clean, powder-free gloves or finger cots when handling the PCB.
• Always hold the PCB by the edges when handling is required.
• Avoid touching the surface of the PCB and other component packages, especially near sensitive nodes or
input traces.
• Be cautious when breathing, speaking, and sneezing to prevent moisture or saliva from contacting the PCB.
• Do not allow direct airflow onto the board. Moving air can blow dust and moisture onto sensitive nodes.
Airflow also introduces moving charges that manifest as a small current at the input.
• When not in use, place the PCB in an ESD bag or other enclosure to prevent dust and other contaminants
from settling on the board.
• If configuring through-hole components in sensitive nodes, handle the components by the wire leads only.
A rigorous cleaning protocol is required after PCB assembly to remove all contaminants that can degrade input
bias performance of the OPA928. Repeat the cleaning procedure any time the board is soldered or modified
near sensitive nodes, or if contamination of these nodes is suspected.
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8.1.2 Guarding Considerations
图 8-1 details how to implement a guard in printed circuit board (PCB) layout. This section explores
considerations for driving the PCB guard with the OPA928 internal guard buffer, an external guard driver, or by
connecting the guard copper directly to the analog ground.
OPA928
Input
+
2.5 V
VOUT
Leakage
Path
CSTRAY
RLEAK
–
V = 0 V
RISO
Guard
2.5 V
Leakage
Path
CSTRAY
RLEAK
V = 2.5 V
GND
图8-1. Driving the Guard, Internal Guard Buffer
The guard presents a low-impedance path for leakage currents of equal potential to the high-impedance node
that is being guarded. For a noninverting configuration, the common-mode changes with the input signal and the
guard must be actively driven by a voltage follower that tracks the input signal. Choose a low-offset, low-noise
amplifier for the guard driver because any voltage potential between guard and input causes current to leak into
the high-impedance trace. The OPA928 features a high-performance internal guard buffer that can be accessed
at pin 2 and pin 7 to drive the PCB guard copper; see the Electrical Characteristics. The internal guard buffer
tracks the voltage of the OPA928 input signal and is isolated from capacitive loads through a 1-kΩ isolation
resistor, RISO
.
图 8-2 shows how the PCB guard is driven with an external guard driver instead of the OPA928 internal guard
buffer. To prevent the input bias current of the external guard driver from degrading the input signal, track the
low-impedance input of the OPA928. If an external guard driver is used, the OPA928 guard pins can be left
unconnected or can be overdriven by the external guard driver. Include an isolation resistor at the output of the
guard driver to prevent gain peaking due to capacitive loading and to provide short-circuit protection. Make sure
that the guard driver is stable and capable of driving the capacitive load presented by the guard, including long
cable lengths, if applicable.
Input
2.5 V
+
OPA928
–
VOUT
Leakage
Path
CSTRAY
RLEAK
V = 0 V
RISO
Guard
2.5 V
Leakage
Path
External
Guard Driver
V = 2.5 V
RLEAK
CSTRAY
GND
图8-2. Driving the Guard, External Guard Driver
For inverting configurations, the input common-mode voltage is fixed to the analog ground or some dc reference
voltage applied to the noninverting input. In this case, tie the PCB guard directly to the ground or low-impedance
reference of the signal amplifier. Tying the PCB guard makes sure that the guard potential is always equal to the
input common-mode voltage, without the additional offset and noise of an active guard driver. If the PCB guard is
connected to the analog ground of the circuit, make sure to ground return paths in the PCB. Keep power and
digital grounds separate from the guard and prevent ground loops from occurring. For inverting configurations,
the OPA928 internal guard buffer or an external guard driver can be used to drive the PCB guard, and the same
considerations apply as discussed for noninverting configurations.
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8.1.3 Humidity Considerations
The resistance of insulators is substantially affected by both temperature and humidity. Humidity can significantly
lower the effective resistance of insulators and cause an increase in leakage current around the affected
material. When water molecules settle on the surface of a given material, such as the plastic packaging and
PCB, a parallel and more electrically conductive path is created. Effective guarding techniques and appropriate
materials can help mitigate this behavior in the sensitive applications.
In some cases, water molecules can also penetrate the surface of a given material. The water molecules in the
material increase the conductivity of the body of the material and a reduction of resitance is established across
all adjacent nodes. Contrary to surface level leakge paths, leakage through the material cannot me mitigated
with guarding techniques. Use PCB materials with low humidity absorption properties to reduce moisture related
errors.
8.1.4 Dielectric Relaxation
All materials are prone to polarization in the presence of an electric field. The molecules of the given material
within the electric field become aligned at varying rates; a phenomena known as polarization. The rate depends
on the strength of the electric field and the susceptibility of the material. When the electric field is removed, the
molecules in the material return to the original alignment and random distribution, a phenomena known as
relaxation. The rate at which the molecules return to normal alignment depends on the permittivity and resistivity
of the material. In conductors, polarization and relaxation happens nearly instantaneously. In dielectrics, the time
delay for polarization and relaxation can be significant.
In most applications, dielectric relaxation is not a major design concern. However, for femtoampere leakage
current, dielectric relaxation becomes a major concern. The realignment of molecules causes a small
displacement current to appear across the material. The displacement current from the dielectric relaxation is
often greater than the input bias current level of the OPA928. The time required for the displacement current in
common FR-4 PCB materials to dissipate under the input bias current level of the OPA928 can take well over an
hour. To minimize the dielectric relaxation time and the leakage effects, use ceramic-based PCB materials such
as Rogers 4350B.
8.2 Typical Applications
8.2.1 High-Impedance (Hi-Z) Amplifier
The OPA928 behaves very close to an ideal op amp in regards to the input current. The near-zero input bias
current performance enables applications with extremely high impedance signal sources. For example, pH
probes can have an output impedance of up to 10 GΩ. Most op amps are inadequate to use with this kind of
sensor impedance. For example, a CMOS op amp with 1 pA of input bias current loads the sensor and causes a
large, and unacceptable, 10-mV error at the input. In 图8-3, the OPA928 is used to gain up the small signal from
the pH probe sensor. The large input impedance and ultra-low bias current into the positive input pin of the
OPA928 does not load the sensor and minimizes the input bias current error.
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1 k
13 k
VREF
15 V
–
OPA928
VOUT
Guard
+
GND
15 V
pH
Probe
Sensor
15 V
–
+
11.4 k
VREF
OPA206
1 nF
GND
10 k
GND
图8-3. High Impedance pH Probe Amplifier Circuit
8.2.1.1 Design Requirements
The primary objective is to design a single-supply, pH-probe gain amplifier.
• Supply voltage: 15 V
• pH-probe sensor impedance: 10 GΩ
• Temperature range: 25ºC to 85ºC
8.2.1.2 Detailed Design Procedure
In the 图 8-3 example, the pH-probe sensor is assumed to produce an output of ±59 mV/pH at room
temperature, or 25°C, and ±71 mV/pH at 85°C. The pH probe can be modeled as a small, variable battery in
series with a 10‑GΩ resistor. As a result of the intrinsic characteristics of the pH probe, a near 0‑V output is
produced for a neutral pH value of 7. A gain of 14 V/V provides a wide output swing of approximately ±7 V. To
enable single supply operation, a 7-V reference voltage (VREF) is created using the 15-V supply voltage and a
simple voltage divider. The output swing is shifted to 0 V to 14 V, and is conveniently proportional to the
approximately 1 V/pH at 85°C. Temperature calibration of the pH sensor (not shown) is necessary for accurate
results when wide temperature variation is expected.
8.2.1.3 Application Curve
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-500 -400 -300 -200 -100
0
100 200 300 400 500
pH Sensor Voltage (mV)
图8-4. Single Supply, pH-Probe Sensor Transfer Function
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8.2.2 Transimpedance Amplifier
图 8-5 shows the OPA928 configured as a transimpedance amplifier (TIA) for a low-light photodiode. TIAs are
needed to amplify the light-dependent current of the photodiode. In low-light conditions, photodiodes produce a
very small current and ultra-low input bias current and large gain in excess of 109 V/A is required. For a full
analysis of the TIA circuit, including theory, calculations, and measured data, see the Transimpedance Amplifiers
(TIA): Choosing the Best Amplifier for the Job application brief.
10 G
Guard
–
OPA928
VOUT
+
GND
GND
图8-5. OPA928 Simplified Photodiode Transimpedance Amplifier
8.2.2.1 Design Requirements
The design requirements for this design are:
• Transimpedance gain: 10,000,000,000 A/V
• Supply voltage rail: 5 V
• Photodiode shunt resistance: 5 GΩ
• Photodiode shunt capacitance: 35 pF
8.2.2.2 Detailed Design Procedure
Some photodiode applications operate in dark conditions and require low-light detection. In these cases, the
current output from the photodiode can be miniscule. To make the small diode current measurable, a
transimpedance amplifier (TIA) with a very large gain is required. The ideal transfer function of a resistive
transimpedance amplifier is given by 方程式1:
V
= I
× R
F
(1)
OUT
PD
The photodiode current (IPD) flows through the feedback resistor (RF) and forces an output voltage (VOUT) equal
to the voltage drop across RF. The ideal transfer function gives an intuitive understanding of TIA operation. In
practice, however, nonidealities must be taken into consideration to achieve desirable performance. 图 8-6
illustrates important nonidealities of the transimpedance amplifier circuit.
CSTRAY
CF
RF
GND
Guard
CIN
5 V
Photodiode
CCM
–
OPA928
VOUT
CDIF
RPD
CPD
+
0.2 V
GND
GND
图8-6. Transimpedance Photodiode Application
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One very important consideration, is the input bias current of the op amp. The input bias current directly adds to
IPD and creates an undesired error. The input bias current typically determines the minimum measurable IPD
within a given error tolerance. For example, a 1‑pA input bias current yields a 20% error when measuring a 5‑pA
photodiode current. A 1% error target requires a 50-fA input bias current maximum specification. The ultra-low
input bias current of the OPA928 enables accurate, extremely low IPD measurements. For information on how to
maintain the specified input bias performance, see 节8.4.
The input offset voltage (VOS) of the op amp is another significant source of error. The input offset voltage forces
a voltage across the effective shunt resistance of the diode (RD) and creates an error current (IRPD) equal to
VOS / RPD. In many cases, VOS can be a major source of error. For example, a VOS of 25 μV and an RPD of 1
GΩ creates an IRPD of 25 fA. Take into consideration offset voltage variation with temperature and common-
mode voltage.
In low-light applications, a very large RF is needed to provide the required gain, giving rise to potential stability
problems. RF interacts with the input capacitance (CIN) of the op amp, the photodiode capacitance (CPD), and
stray PCB capacitance to create a low-frequency zero in the noise gain transfer function (1/β). Remember that
CIN includes the differential (CDF) and common-mode (CCM) capacitance of the op amp. The value of CDF and
C
CM are found in the Electrical Characteristics. The zero in 1/β causes the gain to increase over frequency and
is the basis for instability problems. To counteract the zero, create a pole by adding a compensation capacitor
(CF) in the feedback loop. The optimal value selection of CF depends on several parameters and extensive
literature exists on this topic. One approach is to equate two expressions of noise gain. 方程式 2 makes the
assumption that the noise gain only depends on the capacitance of the circuit at a high enough frequency; a
reasonable approximation.
C
+ C
F
GBW
IN
=
(2)
2πR C
C
F F
F
Solving 方程式 2 for CF yields a quadratic equation with one real solution. The quadratic equation is given by 方
程式3:
1 ± 1 + 8πGBWR C
F I
C
=
(3)
F
4πGBWR
F
方程式 3 yields more than 45° of phase margin and some amount of gain peaking. Increasing the value of CF
yields a higher phase margin and limits the peaking response at the expense of signal bandwidth, given by 方程
式 4. For a flat frequency response, use a compensation capacitor calculator. For a very large RF, a very small
capacitor (< 0.5 pA) is required to maintain stability, and stray capacitance in the feedback loop can be sufficient.
1
f
=
(4)
−3dB
2πR C
F F
Another issue arises when using a very large RF. All resistors are sources of thermal noise. The magnitude of
noise density contribution from a resistor is directly correlated to the square root of the resistance value. In a
gain configuration, the feedback resistance and input resistance contribute to the total noise of the circuit. The
thermal noise resistance value in 图 8-6 is given by the parallel combination of RF and RPD. 方程式 5 shows the
input-referred-resistor noise-density equation. The low voltage noise of the OPA928 is not a significant
contributor of noise because RF and RPD are typically very large.
R
R
PD F
e
=
4kT
(5)
n_R
R
+ R
PD
F
In this application, a 5-V output is required from the 500-pA current input from a Si photodiode. A 10-GΩresistor
is used to achieve the required gain of 10,000,000,000 V/A. RPD and CPD of the photodiode is assumed to be 5
GΩ and 35 pF, respectively. Using the specifications of the OPA928 and the aforementioned photodiode
specifications, 方程式 3 calculates CF to be approximately 0.017 pF. The value obtained by calculation is
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impractical; therefore, the smallest standard capacitor available is used (1 pF). If settling time is a major concern,
consider making the required small-value capacitor using PCB traces.
8.3 Power-Supply Recommendations
The OPA928 is specified for operation from 4.5 V to 16 V (±2.25 V to ±8 V). The OPA928 features a high power-
supply rejection ratio (PSRR) and significantly reduces power supply errors at dc. However, a decreasing PSRR
at high frequencies means that high-frequency components in the power supply, such as noise, can be coupled
to the output. Use a linear, low-noise power supply to optimize noise performance. Place 0.1-μF bypass
capacitors close to the power-supply pins to further reduce errors coupling in from the power supplies. For more
detailed information on bypass capacitor placement, see 节 8.4. Switching power supplies generate switching
noise that can manifest at the output of the OPA928. When switching power supplies cannot be avoided, use
proper filtering and a low-dropout regulator to attenuate the switching noise and respective harmonics to an
acceptable level.
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8.4 Layout
8.4.1 Layout Guidelines
For best operational performance of the device, follow PCB layout best practices, including:
• Connect 0.1-µF ceramic bypass capacitors with low equivalent series resistance (ESR) between each supply
pin and ground. Place the capacitors as close to the device as possible. For single-supply applications, use a
single bypass capacitor from V+ to ground. Bypass capacitors are used to reduce coupled noise by providing
low-impedance power sources local to the analog circuitry.
• Physically separate digital and analog grounds, paying attention to the flow of the ground current. Separate
grounding for analog and digital circuitry is one of the simplest and most effective methods for noise
suppression. A ground plane helps distribute heat and reduces EMI noise pickup.
• Place external components as close to the device as possible.
• Keep the length of input traces as short as possible. Input traces are the most sensitive part of the circuit.
In addition to general PCB layout considerations, specific layout techniques must be implemented to achieve
femtoampere-level input bias current. Every insulator, including PCB material, has a finite resistance that can
become a path for current to leak into input traces and degrade input bias performance. To minimize leakage
current paths, implement a guard in the PCB layout. The guard presents a low-impedance path equipotential to
the input traces. Leakage current toward the high impedance input path can be diverted to the low-impedance
guard path. The guard is driven to a potential equal to the input common-mode voltage (see guarding
considerations). Current flowing between the input and guard traces is negligible because both traces are ideally
at the same potential.
Surround all high-impedance input traces with copper guard traces all the way from the source to the input pins
of the OPA928. For inverting configurations, extend the guard copper to the middle of the feedback components,
separating the low-impedance output from the high-impedance input node. Remove all solder mask and
silkscreen from the guard area to reduce surface-charge accumulation and prevent surface-level leakage paths
to the input.
Leakage currents can flow between layers vertically or diagonally through the PCB, as well as horizontally on the
surface layer. The guard must be implemented in a three-dimensional scheme to prevent leakage currents
originating in other layers from flowing into the signal path. Place the guard copper on the next layer directly
below the surface-level signal and guard traces to protect from vertical leakage paths. Surround the sensitive
input traces with a via fence connecting the guard copper on different layers to complete the three-dimensional
guard enclosure. 图8-9 shows the internal copper layers of a four-layer PCB using a three-dimensional guarding
scheme.
A copper ground pour around the OPA928 and guard area is recommended to reduce noise and EMI. In addition
to noise and EMI benefits, this ground pour presents another low-impedance path for leakage currents to take.
Keep voltage potentials other than guard and ground as far as possible from sensitive nodes. The OPA928 SOIC
pinout places the input and power supply pins at opposite ends of the amplifier package to reduce leakage
currents across the package and PCB material. If the power supplies (or other voltages) are present in vias or
through-holes near the OPA928, a ground-potential via fence can be applied locally to these through-holes to
provide a low-impedance path for leakage currents in the direction of sensitive nodes.
High-impedance, femtoampere-level circuits are highly sensitive to electromagnetic interference (EMI). Ground
planes and ground pours in the PCB layout can help reduce the effects of EMI. During operation, a
femtoampere-level PCB is commonly placed within a shielded enclosure tied to ground for further EMI rejection.
In layout, consider enclosing the OPA928 and all high-impedance traces within a local grounded RF shield. An
example of localized RF shielding for high-impedance nodes is available in the OPA928EVM user's guide.
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8.4.2 Layout Examples
Silk screen removed
from guard area
Low-impedance
output node
High-impedance
input node
Guard copper
(solder mask removed)
Ground plane vias
Silk screen
removed from
Ground plane vias
guard area
High-impedance
input node
Guard via fence
Guard via fence
Guard copper
(solder mask removed)
图8-7. Layout Example: Noninverting
图8-8. Layout Example: Inverting Configuration
Configuration
图8-9. Layout Example: Three-Dimensional Guard (4-Layer PCB)
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9 Device and Documentation Support
9.1 Device Support
9.1.1 Development Support
9.1.1.1 PSpice® for TI
PSpice® for TI 是可帮助评估模拟电路性能的设计和仿真环境。在进行布局和制造之前创建子系统设计和原型解决
方案，可降低开发成本并缩短上市时间。
9.1.1.2 TINA-TI™ 仿真软件（免费下载）
TINA-TI™ 仿真软件是一款简单易用、功能强大且基于 SPICE 引擎的电路仿真程序。TINA-TI 仿真软件是 TINA™
软件的一款免费全功能版本，除了一系列无源和有源模型外，此版本软件还预先载入了一个宏模型库。TINA-TI 仿
真软件提供所有传统的SPICE 直流、瞬态和频域分析，以及其他设计功能。
TINA-TI 仿真软件提供全面的后处理能力，便于用户以多种方式获得结果，用户可从设计工具和仿真网页免费下
载。虚拟仪器提供选择输入波形和探测电路节点、电压以及波形的能力，从而构建一个动态的快速启动工具。
备注
必须安装 TINA 软件或者 TINA-TI 软件后才能使用这些文件。请从 TINA-TI™ 软件文件夹中下载免费的
TINA-TI 仿真软件。
9.1.1.3 TI 参考设计
TI 参考设计是由TI 的精密模拟应用专家创建的模拟解决方案。TI 参考设计提供了许多实用电路的工作原理、组件
选择、仿真、完整印刷电路板 (PCB) 电路原理图和布局布线、物料清单以及性能测量结果。TI 参考设计可在线获
取，网址为https://www.ti.com/reference-designs。
9.2 Documentation Support
9.2.1 Related Documentation
• Texas Instruments, OPA928EVM User's Guide
9.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
9.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
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9.5 Trademarks
e-trim™, TINA-TI™, and TI E2E™ are trademarks of Texas Instruments.
TINA™ is a trademark of DesignSoft, Inc.
PSpice® is a registered trademark of Cadence Design Systems, Inc.
所有商标均为其各自所有者的财产。
9.6 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
9.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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24-Mar-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
POPA928DR
ACTIVE
SOIC
D
8
2500
TBD
Call TI
Call TI
-40 to 85
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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