OPT3005 [TI]
用于视频监控摄像头的环境光传感器 (ALS);
| 型号： | OPT3005 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 用于视频监控摄像头的环境光传感器 (ALS) 监控 传感器 |
| 文件： | 总40页 (文件大小：1689K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OPT3005
ZHCSQM3 –DECEMBER 2022
OPT3005 用于视频监控摄像头的环境光传感器(ALS)
850nm 和940nm 的红外光阻隔率超强（在入射角较大
时）。
1 特性
• 采用精密光学滤波以匹配人眼：
OPT3005 是一款用于测量人眼可见光强度的单芯片照
度计。该器件具有精密的光谱响应和超强的红外阻隔功
能，让 OPT3005 能够准确测量人眼可见光的强度，且
不受光源及 850nm 或 940nm 主动照明产生的任何杂
散光影响。对于为追求美观效果而需要将传感器安装在
深色玻璃下的工业设计（尤其是 850nm 或 940nm 主
动照明）而言，超强的红外阻隔功能还有助于保持高精
度。此类系统通常具有来自盖板玻璃的大量 NIR 杂散
反射，这会影响光传感器测量。OPT3005 的精密光学
滤波经过验证，可适应此类杂散 NIR 反射，并可真正
测量人眼感知的环境光。OPT3005 专门针对构建基于
光线的人眼般体验的系统而设计，是人眼匹配度低且红
外阻隔能力差的光电二极管、光敏电阻或其他环境光传
感器优选的替代产品。
– 抑制99.99+%（4 级以上）的近红外线(NIR) 光
（在入射角较大时）
• 内置自动满标度照度范围选择逻辑，可根据输入光
条件切换测量范围，范围之间具有良好的增益匹配
• 测量范围：20mlux 至167klux
• 23 位有效动态范围，具有
自动增益范围设置功能
• 12 种二进制加权满量程范围设置：
范围之间的匹配度小于0.2%（典型值）
• 低工作电流: 1.8µA（典型值）
• 工作温度范围：–40°C 至+85°C
• 宽电源范围：1.6V 至3.6V
• 可耐受5.5V 电压的I/O
• 灵活的中断系统
• 小巧的外形：
凭借内置的满量程设置功能，无需手动选择满量程范围
即可在 20mlux 至 166klux 范围内进行测量。该功能允
许在23 位有效动态范围内进行光测量。
– 2.1mm × 1.9mm × 0.6mm SOT-5X3 封装
2 应用
器件信息
封装(1)
• IP 网络摄像头
• 安防摄像机
• 可视门铃
封装尺寸（标称值）
器件型号
OPT3005
2.10 mm x 1.90 mm x 0.6
mm
SOT-5X3 (8)
• 需要光感应以及850nm 或940nm 有源NIR 照明的
应用
(1) 要了解所有可用封装，请参见数据表末尾的封装选项附录。
3 说明
OPT3005 是一款用于测量可见光密度的传感器。传感
器的光谱响应与人眼的视觉响应紧密匹配，并且对
1
OPT3005
Human Eye
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
300
400
500
600
700
800
900
1000
Cover Glass
OPT3005
Wavelength (nm)
光谱响应：OPT3005 和人眼
850nm/940nm
850nm/940nm
Accurate light
intensity (lux)
I2C
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOSAC5
OPT3005
ZHCSQM3 –DECEMBER 2022
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Table of Contents
8.4 Device Functional Modes..........................................13
8.5 Programming............................................................ 16
8.6 Register Maps...........................................................18
9 Application and Implementation..................................27
9.1 Application Information............................................. 27
9.2 Typical Application.................................................... 28
9.3 Do's and Don'ts.........................................................31
9.4 Power-Supply Recommendations.............................32
9.5 Layout....................................................................... 32
10 Device and Documentation Support..........................34
10.1 Documentation Support.......................................... 34
10.2 接收文档更新通知................................................... 34
10.3 支持资源..................................................................34
10.4 Trademarks.............................................................34
10.5 Electrostatic Discharge Caution..............................34
10.6 术语表..................................................................... 34
11 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 说明（续）.........................................................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings........................................ 4
7.2 ESD Ratings............................................................... 4
7.3 Recommended Operating Conditions.........................4
7.4 Thermal Information....................................................4
7.5 Electrical Characteristics.............................................5
7.6 Timing Requirements..................................................7
7.7 Typical Characteristics................................................8
8 Detailed Description......................................................10
8.1 Overview...................................................................10
8.2 Functional Block Diagram.........................................10
8.3 Feature Description...................................................11
Information.................................................................... 34
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
December 2022
*
Initial release
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5 说明（续）
数字操作可灵活用于系统集成。测量既可连续进行也可单次触发。控制和中断系统可自主操作，允许处理器进入
休眠状态，同时传感器会搜索适当的唤醒事件并通过中断引脚报告。数字输出通过兼容I2C 和SMBus 的双线制串
行接口进行报告。
OPT3005 器件具有低功耗和低电源电压性能，可以提高电池供电系统的电池寿命。
6 Pin Configuration and Functions
SDA
INT
NC
1
2
3
4
8
7
6
5
VDD
ADDR
NC
GND
SCL
图6-1. DTS Package, 8-Pin SOT-5X3, Top View
表6-1. Pin Functions
PIN
TYPE
DESCRIPTION
NO.
1
NAME
VDD
ADDR
NC
Power
Device power. Connect to a 1.6-V to 3.6-V supply.
2
Digital input
No Connection
Power
Address pin. This pin sets the LSBs of the I2C address.
3
No Connection
4
GND
SCL
NC
Ground
I2C clock. Connect with a 10-kΩresistor to a 1.6-V to 5.5-V supply.
5
Digital input
No Connection
Digital output
6
No Connection
7
INT
Interrupt output open-drain. Connect with a 10-kΩresistor to a 1.6-V to 5.5-V
supply.
I2C data. Connect with a 10-kΩresistor to a 1.6-V to 5.5-V supply.
8
SDA
Digital I/O
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.5
–0.5
MAX
6
UNIT
V
Voltage
VDD to GND
SDA, SCL, INT, and ADDR to GND
6
V
Current in to any pin
10
mA
°C
TJ
Junction temperature
Storage temperature
150
150(2)
Tstg
°C
–65
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Long exposure to temperatures higher than 105°C can cause package discoloration, spectral distortion, and measurement inaccuracy.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.6
NOM
MAX
3.6
UNIT
V
VDD
TJ
Operating power-supply voltage
Operating temperature
85
°C
–40
7.4 Thermal Information
OPT3005
THERMAL METRIC(1)
DTS (SOT)
8 Pins
112.2
28.4
UNIT
RθJA
RθJC(top)
RθJB
ΨJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
22.1
Junction-to-top characterization parameter
Junction-to-board characterization parameter
1.2
22
ΨJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
All specifications at TA = 25°C, VDD = 3.3 V, 800-ms conversion-time (CT=1)(1), automatic full-scale range (RN[3:0] = 1100b)
(1), white LED and normal-angle incidence of light, unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Optical
Peak irradiance spectral
responsivity
550
nm
lux
lux
Resolution (LSB)
Lowest full-scale range, RN[3:0]=0000b(1)
0.02
167731.
2
Full-scale illuminance
1.28 lux per ADC code, 2620.8 lux full-scale (RN[3:0] =
0101)(1) , 2000 lux input(2)
1250
1600
1563
2000
0.2
1875 codes
2400 lux(7)
%
Measurement Output result
Relative accuracy between gain
ranges (3)
Infrared response (850nm)(2)
From -85° to +85° angle of incidence
Input illuminance > 80 lux
0.004
%
%
%
2
5
Linearity
Input illuminance < 80 lux
Measurement drift across
temperature
Input illuminance = 2000 lux
0.02 lux per ADC Code
0.06
0
%/°C
ADC
3
Dark Condition ADC output
codes
degree
s
Half-power-angle
50% of full-power reading
VDD at 3.6 V and 1.6 V
57
PSRR Power-supply rejection ratio(4)
0.1
%/V(3)
POWER SUPPLY
VDD
VI2C
Operating Range
1.6
1.6
3.6
5.5
2.5
V
V
Operating range for I2C pull up
resistor
I2C pullup resistor, VDD ≤VI2C
Quiescent current
Active, Vdd=3.6V
1.8
0.3
µA
Shutdown
Dark
(M[1:0]=00)(1)
VDD=3.6V
,
0.47
µA
IQ
Active, Vdd=3.6V
3.7
0.4
0.8
Full-scale lux
Shutdown
(M[1:0]=00)(1)
POR
Power-on-reset threshold
V
DIGITAL
CIO
I/O Pin Capacitance
3
800
100
pF
ms
ms
Total Integration-time(5)
(CT = 1)(1) , 800-ms mode, fixed lux range
(CT = 0)(1) , 100-ms mode, fixed lux range
720
90
880
110
Low-level input voltage (SDA, SCL,
and ADDR)
0.3 X
VDD
VIL
VIH
IIL
0
V
V
High-level input voltage (SDA, SCL,
and ADDR)
0.7 X
VDD
5.5
Low-level input current (SDA, SCL,
and ADDR)
0.01 0.25(6)
0.32
µA
V
Low-level output voltage (SDA and
INT)
VOL
IZH
IOL=3mA
Output logic high, high-Z leakage
current (SDA, INT)
Measured with VDD at pin
0.01 0.25(6)
µA
TEMPERATURE
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7.5 Electrical Characteristics (continued)
All specifications at TA = 25°C, VDD = 3.3 V, 800-ms conversion-time (CT=1)(1), automatic full-scale range (RN[3:0] = 1100b)
(1), white LED and normal-angle incidence of light, unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
85 °C
Specified temperature range
–40
(1) Refers to a control field within the configuration register
(2) Tested with the white LED calibrated to 2k lux and an 850-nm LED
(3) Characterized by measuring fixed near-full-scale light levels on the higher adjacent full-scale range setting.
(4) PSRR is the percent change of the measured lux output from the current value, divided by the change in power supply voltage, as
characterized by results from 3.6-V and 1.6-V power supplies.
(5) The conversion-time, from start of conversion until the data are ready to be read, is the integration-time plus 3 ms.
(6) The specified leakage current is dominated by the production test equipment limitations. Typical values are much smaller
(7) equivalent lux measured with white LED @ around 4000K
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7.6 Timing Requirements
see note (1)
MIN
NOM
MAX UNIT
I2C FAST MODE
fSCL
SCL operating frequency
0.01
1300
600
600
600
20
0.4 MHz
tBUF
Bus free time between stop and start
Hold time after repeated start
Setup time for repeated start
Setup time for stop
ns
ns
ns
ns
tHDSTA
tSUSTA
tSUSTO
tHDDAT
tSUDAT
tLOW
Data hold time
900
ns
ns
ns
ns
ns
ns
Data setup time
100
1300
600
SCL clock low period
SCL clock high period
Clock rise and fall time
Data rise and fall time
tHIGH
tRC and tFC
tRD and tFD
300
300
Bus timeout period. If the SCL line is held low for this duration of time, the bus
state machine is reset.
tTIMEO
28
ms
I2C HIGH-SPEED MODE
fSCL
SCL operating frequency
0.01
160
160
160
160
20
2.6 MHz
tBUF
Bus free time between stop and start
Hold time after repeated start
Setup time for repeated start
Setup time for stop
ns
ns
ns
ns
tHDSTA
tSUSTA
tSUSTO
tHDDAT
tSUDAT
tLOW
Data hold time
140
ns
ns
ns
ns
ns
ns
Data setup time
20
SCL clock low period
SCL clock high period
Clock rise and fall time
Data rise and fall time
240
60
tHIGH
tRC and tFC
tRD and tFD
40
80
Bus timeout period. If the SCL line is held low for this duration of time, the bus
state machine is reset.
tTIMEO
28
ms
(1) All timing parameters are referenced to low and high voltage thresholds of 30% and 70%, respectively, of final settled value.
1/fSCL
tRC
tFC
70%
30%
SCL
SDA
tLOW
tHIGH
tSUSTA
tSUSTO
tHDSTA
tHDDAT
tSUDAT
70%
30%
tBUF
Start
tRD
tFD
Stop
Start
Stop
图7-1. I2C Detailed Timing Diagram
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7.7 Typical Characteristics
At TA = 25°C, VDD = 3.3 V, 800-ms conversion time (CT = 1), automatic full-scale range (RN[3:0] = 1100b), white LED, and
normal-angle incidence of light, unless otherwise specified.
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.2
0.18
0.16
0.14
0.12
0.1
OPT3005
Human Eye
0.08
0.06
0.04
0.02
0
-40
-20
0
20
40
60
80
100
300
400
500
600
700
800
900
1000
Temperature (°C)
Wavelength (nm)
图7-3. Dark Response vs Temperature
图7-2. Spectral Response vs Wavelength
1.1
1000
900
800
700
600
1.08
1.06
1.04
1.02
1
0.98
0.96
0.94
0.92
0.9
-40
-20
0
20
40
60
80
100
Temperature (°C)
1.6
2
2.4 2.8
Power Supply (V)
3.2
3.6
图7-4. Normalized Response vs Temperature
D017
图7-5. Conversion Time vs Power Supply
1.002
1.001
1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.999
0.998
1.6
2
2.4 2.8
Power Supply (V)
3.2
3.6
-90
-70
-50
-30
-10
10
30
50
70
90
D009
Illuminance Angle (è)
D010
图7-6. Normalized Response vs Power-Supply Voltage
spacer
图7-7. Normalized Response vs Illuminance Angle
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7.7 Typical Characteristics (continued)
At TA = 25°C, VDD = 3.3 V, 800-ms conversion time (CT = 1), automatic full-scale range (RN[3:0] = 1100b), white LED, and
normal-angle incidence of light, unless otherwise specified.
4
3.8
3.6
3.4
3.2
3
0.5
0.48
0.46
0.44
0.42
0.4
0.38
0.36
0.34
0.32
0.3
2.8
2.6
2.4
2.2
2
0.28
0.26
0.24
0.22
0.2
1.8
1.6
1.4
1.2
1
0
30000
60000
90000 120000 150000 180000
200
500 1000
500010000
100000 300000
Input Illuminance (Lux)
M[1:0] = 00b
M[1:0] = 10b
图7-9. Shutdown Current vs Input Illuminance
图7-8. Supply Current vs Input Illuminance
3.5
3
1.6
1.4
1.2
1
Vdd = 3.3V
Vdd = 1.6V
Vdd = 3.3V
Vdd = 1.6V
2.5
2
0.8
0.6
0.4
0.2
1.5
1
-40
-20
0
20
40
60
80
100
-40
-20
0
20
40
60
80
100
Temperature (èC)
Temperature (èC)
D013
D014
M[1:0] = 10b
M[1:0] = 00b, input illuminance = 0 lux
spacer
图7-10. Supply Current vs Temperature
图7-11. Shutdown Current vs Temperature
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8 Detailed Description
8.1 Overview
The OPT3005 measures the ambient light that illuminates the device. This device measures light with a spectral
response very closely matched to the human eye along with extreme 850 nm and 940 nm infrared rejection.
Matching the sensor spectral response to that of the human eye response is vital because ambient light sensors
are used to measure and help create human lighting experiences. Extreme rejection of infrared light, which a
human does not see, is a crucial component of this matching, especially when operation in intended underneath
windows that are visibly dark, but infrared transmissive. Systems with 850nm or 940nm active NIR illumination
especially benefit from the IR rejection to measure the ambient light resilient to the stray NIR light reflected by
the cover glass.
The OPT3005 is fully self-contained to measure the ambient light and report the result in lux digitally over the I2C
bus. The result can also be used to alert a system and interrupt a processor with the INT pin. The result can also
be summarized with a programmable window comparison and communicated with the INT pin.
The OPT3005 can be configured into an automatic full-scale, range-setting mode that always selects the best
full-scale range setting for the lighting conditions. This mode frees the user from having to program their software
for potential iterative cycles of measurement and readjustment of the full-scale range until optimal for any given
measurement. The device can be commanded to operate continuously or in single-shot measurement modes.
The device integrates the result over either 100 ms or 800 ms, so the effects of 50-Hz and 60-Hz noise sources
from typical light bulbs are nominally reduced to a minimum.
The device starts up in a low-power shutdown state, such that the OPT3005 only consumes active-operation
power after being programmed into an active state.
The OPT3005 optical filtering system is not excessively sensitive to non-designed for particles and micro-
shadows on the optical surface. This reduced sensitivity is a result of the relatively minor device dependency on
uniform-density optical illumination of the sensor area for infrared rejection. Proper optical surface cleanliness is
always recommended for best results on all optical devices.
8.2 Functional Block Diagram
VDD
VDD
OPT3005
SCL
SDA
INT
SCL
SDA
I2C
Interface
Ambient
Light
Digital Processor
ADC
INT or GPIO
Optical
Filter
ADDR
GND
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8.3 Feature Description
8.3.1 Human Eye Matching
The OPT3005 spectral response closely matches that of the human eye. If the ambient light sensor
measurement is used to help create a good human experience, or create optical conditions that are best for a
human, the sensor must measure the same spectrum of light that a human sees.
The device also has extreme infrared light (IR) rejection for 850nm and 940nm. This IR rejection is especially
important in application where there is active NIR illumination. If the sensor measures infrared light that the
human eye does not see, then a true human eye perceived light intensity is not accurately represented.
Furthermore, if the ambient light sensor is hidden underneath a dark window (such that the end-product user
cannot see the sensor) the infrared rejection of the OPT3005 becomes significantly more important because
many dark windows attenuate visible light but transmit infrared light. This attenuation of visible light and lack of
attenuation of IR light amplifies the ratio of the infrared light to visible light that illuminates the sensor. Results
can still be well matched to the human eye under this condition because of the high infrared rejection of the
OPT3005.
8.3.2 Automatic Full-Scale Range Setting
The OPT3005 has an automatic full-scale range setting feature that eliminates the need to predict and set the
best range for the device. In this mode, the OPT3005 automatically selects the best full-scale range for the given
lighting condition. The OPT3005 has a high degree of result matching between the full-scale range settings. This
matching eliminates the problem of varying results or the need for range-specific, user-calibrated gain factors
when different full-scale ranges are chosen. For further details, see the Automatic Full-Scale Setting Mode
section.
8.3.3 Interrupt Operation, INT Pin, and Interrupt Reporting Mechanisms
The device has an interrupt reporting system that allows the processor connected to the I2C bus to go to sleep,
or otherwise ignore the device results, until a user-defined event occurs that requires possible action.
Alternatively, this same mechanism can also be used with any system that can take advantage of a single digital
signal that indicates whether the light is above or below levels of interest.
The interrupt event conditions are controlled by the high-limit and low-limit registers, as well as the configuration
register latch and fault count fields. The results of comparing the result register with the high-limit register and
low-limit register are referred to as fault events. The fault count register dictates how many consecutive same-
result fault events are required to trigger an interrupt event and subsequently change the state of the interrupt
reporting mechanisms, which are the INT pin, the flag high field, and the flag low field. The latch field allows a
choice between a latched window-style comparison and a transparent hysteresis-style comparison.
The INT pin has an open-drain output, which requires the use of a pull-up resistor. This open-drain output allows
multiple devices with open-drain INT pins to be connected to the same line, thus creating a logical NOR or AND
function between the devices. The polarity of the INT pin can be controlled with the polarity of interrupt field in
the configuration register. When the POL field is set to 0, the pin operates in an active low behavior that pulls the
pin low when the INT pin becomes active. When the POL field is set to 1, the pin operates in an active high
behavior and becomes high impedance, thus allowing the pin to go high when the INT pin becomes active.
Additional details of the interrupt reporting registers are described in the Interrupt Reporting Mechanism Modes
and Internal Registers sections.
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8.3.4 I2C Bus Overview
The OPT3005 offers compatibility with both I2C and SMBus interfaces. The I2C and SMBus protocols are
essentially compatible with one another. The I2C interface is used throughout this document as the primary
example with the SMBus protocol specified only when a difference between the two protocols is discussed.
The OPT3005 is connected to the bus with two pins: an SCL clock input pin and an SDA open-drain bidirectional
data pin. The bus must be controlled by a host device that generates the serial clock (SCL), controls the bus
access, and generates start and stop conditions. To address a specific device, the host initiates a start condition
by pulling the data signal line (SDA) from a high logic level to a low logic level while SCL is high. All sensors on
the bus shift in the sensor address byte on the SCL rising edge, with the last bit indicating whether a read or
write operation is intended. During the ninth clock pulse, the sensor being addressed responds to the host by
generating an acknowledge bit by pulling SDA low.
Data transfer is then initiated and eight bits of data are sent, followed by an acknowledge bit. During data
transfer, SDA must remain stable while SCL is high. Any change in SDA while SCL is high is interpreted as a
start or stop condition. When all data are transferred, the host generates a stop condition, indicated by pulling
SDA from low to high while SCL is high. The OPT3005 includes a 28-ms timeout on the I2C interface to prevent
locking up the bus. If the SCL line is held low for this duration of time, the bus state machine is reset.
8.3.4.1 Serial Bus Address
To communicate with the OPT3005, the host must first initiate an I2C start command. Then, the host must
address sensor devices via a sensor address byte. The sensor address byte consists of seven address bits and
a direction bit that indicates whether the action is to be a read or write operation.
Four I2C addresses are possible by connecting the ADDR pin to one of four pins: GND, VDD, SDA, or SCL. 表
8-1 summarizes the possible addresses with the corresponding ADDR pin configuration. The state of the ADDR
pin is sampled on every bus communication and must be driven or connected to the desired level before any
activity on the interface occurs.
表8-1. Possible I2C Addresses with Corresponding ADDR Configuration
DEVICE I2C ADDRESS
ADDR PIN
1000100
GND
1000101
VDD
1000110
SDA
1000111
SCL
8.3.4.2 Serial Interface
The OPT3005 operates as a sensor device on both the I2C bus and SMBus. Connections to the bus are made
via the SCL clock input line and the SDA open-drain I/O line. The OPT3005 supports the transmission protocol
for standard mode (up to 100 kHz), fast mode (up to 400 kHz), and high-speed mode (up to 2.6 MHz). All data
bytes are transmitted most-significant bits first.
The SDA and SCL pins feature integrated spike-suppression filters and Schmitt triggers to minimize the effects
of input spikes and bus noise. See the Electrical Interface section for further details of the I2C bus noise
immunity.
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8.4 Device Functional Modes
8.4.1 Automatic Full-Scale Setting Mode
The OPT3005 has an automatic full-scale-range setting mode that eliminates the need for a user to predict and
set the best range for the device. This mode is entered when the configuration register range number field
(RN[3:0]) is set to 1100b.
The first measurement that the device takes in auto-range mode is a 10-ms range assessment measurement.
The device then determines the appropriate full-scale range to take the first full measurement.
For subsequent measurements, the full-scale range is set by the result of the previous measurement. If a
measurement is towards the low side of full-scale, the full-scale range is decreased by one or two settings for the
next measurement. If a measurement is towards the upper side of full-scale, the full-scale range is increased by
one setting for the next measurement.
If the measurement exceeds the full-scale range, resulting from a fast increasing optical transient event, the
current measurement is aborted. This invalid measurement is not reported. A 10-ms measurement is taken to
assess and properly reset the full-scale range. Then, a new measurement is taken with this proper full-scale
range. Therefore, during a fast increasing optical transient in this mode, a measurement can possibly take longer
to complete and report than indicated by the configuration register conversion time field (CT).
8.4.2 Interrupt Reporting Mechanism Modes
There are two major types of interrupt reporting mechanism modes: latched window-style comparison mode and
transparent hysteresis-style comparison mode. The configuration register latch field (L) (see the configuration
register, bit 4) controls which of these two modes is used. An end-of-conversion mode is also associated with
each major mode type. The end-of-conversion mode is active when the two most significant bits of the threshold
low register are set to 11b. The mechanisms report via the flag high and flag low fields, the conversion ready
field, and the INT pin.
8.4.2.1 Latched Window-Style Comparison Mode
The latched window-style comparison mode is typically selected when using the OPT3005 to interrupt an
external processor. In this mode, a fault is recognized when the input signal is above the high-limit register or
below the low-limit register. When the consecutive fault events trigger the interrupt reporting mechanisms, these
mechanisms are latched, thus reporting whether the fault is the result of a high or low comparison. These
mechanisms remain latched until the configuration register is read, which clears the INT pin and flag high and
flag low fields. The SMBus alert response protocol, described in detail in the SMBus Alert Response section,
clears the pin but does not clear the flag high and flag low fields. The behavior of this mode, along with the
conversion ready flag, is summarized in 表 8-2. Note that 表 8-2 does not apply when the two threshold low
register MSBs (see the Transparent Hysteresis-Style Comparison Mode section for clarification on the MSBs)
are set to 11b.
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表8-2. Latched Window-Style Comparison Mode: Flag Setting and Clearing Summary(2) (4)
FLAG HIGH
FIELD
FLAG LOW
FIELD
CONVERSION
READY FIELD
OPERATION
INT PIN(1)
The result register is above the high-limit register for fault count times.
See the Result Register and the High-Limit Register for further details.
1
X
1
Active
1
1
The result register is below the low-limit register for fault count times.
See the Result Register and the Low-Limit Register for further details.
X
Active
The conversion is complete with fault count criterion not met
Configuration register read(3)
X
0
X
0
X
Inactive
X
1
0
X
0
X
Configuration register write, M[1:0] = 00b (shutdown)
Configuration register write, M[1:0] > 00b (not shutdown)
SMBus alert response protocol
X
X
X
X
X
X
X
Inactive
(1) The INT pin depends on the setting of the polarity field (POL). The INT pin is low when the pin state is active and POL = 0 (active low)
or when the pin state is inactive and POL = 1 (active high).
(2) X = no change from the previous state.
(3) Immediately after the configuration register is read, the device automatically resets the conversion ready field to the 0 state. Thus, if
two configuration register reads are performed immediately after a conversion completion, the first reads 1 and the second reads 0.
(4) The high-limit register is assumed to be greater than the low-limit register. If this assumption is incorrect, the flag high field and flag low
field can take on different behaviors.
8.4.2.2 Transparent Hysteresis-Style Comparison Mode
The transparent hysteresis-style comparison mode is typically used when a single digital signal is desired that
indicates whether the input light is higher than or lower than a light level of interest. If the result register is higher
than the high-limit register for a consecutive number of events set by the fault count field, the INT line is set to
active, the flag high field is set to 1, and the flag low field is set to 0. If the result register is lower than the low-
limit register for a consecutive number of events set by the fault count field, the INT line is set to inactive, the flag
low field is set to 1, and the flag high field is set to 0. The INT pin and flag high and flag low fields do not change
state with configuration reads and writes. The INT pin and flag fields continually report the appropriate
comparison of the light to the low-limit and high-limit registers. The device does not respond to the SMBus alert
response protocol while in either of the two transparent comparison modes (configuration register, latch field =
0). The behavior of this mode, along with the conversion ready is summarized in 表 8-3. Note that 表 8-3 does
not apply when the two threshold low register MSBs (LE[3:2] from 表8-11) are set to 11.
表8-3. Transparent Hysteresis-Style Comparison Mode: Flag Setting and Clearing Summary(2) (4)
FLAG HIGH
FIELD
FLAG LOW
FIELD
CONVERSION
READY FIELD
OPERATION
INT PIN(1)
The result register is above the high-limit register for fault count times.
See the Result Register and the High-Limit Register for further details.
1
0
0
1
Active
1
1
The result register is below the low-limit register for fault count times.
See the Result Register and the Low-Limit Register for further details.
Inactive
The conversion is complete with fault count criterion not met
Configuration register read(3)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
0
X
0
X
Configuration register write, M[1:0] = 00b (shutdown)
Configuration register write, M[1:0] > 00b (not shutdown)
SMBus alert response protocol
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8.4.2.3 End-of-Conversion Mode
An end-of-conversion indicator mode can be used when every measurement is desired to be read by the
processor, prompted by the INT pin going active on every measurement completion. This mode is entered by
setting the most significant two bits of the low-limit register (LE[3:2] from the Low-Limit Register) to 11b. This
end-of-conversion mode is typically used in conjunction with the latched window-style comparison mode. The
INT pin becomes inactive when the configuration register is read or the configuration register is written with a
non-shutdown parameter or in response to an SMBus alert response. 表 8-4 summarizes the interrupt reporting
mechanisms as a result of various operations.
表8-4. End-of-Conversion Mode while in Latched Window-Style Comparison Mode:
Flag Setting and Clearing Summary(2)
FLAG HIGH
FIELD
FLAG LOW
FIELD
CONVERSION
READY FIELD
OPERATION
INT PIN(1)
Active
The result register is above the high-limit register for fault count times.
See the Result Register and the High-Limit Register for further details.
1
X
1
1
1
The result register is below the low-limit register for fault count times.
See the Result Register and the Low-Limit Register for further details.
X
Active
The conversion is complete with fault count criterion not met
Configuration register read(3)
X
0
X
0
Active
Inactive
X
1
0
X
0
X
Configuration register write, M[1:0] = 00b (shutdown)
Configuration register write, M[1:0] > 00b (not shutdown)
SMBus alert response protocol
X
X
X
X
X
X
X
Inactive
Note that when transitioning from end-of-conversion mode to the standard comparison modes (that is,
programming LE[3:2] from 11b to 00b) while the configuration register latch field (L) is 1, a subsequent write to
the configuration register latch field (L) to 0 is necessary to properly clear the INT pin. The latch field can then be
set back to 1 if desired.
8.4.2.4 End-of-Conversion and Transparent Hysteresis-Style Comparison Mode
The combination of end-of-conversion mode and transparent hysteresis-style comparison mode can also be
programmed simultaneously. The behavior of this combination is shown in 表8-5.
表8-5. End-Of-Conversion Mode while in Transparent Hysteresis-Style Comparison Mode:
Flag Setting and Clearing Summary(2)
FLAG HIGH
FIELD
FLAG LOW
FIELD
CONVERSION
READY FIELD
OPERATION
INT PIN(1)
Active
The result register is above the high-limit register for fault count times.
See the Result Register and the High-Limit Register for further details.
1
0
0
1
1
1
The result register is below the low-limit register for fault count times.
See the Result Register and the Low-Limit Register for further details.
Active
The conversion is complete with fault count criterion not met
Configuration register read(3)
X
X
X
X
X
X
X
X
X
X
Active
Inactive
X
1
0
X
0
X
Configuration register write, M[1:0] = 00b (shutdown)
Configuration register write, M[1:0] > 00b (not shutdown)
SMBus alert response protocol
Inactive
X
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8.5 Programming
The OPT3005 supports the transmission protocol for standard mode (up to 100 kHz), fast mode (up to 400 kHz),
and high-speed mode (up to 2.6 MHz). Fast and standard modes are described as the default protocol, referred
to as F/S. High-speed mode is described in the High-Speed I 2C Mode section.
8.5.1 Writing and Reading
Accessing a specific register on the OPT3005 is accomplished by writing the appropriate register address during
the I2C transaction sequence. Refer to 表 8-6 for a complete list of registers and their corresponding register
addresses. The value for the register address (as shown in 图 8-1) is the first byte transferred after the sensor
address byte with the R/W bit low.
1
9
1
9
SCL
RA
7
RA
6
RA
5
RA
4
RA
3
RA
2
RA
1
RA
0
SDA
1
0
0
0
1
A1
A0
R/W
Start by
Host
ACK by
OPT3005
ACK by
OPT3005
Stop by Host
(optional)
Frame 1: Two-Wire Sensor Address Byte (1)
Frame 2: Register Address Byte
A. The value of the sensor address byte is determined by the ADDR pin setting; see 表8-1.
图8-1. Setting the I2C Register Address
Writing to a register begins with the first byte transmitted by the host. This byte is the sensor address with the
R/W bit low. The OPT3005 then acknowledges receipt of a valid address. The next byte transmitted by the host
is the address of the register that data are to be written to. The next two bytes are written to the register
addressed by the register address. The OPT3005 acknowledges receipt of each data byte. The host can
terminate the data transfer by generating a start or stop condition.
When reading from the OPT3005, the last value stored in the register address by a write operation determines
which register is read during a read operation. To change the register address for a read operation, a new partial
I2C write transaction must be initiated. This partial write is accomplished by issuing a sensor address byte with
the R/W bit low, followed by the register address byte and a stop command. The host then generates a start
condition and sends the sensor address byte with the R/W bit high to initiate the read command. The next byte is
transmitted by the sensor and is the most significant byte of the register indicated by the register address. This
byte is followed by an acknowledge from the host; then the sensor transmits the least significant byte. The host
acknowledges receipt of the data byte. The host can terminate the data transfer by generating a not-
acknowledge after receiving any data byte, or by generating a start or stop condition. If repeated reads from the
same register are desired, continually sending the register address bytes is not necessary; the OPT3005 retains
the register address until that number is changed by the next write operation.
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图 8-2 and 图 8-3 show the write and read operation timing diagrams, respectively. Note that register bytes are
sent most significant byte first, followed by the least significant byte.
1
9
1
9
1
9
1
9
SCL
RA
7
RA
6
RA
5
RA
4
RA
3
RA
2
RA
1
RA
0
SDA
1
0
0
0
1
A1
A0
R/W
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Start by
Host
ACK by
OPT3005
ACK by
OPT3005
ACK by
OPT3005
Stop by
Host
ACK by
OPT3005
Frame 1 Two-Wire Sensor Address Byte (1)
Frame 2 Register Address Byte
Frame 3 Data MSByte
Frame 4 Data LSByte
A. The value of the sensor address byte is determined by the setting of the ADDR pin; see 表8-1.
图8-2. I2C Write Example
1
9
1
9
1
9
SCL
SDA
1
0
0
0
1
A1
A0 R/W
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Stop by
Sensor
Start by
Host
ACK by
OPT3005
From
OPT3005
ACK by
Host
From
OPT3005
No ACK
by Host(2)
Frame 1 Two-Wire Sensor Address Byte (1)
Frame 2 Data MSByte
Frame 3 Data LSByte
A. The value of the sensor address byte is determined by the ADDR pin setting; see 表8-1.
B. An ACK by the host can also be sent.
图8-3. I2C Read Example
8.5.1.1 High-Speed I2C Mode
When the bus is idle, both the SDA and SCL lines are pulled high by the pull-up resistors or active pull-up
devices. The host generates a start condition followed by a valid serial byte containing the high-speed (HS) host
code 0000 1XXXb. This transmission is made in either standard mode or fast mode (up to 400 kHz). The
OPT3005 does not acknowledge the HS host code but does recognize the code and switches the internal filters
to support a 2.6-MHz operation.
The host then generates a repeated start condition (a repeated start condition has the same timing as the start
condition). After this repeated start condition, the protocol is the same as F/S mode, except that transmission
speeds up to 2.6 MHz are allowed. Instead of using a stop condition, use repeated start conditions to secure the
bus in HS mode. A stop condition ends the HS mode and switches all internal filters of the OPT3005 to support
the F/S mode.
8.5.1.2 General-Call Reset Command
The I2C general-call reset allows the host controller in one command to reset all devices on the bus that respond
to the general-call reset command. The general call is initiated by writing to the I2C address 0 (0000 0000b). The
reset command is initiated when the subsequent second address byte is 06h (0000 0110b). With this transaction,
the device issues an acknowledge bit and sets all of the registers to the power-on-reset default condition.
8.5.1.3 SMBus Alert Response
The SMBus alert response provides a quick identification for which device issued the interrupt. Without this alert
response capability, the processor does not know which device pulled the interrupt line when there are multiple
sensor devices connected.
The OPT3005 is designed to respond to the SMBus alert response address, when in the latched window-style
comparison mode (configuration register, latch field = 1). The OPT3005 does not respond to the SMBus alert
response when in transparent mode (configuration register, latch field = 0).
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The response behavior of the OPT3005 to the SMBus alert response is shown in 图 8-4. When the interrupt line
to the processor is pulled to active, the host can broadcast the alert response sensor address (0001 1001b).
Following this alert response, any sensor devices that generated an alert identify themselves by acknowledging
the alert response and sending their respective I2C address on the bus. The alert response can activate several
different sensor devices simultaneously. If more than one sensor attempts to respond, bus arbitration rules apply.
The device with the lowest address wins the arbitration. If the OPT3005 loses the arbitration, then the device
does not acknowledge the I2C transaction and the INT pin remains in an active state, prompting the I2C host
processor to issue a subsequent SMBus alert response. When the OPT3005 wins the arbitration, the device
acknowledges the transaction and sets the INT pin to inactive. The host can issue that same command again, as
many times as necessary to clear the INT pin. See the Interrupt Reporting Mechanism Modes section for
additional details of how the flags and INT pin are controlled. The host can obtain information about the source
of the OPT3005 interrupt from the address broadcast in the above process. The flag high field (configuration
register, bit 6) is sent as the final LSB of the address to provide the host additional information about the cause
of the OPT3005 interrupt. If the host requires additional information, the result register or the configuration
register can be queried. The flag high and flag low fields are not cleared upon an SMBus alert response.
INT
1
9
1
9
SCL
SDA
0
0
0
1
1
0
0
R/W
1
0
0
0
1
A1
A0 FH(1)
Start By
Host
ACK By
Device
From
Device
NACK By Stop By
Host Host
Frame 1 SMBus ALERT Response Address Byte
Frame 2 Sensor Address Byte(2)
A. FH is the flag high field (FH) in the configuration register (see 表8-10).
B. A1 and A0 are determined by the ADDR pin; see 表8-1.
图8-4. Timing Diagram for SMBus Alert Response
8.6 Register Maps
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8.6.1 Internal Registers
The device is operated over the I2C bus with registers that contain configuration, status, and result information. All registers are 16 bits long.
There are four main registers: result, configuration, low-limit, and high-limit. There are also two ID registers: manufacturer ID and device ID. 表 8-6 lists
these registers.
表8-6. Register Map
ADDRESS
REGISTER
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
(Hex)(1)
Result
Configuration
Low Limit
00h
E3
RN3
LE3
E2
RN2
LE2
E1
RN1
LE1
E0
RN0
LE0
R11
CT
R10
M1
R9
M0
R8
OVF
TL8
TH8
ID8
R7
CRF
TL7
TH7
ID7
R6
FH
R5
FL
R4
L
R3
POL
TL3
TH3
ID3
R2
ME
R1
FC1
TL1
TH1
ID1
R0
FC0
TL0
TH0
ID0
01h
02h
TL11
TH11
ID11
DID11
TL10
TH10
ID10
DID10
TL9
TH9
ID9
TL6
TH6
ID6
TL5
TH5
ID5
TL4
TH4
ID4
DID4
TL2
TH2
ID2
High Limit
03h
HE3
ID15
DID15
HE2
ID14
DID14
HE1
ID13
DID13
HE0
ID12
DID12
Manufacturer ID
Device ID
7Eh
7Fh
DID9
DID8
DID7
DID6
DID5
DID3
DID2
DID1
DID0
(1) Register offset and register address are used interchangeably.
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8.6.1.1 Register Descriptions
备注
Register offset and register address are used interchangeably.
8.6.1.1.1 Result Register (offset = 00h)
This register contains the result of the most recent light to digital conversion. This 16-bit register has two fields: a
4-bit exponent and a 12-bit mantissa.
图8-5. Result Register (Read-Only)
15
E3
R
14
E2
R
13
E1
R
12
E0
R
11
R11
R
10
R10
R
9
R9
R
8
R8
R
7
R7
R
6
R6
R
5
R5
R
4
R4
R
3
R3
R
2
R2
R
1
R1
R
0
R0
R
LEGEND: R = Read only
表8-7. Result Register Field Descriptions
Bit
Field
Type
Reset
Description
Exponent.
15:12
E[3:0]
R
0h
These bits are the exponent bits. 表8-8 provides further details.
Fractional result.
These bits are the result in straight binary coding (zero to full-scale).
11:0
R[11:0]
R
000h
表8-8. Full-Scale Range and LSB Size as a Function of Exponent Level
E3
0
0
0
0
0
0
0
0
1
1
1
1
E2
0
0
0
0
1
1
1
1
0
0
0
0
E1
0
0
1
1
0
0
1
1
0
0
1
1
E0
0
1
0
1
0
1
0
1
0
1
0
1
FULL-SCALE RANGE (lux)
LSB SIZE (lux per LSB)
81.90
0.02
0.04
0.08
0.16
0.32
0.64
1.28
2.56
5.12
10.24
20.48
40.96
163.80
327.60
655.20
1310.40
2620.80
5241.60
10483.20
20966.40
41932.80
83865.60
167731.2
The formula to translate this register into lux is given in 方程式1:
lux = LSB_Size × R[11:0]
where:
(1)
LSB_Size = 0.02 × 2E[3:0]
(2)
(3)
LSB_Size can also be taken from 表8-8. The complete lux equation is shown in 方程式3:
lux = 0.02 × (2E[3:0]) × R[11:0]
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A series of result register output examples with the corresponding LSB weight and resulting lux are given in 表
8-9. Note that many combinations of exponents (E[3:0]) and fractional results (R[11:0]) can map onto the same
lux result, as shown in the examples of 表8-9.
表8-9. Examples of Decoding the Result Register into lux
RESULT REGISTER
(Bits 15:0, Binary)
EXPONENT
(E[3:0], Hex)
FRACTIONAL RESULT
(R[11:0], Hex)
LSB WEIGHT
(lux, Decimal)
RESULTING LUX
(Decimal)
0000 0000 0000 0001b
0000 1111 1111 1111b
0011 0100 0101 0110b
0111 1000 1001 1010b
1000 1000 0000 0000b
1001 0100 0000 0000b
1010 0010 0000 0000b
1011 0001 0000 0000b
1011 0000 0000 0001b
1011 1111 1111 1111b
00h
00h
03h
07h
08h
09h
0Ah
0Bh
0Bh
0Bh
001h
FFFh
456h
89Ah
800h
400h
200h
100h
001h
FFFh
0.02
0.02
0.02
81.9
0.16
177.60
2.56
5637.12
10485.76
10485.76
10485.76
10485.76
40.96
5.12
10..24
20.48
40.96
40.96
40.96
167731.2
Note that the exponent field can be disabled (set to zero) by enabling the exponent mask (configuration register,
ME field = 1) and manually programming the full-scale range (configuration register, RN[3:0] < 1100b (0Ch)),
allowing for simpler operation in a manually-programmed, full-scale mode. Calculating lux from the result register
contents only requires multiplying the result register by the LSB weight (in lux) associated with the specific
programmed full-scale range (see 表8-8). See the Low-Limit Register for details.
See the configuration register conversion time field (CT, bit 11) description for more information on lux resolution
as a function of conversion time.
8.6.1.1.2 Configuration Register (offset = 01h) [reset = C810h]
This register controls the major operational modes of the device. This register has 11 fields, which are
documented below. If a measurement conversion is in progress when the configuration register is written, the
active measurement conversion immediately aborts. If the new configuration register directs a new conversion,
that conversion is subsequently started.
图8-6. Configuration Register
15
14
13
12
11
10
M1
9
8
OVF
R
RN3
R/W
RN2
R/W
RN1
R/W
RN0
R/W
CT
M0
R/W
R/W
R/W
7
CRF
R
6
FH
R
5
FL
R
4
L
3
2
1
0
POL
R/W
ME
R/W
FC1
R/W
FC0
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only
表8-10. Configuration Register Field Descriptions
Bit
Field
Type
Reset
Description
Range number field (read or write).
The range number field selects the full-scale lux range of the device. The format of this field is
the same as the result register exponent field (E[3:0]); see 表8-8. When RN[3:0] is set to 1100b
(0Ch), the device operates in automatic full-scale setting mode, as described in the Automatic
Full-Scale Setting Mode section. In this mode, the automatically chosen range is reported in the
result exponent (register 00h, E[3:0]).
15:12 RN[3:0] R/W
1100b
The device powers up as 1100 in automatic full-scale setting mode. Codes 1101b, 1110b, and
1111b (0Dh, 0Eh, and 0Fh) are reserved for future use.
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表8-10. Configuration Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
Conversion time field (read or write).
The conversion time field determines the length of the light to digital conversion process. The
choices are 100 ms and 800 ms. A longer integration time allows for a lower noise
measurement.
The conversion time also relates to the effective resolution of the data conversion process. The
800-ms conversion time allows for the fully specified lux resolution. The 100-ms conversion time
with full-scale ranges above 0101b for E[3:0] in the result and configuration registers also allows
for the fully specified lux resolution. The 100-ms conversion time with full-scale ranges below
and including 0101b for E[3:0] can reduce the effective result resolution by up to three bits, as a
function of the selected full-scale range. Range 0101b reduces by one bit. Ranges 0100b,
0011b, 0010b, and 0001b reduces by two bits. Range 0000b reduces by three bits. The result
register format and associated LSB weight does not change as a function of the conversion
time.
11
CT
R/W
1b
0 = 100 ms
1 = 800 ms
Mode of conversion operation field (read or write).
The mode of conversion operation field controls whether the device is operating in continuous
conversion, single-shot, or low-power shutdown mode. The default is 00b (shutdown mode),
such that upon power-up, the device only consumes operational level power after appropriately
programming the device.
When single-shot mode is selected by writing 01b to this field, the field continues to read 01b
while the device is actively converting. When the single-shot conversion is complete, the mode
of conversion operation field is automatically set to 00b and the device is shut down.
When the device enters shutdown mode, either by completing a single-shot conversion or by a
manual write to the configuration register, there is no change to the state of the reporting flags
(conversion ready, flag high, flag low) or the INT pin. These signals are retained for subsequent
read operations while the device is in shutdown mode.
10:9
M[1:0]
R/W
00b
00 = Shutdown (default)
01 = Single-shot
10, 11 = Continuous conversions
Overflow flag field (read-only).
The overflow flag field indicates when an overflow condition occurs in the data conversion
process, typically because the light illuminating the device exceeds the programmed full-scale
range of the device. Under this condition OVF is set to 1, otherwise OVF remains at 0. The field
is reevaluated on every measurement.
If the full-scale range is manually set (RN[3:0] field < 1100b), the overflow flag field can be set
while the result register reports a value less than full-scale. This result occurs if the input light
has a temporary high spike level that temporarily overloads the integrating ADC converter
circuitry but returns to a level within range before the conversion is complete. Thus, the overflow
flag reports a possible error in the conversion process. This behavior is common to integrating-
style converters.
8
OVF
R
0b
If the full-scale range is automatically set (RN[3:0] field = 1100b), the only condition that sets the
overflow flag field is if the input light is beyond the full-scale level of the entire device. When
there is an overflow condition and the full-scale range is not at maximum, the OPT3005 aborts
the current conversion, sets the full-scale range to a higher level, and starts a new conversion.
The flag is set at the end of the process. This process repeats until there is either no overflow
condition or until the full-scale range is set to the maximum range.
Conversion ready field (read-only).
The conversion ready field indicates when a conversion completes. The field is set to 1 at the
end of a conversion and is cleared (set to 0) when the configuration register is subsequently
read or written with any value except one containing the shutdown mode (mode of operation
field, M[1:0] = 00b). Writing a shutdown mode does not affect the state of this field; see the
Interrupt Reporting Mechanism Modes section for more details.
7
6
CRF
FH
R
R
0b
0b
Flag high field (read-only).
The flag high field (FH) identifies that the result of a conversion is larger than a specified level of
interest. FH is set to 1 when the result is larger than the level in the high-limit register (register
address 03h) for a consecutive number of measurements defined by the fault count field
(FC[1:0]). See the Interrupt Reporting Mechanism Modes section for more details on clearing
and other behaviors of this field.
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表8-10. Configuration Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
Flag low field (read-only).
The flag low field (FL) identifies that the result of a conversion is smaller than a specified level of
interest. FL is set to 1 when the result is smaller than the level in the low-limit register (register
address 02h) for a consecutive number of measurements defined by the fault count field
(FC[1:0]). See the Interrupt Reporting Mechanism Modes section for more details on clearing
and other behaviors of this field.
5
FL
R
0b
Latch field (read or write).
The latch field controls the functionality of the interrupt reporting mechanisms: the INT pin, the
flag high field (FH), and flag low field (FL). This bit selects the reporting style between a latched
window-style comparison and a transparent hysteresis-style comparison.
0 = The device functions in transparent hysteresis-style comparison operation, where the three
interrupt reporting mechanisms directly reflect the comparison of the result register with the
high- and low-limit registers with no user-controlled clearing event. See the Interrupt Operation,
INT Pin, and Interrupt Reporting Mechanisms section for further details.
4
L
R/W
1b
1 = The device functions in latched window-style comparison operation, latching the interrupt
reporting mechanisms until a user-controlled clearing event.
Polarity field (read or write).
The polarity field controls the polarity or active state of the INT pin.
0 = The INT pin reports active low, pulling the pin low upon an interrupt event.
1 = Operation of the INT pin is inverted, where the INT pin reports active high, becoming high
impedance and allowing the INT pin to be pulled high upon an interrupt event.
3
2
POL
ME
R/W
R/W
0b
0b
Mask exponent field (read or write).
The mask exponent field forces the result register exponent field (register 00h, bits E[3:0]) to
0000b when the full-scale range is manually set, which can simplify the processing of the result
register when the full-scale range is manually programmed. This behavior occurs when the
mask exponent field is set to 1 and the range number field (RN[3:0]) is set to less than 1100b.
Note that the masking is only performed to the result register. When using the interrupt reporting
mechanisms, the result comparison with the low-limit and high-limit registers is unaffected by
the ME field.
Fault count field (read or write).
The fault count field instructs the device as to how many consecutive fault events are required to
trigger the interrupt reporting mechanisms: the INT pin, the flag high field (FH), and flag low field
(FL). The fault events are described in the latch field (L), flag high field (FH), and flag low field
1:0
FC[1:0]
R/W
00b
(FL) descriptions.
00 = One fault count (default)
01 = Two fault counts
10 = Four fault counts
11 = Eight fault counts
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8.6.1.1.3 Low-Limit Register (offset = 02h) [reset = C0000h]
This register sets the lower comparison limit for the interrupt reporting mechanisms: the INT pin, the flag high
field (FH), and flag low field (FL), as described in the Interrupt Reporting Mechanism Modes section.
图8-7. Low-Limit Register
15
14
13
12
11
10
9
8
LE3
R/W
LE2
R/W
LE1
R/W
LE0
R/W
TL11
R/W
TL10
R/W
TL9
R/W
TL8
R/W
7
6
5
4
3
2
1
0
TL7
R/W
TL6
R/W
TL5
R/W
TL4
R/W
TL3
R/W
TL2
R/W
TL1
R/W
TL0
R/W
LEGEND: R/W = Read/Write
表8-11. Low-Limit Register Field Descriptions
Bit
Field
Type
Reset
Description
Exponent.
15:12
LE[3:0]
R/W
0h
These bits are the exponent bits. 表8-12 provides further details.
Result.
11:0
TL[11:0]
R/W
000h
These bits are the result in straight binary coding (zero to full-scale).
The format of this register is nearly identical to the format of the result register described in the Result Register.
The low-limit register exponent (LE[3:0]) is similar to the result register exponent (E[3:0]). The low-limit register
result (TL[11:0]) is similar to result register result (R[11:0]).
The equation to translate this register into the lux threshold is given in 方程式 4, which is similar to the equation
for the result register, 方程式3.
lux = 0.01 × (2LE[3:0]) × TL[11:0]
(4)
表 8-12 gives the full-scale range and LSB size as it applies to the low-limit register. The detailed discussion and
examples given in for the Result Register apply to the low-limit register as well.
表8-12. Full-Scale Range and LSB Size as a Function of Exponent Level
LE3
0
LE2
LE1
LE0
FULL-SCALE RANGE (lux)
LSB SIZE (lux per LSB)
0
0
0
81.90
0.02
0.04
0.08
0.16
0.32
0.64
1.28
2.56
5.12
10.24
20.48
40.96
0
0
0
1
163.80
0
0
1
0
327.60
0
0
1
1
655.20
0
1
0
0
1310.40
0
1
0
1
2620.80
0
1
1
0
5241.60
0
1
1
1
10483.20
20966.40
41932.80
83865.60
167731.2
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
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备注
The result and limit registers are all converted into lux values internally for comparison. These
registers can have different exponent fields. However, when using a manually-set full-scale range
(configuration register, RN < 0Ch, with mask enable (ME) active), programming the manually-set full-
scale range into the LE[3:0] and HE[3:0] fields can simplify the choice of programming the register.
This simplification results in the user only having to think about the fractional result and not the
exponent part of the result.
8.6.1.1.4 High-Limit Register (offset = 03h) [reset = BFFFh]
The high-limit register sets the upper comparison limit for the interrupt reporting mechanisms: the INT pin, the
flag high field (FH), and flag low field (FL), as described in the Interrupt Operation, INT Pin, and Interrupt
Reporting Mechanisms section. The format of this register is almost identical to the format of the low-limit
register (described in the Low-Limit Register) and the result register (described in the Result Register). To
explain the similarity in more detail, the high-limit register exponent (HE[3:0]) is similar to the low-limit register
exponent (LE[3:0]) and the result register exponent (E[3:0]). The high-limit register result (TH[11:0]) is similar to
the low-limit result (TH[11:0]) and the result register result (R[11:0]). Note that the comparison of the high-limit
register with the result register is unaffected by the ME bit.
When using a manually-set, full-scale range with the mask enable (ME) active, programming the manually-set,
full-scale range into the HE[3:0] bits can simplify the choice of values required to program into this register. The
formula to translate this register into lux is similar to 方程式4. The full-scale values are similar to 表8-8.
图8-8. High-Limit Register
15
14
13
12
11
10
9
8
HE3
R/W
HE2
R/W
HE1
R/W
HE0
R/W
TH11
R/W
TH10
R/W
TH9
R/W
TH8
R/W
7
6
5
4
3
2
1
0
TH7
R/W
TH6
R/W
TH5
R/W
TH4
R/W
TH3
R/W
TH2
R/W
TH1
R/W
TH0
R/W
LEGEND: R/W = Read/Write
表8-13. High-Limit Register Field Descriptions
Bit
Field
Type
Reset
Description
Exponent.
These bits are the exponent bits.
15:12
HE[3:0]
R/W
Bh
Result.
11:0
TH[11:0]
R/W
FFFh
These bits are the result in straight binary coding (zero to full-scale).
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8.6.1.1.5 Manufacturer ID Register (offset = 7Eh) [reset = 5449h]
This register is intended to help uniquely identify the device.
图8-9. Manufacturer ID Register
15
ID15
R
14
ID14
R
13
ID13
R
12
ID12
R
11
ID11
R
10
ID10
R
9
ID9
R
8
ID8
R
7
ID7
R
6
ID6
R
5
ID5
R
4
ID4
R
3
ID3
R
2
ID2
R
1
ID1
R
0
ID0
R
LEGEND: R = Read only
表8-14. Manufacturer ID Register Field Descriptions
Bit
Field
Type
Reset
Description
Manufacturer ID.
15:0
ID[15:0]
R
5449h
The manufacturer ID reads 5449h. In ASCII code, this register reads TI.
8.6.1.1.6 Device ID Register (offset = 7Fh) [reset = 3001h]
This register is also intended to help uniquely identify the device.
图8-10. Device ID Register
15
DID15
R
14
DID14
R
13
DID13
R
12
DID12
R
11
DID11
R
10
DID10
R
9
DID9
R
8
DID8
R
7
DID7
R
6
DID6
R
5
DID5
R
4
DID4
R
3
DID3
R
2
DID2
R
1
DID1
R
0
DID0
R
LEGEND: R = Read only
表8-15. Device ID Register Field Descriptions
Bit
Field
Type
Reset
Description
Device ID.
The device ID reads 3001h.
15:0
DID[15:0]
R
3001h
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
Ambient light sensors are used in a wide variety of applications that require control as a function of ambient light.
Because ambient light sensors nominally match the human eye spectral response, the sensors are better than
photodiodes when the goal is to create an experience for human beings. Very common applications include
display optical-intensity control and industrial or home lighting control.
There are two categories of interface to the OPT3005: electrical and optical.
9.1.1 Electrical Interface
The electrical interface is quite simple, as illustrated in 图 9-1. Connect the OPT3005 I2C SDA and SCL pins to
the same pins of an applications processor, microcontroller, or other digital processor. If that digital processor
requires an interrupt resulting from an event of interest from the OPT3005, then connect the INT pin to either an
interrupt or general-purpose I/O pin of the processor. There are multiple uses for this interrupt, including
signaling the system to wake up from low-power mode, processing other tasks while waiting for an ambient light
event of interest, or alerting the processor that a sample is ready to be read. Connect pullup resistors between a
power supply appropriate for digital communication and the SDA and SCL pins (because the pins have open-
drain output structures). If the INT pin is used, connect a pullup resistor to the INT pin. A typical value for these
pullup resistors is 10 kΩ. The resistor choice can be optimized in conjunction to the bus capacitance to balance
the system speed, power, noise immunity, and other requirements.
The power supply and grounding considerations are discussed in the Power-Supply Requirements section.
Although spike suppression is integrated in the SDA and SCL pin circuits, use proper layout practices to
minimize the amount of coupling into the communication lines. One possible introduction of noise occurs from
capacitively coupling signal edges between the two communication lines themselves. Another possible noise
introduction comes from other switching noise sources present in the system, especially for long communication
lines. In noisy environments, shield communication lines to reduce the possibility of unintended noise coupling
into the digital I/O lines that can be incorrectly interpreted.
9.1.2 Optical Interface
The optical interface is physically located within the package, facing away from the PCB, as specified by the
Sensor Area in 图9-2.
Physical components, such as a plastic housing and a window that allows light from outside of the design to
illuminate the sensor (see 图9-2), can help protect the OPT3005 and neighboring circuitry. Sometimes, a dark or
opaque window is used to further enhance the visual appeal of the design by hiding the sensor from view. This
window material is typically transparent plastic or glass.
Any physical component that affects the light that illuminates the sensing area of a light sensor also affects the
performance of that light sensor. Therefore, for the best performance, make sure to understand and control the
effect of these components. Design a window width and height to permit light from a sufficient field of view to
illuminate the sensor. For best performance, use a field of view of at least ±35 or more. Understanding and
designing the field of view is discussed further in OPT3001: Ambient Light Sensor Application Guide.
The visible-spectrum transmission for dark windows typically ranges between 5% to 30%, but can be less than
1%. Specify a visible-spectrum transmission as low as, but no more than, necessary to achieve sufficient visual
appeal because decreased transmission decreases the available light for the sensor to measure. The windows
are made dark by either applying an ink to a transparent window material, or including a dye or other optical
substance within the window material itself. This attenuating transmission in the visible spectrum of the window
creates a ratio between the light on the outside of the design and the light that is measured by the OPT3005. To
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accurately measure the light outside of the design, compensate the OPT3005 measurement for this ratio; an
example is given in Dark Window Selection and Compensation.
Ambient light sensors are used to help create lighting experiences for humans; therefore, the matching of the
sensor spectral response to that of the human eye response is vital. Infrared light is not visible to the human eye
and can interfere with the measurement of visible light when sensors lack infrared rejection. Therefore, the ratio
of visible light to interfering infrared light affects the accuracy of any practical system that represents the human
eye. The strong rejection of infrared light by the OPT3005 allows measurements consistent with human
perception under high-infrared lighting conditions, such as from incandescent, halogen, or sunlight sources.
Although the inks and dyes of dark windows serve their primary purpose of being minimally transmissive to
visible light, some inks and dyes can also be very transmissive to infrared light. The use of these inks and dyes
further decreases the ratio of visible to infrared light, and thus decreases sensor measurement accuracy.
However, because of the excellent infrared rejection of the OPT3005, this effect is minimized, and good results
are achieved under a dark window with similar spectral responses to those shown in 图9-3.
For best accuracy, avoid grill-like window structures, unless the designer understands the optical effects
sufficiently. These grill-like window structures create a nonuniform illumination pattern at the sensor that make
light measurement results vary with placement tolerances and angle of incidence of the light. If a grill-like
structure is desired, the OPT3005 is an excellent sensor choice because the device is minimally sensitive to
illumination uniformity issues disrupting the measurement process.
Light pipes can appear attractive for aiding in the optomechanical design that brings light to the sensor; however,
do not use light pipes with any ambient light sensor unless the system designer fully understands the
ramifications of the optical physics of light pipes within the full context of his design and objectives.
9.2 Typical Application
Measuring the ambient light with the OPT3005 in a product case and under a dark window is described in this
section. The schematic for this design is shown in 图9-1.
VDD
VDD
OPT3005
SCL
SDA
INT
SCL
SDA
I2C
Interface
Ambient
Light
Digital Processor
ADC
INT or GPIO
Optical
Filter
ADDR
GND
图9-1. Measuring Ambient Light in a Product Case Behind a Dark Window
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9.2.1 Design Requirements
The basic requirements of this design are:
• Sensor is hidden under dark glass so that sensor is not obviously visible. Note that this requirement is
subjective to designer preference.
• Accuracy of measurement of fluorescent light is 15%
• Variation in measurement between fluorescent, halogen, and incandescent bulbs (also known as light source
variation) is as small as possible.
9.2.2 Detailed Design Procedure
9.2.2.1 Optomechanical Design
After completing the electrical design, the next task is the optomechanical design. Design a product case that
includes a window to transmit the light from outside the product to the sensor, as shown in 图 9-2. Design the
window width and window height to give a ±45° field of view. A rigorous design of the field of view takes into
account the location of the sensor area, as shown in 图 9-2. The OPT3005 active sensor area is centered along
one axis of the package top view, but has a minor offset on the other axis of the top view. Window sizing and
placement is discussed in more rigorous detail in OPT3001: Ambient Light Sensor Application Guide.
Window Width
Window
Product Case
Field of View
Window Height
OPT3005
Side View
Active Sensor Area
PCB
图9-2. Product Case and Window Over the OPT3005
9.2.2.2 Dark Window Selection and Compensation
There are several approaches to selecting and compensating for a dark window. One of many approaches is the
method described here.
Sample several different windows with various levels of darkness. Choose a window that is dark enough to
optimize the balance between the aesthetics of the device and sensor performance. Note that the aesthetic
evaluation is the subjective opinion of the designer; therefore, to see the window on the physical design rather
than refer to window transmission specifications on paper is important. Make sure that the chosen window is not
darker than absolutely necessary because a darker window allows less light to illuminate the sensor and
therefore impedes sensor accuracy.
The window chosen for this application example is dark and has less than 7% transmission at 550 nm. 图 9-3
shows the normalized response of the spectrum. Note that the equipment used to measure the transmission
spectrum is not capable of measuring the absolute accuracy (non-normalized) of the dark window sample, but
only the relative normalized spectrum. Also note that the window is much more transmissive to infrared
wavelengths longer than 700 nm than to visible wavelengths between 400 nm and 650 nm. This imbalance
between infrared and visible light decreases the ratio of visible light to infrared light at the sensor. TI
recommends to have the window decrease this ratio as little as possible (by having a window with a close ratio
of visible transmission to infrared transmission)
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1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
300
400
500
600 700
Wavelength (nm)
800
900
1000
D018
图9-3. Normalized Transmission Spectral Response of the Chosen Dark Window
After choosing the dark window, measure the attenuating effect of the dark window for later compensation. To
measure this attenuation, measure a fluorescent light source with a lux meter, then measure that same light with
the OPT3005 under the dark window. To measure accurately, using a fixture that can accommodate either the
lux meter or the design containing the OPT3005 and dark window is important, with the center of each of the
sensing areas being in exactly the same X, Y, Z location, as shown in 图 9-4. The Z placement of the design
(distance from the light source) is the top of the window, and not the OPT3005 itself.
Light Source
Light Source
OPT3005
and
Window
Lux
Meter
图9-4. Fixture with One Light Source Accommodating Either a Lux Meter or the Design (Window and
OPT3005) in the Exact Same X,Y,Z Position
The fluorescent light in this location measures 1000 lux with the lux meter, and 73 lux with the OPT3005 under
the dark window within the application. Therefore, the window has an effective transmission of 7.3% for the
fluorescent light. This 7.3% is the weighted average attenuation across the entire spectrum, weighted by the
spectral response of the lux meter (or photopic response).
For all subsequent OPT3005 measurements under this dark window, the following formula is applied.
Compensated Measurement = Uncompensated Measurement / (7.3%)
(5)
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9.2.3 Application Curves
To validate that the design example now measures correctly, create a sequential number of different light
intensities with the fluorescent light by using neutral density filters to attenuate the light. Different light intensities
can also be created by changing the distance between the light source, and the measurement devices.
However, these two methods for changing the light level have minor accuracy tradeoffs that are beyond the
scope of this discussion. Measure each intensity with both the lux meter and the OPT3005 under the window,
and compensate using 方程式 5. The results are displayed in 图 9-5, and show that the application accurately
reports results very similar to the lux meter.
To validate that the design measures a variety of light sources correctly, despite the large ratio of infrared
transmission to visible light transmission of the window, measure the application with a halogen bulb and an
incandescent bulb. Use the physical location and light attenuation procedures that were used for the fluorescent
light.
The addition of the dark window changes the results as seen in 图9-5.
Results can vary at different angles of light because the OPT3005 does not match the lux meter at all angles of
light.
If the measurement variation between the light sources is not acceptable, choose a different window that has a
closer ratio of visible light transmission to infrared light transmission.
1000
Compensated
Uncompensated
900
800
700
600
500
400
300
200
100
0
0
100 200 300 400 500 600 700 800 900 1000
Lux Meter (Lux)
图9-5. Uncompensated and Compensated Output of the OPT3005 Under a Dark Window Illuminated by
Fluorescent Light Source
9.3 Do's and Don'ts
As with any optical product, special care must be taken into consideration when handling the OPT3005.
Although the OPT3005 has low sensitivity to dust and scratches, proper optical device handling procedures are
still recommended.
The optical surface of the device must be kept clean for the best performance in both prototyping with the device
and mass production manufacturing procedures. Tweezers with plastic or rubber contact surfaces are
recommended to avoid scratches on the optical surface. Avoid manipulation with metal tools when possible. The
optical surface must be kept clean of fingerprints, dust, and other optical-inhibiting contaminants.
If the device optical surface requires cleaning, the use of de-ionized water or isopropyl alcohol is recommended.
A few gentle brushes with a soft swab are appropriate. Avoid potentially abrasive cleaning and manipulating
tools and excessive force that can scratch the optical surface.
If the OPT3005 performs less than expected, then inspect the optical surface for dirt, scratches, or other optical
artifacts.
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9.4 Power-Supply Recommendations
Although the OPT3005 has low sensitivity to power-supply issues, good practices are always recommended. For
best performance, the OPT3005 VDD pin must have a stable, low-noise power supply with a 100-nF bypass
capacitor close to the device and solid grounding. There are many options for powering the OPT3005 because
the device current consumption levels are very low.
9.5 Layout
9.5.1 Layout Guidelines
The PCB layout design for the OPT3005 requires a couple of considerations. Bypass the power supply with a
capacitor placed close to the OPT3005. Note that optically reflective surfaces of components also affect the
performance of the design. The three-dimensional geometry of all components and structures around the sensor
must be taken into consideration to prevent unexpected results from secondary optical reflections. Placing
capacitors and components at a distance of at least twice the height of the component is usually sufficient. The
best optical layout is to place all close components on the opposite side of the PCB from the OPT3005.
However, this approach is not practical for the constraints of every design.
Electrically connecting the thermal pad to ground is recommended. This connection can be created either with a
PCB trace or with vias to ground directly on the thermal pad itself. If the thermal pad contains vias, then the vias
are recommended to be of a small diameter (< 0.2 mm) to prevent them from wicking the solder away from the
appropriate surfaces.
An example PCB layout with the OPT3005 is shown in 图9-6.
9.5.2 Layout Example
OPT3005
To VDD Power Supply
To Processor
Bypass Capacitor
图9-6. Example PCB Layout with the OPT3005 SOT-5X3 (8) Package
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9.5.3 Soldering and Handling Recommendations
Soldering temperature profile and guidelines are published in future revisions of this document.
As with most optical devices, handle the OPT3005 with special care to ensure optical surfaces stay clean and
free from damage. See the Do's and Don'ts section for more detailed recommendations. For best optical
performance, solder flux and any other possible debris must be cleaned after soldering processes.
9.5.4 Mechanical Drawings
1
8
A
A
0.3811
Section A
图9-7. Package Orientation Visual Reference of Pin 1 (Top View) & Sectional View
Identifying Package Orientation Using Automated Optical Inspection (AOI) Systems
Automated optical inspection (AOI) systems are used in the PCB assembly process to identify the device
orientation during device placement. Typically, on non-optical packages, the pin 1 marker is a white dot or
indentation on the black package. This is used by the AOI system to orient the package. Light sensor ICs such
as OPT3005 utilize a transparent package to allow light to enter the package and reach the sensor. This section
provides instruction for determining orientation on the package. The following figures show how the package can
be oriented from the bottom and top side. On the bottom side the package has a pin 1 identifier. On the top side
there are four features that can be used to orient the device. 1) the pin 1 identifier can be seen through the
package. 2) and 3) the bond wires and bond pads on the die can also be used. The asymmetry in either wires or
pads (4 at the top and 2 at the bottom) can be used to orient the device. 4) the rectangular feature on the die
indicates orientation.
图9-8. Identifying Package Orientation - Backside
图9-9. Identifying Package Orientation - Topside
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10 Device and Documentation Support
10.1 Documentation Support
10.1.1 Related Documentation
For related documentation see the following:
• OPT3005EVM User's Guide
• OPT3001: Ambient Light Sensor Application Guide
10.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
10.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
10.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
10.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPT3005DTSR
OPT3005DTST
ACTIVE
ACTIVE
SOT-5X3
SOT-5X3
DTS
DTS
8
8
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
3005
3005
Samples
Samples
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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30-Dec-2022
Addendum-Page 2
PACKAGE OUTLINE
FCSOT - 0.6 mm max height
FLIPCHIP SOT
DTS0008A
1.3
1.1
B
A
PIN 1
INDEX AREA
1
8
7
6X (0.5)
2
3
2.2
2.0
6
5
4
0.27
8X
0.17
0.1
C A B
C
2.0
1.8
0.05
SEATING PLANE
0.18
0.08
C
0.6 MAX
0.45
8X
0.05
0.00
0.25
4
5
6
7
8
3
2
1
0.05 C
4226132/B 07/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not incude mold flash, protrusions or gate burrs.
Mold flash, interlead flash, protrusions or gate burrs shall not exceed 0.15 per end or side
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EXAMPLE BOARD LAYOUT
FCSOT - 0.6 mm max height
FLIPCHIP SOT
DTS0008A
(1.72)
8X (0.72)
8X (0.3)
1
8
7
6
2
3
SYMM
6X (0.5)
5
4
SYMM
(R0.05) TYP
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 30X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4226132/B 07/2021
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
FCSOT - 0.6 mm max height
FLIPCHIP SOT
DTS0008A
(1.72)
8X (0.72)
1
8
7
8X (0.3)
2
3
SYMM
6
5
6X (0.5)
4
SYMM
(R0.05) TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 30X
4226132/B 07/2021
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
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