PCA9515AD [TI]
DUAL BIDIRECTIONAL I2C BUS AND SMBus REPEATER; 双路双向I2C总线和SMBus中继器
| 型号： | PCA9515AD |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DUAL BIDIRECTIONAL I2C BUS AND SMBus REPEATER |
| 文件： | 总13页 (文件大小：275K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PCA9515A
DUAL BIDIRECTIONAL I2C BUS AND SMBus REPEATER
www.ti.com
SCPS150A–DECEMBER 2005–REVISED JUNE 2006
FEATURES
•
•
•
•
•
Two-Channel Bidirectional Buffers
I2C Bus and SMBus Compatible
Active-High Repeater-Enable Input
Open-Drain I2C I/O
5.5-V Tolerant I2C I/O and Enable Input
Support Mixed-Mode Signal Operation
•
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
D, DCT, DGK, OR PW PACKAGE
(TOP VIEW)
•
•
Lockup-Free Operation
V
1
2
3
4
8
7
6
5
Accommodates Standard Mode and Fast
Mode I2C Devices and Multiple Masters
NC
SCL0
SDA0
GND
CC
SCL1
SDA1
EN
•
Supports Arbitration and Clock Stretching
Across the Repeater
•
•
Powered-Off High-Impedance I2C Pins
NC – No internal connection
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
DESCRIPTION/ORDERING INFORMATION
This dual bidirectional I2C buffer is operational at 2.3-V to 3.6-V VCC
.
The PCA9515A is a BiCMOS integrated circuit intended for I2C bus and SMBus systems applications. The
device contains two identical bidirectional open-drain buffer circuits that enable I2C and similar bus systems to
be extended without degradation of system performance. Both buffers specifically are designed to support the
standard low-level-contention arbitration of the I2C bus and support clock stretching.
The PCA9515A buffers both the serial data (SDA) and serial clock (SCL) signals on the I2C bus, while retaining
all the operating modes and features of the I2C system. This enables two buses of 400-pF bus capacitance to be
connected in an I2C application.
The I2C bus capacitance limit of 400 pF restricts the number of devices and bus length. Using the PCA9515A
enables the system designer to isolate two halves of a bus, accommodating more I2C devices or longer trace
lengths.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
PCA9515AD
TOP-SIDE MARKING(2)
Tube of 75
SOIC – D
Reel of 2500
Reel of 250
Reel of 3000
Reel of 250
Tube of 150
Reel of 2000
Reel of 250
Reel of 2500
PCA9515ADR
PD515A
PCA9515ADT
PCA9515ADCTR
PCA9515ADCTT
PCA9515APW
SSOP – DCT
PREVIEW
–40°C to 85°C
TSSOP – PW
VSSOP – DGK
PCA9515APWR
PCA9515APWT
PCA9515ADGKR
PD515A
7B_
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DGK: The actual top-side marking has one additional character that designates the assembly/test site.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2005–2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
PCA9515A
DUAL BIDIRECTIONAL I2C BUS AND SMBus REPEATER
www.ti.com
SCPS150A–DECEMBER 2005–REVISED JUNE 2006
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
The PCA9515A has an active-high enable (EN) input with an internal pullup, which allows the user to select
when the repeater is active. This can be used to isolate a badly behaved slave on power-up reset. It never
should change state during an I2C operation, because disabling during a bus operation hangs the bus, and
enabling part way through a bus cycle could confuse the I2C parts being enabled. The EN input should change
state only when the global bus and the repeater port are in an idle state, to prevent system failures.
The PCA9515A also can be used to run two buses: one at 5-V interface levels and the other at 3.3-V interface
levels, or one at 400-kHz operating frequency and the other at 100-kHz operating frequency. If the two buses
are operating at different frequencies, the 100-kHz bus must be isolated when the 400-kHz operation of the
other bus is required. If the master is running at 400 kHz, the maximum system operating frequency may be less
than 400 kHz, because of the delays that are added by the repeater.
The output low levels for each internal buffer are approximately 0.5 V, but the input voltage of each internal
buffer must be 70 mV or more below the output low level, when the output internally is driven low. This prevents
a lockup condition from occurring when the input low condition is released.
Two or more PCA9515A devices cannot be used in series. The PCA9515A design does not allow this
configuration. Because there is no direction pin, slightly different valid low-voltage levels are used to avoid
lockup conditions between the input and the output of each repeater. A valid low applied at the input of a
PCA9515A is propagated as a buffered low with a slightly higher value on the enabled outputs. When this
buffered low is applied to another PCA9515A-type device in series, the second device does not recognize it as a
valid low and does not propagate it as a buffered low again.
The device contains a power-up control circuit that sets an internal latch to prevent the output circuits from
becoming active until VCC is at a valid level (VCC = 2.3 V).
As with the standard I2C system, pullup resistors are required to provide the logic high levels on the buffered
bus. The PCA9515A has standard open-collector configuration of the I2C bus. The size of these pullup resistors
depends on the system, but each side of the repeater must have a pullup resistor. The device is designed to
work with Standard Mode and Fast Mode I2C devices in addition to SMBus devices. Standard Mode I2C devices
only specify 3 mA in a generic I2C system where Standard Mode devices and multiple masters are possible.
Under certain conditions, high termination currents can be used.
TERMINAL FUNCTIONS
NO.
1
NAME
DESCRIPTION
No internal connection
NC
2
SCL0 Serial clock bus 0
SDA0 Serial data bus 0
GND Supply ground
3
4
5
EN
Active-high repeater enable input
6
SDA1 Serial data bus 1
SCL1 Serial clock bus 1
7
8
VCC
Supply power
FUNCTION TABLE
INPUT
EN
FUNCTION
L
Outputs disabled
SDA0 = SDA1,
SCL0 = SCL1
H
2
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PCA9515A
DUAL BIDIRECTIONAL I2C BUS AND SMBus REPEATER
www.ti.com
SCPS150A–DECEMBER 2005–REVISED JUNE 2006
LOGIC DIAGRAM (POSITIVE LOGIC)
V
CC
8
PCA9515A
3
6
SDA0
SDA1
2
7
SCL0
SCL1
Pullup
Resistor
5
EN
4
3
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PCA9515A
DUAL BIDIRECTIONAL I2C BUS AND SMBus REPEATER
www.ti.com
SCPS150A–DECEMBER 2005–REVISED JUNE 2006
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX
UNIT
VCC
VI
Supply voltage range
7
V
Enable input voltage range(2)
I2C bus voltage range(2)
Input clamp current
7
7
V
VI/O
IIK
V
VI < 0
–50
–50
±50
±100
97
mA
mA
mA
mA
IOK
IO
Output clamp current
VO < 0
Continuous output current
Continuous current through VCC or GND
D package
DCT package
DGK package
PW package
220
172
149
150
θJA
Package thermal impedance(3)
°C/W
°C
Tstg
Storage temperature range
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions
MIN
2.3
MAX
UNIT
VCC
VIH
Supply voltage
3.6
V
SDA and SCL inputs
EN input
0.7 × VCC
2
5.5
High-level input voltage
V
5.5
SDA and SCL inputs
EN input
–0.5
0.3 × VCC
(1)
VIL
VILc
IOL
TA
Low-level input voltage
V
V
–0.5
0.8
0.4
6
(1)
SDA and SCL low-level input voltage contention
Low-level output current
–0.5
VCC = 2.3 V
VCC = 3 V
mA
°C
6
Operating free-air temperature
–40
85
(1) VIL specification is for the EN input and the first low level seen by the SDAx and SCLx lines. VILc is for the second and subsequent low
levels seen by the SDAx and SCLx lines. VILc must be at least 70 mV below VOL
.
4
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PCA9515A
DUAL BIDIRECTIONAL I2C BUS AND SMBus REPEATER
www.ti.com
SCPS150A–DECEMBER 2005–REVISED JUNE 2006
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
II = –18 mA
VCC
MIN TYP(1)
MAX UNIT
VIK
Input diode clamp voltage
2.3 V to 3.6 V
–1.2
V
SDAx,
SCLx
VOL
Low-level output voltage
IOL = 20 µA or 6 mA
II = 10 µA
2.3 V to 3.6 V
2.3 V to 3.6 V
0.47
0.52
0.6
V
Low-level input voltage below SDAx,
VOL – VILc
70
mV
mA
low-level output voltage
Quiescent supply current
SCLx
2.7 V
3.6 V
2.7 V
0.5
0.5
1
3
3
4
Both channels high,
SDAx = SCLx = VCC
Both channels low,
SDA0 = SCL0 = GND and
SDA1 = SCL1 = open; or
SDA0 = SCL0 = open and
SDA1 = SCL1 = GND
ICC
3.6 V
1
4
2.7 V
3.6 V
1
1
4
4
In contention,
SDAx = SCLx = GND
VI = 3.6 V
VI = 0.2 V
VI = VCC
±1
3
SDAx,
SCLx
II
Input current
2.3 V to 3.6 V
µA
±1
–20
0.5
0.5
EN
VI = 0.2 V
VI = 3.6 V
–10
SDAx,
SCLx
Ioff
Leakage current
EN = L or H
0 V
µA
µA
VI = GND
Leakage current during
power up
SDAx,
SCLx
II(ramp)
VI = 3.6 V
EN = L or H
0 V to 2.3 V
3.3 V
1
9
9
EN
7
7
Cin
Input capacitance
VI = 3 V or GND
pF
SDAx,
SCLx
EN = H
3.3 V
(1) All typical values are at nominal supply voltage (VCC = 2.5 V or 3.3 V) and TA = 25°C.
Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 2.5 V
VCC = 3.3 V
± 0.2 V
± 0.3 V
UNIT
MIN
100
130
MAX
MIN
100
100
MAX
tsu
th
Setup time, EN↑ before Start condition
Hold time, EN↓ after Stop condition
ns
ns
Switching Characteristics
over recommended operating free-air temperature range, CL ≤ 100 pF (unless otherwise noted)
VCC = 2.5 V ± 0.2 V
MIN TYP(1)
MAX
VCC = 3.3 V ± 0.3 V
MIN TYP(1)
MAX
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
tPZL
tPLZ
ttHL
ttLH
45
33
82
113
57
130
190
45
33
68
102
58
120
180
SDA0, SCL0 or SDA1, SCL1 or
Propagation delay time(2)
ns
ns
SDA1, SCL1
SDA0, SCL0
Output transition time(2)
(SDAx, SCLx)
80%
20%
20%
80%
148
147
(1) All typical values are at nominal supply voltage (VCC = 2.5 V or 3.3 V) and TA = 25°C.
(2) Different load resistance and capacitance alter the RC time constant, thereby changing the propagation delay and transition times.
5
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PCA9515A
DUAL BIDIRECTIONAL I2C BUS AND SMBus REPEATER
www.ti.com
SCPS150A–DECEMBER 2005–REVISED JUNE 2006
PARAMETER MEASUREMENT INFORMATION
V
CC
V
CC
V
IN
V
OUT
S1
R
L
= 1.35 kΩ
PULSE
DUT
GND
GENERATOR
R
T
C = 50 pF
L
(see Note A)
(see Note B)
TEST
S1
t /t
PLZ PZL
V
CC
TEST CIRCUIT FOR OPEN-DRAIN OUTPUT
Input
V
CC
1.5 V
1.5 V
0 V
t
t
PLZ
PZL
Output
V
V
CC
80%
80%
1.5 V
20%
1.5 V
20%
OL
t
t
tLH
tHL
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
A. RT termination resistance should be equal to ZOUT of pulse generators.
B. CL includes probe and jig capacitance.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω,
slew rate ≥ 1 V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLH and tPHL are the same as tpd
F. tPLZ and tPHZ are the same as tdis
G. tPZL and tPZH are the same as ten
.
.
.
Figure 1. Test Circuit and Voltage Waveforms
6
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PCA9515A
DUAL BIDIRECTIONAL I2C BUS AND SMBus REPEATER
www.ti.com
SCPS150A–DECEMBER 2005–REVISED JUNE 2006
APPLICATION INFORMATION
A typical application is shown in Figure 2. In this example, the system master is running on a 3.3-V bus, while
the slave is connected to a 5-V bus. Both buses run at 100 kHz, unless the slave bus is isolated, and then the
master bus can run at 400 kHz. Master devices can be placed on either bus.
3.3 V
5 V
SDA
SCL
SDA1
SCL1
SDA0
SCL0
SDA
SCL
2
PCA9515A
EN
2
I C BUS SLAVE
100 kHz
I C BUS MASTER
400 kHz
BUS 0
BUS 1
Figure 2. Typical Application
The PCA9515A is 5.5-V tolerant, so it does not require any additional circuitry to translate between the different
bus voltages.
When one side of the PCA9515A is pulled low by a device on the I2C bus, a CMOS hysteresis-type input detects
the falling edge and causes an internal driver on the other side to turn on, thus causing the other side also to go
low. The side driven low by the PCA9515A typically is at VOL = 0.5 V.
Figure 3 and Figure 4 show the waveforms that are seen in a typical application. If the bus master in Figure 2
writes to the slave through the PCA9515A, Bus 0 has the waveform shown in Figure 3. This looks like a normal
I2C transmission until the falling edge of the eighth clock pulse. At that point, the master releases the data line
(SDA) while the slave pulls it low through the PCA9515A. Because the VOL of the PCA9515A typically is around
0.5 V, a step in the SDA is seen. After the master has transmitted the ninth clock pulse, the slave releases the
data line.
9th Clock Pulse
SCL
SDA
V
OL
of Master
V
OL
of PCA9515A
Figure 3. Bus 0 Waveforms
7
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PCA9515A
DUAL BIDIRECTIONAL I2C BUS AND SMBus REPEATER
www.ti.com
SCPS150A–DECEMBER 2005–REVISED JUNE 2006
APPLICATION INFORMATION (continued)
9th Clock Pulse
SCL
SDA
V
OL
of Slave
V
OL
of PCA9515A
Figure 4. Bus 1 Waveforms
On the Bus 1 side of the PCA9515A, the clock and data lines have a positive offset from ground equal to the
VOL of the PCA9515A. After the eighth clock pulse, the data line is pulled to the VOL of the slave device, which is
very close to ground in the example.
It is important to note that any arbitration or clock-stretching events on Bus 1 require that the VOL of the devices
on Bus 1 be 70 mV below the VOL of the PCA9515A (see VOL – VILc in Electrical Characteristics) to be
recognized by the PCA9515A and transmitted to Bus 0.
8
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PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
PCA9515AD
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
8
8
8
8
8
8
8
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCA9515ADGKR
PCA9515ADGKRG4
PCA9515ADR
MSOP
MSOP
SOIC
DGK
DGK
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCA9515ADT
SOIC
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCA9515APW
TSSOP
TSSOP
TSSOP
PW
PW
PW
150 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCA9515APWR
PCA9515APWT
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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