PCA9546APWT [TI]
4-CHANNEL I2C AND SMBus SWITCH WITH RESET FUNCTION; 4通道I2C和SMBus带复位功能开关
| 型号： | PCA9546APWT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 4-CHANNEL I2C AND SMBus SWITCH WITH RESET FUNCTION |
| 文件： | 总28页 (文件大小：1060K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PCA9546A
4-CHANNEL I2C AND SMBus SWITCH
WITH RESET FUNCTION
www.ti.com
SCPS148D–OCTOBER 2005–REVISED OCTOBER 2006
FEATURES
•
•
•
•
1-of-4 Bidirectional Translating Switches
I2C Bus and SMBus Compatible
Active-Low Reset Input
•
•
•
Supports Hot Insertion
Low Standby Current
Operating Power-Supply Voltage Range of
2.3 V to 5.5 V
Three Address Pins, Allowing up to Eight
Devices on the I2C Bus
Channel Selection Via I2C Bus
•
•
•
5.5-V Tolerant Inputs
•
•
0 to 400-kHz Clock Frequency
Power Up With All Switch Channels
Deselected
Latch-Up Performance Exceeds 100 mA Per
JESD 78
•
•
Low RON Switches
•
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
Allows Voltage-Level Translation Between
1.8-V, 2.5-V, 3.3-V, and 5-V Buses
•
No Glitch on Power Up
– 1000-V Charged-Device Model (C101)
DESCRIPTION/ORDERING INFORMATION
The PCA9546A is a quad bidirectional translating switch controlled via the I2C bus. The SCL/SDA upstream pair
fans out to four downstream pairs, or channels. Any individual SCn/SDn channel or combination of channels can
be selected, determined by the contents of the programmable control register.
An active-low reset (RESET) input allows the PCA9546A to recover from a situation in which one of the
downstream I2C buses is stuck in a low state. Pulling RESET low resets the I2C state machine and causes all
the channels to be deselected, as does the internal power-on reset function.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
PCA9546ARVR
PCA9546ARGYR
PCA9546AD
TOP-SIDE MARKING
PREVIEW
QFN – RGV
QFN – RGY
Reel of 2500
Reel of 1000
Tube of 40
PD546A
PCA9546ADG4
PCA9546ADR
SOIC – D
Reel of 2500
Reel of 250
PCA9546A
PCA9546ADRG4
PCA9546ADT
PCA9546ADTG4
PCA9546ADW
Tube of 40
Reel of 2000
Reel of 250
PCA9546A
PREVIEW
–40°C to 85°C
SOIC – DW
PCA9546ADWR
PCA9546ADWT
PCA9546APW
Tube of 90
Reel of 2000
Reel of 250
PCA9546APWE4
PCA9546APWR
PCA9546APWRE4
PCA9546APWT
PCA9546APWTE4
PCA9546ADGVR
PCA9546ADGVT
TSSOP – PW
TVSOP – DGV
PD546A
Reel of 2000
Reel of 250
PD546A
PREVIEW
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2005–2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
PCA9546A
4-CHANNEL I2C AND SMBus SWITCH
WITH RESET FUNCTION
www.ti.com
SCPS148D–OCTOBER 2005–REVISED OCTOBER 2006
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
The pass gates of the switches are constructed such that the VCC pin can be used to limit the maximum high
voltage, which will be passed by the PCA9546A. This allows the use of different bus voltages on each pair, so
that 1.8-V, 2.5-V, or 3.3-V parts can communicate with 5-V parts without any additional protection. External
pullup resistors pull the bus up to the desired voltage level for each channel. All I/O pins are 5.5-V tolerant.
RGV PACKAGE
RGY PACKAGE
(TOP VIEW)
(TOP VIEW)
D, DGV, DW, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A0
A1
VCC
1
16
16 15 14 13
2
3
4
5
6
7
15
14
13
12
11
10
A1
RESET
SD0
SDA
SCL
A2
SDA
SCL
A2
1
2
3
4
12
SCL
A2
RESET
SD0
RESET
SD0
11
10
9
SC0
SC3
SD3
SC2
SC0
SC3
SD3
SC0
SC3
SD3
SC2
SD2
SD1
SD1
SD1
SC1
5
6
7
8
8
9
SC1
GND
TERMINAL FUNCTIONS
NO.
NAME
DESCRIPTION
D, DGV, DW, PW,
AND RGY
RGV
1
2
15
16
1
A0
A1
Address input 0. Connect directly to VCC or ground.
Address input 1. Connect directly to VCC or ground.
3
RESET
SD0
SC0
SD1
SC1
GND
SD2
SC2
SD3
SC3
A2
Active low reset input. Connect to VCC through a pullup resistor, if not used.
Serial data 0. Connect to VCC through a pullup resistor.
Serial clock 0. Connect to VCC through a pullup resistor.
Serial data 1. Connect to VCC through a pullup resistor.
Serial clock 1. Connect to VCC through a pullup resistor.
Ground
4
2
5
3
6
4
7
5
8
6
9
7
Serial data 2. Connect to VCC through a pullup resistor.
Serial clock 2. Connect to VCC through a pullup resistor.
Serial data 3. Connect to VCC through a pullup resistor.
Serial clock 3. Connect to VCC through a pullup resistor.
Address input 2. Connect directly to VCC or ground.
Serial clock line. Connect to VCC through a pullup resistor.
Serial data line. Connect to VCC through a pullup resistor.
Supply power
10
11
12
13
14
15
16
8
9
10
11
12
13
14
SCL
SDA
VCC
2
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PCA9546A
4-CHANNEL I2C AND SMBus SWITCH
WITH RESET FUNCTION
www.ti.com
SCPS148D–OCTOBER 2005–REVISED OCTOBER 2006
BLOCK DIAGRAM
PCA9546A
5
SC0
SC1
SC2
SC3
SD0
SD1
SD2
7
10
12
4
6
9
11
SD3
Switch Control Logic
8
GND
16
3
V
CC
Power-On Reset
RESET
14
15
1
SCL
SDA
A0
2
Input Filter
A1
2
I C Bus Control
13
A2
A. Pin numbers shown are for the D, DGV, DW, PW and RGY packages.
3
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PCA9546A
4-CHANNEL I2C AND SMBus SWITCH
WITH RESET FUNCTION
www.ti.com
SCPS148D–OCTOBER 2005–REVISED OCTOBER 2006
Device Address
Following a start condition, the bus master must output the address of the slave it is accessing. The address of
the PCA9546A is shown in Figure 1. To conserve power, no internal pullup resistors are incorporated on the
hardware-selectable address pins, and they must be pulled high or low.
Slave Address
0
1
1
1
A2 A1
R/W
A0
Hardware
Selectable
Fixed
Figure 1. PCA9546A Address
The last bit of the slave address defines the operation to be performed. When set to a logic 1, a read is selected,
while a logic 0 selects a write operation.
Control Register
Following the successful acknowledgment of the slave address, the bus master sends a byte to the PCA9546A,
which is stored in the control register (see Figure 2). If multiple bytes are received by the PCA9546A, it will save
the last byte received. This register can be written and read via the I2C bus.
Channel Selection Bits
(Read/Write)
7
6
5
4
3
2
1
0
X
X
X
X
B3
B2
B1
B0
Channel 0
Channel 1
Channel 2
Channel 3
Figure 2. Control Register
Control Register Definition
One or several SCn/SDn downstream pairs, or channels, are selected by the contents of the control register
(see Table 1). This register is written after the PCA9546A has been addressed. The four LSBs of the control
byte are used to determine which channel or channels are to be selected. When a channel is selected, the
channel becomes active after a stop condition has been placed on the I2C bus. This ensures that all SCn/SDn
lines are in a high state when the channel is made active, so that no false conditions are generated at the time
of connection. A stop condition always must occur right after the acknowledge cycle.
4
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PCA9546A
4-CHANNEL I2C AND SMBus SWITCH
WITH RESET FUNCTION
www.ti.com
SCPS148D–OCTOBER 2005–REVISED OCTOBER 2006
Table 1. Control Register Write (Channel Selection), Control Register Read (Channel Status)(1)
B7
B6
B5
B4
B3
B2
B1
B0
0
COMMAND
Channel 0 disabled
X
X
X
X
X
X
X
1
Channel 0 enabled
Channel 1 disabled
Channel 1 enabled
Channel 2 disabled
Channel 2 enabled
Channel 3 disabled
Channel 3 enabled
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
X
0
1
X
0
X
0
X
0
X
0
X
0
X
0
X
0
No channel selected,
power-up/reset default state
0
(1) Several channels can be enabled at the same time. For example, B3 =0, B2 = 1, B1 = 1, B0 = 0 means that channels 0 and 3 are
disabled, and channels 1 and 2 are enabled. Care should be taken not to exceed the maximum bus capacity.
RESET Input
The RESET input is an active-low signal that may be used to recover from a bus-fault condition. When this
signal is asserted low for a minimum of tWL, the PCA9446A resets its registers and I2C state machine and
deselects all channels. The RESET input must be connected to VCC through a pullup resistor.
Power-On Reset
When power is applied to VCC, an internal power-on reset holds the PCA9546A in a reset condition until VCC has
reached VPOR. At this point, the reset condition is released, and the PCA9546A registers and I2C state machine
are initialized to their default states, all zeroes, causing all the channels to be deselected. Thereafter, VCC must
be lowered below 0.2 V to reset the device.
Voltage Translation
The pass-gate transistors of the PCA9546A are constructed such that the VCC voltage can be used to limit the
maximum voltage that will be passed from one I2C bus to another.
Figure 3 shows the voltage characteristics of the pass-gate transistors (note that the graph was generated using
the data specified in the electrical characteristics section of this data sheet). In order for the PCA9546A to act as
a voltage translator, the Vpass voltage must be equal to or lower than the lowest bus voltage. For example, if the
main bus is running at 5 V, and the downstream buses are 3.3 V and 2.7 V, then Vpass must be equal to or
below 2.7 V to effectively clamp the downstream bus voltages. As shown in Figure 3, Vpass (max) is at 2.7 V
when the PCA9546A supply voltage is 3.5 V or lower, so the PCA9546A supply voltage could be set to 3.3 V.
Pullup resistors then can be used to bring the bus voltages to their appropriate levels (see Figure 12).
5
4.5
Maximum
4
Typical
3.5
3
2.5
2
Minimum
1.5
1
2
2.5
3
3.5
4
4.5
5
5.5
V
CC
(V)
Figure 3. Vpass Voltage vs VCC
5
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PCA9546A
4-CHANNEL I2C AND SMBus SWITCH
WITH RESET FUNCTION
www.ti.com
SCPS148D–OCTOBER 2005–REVISED OCTOBER 2006
I2C Interface
The I2C bus is for two-way two-line communication between different ICs or modules. The two lines are a serial
data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pullup
resistor when connected to the output stages of a device. Data transfer can be initiated only when the bus is not
busy.
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high
period of the clock pulse, as changes in the data line at this time are interpreted as control signals (see
Figure 4).
SDA
SCL
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Figure 4. Bit Transfer
Both data and clock lines remain high when the bus is not busy. A high-to-low transition of the data line while
the clock is high is defined as the start condition (S). A low-to-high transition of the data line while the clock is
high is defined as the stop condition (P) (see Figure 5).
SDA
SCL
S
P
Start Condition
Stop Condition
Figure 5. Definition of Start and Stop Conditions
A device generating a message is a transmitter; a device receiving is the receiver. The device that controls the
message is the master, and the devices that are controlled by the master are the slaves (see Figure 6).
SDA
SCL
2
I C
Master
Transmitter/
Receiver
Master
Transmitter/
Receiver
Slave
Transmitter/
Receiver
Master
Transmitter
Slave
Receiver
Multiplexer
Slave
Figure 6. System Configuration
6
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PCA9546A
4-CHANNEL I2C AND SMBus SWITCH
WITH RESET FUNCTION
www.ti.com
SCPS148D–OCTOBER 2005–REVISED OCTOBER 2006
The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is
not limited. Each byte of eight bits is followed by one acknowledge (ACK) bit. The transmitter must release the
SDA line before the receiver can send an ACK bit.
When a slave receiver is addressed, it must generate an ACK after the reception of each byte. Also, a master
must generate an ACK after the reception of each byte that has been clocked out of the slave transmitter. The
device that acknowledges must pull down the SDA line during the ACK clock pulse so that the SDA line is stable
low during the high pulse of the ACK-related clock period (see Figure 7). Setup and hold times must be taken
into account.
Data Output
by Transmitter
NACK
Data Output
by Receiver
ACK
SCL From
1
2
8
9
Master
S
Start
Clock Pulse for ACK
Condition
Figure 7. Acknowledgment on the I2C Bus
Data is transmitted to the PCA9546A control register using the write mode shown in Figure 8.
Slave Address
Control Register
S
1
1
1
0
A2 A1 A0
0
A
X
X
X
X
B3 B2 B1 B0
A
P
SDA
Start Condition
R/W ACK From Slave
ACK From Slave
Stop Condition
Figure 8. Write Control Register
Data is read from the PCA9546A control register using the read mode shown in Figure 9.
Slave Address
Control Register
SDA
P
S
1
1
1
1
A
NA
B3 B2 B1 B0
0
A2 A1 A0
0
0
0
0
Start Condition
R/W ACK From Slave
NACK From Master Stop Condition
Figure 9. Read Control Register
7
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PCA9546A
4-CHANNEL I2C AND SMBus SWITCH
WITH RESET FUNCTION
www.ti.com
SCPS148D–OCTOBER 2005–REVISED OCTOBER 2006
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
MAX UNIT
VCC
VI
Supply voltage range
Input voltage range(2)
Input current
7
7
V
V
II
±20
±25
±100
±100
73
mA
mA
mA
mA
IO
Output current
Continuous current through VCC
Continuous current through GND
D package
DGV package
DW package
PW package
RGV package
RGY package
120
57
θJA
Package thermal impedance(3)
°C/W
108
TBD
50
Ptot
Tstg
TA
Total power dissipation
400
150
85
mW
°C
Storage temperature range
Operating free-air temperature range
–65
–40
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions(1)
MIN
2.3
MAX UNIT
VCC
VIH
Supply voltage
5.5
6
V
SCL, SDA
0.7 × VCC
0.7 × VCC
–0.5
High-level input voltage
V
A2–A0, RESET
SCL, SDA
VCC + 0.5
0.3 × VCC
0.3 × VCC
85
VIL
TA
Low-level input voltage
V
A2–A0, RESET
–0.5
Operating free-air temperature
–40
°C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
8
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PCA9546A
4-CHANNEL I2C AND SMBus SWITCH
WITH RESET FUNCTION
www.ti.com
SCPS148D–OCTOBER 2005–REVISED OCTOBER 2006
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VI = VCC or
VCC
MIN TYP(1)
MAX UNIT
VPOR
Power-on reset voltage(2)
No load,
VPOR
1.6
2.1
V
GND
5 V
3.6
4.5 V to 5.5 V
3.3 V
2.6
1.9
1.6
1.5
1.1
4.5
2.8
2
Vpass
Switch output voltage
VSWin = VCC
,
ISWout = –100 µA
V
3 V to 3.6 V
2.5 V
2.3 V to 2.7 V
VOL = 0.4 V
VOL = 0.6 V
3
6
7
IOL
SCL, SDA
2.3 V to 5.5 V
2.3 V to 5.5 V
mA
10
SCL, SDA
±1
±1
±1
±1
12
11
10
1
SC3–SC0, SD3–SD0
A2–A0
II
VI = VCC or GND
µA
RESET
5.5 V
3.6 V
2.7 V
5.5 V
3.6 V
2.7 V
5.5 V
3.6 V
2.7 V
3
3
Operating mode fSCL = 100 kHz VI = VCC or GND,
IO = 0
IO = 0
IO = 0
3
0.3
0.1
0.1
0.3
0.1
0.1
ICC
Low inputs
High inputs
VI = GND,
1
µA
1
Standby mode
1
VI = VCC
,
1
1
SCL or SDA input at 0.6 V,
Other inputs at VCC or GND
8
8
15
15
Supply-current
change
∆ICC
SCL, SDA
µA
SCL or SDA input at VCC – 0.6 V,
Other inputs at VCC or GND
2.3 V to 5.5 V
2.3 V to 5.5 V
A2–A0
4.5
4.5
15
6
6
5.5
19
8
Ci
VI = VCC or GND
pF
pF
RESET
SCL, SDA
(3)
Cio(OFF)
VI = VCC or GND,
Switch OFF
2.3 V to 5.5 V
SC3–SC0, SD3–SD0
4.5 V to 5.5 V
3 V to 3.6 V
4
5
7
9
16
20
45
VO = 0.4 V,
VO = 0.4 V,
IO = 15 mA
IO = 10 mA
RON
Switch on-state resistance
11
16
Ω
2.3 V to 2.7 V
(1) All typical values are at nominal supply voltage (2.5-V, 3.3-V, or 5-V VCC), TA = 25°C.
(2) The power-on reset circuit resets the I2C bus logic with VCC < VPOR. VCC must be lowered to 0.2 V to reset the device.
(3) Cio(ON) depends on internal capacitance and external capacitance added to the SCn lines when channels(s) are ON.
9
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PCA9546A
4-CHANNEL I2C AND SMBus SWITCH
WITH RESET FUNCTION
www.ti.com
SCPS148D–OCTOBER 2005–REVISED OCTOBER 2006
I2C Interface Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 10)
STANDARD MODE
I2C BUS
FAST MODE
I2C BUS
UNIT
MIN
0
MAX
MIN
0
MAX
400 kHz
fscl
tsch
tscl
tsp
I2C clock frequency
I2C clock high time
I2C clock low time
I2C spike time
I2C serial-data setup time
I2C serial-data hold time
I2C input rise time
I2C input fall time
100
4
0.6
1.3
µs
µs
ns
ns
µs
ns
ns
ns
µs
µs
µs
µs
µs
µs
4.7
50
50
tsds
tsdh
ticr
250
0(1)
100
0(1)
(2)
1000
300
20 + 0.1Cb
300
300
300
(2)
(2)
ticf
20 + 0.1Cb
20 + 0.1Cb
tocf
tbuf
tsts
tsth
tsps
I2C output fall time
10-pF to 400-pF bus
300
I2C bus free time between stop and start
I2C start or repeated start condition setup
I2C start or repeated start condition hold
I2C stop condition setup
4.7
4.7
4
1.3
0.6
0.6
0.6
4
tvdL(Data) Valid-data time (high to low)(3)
tvdH(Data) Valid-data time (low to high)(3)
SCL low to SDA output low valid
SCL low to SDA output high valid
1
1
0.6
0.6
ACK signal from SCL low
to SDA output low
tvd(ack)
Cb
Valid-data time of ACK condition
I2C bus capacitive load
1
1
µs
400
400
pF
(1) A device internally must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal), in order to
bridge the undefined region of the falling edge of SCL.
(2) Cb = total bus capacitance of one bus line in pF
(3) Data taken using a 1-kΩ pullup resistor and 50-pF load (see Figure 10)
Switching Characteristics
over recommended operating free-air temperature range, CL ≤ 100 pF (unless otherwise noted) (see Figure 10)
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX UNIT
RON = 20 Ω, CL = 15 pF
RON = 20 Ω, CL = 50 pF
0.3
ns
1
(1)
tpd
Propagation delay time
SDA or SCL
SDn or SCn
(1) The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load
capacitance, when driven by an ideal voltage source (zero output impedance).
Interrupt and Reset Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
MAX UNIT
tWL
Pulse duration, RESET low
RESET time (SDA clear)
6
ns
(1)
trst
500
ns
ns
tREC(STA)
Recovery time from RESET to start
0
(1) trst is the propagation delay measured from the time the RESET pin is first asserted low to the time the SDA pin is asserted high,
signaling a stop condition. It must be a minimum of tWL
.
10
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PCA9546A
4-CHANNEL I2C AND SMBus SWITCH
WITH RESET FUNCTION
www.ti.com
SCPS148D–OCTOBER 2005–REVISED OCTOBER 2006
PARAMETER MEASUREMENT INFORMATION
V
CC
R
L
= 1 kΩ
SDn, SCn
DUT
C
L
= 50 pF
(See Note A)
2
I C PORT LOAD CONFIGURATION
Two Bytes for Complete
Device Programming
Stop
Start
Address
Bit 7
(MSB)
R/W
Bit 0
(LSB)
Data
Bit 7
(MSB)
Data
Bit 0
(LSB)
Stop
Condition
(P)
ACK
(A)
Address
Bit 6
Address
Bit 1
ACK
(A)
Condition Condition
(P) (S)
BYTE
DESCRIPTION
2
1
I C address + R/W
2
Control register data
t
scl
t
sch
0.7 × V
0.3 × V
CC
SCL
SDA
CC
t
vd(ACK)
t
icr
t
sts
or t
vdL
t
icf
t
buf
t
sp
t
vdH
0.7 × V
0.3 × V
CC
CC
t
icf
t
icr
t
sdh
t
sps
t
sth
t
Repeat
sds
Stop
Condition
Start
Condition
Start or Repeat
Start Condition
VOLTAGE WAVEFORMS
A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω,
tr/tf ≤ 30 ns.
C. The outputs are measured one at a time, with one transition per measurement.
Figure 10. I2C Interface Load Circuit, Byte Descriptions, and Voltage Waveforms
11
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PCA9546A
4-CHANNEL I2C AND SMBus SWITCH
WITH RESET FUNCTION
www.ti.com
SCPS148D–OCTOBER 2005–REVISED OCTOBER 2006
PARAMETER MEASUREMENT INFORMATION (continued)
Start
ACK or Read Cycle
SCL
SDA
30%
50%
t
rst
RESET
LEDx
t
REC
t
WL
t
rst
50%
LED OFF
Figure 11. Reset Timing
12
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PCA9546A
4-CHANNEL I2C AND SMBus SWITCH
WITH RESET FUNCTION
www.ti.com
SCPS148D–OCTOBER 2005–REVISED OCTOBER 2006
APPLICATION INFORMATION
Figure 12 shows an application in which the PCA9546A can be used.
V
CC
= 2.7 V to 5.5 V
V
CC
= 3.3 V
16
V
CC
= 2.7 V to 5.5 V
See Note A
4
5
15
14
SD0
SDA
SCL
SDA
SCL
Channel 0
2
I C/SMBus
Master
SC0
3
V
CC
= 2.7 V to 5.5 V
RESET
See Note A
6
7
SD1
SC1
Channel 1
V
CC
= 2.7 V to 5.5 V
PCA9546A
See Note A
9
SD2
SC2
Channel 2
10
V
= 2.7 V to 5.5 V
CC
13
A2
See Note A
2
1
8
A1
11
12
SD3
SC3
A0
Channel 3
GND
A. Pin numbers shown are for the D, DGV, DW, PW, and RGY packages.
Figure 12. Typical Application
13
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PACKAGE OPTION ADDENDUM
www.ti.com
30-Jan-2007
PACKAGING INFORMATION
Orderable Device
PCA9546AD
Status (1)
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
16
16
16
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCA9546ADG4
PCA9546ADGVR
SOIC
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TVSOP
DGV
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCA9546ADGVT
PCA9546ADR
PREVIEW
ACTIVE
TVSOP
SOIC
DGV
D
20
16
250
TBD
Call TI
Call TI
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCA9546ADRG4
PCA9546ADT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
D
D
16
16
16
16
16
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCA9546ADTG4
PCA9546ADW
PCA9546ADWR
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DW
DW
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCA9546ADWT
PREVIEW
PREVIEW
DW
16
20
250
TBD
TBD
Call TI
Call TI
Call TI
Call TI
PCA9546AGQNR
BGA MI
CROSTA
R JUNI
OR
GQN
1000
PCA9546APW
PCA9546APWE4
PCA9546APWR
PCA9546APWRE4
PCA9546APWT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PREVIEW
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
QFN
PW
PW
16
16
16
16
16
16
16
16
16
20
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PW
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCA9546APWTE4
PCA9546ARGVR
PCA9546ARGYR
PCA9546ARGYRG4
PCA9546AZQNR
PW
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
RGV
RGY
RGY
ZQN
2500 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
QFN
1000 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
QFN
1000 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
BGA MI
CROSTA
R JUNI
OR
1000
TBD
Call TI
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Jan-2007
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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