PCA9548A [TI]
8-CHANNEL I2C SWITCH WITH RESET; 带复位8通道I2C开关
| 型号： | PCA9548A |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8-CHANNEL I2C SWITCH WITH RESET |
| 文件： | 总23页 (文件大小：522K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PCA9548A
8-CHANNEL I2C SWITCH
WITH RESET
www.ti.com
SCPS143B–OCTOBER 2006–REVISED MARCH 2007
FEATURES
•
•
•
•
1-of-8 Bidirectional Translating Switches
I2C Bus and SMBus Compatible
Active-Low Reset Input
•
•
•
•
No Glitch on Power-Up
Supports Hot Insertion
Low Standby Current
Address by Three Hardware Address Pins for
Use of up to Eight Devices
Operating Power-Supply Voltage Range of
2.3 V to 5.5 V
•
•
Channel Selection Via I2C Bus
•
•
•
5-V Tolerant Inputs
400-kHz Fast I2C Bus
Power-Up With All Switch Channels
Deselected
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
•
•
Low RON Switches
Allows Voltage-Level Translation Between
2.5-V, 3.3-V, and 5-V Buses
•
ESD Protection Exceeds JESD 22
–
–
–
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
1000-V Charged-Device Model (C101)
DB, DGV, DW, OR PW PACKAGE
(TOP VIEW)
RGE PACKAGE
(TOP VIEW)
VCC
1
24
23
22
21
20
19
18
17
16
15
14
13
A0
A1
2
SDA
SCL
A2
3
RESET
SD0
SC0
SD1
SC1
SD2
SC2
SD3
SC3
GND
24 23 22 21 20 19
4
1
18
17
16
15
14
13
SD0
SC0
SD1
SC1
SD2
SC2
A2
5
SC7
SD7
SC6
SD6
SC5
SD5
SC4
SD4
2
3
4
5
6
SC7
SD7
SC6
SD6
SC5
6
7
8
9
10
11
12
7
8 9 10 11 12
DESCRIPTION/ORDERING INFORMATION
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
PCA9548ARGER
PCA9548ADBR
TOP-SIDE MARKING
QFN – RGE
SSOP – DB
TVSOP – DGV
SOIC – DW
Reel of 3000
PD548A
Reel of 2000
Reel of 250
Reel of 2000
Reel of 2000
Tube of 25
PD548A
PCA9548ADBT
PCA9548ADGVR
PCA9548ADWR
PD548A
–40°C to 85°C
PCA9548A
PCA9548ADW
Reel of 2000
Tube of 60
PCA9548APWR
TSSOP – PW
PD548A
PCA9548APW
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006–2007, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
PCA9548A
8-CHANNEL I2C SWITCH
WITH RESET
www.ti.com
SCPS143B–OCTOBER 2006–REVISED MARCH 2007
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
The PCA9548A has eight bidirectional translating switches that can be controlled via the I2C bus. The SCL/SDA
upstream pair fans out to eight downstream pairs, or channels. Any individual SCx/SDx channel or combination
of channels can be selected, determined by the contents of the programmable control register.
The system master can reset the PCA9548A in the event of a timeout or other improper operation by asserting a
low in the RESET input. Similarly, the power-on reset deselects all channels and initializes the I2C/SMBus state
machine. Asserting RESET causes the same reset/initialization to occur without depowering the part.
The pass gates of the switches are constructed so that the VCC pin can be used to limit the maximum high
voltage, which is passed by the PCA9548A. This allows the use of different bus voltages on each pair, so that
2.5-V or 3.3-V parts can communicate with 5-V parts, without any additional protection. External pullup resistors
pull the bus up to the desired voltage level for each channel. All I/O pins are 5-V tolerant.
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PCA9548A
8-CHANNEL I2C SWITCH
WITH RESET
www.ti.com
SCPS143B–OCTOBER 2006–REVISED MARCH 2007
FUNCTIONAL BLOCK DIAGRAM
PCA9548A
SC0
SC1
SC2
SC3
SC4
SC5
SC6
SC7
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
Switch Control Logic
GND
VCC
Reset Circuit
RESET
A0
A1
A2
SCL
SDA
Input Filter
I2C Bus Control
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PCA9548A
8-CHANNEL I2C SWITCH
WITH RESET
www.ti.com
SCPS143B–OCTOBER 2006–REVISED MARCH 2007
TERMINAL FUNCTIONS
NO.
SOIC (DW),
NAME
DESCRIPTION
SSOP (DB),
TSSOP (PW), AND
TVSOP (DGV)
QFN (RGE)
1
22
23
24
1
A0
A1
Address input 0. Connect directly to VCC or ground.
Address input 1. Connect directly to VCC or ground.
2
3
RESET
SD0
SC0
SD1
SC1
SC2
SC2
SD3
SC3
GND
SD4
SC4
SD5
SC5
SD6
SC6
SD7
SC7
A2
Active-low reset input. Connect to VCC through a pullup resistor, if not used.
Serial data 0. Connect to VCC through a pullup resistor.
Serial clock 0. Connect to VCC through a pullup resistor.
Serial data 1. Connect to VCC through a pullup resistor.
Serial clock 1. Connect to VCC through a pullup resistor.
Serial data 2. Connect to VCC through a pullup resistor.
Serial clock 2. Connect to VCC through a pullup resistor.
Serial data 3. Connect to VCC through a pullup resistor.
Serial clock 3. Connect to VCC through a pullup resistor.
Ground
4
5
2
6
3
7
4
8
5
9
6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Serial data 4. Connect to VCC through a pullup resistor.
Serial clock 4. Connect to VCC through a pullup resistor.
Serial data 5. Connect to VCC through a pullup resistor.
Serial clock 5. Connect to VCC through a pullup resistor.
Serial data 6. Connect to VCC through a pullup resistor.
Serial clock 6. Connect to VCC through a pullup resistor.
Serial data 7. Connect to VCC through a pullup resistor.
Serial clock 7. Connect to VCC through a pullup resistor.
Address input 2. Connect directly to VCC or ground.
Serial clock bus. Connect to VCC through a pullup resistor.
Serial data bus. Connect to VCC through a pullup resistor.
Supply voltage
SCL
SDA
VCC
I2C Interface
The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be
connected to a positive supply through a pullup resistor when connected to the output stages of a device. Data
transfer may be initiated only when the bus is not busy.
I2C communication with this device is initiated by a master sending a start condition, a high-to-low transition on
the SDA input/output while the SCL input is high (see Figure 1). After the start condition, the device address
byte is sent, most significant bit (MSB) first, including the data direction bit (R/W).
After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA
input/output during the high of the ACK-related clock pulse. The address inputs (A0–A2) of the slave device
must not be changed between the start and the stop conditions.
On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control
commands (start or stop) (see Figure 2).
A stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the
master (see Figure 1).
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PCA9548A
8-CHANNEL I2C SWITCH
WITH RESET
www.ti.com
SCPS143B–OCTOBER 2006–REVISED MARCH 2007
Any number of data bytes can be transferred from the transmitter to receiver between the start and the stop
conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before
the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK
clock pulse so that the SDA line is stable low during the high pulse of the ACK-related clock period (see
Figure 3). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly,
the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold
times must be met to ensure proper operation.
A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK)
after the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line
high. In this event, the transmitter must release the data line to enable the master to generate a stop condition.
SDA
SCL
S
P
Start Condition
Stop Condition
Figure 1. Definition of Start and Stop Conditions
SDA
SCL
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Figure 2. Bit Transfer
Data Output
by Transmitter
NACK
Data Output
by Receiver
ACK
SCL From
Master
1
2
8
9
S
Start
Clock Pulse for
Condition
Acknowledgment
Figure 3. Acknowledgment on I2C Bus
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PCA9548A
8-CHANNEL I2C SWITCH
WITH RESET
www.ti.com
SCPS143B–OCTOBER 2006–REVISED MARCH 2007
Device Address
Figure 4 shows the address byte of the PCA9548A.
Slave Address
1
1
1
0
A2 A1 A0 R/W
Hardware
Selectable
Fixed
Figure 4. PCA9548A Address
Address Reference
INPUTS
I2C BUS SLAVE ADDRESS
A2
L
A1
L
A0
L
112 (decimal), 70 (hexadecimal)
113 (decimal), 71 (hexadecimal)
114 (decimal), 72 (hexadecimal)
115 (decimal), 73 (hexadecimal)
116 (decimal), 74 (hexadecimal)
117 (decimal), 75 (hexadecimal)
118 (decimal), 76 (hexadecimal)
119 (decimal), 77 (hexadecimal)
L
L
H
L
L
H
H
L
L
H
L
H
H
H
H
L
H
L
H
H
H
The last bit of the slave address defines the operation (read or write) to be performed. When it is high (1), a read
is selected, while a low (0) selects a write operation.
Control Register
Following the successful acknowledgment of the address byte, the bus master sends a command byte that is
stored in the control register in the PCA9548A (see Figure 5). This register can be written and read via the I2C
bus. Each bit in the command byte corresponds to a SCn/SDn channel and a high (or 1) selects this channel.
Multiple SCn/SDn channels may be selected at the same time. When a channel is selected, the channel
becomes active after a stop condition has been placed on the I2C bus. This ensures that all SCn/SDn lines are
in a high state when the channel is made active, so that no false conditions are generated at the time of
connection. A stop condition always must occur immediately after the acknowledge cycle. If multiple bytes are
received by the PCA9548A, it saves the last byte received.
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PCA9548A
8-CHANNEL I2C SWITCH
WITH RESET
www.ti.com
SCPS143B–OCTOBER 2006–REVISED MARCH 2007
Channel Selection Bits (Read/Write)
B7
B6
B5
B4
B3
B2
B1
B0
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
Figure 5. Control Register
Command Byte Definition
CONTROL REGISTER BITS
COMMAND
B0
B7
B6
B5
B4
B3
B2
B1
0
1
Channel 0 disabled
Channel 0 enabled
Channel 1 disabled
Channel 1 enabled
Channel 2 disabled
Channel 2 enabled
Channel 3 disabled
Channel 3 enabled
Channel 4 disabled
Channel 4 enabled
Channel 5 disabled
Channel 5 enabled
Channel 6 disabled
Channel 6 enabled
Channel 7 disabled
Channel 7 enabled
X
X
X
X
X
X
X
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
X
X
X
X
X
0
1
X
X
X
X
0
1
X
X
X
0
1
X
X
0
1
X
0
1
X
0
X
0
X
0
X
0
X
0
X
0
X
0
No channel selected,
power-up/reset default state
0
RESET Input
The RESET input is an active-low signal that may be used to recover from a bus-fault condition. When this
signal is asserted low for a minimum of tWL, the PCA9548A resets its registers and I2C state machine and
deselects all channels. The RESET input must be connected to VCC through a pullup resistor.
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PCA9548A
8-CHANNEL I2C SWITCH
WITH RESET
www.ti.com
SCPS143B–OCTOBER 2006–REVISED MARCH 2007
Power-On Reset
When power (from 0 V) is applied to VCC, an internal power-on reset holds the PCA9548A in a reset condition
until VCC has reached VPOR. At that point, the reset condition is released and the PCA9548A registers and I2C
state machine initialize to their default states. After that, VCC must be lowered to below 0.2 V and then back up
to the operating voltage for a power-reset cycle.
Voltage Translation
The pass-gate transistors of the PCA9548A are constructed such that the VCC voltage can be used to limit the
maximum voltage that is passed from one I2C bus to another. Figure 6 shows the voltage characteristics of the
pass-gate transistors (note that the graph was generated using the data specified in the Electrical
Characteristics section of this data sheet).
5
4.5
ISWout = –100µA
Maximum
4
3.5
Typical
3
2.5
2
Minimum
1.5
1
2
2.5
3
3.5
4
4.5
5
5.5
VCC (V)
Figure 6. Pass-Gate Voltage vs Supply Voltage at Three Process Points
For the PCA9548A to act as a voltage translator, the Vo(sw) voltage must be equal to, or lower than, the lowest
bus voltage. For example, if the main bus is running at 5 V and the downstream buses are 3.3 V and 2.7 V,
Vo(sw) should be equal to or below 2.7 V to effectively clamp the downstream bus voltages. As shown in
Figure 6, Vo(sw)(max) is 2.7 V when the PCA9548A supply voltage is 3.5 V or lower, so the PCA9548A supply
voltage can be set to 3.3 V. Pullup resistors then can be used to bring the bus voltages to their appropriate
levels (see Figure 11).
Bus Transactions
Data is exchanged between the master and PCA9548A through write and read commands.
Writes
Data is transmitted to the PCA9548A by sending the device address and setting the least-significant bit (LSB) to
a logic 0 (see Figure 4 for device address). The command byte is sent after the address and determines which
SCn/SDn channel receives the data that follows the command byte (see Figure 7). There is no limitation on the
number of data bytes sent in one write transmission.
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PCA9548A
8-CHANNEL I2C SWITCH
WITH RESET
www.ti.com
SCPS143B–OCTOBER 2006–REVISED MARCH 2007
Slave Address
Control Register
P
SDA
S
1
1
1
0
A2 A1 A0
0
A
B7 B6 B5 B4 B3 B2 B1 B0
A
Start Condition
R/W ACK From Slave
ACK From Slave
Stop Condition
Figure 7. Write to Control Register
Reads
The bus master first must send the PCA9548A address with the LSB set to a logic 1 (see Figure 4 for device
address). The command byte is sent after the address and determines which SCn/SDn channel is accessed.
After a restart, the device address is sent again, but this time, the LSB is set to a logic 1. Data from the
SCn/SDn channel defined by the command byte then is sent by the PCA9548A (see Figure 8). After a restart,
the value of the SCn/SDn channel defined by the command byte matches the SCn/SDn channel being accessed
when the restart occurred. Data is clocked into the SCn/SDn channel on the rising edge of the ACK clock pulse.
There is no limitation on the number of data bytes received in one read transmission, but when the final byte is
received, the bus master must not acknowledge the data.
Slave Address
Control Register
SDA
B7 B6 B5 B4 B3 B2 B1 B0 NA
P
S
1
1
1
0
A2 A1 A0
1
A
Start Condition
R/W ACK From Slave
NACK From Master Stop Condition
Figure 8. Read From Control Register
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PCA9548A
8-CHANNEL I2C SWITCH
WITH RESET
www.ti.com
SCPS143B–OCTOBER 2006–REVISED MARCH 2007
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
MAX
UNIT
VCC
VI
Supply voltage range
Input voltage range(2)
Input current
7
V
7
±20
±25
±100
63
V
II
mA
mA
mA
IO
Output current
ICC
Supply current
DB package
DGV package
DW package
PW package
RGE package
RGE package
86
θJA
Package thermal impedance, junction to free air(3)
46
°C/W
88
45
θJP
Tstg
TA
Package thermal impedance, junction to pad
Storage temperature range
1.5
150
85
°C/W
°C
–65
–40
Operating free-air temperature range
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions(1)
MIN
2.3
MAX UNIT
VCC
VIH
Supply voltage
5.5
6
V
SCL, SDA
0.7 × VCC
0.7 × VCC
–0.5
High-level input voltage
V
A2–A0, RESET
SCL, SDA
VCC + 0.5
0.3 × VCC
0.3 × VCC
85
VIL
TA
Low-level input voltage
V
A2–A0, RESET
–0.5
Operating free-air temperature
–40
°C
(1) All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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PCA9548A
8-CHANNEL I2C SWITCH
WITH RESET
www.ti.com
SCPS143B–OCTOBER 2006–REVISED MARCH 2007
Electrical Characteristics
VCC = 2.3 V to 3.6 V, over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
Power-on reset voltage(2)
TEST CONDITIONS
VCC
VPOR
MIN TYP(1)
MAX UNIT
VPOR
No load, VI = VCC or GND
1.6
2.1
4.5
2.8
2
V
5 V
3.6
4.5 V to 5.5 V
3.3 V
2.6
1.9
1.6
1.5
1.1
Vo(sw)
Switch output voltage
Vi(sw) = VCC, ISWout = –100 µA
V
3 V to 3.6 V
2.5 V
2.3 V to 2.7 V
VOL = 0.4 V
VOL = 0.6 V
3
6
6
9
IOL
SDA
2.3 V to 5.5 V
2.3 V to 5.5 V
mA
SCL, SDA
±1
±1
±1
±1
80
35
20
30
15
8
SC7–SC0, SD7–SD0
A2–A0
II
VI = VCC or GND
µA
RESET
5.5 V
3.6 V
2.7 V
5.5 V
3.6 V
2.7 V
5.5 V
3.6 V
2.7 V
5.5 V
3.6 V
2.7 V
50
20
11
9
fSCL = 400 kHz
VI = VCC or GND, IO = 0
VI = VCC or GND, IO = 0
VI = GND, IO = 0
Operating mode
fSCL = 100 kHz
Low inputs
6
4
ICC
µA
0.2
0.1
0.1
0.2
0.1
0.1
1
1
1
Standby mode
1
High inputs
VI = VCC, IO = 0
1
1
SCL or SDA input at 0.6 V,
Other inputs at VCC or GND
3
3
20
20
Supply-current
change
∆ICC
SCL, SDA
2.3 V to 5.5 V
µA
SCL or SDA input at VCC – 0.6 V,
Other inputs at VCC or GND
A2–A0
RESET
SCL
4
4
5
5
VI = VCC or GND
Ci
2.3 V to 5.5 V
2.3 V to 5.5 V
pF
pF
Ω
VI = VCC or GND, Switch OFF
VI = VCC or GND, Switch OFF
20
20
5.5
10
12
15
28
28
7.5
20
30
45
SDA
(3)
Cio(off)
SC7–SC0, SD7–SD0
Switch-on resistance
4.5 V to 5.5 V
3 V to 3.6 V
4
5
7
VO = 0.4 V, IO = 15 mA
VO = 0.4 V, IO = 10 mA
ron
2.3 V to 2.7 V
(1) All typical values are at nominal supply voltage (2.5-V, 3.3-V, or 5-V VCC), TA = 25°C.
(2) The power-on reset circuit resets the I2C bus logic with VCC < VPOR. VCC must be lowered to 0.2 V to reset the device.
(3) Cio(ON) depends on internal capacitance and external capacitance added to the SCn lines when channels(s) are ON.
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PCA9548A
8-CHANNEL I2C SWITCH
WITH RESET
www.ti.com
SCPS143B–OCTOBER 2006–REVISED MARCH 2007
I2C Interface Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 9)
STANDARD MODE
I2C BUS
FAST MODE
I2C BUS
UNIT
MIN
0
MAX
MIN
0
MAX
400 kHz
fscl
tsch
tscl
tsp
I2C clock frequency
I2C clock high time
I2C clock low time
I2C spike time
I2C serial-data setup time
I2C serial-data hold time
I2C input rise time
100
4
0.6
1.3
µs
µs
ns
ns
µs
ns
ns
ns
µs
µs
µs
µs
µs
µs
4.7
50
50
tsds
tsdh
ticr
250
0(1)
100
0(1)
(2)
1000
300
20 + 0.1Cb
300
300
300
(2)
(2)
ticf
I2C input fall time
20 + 0.1Cb
20 + 0.1Cb
tocf
tbuf
tsts
tsth
tsps
I2C output (SDn) fall time (10-pF to 400-pF bus)
I2C bus free time between stop and start
I2C start or repeated start condition setup
I2C start or repeated start condition hold
I2C stop condition setup
300
4.7
4.7
4
1.3
0.6
0.6
0.6
4
tvdL(Data) Valid-data time (high to low)(3)
tvdH(Data) Valid-data time (low to high)(3)
SCL low to SDA output low valid
SCL low to SDA output high valid
1
1
0.6
0.6
ACK signal from SCL low
to SDA output low
tvd(ack)
Cb
Valid-data time of ACK condition
I2C bus capacitive load
1
1
µs
400
400
pF
(1) A device internally must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal), to bridge
the undefined region of the falling edge of SCL.
(2) Cb = total bus capacitance of one bus line in pF
(3) Data taken using a 1-kΩ pullup resistor and 50-pF load (see Figure 10)
Switching Characteristics
over recommended operating free-air temperature range, CL ≤ 100 pF (unless otherwise noted) (see Figure 9)
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX UNIT
RON = 20 Ω, CL = 15 pF
RON = 20 Ω, CL = 50 pF
0.3
ns
1
(1)
(2)
tpd
trst
Propagation delay time
RESET time (SDA clear)
SDA or SCL
RESET
SDn or SCn
SDA
500
ns
(1) The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load
capacitance, when driven by an ideal voltage source (zero output impedance).
(2) trst is the propagation delay measured from the time the RESET pin is first asserted low to the time the SDA pin is asserted high,
signaling a stop condition. It must be a minimum of tWL
.
Reset Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
6
MAX UNIT
tW(L)
Pulse duration, RESET low
ns
ns
tREC(STA)
Recovery time from RESET to start
0
12
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PCA9548A
8-CHANNEL I2C SWITCH
WITH RESET
www.ti.com
SCPS143B–OCTOBER 2006–REVISED MARCH 2007
PARAMETER MEASUREMENT INFORMATION
VCC
RL = 1 kΩ
SDA
DUT
CL = 50 pF
(see Note A)
SDA LOAD CONFIGURATION
Three Bytes for Complete
Device Programming
Stop Start
Condition Condition
Address
Bit 7
(MSB)
Data
Bit 7
(MSB)
Data
Bit 0
(LSB)
Stop
Condition
(P)
R/W
Bit 0
(LSB)
ACK
(A)
Address
Bit 6
Address
Bit 1
(P)
(S)
tscl
tsch
0.7 × VCC
0.3 × VCC
SCL
SDA
ticr
tsts
tvd(ack)
ticf
tbuf
tsp
tvdH(Data)
0.7 × VCC
0.3 × VCC
tvdL(Data)
ticr
ticf
tsdh
tsps
tsth
tsds
Repeat Start
Condition
Stop
Condition
Start or
Repeat Start
Condition
VOLTAGE WAVEFORMS
BYTE
1
DESCRIPTION
I2C address
P-port data
2, 3
A. CL includes probe and jig capacitance.
B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C. Not all parameters and waveforms are applicable to all devices.
Figure 9. I2C Load Circuit and Voltage Waveforms
13
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PCA9548A
8-CHANNEL I2C SWITCH
WITH RESET
www.ti.com
SCPS143B–OCTOBER 2006–REVISED MARCH 2007
PARAMETER MEASUREMENT INFORMATION (continued)
V
CC
R
L
= 1 kΩ
SDA
DUT
C
L
= 50 pF
(see Note A)
SDA LOAD CONFIGURATION
Start
SCL
ACK or Read Cycle
SDA
0.3 y V
CC
t
RESET
RESET
V /2
CC
t
REC
t
w
SDn, SCn
0.3 y V
CC
t
RESET
A. CL includes probe and jig capacitance.
B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C. I/Os are configured as inputs.
D. Not all parameters and waveforms are applicable to all devices.
Figure 10. Reset Load Circuit and Voltage Waveforms
14
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PCA9548A
8-CHANNEL I2C SWITCH
WITH RESET
www.ti.com
SCPS143B–OCTOBER 2006–REVISED MARCH 2007
APPLICATION INFORMATION
Figure 11 shows an application in which the PCA9548A can be used.
V
CC
= 2.7 V to 5.5 V
V
CC
= 3.3 V
24
V
CC
= 2.7 V to 5.5 V
See Note A
4
5
23
22
SD0
SDA
SDA
SCL
Channel 0
2
I C/SMBus
Master
SCL
SC0
3
V
CC
= 2.7 V to 5.5 V
RESET
RESET
See Note A
6
7
SD1
SC1
Channel 1
V
CC
= 2.7 V to 5.5 V
See Note A
8
9
SD2
SC2
Channel 2
V
CC
= 2.7 V to 5.5 V
See Note A
10
11
SD3
SC3
Channel 3
V
CC
= 2.7 V to 5.5 V
PCA9548A
See Note A
13
14
SD4
SC4
Channel 4
V
CC
= 2.7 V to 5.5 V
See Note A
15
16
SD5
SC5
Channel 5
V
CC
= 2.7 V to 5.5 V
See Note A
17
18
SD6
SC6
Channel 6
V
= 2.7 V to 5.5 V
CC
21
A2
See Note A
2
1
A1
A0
19
20
SD7
SC7
Channel 7
12
GND
A. Pin numbers shown are for the DB, DW, PW, and DGV packages.
Figure 11. Typical Application
15
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PACKAGE OPTION ADDENDUM
www.ti.com
20-Mar-2007
PACKAGING INFORMATION
Orderable Device
PCA9548ADB
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SSOP
DB
24
24
24
24
24
24
24
24
60 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCA9548ADBR
PCA9548ADGVR
PCA9548ADW
PCA9548ADWR
PCA9548APW
SSOP
TVSOP
SOIC
DB
DGV
DW
DW
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
QFN
60 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCA9548APWR
PCA9548ARGER
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
RGE
3000 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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