PCF8575PWR [TI]
REMOTE 16-BIT I2C AND SMBus I/O EXPANDER WITH INTERRUPT OUTPUT; 远程16位I2C和SMBus I / O扩展器,带有中断输出型号: | PCF8575PWR |
厂家: | TEXAS INSTRUMENTS |
描述: | REMOTE 16-BIT I2C AND SMBus I/O EXPANDER WITH INTERRUPT OUTPUT |
文件: | 总28页 (文件大小:750K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PCF8575
REMOTE 16-BIT I2C AND SMBus I/O EXPANDER
WITH INTERRUPT OUTPUT
www.ti.com
SCPS121C–JANUARY 2005–REVISED OCTOBER 2006
FEATURES
•
Low Standby-Current Consumption of
10 µA Max
I2C to Parallel-Port Expander
Open-Drain Interrupt Output
Compatible With Most Microcontrollers
400-kHz Fast I2C Bus
•
•
•
Current Source to VCC for Actively Driving a
High at the Output
•
•
•
•
•
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
Address by Three Hardware Address Pins for
Use of up to Eight Devices
– 1000-V Charged-Device Model (C101)
•
Latched Outputs With High-Current Drive
Capability for Directly Driving LEDs
DB, DBQ, DGV, DW, OR PW PACKAGE
(TOP VIEW)
RHL PACKAGE
(TOP VIEW)
RGE PACKAGE
(TOP VIEW)
1
24
23
22
21
20
19
18
17
16
15
14
13
INT
A1
V
CC
1
24
2
SDA
SCL
A0
24 23 22 21 20 19
23
2
SDA
SCL
A0
P17
P16
P15
P14
P13
P12
P11
A1
A2
3
A2
P00
P01
P03
P03
P04
P05
1
2
3
4
5
6
18 A0
22
21
20
19
18
17
16
15
14
3
4
P00
P01
P02
P03
P04
P05
P06
P07
GND
17 P17
16 P16
15 P15
14 P14
13 P13
4
P00
P01
P02
P03
P04
P05
P06
P07
5
P17
P16
P15
P14
P13
P12
P11
P10
5
6
6
7
7
8
8
9
7
8 9 10 11 12
9
10
11
12
10
11
12
13
DESCRIPTION/ORDERING INFORMATION
This 16-bit I/O expander for the two-line bidirectional bus (I2C) is designed for 2.5-V to 5.5-V VCC operation.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
PCF8575DBR
TOP-SIDE MARKING
Reel of 2000
SSOP – DB
PF575
Reel of 250
Reel of 2500
Reel of 2000
Tube of 25
PCF8575DBT
QSOP – DBQ
TVSOP – DGV
PCF8575DBQR
PCF8575DGVR
PCF8575DW
PCF8575
PF575
SOIC – DW
PCF8575
–40°C to 85°C
Reel of 2000
Tube of 60
PCF8575DWR
PCF8575PW
TSSOP – PW
Reel of 1200
Reel of 250
Reel of 3000
Reel of 1000
PCF8575PWR
PF575
PCF8575PWT
QFN – RGE
QFN – RHL
PCF8575RGER
PCF8575RHLR
PF575
PF575
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2005–2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
PCF8575
REMOTE 16-BIT I2C AND SMBus I/O EXPANDER
WITH INTERRUPT OUTPUT
www.ti.com
SCPS121C–JANUARY 2005–REVISED OCTOBER 2006
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
The PCF8575 provides general-purpose remote I/O expansion for most microcontroller families via the I2C
interface serial clock (SCL) and serial data (SDA).
The device features a 16-bit quasi-bidirectional input/output (I/O) port (P07–P00, P17–P10), including latched
outputs with high-current drive capability for directly driving LEDs. Each quasi-bidirectional I/O can be used as
an input or output without the use of a data-direction control signal. At power on, the I/Os are high. In this mode,
only a current source (IOH) to VCC is active. An additional strong pullup to VCC (IOHT) allows fast-rising edges into
heavily loaded outputs. This device turns on when an output is written high and is switched off by the negative
edge of SCL. The I/Os should be high before being used as inputs. After power on, as all the I/Os are set high,
all of them can be used as inputs. Any change in setting of the I/Os as either input or outputs can be done with
the write mode. If a high is applied externally to an I/O that has been written earlier to low, a large current (IOL
)
will flow to GND.
The PCF8575 provides an open-drain interrupt (INT) output, which can be connected to the interrupt input of a
microcontroller. An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After
time, tiv, the signal INT is valid. Resetting and reactivating the interrupt circuit is achieved when data on the port
is changed to the original setting, or data is read from or written to the port that generated the interrupt.
Resetting occurs in the read mode at the acknowledge (ACK) bit after the rising edge of the SCL signal or in the
write mode at the ACK bit after the falling edge of the SCL signal. Interrupts that occur during the ACK clock
pulse can be lost (or be very short), due to the resetting of the interrupt during this pulse. Each change of the
I/Os after resetting is detected and is transmitted as INT. Reading from or writing to another device does not
affect the interrupt circuit.
By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data
on its ports, without having to communicate via the I2C bus. Thus, the PCF8575 can remain a simple slave
device.
Every data transmission to or from the PCF8575 must consist of an even number of bytes. The first data byte in
every pair refers to port 0 (P07–P00), and the second data byte in every pair refers to port 1 (P17–P10). To
write to the ports (output mode), the master first addresses the slave device, setting the last bit of the byte
containing the slave address to logic 0. The PCF8575 acknowledges, and the master sends the first data byte
for P07–P00. After the first data byte is acknowledged by the PCF8575, the second data byte (P17–P10) is sent
by the master. Once again, the PCF8575 acknowledges the receipt of the data, after which this 16-bit data is
presented on the port lines.
The number of data bytes that can be sent successively is not limited. After every two bytes, the previous data is
overwritten. When the PCF8575 receives the pairs of data bytes, the first byte is referred to as P07–P00 and the
second byte as P17–P10. The third byte is referred to as P07–P00, the fourth byte as P17–P10, and so on.
Before reading from the PCF8575, all ports desired as input should be set to logic 1. To read from the ports
(input mode), the master first addresses the slave device, setting the last bit of the byte containing the slave
address to logic 1. The data bytes that follow on the SDA are the values on the ports. If the data on the input
port changes faster than the master can read, this data may be lost.
When power is applied to VCC, an internal power-on reset holds the PCF8575 in a reset state until VCC has
reached VPOR. At that time, the reset condition is released, and the device I2C-bus state machine initializes the
bus to its default state.
The hardware pins (A0, A1, and A2) are used to program and vary the fixed I2C address and allow up to eight
devices to share the same I2C bus or SMBus. The fixed I2C address of the PCF8575 is the same as the
PCF8575C, PCF8574, PCA9535, and PCA9555, allowing up to eight of these devices, in any combination, to
share the same I2C bus or SMBus.
2
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PCF8575
REMOTE 16-BIT I2C AND SMBus I/O EXPANDER
WITH INTERRUPT OUTPUT
www.ti.com
SCPS121C–JANUARY 2005–REVISED OCTOBER 2006
TERMINAL FUNCTIONS
NO.
DB, DBQ, DGV,
DW, PW, AND
RHL
NAME
FUNCTION
RGE
1
22
23
24
1
INT
A1
Interrupt output. Connect to VCC through a pullup resistor.
Address input 1. Connect directly to VCC or ground. Pullup resistors are not needed.
Address input 2. Connect directly to VCC or ground. Pullup resistors are not needed.
P-port input/output. Push-pull design structure.
P-port input/output. Push-pull design structure.
P-port input/output. Push-pull design structure.
P-port input/output. Push-pull design structure.
P-port input/output. Push-pull design structure.
P-port input/output. Push-pull design structure.
P-port input/output. Push-pull design structure.
P-port input/output. Push-pull design structure.
Ground
2
3
A2
4
P00
P01
P02
P03
P04
P05
P06
P07
GND
P10
P11
P12
P13
P14
P15
P16
P17
A0
5
2
6
3
7
4
8
5
9
6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
P-port input/output. Push-pull design structure.
P-port input/output. Push-pull design structure.
P-port input/output. Push-pull design structure.
P-port input/output. Push-pull design structure.
P-port input/output. Push-pull design structure.
P-port input/output. Push-pull design structure.
P-port input/output. Push-pull design structure.
P-port input/output. Push-pull design structure.
Address input 0. Connect directly to VCC or ground. Pullup resistors are not needed.
Serial clock line. Connect to VCC through a pullup resistor
Serial data line. Connect to VCC through a pullup resistor.
Supply voltage
SCL
SDA
VCC
3
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PCF8575
REMOTE 16-BIT I2C AND SMBus I/O EXPANDER
WITH INTERRUPT OUTPUT
www.ti.com
SCPS121C–JANUARY 2005–REVISED OCTOBER 2006
LOGIC DIAGRAM (POSITIVE LOGIC)
PCF8575
1
Interrupt
Logic
LP Filter
INT
21
2
A0
A1
A2
P07−P00
P17−P10
3
22
23
SCL
SDA
2
Input
Filter
I C Bus
Shift
Register
I/O
Port
16 Bits
Control
Write Pulse
Read Pulse
24
12
V
Power-On
Reset
CC
GND
SIMPLIFIED SCHEMATIC DIAGRAM OF EACH P-PORT INPUT/OUTPUT
V
CC
Write Pulse
I
OH
100 µA
I
OHT
Data From
Shift Register
D
C
Q
FF
S
P07−P00
P17−P10
I
I
OL
Power-On
Reset
D
C
Q
GND
FF
S
I
Read Pulse
To Interrupt
Logic
Data To
Shift Register
4
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PCF8575
REMOTE 16-BIT I2C AND SMBus I/O EXPANDER
WITH INTERRUPT OUTPUT
www.ti.com
SCPS121C–JANUARY 2005–REVISED OCTOBER 2006
I2C Interface
The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be
connected to a positive supply via a pullup resistor when connected to the output stages of a device. Data
transfer may be initiated only when the bus is not busy.
I2C communication with this device is initiated by a master sending a Start condition, a high-to-low transition on
the SDA input/output while the SCL input is high (see Figure 1). After the Start condition, the device address
byte is sent, most significant bit (MSB) first, including the data direction bit (R/W). This device does not respond
to the general call address. After receiving the valid address byte, this device responds with an ACK, a low on
the SDA input/output during the high of the ACK-related clock pulse. The address inputs (A2–A0) of the slave
device must not be changed between the Start and Stop conditions.
The data byte follows the address ACK. If the R/W bit is high, the data from this device are the values read from
the P port. If the R/W bit is low, the data are from the master, to be output to the P port. The data byte is
followed by an ACK sent from this device. If other data bytes are sent from the master, following the ACK, they
are ignored by this device. Data are output only if complete bytes are received and acknowledged. The output
data is valid at time (tpv) after the low-to-high transition of SCL, during the clock cycle for the ACK.
On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control
commands (Start or Stop) (see Figure 2).
A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the
master (see Figure 1).
The number of data bytes transferred between the Start and Stop conditions from transmitter to receiver is not
limited. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before the
receiver can send an ACK bit.
A slave receiver that is addressed must generate an ACK after the reception of each byte. Also, a master must
generate an ACK after the reception of each byte that has been clocked out of the slave transmitter. The device
that acknowledges has to pull down the SDA line during the ACK clock pulse so that the SDA line is stable low
during the high pulse of the ACK-related clock period (see Figure 3). Setup and hold times must be taken into
account.
A master receiver must signal an end of data to the transmitter by not generating an acknowledge (NACK) after
the last byte that has been clocked out of the slave. This is done by the master receiver by holding the SDA line
high. In this event, the transmitter must release the data line to enable the master to generate a Stop condition.
SDA
SCL
S
P
Start Condition
Stop Condition
Figure 1. Definition of Start and Stop Conditions
5
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PCF8575
REMOTE 16-BIT I2C AND SMBus I/O EXPANDER
WITH INTERRUPT OUTPUT
www.ti.com
SCPS121C–JANUARY 2005–REVISED OCTOBER 2006
SDA
SCL
Data Line
Stable;
Change
of Data
Data Valid
Allowed
Figure 2. Bit Transfer
Data Output
by Transmitter
NACK
Data Output
by Receiver
ACK
SCL from
Master
1
2
8
9
S
Start
Clock Pulse for
Condition
Acknowledgment
Figure 3. Acknowledgment on I2C Bus
Interface Definition
BIT
BYTE
7 (MSB)
L
6
5
4
3
2
1
0 (LSB)
I2C slave address
P0x I/O data bus
P1x I/O data bus
H
L
L
A2
A1
A0
R/W
P00
P10
P07
P06
P16
P05
P15
P04
P14
P03
P13
P02
P12
P01
P11
P17
6
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PCF8575
REMOTE 16-BIT I2C AND SMBus I/O EXPANDER
WITH INTERRUPT OUTPUT
www.ti.com
SCPS121C–JANUARY 2005–REVISED OCTOBER 2006
Figure 4 and Figure 5 show the address and timing diagrams for the write and read modes, respectively.
Integral Multiples of Two Bytes
SCL
1
6
2
3
4
6
7
8
1
2
3
4
5
7
8
1
2
3
4
5
6
7
8
5
ACK
From Slave
Start
Condition
ACK
From Slave
ACK
From Slave
R/W
Slave Address (PCF8575C)
Data to Port 0
Data to Port 1
SDA
S
0
1
0
0
A2 A1 A0
0
A
P07 P06
1
P00
A
P17
P10 A
P05
Write to
Port
Data A0
and B0
Valid
Data Output
Voltage
t
pv
P05 Output
Voltage
I
P05 Pullup
Output
OH
I
OHT
Current
INT
t
ir
Figure 4. Write Mode (Output)
SCL
1
6
2
3
4
6
7
8
1
2
3
4
5
7
8
1
2
3
4
5
6
7
8
5
ACK
From Master
ACK
From Slave
ACK
From Master
R/W
P07 P06 P05 P04 P03 P02 P01 P00
P17 P16 P15 P14 P13 P12 P11 P10
SDA
S
0
1
0
0
A2
1
A
A
P07 P06
A
A1 A0
Read From
Port
Data Into
Port
P17 to P10
P07 to P00
P17 to P10
P07 to P00
t
su
t
h
INT
t
ir
t
iv
t
ir
A low-to-high transition of SDA while SCL is high is defined as the stop condition (P). The transfer of data can be stopped at any moment by
a stop condition. When this occurs, data present at the latest ACK phase is valid (output mode). Input data is lost.
Figure 5. Read Mode (Input)
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PCF8575
REMOTE 16-BIT I2C AND SMBus I/O EXPANDER
WITH INTERRUPT OUTPUT
www.ti.com
SCPS121C–JANUARY 2005–REVISED OCTOBER 2006
Address Reference
INPUTS
I2C BUS SLAVE ADDRESS
A2
L
A1
L
A0
L
32 (decimal), 20 (hexadecimal)
33 (decimal), 21 (hexadecimal)
34 (decimal), 22 (hexadecimal)
35 (decimal), 23 (hexadecimal)
36 (decimal), 24 (hexadecimal)
37 (decimal), 25 (hexadecimal)
38 (decimal), 26 (hexadecimal)
39 (decimal), 27 (hexadecimal)
L
L
H
L
L
H
H
L
L
H
L
H
H
H
H
L
H
L
H
H
H
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX
6.5
UNIT
VCC
VI
Supply voltage range
Input voltage range(2)
Output voltage range(2)
V
VCC + 0.5
VCC + 0.5
–20
–20
–20
50
V
VO
IIK
V
Input clamp current
VI < 0
mA
mA
mA
mA
mA
mA
IOK
IOK
IOL
IOH
Output clamp current
VO < 0
Input/output clamp current
Continuous output low current
Continuous output high current
Continuous current through VCC or GND
VO < 0 or VO > VCC
VO = 0 to VCC
VO = 0 to VCC
–4
±100
63
DB package
DBQ package
DGV package
DW package
PW package
RGE package
RHL package
61
86
θJA
Package thermal impedance(3)
46
°C/W
88
53
43
Tstg
Storage temperature range
–65
150
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions
MIN
2.5
MAX
5.5
UNIT
V
VCC
VIH
VIL
Supply voltage
High-level input voltage
0.7 × VCC
–0.5
VCC + 0.5
0.3 × VCC
–1
V
Low-level input voltage
V
IOH
IOHT
IOL
P-port high-level output current
P-port transient pullup current
P-port low-level output current
Operating free-air temperature
mA
mA
mA
°C
–10
25
TA
–40
85
8
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REMOTE 16-BIT I2C AND SMBus I/O EXPANDER
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SCPS121C–JANUARY 2005–REVISED OCTOBER 2006
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
II = –18 mA
VCC
2.5 V to 5.5 V
VPOR
MIN TYP(1)
MAX
UNIT
V
VIK
Input diode clamp voltage
VPOR Power-on reset voltage(2)
–1.2
1.2
VI = VCC or GND, IO = 0
VO = GND
1.8
V
IOH P port
2.5 V to 5.5 V
2.5 V
–30
–300
µA
mA
IOHT P-port transient pullup current
SDA
High during ACK, VOH = GND
VOL = 0.4 V
–0.5
3
–1
VOL = 0.4 V
5
15
25
IOL
P port
2.5 V to 5.5 V
mA
VOL = 1 V
10
1.6
INT
VOL = 0.4 V
SCL, SDA
A0, A1, A2
P port
±5
±1
II
VI = VCC or GND
2.5 V to 5.5 V
µA
µA
IIHL
VI ≥ VCC or VI ≤ GND
2.5 V to 5.5 V
5.5 V
±400
200
75
100
30
VI = VCC or GND, IO = 0,
fscl = 400 kHz
Operating mode
Standby mode
3.6 V
2.7 V
20
50
ICC
µA
5.5 V
2.5
2.5
2.5
10
VI = VCC or GND, IO = 0, fscl = 0 kHz
3.6 V
10
2.7 V
10
One input at VCC – 0.6 V,
Other inputs at VCC or GND
∆ICC Supply current increase
2.5 V to 5.5 V
2.5 V to 5.5 V
200
µA
CI
SCL
VI = VCC or GND
3
3
4
7
7
pF
SDA
P port
Cio
VIO = VCC or GND
2.5 V to 5.5 V
pF
10
(1) All typical values are at nominal supply voltage (2.5-V, 3.3-V, or 5-V VCC) and TA = 25°C.
(2) The power-on reset circuit resets the I2C bus logic with VCC < VPOR and sets all I/Os to logic high (with current source to VCC).
I2C Interface Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 6)
MIN
MAX UNIT
fscl
tsch
tscl
tsp
I2C clock frequency
I2C clock high time
I2C clock low time
I2C spike time
I2C serial data setup time
I2C serial data hold time
I2C input rise time
I2C input fall time
I2C output fall time
I2C bus free time between Stop and Start
I2C start or repeated Start condition setup
I2C start or repeated Start condition hold
I2C Stop condition setup
Valid-data time
400
kHz
µs
µs
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
µs
pF
0.6
1.3
50
tsds
tsdh
ticr
100
0
(1)
20 + 0.1Cb
300
300
300
(1)
ticf
20 + 0.1Cb
tocf
tbuf
tsts
tsth
tsps
tvd
10-pF to 400-pF bus
1.3
0.6
0.6
0.6
SCL low to SDA output valid
1.2
Cb
I2C bus capacitive load
400
(1) Cb = total bus capacitance of one bus line in pF
9
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REMOTE 16-BIT I2C AND SMBus I/O EXPANDER
WITH INTERRUPT OUTPUT
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SCPS121C–JANUARY 2005–REVISED OCTOBER 2006
Switching Characteristics
over recommended operating free-air temperature range, CL ≤ 100 pF (unless otherwise noted) (see Figure 7 and Figure 8)
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX
UNIT
tiv
tir
Interrupt valid time
Interrupt reset delay time
Output data valid
P port
SCL
INT
INT
4
4
4
µs
µs
µs
µs
µs
tpv
tsu
th
SCL
P port
SCL
SCL
Input data setup time
Input data hold time
P port
P port
0
4
10
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REMOTE 16-BIT I2C AND SMBus I/O EXPANDER
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SCPS121C–JANUARY 2005–REVISED OCTOBER 2006
TYPICAL OPERATING CHARACTERISTICS
TA = 25°C (unless otherwise noted)
Standby Supply Current
Supply Current
vs Supply Voltage
Supply Current
vs Temperature
vs Temperature
90
100
90
80
70
60
50
40
30
20
10
0
120
SCL = V
CC
f
= 400 kHz
All I/Os unloaded
f
= 400 kHz
All I/Os unloaded
SCL
SCL
80
70
60
50
40
30
20
10
0
All I/Os unloaded
100
80
60
40
20
0
V
CC
= 5 V
V
CC
= 5 V
V
CC
= 2.5 V
V
CC
= 3.3 V
V
CC
= 3.3 V
V
CC
= 2.5 V
−50 −25
0
25 50 75 100 125
−50 −25
0
25 50 75 100 125
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Temperature (5C)
Temperature (5C)
Supply Voltage (V)
I/O Sink Current
I/O Sink Current
I/O Sink Current
vs Output Low Voltage
vs Output Low Voltage
vs Output Low Voltage
20
18
16
14
12
10
8
25
20
15
10
5
35
30
25
20
15
10
5
V
CC
= 2.5 V
V
CC
= 3.3 V
V
CC
= 5 V
T
A
= −40_C
T
= −40_C
T
A
= −40_C
A
T
= 25_C
A
T
A
= 25_C
T
A
= 25_C
6
T
A
= 85_C
T
A
= 85_C
T
A
= 85_C
4
2
0
0
0
0.0 0.1 0.2 0.3 0.4 0.5 0.6
0.0 0.1 0.2 0.3 0.4 0.5 0.6
0.0 0.1 0.2 0.3 0.4 0.5 0.6
V
OL
(V)
V
OL
(V)
Vol (V)
I/O Source Current
vs Output High Voltage
I/O Source Current
vs Output High Voltage
I/O Output Low Voltage
vs Temperature
600
500
400
300
200
100
0
45
40
35
30
25
20
15
10
5
45
40
35
30
25
20
15
10
5
V
CC
= 2.5 V
V
CC
= 3.3 V
T
A
= −40_C
T
= 25_C
A
V
CC
= 5 V, I
= 10 mA
SINK
T
A
= −40_C
T
= 25_C
A
V
CC
= 2.5 V, I
= 10 mA
= 5 V,
SINK
V
CC
V
CC
= 2.5 V,
I
= 1 mA
SINK
T
= 85_C
T
A
= 85_C
A
I
= 1 mA
SINK
0
0
−50 −25
0
25 50 75 100 125
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
Temperature (5C)
V
CC
− V (V)
V
CC
− V (V)
OH
OH
11
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REMOTE 16-BIT I2C AND SMBus I/O EXPANDER
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SCPS121C–JANUARY 2005–REVISED OCTOBER 2006
I/O Source Current
vs Output High Voltage
I/O High Voltage
vs Temperature
45
350
300
250
200
150
100
50
V
CC
= 5 V
T
= −40_C
40
35
30
25
20
15
10
5
A
V
CC
= 5 V
T
A
= 25_C
V
CC
= 3.3 V
V
CC
= 2.5 V
T
A
= 85_C
0
0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
−50 −25
0
25 50 75 100 125
Temperature (5C)
V
CC
− V (V)
OH
12
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REMOTE 16-BIT I2C AND SMBus I/O EXPANDER
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SCPS121C–JANUARY 2005–REVISED OCTOBER 2006
PARAMETER MEASUREMENT INFORMATION
V
CC
R
L
= 1 kΩ
SDA
DUT
C
L
= 50 pF
SDA LOAD CONFIGURATION
3 Bytes for Complete Device
Programming
Stop
Start
Address
Bit 7
(MSB)
R/W
Bit 0
(LSB)
Data
Bit 07
(MSB)
Data
Bit 10 Condition
(LSB)
Stop
ACK
(A)
Address
Bit 6
Address
Bit 1
Condition Condition
(P) (S)
(P)
t
scl
t
sch
0.7 × V
0.3 × V
CC
SCL
SDA
CC
t
icr
t
sts
t
PHL
t
icf
t
buf
t
t
sp
PLH
0.7 × V
0.3 × V
CC
CC
t
icf
t
icr
t
sdh
t
sps
t
sth
t
sds
Repeat
Start
Condition
Stop
Condition
Start or
Repeat
Start
Condition
VOLTAGE WAVEFORMS
BYTE
DESCRIPTION
2
1
I C address
2, 3
P-port data
Figure 6. I2C Interface Load Circuit and Voltage Waveforms
13
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REMOTE 16-BIT I2C AND SMBus I/O EXPANDER
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SCPS121C–JANUARY 2005–REVISED OCTOBER 2006
PARAMETER MEASUREMENT INFORMATION (continued)
V
CC
R
L
= 4.7 kΩ
INT
DUT
C
L
= 100 pF
INTERRUPT LOAD CONFIGURATION
ACK
From Slave
ACK
From Slave
Start
Condition
16 Bits
(2 Data Bytes)
R/W
From Port
Slave Address (PCF8575)
Data From Port
Data 3
A
2
A A
1 0
S
0
1
0
0
1
A
Data 1
Data 2
A
1
P
1
2
3
4
5
6
7
8
A
A
t
ir
B
B
t
ir
INT
A
t
iv
t
sps
A
Data
Into
Port
Address
Data 1
Data 2
Data 3
0.7 × V
0.3 × V
CC
0.7 × V
0.3 × V
CC
SCL
INT
INT
R/W
A
CC
CC
t
iv
t
ir
0.7 × V
0.7 × V
CC
CC
P
n
0.3 × V
0.3 × V
CC
CC
View A−A
View B−B
Figure 7. Interrupt Load Circuit and Voltage Waveforms
14
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REMOTE 16-BIT I2C AND SMBus I/O EXPANDER
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SCPS121C–JANUARY 2005–REVISED OCTOBER 2006
PARAMETER MEASUREMENT INFORMATION (continued)
V
CC
V
CC
R
L
= 1 kΩ
R
L
= 4.7 kΩ
SDA
INT
Pn
DUT
DUT
DUT
C
L
= 50 pF
C
L
= 100 pF
C = 100 pF
L
GND
GND
INTERRUPT LOAD CONFIGURATION
GND
P-PORT LOAD CONFIGURATION
SDA LOAD CONFIGURATION
0.7 × V
0.3 × V
CC
SCL
SDA
P00
A
P17
CC
Slave
ACK
t
pv
P
n
Last Stable Bit
Unstable
Data
Write-Mode Timing (R/W = 0)
0.7 × V
0.3 × V
CC
SCL
P00
A
P17
CC
t
su
t
h
0.7 × V
0.3 × V
CC
P
n
CC
Read-Mode Timing (R/W = 1)
Figure 8. P-Port Load Circuits and Voltage Waveforms
15
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REMOTE 16-BIT I2C AND SMBus I/O EXPANDER
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SCPS121C–JANUARY 2005–REVISED OCTOBER 2006
THERMAL PAD MECHANICAL DATA
RGE (S-PQFP-N24)
16
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SCPS121C–JANUARY 2005–REVISED OCTOBER 2006
THERMAL PAD MECHANICAL DATA
RHL (S-PQFP-N24)
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PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2006
PACKAGING INFORMATION
Orderable Device
PCF8575DB
Status (1)
PREVIEW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PREVIEW
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SSOP
DB
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
60 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCF8575DBQR
PCF8575DBQRE4
PCF8575DBQRG4
PCF8575DBR
SSOP/
QSOP
DBQ
DBQ
DBQ
DB
2500 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
SSOP/
QSOP
2500 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
SSOP/
QSOP
2500 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
SSOP
SSOP
TVSOP
TVSOP
SOIC
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCF8575DBRE4
PCF8575DGVR
PCF8575DGVRE4
PCF8575DW
DB
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DGV
DGV
DW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCF8575DWR
PCF8575PW
SOIC
DW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
QFN
PW
60 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCF8575PWE4
PCF8575PWR
PCF8575PWRE4
PCF8575RGER
PCF8575RHLR
PW
60 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
RGE
RHL
3000 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
QFN
1000
TBD
Call TI
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2006
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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相关型号:
PCF8575TS/1
IC 16 I/O, PIA-GENERAL PURPOSE, PDSO24, 5.30 MM, PLASTIC, MO-150AG, SOT340-1, SSOP-24, Parallel IO Port
NXP
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