PCI1410A_09 [TI]
PC Card Controllers;
| 型号： | PCI1410A_09 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | PC Card Controllers PC |
| 文件： | 总140页 (文件大小：619K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀ ꢁ ꢂꢃ ꢄ ꢃ ꢅꢆ ꢇ ꢈ ꢉ ꢊꢇ ꢇ ꢋꢊ ꢀꢇ ꢌ
ꢀꢁ ꢁ ꢍ ꢎꢏ ꢁ ꢐ ꢑ ꢒꢎꢐ ꢓꢓ ꢔꢎ ꢕ
Data Manual
2000
PCIBus Solutions
SCPS057
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 2000, Texas Instruments Incorporated
Contents
Section
Title
Page
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
1.1
1.2
1.3
1.4
1.5
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
2
3
Terminal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
Feature/Protocol Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
3.1
3.2
3.3
3.4
Power-Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
Clamping Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
Peripheral Component Interconnect (PCI) Interface . . . . . . . . . . . . . . 3–2
3.4.1
3.4.2
PCI Bus Lock (LOCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
Loading Subsystem Identification . . . . . . . . . . . . . . . . . . . . . 3–3
3.5
PC Card Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3
3.5.1
3.5.2
3.5.3
3.5.4
3.5.5
3.5.6
3.5.7
3.5.8
3.5.9
3.5.10
3.5.11
PC Card Insertion/Removal and Recognition . . . . . . . . . . . 3–3
P C Power-Switch Interface (TPS2211) . . . . . . . . . . . . . . . 3–4
2
Zoomed-Video Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5
Ultrazoomed Video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6
Internal Ring Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6
Integrated Pullup Resistors for PC Card Interface . . . . . . . 3–7
SPKROUT and CAUDPWM Usage . . . . . . . . . . . . . . . . . . . 3–7
LED Socket Activity Indicators . . . . . . . . . . . . . . . . . . . . . . . . 3–8
PC Card-16 Distributed DMA Support . . . . . . . . . . . . . . . . . 3–8
PC Card-16 PC/PCI DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10
CardBus Socket Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10
3.6
3.7
Serial Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–11
3.6.1
3.6.2
3.6.3
3.6.4
Serial Bus-Interface Implementation . . . . . . . . . . . . . . . . . . . 3–11
Serial Bus-Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . 3–11
Serial Bus EEPROM Application . . . . . . . . . . . . . . . . . . . . . . 3–13
Accessing Serial Bus Devices Through Software . . . . . . . . 3–14
Programmable Interrupt Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15
3.7.1
3.7.2
3.7.3
3.7.4
PC Card Functional and Card Status Change Interrupts . 3–15
Interrupt Masks and Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–16
Using Parallel IRQ Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 3–17
Using Parallel PCI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 3–18
iii
3.7.5
3.7.6
Using Serialized IRQSER Interrupts . . . . . . . . . . . . . . . . . . . 3–18
SMI Support in the PCI1410A Device . . . . . . . . . . . . . . . . . . 3–18
3.8
Power-Management Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–19
3.8.1
3.8.2
3.8.3
3.8.4
3.8.5
3.8.6
3.8.7
3.8.8
3.8.9
3.8.10
Clock-Run Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–19
CardBus PC Card Power Management . . . . . . . . . . . . . . . . 3–19
16-Bit PC Card Power Management . . . . . . . . . . . . . . . . . . . 3–19
Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–20
Requirements for Suspend Mode . . . . . . . . . . . . . . . . . . . . . 3–21
Ring Indicate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–21
PCI Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–22
CardBus Device Class Power Management . . . . . . . . . . . . 3–23
ACPI Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–23
Master List of PME Context Bits and
Global Reset-Only Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–24
4
PC Card Controller Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2
Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2
Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4
Revision ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5
PCI Class Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5
Cache Line Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5
Latency Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–6
4.10 Header Type Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–6
4.11 BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–6
4.12 CardBus Socket/ExCA Base-Address Register . . . . . . . . . . . . . . . . . . 4–7
4.13 Capability Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–7
4.14 Secondary Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8
4.15 PCI Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9
4.16 CardBus Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9
4.17 Subordinate Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9
4.18 CardBus Latency Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–10
4.19 Memory Base Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–10
4.20 Memory Limit Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–11
4.21 I/O Base Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–11
4.22 I/O Limit Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–12
4.23 Interrupt Line Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–12
4.24 Interrupt Pin Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–13
4.25 Bridge Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–14
4.26 Subsystem Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–15
4.27 Subsystem ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–15
4.28 PC Card 16-Bit I/F Legacy-Mode Base-Address Register . . . . . . . . . 4–15
4.29 System Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–16
iv
4.30 Multifunction Routing Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–19
4.31 Retry Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–20
4.32 Card Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–21
4.33 Device Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–22
4.34 Diagnostic Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–23
4.35 Socket DMA Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–24
4.36 Socket DMA Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–25
4.37 Capability ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–26
4.38 Next-Item Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–26
4.39 Power Management Capabilities Register . . . . . . . . . . . . . . . . . . . . . . 4–27
4.40 Power Management Control/Status Register . . . . . . . . . . . . . . . . . . . . 4–28
4.41 Power Management Control/Status Bridge Support Extensions
Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–29
4.42 Power Management Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–29
4.43 General-Purpose Event Status Register . . . . . . . . . . . . . . . . . . . . . . . . 4–30
4.44 General-Purpose Event Enable Register . . . . . . . . . . . . . . . . . . . . . . . 4–31
4.45 General-Purpose Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–32
4.46 General-Purpose Output Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–33
4.47 Serial Bus Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–33
4.48 Serial Bus Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–34
4.49 Serial Bus Slave Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–34
4.50 Serial Bus Control and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . 4–35
ExCA Compatibility Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1
5
5.1
5.2
5.3
ExCA Identification and Revision Register . . . . . . . . . . . . . . . . . . . . . . 5–4
ExCA Interface Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5
ExCA Power Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–6
5.3.1
5.3.2
Intel 82365SL Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–6
Intel 82365SL-DF Support . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–7
5.4
5.5
5.6
5.7
5.8
5.9
ExCA Interrupt and General Control Register . . . . . . . . . . . . . . . . . . . 5–8
ExCA Card Status-Change Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–9
ExCA Card Status-Change-Interrupt Configuration Register . . . . . . . 5–10
ExCA Address Window Enable Register . . . . . . . . . . . . . . . . . . . . . . . . 5–11
ExCA I/O Window Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–12
ExCA I/O Windows 0 and 1 Start-Address Low-Byte Registers . . . . 5–13
5.10 ExCA I/O Windows 0 and 1 Start-Address High-Byte Registers . . . . 5–13
5.11 ExCA I/O Windows 0 and 1 End-Address Low-Byte Registers . . . . . 5–14
5.12 ExCA I/O Windows 0 and 1 End-Address High-Byte Registers . . . . 5–14
5.13 ExCA Memory Windows 0–4 Start-Address Low-Byte Registers . . . 5–15
5.14 ExCA Memory Windows 0–4 Start-Address High-Byte Registers . . . 5–16
5.15 ExCA Memory Windows 0–4 End-Address Low-Byte Registers . . . . 5–17
5.16 ExCA Memory Windows 0–4 End-Address High-Byte Registers . . . 5–18
5.17 ExCA Memory Windows 0–4 Offset-Address Low-Byte Registers . . 5–19
5.18 ExCA Memory Windows 0–4 Offset-Address High-Byte Registers . 5–20
5.19 ExCA Card Detect and General Control Register . . . . . . . . . . . . . . . . 5–21
v
5.20 ExCA Global Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–22
5.21 ExCA I/O Windows 0 and 1 Offset-Address Low-Byte Registers . . . 5–23
5.22 ExCA I/O Windows 0 and 1 Offset-Address High-Byte Registers . . . 5–23
5.23 ExCA Memory Windows 0–4 Page Register . . . . . . . . . . . . . . . . . . . . 5–24
CardBus Socket Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1
6
7
6.1
6.2
6.3
6.4
6.5
6.6
Socket Event Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2
Socket Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3
Socket Present State Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4
Socket Force Event Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–6
Socket Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7
Socket Power Management Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8
Distributed DMA (DDMA) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–1
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
DMA Current Address/Base Address Register . . . . . . . . . . . . . . . . . . . 7–1
DMA Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–2
DMA Current Count/Base Count Register . . . . . . . . . . . . . . . . . . . . . . . 7–2
DMA Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–3
DMA Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–3
DMA Request Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–4
DMA Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–4
DMA Master Clear Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–5
DMA Multichannel/Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–5
8
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–1
8.1
Absolute Maximum Ratings Over Operating Temperature
Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–1
8.2
8.3
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 8–2
Electrical Characteristics Over Recommended Operating
Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–3
8.4
8.5
8.6
PCI Clock/Reset Timing Requirements Over Recommended
Ranges of Supply Voltage and Operating Free-Air Temperature . . . 8–4
PCI Timing Requirements Over Recommended Ranges of
Supply Voltage and Operating Free-Air Temperature . . . . . . . . . . . . . 8–4
PC Card Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–4
9
Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–1
vi
List of Illustrations
Figure
Title
Page
2–1 PCI-to-CardBus Terminal Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
2–2 PCI-to-PC Card (16-Bit) Terminal Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
2–3 GGU Package Terminal Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
2–4 GHK Package Terminal Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
3–1 PCI1410A Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
3–2 3-State Bidirectional Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
3–3 TPS2211 Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4
3–4 TPS2211 Typical Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5
3–5 Zoomed-Video Implementation Using the PCI1410A Device . . . . . . . . . . . . 3–5
3–6 Zoomed-Video Switching Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6
3–7 Sample Application of SPKROUT and CAUDPWM . . . . . . . . . . . . . . . . . . . . 3–8
3–8 Two Sample LED Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8
3–9 Serial EEPROM Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–11
3–10 Serial Bus Start/Stop Conditions and Bit Transfers . . . . . . . . . . . . . . . . . . . 3–12
3–11 Serial Bus-Protocol Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–12
3–12 Serial Bus Protocol – Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–13
3–13 Serial Bus Protocol – Byte Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–13
3–14 EEPROM Interface Doubleword Data Collection . . . . . . . . . . . . . . . . . . . . . 3–13
3–15 EEPROM Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–14
3–16 IRQ Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–18
3–17 Suspend Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–20
3–18 Signal Diagram of Suspend Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–21
3–19 RI_OUT Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–22
3–20 Block Diagram of a Status/Enable Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–24
5–1 ExCA Register Access Through I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1
5–2 ExCA Register Access Through Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1
6–1 Accessing CardBus Socket Registers Through PCI Memory . . . . . . . . . . . . 6–1
vii
List of Tables
Table
Title
Page
2–1 CardBus and 16-Bit PC Card Signal Names by GGU Terminal Number . . 2–4
2–2 CardBus and 16-Bit PC Card Signal Names by PGE Terminal Number . . . 2–5
2–3 CardBus and 16-Bit PC Card Signal Names by GHK Terminal Number . . . 2–6
2–4 CardBus PC Card Signal Names Sorted Alphabetically to
GGU/PGE/GHK Terminal Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8
2–5 16-Bit PC Card Signal Names Sorted Alphabetically to
GGU/PGE/GHK Terminal Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–10
2–6 Power Supply Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12
2–7 PC Card Power-Switch Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12
2–8 PCI System Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12
2–9 PCI Address and Data Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–13
2–10 PCI Interface Control Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14
2–11 Multifunction and Miscellaneous Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15
2–12 16-Bit PC Card Address and Data Terminals . . . . . . . . . . . . . . . . . . . . . . . . 2–16
2–13 16-Bit PC Card Interface Control Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17
2–14 CardBus PC Card Interface System Terminals . . . . . . . . . . . . . . . . . . . . . . . 2–18
2–15 CardBus PC Card Address and Data Terminals . . . . . . . . . . . . . . . . . . . . . . 2–19
2–16 CardBus PC Card Interface Control Terminals . . . . . . . . . . . . . . . . . . . . . . . 2–20
3–1 PC Card Card-Detect and Voltage-Sense Connections . . . . . . . . . . . . . . . . 3–4
3–2 Distributed DMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9
3–3 PC/PCI Channel Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10
3–4 I/O Addresses Used for PC/PCI DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10
3–5 CardBus Socket Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–11
3–6 Registers and Bits Loadable Through Serial EEPROM . . . . . . . . . . . . . . . . . 3–13
3–7 PCI1410A Registers Used to Program Serial Bus Devices . . . . . . . . . . . . . 3–15
3–8 PC Card Interrupt Events and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–16
3–9 Interrupt Mask and Flag Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–17
3–10 SMI Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–18
3–11 Power-Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–23
4–1 PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
4–2 Bit-Field Access Tag Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2
4–3 Command Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3
4–4 Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4
4–5 Secondary Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8
4–6 Bridge Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–14
4–7 System Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–17
4–8 Multifunction Routing Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–19
4–9 Retry Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–20
viii
4–10 Card Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–21
4–11 Device Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–22
4–12 Diagnostic Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–23
4–13 Socket DMA Register 0 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–24
4–14 Socket DMA Register 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–25
4–15 Power Management Capabilities Register Description . . . . . . . . . . . . . . . . 4–27
4–16 Power Management Control/Status Register Description . . . . . . . . . . . . . . 4–28
4–17 Power Management Control/Status Bridge Support
Extensions Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–29
4–18 General-Purpose Event Status Register Description . . . . . . . . . . . . . . . . . . 4–30
4–19 General-Purpose Event Enable Register Description . . . . . . . . . . . . . . . . . 4–31
4–20 General-Purpose Input Register Description . . . . . . . . . . . . . . . . . . . . . . . . . 4–32
4–21 General-Purpose Output Register Description . . . . . . . . . . . . . . . . . . . . . . . 4–33
4–22 Serial Bus Data Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–33
4–23 Serial Bus Index Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–34
4–24 Serial Bus Slave Address Register Description . . . . . . . . . . . . . . . . . . . . . . 4–34
4–25 Serial Bus Control and Status Register Description . . . . . . . . . . . . . . . . . . . 4–35
5–1 ExCA Registers and Offsets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2
5–2 ExCA Identification and Revision Register Description . . . . . . . . . . . . . . . . . 5–4
5–3 ExCA Interface Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5
5–4 ExCA Power Control Register 82365SL Support Description . . . . . . . . . . . . 5–6
5–5 ExCA Power Control Register 82365SL-DF Support Description . . . . . . . . 5–7
5–6 ExCA Interrupt and General Control Register Description . . . . . . . . . . . . . . 5–8
5–7 ExCA Card Status-Change Register Description . . . . . . . . . . . . . . . . . . . . . . 5–9
5–8 ExCA Card Status-Change-Interrupt Configuration Register Description . . 5–10
5–9 ExCA Address Window Enable Register Description . . . . . . . . . . . . . . . . . . . 5–11
5–10 ExCA I/O Window Control Register Description . . . . . . . . . . . . . . . . . . . . . . 5–12
5–11 ExCA Memory Windows 0–4 Start-Address High-Byte Registers
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–16
5–12 ExCA Memory Windows 0–4 End-Address High-Byte Registers
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–18
5–13 ExCA Memory Windows 0–4 Offset-Address High-Byte Registers
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–20
5–14 ExCA Card Detect and General Control Register Description . . . . . . . . . . 5–21
5–15 ExCA Global Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . 5–22
6–1 CardBus Socket Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1
6–2 Socket Event Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2
6–3 Socket Mask Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3
6–4 Socket Present State Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4
6–5 Socket Force Event Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–6
6–6 Socket Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7
6–7 Socket Power Management Register Description . . . . . . . . . . . . . . . . . . . . . 6–8
ix
7–1 Distributed DMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–1
7–2 DMA Command Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–3
7–3 DMA Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–3
7–4 DMA Mode Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–4
7–5 DMA Multichannel/Mask Register Description . . . . . . . . . . . . . . . . . . . . . . . . 7–5
8–1 PC Card Address Setup Time, t
, 8-Bit and 16-Bit PCI Cycles . . . . . . . 8–4
su(A)
8–2 PC Card Command Active Cycle Time, t
8–3 PC Card Command Active Cycle Time, t
, 8-Bit PCI Cycles . . . . . . . . . . 8–5
, 16-Bit PCI Cycles . . . . . . . . . 8–5
c(A)
c(A)
8–4 PC Card Address Hold Time, t
, 8-Bit and 16-Bit PCI Cycles . . . . . . . . . 8–5
h(A)
x
1 Introduction
1.1 Description
The TI PCI1410A device is a high-performance PCI-to-PC Card controller that supports a single PC Card socket
compliant with the PC Card Standard. The PCI1410A device provides features that make it the best choice for
bridging between PCI and PC Cards in both notebook and desktop computers. The PC Card Standard retains the
16-bit PC Card specification defined in PCI Local Bus Specification and defines the new 32-bit PC Card, CardBus,
as being capable of full 32-bit data transfers at 33 MHz. The PCI1410A device supports both 16-bit and CardBus PC
Cards, powered at 5 V or 3.3 V, as required.
The PCI1410A device is compliant with the PCI Local Bus Specification, and its PCI interface can act as either a PCI
master device or a PCI slave device. The PCI bus mastering is initiated during 16-bit PC Card DMA transfers or
CardBus PC Card bridging transactions. The PCI1410A device also is compliant with the latest PCI Bus Power
Management Interface Specification and PCI Bus Power Management Interface Specification for PCI to CardBus
Bridges.
All card signals are buffered internally to allow hot insertion and removal without external buffering. The PCI1410A
device is register-compatible with the Intel 82365SL-DF and 82365SL ExCA controllers. The PCI1410A internal
data-path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum
performance. Independent buffering and a pipeline architecture provide an unsurpassed performance level with
sustained bursting. The PCI1410A device also can be programmed to accept fast-posted writes to improve
system-bus utilization.
Multiple system-interrupt signaling options are provided, including: parallel PCI, parallel ISA, serialized ISA, and
serialized PCI. Furthermore, general-purpose inputs and outputs are provided for the board designer to implement
sideband functions. Many other features designed into the PCI1410A device, such as socket-activity light-emitting
diode (LED) outputs, are discussed in detail throughout the design specification.
An advanced complementary metal-oxide semiconductor (CMOS) process achieves low system power
consumption, while operating at PCI clock rates up to 33 MHz. Several low-power modes enable the host power
management system to further reduce power consumption.
1.2 Features
The PCI1410A device supports the following features:
•
•
•
Ability to wake from D3
and D3
hot cold
Full compatiblity with the Intel 430TX (Mobile Triton II) chipset
A 144-terminal low-profile QFP (PGE), 144-terminal MicroStar BGA ball grid array (GGU) package, or
209-terminal MicroStar BGA (GHK) package
•
•
•
•
•
3.3-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments
Mix-and-match 5-V/3.3-V 16-bit PC Cards and 3.3-V CardBus Cards
Single PC Card or CardBus slot with hot insertion and removal
Burst transfers to maximize data throughput on the PCI bus and the CardBus bus
Parallel PCI interrupts, parallel ISA IRQ and parallel PCI interrupts, serial ISA IRQ with parallel PCI
interrupts, and serial ISA IRQ and PCI interrupts
•
•
Serial EEPROM interface for loading subsystem ID and subsystem vendor ID
Pipelined architecture allows greater than 130 Mbit/s sustained throughput from CardBus to PCI and from
PCI to CardBus
1–1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Interface to parallel single-slot PC Card power-switch interfaces like the TI TPS2211 device
Up to five general-purpose I/Os
Programmable output select for CLKRUN
Five PCI memory windows and two I/O windows available to the 16-bit PC Card socket
Two I/O windows and two memory windows available to the CardBus socket
Exchangeable card architecture (ExCA) compatible registers are mapped in memory and I/O space
Compatibility with Intel 82365SL-DF and 82365SL registers
Distributed DMA (DDMA) and PC/PCI DMA
16-bit DMA on the PC Card socket
Ring indicate, SUSPEND, PCI CLKRUN, and CardBus CCLKRUN
Socket-activity LED pins
PCI bus lock (LOCK)
Advanced submicron, low-power CMOS technology
Internal ring oscillator
1.3 Related Documents
•
•
•
•
•
•
•
•
•
•
Advanced Configuration and Power Interface (ACPI) Specification (Revision 2.0)
PCI Bus Power Management Interface Specification (Revision 1.1)
PCI Bus Power Management Interface Specification for PCI to CardBus Bridges (Revision 0.6)
PCI Local Bus Specification (Revision 2.2)
PCI Mobile Design Guide (Revision 1.0)
PCI14xx Implementation Guide for D3 Wake-Up
PC Card Standard, Release 7
PC 98
PC 99
Serialized IRQ Support for PCI Systems (Revision 6)
1.4 Trademarks
MicroStar BGA and TI are trademarks of Texas Instruments.
Intel is a trademark of Intel Corporation.
Maxim is a trademark of Maxim Integrated Products, Inc.
Other trademarks are the property of their respective owners.
1.5 Ordering Information
ORDERING NUMBER
PCI1410A
NAME
VOLTAGE
PACKAGE
144-terminal LQFP
PC Card controller
3.3-V, 5-V tolerant I/Os
144-terminal PBGA
209-terminal PBGA
1–2
2 Terminal Descriptions
The PCI1410A device is packaged in either a 144-terminal GGU MicroStar BGA or a 144-terminal PGE package.
It also is packaged in a 209-terminal GHK MicroStar BGA that is pin-compatible with the TI PCI4410A device. The
PCI4410A device is a single-socket CardBus bridge with integrated OHCI link. Figure 2–1 is a PGE-package terminal
diagram showing PCI-to-CardBus signal names. Figure 2–2 is a PGE-package terminal diagram showing PCI-to-PC
Card signal names. Figure 2–3 and Figure 2–4 are terminal diagrams for the GGU and GHK packages, respectively.
PGE LOW-PROFILE QUAD FLAT PACKAGE
(TOP VIEW)
VPPD1
VPPD0
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
CTRDY
CIRDY
CFRAME
CC/BE2
CAD17
GND
CAD18
CAD19
CVS2
109
110
111
112
113
114
SUSPEND
MFUNC6
MFUNC5
MFUNC4
GRST
115
116
MFUNC3
MFUNC2
117
118
CAD20
V
CCI
119
120
121
122
SPKROUT
MFUNC1
MFUNC0
RI_OUT/PME
GND
CRST
CAD21
CAD22
V
CC
123
124
CREQ
CAD23
CC/BE3
AD0
AD1
AD2
AD3
AD4
AD5
AD6
125
126
V
CCCB
CAD24
CAD25
CAD26
GND
CVS1
CINT
127
128
129
130
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
V
AD7
131
132
CC
133
134
CSERR
CAUDIO
CSTSCHG
C/BE0
AD8
AD9
135
136
137
138
AD10
CCLKRUN
CCD2
V
CCP
V
AD11
GND
CC
139
140
CAD27
CAD28
CAD29
CAD30
CRSVD
CAD31
AD12
AD13
AD14
AD15
C/BE1
141
142
143
144
Figure 2–1. PCI-to-CardBus Terminal Diagram
2–1
PGE LOW-PROFILE QUAD FLAT PACKAGE
(TOP VIEW)
VPPD1
VPPD0
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
ADDR22
109
110
ADDR15
ADDR23
ADDR12
ADDR24
GND
ADDR7
ADDR25
VS2
111
112
113
114
SUSPEND
MFUNC6
MFUNC5
MFUNC4
GRST
115
116
MFUNC3
MFUNC2
117
118
V
ADDR6
CCI
119
120
121
122
SPKROUT
MFUNC1
MFUNC0
RI_OUT/PME
GND
RESET
ADDR5
ADDR4
V
CC
123
124
INPACK
ADDR3
REG
AD0
AD1
AD2
AD3
AD4
AD5
AD6
125
126
V
CCCB
127
128
129
130
ADDR2
ADDR1
ADDR0
GND
VS1
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
V
AD7
131
132
CC
READY(IREQ)
WAIT
BVD2(SPKR)
133
134
C/BE0
AD8
AD9
BVD1(STSCHG/RI)
WP(IOIS16)
CD2
135
136
137
138
AD10
V
CCP
V
AD11
GND
CC
139
140
DATA0
DATA8
DATA1
DATA9
DATA2
DATA10
AD12
AD13
AD14
AD15
C/BE1
141
142
143
144
Figure 2–2. PCI-to-PC Card (16-Bit) Terminal Diagram
2–2
N
M
L
K
J
H
G
F
E
D
C
B
A
1
2 3 4 5 6 7 8 9 10 11 12 13
Figure 2–3. GGU Package Terminal Diagram
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
3
5
7
9
11 13 15 17 19
10 12 14 16 18
2
4
6
8
Figure 2–4. GHK Package Terminal Diagram
Table 2–1 shows the terminal assignments for the 144-terminal GGU CardBus and 16-bit PC Card signal names.
Table 2–2 shows the terminal assignments for the 144-terminal PGE CardBus and 16-bit PC Card signal names.
Table 2–3 shows the terminal assignments for the 209-terminal GHK CardBus and 16-bit PC Card signal names.
Table 2–4 shows the CardBus PC Card signal names, sorted alphabetically to the GGU/PGE/GHK terminal numbers.
Table 2–5 shows the 16-bit PC Card signal names, sorted alphabetically to the GGU/PGE/GHK terminal numbers.
2–3
Table 2–1. CardBus and 16-Bit PC Card Signal Names by GGU Terminal Number
SIGNAL NAME
CARD
BUS
REQ
SIGNAL NAME
CARD
SIGNAL NAME
SIGNAL NAME
CARD
BUS
GND
AD9
TERM.
NO.
TERM.
NO.
TERM.
NO.
TERM.
NO.
CARD
16-BIT
BUS
16-BIT
16-BIT
16-BIT
BUS
A1
A2
A3
A4
REQ
C11
C12
C13
D1
CGNT
WE
G10
G11
G12
G13
CAD11
CAD10
CAD9
OE
L4
L5
L6
L7
GND
AD9
DATA2
DATA8
CD2
CRSVD
CAD28
CCD2
CSTOP
CPERR
AD27
ADDR20
ADDR14
AD27
CE2
ADDR10
V
CC
V
CC
V
V
AD2
AD2
CCCB
CCCB
RI_OUT/
PME
RI_OUT/
PME
WAIT
A5
CSERR
CAD26
D2
AD28
AD28
H1
PCLK
PCLK
L8
ADDR0
A6
A7
D3
D4
GND
GND
H2
H3
GND
GND
L9
V
V
CCI
MFUNC4
CCI
MFUNC4
V
V
AD29
AD29
AD19
AD19
L10
CCCB
CCCB
WP
(IOIS16)
ADDR3
ADDR5
A8
A9
CAD23
CAD21
D5
D6
CCLKRUN
CINT
H4
AD18
CAD7
AD18
L11
L12
SUSPEND SUSPEND
READY
(IREQ)
H10
DATA7
CCD1
CD1
ADDR25
ADDR12
ADDR15
ADDR22
GNT
A10
A11
A12
A13
B1
CAD19
CC/BE2
CIRDY
CTRDY
GNT
D7
D8
CAD25
CAD22
CVS2
ADDR1
ADDR4
VS2
H11
H12
H13
J1
V
V
L13
M1
M2
M3
M4
M5
M6
M7
CAD0
SERR
PAR
DATA3
SERR
PAR
CC
CC
CAD8
CC/BE0
AD17
DATA15
CE1
D9
D10
D11
D12
D13
E1
CAD17
CBLOCK
ADDR24
ADDR19
AD17
AD14
AD11
AD8
AD14
AD11
AD8
J2
AD16
AD16
DATA10
DATA1
B2
CAD31
CAD29
V
CC
V
CC
J3
C/BE2
FRAME
CAD3
C/BE2
FRAME
DATA5
B3
CPAR
C/BE3
ADDR13
C/BE3
J4
AD6
AD6
V
CC
B4
V
CC
J10
AD4
AD4
BVD2
(SPKR)
B5
CAUDIO
E2
AD24
AD24
J11
CAD6
DATA13
M8
GND
GND
GND
B6
B7
GND
E3
E4
AD25
AD25
J12
J13
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
CAD5
CRSVD
IRDY
DATA6
DATA14
IRDY
M9
M10
M11
M12
M13
N1
SPKROUT SPKROUT
REG
CC/BE3
CREQ
CRST
AD26
AD26
GRST
GRST
INPACK
RESET
ADDR7
ADDR23
ADDR16
ADDR21
AD30
B8
E10
E11
E12
E13
F1
CRSVD
CC/BE1
CAD16
CAD14
AD22
ADDR18
ADDR8
ADDR17
ADDR9
AD22
MFUNC6
VPPD1
VCCD1
C/BE1
AD15
MFUNC6
VPPD1
VCCD1
C/BE1
AD15
B9
V
CC
V
CC
B10
B11
B12
B13
C1
CAD18
CFRAME
CCLK
TRDY
AD12
AD10
AD7
TRDY
AD12
AD10
AD7
N2
CDEVSEL
AD30
F2
AD23
AD23
N3
AD13
AD13
F3
V
CC
V
CC
AD1
AD1
N4
V
CCP
V
CCP
AD31
C2
AD31
F4
IDSEL
CAD15
CAD12
IDSEL
IOWR
MFUNC0 MFUNC0
MFUNC2 MFUNC2
N5
C/BE0
AD5
C/BE0
AD5
DATA9
DATA0
C3
CAD30
CAD27
F10
F11
N6
C4
ADDR11
CAD2
GND
DATA11
GND
N7
AD3
AD3
BVD1
(STSCHG/RI)
C5
CSTSCHG
F12
GND
GND
K11
N8
AD0
AD0
VS1
C6
C7
CVS1
F13
G1
G2
G3
G4
CAD13
IORD
K12
K13
L1
CAD1
CAD4
DATA4
N9
MFUNC1
MFUNC3
MFUNC5
VPPD0
MFUNC1
MFUNC3
MFUNC5
VPPD0
ADDR2
CAD24
V
CCP
V
CCP
DATA12
N10
N11
N12
N13
V
CC
C8
V
CC
AD21
AD20
PRST
AD21
AD20
PRST
DEVSEL DEVSEL
ADDR6
GND
C9
CAD20
GND
L2
STOP
PERR
STOP
PERR
C10
L3
VCCD0
VCCD0
2–4
Table 2–2. CardBus and 16-Bit PC Card Signal Names by PGE Terminal Number
SIGNAL NAME
SIGNAL NAME
CARD
BUS
C/BE1
SIGNAL NAME
CARD
SIGNAL NAME
TERM
NO.
TERM
NO.
TERM
NO.
TERM
NO.
CARD
16-BIT
BUS
CARD
16-BIT
16-BIT
16-BIT
BUS
VCCD0
VCCD1
CCD1
CAD0
CAD2
GND
BUS
CTRDY
CIRDY
CFRAME
CC/BE2
CAD17
GND
1
2
REQ
REQ
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
C/BE1
AD15
AD14
AD13
AD12
GND
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
VCCD0
VCCD1
CD1
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
ADDR22
ADDR15
ADDR23
ADDR12
ADDR24
GND
GNT
GNT
AD15
AD14
AD13
AD12
GND
AD11
3
AD31
AD30
AD29
GND
AD31
AD30
AD29
GND
4
DATA3
DATA11
GND
5
6
7
AD28
AD27
AD26
AD25
AD24
C/BE3
IDSEL
AD28
AD27
AD26
AD25
AD24
C/BE3
IDSEL
AD11
CAD1
CAD4
CAD3
CAD6
CAD5
CRSVD
CAD7
DATA4
DATA12
DATA5
DATA13
DATA6
DATA14
DATA7
CAD18
CAD19
CVS2
ADDR7
ADDR25
VS2
8
V
CCP
V
CCP
9
AD10
AD9
AD10
AD9
10
11
12
13
14
15
16
17
18
19
20
21
22
CAD20
CRST
ADDR6
RESET
ADDR5
ADDR4
AD8
AD8
C/BE0
AD7
C/BE0
AD7
CAD21
CAD22
V
V
CC
V
CC
V
CC
V
V
CC
V
V
CC
CC
CC
CC
AD23
AD22
AD21
AD23
AD22
AD21
AD6
AD5
AD4
AD3
AD2
AD1
AD0
GND
AD6
AD5
AD4
AD3
AD2
AD1
AD0
GND
CAD8
DATA15
CE1
CREQ
INPACK
ADDR3
REG
CC/BE0
CAD9
CAD23
CC/BE3
ADDR10
V
V
CCP
V
V
V
V
CCCB
CCP
CCCB
CCCB
CCCB
AD20
PRST
PCLK
GND
AD20
PRST
PCLK
GND
CAD10
CAD11
CAD13
GND
CE2
OE
CAD24
CAD25
CAD26
GND
ADDR2
ADDR1
ADDR0
GND
IORD
GND
RI_OUT/
PME
RI_OUT/
PME
23
AD19
AD19
59
95
CAD12
ADDR11
131
CVS1
VS1
READY
(IREQ)
24
25
26
AD18
AD17
AD16
AD18
AD17
AD16
60
61
62
MFUNC0
MFUNC1
MFUNC0
MFUNC1
96
97
98
CAD15
CAD14
CAD16
IOWR
132
133
134
CINT
ADDR9
ADDR17
CSERR
CAUDIO
WAIT
BVD2
(SPKR)
SPKROUT SPKROUT
BVD1
(STSCHG/RI)
27
C/BE2
C/BE2
63
V
CCI
V
CCI
99
CC/BE1
ADDR8
135
CSTSCHG
28
29
30
31
32
33
34
35
36
FRAME FRAME
IRDY IRDY
64
65
66
67
68
69
70
71
72
MFUNC2
MFUNC3
GRST
MFUNC2
MFUNC3
GRST
100
101
102
103
104
105
106
107
108
CRSVD
CPAR
ADDR18
ADDR13
136
137
138
139
140
141
142
143
144
CCLKRUN WP (IOIS16)
CCD2 CD2
V
V
V
CC
V
CC
V
CC
V
CC
CC
TRDY
DEVSEL DEVSEL
CC
TRDY
MFUNC4
MFUNC5
MFUNC6
MFUNC4
MFUNC5
MFUNC6
CBLOCK
CPERR
CSTOP
CGNT
ADDR19
ADDR14
ADDR20
WE
CAD27
CAD28
CAD29
CAD30
CRSVD
CAD31
DATA0
DATA8
DATA1
DATA9
DATA2
DATA10
STOP
PERR
SERR
PAR
STOP
PERR
SERR
PAR
SUSPEND SUSPEND
VPPD0
VPPD1
VPPD0
VPPD1
CDEVSEL ADDR21
CCLK ADDR16
2–5
Table 2–3. CardBus and 16-Bit PC Card Signal Names by GHK Terminal Number
SIGNAL NAME
CARDBUS 16-BIT
SIGNAL NAME
CARDBUS 16-BIT
SIGNAL NAME
CARDBUS 16-BIT
TERM
NO.
TERM
NO.
TERM
NO.
A4
A5
NC
NC
E9
E10
E11
E12
E13
E14
E17
E18
E19
F1
CAD29
CSTSCHG
GND
DATA1
BVD1(STSCHG/RI)
GND
H17
H18
H19
J1
CAD11
CAD10
OE
NC
NC
CE2
A6
NC
NC
V
V
CCCB
CCCB
A7
NC
NC
CREQ
CVS2
CFRAME
CDEVSEL
CSTOP
CBLOCK
NC
INPACK
VS2
AD31
AD30
AD29
GND
AD31
AD30
AD29
GND
A8
CAD30
CCD2
CINT
CAD24
DATA9
CD2
J2
A9
ADDR23
ADDR21
ADDR20
ADDR19
NC
J3
A10
A11
A12
A13
A14
A15
A16
B5
READY(IREQ)
ADDR2
J5
J6
AD28
CC/BE0
CAD9
CAD8
AD28
CE1
V
V
V
V
J14
J15
J17
J18
J19
K1
CCCB
CCCB
ADDR10
DATA15
CC
CC
CAD20
GND
CTRDY
NC
ADDR6
GND
ADDR22
NC
F2
NC
NC
F3
NC
NC
V
CC
V
CC
F5
NC
NC
CAD7
AD27
AD26
AD25
AD24
C/BE3
CRSVD
CAD5
CAD6
CAD3
CAD4
IDSEL
DATA7
AD27
F6
NC
NC
B6
NC
NC
F7
NC
NC
K2
AD26
B7
NC
NC
F8
NC
NC
K3
AD25
B8
CRSVD
DATA2
F9
CAD28
CCLKRUN
CVS1
CRST
CC/BE2
CPERR
CGNT
DATA8
WP(IOIS16)
VS1
K5
AD24
B9
V
CC
V
CC
F10
F11
F12
F13
F14
F15
F17
F18
F19
G1
K6
C/BE3
DATA14
DATA6
DATA13
DATA5
DATA12
IDSEL
B10
B11
B12
B13
B14
B15
C5
CSERR
CAD25
CC/BE3
CAD22
CAD19
CAD17
NC
WAIT
K14
K15
K17
K18
K19
L1
ADDR1
REG
RESET
ADDR12
ADDR14
WE
ADDR4
ADDR25
ADDR24
NC
V
CC
V
CC
CRSVD
CC/BE1
NC
ADDR18
ADDR8
NC
L2
V
CC
V
CC
C6
NC
NC
L3
AD23
AD21
AD22
CAD1
GND
AD23
AD21
AD22
DATA4
GND
C7
NC
NC
L5
C8
CAD31
CAD27
CAUDIO
CAD26
CAD23
CAD21
CAD18
CIRDY
NC
DATA10
DATA0
BVD2(SPKR)
ADDR0
ADDR3
ADDR5
ADDR7
ADDR15
NC
G2
NC
NC
L6
C9
G3
NC
NC
L14
L15
L17
L18
L19
M1
M2
M3
M5
M6
C10
C11
C12
C13
C14
C15
D1
G5
NC
NC
G6
NC
NC
CAD2
CAD0
CCD1
DATA11
DATA3
CD1
G14 CAD16
G15 CPAR
G17 CAD14
G18 CAD15
G19 CAD12
ADDR17
ADDR13
ADDR9
IOWR
ADDR11
GNT
V
CCP
V
CCP
AD20
PRST
GND
AD20
PRST
GND
PCLK
NC
D19
E1
CCLK
NC
ADDR16
NC
H1
H2
GNT
REQ
NC
REQ
PCLK
E2
NC
NC
H3
NC
M14 NC
E3
NC
NC
H5
NC
NC
M15 NC
NC
E6
NC
NC
H6
NC
NC
M17 NC
NC
E7
NC
NC
H14
H15
CAD13
GND
IORD
GND
M18 VCCD0
M19 VCCD1
VCCD0
VCCD1
E8
NC
NC
2–6
Table 2–3. CardBus and 16-Bit PC Card Signal Names by GHK Terminal Number (Continued)
SIGNAL NAME
CARDBUS 16-BIT
SIGNAL NAME
CARDBUS 16-BIT
SIGNAL NAME
CARDBUS 16-BIT
TERM.
NO.
TERM.
NO.
TERM.
NO.
N1
N2
AD19
AD18
AD17
IRDY
AD16
NC
AD19
AD18
AD17
IRDY
AD16
NC
R1
R2
TRDY
STOP
SERR
AD14
AD10
AD6
TRDY
STOP
SERR
AD14
AD10
AD6
U15
V5
NC
NC
AD12
AD12
N3
R3
V6
V
CCP
V
CCP
N5
R6
V7
AD7
AD7
N6
R7
V8
AD4
AD4
N14
N15
N17
N18
N19
P1
R8
V9
AD1
AD1
NC
NC
R9
GND
GND
V10
V11
V12
V13
V14
V15
W4
MFUNC1
GRST
VPPD0
NC
MFUNC1
GRST
VPPD0
NC
NC
NC
R10
R11
R12
R13
R14
R17
R18
R19
T1
V
CCI
V
CCI
NC
NC
MFUNC6
NC
MFUNC6
NC
NC
NC
C/BE2
FRAME
C/BE2
FRAME
NC
NC
NC
NC
P2
NC
NC
NC
NC
P3
V
CC
V
CC
NC
NC
C/BE1
GND
AD9
C/BE1
GND
AD9
P5
PERR
DEVSEL
AD13
AD8
PERR
DEVSEL
AD13
AD8
NC
NC
W5
P6
NC
NC
W6
P7
PAR
PAR
W7
V
CC
V
CC
P8
T19
U5
NC
NC
W8
AD3
AD3
P9
RI_OUT/PME
MFUNC2
MFUNC5
NC
RI_OUT/PME
MFUNC2
MFUNC5
NC
AD15
AD11
C/BE0
AD5
AD15
AD11
C/BE0
AD5
W9
AD2
AD2
P10
P11
P12
P13
P14
P15
P17
P18
P19
U6
W10
W11
W12
W13
W14
W15
W16
MFUNC0
MFUNC3
SUSPEND
NC
MFUNC0
MFUNC3
SUSPEND
NC
U7
U8
NC
NC
U9
AD0
AD0
NC
NC
U10
U11
U12
U13
U14
SPKROUT
MFUNC4
VPPD1
NC
SPKROUT
MFUNC4
VPPD1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
2–7
Table 2–4. CardBus PC Card Signal Names Sorted Alphabetically to GGU/PGE/GHK Terminal Number
TERM. NO.
PGE
57
56
55
54
53
52
51
49
47
46
45
43
41
40
39
38
26
25
24
23
19
17
16
15
11
TERM. NO.
PGE
92
TERM. NO.
PGE
119
143
100
84
SIGNAL
NAME
SIGNAL
NAME
SIGNAL NAME
GGU
N8
K7
GHK
U9
V9
GGU
G10
F11
F13
E13
F10
E12
D10
B10
A10
C9
GHK
H17
G19
H14
G17
G18
G14
B15
C14
B14
A14
C13
B13
C12
A11
B11
C11
C9
GGU
B9
GHK
F12
B8
AD0
CAD11
CRST
AD1
CAD12
CAD13
CAD14
CAD15
CAD16
CAD17
CAD18
CAD19
CAD20
CAD21
CAD22
CAD23
CAD24
CAD25
CAD26
CAD27
CAD28
CAD29
CAD30
CAD31
CAUDIO
C/BE0
95
CRSVD
CRSVD
CRSVD
CSERR
CSTOP
CSTSCHG
CTRDY
CVS1
A2
AD2
L7
W9
W8
V8
93
E10
J13
A5
F18
K14
B10
E18
E10
A16
F11
E13
P6
AD3
N7
M7
N6
M6
K6
97
AD4
96
133
105
135
109
131
117
32
AD5
U8
R8
V7
98
C12
C5
AD6
113
115
116
118
120
121
124
127
128
129
139
140
141
142
144
134
48
AD7
A13
C6
AD8
M5
L5
P8
AD9
W6
R7
U6
V5
CVS2
D9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
CAD0
CAD1
CAD2
CAD3
CAD4
CAD5
CAD6
CAD7
CAD8
CAD9
CAD10
K5
A9
DEVSEL
FRAME
GND
L1
M4
K4
D8
J4
28
P2
A8
D3
6
A15
E11
H15
J5
N3
M3
N2
J2
P7
C7
GND
H2
22
R6
U5
N6
N3
N2
N1
M2
L5
D7
GND
L4
42
A6
GND
M8
K11
F12
C10
B6
58
C4
GND
78
L15
M5
J1
A3
F9
GND
94
H4
H3
G3
G2
F1
B3
E9
GND
114
130
2
R9
C3
A8
GND
W5
H1
B2
C8
GNT
B1
B5
C10
U7
GRST
M10
F4
66
V11
L1
L6
N5
IDSEL
13
F2
L3
C/BE1
N1
37
W4
IRDY
K1
29
N5
E2
K5
C/BE2
J3
27
P1
MFUNC0
MFUNC1
MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6
PAR
K8
60
W10
V10
P10
W11
U11
P11
R11
T1
E3
10
9
K3
C/BE3
E1
12
K6
N9
61
E4
K2
CBLOCK
CC/BE0
CC/BE1
CC/BE2
CC/BE3
CCD1
D11
H13
E11
A11
B7
103
88
E19
J14
F19
F13
B12
L19
A9
K9
64
D1
D2
D4
C1
C2
L13
K12
K10
J10
K13
J12
J11
H10
H12
G12
G11
8
K1
N10
L10
N11
M11
M2
H1
65
7
J6
99
67
5
J3
112
125
75
68
4
J2
69
3
J1
L12
A4
36
76
79
77
81
80
83
82
85
87
89
91
L18
L14
L17
K18
K19
K15
K17
J19
J17
J15
H18
CCD2
137
108
136
107
111
106
132
110
101
104
123
PCLK
21
M6
CCLK
B12
D5
D19
F10
E17
E14
F15
A10
C15
G15
F14
E12
PERR
L3
34
P5
CCLKRUN
CDEVSEL
CFRAME
CGNT
PRST
G4
A1
20
M3
B13
B11
C11
D6
REQ
1
H2
RI_OUT/PME
SERR
L8
59
P9
M1
M9
L2
35
R3
CINT
SPKROUT
STOP
62
U10
R2
CIRDY
CPAR
A12
D13
C13
B8
33
SUSPEND
TRDY
L11
K3
70
W12
R1
CPERR
CREQ
31
V
F3
14
A13
CC
2–8
Table 2–4. CardBus PC Card Signal Names Sorted Alphabetically to GGU/PGE/GHK
Terminal Number (Continued)
TERM. NO.
TERM. NO.
TERM. NO.
SIGNAL
NAME
SIGNAL
NAME
SIGNAL NAME
GGU
K2
PGE
30
GHK
B9
GGU
B4
PGE
138
90
GHK
W7
GGU
L9
PGE
63
GHK
R10
M1
V
CC
V
CC
V
CC
V
CC
V
CC
V
V
V
V
V
V
CC
CCI
L6
50
F17
J18
L2
G13
A7
A12
H19
M18
M19
G1
18
CCCB
CCCB
CCP
CCP
H11
D12
C8
86
126
73
N4
44
V6
102
122
VCCD0
VCCD1
N13
M13
VPPD0
VPPD1
N12
M12
71
V12
U12
P3
74
72
2–9
Table 2–5. 16-Bit PC Card Signal Names Sorted Alphabetically to GGU/PGE/GHK Terminal Number
TERM. NO.
GGU PGE
TERM. NO.
GGU PGE
TERM. NO.
GGU PGE
SIGNAL NAME
SIGNAL NAME
SIGNAL NAME
GHK
U9
V9
GHK
G19
F13
G15
F14
C15
D19
G14
F18
E19
E18
E17
A16
E14
B15
B14
E10
C10
U7
GHK
A15
E11
H15
J5
AD0
N8
K7
L7
57
56
55
54
53
52
51
49
47
46
45
43
41
40
39
38
26
25
24
23
19
17
16
15
11
10
9
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
ADDR16
ADDR17
ADDR18
ADDR19
ADDR20
ADDR21
ADDR22
ADDR23
ADDR24
ADDR25
BVD1(STSCHG/RI)
BVD2(SPKR)
C/BE0
F11
A11
D13
C13
A12
B12
E12
E10
D11
C12
B13
A13
B11
D10
A10
C5
95
112
101
104
110
108
98
GND
D3
H2
6
22
42
58
78
94
114
130
2
AD1
GND
AD2
W9
W8
V8
GND
L4
AD3
N7
M7
N6
M6
K6
M5
L5
GND
M8
K11
F12
C10
B6
AD4
GND
L15
M5
AD5
U8
R8
V7
GND
AD6
GND
R9
AD7
100
103
105
107
109
111
113
116
135
134
48
GND
W5
H1
AD8
P8
GNT
B1
AD9
W6
R7
U6
V5
GRST
M10
F4
66
13
123
93
96
29
60
61
64
65
67
68
69
92
36
21
34
20
132
125
1
V11
L1
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
ADDR10
K5
M4
K4
N3
M3
N2
J2
IDSEL
INPACK
IORD
B8
E12
H14
G18
N5
F13
F10
K1
P7
IOWR
R6
U5
N6
N3
N2
N1
M2
L5
IRDY
MFUNC0
MFUNC1
MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6
OE
K8
W10
V10
P10
W11
U11
P11
R11
H17
T1
B5
N9
J1
N5
K9
H4
H3
G3
G2
F1
C/BE1
N1
37
W4
P1
N10
L10
N11
M11
G10
M2
H1
C/BE2
J3
27
C/BE3
E1
12
K6
CD1
L12
A4
75
L19
A9
L6
CD2
137
88
F2
L3
CE1
H13
G11
C4
J14
H18
C9
PAR
E2
E3
E4
D1
D2
D4
C1
C2
A6
D7
C7
A8
D8
A9
C9
B10
E11
E13
G12
K5
CE2
91
PCLK
M6
K3
DATA0
139
141
143
76
PERR
L3
P5
K2
DATA1
B3
E9
PRST
G4
D6
M3
8
K1
DATA2
A2
B8
READY(IREQ)
REG
A10
B12
H2
7
J6
DATA3
L13
K12
J10
J12
H10
A3
L18
L14
K18
K15
J19
F9
B7
5
J3
DATA4
79
REQ
A1
4
J2
DATA5
81
RESET
RI_OUT/PME
SERR
B9
119
59
35
62
33
70
31
14
30
50
86
102
122
F12
P9
3
J1
DATA6
83
L8
129
128
127
124
121
120
118
115
99
97
89
C11
B11
A11
C12
B13
C13
A14
C14
F19
G17
J15
DATA7
85
M1
M9
L2
R3
DATA8
140
142
144
77
SPKROUT
STOP
U10
R2
DATA9
C3
A8
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
DEVSEL
FRAME
B2
C8
SUSPEND
TRDY
L11
K3
W12
R1
K10
K13
J11
J13
H12
L1
L17
K19
K17
K14
J17
P6
80
V
V
V
V
V
V
F3
A13
B9
CC
CC
CC
CC
CC
CC
82
K2
84
L6
F17
J18
L2
87
H11
D12
C8
32
J4
28
P2
P3
2–10
Table 2–5. 16-Bit PC Card Signal Names Sorted Alphabetically to GGU/PGE/GHK
Terminal Number (Continued)
TERM. NO.
GGU PGE
TERM. NO.
GGU PGE
TERM. NO.
GGU PGE
SIGNAL NAME
SIGNAL NAME
SIGNAL NAME
VS1
GHK
W7
GHK
R10
M1
GHK
F11
E13
B10
F15
F10
V
V
V
B4
G13
A7
138
90
V
V
V
L9
G1
63
18
44
71
72
C6
D9
131
117
133
106
136
CC
CCI
A12
H19
M18
M19
VS2
CCCB
CCCB
CCP
CCP
126
73
N4
V6
WAIT
A5
VCCD0
VCCD1
N13
M13
VPPD0
VPPD1
N12
M12
V12
U12
WE
C11
D5
74
WP(IOIS16)
2–11
The terminals are grouped in tables by functionality, such as PCI system function and power-supply function (see
Table 2–6 through Table 2–16). The terminal numbers also are listed for convenient reference.
Table 2–6. Power-Supply Terminals
TERMINAL
NUMBER
PGE
DESCRIPTION
NAME
GGU
GHK
B6, C10, 6, 22, 42, A15, E11,
D3, F12,
H2, K11,
L4, M8
58, 78,
94, 114,
130
H15, J5,
L15, M5,
R9, W5
GND
Device ground terminals
B4, C8,
D12, F3,
H11, K2, 102, 122,
L6
A7, G13
L9
14, 30,
50, 86,
A13, B9,
F17, J18,
L2, P3,
W7
Power-supply terminal for core logic (3.3 V)
V
CC
138
90, 126
63
A12, H19 Clamp voltage for PC Card interface. Matches card signaling environment, 5 V or 3.3 V.
V
CCCB
R10
Clamp voltage for interrupt subsystem interface and miscellaneous I/O, 5 V or 3.3 V
Clamp voltage for PCI signaling, 5 V or 3.3 V
V
CCI
G1, N4
18, 44
M1, V6
V
CCP
Table 2–7. PC Card Power-Switch Terminals
TERMINAL
NUMBER
GGU PGE GHK
I/O
DESCRIPTION
NAME
VCCD0
VCCD1
N13
M13
73
74
M18
M19
O
O
Logic controls to the TPS2211 PC Card power-switch interface to control AVCC.
Logic controls to the TPS2211 PC Card power-switch interface to control AVPP.
VPPD0
VPPD1
N12
M12
71
72
V12
U12
Table 2–8. PCI System Terminals
TERMINAL
NUMBER
GGU PGE GHK
I/O
DESCRIPTION
NAME
Global reset. When global reset is asserted, GRST causes the PCI1410A device to place all output
buffers in a high-impedance state and reset all internal registers. When GRST is asserted, the device
is completely in its default state. For systems that require wake-up from D3, GRST normally is
asserted only during initial boot. PRST should be asserted following initial boot so that PME context
is retained when transitioning from D3 to D0. For systems that do not require wake-up from D3, GRST
should be tied to PRST.
GRST
M10
66
V11
I
When the SUSPEND mode is enabled, the device is protected from GRST, and the internal registers
are preserved. All outputs are placed in a high-impedance state.
PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are sampled
at the rising edge of PCLK.
PCLK
PRST
H1
G4
21
20
M6
M3
I
I
PCI bus reset. When the PCI bus reset is asserted, PRST causes the PCI1410A device to place all
output buffers in a high-impedance state and reset internal registers. When PRST is asserted, the
device is completely nonfunctional. After PRST is deasserted, the PCI1410A device is in a default
state.
When the SUSPEND mode is enabled, the device is protected from PRST, and the internal registers
are preserved. All outputs are placed in a high-impedance state.
2–12
Table 2–9. PCI Address and Data Terminals
TERMINAL
NUMBER
PGE GHK
I/O
DESCRIPTION
NAME
GGU
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
C2
C1
D4
D2
D1
E4
E3
E2
F2
F1
G2
G3
H3
H4
J1
3
4
5
7
8
9
J1
J2
J3
J6
K1
K2
K3
K5
L3
10
11
15
16
17
19
23
24
25
26
38
39
40
41
43
45
46
47
49
51
52
53
54
55
56
57
L6
L5
M2
N1
N2
N3
N6
U5
R6
P7
V5
U6
R7
W6
P8
V7
R8
U8
V8
W8
W9
V9
U9
PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the
primary interface. During the address phase of a primary bus PCI cycle, AD31–AD0 contain a 32-bit
address or other destination information. During the data phase, AD31–AD0 contain data.
J2
I/O
N2
M3
N3
K4
M4
K5
L5
M5
K6
M6
N6
M7
N7
L7
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
K7
N8
AD0
PCI bus commands and byte enables. These signals are multiplexed on the same PCI terminals.
During the address phase of a primary bus PCI cycle, C/BE3–C/BE0 define the bus command.
During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which
byte paths of the full 32-bit data bus carry meaningful data. C/BE0 applies to byte 0 (AD7–AD0),
C/BE1 applies to byte 1 (AD15–AD8), C/BE2 applies to byte 2 (AD23–AD16), and C/BE3 applies
to byte 3 (AD31–AD24).
E1
J3
N1
N5
12
27
37
48
K6
P1
W4
U7
C/BE3
C/BE2
C/BE1
C/BE0
I/O
I/O
PCI bus parity. In all PCI bus read and write cycles, the PCI1410A device calculates even parity
across the AD31–AD0 and C/BE3–C/BE0 buses. As an initiator during PCI cycles, the PCI1410A
device outputs this parity indicator with a one-PCLK delay. As a target during PCI cycles, the
calculated parity is compared to the initiator parity indicator. A compare error results in the assertion
of a parity error (PERR).
PAR
M2
36
T1
2–13
Table 2–10. PCI Interface Control Terminals
TERMINAL
NUMBER
GGU PGE GHK
I/O
DESCRIPTION
NAME
PCI device select. The PCI1410A device asserts DEVSEL to claim a PCI cycle as the target device.
As a PCI initiator on the bus, the PCI1410A device monitors DEVSEL until a target responds. If no
target responds before timeout occurs, the PCI1410A device terminates the cycle with an initiator
abort.
L1
J4
32
28
P6
P2
I/O
DEVSEL
PCI cycle frame. FRAME is driven by the initiator of a bus cycle. FRAME is asserted to indicate that
I/O a bus transaction is beginning, and data transfers continue while this signal is asserted. When FRAME
is deasserted, the PCI bus transaction is in the final data phase.
FRAME
PCI bus grant. GNT is driven by the PCI bus arbiter to grant the PCI1410A device access to the PCI
B1
F4
K1
2
H1
L1
N5
I
I
bus after the current data transaction has completed. GNT may or may not follow a PCI bus request,
depending on the PCI bus parking algorithm.
GNT
IDSEL
IRDY
Initialization device select. IDSEL selects the PCI1410A device during configuration space accesses.
IDSEL can be connected to one of the upper 24 PCI address lines on the PCI bus.
13
29
PCI initiator ready. IRDY indicates the PCI bus initiator’s ability to complete the current data phase
I/O of the transaction. A data phase is completed on a rising edge of PCLK, when both IRDY and TRDY
are asserted. Until IRDY and TRDY are both sampled asserted, wait states are inserted.
PCI parity error indicator. PERR is driven by a PCI device to indicate that calculated parity does not
I/O match PAR when PERR is enabled through bit 6 (PERR_EN) of the command register (PCI offset 04h,
see Section 4.4).
L3
A1
34
1
P5
H2
PERR
REQ
PCI bus request. REQ is asserted by the PCI1410A device to request access to the PCI bus as an
O
initiator.
PCI system error. SERR is an output that is pulsed from the PCI1410A device when enabled through
bit 8 (SERR_EN) of the command register (PCI offset 04h, see Section 4.4) indicating a system error
has occurred. The PCI1410A device need not be the target of the PCI cycle to assert this signal. When
SERR is enabled in the command register, this signal also pulses, indicating that an address parity
error has occurred on a CardBus interface.
M1
35
R3
O
SERR
PCI cycle stop signal. STOP is driven by a PCI target to request the initiator to stop the current PCI
L2
K3
33
31
R2
R1
I/O bus transaction. STOP is used for target disconnects and is commonly asserted by target devices that
do not support burst data transfers.
STOP
TRDY
PCI target ready. TRDY indicates the primary bus target’s ability to complete the current data phase
I/O of the transaction. A data phase is completed on a rising edge of PCLK, when both IRDY and TRDY
are asserted. Until both IRDY and TRDY are asserted, wait states are inserted.
2–14
Table 2–11. Multifunction and Miscellaneous Terminals
TERMINAL
NUMBER
GGU PGE GHK
I/O
DESCRIPTION
NAME
Multifunction terminal 0. MFUNC0 can be configured as parallel PCI interrupt INTA, GPI0,
GPO0, socket activity LED output, zoomed-video (ZV) switching outputs, CardBus audio PWM,
GPE, or a parallel IRQ. See Section 4.30, Multifunction Routing Register, for configuration
details.
MFUNC0
K8
60
W10 I/O
Multifunction terminal 1. MFUNC1 can be configured as GPI1, GPO1, socket activity LED
output, ZV switching outputs, CardBus audio PWM, GPE, or a parallel IRQ. See Section 4.30,
Multifunction Routing Register, for configuration details.
MFUNC1
N9
61
V10
P10
I/O
Serial data (SDA). When VCCD0 and VCCD1 are high after a PCI reset, the MFUNC1 terminal
provides the SDA signaling for the serial bus interface. The two-terminal serial interface loads
the subsystem identification and other register defaults from an EEPROM after a PCI reset. See
Section 3.6.1, Serial Bus Interface Implementation, for details on other serial bus applications.
Multifunction terminal 2. MFUNC2 can be configured as PC/PCI DMA request, GPI2, GPO2,
MFUNC2
MFUNC3
K9
64
65
I/O socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE, RI_OUT, or a
parallel IRQ. See Section 4.30, Multifunction Routing Register, for configuration details.
Multifunction terminal 3. MFUNC3 can be configured as a parallel IRQ or the serialized interrupt
signal IRQSER. See Section 4.30, Multifunction Routing Register, for configuration details.
N10
W11 I/O
Multifunction terminal 4. MFUNC4 can be configured as PCI LOCK, GPI3, GPO3, socket activity
LED output, ZV switching outputs, CardBus audio PWM, GPE, RI_OUT, or a parallel IRQ. See
Section 4.30, Multifunction Routing Register, for configuration details.
MFUNC4
MFUNC5
L10
67
U11
I/O
Serial clock (SCL). When VCCD0 and VCCD1 are high after a PCI reset, the MFUNC4 terminal
provides the SCL signaling for the serial bus interface. The two-terminal serial interface loads
the subsystem identification and other register defaults from an EEPROM after a PCI reset. See
Section 3.6.1, Serial Bus Interface Implementation, for details on other serial bus applications.
Multifunction terminal 5. MFUNC5 can be configured as PC/PCI DMA grant, GPI4, GPO4,
N11
68
P11
I/O socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE, or a parallel IRQ.
See Section 4.30, Multifunction Routing Register, for configuration details.
Multifunction terminal 6. MFUNC6 can be configured as a PCI CLKRUN or a parallel IRQ. See
Section 4.30, Multifunction Routing Register, for configuration details.
MFUNC6
M11
L8
69
59
R11
P9
I/O
Ring indicate out and power-management event output. Terminal provides an output for
ring-indicate or PME signals.
RI_OUT/PME
O
Speaker output. SPKROUT is the output to the host system that can carry SPKR or CAUDIO
M9
62
70
U10
O
I
through the PCI1410A device from the PC Card interface. SPKROUT is driven as the
exclusive-OR combination of card SPKR//CAUDIO inputs.
SPKROUT
SUSPEND
Suspend. SUSPEND protects the internal registers from clearing when the GRST or PRST
signal is asserted. See Section 3.8.4, Suspend Mode, for details.
L11
W12
2–15
Table 2–12. 16-Bit PC Card Address and Data Terminals
TERMINAL
NUMBER
I/O
DESCRIPTION
NAME
GGU
PGE
GHK
ADDR25
ADDR24 D10
ADDR23
ADDR22
ADDR21
A10
116
113
111
109
107
105
103
100
98
108
110
104
101
112
95
B14
B15
E14
A16
E17
E18
E19
F18
G14
D19
C15
F14
G15
F13
G19
J15
B11
A13
B13
ADDR20 C12
ADDR19
ADDR18
ADDR17
ADDR16
ADDR15
ADDR14 C13
ADDR13 D13
ADDR12
ADDR11
D11
E10
E12
B12
A12
O
PC Card address. 16-bit PC Card address lines. ADDR25 is the most significant bit.
A11
F11
ADDR10 G12
89
ADDR9
ADDR8
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
E13
E11
B10
C9
A9
D8
A8
C7
D7
A6
97
99
G17
F19
C14
A14
C13
B13
C12
A11
B11
C11
115
118
120
121
124
127
128
129
DATA15
DATA14
DATA13
DATA12
DATA11
DATA10
DATA9
DATA8
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
H12
J13
J11
K13
K10
B2
87
84
82
80
77
144
142
140
85
83
81
79
76
143
141
139
J17
K14
K17
K19
L17
C8
C3
A3
A8
F9
I/O
PC Card data. 16-bit PC Card data lines. DATA15 is the most significant bit.
H10
J12
J10
K12
L13
A2
J19
K15
K18
L14
L18
B8
B3
C4
E9
C9
2–16
Table 2–13. 16-Bit PC Card Interface Control Terminals
TERMINAL
NUMBER
I/O
DESCRIPTION
NAME
GGU
PGE
GHK
Battery voltage detect 1. BVD1 is generated by 16-bit memory PC Cards that include
batteries. BVD1 is used with BVD2 as an indication of the condition of the batteries on a
memory PC Card. Both BVD1 and BVD2 are high when the battery is good. When BVD2
is low and BVD1 is high, the battery is weak and should be replaced. When BVD1 is low,
the battery is no longer serviceable and the data in the memory PC Card is lost. See
Section 5.6, ExCA Card Status-Change-Interrupt Configuration Register, for enable bits.
See Section 5.5, ExCA Card Status-Change Register, and Section 5.2, ExCA Interface
Status Register, for the status bits for this signal.
BVD1
(STSCHG/RI)
C5
135
E10
I
Status change. STSCHG is used to alert the system to a change in the READY, write protect,
or battery voltage dead condition of a 16-bit I/O PC Card.
Ring indicate. RI is used by 16-bit modem cards to indicate a ring detection.
Battery voltage detect 2. BVD2 is generated by 16-bit memory PC Cards that include
batteries. BVD2 is used with BVD1 as an indication of the condition of the batteries on a
memory PC Card. Both BVD1 and BVD2 are high when the battery is good. When BVD2
is low and BVD1 is high, the battery is weak and should be replaced. When BVD1 is low,
the battery is no longer serviceable and the data in the memory PC Card is lost. See
Section 5.6, ExCA Card Status-Change-Interrupt Configuration Register, for enable bits.
See Section 5.5, ExCA Card Status-Change Register, and Section 5.2, ExCA Interface
Status Register, for the status bits for this signal.
BVD2
(SPKR)
B5
134
C10
I
Speaker. SPKR is an optional binary audio signal available only when the card and socket
have been configured for the 16-bit I/O interface. The audio signals from cards A and B are
combined by the PCI1410A device and are output on SPKROUT.
DMA request. BVD2 can be used as the DMA request signal during DMA operations to a
16-bit PC Card that supports DMA. The PC Card asserts BVD2 to indicate a request for a
DMA operation.
Card detect 1 and card detect 2. CD1 and CD2 are connected internally to ground on the
PC Card. When a PC Card is inserted into a socket, CD1 and CD2 are pulled low. For signal
status, see Section 5.2, ExCA Interface Status Register.
L12
A4
75
137
L19
A9
CD1
CD2
I
Card enable 1 and card enable 2. CE1 and CE2 enable even- and odd-numbered address
bytes. CE1 enables even-numbered address bytes, and CE2 enables odd-numbered
address bytes.
H13
G11
88
91
J14
H18
CE1
CE2
O
Input acknowledge. INPACK is asserted by the PC Card when it can respond to an I/O read
cycle at the current address.
INPACK
IORD
IOWR
OE
B8
123
93
E12
H14
G18
I
DMA request. INPACK can be used as the DMA request signal during DMA operations from
a 16-bit PC Card that supports DMA. If it is used as a strobe, the PC Card asserts this signal
to indicate a request for a DMA operation.
I/O read. IORD is asserted by the PCI1410A device to enable 16-bit I/O PC Card data output
during host I/O read cycles.
F13
F10
O
O
DMA write. IORD is used as the DMA write strobe during DMA operations from a 16-bit PC
Card that supports DMA. The PCI1410A device asserts IORD during DMA transfers from
the PC Card to host memory.
I/O write. IOWR is driven low by the PCI1410A device to strobe write data into 16-bit I/O PC
Cards during host I/O write cycles.
96
DMA read. IOWR is used as the DMA write strobe during DMA operations from a 16-bit PC
Card that supports DMA. The PCI1410A device asserts IOWR during transfers from host
memory to the PC Card.
Output enable. OE is driven low by the PCI1410A device to enable 16-bit memory PC Card
data output during host memory read cycles.
G10
92
H17
O
DMA terminal count. OE is used as terminal count (TC) during DMA operations to a 16-bit
PC Card that supports DMA. The PCI1410A device asserts OE to indicate TC for a DMA
write operation.
2–17
Table 2–13. 16-Bit PC Card Interface Control Terminals (Continued)
TERMINAL
NUMBER
I/O
DESCRIPTION
NAME
GGU
PGE
GHK
Ready. The ready function is provided by READY when the 16-bit PC Card and the host socket
are configured for the memory-only interface. READY is driven low by the 16-bit memory PC
Cards to indicate that the memory card circuits are busy processing a previous write command.
READY is driven high when the 16-bit memory PC Card is ready to accept a new data-transfer
command.
READY
(IREQ)
D6
132
A10
I
Interrupt request. IREQ is asserted by a 16-bit I/O PC Card to indicate to the host that a device
on the 16-bit I/O PC Card requires service by the host software. IREQ is high (deasserted) when
no interrupt is requested.
Attribute memory select. REG remains high for all common memory accesses. When REG is
asserted, access is limited to attribute memory (OE or WE active) and to the I/O space (IORD or
IOWR active). Attribute memory is a separately accessed section of card memory and generally
is used to record card capacity and other configuration and attribute information.
B7
B9
125
119
B12
F12
O
REG
DMA acknowledge. REG is used as a DMA acknowledge (DACK) during DMA operations to a
16-bit PC Card that supports DMA. The PCI1410A device asserts REG to indicate a DMA
operation. REG is used in conjunction with the DMA read (IOWR) or DMA write (IORD) strobes
to transfer data.
RESET
O
PC Card reset. RESET forces a hard reset to a 16-bit PC Card.
VS1
VS2
C6
D9
131
117
F11
E13
Voltage sense 1 and voltage sense 2. VS1 and VS2, when used in conjunction with each other,
determine the operating voltage of the PC Card.
I/O
Bus cycle wait. WAIT is driven by a 16-bit PC Card to extend the completion of the memory or
I/O cycle in progress.
A5
133
B10
I
WAIT
Write enable. WE is used to strobe memory write data into 16-bit memory PC Cards. WE also is
used for memory PC Cards that employ programmable memory technologies.
WE
C11
106
F15
O
DMA terminal count. WE is used as TC during DMA operations to a 16-bit PC Card that supports
DMA. The PCI1410A device asserts WE to indicate TC for a DMA read operation.
Write protect. WP applies to 16-bit memory PC Cards. WP reflects the status of the write-protect
switch on 16-bit memory PC Cards. For 16-bit I/O cards, WP is used for the 16-bit port (IOIS16)
function.
I/O is 16 bits. IOIS16 applies to 16-bit I/O PC Cards. IOIS16 is asserted by the 16-bit PC Card
when the address on the bus corresponds to an address to which the 16-bit PC Card responds,
and the I/O port that is addressed is capable of 16-bit accesses.
WP
(IOIS16)
D5
136
F10
I
DMA request. WP can be used as the DMA request signal during DMA operations to a 16-bit
PC Card that supports DMA. If used, the PC Card asserts WP to indicate a request for a DMA
operation.
Table 2–14. CardBus PC Card Interface System Terminals
TERMINAL
NUMBER
I/O
DESCRIPTION
NAME
GGU
PGE
GHK
CardBus clock. CCLK provides synchronous timing for all transactions on the CardBus interface.
All signals except CRST, CCLKRUN, CINT, CSTSCHG, CAUDIO, CCD2, CCD1, CVS2, and
CVS1 are sampled on the rising edge of CCLK, and all timing parameters are defined with the
rising edge of this signal. CCLK operates at the PCI bus clock frequency, but it can be stopped
in the low state or slowed down for power savings.
CCLK
B12
108
D19
O
CardBus clock run. CCLKRUN is used by a CardBus PC Card to request an increase in the CCLK
frequency, and by the PCI1410A device to indicate that the CCLK frequency is going to be
decreased.
D5
B9
136
119
F10
F12
I/O
O
CCLKRUN
CRST
CardBus reset. CRST brings CardBus PC Card-specific registers, sequencers, and signals to a
known state. When CRST is asserted, all CardBus PC Card signals are placed in a
high-impedance state, and the PCI1410A device drives these signals to a valid logic level.
Assertion can be asynchronous to CCLK, but deassertion must be synchronous to CCLK.
2–18
Table 2–15. CardBus PC Card Address and Data Terminals
TERMINAL
NUMBER
I/O
DESCRIPTION
NAME
GGU
PGE
GHK
CAD31
CAD30
CAD29
CAD28
CAD27
CAD26
CAD25
CAD24
CAD23
CAD22
CAD21
CAD20
CAD19
CAD18
CAD17
CAD16
CAD15
CAD14
CAD13
CAD12
CAD11
CAD10
CAD9
B2
C3
B3
A3
C4
A6
D7
C7
A8
144
142
141
140
139
129
128
127
124
121
120
118
116
115
113
98
96
97
93
95
92
91
89
87
C8
A8
E9
F9
C9
C11
B11
A11
C12
B13
C13
A14
B14
C14
B15
G14
G18
G17
H14
G19
H17
H18
J15
J17
J19
K17
K15
K19
K18
L17
L14
L18
D8
A9
C9
A10
B10
D10
E12
F10
E13
F13
F11
G10
G11
G12
H12
H10
J11
J12
K13
J10
K10
K12
L13
CardBus address and data. These signals make up the multiplexed CardBus address and data
bus on the CardBus interface. During the address phase of a CardBus cycle, CAD31–CAD0
contain a 32-bit address. During the data phase of a CardBus cycle, CAD31–CAD0 contain data.
CAD31 is the most significant bit.
I/O
CAD8
CAD7
CAD6
CAD5
CAD4
CAD3
CAD2
CAD1
85
82
83
80
81
77
79
76
CAD0
CardBus bus commands and byte enables. CC/BE3–CC/BE0 are multiplexed on the same
CardBus terminals. During the address phase of a CardBus cycle, CC/BE3–CC/BE0 define the
bus command. During the data phase, this 4-bit bus is used as byte enables. The byte enables
determine which byte paths of the full 32-bit data bus carry meaningful data. CC/BE0 applies to
byte 0 (CAD7–CAD0), CC/BE1 applies to byte 1 (CAD15–CAD8), CC/BE2 applies to byte 2
(CAD23–CAD16), and CC/BE3 applies to byte 3 (CAD31–CAD24).
B7
125
112
99
B12
F13
F19
J14
CC/BE3
CC/BE2
CC/BE1
CC/BE0
A11
E11
H13
I/O
I/O
88
CardBus parity. In all CardBus read and write cycles, the PCI1410A device calculates even parity
across the CAD and CC/BE buses. As an initiator during CardBus cycles, the PCI1410A device
outputs CPAR with a one-CCLK delay. As a target during CardBus cycles, the calculated parity
is compared to the initiator’s parity indicator; a compare error results in a parity-error assertion.
CPAR
D13
101
G15
2–19
Table 2–16. CardBus PC Card Interface Control Terminals
TERMINAL
NUMBER
I/O
DESCRIPTION
NAME
GGU
PGE
134
103
GHK
C10
E19
CardBus audio. CAUDIO is a digital input signal from a PC Card to the system speaker. The
PCI1410A device supports the binary audio mode and outputs a binary signal from the card to
SPKROUT.
CAUDIO
CBLOCK
B5
I
I/O
I
D11
CardBus lock. CBLOCK is used to gain exclusive access to a target.
CardBus detect 1 and CardBus detect 2. CCD1 and CCD2 are used in conjunction with CVS1
and CVS2 to identify card insertion and interrogate cards to determine the operating voltage and
card type.
L12
A4
75
137
L19
A9
CCD1
CCD2
CardBus device select. The PCI1410A device asserts CDEVSEL to claim a CardBus cycle as
the target device. As a CardBus initiator on the bus, the PCI1410A device monitors CDEVSEL
until a target responds. If no target responds before timeout occurs, the PCI1410A device
terminates the cycle with an initiator abort.
B13
B11
107
111
E17
E14
I/O
I/O
CDEVSEL
CFRAME
CardBus cycle frame. CFRAME is driven by the initiator of a CardBus bus cycle. CFRAME is
asserted to indicate that a bus transaction is beginning, and data transfers continue while this
signal is asserted. When CFRAME is deasserted, the CardBus bus transaction is in the final
data phase.
CardBus bus grant. CGNT is driven by the PCI1410A device to grant a CardBus PC Card
access to the CardBus bus after the current data transaction has been completed.
C11
D6
106
132
F15
A10
O
I
CGNT
CINT
CardBus interrupt. CINT is asserted low by a CardBus PC Card to request interrupt servicing
from the host.
CardBus initiator ready. CIRDY indicates the ability of the CardBus initiator to complete the
current data phase of the transaction. A data phase is completed on a rising edge of CCLK when
both CIRDY and CTRDY are asserted. Until both CIRDY and CTRDY are sampled asserted,
wait states are inserted.
A12
110
C15
I/O
CIRDY
CardBus parity error. CPERR reports parity errors during CardBus transactions, except during
special cycles. It is driven low by a target two clocks following that data when a parity error is
detected.
C13
B8
104
123
133
F14
E12
B10
I/O
CPERR
CREQ
CardBus request. CREQ indicates to the arbiter that the CardBus PC Card desires use of the
CardBus bus as an initiator.
I
I
CardBus system error. CSERR reports address parity errors and other system errors that could
lead to catastrophic results. CSERR is driven by the card synchronous to CCLK. The PCI1410A
device can report CSERR to the system by assertion of SERR on the PCI interface.
A5
CSERR
CardBus stop. CSTOP is driven by a CardBus target to request the initiator to stop the current
CardBus transaction. CSTOP is used for target disconnects, and is commonly asserted by
target devices that do not support burst data transfers.
C12
C5
105
135
109
E18
E10
A16
I/O
I
CSTOP
CSTSCHG
CTRDY
CardBus status change. CSTSCHG alerts the system to a change in the card status, and is
used as a wake-up mechanism.
CardBus target ready. CTRDY indicates the ability of the CardBus target ability to complete the
current data phase of the transaction. A data phase is completed on a rising edge of CCLK,
when both CIRDY and CTRDY are asserted; until this time, wait states are inserted.
A13
I/O
CardBus voltage sense 1 and CardBus voltage sense 2. CVS1 and CVS2 are used in
conjunction with CCD1 and CCD2 to identify card insertion and interrogate cards to determine
the operating voltage and card type.
CVS1
CVS2
C6
D9
131
117
F11
E13
I/O
2–20
3 Feature/Protocol Descriptions
The following sections give an overview of the PCI1410A device. Figure 3–1 shows a simplified block diagram of the
PCI1410A device. The PCI interface includes all address/data and control signals for PCI protocol. The interrupt
interface includes terminals for parallel PCI, parallel ISA, and serialized PCI and ISA signaling. Miscellaneous system
interface terminals include multifunction terminals: SUSPEND, RI_OUT/PME (power-management control signal),
and SPKROUT.
PCI Bus
INTA
Interrupt
Activity LED
Controller
TPS2211
Power
Switch
PCI950
IRQSER
Deserializer
IRQSER
3
PCI1410A
IRQ2–15
4
PC Card
Socket
68
Zoomed Video
19
VGA
Controller
23
PCI930
ZV Switch
Zoomed Video
4
Audio
Subsystem
External ZV Port
NOTE: The PC Card interface is 68 terminals for CardBus and 16-bit PC Cards. In ZV mode, 23 terminals are used for routing the ZV signals
to the VGA controller and audio subsystem.
Figure 3–1. PCI1410A Simplified Block Diagram
3.1 Power-Supply Sequencing
The PCI1410A device contains 3.3-V I/O buffers with 5-V tolerance, requiring a core power supply and clamp
voltages. The core power supply always is 3.3 V. The clamp voltages can be either 3.3 V or 5 V, depending on the
interface. The following power-up and power-down sequences are recommended.
The power-up sequence is:
1. Apply 3.3-V power to the core.
2. Assert GRST to the device to disable the outputs during power up. Output drivers must be powered up in
the high-impedance state to prevent high current levels through the clamp diodes to the 5-V supply.
3. Apply the clamp voltage.
The power-down sequence is:
1. Use GRST to switch outputs to a high-impedance state.
2. Remove the clamp voltage.
3. Remove the 3.3-V power from the core.
3–1
3.2 I/O Characteristics
Figure 3–2 shows a 3-state bidirectional buffer. Section 8.2, Recommended Operating Conditions, provides the
electrical characteristics of the inputs and outputs.
NOTE: The PCI1410A device meets the ac specifications of the PC Card Standard and PCI
Local Bus Specification.
V
CCP
Tied for Open Drain
OE
Pad
Figure 3–2. 3-State Bidirectional Buffer
NOTE: Unused pins (input or I/O) must be held high or low to prevent them from floating.
3.3 Clamping Voltages
The clamping voltages are set to match whatever external environment the PCI1410A device is interfaced with: 3.3 V
or 5 V. The I/O sites can be pulled through a clamping diode to a voltage rail that protects the core from external
signals. The core power supply always is 3.3 V and is independent of the clamping voltages. For example, PCI
signaling can be either 3.3 V or 5 V, and the PCI1410A device must reliably accommodate both voltage levels. This
is accomplished by using a 3.3-V I/O buffer that is 5-V tolerant, with the applicable clamping voltage applied. If a
system designer desires a 5-V PCI bus, V
can be connected to a 5-V power supply.
CCP
The PCI1410A device requires three separate clamping voltages because it supports a wide range of features. The
three voltages are listed and defined in Section 8.2, Recommended Operating Conditions.
3.4 Peripheral Component Interconnect (PCI) Interface
The PCI1410A device is fully compliant with the PCI Local Bus Specification. The PCI1410A device provides all
required signals for PCI master or slave operation, and can operate in either a 5-V or 3.3-V signaling environment
by connecting the V
device provides the optional interrupt signal INTA.
terminals to the desired voltage level. In addition to the mandatory PCI signals, the PCI1410A
CCP
3.4.1 PCI Bus Lock (LOCK)
The bus-locking protocol defined in the PCI Local Bus Specification is not highly recommended, but is provided on
the PCI1410A device as an additional compatibility feature. The PCI LOCK signal can be routed to the MFUNC4
terminal via the multifunction routing register. See Section 4.30, Multifunction Routing Register, for details. Note that
the use of LOCK is supported only by PCI-to-CardBus bridges in the downstream direction (away from the processor).
PCI LOCK indicates an atomic operation that may require multiple transactions to complete. When LOCK is asserted,
nonexclusive transactions can proceed to an address that currently is not locked. A grant to start a transaction on
the PCI bus does not guarantee control of LOCK; control of LOCK is obtained under its own protocol. It is possible
for different initiators to use the PCI bus while a single master retains ownership of LOCK. Note that the CardBus
signal for this protocol is CBLOCK to avoid confusion with the bus clock.
An agent may need to do an exclusive operation because a critical access to memory might be broken into several
transactions, but the master wants exclusive rights to a region of memory. The granularity of the lock is defined by
PCI to be 16 bytes, aligned. The LOCK protocol defined by the PCI Local Bus Specification allows a resource lock
without interfering with nonexclusive real-time data transfer, such as video.
The PCI bus arbiter may be designed to support only complete bus locks using the LOCK protocol. In this scenario,
the arbiter will not grant the bus to any other agent (other than the LOCK master) while LOCK is asserted. A complete
3–2
bus lock may have a significant impact on the performance of the video. The arbiter that supports complete bus lock
must grant the bus to the cache to perform a writeback due to a snoop to a modified line when a locked operation
is in progress.
The PCI1410A device supports all LOCK protocol associated with PCI-to-PCI bridges, as also defined for
PCI-to-CardBus bridges. This includes disabling write posting while a locked operation is in progress, which can solve
a potential deadlock when using devices such as PCI-to-PCI bridges. The potential deadlock can occur if a CardBus
target supports delayed transactions and blocks access to the target until it completes a delayed read. This target
characteristic is prohibited by the PCI Local Bus Specification, and the issue is resolved by the PCI master using
LOCK.
3.4.2 Loading Subsystem Identification
The subsystem vendor ID register (PCI offset 40h, see Section 4.26) and subsystem ID register (PCI offset 42h, see
Section 4.27) make up a doubleword of PCI configuration space located at offset 40h for functions 0 and 1. This
doubleword register is used for system and option card (mobile dock) identification purposes and is required by some
operating systems.
The PCI1410A device offers two mechanisms to load a read-only value into the subsystem registers. The first
mechanism relies upon the system BIOS providing the subsystem ID value. The default access mode to the
subsystem registers is read-only, but can be made read/write by clearing bit 5 (SUBSYSRW) in the system control
register (PCI offset 80h, see Section 4.29). When this bit is cleared, the BIOS can write a subsystem identification
value into the registers at PCI offset 40h. The BIOS must set the SUBSYSRW bit such that the subsystem vendor
ID register and subsystem ID register are limited to read-only access. This approach saves the added cost of
implementing the serial electrically erasable programmable ROM (EEPROM).
In some conditions, such as in a docking environment, the subsystem vendor ID register and subsystem ID register
must be loaded with a unique identifier via a serial EEPROM. The PCI1410A device loads the data from the serial
EEPROM after a reset of the primary bus. Note that the SUSPEND input gates the PCI reset from the entire PCI1410A
core, including the serial bus state machine (see Section 3.8.4, Suspend Mode, for details on using SUSPEND).
The PCI1410A device provides a two-line serial bus host controller that can interface to a serial EEPROM. See
Section 3.6, Serial Bus Interface, for details on the two-wire serial bus controller and applications.
3.5 PC Card Applications
This section describes the PC Card interfaces of the PCI1410A device:
•
•
•
•
•
•
•
•
Card insertion/removal and recognition
P C power-switch interface
2
Zoomed-video (ZV) support
Speaker and audio applications
LED socket activity indicators
PC Card-16 DMA support
PC Card controller programming model
CardBus socket registers
3.5.1 PC Card Insertion/Removal and Recognition
The PC Card Standard addresses the card-detection and recognition process through an interrogation procedure
that the socket must initiate on card insertion into a cold, nonpowered socket. Through this interrogation, card voltage
requirements and interface (16-bit versus CardBus) are determined.
The scheme uses the card-detect and voltage-sense signals. The configuration of these four terminals identifies the
card type and voltage requirements of the PC Card interface. The encoding scheme is defined in the PC Card
Standard and in Table 3–1.
3–3
Table 3–1. PC Card Card-Detect and Voltage-Sense Connections
CD2//CCD2
Ground
CD1//CCD1
Ground
VS2//CVS2
Open
VS1//CVS1
Open
KEY
5 V
5 V
5 V
LV
INTERFACE
16-bit PC Card
VOLTAGE
5 V
Ground
Ground
Open
Ground
16-bit PC Card
5 V and 3.3 V
5 V, 3.3 V, and X.X V
3.3 V
Ground
Ground
Ground
Ground
16-bit PC Card
Ground
Ground
Open
Ground
16-bit PC Card
Ground
Connect to CVS1
Ground
Open
Connect to CCD1
Ground
LV
CardBus PC Card
16-bit PC Card
3.3 V
Ground
Ground
LV
3.3 V and X.X V
3.3 V and X.X V
3.3 V, X.X V, and Y.Y V
Y.Y V
Connect to CVS2
Connect to CVS1
Ground
Ground
Connect to CCD2
Ground
Ground
LV
CardBus PC Card
CardBus PC Card
16-bit PC Card
Ground
Connect to CCD2
Open
LV
Ground
Ground
LV
Connect to CVS2
Ground
Ground
Connect to CCD2
Connect to CCD1
Open
Open
LV
CardBus PC Card
CardBus PC Card
CardBus PC Card
Y.Y V
Connect to CVS2
Ground
Open
LV
X.X V and Y.Y V
Y.Y V
Connect to CVS1
Ground
Connect to CCD2
Connect to CCD1
Ground
LV
Connect to CVS1
Connect to CVS2
Ground
Reserved
Reserved
Ground
Connect to CCD1
2
3.5.2 P C Power-Switch Interface (TPS2211)
2
The PCI1410A device provides a P C (PCMCIA peripheral control) interface for control of the PC Card power switch.
The VCCD and VPPD terminals are used with the TI TPS2211 single-slot PC Card power-switch interface to provide
power-switch support. Figure 3–3 shows terminal assignments for the TPS2211 power-switch interface. Figure 3–4
illustrates a typical application, where the PCI1410A device represents the PC Card controller.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCCD0
VCCD1
3.3V
3.3V
5V
SHDN
VPPD0
VPPD1
AVCC
AVCC
AVCC
AVPP
12V
5V
GND
OC
Figure 3–3. TPS2211 Terminal Assignments
The PCI1410A device also includes support for the Maxim 1602 single-channel CardBus and PCMCIA
power-switching network. Application of this power switch is similar to the TPS2211 power-switch interface.
3–4
Power Supply
TPS2211
12 V
5 V
12V
5V
3.3 V
3.3V
AVPP
AVCC
V
V
V
V
PP1
PP2
CC
SHDN
SHDN
Supervisor
PC Card
CC
VCCD0
VCCD1
VPPD0
VPPD1
PCI1410A
(PC Card
Controller)
Figure 3–4. TPS2211 Typical Application
3.5.3 Zoomed-Video Support
The PCI1410A device allows for the implementation of ZV for PC Cards. ZV is supported by setting bit 6 (ZVENABLE)
in the card control register (PCI offset 91h, see Section 4.32) on a per-socket function basis. Setting this bit puts PC
Card 16 address lines ADDR25–ADDR4 of the PC Card interface in the high-impedance state. These lines can then
transfer video and audio data directly to the appropriate controller. Card address lines ADDR3–ADDR0 can still
access PC Card CIS registers for PC Card configuration. Figure 3–5 illustrates a PCI1410A ZV implementation.
Speakers
CRT
Motherboard
PCI Bus
VGA
Controller
Audio
Codec
Zoomed
Video Port
PCM
Audio
Input
PC Card
19
19
4
Video
Audio
4
PC Card
Interface
PCI1410A
Figure 3–5. Zoomed-Video Implementation Using the PCI1410A Device
Not shown in Figure 3–5 is the multiplexing scheme used to route a socket ZV source or an external ZV source to
the graphics controller. A typical external source might be provided from a high-speed serial bus like IEEE 1394. The
PCI1410A device provides ZVSTAT and ZVSEL0 signals on the multifunction terminals to switch external bus drivers.
Figure 3–6 shows an implementation for switching between two ZV streams using external logic.
3–5
PCI1410A
ZVSTAT
ZVSEL0
Figure 3–6. Zoomed-Video Switching Application
Figure 3–6 illustrates an implementation using standard three-state bus drivers with active-low output enables.
ZVSEL0 is an active-low output indicating that the socket ZV mode is enabled. ZVSTAT is an active-high output,
indicating that the PCI1410A socket is enabled for ZV mode. The implementation shown in Figure 3–6 can be used
if PC Card ZV is prioritized over other sources.
3.5.4 Ultrazoomed Video
Ultrazoomed video is an enhancement to the PCI1410A DMA engine and is intended to improve the 16-bit bandwidth
for MPEG I and MPEG II decoder PC Cards. This enhancement allows the PCI1410A device to fetch 32 bits of data
from memory, versus the PCI11XX/PCI12XX 16-bit fetch capability. This enhancement allows a higher sustained
throughput to the 16-bit PC Card because the PCI1410A device prefetches an extra 16 bits (32 bits total) during each
PCI read transaction. If the PCI bus becomes busy, the PCI1410A device has an extra 16 bits of data to perform
back-to-back 16-bit transactions to the PC Card before having to fetch more data. This feature is built into the DMA
engine, and software is not required to enable this enhancement.
NOTE: The PCI11XX and PCI12XX series CardBus controllers have enough 16-bit bandwidth
to support MPEG II PC Card decoders. But, it was decided to improve the bandwidth even more
in the PCI14XX series CardBus controllers.
3.5.5 Internal Ring Oscillator
The internal ring oscillator provides an internal clock option for the PCI1410A device so that the PCI clock is not
required for the PCI1410A device to power down a socket or interrogate a PC Card. This internal oscillator operates
nominally at 16 kHz and can be enabled by setting bit 27 (P2CCLK) of the system control register (PCI offset 80h,
see Section 4.29) to 1. This function is disabled by default.
3–6
3.5.6 Integrated Pullup Resistors for PC Card Interface
The PC Card Standard requires pullup resistors on various terminals to support both CardBus and 16-bit card
configurations. Unlike the PCI1210 or PCI1211 device, which required external pullup resistors, the PCI1410A device
has integrated all of these pullup resistors.
PIN NUMBER
SIGNAL NAME
GGU
C13
D6
PGE
104
132
110
75
GHK
F14
A10
C15
L19
F11
E19
E18
E17
A16
E13
F12
B10
E12
C10
E10
A9
ADDR14/CPERR
READY/CINT
ADDR15/CIRDY
CD1/CCD1
A12
L12
C6
VS1/CVS1
131
103
105
107
109
117
119
133
123
134
135
137
ADDR19/CBLOCK
ADDR20/CSTOP
ADDR21/CDEVSEL
ADDR22/CTRDY
VS2/CVS2
D11
C12
B13
A13
D9
RESET/CRST
B9
WAIT/CSERR
A5
INPACK/CREQ
BVD2(SPKR)/CAUDIO
BVD1(STSCHG)/CSTSCHG
CD2/CCD2
B8
B5
C5
A4
3.5.7 SPKROUT and CAUDPWM Usage
SPKROUT carries the digital audio signal from the PC Card to the system. When a 16-bit PC Card is configured for
I/O mode, the BVD2 terminal becomes SPKR. This terminal also is used in CardBus binary audio applications, and
is referred to as CAUDIO. SPKR passes a TTL-level digital audio signal to the PCI1410A device. The CardBus
CAUDIO signal also can pass a single-amplitude binary waveform. The binary audio signal from the PC Card socket
is used in the PCI1410A device to produce SPKROUT. This output is enabled by bit 1 (SPKROUTEN) in the card
control register (PCI offset 91h, see Section 4.32).
Older controllers support CAUDIO in binary or PWM mode, but use the same terminal (SPKROUT). Some audio chips
may not support both modes on one terminal and may have a separate terminal for binary and PWM. The PCI1410A
implementation includes a signal for PWM, CAUDPWM, which can be routed to an MFUNC terminal. Bit 2
(AUD2MUX), located in the card control register, is programmed to route a CardBus CAUDIO PWM terminal to
CAUDPWM. See Section 4.30, Multifunction Routing Register, for details on configuring the MFUNC terminals.
Figure 3–7 illustrates a sample application using SPKROUT and CAUDPWM.
3–7
System
Core Logic
BINARY_SPKR
PWM_SPKR
SPKROUT
CAUDPWM
Speaker
Subsystem
PCI1410A
Figure 3–7. Sample Application of SPKROUT and CAUDPWM
3.5.8 LED Socket Activity Indicators
The socket activity LEDs indicate when a PC Card is being accessed. The LED_SKT signal can be routed to the
multifunction terminals. When configured for LED output, this terminal outputs an active high signal to indicate socket
activity. See Section 4.30, Multifunction Routing Register, for details on configuring the multifunction terminals.
The LED signal is active high and is driven in pulses of 64-ms duration. When the LED is not being driven high, it is
driven to a low state. Either of the two circuits shown in Figure 3–8 can be implemented to provide LED signaling,
and it is left for the board designer to implement the circuit that best fits the application.
The LED activity signals are valid when a card is inserted, powered, and not in reset. For PC Card-16, the LED activity
signal is pulsed when READY/IREQ is low. For CardBus cards, the LED activity signal is pulsed if CFRAME, CIRDY,
or CREQ is active.
Current Limiting
R ≈ 500 Ω
LED
PCI1410A
Current Limiting
R ≈ 500 Ω
Application-
Specific Delay
LED
PCI1410A
Figure 3–8. Two Sample LED Circuits
As indicated, the LED signals are driven for a period of 64 ms by a counter circuit. To avoid the possibility of the LED
appearing to be stuck when the PCI clock is stopped, the LED signaling is cut off when the SUSPEND signal is
asserted, when the PCI clock is to be stopped during the clock run protocol, or when in the D2 or D1 power state.
If any additional socket activity occurs during this counter cycle, the counter is reset and the LED signal remains
driven. If socket activity is frequent (at least once every 64 ms), the LED signal remains driven.
3.5.9 PC Card-16 Distributed DMA Support
The PCI1410A device supports a distributed DMA slave engine for 16-bit PC Card DMA support. The distributed DMA
(DDMA) slave register set provides the programmability necessary for the slave DMA engine. Table 3–2 provides the
DMA register configuration.
Two socket function-dependent PCI configuration header registers that are critical for DMA are the socket DMA
register 0 (PCI offset 94h, see Section 4.35) and the socket DMA register 1 (PCI offset 98h, see Section 4.36).
3–8
Distributed DMA is enabled through socket DMA register 0, and the contents of this register configure the PC Card-16
terminal (SPKR, IOIS16, or INPACK), which is used for the DMA request signal, DREQ. The base address of the DMA
slave registers and the transfer size (bytes or words) are programmed through the socket DMA register 1. See the
programming model and register descriptions in Section 7 for details.
Table 3–2. Distributed DMA Registers
DMA
TYPE
REGISTER NAME
BASE ADDRESS
OFFSET
R
W
R
Current address
Base address
Current count
Base count
Reserved
Reserved
Page
00h
04h
08h
0Ch
Reserved
Reserved
Reserved
W
R
N/A
Mode
N/A
Request
N/A
Status
W
R
Command
Multichannel
Mask
Reserved
W
Master clear
The DMA registers contain control and status information consistent with the 8237 DMA controller; however, the
register locations are reordered and expanded in some cases. While the DMA register definitions are identical to
those of the same name in the 8237 DMA controller, some register bits defined in the 8237 DMA controller do not
apply to distributed DMA in a PCI environment. In such cases, the PCI1410A device implements these obsolete
register bits as read-only, nonfunctional bits. The reserved registers shown in Table 3–2 are implemented as
read-only and return 0s when read. Write transactions to reserved registers have no effect.
The DMA transfer is prefaced by several configuration steps that are specific to the PC Card and must be completed
after the PC Card is inserted and interrogated. These steps include setting the proper DREQ signal assignment,
setting the data transfer width, and mapping and enabling the DMA register set. As discussed above, this is done
through socket DMA register 0 and socket DMA register 1. The DMA register set is then programmed similarly to an
8237 controller, and the PCI1410A device awaits a DREQ assertion from the PC Card requesting a DMA transfer.
DMA writes transfer data from the PC Card-to-PCI memory addresses. The PCI1410A device accepts data 8 or
16 bits at a time, depending on the programmed data width, and then requests access to the PCI bus by asserting
its REQ signal. Once the PCI bus is granted in an idle state, the PCI1410A device initiates a PCI memory write
command to the current memory address and transfers the data in a single data phase. After terminating the PCI
cycle, the PCI1410A device accepts the next byte(s) from the PC Card until the transfer count expires.
DMA reads transfer data from PCI memory addresses to the PC Card application. Upon the assertion of DREQ, the
PCI1410A device asserts REQ to acquire the PCI bus. Once the bus is granted in an idle state, the PCI1410A device
initiates a PCI memory read operation to the current memory address and accepts 8 or 16 bits of data, depending
on the programmed data width. After terminating the PCI cycle, the data is passed on to the PC Card. After terminating
the PC Card cycle, the PCI1410A device requests access to the PCI bus again, until the transfer count has expired.
The PCI1410A target interface acts normally during this procedure and accepts I/O reads and writes to the DMA
registers. While a DMA transfer is in progress and the host resets the DMA channel, the PCI1410A device asserts
TC and ends the PC Card cycle(s). TC is indicated in the DMA status register (DMA offset 08h, see Section 7.5). At
the PC Card interface, the PCI1410A device supports demand mode transfers. The PCI1410A device asserts DACK
during the transfer unless DREQ is deasserted before TC. TC is mapped to the OE PC Card terminal for DMA write
operations and is mapped to the WE PC Card terminal for DMA read operations. The DACK signal is mapped to the
PC Card REG signal in all transfers, and the DREQ terminal is routed to one of three options, which is programmed
through socket DMA register 0.
3–9
3.5.10 PC Card-16 PC/PCI DMA
Some chip sets provide a way for legacy I/O devices to do DMA transfers on the PCI bus. In the PC/PCI DMA protocol,
the PCI1410A device acts as a PCI target device to certain DMA-related I/O addresses. The PCI1410A PCREQ and
PCGNT signals are provided as a point-to-point connection to a chipset supporting PC/PCI DMA. The PCREQ and
PCGNT signals may be routed to the MFUNC2 and MFUNC5 terminals, respectively. See Section 4.30, Multifunction
Routing Register, for details on configuring the multifunction terminals.
Under the PC/PCI protocol, a PCI DMA slave device (such as the PCI1410A device) requests a DMA transfer on a
particular channel using a serialized protocol on PCREQ. The I/O DMA bus master arbitrates for the PCI bus and
grants the channel through a serialized protocol on PCGNT when it is ready for the transfer. The I/O cycle and memory
cycles are then presented on the PCI bus, which performs the DMA transfers similarly to legacy DMA master devices.
PC/PCI DMA is enabled for each PC Card-16 slot by setting bit 19 (CDREQEN) in the respective system control
register (PCI offset 80h, see Section 4.29). On power up, this bit is reset and the card PC/PCI DMA is disabled. Bit 3
(CDMA_EN) of the system control register is a global enable for PC/PCI DMA, and is set at power up and never
cleared if the PC/PCI DMA mechanism is implemented. The desired DMA channel for each PC Card-16 slot must
be configured through bits 18–16 (CDMACHAN field) in the system control register. The channels are configured as
indicated in Table 3–3.
Table 3–3. PC/PCI Channel Assignments
SYSTEM CONTROL
CHANNEL TRANSFER
DATA WIDTH
REGISTER
DMA CHANNEL
BIT 18
BIT 17
BIT16
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
8-bit DMA transfers
8-bit DMA transfers
8-bit DMA transfers
8-bit DMA transfers
Not used
16-bit DMA transfers
16-bit DMA transfers
16-bit DMA transfers
As in distributed DMA, the PC Card terminal mapped to DREQ must be configured through socket DMA register 0
(PCI offset 94h, see Section 4.35). The data transfer width is a function of channel number, and the DMA slave
registers are not used. When a DREQ is received from a PC Card and the channel has been granted, the PCI1410A
device decodes the I/O addresses listed in Table 3–4 and performs actions dependent upon the address.
Table 3–4. I/O Addresses Used for PC/PCI DMA
DMA I/O ADDRESS
DMA CYCLE TYPE
Normal
TERMINAL COUNT
PCI CYCLE TYPE
I/O read/write
I/O read/write
I/O read
00h
04h
C0h
C4h
0
1
0
1
Normal TC
Verify
Verify TC
I/O read
When the PC/PCI DMA is used as a PC Card-16 DMA mechanism, it may not provide the performance levels of DMA;
however, the design of a PCI target implementing PC/PCI DMA is considerably less complex. No bus master state
machine is required to support PC/PCI DMA, since the DMA control is centralized in the chipset. This DMA scheme
often is referred to as centralized DMA for this reason.
3.5.11 CardBus Socket Registers
The PCI1410A device contains all registers for compatibility with the PC Card Standard. These registers exist as the
CardBus socket registers and are listed in Table 3–5.
3–10
Table 3–5. CardBus Socket Registers
REGISTER NAME
OFFSET
Socket event
Socket mask
00h
04h
08h
0Ch
10h
14h
18h
1Ch
20h
Socket present state
Socket force event
Socket control
Reserved
Reserved
Reserved
Socket power management
3.6 Serial Bus Interface
The PCI1410A device provides a serial bus interface to load subsystem identification and select register defaults
2
through a serial EEPROM and to provide a PC Card power switch interface alternative to P C. See Section 3.5.2,
2
2
P C Power-Switch Interface (TPS2211), for details. The PCI1410A serial bus interface is compatible with various I C
and SMBus components.
3.6.1 Serial Bus-Interface Implementation
To enable the serial interface, a pullup resistor must be implemented on the VCCD0 and VCCD1 terminals and the
appropriate pullup resistors must be implemented on the SDA and SCL signals, that is, the MFUNC1 and MFUNC4
terminals. When the interface is detected, bit 3 (SBDETECT) in the serial bus control and status register (PCI offset
B3h, see Section 4.50) is set. The SBDETECT bit is cleared by a writeback of 1.
The PCI1410A device implements a two-pin serial interface with one clock signal (SCL) and one data signal (SDA).
When pullup resistors are provided on the VCCD0 and VCCD1 terminals, the SCL signal is mapped to the MFUNC4
terminal and the SDA signal is mapped to the MFUNC1 terminal. The PCI1410A device drives SCL at nearly 100 kHz
2
during data transfers, which is the maximum specified frequency for standard-mode I C. The serial EEPROM must
be located at address A0h. Figure 3–9 illustrates an example application implementing the two-wire serial bus.
V
CC
Serial
EEPROM
5 V
PCI1410A
VCCD0
VCCD1
A2
A1
A0
MFUNC4
MFUNC1
SCL
SDA
Figure 3–9. Serial EEPROM Application
Some serial device applications may include PC Card power switches, ZV source switches, card ejectors, or other
devices that may enhance the user’s PC Card experience. The serial EEPROM device and PC Card power switches
are discussed in the sections that follow.
3.6.2 Serial Bus-Interface Protocol
The SCL and SDA signals are bidirectional, open-drain signals and require pullup resistors as shown in Figure 3–9.
2
The PCI1410A device supports up to 100-Kb/s data transfer rate and is compatible with standard-mode I C using
7-bit addressing.
3–11
All data transfers are initiated by the serial bus master. The beginning of a data transfer is indicated by a start
condition, which is signaled when the SDA line transitions to a low state while SCL is in the high state, as illustrated
in Figure 3–10. The end of a requested data transfer is indicated by a stop condition, which is signaled by a low-to-high
transition of SDA while SCL is in the high state, as shown in Figure 3–10. Data on SDA must remain stable during
the high state of the SCL signal, as changes on the SDA signal during the high state of SCL are interpreted as control
signals, that is, a start or a stop condition.
SDA
SCL
Start
Condition
Stop
Condition
Change of
Data Allowed
Data Line Stable,
Data Valid
Figure 3–10. Serial Bus Start/Stop Conditions and Bit Transfers
Data is transferred serially in 8-bit bytes. The number of bytes that can be transmitted during a data transfer is
unlimited; however, each byte must be completed with an acknowledge bit. An acknowledge (ACK) is indicated by
the receiver pulling the SDA signal low so that it remains low during the high state of the SCL signal. Figure 3–11
illustrates the acknowledge protocol.
SCL From
1
2
3
7
8
9
Master
SDA Output
By Transmitter
SDA Output
By Receiver
Figure 3–11. Serial Bus-Protocol Acknowledge
The PCI1410A device is a serial bus master; all other devices connected to the serial bus external to the PCI1410A
device are slave devices. As the bus master, the PCI1410A device drives the SCL clock at nearly 100 kHz during
bus cycles and places SCL in a high-impedance state (zero frequency) during idle states.
Typically, the PCI1410A device masters byte reads and byte writes under software control. Doubleword reads are
performed by the serial EEPROM initialization circuitry upon a PCI reset, and may not be generated under software
control. See Section 3.6.3, Serial Bus EEPROM Application, for details on how the PCI1410A device automatically
loads the subsystem identification and other register defaults through a serial bus EEPROM.
Figure 3–12 illustrates a byte write. The PCI1410A device issues a start condition and sends the 7-bit slave device
address and the command bit 0. A 0 in the R/W command bit indicates that the data transfer is a write. The slave
device acknowledges if it recognizes the address. If there is no acknowledgment received by the PCI1410A device,
an appropriate status bit is set in the serial bus control and status register (PCI offset B3h, see Section 4.50). The
word address byte is then sent by the PCI1410A device and another slave acknowledgment is expected. The
PCI1410A device then delivers the data byte, MSB first, and expects a final acknowledgment before issuing the stop
condition.
3–12
Slave Address
Word Address
Data Byte
S
b6 b5 b4 b3 b2 b1 b0
0
A
b7 b6 b5 b4 b3 b2 b1 b0
A
b7 b6 b5 b4 b3 b2 b1 b0
A
P
R/W
A = Slave Acknowledgement
S/P = Start/Stop Condition
Figure 3–12. Serial Bus Protocol – Byte Write
Figure 3–13 illustrates a byte read. The read protocol is very similar to the write protocol, except the R/W command
bit must be set to 1 to indicate a read-data transfer. In addition, the PCI1410A master must acknowledge reception
of the read bytes from the slave transmitter. The slave transmitter drives the SDA signal during read data transfers.
The SCL signal remains driven by the PCI1410A master.
Slave Address
Word Address
S
b6 b5 b4 b3 b2 b1 b0
1
A
b7 b6 b5 b4 b3 b2 b1 b0
A
R/W
Data Byte
Slave Address
A
b7 b6 b5 b4 b3 b2 b1 b0
M
P
b6 b5 b4 b3 b2 b1 b0
A = Slave Acknowledgement
S/P = Start/Stop Condition
Figure 3–13. Serial Bus Protocol – Byte Read
Figure 3–14 illustrates EEPROM interface doubleword data-collection protocol.
Slave Address
Word Address
Slave Address
S
1
0
1
0
0
0
0
0
A
b7 b6 b5 b4 b3 b2 b1 b0
A
S
1
0
1
0
0
0
0
1
A
Start
R/W
Restart
R/W
Data Byte 3
M
Data Byte 2
M
Data Byte 1
M
Data Byte 0
M
P
A = Slave Acknowledgement
M = Master Acknowledgement
S/P = Start/Stop Condition
Figure 3–14. EEPROM Interface Doubleword Data Collection
3.6.3 Serial Bus EEPROM Application
When the PCI bus is reset and the serial bus interface is detected, the PCI1410A device attempts to read the
subsystem identification and other register defaults from a serial EEPROM. The registers and corresponding bits that
may be loaded with defaults through the EEPROM are provided in Table 3–6.
Table 3–6. Registers and Bits Loadable Through Serial EEPROM
OFFSET
REFERENCE
PCI OFFSET
REGISTER
BITS LOADED FROM EEPROM
01h
02h
03h
04h
40h
80h
8Ch
90h
Subsystem vendor ID, subsystem ID
System control
31–0
31–30, 27, 26, 24, 15, 14, 6–3, 1
27–0
Multifunction routing
Retry status, card control, device control, diagnostic
31, 28–24, 22, 19–16, 15, 7, 6
3–13
Figure 3–15 details the EEPROM data format. This format must be followed for the PCI1410A device to properly load
initializations from a serial EEPROM. Any undefined condition results in a terminated load and sets bit 0 (ROM_ERR)
in the serial bus control and status register (PCI offset B3h, see Section 4.50).
Slave Address = 1010 000
Reference(0)
Byte 3 (0)
Byte 2 (0)
Byte 1 (0)
Byte 0 (0)
RSVD
Word Address 00h
Word Address 01h
Word Address 02h
Word Address 03h
Word Address 04h
Reference(n)
Byte 3 (n)
Byte 2 (n)
Byte 1 (n)
Byte 0 (n)
RSVD
Word Address 8 × (n–1)
Word Address 8 × (n–1) + 1
Word Address 8 × (n–1) + 2
Word Address 8 × (n–1) + 3
Word Address 8 × (n–1) + 4
RSVD
RSVD
RSVD
Reference(1)
Word Address 08h
RSVD
EOL
Word Address 8 × (n)
Figure 3–15. EEPROM Data Format
The byte at the EEPROM word address 00h must contain either a valid offset reference, as listed in Table 3–6, or
an end-of-list (EOL) indicator. The EOL indicator has a byte value of FFh, and indicates the end of the data to load
from the EEPROM. Only doubleword registers are loaded from the EEPROM, and all bit fields must be considered
when programming the EEPROM.
The serial EEPROM is addressed at slave address 1010 000b by the PCI1410A device. All hardware address bits
for the EEPROM should be tied to the appropriate level to achieve this address. The serial EEPROM chip in the
sample application circuit (Figure 3–9) assumes the 1010b high address nibble. The lower three address bits are
terminal inputs to the chip, and the sample application shows these terminal inputs tied to GND.
When a valid offset reference is read, four bytes are read from the EEPROM, MSB first, as illustrated in Figure 3–14.
The address autoincrements after every byte transfer according to the doubleword read protocol. Note that the word
addresses align with the data format illustrated in Figure 3–15. The PCI1410A device continues to load data from
the serial EEPROM until an end-of-list indicator is read. Three reserved bytes are stuffed to maintain 8-byte data
structures.
Note, the 8-byte data structure is important to provide correct addressing per the doubleword read format shown in
Figure 3–14. In addition, the reference offsets must be loaded in the EEPROM in sequential order, that is, 01h, 02h,
03h, 04h. If the offsets are not sequential, the registers will be loaded incorrectly.
3.6.4 Accessing Serial Bus Devices Through Software
The PCI1410A device provides a programming mechanism to control serial bus devices through software. The
programming is accomplished through a doubleword of PCI configuration space at offset B0h. Table 3–7 lists the
registers used to program a serial bus device through software.
3–14
Table 3–7. PCI1410A Registers Used to Program Serial Bus Devices
PCI OFFSET
REGISTER NAME
DESCRIPTION
B0h
Serial bus data
Contains the data byte to send on write commands or the received data byte on read commands
The content of this register is sent as the word address on byte writes or reads. This register is not used
in the quick command protocol.
B1h
B2h
B3h
Serial bus index
Serial bus slave
address
Write transactions to this register initiate a serial bus transaction. The slave device address and the R/W
command selector are programmed through this register.
Serial bus control
and status
Read data valid, general busy, and general error status are communicated through this register. In
addition, the protocol select bit is programmed through this register.
To write a byte, the serial bus data register must be programmed with the data, the serial bus index register must be
programmed with the byte address, and the serial bus slave address register must be programmed with the 7-bit slave
address (SLAVADDR field) and bit 0 (RWCMD) must be reset.
On byte reads, the byte address is programmed into the serial bus index register, the serial bus slave address register
must be programmed with the 7-bit slave address (SLAVADDR field) and bit 0 (RWCMD) must be set, and bit 5
(REQBUSY) in the serial bus control and status register (PCI offset B3h, see Section 4.50) must be polled until clear.
Then the contents of the serial bus data register are valid read data from the serial bus interface.
3.7 Programmable Interrupt Subsystem
Interrupts provide a way for I/O devices to let the microprocessor know that they require servicing. The dynamic
nature of PC Cards and the abundance of PC Card I/O applications require substantial interrupt support from the
PCI1410A device. The PCI1410A device provides several interrupt signaling schemes to accommodate the needs
of a variety of platforms. The different mechanisms for dealing with interrupts in this device are based on various
specifications and industry standards. The ExCA register set provides interrupt control for some 16-bit PC Card
functions, and the CardBus socket register set provides interrupt control for the CardBus PC Card functions. The
PCI1410A device is, therefore, backward compatible with existing interrupt control register definitions, and new
registers have been defined where required.
The PCI1410A device detects PC Card interrupts and events at the PC Card interface and notifies the host controller,
using one of several interrupt signaling protocols. To simplify the discussion of interrupts in the PCI1410A device,
PC Card interrupts are classified either as card status change (CSC) or as functional interrupts.
The method by which any type of PCI1410A interrupt is communicated to the host interrupt controller varies from
system to system. The PCI1410A device offers system designers the choice of using parallel PCI interrupt signaling,
parallel ISA-type IRQ interrupt signaling, or the IRQSER serialized ISA and/or PCI interrupt protocol. It is possible
to use the parallel PCI interrupts in combination with either parallel IRQs or serialized IRQs, as detailed in the sections
that follow. All interrupt signaling is provided through the seven multifunction terminals, MFUNC0–MFUNC6.
3.7.1 PC Card Functional and Card Status Change Interrupts
PC Card functional interrupts are defined as requests from a PC Card application for interrupt service and are
indicated by asserting specially defined signals on the PC Card interface. Functional interrupts are generated by
16-bit I/O PC Cards and by CardBus PC Cards.
Card status change (CSC)-type interrupts are defined as events at the PC Card interface that are detected by the
PCI1410A device, and may warrant notification of host card and socket services software for service. CSC events
include both card insertion and removal from PC Card sockets, as well as transitions of certain PC Card signals.
Table 3–8 summarizes the sources of PC Card interrupts and the type of card associated with them. CSC and
functional interrupt sources are dependent on the type of card inserted in the PC Card socket. The three types of cards
that can be inserted into any PC Card socket are:
•
•
•
16-bit memory cards
16-bit I/O cards
CardBus cards
3–15
Functional interrupt events are valid only for 16-bit I/O and CardBus cards; that is, the functional interrupts are not
valid for 16-bit memory cards. Furthermore, card insertion and removal-type CSC interrupts are independent of the
card type.
Table 3–8. PC Card Interrupt Events and Description
CARD TYPE
EVENT
TYPE
SIGNAL
DESCRIPTION
A transition on BVD1 indicates a change in the
PC Card battery conditions.
BVD1(STSCHG)//CSTSCHG
Battery conditions
(BVD1, BVD2)
CSC
A transition on BVD2 indicates a change in the
PC Card battery conditions.
16-bit
memory
BVD2(SPKR)//CAUDIO
READY(IREQ)//CINT
Wait states
(READY)
A transition on READY indicates a change in the ability
of the memory PC Card to accept or provide data.
CSC
CSC
Change in card
status (STSCHG)
The assertion of STSCHG indicates a status change
on the PC Card.
BVD1(STSCHG)//CSTSCHG
READY(IREQ)//CINT
16-bit I/O
CardBus
Interrupt request
(IREQ)
The assertion of IREQ indicates an interrupt request
from the PC Card.
Functional
CSC
Change in card
status (CSTSCHG)
The assertion of CSTSCHG indicates a status change
on the PC Card.
BVD1(STSCHG)//CSTSCHG
READY(IREQ)//CINT
Interrupt request
(CINT)
The assertion of CINT indicates an interrupt request
from the PC Card.
Functional
A transition on either CD1//CCD1 or CD2//CCD2
indicates an insertion or removal of a 16-bit or CardBus
PC Card.
Card insertion
or removal
CD1//CCD1,
CD2//CCD2
CSC
CSC
All PC Cards
Power cycle
complete
An interrupt is generated when a PC Card power-up
cycle has completed.
N/A
The naming convention for PC Card signals describes the function for 16-bit memory, I/O cards, and CardBus. For
example, READY(IREQ)//CINT includes READY for 16-bit memory cards, IREQ for 16-bit I/O cards, and CINT for
CardBus cards. The 16-bit memory card signal name is first, with the I/O card signal name second, enclosed in
parentheses. The CardBus signal name follows after a double slash (//).
The PC Card Standard describes the power-up sequence that must be followed by the PCI1410A device when an
insertion event occurs and the host requests that the socket V
and V
be powered. Upon completion of this
CC
PP
power-up sequence, the PCI1410A interrupt scheme can be used to notify the host system (see Table 3–8), denoted
by the power cycle complete event. This interrupt source is considered a PCI1410A internal event because it depends
on the completion of applying power to the socket rather than on a signal change at the PC Card interface.
3.7.2 Interrupt Masks and Flags
Host software may individually mask (or disable) most of the potential interrupt sources listed in Table 3–8 by setting
the appropriate bits in the PCI1410A device. By individually masking the interrupt sources listed, software can control
those events that cause a PCI1410A interrupt. Host software has some control over the system interrupt the
PCI1410A device asserts by programming the appropriate routing registers. The PCI1410A device allows host
software to route PC Card CSC and PC Card functional interrupts to separate system interrupts. Interrupt routing is
somewhat specific to the interrupt signaling method used. This is discussed in more detail in the following sections.
When an interrupt is signaled by the PCI1410A device, the interrupt service routine must determine which of the
events listed in Table 3–9 caused the interrupt. Internal registers in the PCI1410A device provide flags that report the
source of an interrupt. By reading these status bits, the interrupt service routine can determine the action to be taken.
Table 3–9 details the registers and bits associated with masking and reporting potential interrupts. All interrupts can
be masked, except the functional PC Card interrupts, and an interrupt status flag is available for all types of interrupts.
3–16
Table 3–9. Interrupt Mask and Flag Registers
CARD TYPE
EVENT
MASK
FLAG
Battery conditions
(BVD1, BVD2)
ExCA offset 05h/805h
bits 1 and 0
ExCA offset 04h/804h
bits 1 and 0
16-bit
memory
Wait states
(READY)
ExCA offset 05h/805h
bit 2
ExCA offset 04h/804h
bit 2
Change in card status
(STSCHG)
ExCA offset 05h/805h
bit 0
ExCA offset 04h/804h
bit 0
16-bit I/O
Interrupt request
(IREQ)
PCI configuration offset 91h
bit 0
Always enabled
All 16-bit
PC Cards
ExCA offset 05h/805h
bit 3
ExCA offset 04h/804h
bit 3
Power cycle complete
Change in card status
(CSTSCHG)
Socket mask
bit 0
Socket event
bit 0
Interrupt request
(CINT)
PCI configuration offset 91h
bit 0
Always enabled
CardBus
Socket mask
bit 3
Socket event
bit 3
Power cycle complete
Card insertion or
removal
Socket mask
bits 2 and 1
Socket event
bits 2 and 1
Notice that there is not a mask bit to stop the PCI1410A device from passing PC Card functional interrupts through
to the appropriate interrupt scheme. These interrupts are not valid until the card is properly powered, and there never
should be a card interrupt that does not require service after proper initialization.
Table 3–9 lists the various methods of clearing the interrupt flag bits. The flag bits in the ExCA registers (16-bit PC
Card-related interrupt flags) can be cleared using two different methods. One method is an explicit write of 1 to the
flag bit to clear, and the other is by reading the flag bit register. The selection of flag bit clearing is made by bit 2
(IFCMODE) in the ExCA global control register (ExCA offset 1Eh, see Section 5.20) and defaults to the flag cleared
on read method.
The CardBus-related interrupt flags can be cleared by an explicit write of 1 to the interrupt flag in the socket force event
register (CardBus offset 0Ch, see Section 6.4). Although some of the functionality is shared between the CardBus
registers and the ExCA registers, software should not program the chip through both register sets when a CardBus
card is functioning.
3.7.3 Using Parallel IRQ Interrupts
The seven multifunction terminals, MFUNC6–MFUNC0, implemented in the PCI1410A device may be routed to
obtain a subset of the ISA IRQs . The IRQ choices provide ultimate flexibility in PC Card host interruptions. To use
the parallel ISA type IRQ interrupt signaling, software must program the device control register (PCI offset 92h, see
Section 4.33), to select the parallel IRQ signaling scheme. See Section 4.30, Multifunction Routing Register, for
details on configuring the multifunction terminals.
A system using parallel IRQs requires a minimum of one PCI terminal, INTA, to signal CSC events. This requirement
is dictated by certain card and socket services software. The INTA requirement calls for routing the MFUNC0 terminal
for INTA signaling. This leaves (at a maximum) six different IRQs to support legacy 16-bit PC Card functions.
As an example, suppose the six IRQs used by legacy PC Card applications are IRQ3, IRQ4, IRQ5, IRQ10, IRQ11,
and IRQ15. The multifunction routing register must be programmed to a value of 0FBA 5432h. This value routes the
MFUNC0 terminal to INTA signaling and routes the remaining terminals as illustrated in Figure 3–16. Not shown is
that INTA also must be routed to the programmable interrupt controller (PIC), or to some circuitry that provides parallel
PCI interrupts to the host.
3–17
PCI1410A
MFUNC1
PIC
IRQ3
MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6
IRQ4
IRQ5
IRQ10
IRQ11
IRQ15
Figure 3–16. IRQ Implementation
Power-on software is responsible for programming the multifunction routing register to reflect the IRQ configuration
of a system implementing the PCI1410A device. See Section 4.30, Multifunction Routing Register, for details on
configuring the multifunction terminals.
The parallel ISA-type IRQ signaling from the MFUNC6–MFUNC0 terminals is compatible with those input directly into
the 8259 PIC. The parallel IRQ option is provided for system designs that require legacy ISA IRQs. Design constraints
may demand more MFUNC6–MFUNC0 IRQ terminals than the PCI1410A device makes available.
3.7.4 Using Parallel PCI Interrupts
Parallel PCI interrupts are available when exclusively in parallel PCI interrupt mode, parallel ISA IRQ signaling mode,
and when only IRQs are serialized with the IRQSER protocol. The socket function interrupts are routed to INTA
(MFUNC0).
3.7.5 Using Serialized IRQSER Interrupts
The serialized interrupt protocol implemented in the PCI1410A device uses a single terminal to communicate all
interrupt status information to the host controller. The protocol defines a serial packet consisting of a start cycle,
multiple interrupt indication cycles, and a stop cycle. All data in the packet is synchronous with the PCI clock. The
packet data describes 16 parallel ISA IRQ signals and the optional 4 PCI interrupts INTA, INTB, INTC, and INTD. For
details on the IRQSER protocol, refer to the document Serialized IRQ Support for PCI Systems.
3.7.6 SMI Support in the PCI1410A Device
The PCI1410A device provides a mechanism for interrupting the system when power changes have been made to
the PC Card socket interfaces. The interrupt mechanism is designed to fit into a system maintenance interrupt (SMI)
scheme. SMI interrupts are generated by the PCI1410A device, when enabled, after a write cycle to either the socket
control register (CardBus offset 10h, see Section 6.5) of the CardBus register set or the ExCA power control register
(ExCA offset 02h, see Section 5.3) causes a power cycle change sequence to be sent on the power-switch interface.
The SMI control is programmed through three bits in the system control register (PCI offset 80h, see Section 4.29).
These bits are SMIROUTE (bit 26), SMISTATUS (bit 25), and SMIENB (bit 24). Table 3–10 describes the SMI control
bits function.
Table 3–10. SMI Control
BIT NAME
SMIROUTE
SMISTATUS
SMIENB
FUNCTION
This shared bit controls whether the SMI interrupts are sent as a CSC interrupt or as IRQ2.
This socket-dependent bit is set when an SMI interrupt is pending. This status flag is cleared by writing back a 1.
When set, SMI interrupt generation is enabled.
If CSC SMI interrupts are selected, the SMI interrupt is sent as the CSC. The CSC interrupt can be either level or edge
mode, depending upon bit 1 (CSCMODE) in the ExCA global control register (ExCA offset 1Eh, see Section 5.20).
If IRQ2 is selected by SMIROUTE, the IRQSER signaling protocol supports SMI signaling in the IRQ2 IRQ/Data slot.
In a parallel ISA IRQ system, the support for an active low IRQ2 is provided only if IRQ2 is routed to either MFUNC1,
MFUNC3, or MFUNC6 through the multifunction routing register (PCI offset 8Ch, see Section 4.30).
3–18
3.8 Power-Management Overview
In addition to the low-power CMOS technology process used for the PCI1410A device, various features are designed
into the device to allow implementation of popular power-saving techniques. These features and techniques are
discussed in this section.
3.8.1 Clock-Run Protocol
The PCI CLKRUN feature is the primary method of power management on the PCI interface of the PCI1410A device.
CLKRUN signaling is provided through the MFUNC6 terminal. Because some chipsets do not implement CLKRUN,
this is not always available to the system designer, and alternate power-saving features are provided. For details on
the CLKRUN protocol see the PCI Mobile Design Guide.
The PCI1410A device does not permit the central resource to stop the PCI clock under any of the following conditions:
•
•
•
•
•
•
Bit 1 (KEEPCLK) in the system control register (PCI offset 80h, see Section 4.29) is set.
The PC Card-16 resource manager is busy.
The PCI1410A CardBus master state machine is busy. A cycle may be in progress on CardBus.
The PCI1410A master is busy. There may be posted data from CardBus to PCI in the PCI1410A device.
Interrupts are pending.
The CardBus CCLK for either socket has not been stopped by the PCI1410A CCLKRUN manager.
The PCI1410A device restarts the PCI clock using the CLKRUN protocol under any of the following conditions:
•
•
•
•
•
A PC Card-16 IREQ or a CardBus CINT has been asserted.
A CardBus CBWAKE (CSTSCHG) or PC Card-16 STSCHG/RI event occurs.
A CardBus attempts to start the CCLK using CCLKRUN.
A CardBus card arbitrates for the CardBus bus using CREQ.
A 16-bit DMA PC Card asserts DREQ.
3.8.2 CardBus PC Card Power Management
The PCI1410A device implements its own card power-management engine that can turn off CCLK to a socket when
there is no activity to the CardBus PC Card. The PCI clock-run protocol is followed on the CardBus CCLKRUN
interface to control this clock management.
3.8.3 16-Bit PC Card Power Management
Bit 7 (COE) in the ExCA power control register (ExCA offset 02h, see Section 5.3) and bit 0 (PWRDWN) in the ExCA
global control register (ExCA offset 1Eh, see Section 5.20) are provided for 16-bit PC Card power management. The
COE bit places the card interface in a high-impedance state to save power. The power savings when using this feature
are minimal. The COE bit will reset the PC Card when used, and the PWRDWN bit will not. Furthermore, the
PWRDWN bit is an automatic COE, that is, the PWRDWN performs the COE function when there is no card activity.
NOTE: The 16-bit PC Card must implement the proper pullup resistors for the COE and
PWRDWN modes.
3–19
3.8.4 Suspend Mode
The SUSPEND signal, provided for backward compatibility, gates the PRST (PCI reset) signal and the GRST (global
reset) signal from the PCI1410A device. Besides gating PRST and GRST, SUSPEND also gates PCLK inside the
PCI1410A device to minimize power consumption.
Gating PCLK does not create any issues with respect to the power-switch interface in the PCI1410A device. This is
because the PCI1410A device does not depend on the PCI clock to clock the power-switch interface. There are two
methods to clock the power-switch interface in the PCI1410A device:
•
•
Use an external clock to the PCI1410A PCLK terminal.
Use the internal oscillator.
It also should be noted that asynchronous signals, such as card status-change interrupts and RI_OUT, can be passed
to the host system without a PCI clock. However, if card status-change interrupts are routed over the serial interrupt
stream, the PCI clock must be restarted to pass the interrupt, because neither the internal oscillator nor an external
clock is routed to the serial interrupt state machine. Figure 3–17 shows the suspend logic diagram.
xRST
xRSTIN
PCI1410A
Core
SUSPEND
GNT
SUSPENDIN
PCLKIN
PCLK
Figure 3–17. Suspend Logic Diagram
Figure 3–18 is a signal diagram of the suspend function.
3–20
xRST
GNT
SUSPEND
PCLK
External Terminals
Internal Signals
xRSTIN
SUSPENDIN
PCLKIN
Figure 3–18. Signal Diagram of Suspend Function
3.8.5 Requirements for Suspend Mode
The suspend mode prevents the clearing of all register contents on the assertion of reset (PRST or GRST) that would
require the reconfiguration of the PCI1410A device by software. Asserting the SUSPEND signal places the controller
PCI outputs in a high-impedance state and gates the PCLK signal internally to the controller unless a PCI transaction
currently is in process (GNT is asserted). It is important that the PCI bus not be parked on the PCI1410A device when
SUSPEND is asserted, because the outputs are in a high-impedance state.
The GPIOs, MFUNC signals, and RI_OUT signals are all active during SUSPEND, unless they are disabled in the
appropriate PCI1410A registers.
3.8.6 Ring Indicate
The RI_OUT output is an important feature in power management, allowing a system to go into a suspended mode
and wake up on modem rings and other card events. TI-designed flexibility permits this signal to fit wide platform
requirements. RI_OUT on the PCI1410A device can be asserted under any of the following conditions:
•
A 16-bit PC Card modem in a powered socket asserts RI to indicate to the system the presence of an
incoming call.
•
•
A powered-down CardBus card asserts CSTSCHG (CBWAKE), requesting system and interface wake-up.
A powered CardBus card asserts CSTSCHG from the insertion/removal of cards or change in battery
voltage levels.
Figure 3–19 shows various enable bits for the PCI1410A RI_OUT function; however, it does not show the masking
of CSC events. See Table 3–9 for a detailed description of CSC interrupt masks and flags.
3–21
RI_OUT Function
CSTSMASK
RIENB
PC Card
Socket
RINGEN
Card
I/F
RI_OUT
CDRESUME
Figure 3–19. RI_OUT Functional Diagram
RI from the 16-bit PC Card interface is masked by bit 7 (RINGEN) in the ExCA interrupt and general control register
(ExCA offset 03h, see Section 5.4). This is programmed on a per-socket basis and is applicable only when a 16-bit
card is powered in the socket.
The CBWAKE, signaling to RI_OUT, is enabled through the same mask as the CSC event for CSTSCHG. The mask
bit (bit 0, CSTSMASK) is programmed through the socket mask register (CardBus offset 04h, see Section 6.2) in the
CardBus socket registers.
3.8.7 PCI Power Management
The PCI Bus Power Management Interface Specification for PCI to CardBus Bridges establishes the infrastructure
required for the operating system to control the power of PCI functions. This is done by defining a standard PCI
interface and operations to manage the power of PCI functions on the bus. The PCI bus and the PCI functions can
be assigned one of four software-visible power-management states that result in varying levels of power savings.
The four power-management states of PCI functions are:
•
•
•
D0 – Fully-on state
D1 and D2 – Intermediate states
D3 – Off state
Similarly, bus power states of the PCI bus are B0–B3. The bus power states B0–B3 are derived from the device power
state of the originating bridge device.
For the operating system (OS) to manage the device power states on the PCI bus, the PCI function must support four
power-management operations. These operations are:
•
•
•
•
Capabilities reporting
Power status reporting
Setting the power state
System wake-up
The OS identifies the capabilities of the PCI function by traversing the new capabilities list. The presence of
capabilities, in addition to the standard PCI capabilities, is indicated by a 1 in bit 4 (CAPLIST) of the status register
(PCI offset 06h, see Section 4.5).
The capabilities pointer provides access to the first item in the linked list of capabilities. For the PCI1410A device,
a CardBus bridge with PCI configuration space header type 2, the capabilities pointer is mapped to an offset of 14h.
The first byte of each capability register block is required to be a unique ID of that capability. PCI power management
has been assigned an ID of 01h. The next byte is a pointer to the next pointer item in the list of capabilities. If there
are no more items in the list, the next item pointer should be set to 0. The registers following the next item pointer
are specific to the capabilities of their corresponding power-management functions. The PCI power-management
capability implements the register block outlined in Table 3–11.
3–22
Table 3–11. Power-Management Registers
REGISTER NAME
OFFSET
A0h
Power management capabilities
PMCSR bridge support extensions
Next-item pointer
Capability ID
PM data
Power management control/status
A4h
The power management capabilities register (PCI offset A2h, see Section 4.39) provides information on the
capabilities of the function related to power management. The power management control/status register (PCI offset
A4h, see Section 4.40) enables control of power management states and enables/monitors power management
events. The data register is an optional register that can provide dynamic data.
For more information on PCI power management, see the PCI Bus Power Management Interface Specification for
PCI to CardBus Bridges.
3.8.8 CardBus Device Class Power Management
The PCI Bus Power Management Interface Specification for PCI to CardBus Bridges was approved by PCMCIA in
December of 1997. This specification follows the device and bus state definitions provided in the PCI Bus Power
Management Interface Specification published by the PCI Special Interest Group (SIG). The main issue addressed
in the PCI Bus Power Management Interface Specification for PCI to CardBus Bridges is wake-up from D3 or D3
without losing wake-up context (also called PME context).
hot
cold
The specific issues addressed by the PCI Bus Power Management Interface Specification for PCI to CardBus Bridges
for D3 wake up are as follows:
•
Preservation of device context: The specification states that a reset must occur when transitioning from D3
to D0. Some method to preserve wake-up context must be implemented so that the reset does not clear
the PME context registers.
•
Power source in D3
if wake-up support is required from this state.
cold
The Texas Instruments PCI1410A device addresses these D3 wake-up issues in the following manner:
• Two resets are provided to handle preservation of PME context bits:
–
Global reset (GRST) is used only on the initial boot up of the system after power up. It places the
PCI1410A device in its default state and requires BIOS to configure the device before becoming fully
functional.
–
PCI reset (PRST) now has dual functionality based on whether PME is enabled or not. If PME is
enabled, PME context is preserved. If PME is not enabled, PRST acts the same as a normal PCI reset.
Please see the master list of PME context bits in Section 3.8.10.
•
Power source in D3
auxiliary power source must be supplied to the PCI1410A V
if wake-up support is required from this state. Since V
is removed in D3
, an
cold
CC
cold
terminals. Consult the PCI14xx
CC
Implementation Guide for D3 Wake-Up or the PCI Power Management Interface Specification for PCI to
CardBus Bridges for further information.
3.8.9 ACPI Support
The Advanced Configuration and Power Interface (ACPI) Specification provides a mechanism that allows unique
pieces of hardware to be described to the ACPI driver. The PCI1410A device offers a generic interface that is
compliant with ACPI design rules.
Two doublewords of general-purpose ACPI programming bits reside in PCI1410A PCI configuration space at offset
A8h. The programming model is broken into status and control functions. In compliance with ACPI, the top-level event
status and enable bits reside in the general-purpose event status (PCI offset A8h, see Section 4.43) and
general-purpose event enable (PCI offset AAh, see Section 4.44) registers. The status and enable bits are
implemented as defined by ACPI and illustrated in Figure 3–20.
3–23
Status Bit
Event Input
Enable Bit
Event Output
Figure 3–20. Block Diagram of a Status/Enable Cell
The status and enable bits generate an event that allows the ACPI driver to call a control method associated with the
pending status bit. The control method can then control the hardware by manipulating the hardware control bits or
by investigating child status bits and calling their respective control methods. A hierarchical implementation would
be somewhat limiting, however, as upstream devices would have to remain in some level of power state to report
events.
For more information on ACPI, see the Advanced Configuration and Power Interface (ACPI) Specification.
3.8.10 Master List of PME Context Bits and Global Reset-Only Bits
If the PME enable bit (bit 8) of the power management control/status register (PCI offset A4h, see Section 4.40) is
asserted, the assertion of PRST will not clear the following PME context bits. If the PME enable bit is not asserted,
the PME context bits are cleared with PRST. The PME context bits are:
•
•
•
•
•
•
•
•
•
•
Bridge control register (PCI offset 3Eh, see Section 4.25): bit 6
Power management capabilities register (PCI offset A2h, see Section 4.39): bit 15
Power management control/status register (PCI offset A4h, see Section 4.40): bits 15, 8
ExCA power control register (ExCA offset 802h, see Section 5.3): bits 4, 3, 1, 0
ExCA interrupt and general control (ExCA offset 803h, see Section 5.4): bits 6, 5
ExCA card status-change-interrupt configuration register (ExCA offset 805h, see Section 5.6): bits 3–0
CardBus socket event register (CardBus offset 00h, see Section 6.1): bits 3–0
CardBus socket mask register (CardBus offset 04h, see Section 6.2): bits 3–0
CardBus socket present state register (CardBus offset 08h, see Section 6.3): bits 13–10, 7, 5–0
CardBus socket control register (CardBus offset 10h, see Section 6.5): bits 6–4, 2–0
Global reset places all registers in their default state, regardless of the state of the PME enable bit. The GRST signal
is gated only by the SUSPEND signal. This means that assertion of SUSPEND blocks the GRST signal internally,
thus preserving all register contents. The registers cleared by GRST are:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Subsystem vendor ID (PCI offset 40h, see Section 4.26): bits 15–0
Subsystem ID (PCI offset 42h, see Section 4.27): bits 15–0
PC Card 16-bit legacy-mode base address register (PCI offset 44h, see Section 4.28): bits 31–1
System control register (PCI offset 80h, see Section 4.29): bits 31, 30, 27, 26, 24–14, 7–0
Multifunction routing register (PCI offset 8Ch, see Section 4.30): bits 27–0
Retry status register (PCI offset 90h, see Section 4.31): bits 7, 6, 3, 1
Card control register (PCI offset 91h, see Section 4.32): bits 7–5, 2–0
Device control register (PCI offset 92h, see Section 4.33): bits 7–5, 3–0
Diagnostic register (PCI offset 93h, see Section 4.34): bits 7–0
Socket DMA register 0 (PCI offset 94h, see Section 4.35): bits 1–0
Socket DMA register 1 (PCI offset 98h, see Section 4.36): bits 15–4, 2–0
General-purpose event enable register (PCI offset AAh, see Section 4.44): bits 15, 11, 8, 4–0
General-purpose output (PCI offset AEh, see Section 4.46): bits 4–0
Serial bus data (PCI offset B0h, see Section 4.47): bits 7–0
Serial bus index (PCI offset B1h, see Section 4.48): bits 7–0
Serial bus slave address register (PCI offset B2h, see Section 4.49): bits 7–0
Serial bus control and status register (PCI offset B3h, see Section 4.50): bits 7, 2
ExCA identification and revision register (ExCA offset 00h, see Section 5.1): bits 7–0
ExCA card status change register (ExCA offset 804h, see Section 5.5): bits 3–0
ExCA global control register (ExCA offset 1Eh, see Section 5.20): bits 3–0
3–24
4 PC Card Controller Programming Model
This section describes the PCI1410A PCI configuration registers that make up the 256-byte PCI configuration header
for each PCI1410A function. As noted, some bits are global in nature and are accessed only through function 0.
4.1 PCI Configuration Registers
The configuration header is compliant with the PCI Local Bus Specification as a CardBus bridge header and is PC 99
compliant as well. Table 4–1 shows the PCI configuration header, which includes both the predefined portion of the
configuration space and the user-definable registers.
Table 4–1. PCI Configuration Registers
REGISTER NAME
OFFSET
00h
Device ID
Status
Vendor ID
Command
04h
PCI class code
Header type
Revision ID
08h
BIST
Latency timer
Cache line size
0Ch
10h
CardBus socket/ExCA base-address
Reserved
Secondary status
Capability pointer
PCI bus number
14h
CardBus latency timer
Subordinate bus number
CardBus bus number
18h
Memory base register 0
Memory limit register 0
Memory base register 1
Memory limit register 1
I/O base register 0
1Ch
20h
24h
28h
2Ch
30h
I/O limit register 0
I/O base register 1
34h
I/O limit register 1
38h
Bridge control
Subsystem ID
Interrupt pin
Interrupt line
3Ch
40h
Subsystem vendor ID
PC Card 16-bit I/F legacy-mode base address
44h
Reserved
System control
Reserved
48h–7Ch
80h
84h–88h
8Ch
90h
Multifunction routing
Diagnostic
Device control
Card control
Retry status
Capability ID
Socket DMA register 0
94h
Socket DMA register 1
Reserved
98h
9Ch
A0h
Power management capabilities
Power management
Next-item pointer
Power management data
control/status bridge
support extensions
Power management control/status
A4h
General-purpose event enable
General-purpose output
Serial bus control and
status
General-purpose event status
General-purpose input
A8h
ACh
Serial bus slave address
Serial bus index
Serial bus data
B0h
Reserved
B4h–FCh
4–1
A bit description table, typically included when a register contains bits of more than one type or purpose, indicates
bit field names, a detailed field description, and field access tags, which appear in the type column of the
bit-description table. Table 4–2 describes the field access tags.
Table 4–2. Bit-Field Access Tag Descriptions
ACCESS TAG
NAME
Read
Write
Set
MEANING
†
Field can be read by software.
R
W
S
Field can be written by software to any value.
Field can be set by a write of 1. Writes of 0 have no effect.
Field can be cleared by a write of 1. Writes of 0 have no effect.
Field can be autonomously updated by the PCI1410A device.
C
U
Clear
Update
†
A bit can display either of two types of behavior when read. After having been read, it can maintain the value it had previously, or the read
process can cause it to be reset to 0.
4.2 Vendor ID Register
The vendor ID register contains a value allocated by the PCI Special Interest Group (SIG) and identifies the
manufacturer of the PCI device. The vendor ID assigned to TI is 104Ch.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Vendor ID
R
0
R
0
R
0
R
1
R
0
R
0
R
0
R
0
R
0
R
1
R
0
R
0
R
1
R
1
R
0
R
0
Register:
Offset:
Type:
Vendor ID
00h
Read-only
104Ch
Default:
4.3 Device ID Register
The device ID register contains a value assigned to the PCI1410A device by TI. The device identification for the
PCI1410A device is AC50h.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Device ID
R
1
R
0
R
1
R
0
R
1
R
1
R
0
R
0
R
0
R
1
R
0
R
1
R
0
R
0
R
0
R
0
Register:
Offset:
Type:
Device ID
02h
Read-only
AC50h
Default:
4–2
4.4 Command Register
The command register provides control over the PCI1410A interface to the PCI bus. All bit functions adhere to the
definitions in PCI Local Bus Specification. See Table 4–3 for the complete description of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Command
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R
0
R/W
0
R/W
0
R
0
R
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
Type:
Command
04h
Read-only, Read/Write
0000h
Default:
Table 4–3. Command Register Description
FUNCTION
BIT
SIGNAL
TYPE
15–10
RSVD
R
Reserved. Bits 15–10 return 0s when read.
Fast back-to-back enable. The PCI1410A device does not generate fast back-to-back transactions;
therefore, bit 9 returns 0 when read.
9
8
FBB_EN
R
System error (SERR) enable. Bit 8 controls the enable for the SERR driver on the PCI interface. SERR can
be asserted after detecting an address parity error on the PCI bus. Both bits 8 and 6 must be set for the
PCI1410A device to report address parity errors.
SERR_EN
R/W
0 = Disables the SERR output driver (default).
1 = Enables the SERR output driver.
Address/data stepping control. The PCI1410A device does not support address/data stepping; therefore,
bit 7 is hardwired to 0.
7
6
STEP_EN
PERR_EN
R
Parity-error response enable. Bit 6 controls the PCI1410A device response to parity errors through PERR.
Data parity errors are indicated by asserting PERR; address parity errors are indicated by asserting SERR.
0 = PCI1410A device ignores detected parity error (default).
R/W
1 = PCI1410A device responds to detected parity errors.
VGA palette snoop. When bit 5 is set to 1, palette snooping is enabled (that is, the PCI1410A device does
not respond to palette register writes and snoops the data). When bit 5 is 0, the PCI1410A device treats all
palette accesses like all other accesses.
5
VGA_EN
R/W
Memory write and invalidate enable. Bit 4 controls whether a PCI initiator device can generate memory write
and invalidate commands. The PCI1410A controller does not support memory write and invalidate
commands. It uses memory write commands instead; therefore, this bit is hardwired to 0.
4
3
MWI_EN
SPECIAL
R
R
Special cycles. Bit 3 controls whether or not a PCI device ignores PCI special cycles. The PCI1410A device
does not respond to special cycle operations; therefore, this bit is hardwired to 0.
Bus-master control. Bit 2 controls whether or not the PCI1410A device can act as a PCI bus initiator
(master). The PCI1410A device can take control of the PCI bus only when this bit is set.
0 = Disables the PCI1410A device’s ability to generate PCI bus accesses (default).
1 = Enables the PCI1410A device’s ability to generate PCI bus accesses.
2
MAST_EN
R/W
Memory space enable. Bit 1 controls whether or not the PCI1410A device can claim cycles in PCI memory
space.
1
0
MEM_EN
IO_EN
R/W
R/W
0 = Disables the PCI1410A device response to memory space accesses (default).
1 = Enables the PCI1410A device response to memory space accesses.
I/O space control. Bit 0 controls whether or not the PCI1410A device can claim cycles in PCI I/O space.
0 = Disables the PCI1410A device response to I/O space accesses (default).
1 = Enables the PCI1410A device response to I/O space accesses.
4–3
4.5 Status Register
The status register provides device information to the host system. Bits in this register can be read normally. A bit
in the status register is reset when a 1 is written to that bit location; a 0 written to a bit location has no effect. All bit
functions adhere to the definitions in the PCI Local Bus Specification. PCI bus status is shown through each function.
See Table 4–4 for a complete description of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Status
R/C
0
R/C
0
R/C
0
R/C
0
R/C
0
R
0
R
1
R/C
0
R
0
R
0
R
0
R
1
R
0
R
0
R
0
R
0
Register:
Offset:
Type:
Status
06h
Read-only, Read/Clear
0210h
Default:
Table 4–4. Status Register Description
BIT
SIGNAL
TYPE
FUNCTION
Detected parity error. Bit 15 is set when a parity error is detected (either address or data). Write a 1 to clear
this bit.
15
PAR_ERR
R/C
Signaled system error. Bit 14 is set when SERR is enabled and the PCI1410A device signals a system error
to the host. Write a 1 to clear this bit.
14
13
SYS_ERR
MABORT
R/C
R/C
R/C
R/C
R
Received master abort. Bit 13 is set when a cycle initiated by the PCI1410A device on the PCI bus is
terminated by a master abort. Write a 1 to clear this bit.
Received target abort. Bit 12 is set when a cycle initiated by the PCI1410A device on the PCI bus is
terminated by a target abort. Write a 1 to clear this bit.
12
TABT_REC
TABT_SIG
PCI_SPEED
Signaled target abort. Bit 11 is set by the PCI1410A device when it terminates a transaction on the PCI bus
with a target abort. Write a 1 to clear this bit.
11
DEVSEL timing. These bits encode the timing of DEVSEL and are hardwired 01b, indicating that the
PCI1410A device asserts PCI_SPEED at a medium speed on nonconfiguration cycle accesses.
10–9
Data parity error detected. Write a 1 to clear this bit.
0 = The conditions for setting bit 8 have not been met.
1 = A data parity error occurred, and the following conditions were met:
a. PERR was asserted by any PCI device, including the PCI1410A device.
b. The PCI1410A device was the bus master during the data parity error.
c. Bit 6 (PERR_EN) in the command register (PCI offset 04h, see Section 4.4) is set.
8
DATAPAR
R/C
Fast back-to-back capable. The PCI1410A device cannot accept fast back-to-back transactions; therefore,
bit 7 is hardwired to 0.
7
6
5
FBB_CAP
UDF
R
R
R
User-definable feature support. The PCI1410A device does not support the user-definable features;
therefore, bit 6 is hardwired to 0.
66-MHz capable. The PCI1410A device operates at a maximum PCLK frequency of 33 MHz; therefore, bit 5
is hardwired to 0.
66MHZ
Capabilities list. Bit 4 returns 1 when read. This bit indicates that capabilities, in addition to standard PCI
capabilities, are implemented. The linked list of PCI power management capabilities is implemented in this
function.
4
CAPLIST
RSVD
R
R
3–0
Reserved. Bits 3–0 return 0s when read.
4–4
4.6 Revision ID Register
The revision ID register indicates the silicon revision of the PCI1410A device.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Revision ID
R
0
R
0
R
0
R
0
R
0
R
0
R
1
R
0
Register:
Offset:
Type:
Revision ID
08h
Read-only
02h
Default:
4.7 PCI Class Code Register
The class code register recognizes the PCI1410A device as a bridge device (06h) and CardBus bridge device (07h)
with a 00h programming interface.
Bit
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Name
PCI class code
Base class
Subclass
Programming interface
Type
R
0
R
0
R
0
R
0
R
0
R
1
R
1
R
0
R
0
R
0
R
0
R
0
R
0
R
1
R
1
R
1
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Default
Register:
Offset:
Type:
PCI class code
09h
Read-only
06 0700h
Default:
4.8 Cache Line Size Register
The cache line size register is programmed by host software to indicate the system cache line size.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Cache line size
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
Type:
Cache line size
0Ch
Read/Write
00h
Default:
4–5
4.9 Latency Timer Register
The latency timer register specifies the latency timer for the PCI1410A device in units of PCI clock cycles. When the
PCI1410A device is a PCI bus initiator and asserts FRAME, the latency timer begins counting from zero. If the latency
timer expires before the PCI1410A transaction has terminated, the PCI1410A device terminates the transaction when
its GNT is deasserted.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Latency timer
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
Type:
Latency timer
0Dh
Read/Write
00h
Default:
4.10 Header Type Register
This register returns 02h when read, indicating that the PCI1410A configuration spaces adhere to the CardBus bridge
PCI header. The CardBus bridge PCI header ranges from PCI register 0 to 7Fh, and 80h–FFh are user-definable
extension registers.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Header type
R
0
R
0
R
0
R
0
R
0
R
0
R
1
R
0
Register:
Offset:
Type:
Header type
0Eh
Read-only
02h
Default:
4.11 BIST Register
Because the PCI1410A device does not support a built-in self-test (BIST), this register returns the value of 00h when
read.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
BIST
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Offset:
Type:
BIST
0Fh
Read-only
00h
Default:
4–6
4.12 CardBus Socket/ExCA Base-Address Register
The CardBus socket/ExCA base-address register is programmed with a base address referencing the CardBus
socket registers and the memory-mapped ExCA register set. Bits 31–12 are read/write and allow the base address
to be located anywhere in the 32-bit PCI memory address space on a 4-Kbyte boundary. Bits 11–0 are read-only,
returning 0s when read. When software writes all 1s to this register, the value read back is FFFF F000h, indicating
that at least 4 Kbytes of memory address space are required. The CardBus registers start at offset 000h, and the
memory-mapped ExCA registers begin at offset 800h.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
CardBus socket/ExCA base-address
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
CardBus socket/ExCA base-address
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Offset:
Type:
CardBus socket/ExCA base-address
10h
Read-only, Read/Write
0000 0000h
Default:
4.13 Capability Pointer Register
The capability pointer register provides a pointer into the PCI configuration header where the PCI
power-management register block resides. PCI header doublewords at A0h and A4h provide the power-management
(PM) registers. The socket has its own capability pointer register. This register returns A0h when read.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Capability pointer
R
1
R
0
R
1
R
0
R
0
R
0
R
0
R
0
Register:
Offset:
Type:
Capability pointer
14h
Read-only
A0h
Default:
4–7
4.14 Secondary Status Register
The secondary status register is compatible with the PCI-to-PCI bridge secondary status register and indicates
CardBus-related device information to the host system. This register is very similar to the status register (PCI offset
06h); status bits are cleared by writing a 1. See Table 4–5 for a complete description of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Secondary status
R/C
0
R/C
0
R/C
0
R/C
0
R/C
0
R
0
R
1
R/C
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Offset:
Type:
Secondary status
16h
Read-only, Read/Clear
0200h
Default:
Table 4–5. Secondary Status Register Description
BIT
SIGNAL
TYPE
FUNCTION
Detected parity error. Bit 15 is set when a CardBus parity error is detected (either address or data). Write
a 1 to clear this bit.
15
CBPARITY
R/C
Signaled system error. Bit 14 is set when CSERR is signaled by a CardBus card. The PCI1410A device
does not assert CSERR. Write a 1 to clear this bit.
14
13
CBSERR
CBMABORT
REC_CBTA
SIG_CBTA
CB_SPEED
R/C
R/C
R/C
R/C
R
Received master abort. Bit 13 is set when a cycle initiated by the PCI1410A device on the CardBus bus
is terminated by a master abort. Write a 1 to clear this bit.
Received target abort. Bit 12 is set when a cycle initiated by the PCI1410A device on the CardBus bus
is terminated by a target abort. Write a 1 to clear this bit.
12
Signaled target abort. Bit 11 is set by the PCI1410A device when it terminates a transaction on the CardBus
bus with a target abort. Write a 1 to clear this bit.
11
CDEVSEL timing. These bits encode the timing of CDEVSEL and are hardwired 01b, indicating that the
PCI1410A device asserts CB_SPEED at a medium speed.
10–9
CardBus data parity error detected. Write a 1 to clear this bit.
0 = The conditions for setting bit 8 have not been met.
1 = A data parity error occurred and the following conditions were met:
a. CPERR was asserted on the CardBus interface.
8
CB_DPAR
R/C
b. The PCI1410A device was the bus master during the data parity error.
c. Bit 0 (CPERREN) in the bridge control register (PCI offset 3Eh, see Section 4.25) is set.
Fast back-to-back capable. The PCI1410A device cannot accept fast back-to-back transactions;
therefore, bit 7 is hardwired to 0.
7
6
CBFBB_CAP
CB_UDF
R
R
User-definable feature support. The PCI1410A device does not support the user-definable features;
therefore, bit 6 is hardwired to 0.
66-MHz capable. The PCI1410A CardBus interface operates at a maximum CCLK frequency of 33 MHz;
therefore, bit 5 is hardwired to 0.
5
CB66MHZ
RSVD
R
R
4–0
Reserved. Bits 4–0 return 0s when read.
4–8
4.15 PCI Bus Number Register
The PCI bus number register is programmed by the host system to indicate the bus number of the PCI bus to which
the PCI1410A device is connected. The PCI1410A device uses this register in conjunction with the CardBus bus
number (PCI offset 19h, see Section 4.16) and subordinate bus number (PCI offset 1Ah, see Section 4.17) registers
to determine when to forward PCI configuration cycles to its secondary buses.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
PCI bus number
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
Type:
PCI bus number
18h
Read/Write
00h
Default:
4.16 CardBus Bus Number Register
The CardBus bus number register is programmed by the host system to indicate the bus number of the CardBus bus
to which the PCI1410A device is connected. The PCI1410A device uses this register in conjunction with the PCI bus
number (PCI offset 18h, see Section 4.15) and subordinate bus number (PCI offset 1Ah, see Section 4.17) registers
to determine when to forward PCI configuration cycles to its secondary buses.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
CardBus bus number
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
Type:
CardBus bus number
19h
Read/Write
00h
Default:
4.17 Subordinate Bus Number Register
The subordinate bus number register is programmed by the host system to indicate the highest-numbered bus below
the CardBus bus. The PCI1410A device uses this register in conjunction with the PCI bus number (PCI offset 18h,
see Section 4.15) and CardBus bus number (PCI offset 19h, see Section 4.16) registers to determine when to forward
PCI configuration cycles to its secondary buses.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Subordinate bus number
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
Type:
Subordinate bus number
1Ah
Read/Write
00h
Default:
4–9
4.18 CardBus Latency Timer Register
This register is programmed by the host system to specify the latency timer for the PCI1410A CardBus interface in
units of CCLK cycles. When the PCI1410A device is a CardBus initiator and asserts CFRAME, the CardBus latency
timer begins counting. If the latency timer expires before the PCI1410A transaction has terminated, the PCI1410A
device terminates the transaction at the end of the next data phase. A recommended minimum value for this register
is 20h, which allows most transactions to be completed.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
CardBus latency timer
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
Type:
CardBus latency timer
1Bh
Read/Write
00h
Default:
4.19 Memory Base Registers 0, 1
The memory base registers indicate the lower address of a PCI memory address range. These registers are used
by the PCI1410A device to determine when to forward a memory transaction to the CardBus bus and when to forward
a CardBus cycle to the PCI bus. Bits 31–12 of these registers are read/write and allow the memory base to be located
anywhere in the 32-bit PCI memory space on 4-Kbyte boundaries. Bits 11–0 are read-only and always return 0s. Write
transactions to these bits have no effect. Bits 8 (PREFETCH0) and 9 (PREFETCH1) of the bridge control register
(PCI offset 3Eh, see Section 4.25) specify whether memory windows 0 and 1 are prefetchable or nonprefetchable.
The memory base register or the memory limit register must be nonzero for the PCI1410A device to claim any memory
transactions through the CardBus memory windows (that is, these windows are not enabled by default to pass the
first 4 Kbytes of memory to CardBus).
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Memory base registers 0, 1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Memory base registers 0, 1
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Offset:
Memory base register 0
1Ch
Register:
Offset:
Memory base register 1
24h
Type:
Default:
Read-only, Read/Write
0000 0000h
4–10
4.20 Memory Limit Registers 0, 1
The memory limit registers indicate the upper address of a PCI memory address range. These registers are used
by the PCI1410A device to determine when to forward a memory transaction to the CardBus bus and when to forward
a CardBus cycle to the PCI bus. Bits 31–12 of these registers are read/write and allow the memory base to be located
anywhere in the 32-bit PCI memory space on 4-Kbyte boundaries. Bits 11–0 are read-only and always return 0s. Write
transactions to these bits have no effect. Bits 8 (PREFETCH0) and 9 (PREFETCH1) of the bridge control register
(PCI offset 3Eh, see Section 4.25) specify whether memory windows 0 and 1 are prefetchable or nonprefetchable.
The memory base register or the memory limit register must be nonzero for the PCI1410A device to claim any memory
transactions through the CardBus memory windows (that is, these windows are not enabled by default to pass the
first 4 Kbytes of memory to CardBus).
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Memory limit registers 0, 1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Memory limit registers 0, 1
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Offset:
Type:
Memory limit registers 0, 1
20h, 28h
Read-only, Read/Write
0000 0000h
Default:
4.21 I/O Base Registers 0, 1
The I/O base registers indicate the lower address of a PCI I/O address range. These registers are used by the
PCI1410A device to determine when to forward an I/O transaction to the CardBus bus and when to forward a CardBus
cycle to the PCI bus. The lower 16 bits of these registers locate the bottom of the I/O window within a 64-Kbyte page,
and the upper 16 bits (31–16) are a page register that locates this 64-Kbyte page in 32-bit PCI I/O address space.
Bits 31–2 are read/write. Bits 1 and 0 are read-only and always return 0s, forcing the I/O window to be aligned on
a natural doubleword boundary.
NOTE: Either the I/O base or the I/O limit register must be nonzero to enable any I/O
transactions.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
I/O base registers 0, 1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
I/O base registers 0, 1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
Register:
Offset:
Type:
I/O base registers 0, 1
2Ch, 34h
Read-only, Read/Write
0000 0000h
Default:
4–11
4.22 I/O Limit Registers 0, 1
The I/O limit registers indicate the upper address of a PCI I/O address range. These registers are used by the
PCI1410A device to determine when to forward an I/O transaction to the CardBus bus and when to forward a CardBus
cycle to the PCI bus. The lower 16 bits of these registers locate the top of the I/O window within a 64-Kbyte page,
and the upper 16 bits are a page register that locates this 64-Kbyte page in 32-bit PCI I/O address space. Bits 15–2
are read/write and allow the I/O limit address to be located anywhere in the 64-Kbyte page (indicated by bits 31–16
of the appropriate I/O base register) on doubleword boundaries.
Bits 31–16 are read-only and always return 0s when read. The page is set in the I/O base register. Bits 1 and 0 are
read-only and always return 0s, forcing I/O windows to be aligned on a natural doubleword boundary. Write
transactions to read-only bits have no effect. The PCI1410A device assumes that the lower 2 bits of the limit address
are 1s.
NOTE: The I/O base or the I/O limit register must be nonzero to enable an I/O transaction.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
I/O limit registers 0, 1
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
I/O limit registers 0, 1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
Register:
Offset:
Type:
I/O limit registers 0, 1
30h, 38h
Read-only, Read/Write
0000 0000h
Default:
4.23 Interrupt Line Register
The interrupt line register communicates interrupt line routing information.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Interrupt line
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Register:
Offset:
Type:
Interrupt line
3Ch
Read/Write
FFh
Default:
4–12
4.24 Interrupt Pin Register
The value read from the interrupt pin register is function dependent and depends on the interrupt signaling mode,
selected through bits 2–1 (INTMODE field) of the device control register (PCI offset 92h, see Section 4.33). The
PCI1410A device defaults to serialized PCI and ISA interrupt mode.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Interrupt pin
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
1
Register:
Offset:
Type:
Interrupt pin
3Dh
Read-only
01h
Default:
4–13
4.25 Bridge Control Register
The bridge control register provides control over various PCI1410A bridging functions. See Table 4–6 for a complete
description of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Bridge control
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
1
R/W
1
R/W
0
R/W
1
R/W
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
Type:
Bridge control
3Eh
Read-only, Read/Write
0340h
Default:
Table 4–6. Bridge Control Register Description
FUNCTION
BIT
SIGNAL
TYPE
15–11
RSVD
R
Reserved. Bits 15–11 return 0s when read.
Write posting enable. Enables write posting to and from the CardBus sockets. Write posting enables
posting of write data on burst cycles. Operating with write posting disabled inhibits performance on burst
cycles. Note that burst write data can be posted, but various write transactions cannot.
10
9
POSTEN
R/W
R/W
Memory window 1 type. Bit 9 specifies whether or not memory window 1 is prefetchable. This bit is socket
dependent. Bit 9 is encoded as:
PREFETCH1
0 = Memory window 1 is nonprefetchable.
1 = Memory window 1 is prefetchable (default).
Memory window 0 type. Bit 8 specifies whether or not memory window 0 is prefetchable. This bit is
encoded as:
8
7
6
5
PREFETCH0
INTR
R/W
R/W
R/W
R/W
0 = Memory window 0 is nonprefetchable.
1 = Memory window 0 is prefetchable (default).
PCI interrupt – IREQ routing enable. Bit 7 selects whether PC Card functional interrupts are routed to PCI
interrupts or to the IRQ specified in the ExCA registers.
0 = Functional interrupts are routed to PCI interrupts (default).
1 = Functional interrupts are routed by ExCAs.
CardBus reset. When bit 6 is set, CRST is asserted on the CardBus interface. CRST also can be asserted
by passing a PRST assertion to CardBus.
CRST
0 = CRST is deasserted.
1 = CRST is asserted (default).
Master abort mode. Bit 5 controls how the PCI1410A device responds to a master abort when the
PCI1410A device is an initiator on the CardBus interface.
MABTMODE
0 = Master aborts are not reported (default).
1 = Signal target abort on PCI and SERR (if enabled)
4
3
RSVD
R
Reserved. Bit 4 returns 0 when read.
VGA enable. Bit 3 affects how the PCI1410A device responds to VGA addresses. When this bit is set,
accesses to VGA addresses are forwarded.
VGAEN
R/W
ISA mode enable. Bit 2 affects how the PCI1410A device passes I/O cycles within the 64-Kbyte ISA range.
This bit is not common between sockets. When this bit is set, the PCI1410A device does not forward the
last 768 bytes of each 1K I/O range to CardBus.
2
1
ISAEN
R/W
R/W
CSERR enable. Bit 1 controls the response of the PCI1410A device to CSERR signals on the CardBus
bus. This bit is common between the two sockets.
CSERREN
0 = CSERR is not forwarded to PCI SERR.
1 = CSERR is forwarded to PCI SERR.
CardBus parity error response enable. Bit 0 controls the response of the PCI1410A device to CardBus
parity errors. This bit is common between the two sockets.
0 = CardBus parity errors are ignored.
0
CPERREN
R/W
1 = CardBus parity errors are reported using CPERR.
4–14
4.26 Subsystem Vendor ID Register
The subsystem vendor ID register is used for system and option-card identification purposes and may be required
for certain operating systems. This register is read-only or read/write, depending on the setting of bit 5 (SUBSYSRW)
in the system control register (PCI offset 80h, see Section 4.29).
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Subsystem vendor ID
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Offset:
Type:
Subsystem vendor ID
40h
Read-only (Read/Write if enabled by SUBSYSRW)
0000h
Default:
4.27 Subsystem ID Register
The subsystem ID register is used for system and option-card identification purposes and may be required for certain
operating systems. This register is read-only or read/write, depending on the setting of bit 5 (SUBSYSRW) in the
system control register (PCI offset 80h, see Section 4.29).
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Subsystem ID
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Offset:
Type:
Subsystem ID
42h
Read-only (Read/Write if enabled by SUBSYSRW)
0000h
Default:
4.28 PC Card 16-Bit I/F Legacy-Mode Base-Address Register
The PCI1410A device supports the index/data scheme of accessing the ExCA registers, which is mapped by this
register. An address written to this register is the address for the index register and the address + 1 is the data address.
Using this access method, applications requiring index/data ExCA access can be supported. The base address can
be mapped anywhere in 32-bit I/O space on a word boundary; hence, bit 0 is read-only, returning 1 when read. See
Section 5, ExCA Compatibility Registers, for register offsets.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
PC Card 16-bit I/F legacy-mode base address
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
PC Card 16-bit I/F legacy-mode base address
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
1
Register:
Offset:
Type:
PC Card 16-bit I/F legacy-mode base address
44h
Read-only, Read/Write
0000 0001h
Default:
4–15
4.29 System Control Register
System-level initializations are performed through programming this doubleword register. See Table 4–7 for a
complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
System control
R/W
0
R/W
0
R
0
R
0
R/W
0
R/W
0
R/C
0
R/W
0
R
0
7
R/W
1
R/W
0
R/W
0
R/W
0
R/W
1
R/W
0
R/W
0
15
14
13
12
11
10
9
8
6
5
4
3
2
1
0
Name
Type
Default
System control
R/W
1
R/W
0
R
0
R
1
R
0
R
0
R
0
R
0
R/W
0
R/W
1
R/W
1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
System control
Read-only, Read/Write, Read/Clear
Offset:
Default:
80h
0044 9060h
4–16
Table 4–7. System Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
Serialized PCI interrupt routing step. Bits 31 and 30 configure the serialized PCI interrupt stream
signaling and accomplish an even distribution of interrupts signaled on the four PCI interrupt slots.
Bits 31 and 30 are encoded as follows:
31–30
SER_STEP
R/W
00 = INTA signaled in INTA IRQSER slots
01 = INTA signaled in INTB IRQSER slots
10 = INTA signaled in INTC IRQSER slots
11 = INTA signaled in INTD IRQSER slots
29–28
RSVD
OSEN
R
Reserved. Bits 29 and 28 return 0s when read.
Internal oscillator enable.
27
R/W
0 = Internal oscillator is disabled (default).
1 = Internal oscillator is enabled.
SMI interrupt routing. Bit 26 selects whether IRQ2 or CSC is signaled when a write occurs to power
a PC Card socket.
26
25
SMIROUTE
SMISTATUS
R/W
R/C
0 = PC Card power change interrupts are routed to IRQ2 (default).
1 = A CSC interrupt is generated on PC Card power changes.
SMI interrupt status. This bit is set when bit 24 (SMIENB) is set and a write occurs to set the socket
power. Writing a 1 to bit 25 clears the status.
0 = SMI interrupt is signaled (default).
1 = SMI interrupt is not signaled.
SMI interrupt mode enable. When bit 24 is set and a write to the socket power control occurs, the SMI
interrupt signaling is enabled and generates an interrupt. This bit is shared and defaults to 0 (disabled).
24
23
SMIENB
RSVD
R/W
R
Reserved. Bit 23 returns 0 when read.
CardBus reserved-terminals signaling. When a CardBus card is inserted and bit 22 is set, the RSVD
CardBus terminals are driven low. When this bit is 0, these signals are placed in a high-impedance
state.
22
21
20
CBRSVD
VCCPROT
REDUCEZV
R/W
R/W
R/W
0 = Place CardBus RSVD in a high-impedance state
1 = Drive Cardbus RSVD low (default)
V
protection enable.
CC
0 = V
protection is enabled for 16-bit cards (default).
protection is disabled for 16-bit cards.
CC
CC
1 = V
Reduced zoomed-video enable. When this bit is enabled, pins ADDR25–ADDR22 of the card interface
for PC Card-16 cards are placed in the high-impedance state. This bit should not be set for normal ZV
operation. This bit is encoded as:
0 = Reduced ZV is disabled (default).
1 = Reduced ZV is enabled.
PC/PCI DMA card enable. When bit 19 is set, the PCI1410A device allows 16-bit PC Cards to request
PC/PCI DMA using the DREQ signaling. DREQ is selected through the socket DMA register (PCI offset
94h, see Section 4.35).
19
CDREQEN
R/W
0 = Ignore DREQ signaling from PC Cards (default)
1 = Signal DMA request on DREQ
PC/PCI DMA channel assignment. Bits 18–16 are encoded as:
0–3 = 8-bit DMA channels
18–16
15
CDMACHAN
MRBURSTDN
MRBURSTUP
R/W
R/W
R/W
4 = Not used (default)
5–7 = 16-bit DMA channels
Memory-read burst-enable downstream. When bit 15 is set, memory-read transactions are allowed to
burst downstream.
0 = Downstream memory-read burst is disabled.
1 = Downstream memory-read burst is enabled (default).
Memory-read burst-enable upstream. When bit 14 is set, the PCI1410A device allows memory-read
transactions to burst upstream.
14
0 = Upstream memory-read burst is disabled (default).
1 = Upstream memory-read burst is enabled.
4–17
Table 4–7. System Control Register Description (Continued)
BIT
13
SIGNAL
SOCACTIVE
RSVD
TYPE
FUNCTION
Socket activity status. When set, bit 13 indicates access has been performed to or from a PC card and
is cleared upon read of this status bit.
0 = No socket activity (default)
1 = Socket activity
R
R
12
Reserved. Bit 12 returns 1 when read.
Power stream in progress status bit. When set, bit 11 indicates that a power stream to the power switch
is in progress and a powering change has been requested. This bit is cleared when the power stream
is complete.
11
PWRSTREAM
R
0 = Power stream is complete and delay has expired.
1 = Power stream is in progress.
Power-up delay in progress status. When set, bit 9 indicates that a power-up stream has been sent to
the power switch and proper power may not yet be stable. This bit is cleared when the power-up delay
has expired.
10
9
DELAYUP
R
R
Power-down delay in progress status. When set, bit 10 indicates that a power-down stream has been
sent to the power switch and proper power may not yet be stable. This bit is cleared when the
power-down delay has expired.
DELAYDOWN
Interrogation in progress. When set, bit 8 indicates an interrogation is in progress and clears when
interrogation completes. This bit is socket dependent.
0 = Interrogation is not in progress (default).
8
INTERROGATE
R
1 = Interrogation is in progress.
Auto power-switch enable.
0 = Bit 5 (AUTOPWRSWEN) in ExCA power control register (ExCA offset 02h, see Section 5.3)
is disabled (default).
7
6
AUTOPWRSWEN
PWRSAVINGS
R/W
R/W
1 = Bit 5 (AUTOPWRSWEN) in ExCA power control register (ExCA offset 02h, see Section 5.3)
is enabled.
Power savings mode enable. When this bit is set, if a CB card is inserted, idle, and without a CB clock,
the applicable CB state machine is not clocked.
Subsystem ID (PCI offset 42h, see Section 4.27), subsystem vendor ID (PCI offset 40h, see
Section 4.26), ExCA identification and revision (ExCA offset 00h, see Section 5.1) registers read/write
enable.
5
SUBSYSRW
R/W
0 = Subsystem ID, subsystem vendor ID, ExCA identification and revision registers are read/write.
1 = Subsystem ID, subsystem vendor ID, ExCA identification and revision registers are read-only
(default).
CardBus data parity SERR signaling enable.
4
3
CB_DPAR
CDMA_EN
R/W
R/W
0 = CardBus data parity is not signaled on PCI SERR.
1 = CardBus data parity is signaled on PCI SERR.
PC/PCI DMA enable. Bit 3 enables PC/PCI DMA when set if MFUNC0–MFUNC6 are configured for
centralized DMA.
0 = Centralized DMA is disabled (default).
1 = Centralized DMA is enabled.
ExCA power control bit. Enabled by selecting the 82365SL mode.
2
1
ExCAPower
KEEPCLK
R/W
R/W
0 = Enables 3.3 V.
1 = Enables 5 V.
Keep clock. This bit works with PCI and CB CLKRUN protocols.
0 = Allows normal functioning of both CLKRUN protocols (default).
1 = Does not allow CB clock or PCI clock to be stopped using the CLKRUN protocols.
RI_OUT/PME multiplex enable.
0 = RI_OUT and PME are both routed to the RI_OUT/PME terminal. If both are enabled at the
same time, RI_OUT has precedence over PME.
0
RIMUX
R/W
1 = Only PME is routed to the RI_OUT/PME terminal.
4–18
4.30 Multifunction Routing Register
The multifunction routing register is used to configure the MFUNC0–MFUNC6 terminals. These terminals can be
configured for various functions. All multifunction terminals default to the general-purpose input configuration. This
register is intended to be programmed once at power-on initialization. The default value for this register also can be
loaded through a serial bus EEPROM. See Table 4–8 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Multifunction routing
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Multifunction routing
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
Type:
Multifunction routing
8Ch
Read-only, Read/Write
0000 0000h
Default:
Table 4–8. Multifunction Routing Register Description
BIT
SIGNAL
TYPE
FUNCTION
31–28
RSVD
R
Bits 31–28 return 0s when read.
Multifunction terminal 6 configuration. These bits control the internal signal mapped to the MFUNC6 terminal
as follows:
0000 = RSVD
0001 = CLKRUN
0010 = IRQ2
0011 = IRQ3
0100 = IRQ4
0101 = IRQ5
0110 = IRQ6
0111 = IRQ7
1000 = IRQ8
1001 = IRQ9
1010 = IRQ10
1011 = IRQ11
1100 = IRQ12
1101 = IRQ13
1110 = IRQ14
1111 = IRQ15
27–24
23–20
MFUNC6
MFUNC5
R/W
R/W
Multifunction terminal 5 configuration. These bits control the internal signal mapped to the MFUNC5 terminal
as follows:
0000 = GPI4
0001 = GPO4
0010 = PCGNT
0011 = IRQ3
0100 = IRQ4
1000 = CAUDPWM
1001 = IRQ9
1010 = IRQ10
1011 = IRQ11
1100 = LED_SKT
1101 = LED_SKT
1110 = GPE
0101 = RSVD
0110 = ZVSTAT
0111 = ZVSEL0
1111 = IRQ15
Multifunction terminal 4 configuration. These bits control the internal signal mapped to the MFUNC4 terminal
as follows:
NOTE: When the serial bus mode is implemented by pulling up the VCCD0 and VCCD1 terminals, the
MFUNC4 terminal provides the SCL signaling.
19–16
MFUNC4
R/W
0000 = GPI3
0100 = IRQ4
0101 = IRQ5
0110 = ZVSTAT
0111 = ZVSEL0
1000 = CAUDPWM
1001 = IRQ9
1010 = IRQ10
1011 = IRQ11
1100 = RI_OUT
1101 = LED_SKT
1110 = GPE
0001 = GPO3
0010 = LOCK PCI
0011 = IRQ3
1111 = IRQ15
Multifunction terminal 3 configuration. These bits control the internal signal mapped to the MFUNC3 terminal
as follows:
0000 = RSVD
0001 = IRQSER
0010 = IRQ2
0011 = IRQ3
0100 = IRQ4
0101 = IRQ5
0110 = IRQ6
0111 = IRQ7
1000 = IRQ8
1001 = IRQ9
1010 = IRQ10
1011 = IRQ11
1100 = IRQ12
1101 = IRQ13
1110 = IRQ14
1111 = IRQ15
15–12
11–8
MFUNC3
MFUNC2
R/W
R/W
Multifunction terminal 2 configuration. These bits control the internal signal mapped to the MFUNC2 terminal
as follows:
0000 = GPI2
0001 = GPO2
0010 = PCREQ
0011 = IRQ3
0100 = IRQ4
0101 = IRQ5
0110 = ZVSTAT
0111 = ZVSEL0
1000 = CAUDPWM
1001 = IRQ9
1010 = IRQ10
1011 = IRQ11
1100 = RI_OUT
1101 = RSVD
1110 = GPE
1111 = IRQ7
4–19
Table 4–8. Multifunction Routing Register Description (Continued)
BIT
SIGNAL
TYPE
FUNCTION
Multifunction terminal 1 configuration. These bits control the internal signal mapped to the MFUNC1 terminal
as follows:
NOTE: When the serial bus mode is implemented by pulling up the VCCD0 and VCCD1 terminals, the
MFUNC1 terminal provides the SDA signaling.
7–4
MFUNC1
R/W
R/W
0000 = GPI1
0001 = GPO1
0010 = RSVD
0011 = IRQ3
0100 = IRQ4
0101 = IRQ5
0110 = ZVSTAT
0111 = ZVSEL0
1000 = CAUDPWM
1001 = IRQ9
1010 = IRQ10
1011 = IRQ11
1100 = LED_SKT
1101 = IRQ13
1110 = GPE
1111 = IRQ15
Multifunction terminal 0 configuration. These bits control the internal signal mapped to the MFUNC0 terminal
as follows:
0000 = GPI0
0001 = GPO0
0010 = INTA
0011 = IRQ3
0100 = IRQ4
0101 = IRQ5
0110 = ZVSTAT
0111 = ZVSEL0
1000 = CAUDPWM
1001 = IRQ9
1010 = IRQ10
1011 = IRQ11
1100 = LED_SKT
1101 = IRQ13
1110 = GPE
3–0
MFUNC0
1111 = IRQ15
4.31 Retry Status Register
The retry status register enables the retry timeout counters and displays the retry expiration status. The flags are set
15
when the PCI1410A device retries a PCI or CardBus master request and the master does not return within 2 PCI
clock cycles. The flags are cleared by writing a 1 to the bit. These bits are expected to be incorporated into the PCI
command, PCI status, and bridge control registers by the PCI SIG. See Table 4–9 for a complete description of the
register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Retry status
R/W
1
R/W
1
R
0
R
0
R/C
0
R
0
R/C
0
R
0
Register:
Offset:
Type:
Retry status
90h
Read-only, Read/Write, Read/Clear
C0h
Default:
Table 4–9. Retry Status Register Description
BIT
SIGNAL
TYPE
FUNCTION
PCI retry timeout counter enable. Bit 7 is encoded:
0 = PCI retry counter is disabled.
7
PCIRETRY
R/W
1 = PCI retry counter is enabled (default).
CardBus retry timeout counter enable. Bit 6 is encoded:
0 = CardBus retry counter is disabled.
6
5–4
3
CBRETRY
RSVD
R/W
R
1 = CardBus retry counter is enabled (default).
Reserved. Bits 5 and 4 return 0s when read.
CardBus target retry expired. Write a 1 to clear bit 3.
0 = Inactive (default)
TEXP_CB
RSVD
R/C
R
1 = Retry has expired.
2
Reserved. Bit 2 returns 0 when read.
PCI target retry expired. Write a 1 to clear bit 1.
0 = Inactive (default)
1
TEXP_PCI
RSVD
R/C
R
1 = Retry has expired.
0
Reserved. Bit 0 returns 0 when read.
4–20
4.32 Card Control Register
The card control register is provided for PCI1130 compatibility. RI_OUT is enabled through this register. See
Table 4–10 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Card control
R/W
0
R/W
0
R/W
0
R
0
R
0
R/W
0
R/W
0
R/C
0
Register:
Offset:
Type:
Card control
91h
Read-only, Read/Write, Read/Clear
00h
Default:
Table 4–10. Card Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
Ring indicate output enable.
0 = Disables any routing of RI_OUT signal (default).
1 = Enables RI_OUT signal for routing to the RI_OUT/PME terminal, when bit 0 (RIMUX) in the system
control register (PCI offset 80h, see Section 4.29) is set to 0, and for routing to MFUNC2 or
MFUNC4.
7
RIENB
R/W
Compatibility ZV mode enable. When set, the PC Card socket interface ZV terminals enter a
high-impedance state. This bit defaults to 0.
6
ZVENABLE
R/W
5
No function
RSVD
R/W
R
This bit has no assigned function.
4–3
Reserved. Bits 4 and 3 return 0 when read.
CardBus audio-to-IRQMUX. When set, the CAUDIO CardBus signal is routed to the corresponding
multifunction terminal, which may be configured for CAUDPWM.
2
1
AUD2MUX
R/W
Speaker out enable. When bit 1 is set, SPKR on the PC Card is enabled and is routed to SPKROUT. The
SPKROUT terminal drives data only when the socket’s SPKROUTEN bit is set. This bit is encoded as:
0 = SPKR to SPKROUT is not enabled (default).
SPKROUTEN
R/W
1 = SPKR to SPKROUT is enabled.
Interrupt flag. Bit 0 is the interrupt flag for 16-bit I/O PC Cards and for CardBus cards. Bit 0 is set when a
functional interrupt is signaled from a PC Card interface. Write back a 1 to clear this bit.
0 = No PC Card functional interrupt is detected (default).
0
IFG
R/C
1 = PC Card functional interrupt is detected.
4–21
4.33 Device Control Register
The device control register is provided for PCI1130 compatibility. The interrupt mode select and the socket-capable
force bits are programmed through this register. See Table 4–11 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Device control
R/W
0
R/W
1
R/W
1
R
0
R/W
0
R/W
1
R/W
1
R/W
0
Register:
Offset:
Type:
Device control
92h
Read-only, Read/Write
66h
Default:
Table 4–11. Device Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
Socket-power lock bit. When this bit is set to 1, software cannot power down the PC Card socket while
in D3. This may be necessary to support wake-up on LAN or RING if the operating system is
programmed to power down a socket when the CardBus controller is placed in the D3 state.
7
SKTPWR_LOCK
R/W
3-V socket-capable force
0 = Not 3-V capable
6
3VCAPABLE
R/W
1 = 3-V capable (default)
5
4
3
IO16V2
RSVD
TEST
R/W
R
Diagnostic bit. This bit defaults to 1.
Reserved. Bit 4 returns 0 when read.
TI test. Only a 0 should be written to bit 3.
R/W
Interrupt signaling mode. Bits 2 and 1 select the interrupt signaling mode. The interrupt signaling
mode bits are encoded:
00 = Parallel PCI interrupts only
01 = Parallel IRQ and parallel PCI interrupts
10 = IRQ serialized interrupts and parallel PCI interrupt
11 = IRQ and PCI serialized interrupts (default)
2–1
INTMODE
RSVD
R/W
R/W
0
Reserved. Bit 0 is reserved for test purposes. Only 0 should be written to this bit.
4–22
4.34 Diagnostic Register
The diagnostic register is provided for internal TI test purposes. It is a read/write register, but only 0s should be written
to it. See Table 4–12 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Diagnostic
R/W
0
R/W
0
R/W
1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
Register:
Offset:
Type:
Diagnostic
93h
Read/Write
21h
Default:
Table 4–12. Diagnostic Register Description
FUNCTION
BIT
7
SIGNAL
TRUE_VAL
RSVD
TYPE
R/W
This bit defaults to 0. This bit is encoded as:
0 = Reads true values in PCI vendor ID and PCI device ID registers (default).
1 = Reads all 1s in the PCI vendor ID and PCI device ID registers.
6
R/W
Reserved. Bit 6 returns 0 when read.
CSC interrupt routing control
0 = CSC interrupts are routed to PCI if ExCA 803 (see Section 5.4) bit 4 = 1.
1 = CSC interrupts are routed to PCI if ExCA 805 (see Section 5.6) bits 7–4 = 0000b (default).
In this case, the setting of ExCA 803 bit 4 is a don’t care.
5
CSC
R/W
4
3
2
1
DIAG4
DIAG3
DIAG2
DIAG1
R/W
R/W
R/W
R/W
Diagnostic RETRY_DIS. Delayed transaction disable.
Diagnostic RETRY_EXT. Extends the latency from 16 to 64.
10
15
.
Diagnostic DISCARD_TIM_SEL_CB. Set = 2 , reset = 2
10
15
.
Diagnostic DISCARD_TIM_SEL_PCI. Set = 2 , reset = 2
Asynchronous interrupt enable.
0
ASYNCINT
R/W
0 = CSC interrupt is not generated asynchronously.
1 = CSC interrupt is generated asynchronously (default).
4–23
4.35 Socket DMA Register 0
The socket DMA register 0 provides control over the PC Card DMA request (DREQ) signaling. See Table 4–13 for
a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Socket DMA register 0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Socket DMA register 0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
Register:
Offset:
Type:
Socket DMA register 0
94h
Read-only, Read/Write
0000 0000h
Default:
Table 4–13. Socket DMA Register 0 Description
FUNCTION
BIT
SIGNAL
TYPE
31–2
RSVD
R
Reserved. Bits 31–2 return 0s when read.
DMA request (DREQ). Bits 1 and 0 indicate which pin on the 16-bit PC Card interface acts as DREQ during
DMA transfers. This field is encoded as:
00 = Socket not configured for DMA (default).
01 = DREQ uses SPKR.
1–0
DREQPIN
R/W
10 = DREQ uses IOIS16.
11 = DREQ uses INPACK.
4–24
4.36 Socket DMA Register 1
The socket DMA register 1 provides control over the distributed DMA (DDMA) registers and the PCI portion of DMA
transfers. The DMA base address locates the DMA registers in a 16-byte region within the first 64 Kbytes of PCI I/O
address space. See Table 4–14 for a complete description of the register contents.
NOTE: 32-bit transfers are not supported; the maximum transfer possible for 16-bit PC Cards
is 16 bits.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Socket DMA register 1
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Socket DMA register 1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
Type:
Socket DMA register 1
98h
Read-only, Read/Write
0000 0000h
Default:
Table 4–14. Socket DMA Register 1 Description
FUNCTION
BIT
SIGNAL
TYPE
31–16
RSVD
R
Reserved. Bits 31–16 return 0s when read.
DMA base address. Locates the socket’s DMA registers in PCI I/O space. This field represents a 16-bit PCI
I/O address. The upper 16 bits of the address are hardwired to 0, forcing this window to within the lower
64 Kbytes of I/O address space. The lower 4 bits are hardwired to 0 and are included in the address decode.
Thus, the window is aligned to a natural 16-byte boundary.
15–4
DMABASE
EXTMODE
R/W
R
3
Extended addressing. This feature is not supported by the PCI4410 and always returns a 0.
Transfer size. Bits 2 and 1 specify the width of the DMA transfer on the PC Card interface and are
encoded as:
00 = Transfers are 8 bits (default).
01 = Transfers are 16 bits.
10 = Reserved
2–1
XFERSIZE
DDMAEN
R/W
R/W
11 = Reserved
DDMA registers decode enable. Enables the decoding of the distributed DMA registers based on the value
of bits 15–4 (DMABASE field).
0 = Disabled (default)
1 = Enabled
0
4–25
4.37 Capability ID Register
The capability ID register identifies the linked list item as the register for PCI power management. The register returns
01h when read, which is the unique ID assigned by the PCI SIG for the PCI location of the capabilities pointer and
the value.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Capability ID
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
1
Register:
Offset:
Type:
Capability ID
A0h
Read-only
01h
Default:
4.38 Next-Item Pointer Register
The next-item pointer register indicates the next item in the linked list of the PCI power-management capabilities.
Because the PCI1410A functions include only one capabilities item, this register returns 0s when read.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Next-item pointer
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Offset:
Type:
Next-item pointer
A1h
Read-only
00h
Default:
4–26
4.39 Power Management Capabilities Register
This register contains information on the capabilities of the PC Card function related to power management. Both
PCI1410A CardBus bridge functions support D0, D1, D2, and D3 power states. See Table 4–15 for a complete
description of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Power management capabilities
R/W
1
R
1
R
1
R
1
R
1
R
1
R
1
R
0
R
0
R
0
R
1
R
0
R
0
R
0
R
0
R
1
Register:
Offset:
Type:
Power management capabilities
A2h
Read/Write, Read-only
FE21h
Default:
Table 4–15. Power Management Capabilities Register Description
BIT
SIGNAL
TYPE
FUNCTION
PME support. This 5-bit field indicates the power states from which the PCI1410A functions can assert
PME. A 0 (zero) for any bit indicates that the function cannot assert the PME signal while in that power state.
These five bits return 11111b when read. Each of these bits is described below:
15
PME_Support
R/W
R
Bit 15 defaults to the value 1, indicating the PME signal can be asserted from the D3
R/W because wake-up support from D3
cold
state. This bit is
is contingent on the system providing an auxiliary power source
cold
to the V
terminals for D3
cold
terminals. If the system designer chooses not to provide an auxiliary power source to the V
CC
CC
wake-up support, the BIOS should write a 0 to this bit.
14–11 PME_Support
Bit 14 contains the value 1, indicating that the PME signal can be asserted from D3 state.
hot
Bit 13 contains the value 1, indicating that the PME signal can be asserted from D2 state.
Bit 12 contains the value 1, indicating that the PME signal can be asserted from D1 state.
Bit 11 contains the value 1, indicating that the PME signal can be asserted from the D0 state.
D2 support. Bit 10 returns a 1 when read, indicating that the CardBus function supports the D2 device
power state.
10
D2_Support
R
D1 support. Bit 9 returns a 1 when read, indicating that the CardBus function supports the D1 device
power state.
9
D1_Support
RSVD
R
R
8–6
Reserved. Bits 8–6 return 0s when read.
Device-specific initialization. Bit 5 returns 1 when read, indicating that the CardBus controller function
requires special initialization (beyond the standard PCI configuration header) before the generic class
device driver is able to use it.
5
DSI
R
Auxiliary power source. Bit 4 is meaningful only if bit 15 (PME_Support, D3
it indicates that support for PME in D3
cold
proprietary delivery vehicle. When bit 4 is 0, it indicates that the function supplies its own auxiliary power
source.
) is set. When bit 4 is set,
requires auxiliary power supplied by the system by way of a
cold
4
AUX_PWR
R
PME clock. Bit 3 returns 0 when read, indicating that no host bus clock is required for the PCI1410A device
to generate PME.
3
PMECLK
VERSION
R
R
Version. Bits 2–0 return 001b when read, indicating that there are four bytes of general-purpose power
management (PM) registers as described in the PCI Bus Power Management Interface Specification.
2–0
4–27
4.40 Power Management Control/Status Register
The power management control/status register determines and changes the current power state of the PCI1410A
CardBus function. The contents of this register are not affected by the internally-generated reset caused by the
transition from D3
to D0 state. All PCI, ExCA, and CardBus registers are reset as a result of a D3
to D0 state
hot
hot
transition. TI-specific registers, PCI power management registers, and the legacy base address register are not reset.
See Table 4–16 for a complete description of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Power management control/status
R/C
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
Register:
Offset:
Type:
Power management control/status
A4h
Read-only, Read/Write, Read/Write to Clear
0000h
Default:
Table 4–16. Power Management Control/Status Register Description
BIT
SIGNAL
TYPE
FUNCTION
PME status. Bit 15 is set when the CardBus function normally would assert PME, independent
of the state of bit 8 (PME_EN). Bit 15 is cleared by a write back of 1, and this also clears PME
if PME was asserted by this function. Writing a 0 to this bit has no effect.
15
PMESTAT
R/C
Data scale. This 2-bit field returns 0s when read. The CardBus function does not return any
dynamic data, as indicated by bit 4 (DYN_DATA_PME_EN).
14–13
12–9
DATASCALE
DATASEL
R
R
Data select. This 4-bit field returns 0s when read. The CardBus function does not return any
dynamic data, as indicated by bit 4 (DYN_DATA_PME_EN).
PME enable. Bit 8 enables the function to assert PME. If this bit is cleared, the assertion of PME
is disabled.
8
PME_EN
RSVD
R/W
R
7–5
4
Reserved. Bits 7–5 return 0s when read.
Dynamic data PME enable. Bit 4 returns 0 when read, because the CardBus function does not
report dynamic data.
DYN_DATA_PME_EN
RSVD
R
3–2
R
Reserved. Bits 3–2 return 0s when read.
Power state. This 2-bit field is used both to determine the current power state of a function and
to set the function into a new power state. This field is encoded as:
00 = D0
01 = D1
10 = D2
1–0
PWR_STATE
R/W
11 = D3
hot
4–28
4.41 Power Management Control/Status Bridge Support Extensions Register
The power management control/status register bridge support extensions support PCI bridge-specific functionality.
See Table 4–17 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Power management control/status bridge support extensions
R
1
R
1
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Offset:
Type:
Power management control/status bridge support extensions
A6h
Read-only
C0h
Default:
Table 4–17. Power Management Control/Status Bridge Support Extensions Register Description
BIT
SIGNAL
TYPE
FUNCTION
BPCC_Enable. Bus power/clock control enable. This bit returns 1 when read.
This bit is encoded as:
0 = Bus power/clock control is disabled.
1 = Bus power/clock control is enabled (default).
7
BPCC_EN
R
A 0 indicates that the bus power/clock control policies defined in the PCI Bus Power Management
Interface Specification are disabled. When the bus power/clock control enable mechanism is disabled,
the bridge power management control/status register power state field (PCI offset A4h, see Section 4.40,
bits 1–0) cannot be used by the system software to control the power or the clock of the bridge secondary
bus. A 1 indicates that the bus power/clock control mechanism is enabled.
B2/B3 support for D3 . The state of this bit determines the action that is to occur as a direct result of
hot
programming the function to D3 . This bit is meaningful only if bit 7 (BPCC_EN) is a 1. This bit is encoded
hot
as:
6
B2_B3
RSVD
R
R
0 = When the bridge is programmed to D3 , its secondary bus will have its power removed (B3).
hot
1 = When the bridge function is programmed to D3 , its secondary bus PCI clock will be
hot
stopped (B2). (Default)
5–0
Reserved. Bits 5–0 return 0s when read.
4.42 Power Management Data Register
The power management data register returns 0s when read, because the CardBus functions do not report dynamic
data.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Power management data
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Offset:
Type:
Power management data
A7h
Read-only
00h
Default:
4–29
4.43 General-Purpose Event Status Register
The general-purpose event status register contains status bits that are set when events occur that are controlled by
the general-purpose control register. The bits in this register and the corresponding GPE are cleared by writing a 1
to the corresponding bit location. The status bits in this register do not depend upon the state of a corresponding bit
in the general-purpose enable register. See Table 4–18 for a complete description of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
General-purpose event status
R/C
0
R
0
R
0
R
0
R/C
0
R
0
R
0
R/C
0
R
0
R
0
R
0
R/C
0
R/C
0
R/C
0
R/C
0
R/C
0
Register:
Offset:
Type:
General-purpose event status
A8h
Read-only, Read/Clear
0000h
Default:
Table 4–18. General-Purpose Event Status Register Description
BIT
15
SIGNAL
ZV_STS
RSVD
TYPE
R/C
R
FUNCTION
PC card ZV status. Bit 15 is set on a change in status of bit 6 (ZVENABLE) in the card control register (PCI
offset 91h, see Section 4.32).
14–12
11
Reserved. Bits 14–12 return 0s when read.
Power change status. Bit 11 is set when software has changed the power state of the socket. A change
PWR_STS
RSVD
R/C
R
in either V
CC
or V for the socket causes this bit to be set.
PP
10–9
8
Reserved. Bits 10 and 9 return 0s when read.
12-V V request status. Bit 8 is set when software has changed the requested V
level to or from 12 V
PP
PP
VPP12_STS
R/C
for the PC Card socket.
7–5
4
RSVD
R
Reserved. Bits 7–5 return 0s when read.
GP4_STS
GP3_STS
GP2_STS
GP1_STS
GP0_STS
R/C
R/C
R/C
R/C
R/C
GPI4 status. Bit 4 is set on a change in status of the MFUNC5 terminal input level.
GPI3 status. Bit 3 is set on a change in status of the MFUNC4 terminal input level.
GPI2 status. Bit 2 is set on a change in status of the MFUNC2 terminal input level.
GPI1 status. Bit 1 is set on a change in status of the MFUNC1 terminal input level.
GPI0 status. Bit 0 is set on a change in status of the MFUNC0 terminal input level.
3
2
1
0
4–30
4.44 General-Purpose Event Enable Register
The general-purpose event enable register contains bits that are set to enable a GPE signal. The GPE signal is driven
until the corresponding status bit is cleared and the event is serviced. The GPE can be signaled only if one of the
multifunction terminals, MFUNC6–MFUNC0, is configured for GPE signaling. See Table 4–19 for a complete
description of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
General-purpose event enable
R/W
0
R
0
R
0
R
0
R/W
0
R
0
R
0
R/W
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
Type:
General-purpose event enable
AAh
Read-only, Read/Write
0000h
Default:
Table 4–19. General-Purpose Event Enable Register Description
BIT
15
SIGNAL
ZV_EN
TYPE
R/W
R
FUNCTION
PC card socket ZV enable. When bit 15 is set, a GPE is signaled on a change in status of bit 6 (ZVENABLE)
in the card control register (PCI offset 91h, see Section 4.32).
14–12
11
RSVD
Reserved. Bits 14–12 return 0s when read.
Power change enable. When bit 11 is set, a GPE is signaled when software has changed the power state
of the socket.
PWR_EN
RSVD
R/W
R
10–9
8
Reserved. Bits 10 and 9 return 0s when read.
12-V V
request enable. When bit 8 is set, a GPE is signaled when software has changed the requested
level to or from 12 V for the card socket.
PP
VPP12_EN
RSVD
R/W
R
V
PP
7–5
4
Reserved. Bits 7–5 return 0s when read.
GPI4 enable. When bit 4 is set, a GPE is signaled when there has been a change in status of the MFUNC5
terminal input level if configured as GPI4.
GP4_EN
R/W
GPI3 enable. When bit 3 is set, a GPE is signaled when there has been a change in status of the MFUNC4
terminal input level if configured as GPI3.
3
2
1
0
GP3_EN
GP2_EN
GP1_EN
GP0_EN
R/W
R/W
R/W
R/W
GPI2 enable. When bit 2 is set, a GPE is signaled when there has been a change in status of the MFUNC2
terminal input if configured as GPI2.
GPI1 enable. When bit 1 is set, a GPE is signaled when there has been a change in status of the MFUNC1
terminal input if configured as GPI1.
GPI0 enable. When bit 0 is set, a GPE is signaled when there has been a change in status of the MFUNC0
terminal input if configured as GPI0.
4–31
4.45 General-Purpose Input Register
The general-purpose input register provides the logical value of the data input from the GPI terminals, MFUNC5,
MFUNC4, and MFUNC2–MFUNC0. See Table 4–20 for a complete description of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
General-purpose input
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
X
R
X
R
X
R
X
R
X
Register:
Offset:
Type:
General-purpose input
ACh
Read-only
00XXh
Default:
Table 4–20. General-Purpose Input Register Description
FUNCTION
BIT
SIGNAL
RSVD
TYPE
15–5
R
R
R
R
R
R
Reserved. Bits 15–5 return 0s when read.
4
3
2
1
0
GPI4_DATA
GPI3_DATA
GPI2_DATA
GPI1_DATA
GPI0_DATA
GPI4 data bit. The value read from bit 4 represents the logical value of the data input from the MFUNC5 terminal.
GPI3 data bit. The value read from bit 3 represents the logical value of the data input from the MFUNC4 terminal.
GPI2 data bit. The value read from bit 2 represents the logical value of the data input from the MFUNC2 terminal.
GPI1 data bit. The value read from bit 1 represents the logical value of the data input from the MFUNC1 terminal.
GPI0 data bit. The value read from bit 0 represents the logical value of the data input from the MFUNC0 terminal.
4–32
4.46 General-Purpose Output Register
The general-purpose output register is used for control of the general-purpose outputs. See Table 4–21 for a
complete description of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
General-purpose output
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
Type:
General-purpose output
AEh
Read-only, Read/Write
0000h
Default:
Table 4–21. General-Purpose Output Register Description
BIT
SIGNAL
TYPE
FUNCTION
15–5
RSVD
R
Reserved. Bits 15–5 return 0s when read.
GPO4 data bit. The value written to bit 4 represents the logical value of the data driven to the MFUNC5
terminal if configured as GPO4. Read transactions return the last data value written.
4
3
2
1
0
GPO4_DATA
GPO3_DATA
GPO2_DATA
GPO1_DATA
GPO0_DATA
R/W
GPIO3 data bit. The value written to bit 3 represents the logical value of the data driven to the MFUNC4
terminal if configured as GPO3. Read transactions return the last data value written.
R/W
R/W
R/W
R/W
GPO2 data bit. The value written to bit 2 represents the logical value of the data driven to the MFUNC2
terminal if configured as GPO2. Read transactions return the last data value written.
GPO1 data bit. The value written to bit 1 represents the logical value of the data driven to the MFUNC1
terminal if configured as GPO1. Read transactions return the last data value written.
GPO0 data bit. The value written to bit 0 represents the logical value of the data driven to the MFUNC0
terminal if configured as GPO0. Read transactions return the last data value written.
4.47 Serial Bus Data Register
The serial bus data register is for programmable serial bus byte reads and writes. This register represents the data
when generating cycles on the serial bus interface. See Table 4–22 for a complete description of the register
contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Serial bus data
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
Type:
Serial bus data
B0h
Read/Write
00h
Default:
Table 4–22. Serial Bus Data Register Description
BIT
SIGNAL
TYPE
FUNCTION
Serial bus data. This bit field represents the data byte in a read or write transaction on the serial interface.
On reads, bit 5 (REQBUSY) in the serial bus control and status register (PCI offset B3h, see Section 4.50)
must be polled to verify that the contents of this register are valid.
7–0
SBDATA
R/W
4–33
4.48 Serial Bus Index Register
The serial bus index register is for programmable serial bus byte reads and writes. This register represents the byte
address when generating cycles on the serial bus interface. See Table 4–23 for a complete description of the register
contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Serial bus index
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
Type:
Serial bus index
B1h
Read/Write
00h
Default:
Table 4–23. Serial Bus Index Register Description
BIT
SIGNAL
TYPE
FUNCTION
7–0
SBINDEX
R/W
Serial bus index. This bit field represents the byte address in a read or write transaction on the serial interface.
4.49 Serial Bus Slave Address Register
The serial bus slave address register is for programmable serial bus byte read and write transactions. See Table 4–24
for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Serial bus slave address
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
Type:
Serial bus slave address
B2h
Read/Write
00h
Default:
Table 4–24. Serial Bus Slave Address Register Description
BIT
SIGNAL
TYPE
FUNCTION
Serial bus slave address. This bit field represents the slave address of a read or write transaction on the
serial interface.
7–1
SLAVADDR
R/W
R/W
Read/write command. Bit 0 indicates the read/write command bit presented to the serial bus on byte read
and write accesses
0
RWCMD
0 = A byte write access is requested to the serial bus interface.
1 = A byte read access is requested to the serial bus interface.
4–34
4.50 Serial Bus Control and Status Register
The serial bus control and status register communicates serial bus status information and selects the quick command
protocol. Bit 5 (REQBUSY) in this register must be polled during serial bus byte reads to indicate when data is valid
in the serial bus data register. See Table 4–25 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Serial bus control and status
R/W
0
R
0
R
0
R
0
R/C
0
R/W
0
R/C
0
R/C
0
Register:
Offset:
Type:
Serial bus control and status
B3h
Read-only, Read/Write, Read/Clear
00h
Default:
Table 4–25. Serial Bus Control and Status Register Description
BIT
7
SIGNAL
PROT_SEL
RSVD
TYPE
R/W
R
FUNCTION
Protocol select. When bit 7 is set, the send byte protocol is used on write requests and the receive byte
protocol is used on read commands. The word address byte (SBINDEX) in the serial bus index register (PCI
offset B1h, see Section 4.48) is not output by the PCI1410A device when bit 7 is set.
6
Reserved. Bit 6 returns 0 when read.
Requested serial bus access busy. Bit 5 indicates that a requested serial bus access (byte read or write)
is in progress. A request is made, and bit 5 is set, by writing to the serial bus slave address register (PCI
offset B2h, see Section 4.49). Bit 5 must be polled on reads from the serial bus interface. After the byte read
access has been requested, the read data is valid in the serial bus data register.
5
4
REQBUSY
ROMBUSY
R
R
Serial EEPROM busy status. Bit 4 indicates the status of the PCI1410A serial EEPROM circuitry. Bit 4 is
set during the loading of the subsystem ID and other default values from the serial bus EEPROM.
0 = Serial EEPROM circuitry is not busy.
1 = Serial EEPROM circuitry is busy.
Serial bus detect. Bit 3 is set when the serial bus interface is detected through pullup resistors on the VCCD0
and VCCD1 terminals after reset. If bit 3 is cleared, the MFUNC4 and MFUNC1 terminals can be used for
alternate functions such as general-purpose inputs and outputs.
0 = Serial bus interface is not detected.
3
SBDETECT
R/C
1 = Serial bus interface is detected.
Serial bus test. When bit 2 is set, the serial bus clock frequency is increased for test purposes.
0 = Serial bus clock is at normal operating frequency, ꢀ100 kHz (default).
1 = Serial bus clock frequency is increased for test purposes.
2
1
SBTEST
R/W
R/C
Requested serial bus access error. Bit 1 indicates when a data error occurs on the serial interface during
a requested cycle and may be set due to a missing acknowledge. Bit 1 is cleared by a write back of 1.
0 = No error is detected during user-requested byte read or write cycle.
REQ_ERR
1 = Data error is detected during user-requested byte read or write cycle.
EEPROM data error status. Bit 0 indicates when a data error occurs on the serial bus interface during the
auto-load from the serial bus EEPROM and may be set due to a missing acknowledge. Bit 0 also is set on
invalid EEPROM data formats. See Section 3.6.1, Serial Bus Interface Implementation, for details on
EEPROM data format. Bit 0 is cleared by a write back of 1.
0
ROM_ERR
R/C
0 = No error is detected during auto-load from serial bus EEPROM.
1 = Data error is detected during auto-load from serial bus EEPROM.
4–35
4–36
5 ExCA Compatibility Registers
The ExCA registers implemented in the PCI1410A device are register-compatible with the Intel 82365SL–DF
PCMCIA controller. The ExCA registers are identified by an offset value that is compatible with the legacy I/O
index/data scheme used on the Intel 82365 ISA controller. The ExCA registers are accessed through this scheme
by writing the register offset value into the index register (I/O base) and reading or writing the data register (I/O base
+ 1). The I/O base address used in the index/data scheme is programmed in the PC Card 16-bit I/F legacy mode base
address register (PCI offset 44h, see Section 4.28). The offsets from this base address run contiguous from 00h to
3Fh for the socket. See Figure 5–1 for an ExCA I/O-mapping illustration.
PCI1410A Configuration Registers
Host I/O Space
Offset
Offset
00h
PC Card
ExCA
10h
44h
Index
Data
Registers
CardBus Socket/ExCA Base Address
16-Bit Legacy-Mode Base Address
3Fh
Figure 5–1. ExCA Register Access Through I/O
The TI PCI1410A device also provides a memory-mapped alias of the ExCA registers by directly mapping them
into PCI memory space. They are located through the CardBus socket/ExCA base address register (PCI offset 10h,
see Section 4.12) at memory offset 800h. See Figure 5–2 for an ExCA memory-mapping illustration. This illustration
also identifies the CardBus socket-register mapping, which is mapped into the same 4K window at memory offset
0h.
Host
Memory Space
PCI1410A Configuration Registers
Offset
00h
Offset
CardBus
Socket
Registers
10h
44h
CardBus Socket/ExCA Base Address
16-Bit Legacy-Mode Base Address
20h
800h
ExCA
Registers
844h
Figure 5–2. ExCA Register Access Through Memory
5–1
The interrupt registers in the ExCA register set, as defined by the 82365SL–DL specification, control such card
functions as reset, type, interrupt routing, and interrupt enables. Special attention must be paid to the interrupt routing
registers and the host-interrupt signaling method selected for the PCI1410A device to ensure that all possible
PCI1410A interrupts potentially can be routed to the programmable interrupt controller. The ExCA registers that are
critical to the interrupt signaling are the ExCA interrupt and general control register (ExCA offset 03h, see Section 5.4)
and the ExCA card status-change-interrupt configuration register (ExCA offset 05h, see Section 5.6).
Access to I/O-mapped 16-bit PC cards is available to the host system via two ExCA I/O windows. These are regions
of host I/O address space into which the card I/O space is mapped. These windows are defined by start, end, and
offset addresses programmed in the ExCA registers described in this section. I/O windows have byte granularity.
Access to memory-mapped 16-bit PC Cards is available to the host system via five ExCA memory windows. These
are regions of host memory space into which the card memory space is mapped. These windows are defined by start,
end, and offset addresses programmed in the ExCA registers described in this section. Table 5–1 identifies each
ExCA register and its respective ExCA offset. Memory windows have 4-Kbyte granularity.
Table 5–1. ExCA Registers and Offsets
PCI MEMORY ADDRESS
OFFSET (HEX)
ExCA OFFSET
(HEX)
EXCA REGISTER NAME
Identification and revision
800
801
802
803
804
805
806
807
808
809
80A
80B
80C
80D
80E
80F
810
811
812
813
814
815
816
817
818
819
81A
81B
81C
81D
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
Interface status
Power control
Interrupt and general control
Card status-change
Card status-change-interrupt configuration
Address window enable
I / O window control
I / O window 0 start-address low-byte
I / O window 0 start-address high-byte
I / O window 0 end-address low-byte
I / O window 0 end-address high-byte
I / O window 1 start-address low-byte
I / O window 1 start-address high-byte
I / O window 1 end-address low-byte
I / O window 1 end-address high-byte
Memory window 0 start-address low-byte
Memory window 0 start-address high-byte
Memory window 0 end-address low-byte
Memory window 0 end-address high-byte
Memory window 0 offset-address low-byte
Memory window 0 offset-address high-byte
Card detect and general control
Reserved
12
13
14
15
16
17
18
19
1A
1B
1C
1D
Memory window 1 start-address low-byte
Memory window 1 start-address high-byte
Memory window 1 end-address low-byte
Memory window 1 end-address high-byte
Memory window 1 offset-address low-byte
Memory window 1 offset-address high-byte
5–2
Table 5–1. ExCA Registers and Offsets (Continued)
PCI MEMORY ADDRESS
OFFSET (HEX)
ExCA OFFSET
EXCA REGISTER NAME
Global control
(HEX)
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
–
81E
81F
820
821
822
823
824
825
826
827
828
829
82A
82B
82C
82D
82E
82F
830
831
832
833
834
835
836
837
838
839
83A
83B
83C
83D
83E
83F
840
841
842
843
844
Reserved
Memory window 2 start-address low-byte
Memory window 2 start-address high-byte
Memory window 2 end-address low-byte
Memory window 2 end-address high-byte
Memory window 2 offset-address low-byte
Memory window 2 offset-address high-byte
Reserved
Reserved
Memory window 3 start-address low-byte
Memory window 3 start-address high-byte
Memory window 3 end-address low-byte
Memory window 3 end-address high-byte
Memory window 3 offset-address low-byte
Memory window 3 offset-address high-byte
Reserved
Reserved
Memory window 4 start-address low-byte
Memory window 4 start-address high-byte
Memory window 4 end-address low-byte
Memory window 4 end-address high-byte
Memory window 4 offset-address low-byte
Memory window 4 offset-address high-byte
I/O window 0 offset-address low-byte
I/O window 0 offset-address high-byte
I/O window 1 offset-address low-byte
I/O window 1 offset-address high-byte
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Memory window 0 page
Memory window 1 page
–
Memory window 2 page
–
Memory window 3 page
–
Memory window 4 page
–
5–3
5.1 ExCA Identification and Revision Register
The ExCA identification and revision register provides host software with information on 16-bit PC Card support and
Intel 82365SL-DF compatibility. This register is read-only or read/write, depending on the setting of bit 5
(SUBSYSRW) in the system control register (PCI offset 80h, see Section 4.29). See Table 5–2 for a complete
description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA identification and revision
R
1
R
0
R/W
0
R/W
0
R/W
0
R/W
1
R/W
0
R/W
0
Register:
Offset:
Type:
ExCA identification and revision
CardBus socket address + 800h; ExCA offset 00h
Read-only, Read/Write
84h
Default:
Table 5–2. ExCA Identification and Revision Register Description
BIT
7–6
5–4
SIGNAL
IFTYPE
RSVD
TYPE
FUNCTION
Interface type. These bits, which are hardwired as 10b, identify the 16-bit PC Card support provided by the
PCI1410A device. The PCI1410A device supports both I/O and memory 16-bit PC cards.
R
R/W
Reserved. Bits 5 and 4 can be used for Intel 82365SL-DF emulation.
Intel 82365SL-DF revision. This field stores the Intel 82365SL-DF revision supported by the PCI1410A
device. Host software can read this field to determine compatibility to the Intel 82365SL-DF register set.
Writing 0010b to this field puts the controller in 82365SL mode. This field defaults to 0100b upon PCI1410A
reset.
3–0
365REV
R/W
5–4
5.2 ExCA Interface Status Register
The ExCA interface status register provides information on the current status of the PC Card interface. An X in the
default bit value indicates that the value of the bit after reset depends on the state of the PC Card interface. See
Table 5–3 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA interface status
R
0
R
0
R
X
R
X
R
X
R
X
R
X
R
X
Register:
Offset:
Type:
ExCA interface status
CardBus socket address + 801h; ExCA offset 01h
Read-only
Default:
00XX XXXXb
Table 5–3. ExCA Interface Status Register Description
FUNCTION
BIT
SIGNAL
TYPE
7
RSVD
R
Reserved. Bit 7 returns 0 when read.
Card Power. Bit 6 indicates the current power status of the PC Card socket. This bit reflects how the ExCA
power control register (ExCA offset 02h, see Section 5.3) is programmed. Bit 6 is encoded as:
6
5
CARDPWR
READY
R
R
0 = V
1 = V
and V
and V
to the socket are turned off (default).
to the socket are turned on.
CC
CC
PP
PP
Ready. Bit 5 indicates the current status of the READY signal at the PC Card interface.
0 = PC Card is not ready for data transfer.
1 = PC Card is ready for data transfer.
Card write protect. Bit 4 indicates the current status of WP at the PC Card interface. This signal reports to
the PCI1410A device whether or not the memory card is write protected. Furthermore, write protection for
an entire PCI1410A 16-bit memory window is available by setting bit 7 (WINWP) in the ExCA memory
window offset-address high-byte register (see Section 5.18).
4
CARDWP
R
0 = WP is 0. PC Card is read/write.
1 = WP is 1. PC Card is read-only.
Card detect 2. Bit 3 indicates the status of CD2 at the PC Card interface. Software can use this and bit 2
(CDETECT1) to determine if a PC Card is fully seated in the socket.
0 = CD2 is 1. No PC Card is inserted.
3
2
CDETECT2
CDETECT1
R
R
1 = CD2 is 0. PC Card is at least partially inserted.
Card detect 1. Bit 2 indicates the status of CD1 at the PC Card interface. Software can use this and bit 3
(CDETECT2) to determine if a PC Card is fully seated in the socket.
0 = CD1 is 1. No PC Card is inserted.
1 = CD1 is 0. PC Card is at least partially inserted.
Battery voltage detect. When a 16-bit memory card is inserted, the field indicates the status of the battery
voltage detect signals (BVD1, BVD2) at the PC Card interface, where bit 1 reflects the BVD2 status and bit 0
reflects BVD1.
00 = Battery is dead.
01 = Battery is dead.
10 = Battery is low; warning.
11 = Battery is good.
1–0
BVDSTAT
R
When a 16-bit I/O card is inserted, this field indicates the status of SPKR (bit 1) and STSCHG (bit 0) at the
PC Card interface. In this case, the two bits in this field directly reflect the current state of these card outputs.
5–5
5.3 ExCA Power Control Register
The ExCA power control register provides PC Card power control. Bit 7 (COE) of this register controls the 16-bit output
enables on the socket interface, and can be used for power management in 16-bit PC Card applications. The
PCI1410A device supports both the 82365SL and 82365SL-DF register models. Bits 3–0 (365REV filed) of the ExCA
identification and revision register (ExCA offset 00h, see Section 5.1) control which register model is supported. See
Table 5–4 and Table 5–5 for a complete description of the register contents.
5.3.1 Intel 82365SL Support
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA power control
R/W
0
R
0
R/W
0
R/W
0
R
0
R
0
R/W
0
R/W
0
Register:
Offset:
Type:
ExCA power control
CardBus socket address + 802h; ExCA offset 02h
Read-only, Read/Write
00h
Default:
Table 5–4. ExCA Power Control Register 82365SL Support Description
BIT
7
SIGNAL
COE
TYPE
R/W
R
FUNCTION
Card output enable. Bit 7 controls the state of all of the 16-bit outputs on the PCI1410A device. This bit
is encoded as:
0 = 16-bit PC Card outputs are disabled (default).
1 = 16-bit PC Card outputs are enabled.
6
RSVD
Reserved. Bit 6 returns 0 when read.
Auto power switch enable. This bit is enabled by bit 7 of the system control register (PCI offset 80h, see
Section 4.29).
5
AUTOPWRSWEN
R/W
0 = Automatic socket power switching based on card detects is disabled.
1 = Automatic socket power switching based on card detects is enabled.
PC Card power enable.
0 = V
1 = V
= V
PP1
= V = No connection
PP2
CC
CC
4
CAPWREN
RSVD
R/W
R
is enabled and controlled by bit 2 (ExCAPower) of the system control register (PCI offset 80h,
and V are controlled according to bits 1–0 (EXCAVPP field).
see Section 4.29), V
PP1
PP2
Reserved. Bits 3 and 2 return 0s when read.
PC Card V power control. Bits 1 and 0 are used to request changes to card V . The PCI1410A device
3–2
PP PP
ignores this field unless V
to the socket is enabled (that is, 5 V or 3.3 V). This field is encoded as:
CC
00 = No connection (default)
01 = V
1–0
EXCAVPP
R/W
CC
10 = 12 V
11 = Reserved
5–6
5.3.2 Intel 82365SL-DF Support
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA power control
R/W
0
R
0
R
0
R/W
0
R/W
0
R
0
R/W
0
R/W
0
Register:
Offset:
Type:
ExCA power control
CardBus socket address + 802h; ExCA offset 02h
Read-only, Read/Write
00h
Default:
Table 5–5. ExCA Power Control Register 82365SL-DF Support Description
BIT
7
SIGNAL
COE
TYPE
R/W
R
FUNCTION
Card output enable. Bit 7 controls the state of all of the 16-bit outputs on the PCI1410A device. This bit is
encoded as:
0 = 16-bit PC Card outputs are disabled (default).
1 = 16-bit PC Card outputs are enabled.
6–5
RSVD
Reserved. Bits 6 and 5 return 0s when read.
V
CC
. Bits 4 and 3 are used to request changes to card V . This field is encoded as:
CC
00 = 0 V (default)
01 = 0 V reserved
10 = 5 V
4–3
EXCAVCC
RSVD
R/W
R
11 = 3.3 V
2
Reserved. Bit 2 returns 0 when read.
PC Card V power control. Bits 1 and 0 are used to request changes to card V . The PCI1410A device
PP PP
ignores this field unless V
to the socket is enabled (that is, 5 V or 3.3 V). This field is encoded as:
CC
00 = No connection (default)
01 = V
1–0
EXCAVPP
R/W
CC
10 = 12 V
11 = Reserved
5–7
5.4 ExCA Interrupt and General Control Register
The ExCA interrupt and general control register controls interrupt routing for I/O interrupts, as well as other critical
16-bit PC Card functions. See Table 5–6 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA interrupt and general control
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
Type:
ExCA interrupt and general control
CardBus socket address + 803h; ExCA offset 03h
Read/Write
00h
Default:
Table 5–6. ExCA Interrupt and General Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
Card ring indicate enable. Bit 7 enables the ring indicate function of BVD1/RI. This bit is encoded as:
0 = Ring indicate is disabled (default).
7
RINGEN
R/W
1 = Ring indicate is enabled.
Card reset. Bit 6 controls the 16-bit PC Card RESET, and allows host software to force a card reset. Bit 6
affects 16-bit cards only. This bit is encoded as:
6
5
RESET
R/W
R/W
0 = RESET signal is asserted (default).
1 = RESET signal is deasserted.
Card type. Bit 5 indicates the PC Card type. This bit is encoded as:
0 = Memory PC Card is installed (default).
1 = I/O PC Card is installed.
CARDTYPE
PCI interrupt CSC routing enable bit. When bit 4 is set (high), the card status-change interrupts are routed
to PCI interrupts. When low, the card status-change interrupts are routed using bits 7–4 (CSCSELECT field)
in the ExCA card status-change interrupt configuration register (ExCA offset 05h, see Section 5.6). This bit
is encoded as:
4
CSCROUTE
R/W
0 = CSC interrupts are routed by ExCA registers (default).
1 = CSC interrupts are routed to PCI interrupts.
Card interrupt select for I/O PC Card functional interrupts. Bits 3–0 select the interrupt routing for I/O
PC Card functional interrupts. This field is encoded as:
0000 = No interrupt routing (default). CSC interrupts routed to PCI interrupts. These bit settings are
ORed with bit 4 (CSCROUTE) for backwards compatibility.
0001 = IRQ1 enabled
0010 = SMI enabled
0011 = IRQ3 enabled
0100 = IRQ4 enabled
0101 = IRQ5 enabled
3–0
INTSELECT
R/W
0100 = IRQ6 enabled
0111 = IRQ7 enabled
1000 = IRQ8 enabled
1001 = IRQ9 enabled
1010 = IRQ10 enabled
1011 = IRQ11 enabled
1100 = IRQ12 enabled
1101 = IRQ13 enabled
1110 = IRQ14 enabled
1111 = IRQ15 enabled
5–8
5.5 ExCA Card Status-Change Register
The ExCA card status-change register controls interrupt routing for I/O interrupts, as well as other critical 16-bit PC
Card functions. The register enables these interrupt sources to generate an interrupt to the host. When the interrupt
source is disabled, the corresponding bit in this register always reads 0. When an interrupt source is enabled, the
corresponding bit in this register is set to indicate that the interrupt source is active. After generating the interrupt to
the host, the interrupt service routine must read this register to determine the source of the interrupt. The interrupt
service routine is responsible for resetting the bits in this register as well. Resetting a bit is accomplished by one of
two methods: a read of this register or an explicit writeback of 1 to the status bit. The choice of these two methods
is based on bit 2 (interrupt flag clear mode select) in the ExCA global control register (ExCA offset 1Eh, see
Section 5.20). See Table 5–7 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA card status-change
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Offset:
Type:
ExCA card status-change
CardBus socket address + 804h; ExCA offset 04h
Read-only
00h
Default:
Table 5–7. ExCA Card Status-Change Register Description
BIT
SIGNAL
TYPE
FUNCTION
7–4
RSVD
R
R
Reserved. Bits 7–4 return 0s when read.
Card detect change. Bit 3 indicates whether a change on CD1 or CD2 occurred at the PC Card interface.
This bit is encoded as:
3
2
CDCHANGE
0 = No change is detected on either CD1 or CD2.
1 = Change is detected on either CD1 or CD2.
Ready change. When a 16-bit memory is installed in the socket, bit 2 includes whether the source of a
PCI1410A interrupt was due to a change on READY at the PC Card interface, indicating that the PC Card
is now ready to accept new data. This bit is encoded as:
READYCHANGE
R
R
R
0 = No low-to-high transition is detected on READY (default).
1 = Detected low-to-high transition on READY.
When a 16-bit I/O card is installed, bit 2 is always 0.
Battery warning change. When a 16-bit memory card is installed in the socket, bit 1 indicates whether the
source of a PCI1410A interrupt was due to a battery-low warning condition. This bit is encoded as:
0 = No battery warning condition (default)
1
0
BATWARN
BATDEAD
1 = Detected battery warning condition.
When a 16-bit I/O card is installed, bit 1 is always 0.
Battery dead or status change. When a 16-bit memory card is installed in the socket, bit 0 indicates whether
the source of a PCI1410A interrupt was due to a battery-dead condition. This bit is encoded as:
0 = STSCHG is deasserted (default).
1 = STSCHG is asserted.
Ring indicate. When the PCI1410A device is configured for ring-indicate operation, bit 0 indicates the
status of RI.
5–9
5.6 ExCA Card Status-Change-Interrupt Configuration Register
The ExCA card status-change-interrupt configuration register controls interrupt routing for card status-change
interrupts, as well as masking CSC interrupt sources. See Table 5–8 for a complete description of the register
contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA status-change-interrupt configuration
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
Type:
ExCA card status-change-interrupt configuration
CardBus socket address + 805h; ExCA offset 05h
Read/Write
00h
Default:
Table 5–8. ExCA Card Status-Change-Interrupt Configuration Register Description
BIT
SIGNAL
TYPE
FUNCTION
Interrupt select for card status change. Bits 7–4 select the interrupt routing for card status change
interrupts.
0000 = CSC interrupts routed to PCI interrupts if bit 5 (CSC) of the diagnostic register (PCI offset 93h, see
Section 4.34) is set to 1. In this case bit 4 (CSCROUTE) of the ExCA interrupt and general control register
(ExCA offset 03h, see Section 5.4) is a don’t care. This is the default setting.
0000 = No ISA interrupt routing if bit 5 (CSC) of the diagnostic register (PCI offset 93h, see Section 4.34)
is set to 0. In this case, CSC interrupts are routed to PCI interrupts by setting bit 4 (CSCROUTE) of the
ExCA interrupt and general control register (ExCA offset 03h, see Section 5.4) to 1.
7–4
CSCSELECT
R/W
This field is encoded as:
0000 = No interrupt routing (default)
0001 = IRQ1 enabled
0010 = SMI enabled
0011 = IRQ3 enabled
0100 = IRQ4 enabled
0101 = IRQ5 enabled
0110 = IRQ6 enabled
0111 = IRQ7 enabled
1000 = IRQ8 enabled
1001 = IRQ9 enabled
1010 = IRQ10 enabled
1011 = IRQ11 enabled
1100 = IRQ12 enabled
1101 = IRQ13 enabled
1110 = IRQ14 enabled
1111 = IRQ15 enabled
Card detect enable. Bit 3 enables interrupts on CD1 or CD2 changes. This bit is encoded as:
0 = Disables interrupts on CD1 or CD2 line changes (default).
3
2
CDEN
R/W
R/W
1 = Enables interrupts on CD1 or CD2 line changes.
Ready enable. Bit 2 enables/disables a low-to-high transition on PC Card READY to generate a host
interrupt. This interrupt source is considered a card status change. This bit is encoded as:
0 = Disables host interrupt generation (default).
READYEN
1 = Enables host interrupt generation.
Battery warning enable. Bit 1 enables/disables a battery warning condition to generate a CSC interrupt.
This bit is encoded as:
1
0
BATWARNEN
BATDEADEN
R/W
R/W
0 = Disables host interrupt generation (default).
1 = Enables host interrupt generation.
Battery-dead enable. Bit 0 enables/disables a battery-dead condition on a memory PC Card or assertion
of the STSCHG I/O PC Card signal to generate a CSC interrupt.
0 = Disables host interrupt generation (default).
1 = Enables host interrupt generation.
5–10
5.7 ExCA Address Window Enable Register
The ExCA address window enable register enables/disables the memory and I/O windows to the 16-bit PC Card. By
default, all windows to the card are disabled. The PCI1410A device does not acknowledge PCI memory or I/O cycles
to the card if the corresponding enable bit in this register is 0, regardless of the programming of the ExCA memory
or I/O window start/end/offset address registers. See Table 5–9 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA address window enable
R/W
0
R/W
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
Type:
ExCA address window enable
CardBus socket address + 806h; ExCA offset 06h
Read-only, Read/Write
00h
Default:
Table 5–9. ExCA Address Window Enable Register Description
BIT
SIGNAL
TYPE
FUNCTION
I/O window 1 enable. Bit 7 enables/disables I/O window 1 for the PC Card. This bit is encoded as:
0 = I/O window 1 is disabled (default).
7
IOWIN1EN
R/W
1 = I/O window 1 is enabled.
I/O window 0 enable. Bit 6 enables/disables I/O window 0 for the PC Card. This bit is encoded as:
0 = I/O window 0 is disabled (default).
6
5
IOWIN0EN
RSVD
R/W
R
1 = I/O window 0 is enabled.
Reserved. Bit 5 returns 0 when read.
Memory window 4 enable. Bit 4 enables/disables memory window 4 for the PC Card. This bit is
encoded as:
4
3
2
1
0
MEMWIN4EN
MEMWIN3EN
MEMWIN2EN
MEMWIN1EN
MEMWIN0EN
R/W
R/W
R/W
R/W
R/W
0 = Memory window 4 is disabled (default).
1 = Memory window 4 is enabled.
Memory window 3 enable. Bit 3 enables/disables memory window 3 for the PC Card. This bit is
encoded as:
0 = Memory window 3 is disabled (default).
1 = Memory window 3 is enabled.
Memory window 2 enable. Bit 2 enables/disables memory window 2 for the PC Card. This bit is
encoded as:
0 = Memory window 2 is disabled (default).
1 = Memory window 2 is enabled.
Memory window 1 enable. Bit 1 enables/disables memory window 1 for the PC Card. This bit is
encoded as:
0 = Memory window 1 is disabled (default).
1 = Memory window 1 is enabled.
Memory window 0 enable. Bit 0 enables/disables memory window 0 for the PC Card. This bit is
encoded as:
0 = Memory window 0 is disabled (default).
1 = Memory window 0 is enabled.
5–11
5.8 ExCA I/O Window Control Register
The ExCA I/O window control register contains parameters related to I/O window sizing and cycle timing. See
Table 5–10 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA I/O window control
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
Type:
ExCA I/O window control
CardBus socket address + 807h; ExCA offset 07h
Read/Write
00h
Default:
Table 5–10. ExCA I/O Window Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
I/O window 1 wait state. Bit 7 controls the I/O window 1 wait state for 16-bit I/O accesses. Bit 7 has no effect
on 8-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel 82365SL-DF
PCMCIA controller. This bit is encoded as:
7
WAITSTATE1
R/W
R/W
0 = 16-bit cycles have standard length (default).
1 = 16-bit cycles are extended by one equivalent ISA wait state.
I/O window 1 zero wait state. Bit 6 controls the I/O window 1 wait state for 8-bit I/O accesses. Bit 6 has
no effect on 16-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel
82365SL-DF PCMCIA controller. This bit is encoded as:
6
ZEROWS1
0 = 8-bit cycles have standard length (default).
1 = 8-bit cycles are reduced to equivalent of three ISA cycles.
I/O window 1 IOIS16 source. Bit 5 controls the I/O window 1 automatic data-sizing feature that uses IOIS16
from the PC Card to determine the data width of the I/O data transfer. This bit is encoded as:
0 = Window data width is determined by DATASIZE1, bit 4 (default).
5
4
IOSIS16W1
DATASIZE1
R/W
R/W
1 = Window data width is determined by IOIS16.
I/O window 1 data size. Bit 4 controls the I/O window 1 data size. Bit 4 is ignored if bit 5 (IOSIS16W1) is
set. This bit is encoded as:
0 = Window data width is 8 bits (default).
1 = Window data width is 16 bits.
I/O window 0 wait state. Bit 3 controls the I/O window 0 wait state for 16-bit I/O accesses. Bit 3 has no effect
on 8-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel 82365SL-DF
PCMCIA controller. This bit is encoded as:
3
2
WAITSTATE0
ZEROWS0
R/W
R/W
0 = 16-bit cycles have standard length (default).
1 = 16-bit cycles are extended by one equivalent ISA wait state.
I/O window 0 zero wait state. Bit 2 controls the I/O window 0 wait state for 8-bit I/O accesses. Bit 2 has
no effect on 16-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel
82365SL-DF PCMCIA controller. This bit is encoded as:
0 = 8-bit cycles have standard length (default).
1 = 8-bit cycles are reduced to equivalent of three ISA cycles.
I/O window 0 IOIS16 source. Bit 1 controls the I/O window 0 automatic data sizing feature that uses IOIS16
from the PC Card to determine the data width of the I/O data transfer. This bit is encoded as:
0 = Window data width is determined by DATASIZE0, bit 0 (default).
1
0
IOSIS16W0
DATASIZE0
R/W
R/W
1 = Window data width is determined by IOIS16.
I/O window 0 data size. Bit 0 controls the I/O window 0 data size. Bit 0 is ignored if bit 1 (IOSIS16W0) is
set. This bit is encoded as:
0 = Window data width is 8 bits (default).
1 = Window data width is 16 bits.
5–12
5.9 ExCA I/O Windows 0 and 1 Start-Address Low-Byte Registers
These registers contain the low byte of the 16-bit I/O window start address for I/O windows 0 and 1. The 8 bits of these
registers correspond to the lower 8 bits of the start address.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA I/O windows 0 and 1 start-address low-byte
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
Register:
Offset:
ExCA I/O window 0 start-address low-byte
CardBus socket address + 808h; ExCA offset 08h
ExCA I/O window 1 start-address low-byte
CardBus socket address + 80Ch; ExCA offset 0Ch
Read/Write
Type:
Default:
00h
5.10 ExCA I/O Windows 0 and 1 Start-Address High-Byte Registers
These registers contain the high byte of the 16-bit I/O window start address for I/O windows 0 and 1. The 8 bits of
these registers correspond to the upper 8 bits of the start address.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA I/O windows 0 and 1 start-address high-byte
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
Register:
Offset:
ExCA I/O window 0 start-address high-byte
CardBus socket address + 809h; ExCA offset 09h
ExCA I/O window 1 start-address high-byte
CardBus socket address + 80Dh; ExCA offset 0Dh
Read/Write
Type:
Default:
00h
5–13
5.11 ExCA I/O Windows 0 and 1 End-Address Low-Byte Registers
These registers contain the low byte of the 16-bit I/O window end address for I/O windows 0 and 1. The 8 bits of these
registers correspond to the lower 8 bits of the end address.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA I/O windows 0 and 1 end-address low-byte
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
Register:
Offset:
ExCA I/O window 0 end-address low-byte
CardBus socket address + 80Ah; ExCA offset 0Ah
ExCA I/O window 1 end-address low-byte
CardBus socket address + 80Eh; ExCA offset 0Eh
Read/Write
Type:
Default:
00h
5.12 ExCA I/O Windows 0 and 1 End-Address High-Byte Registers
These registers contain the high byte of the 16-bit I/O window end address for I/O windows 0 and 1. The 8 bits of these
registers correspond to the upper 8 bits of the end address.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA I/O windows 0 and 1 end-address high-byte
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
Register:
Offset:
ExCA I/O window 0 end-address high-byte
CardBus socket address + 80Bh; ExCA offset 0Bh
ExCA I/O window 1 end-address high-byte
CardBus socket address + 80Fh; ExCA offset 0Fh
Read/Write
Type:
Default:
00h
5–14
5.13 ExCA Memory Windows 0–4 Start-Address Low-Byte Registers
These registers contain the low byte of the 16-bit memory window start address for memory windows 0, 1, 2, 3, and
4. The 8 bits of these registers correspond to bits A19–A12 of the start address.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA memory windows 0–4 start-address low-byte
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
ExCA memory window 0 start-address low-byte
CardBus socket address + 810h; ExCA offset 10h
ExCA memory window 1 start-address low-byte
CardBus socket address + 818h; ExCA offset 18h
ExCA memory window 2 start-address low-byte
CardBus socket address + 820h; ExCA offset 20h
ExCA memory window 3 start-address low-byte
CardBus socket address + 828h; ExCA offset 28h
ExCA memory window 4 start-address low-byte
CardBus socket address + 830h; ExCA offset 30h
Read/Write
Register:
Offset:
Register:
Offset:
Register:
Offset:
Register:
Offset:
Type:
Default:
00h
5–15
5.14 ExCA Memory Windows 0–4 Start-Address High-Byte Registers
These registers contain the high nibble of the 16-bit memory window start address for memory windows 0, 1, 2, 3,
and 4. The lower 4 bits of these registers correspond to bits A23–A20 of the start address. In addition, the memory
window data width and wait states are set in this register. See Table 5–11 for a complete description of the register
contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA memory windows 0–4 start-address high byte
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
ExCA memory window 0 start-address high-byte
CardBus socket address + 811h; ExCA offset 11h
ExCA memory window 1 start-address high-byte
CardBus socket address + 819h; ExCA offset 19h
ExCA memory window 2 start-address high-byte
CardBus socket address + 821h; ExCA offset 21h
ExCA memory window 3 start-address high-byte
CardBus socket address + 829h; ExCA offset 29h
ExCA memory window 4 start-address high-byte
CardBus socket address + 831h; ExCA offset 31h
Read/Write
Register:
Offset:
Register:
Offset:
Register:
Offset:
Register:
Offset:
Type:
Default:
00h
Table 5–11. ExCA Memory Windows 0–4 Start-Address High-Byte Registers Description
BIT
SIGNAL
TYPE
FUNCTION
Data size. Bit 7 controls the memory window data width. This bit is encoded as:
0 = Window data width is 8 bits (default).
7
DATASIZE
R/W
1 = Window data width is 16 bits.
Zero wait state. Bit 6 controls the memory window wait state for 8- and 16-bit accesses. This wait-state timing
emulates the ISA wait state used by the Intel 82365SL-DF PCMCIA controller. This bit is encoded as:
0 = 8- and 16-bit cycles have standard length (default).
6
ZEROWAIT
R/W
1 = 8-bit cycles are reduced to equivalent of three ISA cycles.
16-bit cycles are reduced to equivalent of two ISA cycles.
5–4
3–0
SCRATCH
STAHN
R/W
R/W
Scratch-pad bits. Bits 5 and 4 have no effect on memory window operation.
Start-address high nibble. Bits 3–0 represent the upper address bits A23–A20 of the memory window
start address.
5–16
5.15 ExCA Memory Windows 0–4 End-Address Low-Byte Registers
These registers contain the low byte of the 16-bit memory window end address for memory windows 0, 1, 2, 3, and
4. The 8 bits of these registers correspond to bits A19–A12 of the end address.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA memory windows 0–4 end-address low-byte
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
ExCA memory window 0 end-address low-byte
CardBus socket address + 812h; ExCA offset 12h
ExCA memory window 1 end-address low-byte
CardBus socket address + 81Ah; ExCA offset 1Ah
ExCA memory window 2 end-address low-byte
CardBus socket address + 822h; ExCA offset 22h
ExCA memory window 3 end-address low-byte
CardBus socket address + 82Ah; ExCA offset 2Ah
ExCA memory window 4 end-address low-byte
CardBus socket address + 832h; ExCA offset 32h
Read/Write
Register:
Offset:
Register:
Offset:
Register:
Offset:
Register:
Offset:
Type:
Default:
00h
5–17
5.16 ExCA Memory Windows 0–4 End-Address High-Byte Registers
These registers contain the high nibble of the 16-bit memory window end address for memory windows 0, 1, 2, 3,
and 4. The lower 4 bits of these registers correspond to bits A23–A20 of the end address. In addition, the memory
window wait states are set in this register. See Table 5–12 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA memory windows 0–4 end-address high-byte
R/W
0
R/W
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
ExCA memory window 0 end-address high-byte
CardBus socket address + 813h; ExCA offset 13h
ExCA memory window 1 end-address high-byte
CardBus socket address + 81Bh; ExCA offset 1Bh
ExCA memory window 2 end-address high-byte
CardBus socket address + 823h; ExCA offset 23h
ExCA memory window 3 end-address high-byte
CardBus socket address + 82Bh; ExCA offset 2Bh
ExCA memory window 4 end-address high-byte
CardBus socket address + 833h; ExCA offset 33h
Read-only, Read/Write
Register:
Offset:
Register:
Offset:
Register:
Offset:
Register:
Offset:
Type:
Default:
00h
Table 5–12. ExCA Memory Windows 0–4 End-Address High-Byte Registers Description
BIT
SIGNAL
TYPE
FUNCTION
Wait state. Bits 7 and 6 specify the number of equivalent ISA wait states to be added to 16-bit memory accesses.
The number of wait states added is equal to the binary value of these two bits.
7–6
MEMWS
R/W
5–4
3–0
RSVD
R
Reserved. Bits 5 and 4 return 0s when read.
ENDHN
R/W
End-address high nibble. Bits 3–0 represent the upper address bits A23–A20 of the memory window end address.
5–18
5.17 ExCA Memory Windows 0–4 Offset-Address Low-Byte Registers
These registers contain the low byte of the 16-bit memory window offset address for memory windows 0, 1, 2, 3, and
4. The 8 bits of these registers correspond to bits A19–A12 of the offset address.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA memory windows 0–4 offset-address low-byte
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
ExCA memory window 0 offset-address low-byte
CardBus socket address + 814h; ExCA offset 14h
ExCA memory window 1 offset-address low-byte
CardBus socket address + 81Ch; ExCA offset 1Ch
ExCA memory window 2 offset-address low-byte
CardBus socket address + 824h; ExCA offset 24h
ExCA memory window 3 offset-address low-byte
CardBus socket address + 82Ch; ExCA offset 2Ch
ExCA memory window 4 offset-address low-byte
CardBus socket address + 834h; ExCA offset 34h
Read/Write
Register:
Offset:
Register:
Offset:
Register:
Offset:
Register:
Offset:
Type:
Default:
00h
5–19
5.18 ExCA Memory Windows 0–4 Offset-Address High-Byte Registers
These registers contain the high 6 bits of the 16-bit memory window offset address for memory windows 0, 1, 2, 3,
and 4. The lower 6 bits of these registers correspond to bits A25–A20 of the offset address. In addition, the write
protection and common/attribute memory configurations are set in this register. See Table 5–13 for a complete
description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA memory windows 0–4 offset-address high-byte
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
ExCA memory window 0 offset-address high-byte
CardBus socket address + 815h; ExCA offset 15h
ExCA memory window 1 offset-address high-byte
CardBus socket address + 81Dh; ExCA offset 1Dh
ExCA memory window 2 offset-address high-byte
CardBus socket address + 825h; ExCA offset 25h
ExCA memory window 3 offset-address high-byte
CardBus socket address + 82Dh; ExCA offset 2Dh
ExCA memory window 4 offset-address high-byte
CardBus socket address + 835h; ExCA offset 35h
Read/Write
Register:
Offset:
Register:
Offset:
Register:
Offset:
Register:
Offset:
Type:
Default:
00h
Table 5–13. ExCA Memory Windows 0–4 Offset-Address High-Byte Registers Description
BIT
SIGNAL TYPE
FUNCTION
Write protect. Bit 7 specifies whether write operations to this memory window are enabled. This bit is encoded as:
0 = Write operations are allowed (default).
7
WINWP
R/W
R/W
1 = Write operations are not allowed.
Bit 6 specifies whether this memory window is mapped to card attribute or common memory. This bit is encoded
as:
6
REG
0 = Memory window is mapped to common memory (default).
1 = Memory window is mapped to attribute memory.
5–0
OFFHB
R/W Offset-address high byte. Bits 5–0 represent the upper address bits A25–A20 of the memory window offset address.
5–20
5.19 ExCA Card Detect and General Control Register
The ExCA card detect and general control register controls how the ExCA registers for the socket respond to card
removal, and reports the status of VS1 and VS2 at the PC Card interface. See Table 5–14 for a complete description
of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA I/O card detect and general control
R
X
R
X
R/W
0
R/W
0
R
0
R
0
R/W
0
R
0
Register:
Offset:
Type:
ExCA card detect and general control
CardBus socket address + 816h; ExCA offset 16h
Read-only, Read/Write
Default:
XX00 0000b
Table 5–14. ExCA Card Detect and General Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
VS2 state. Bit 7 reports the current state of VS2 at the PC Card interface and, therefore, has no default value.
7
VS2STAT
R
0 = VS2 low
1 = VS2 high
VS1 state. Bit 6 reports the current state of VS1 at the PC Card interface and, therefore, has no default value.
6
5
VS1STAT
SWCSC
R
0 = VS1 low
1 = VS1 high
Software card-detect interrupt. If bit 3 (CDEN) in the ExCA card status-change-interrupt configuration
register (ExCA offset 05h, see Section 5.6) is set, writing a 1 to bit 5 causes a card-detect
card-status-change interrupt for the associated card socket. If bit 3 (CDEN) in the ExCA card
status-change-interrupt configuration register (see Section 5.6) is cleared to 0, writing a 1 to bit 5 has no
effect. A read operation of this bit always returns 0.
R/W
Card-detect resume enable. If bit 4 is set to 1, once a card-detect change has been detected on CD1 and
CD2 inputs, RI_OUT goes from high to low. RI_OUT remains low until bit 0 (card status change) in the ExCA
card status-change register (ExCA offset 04h, see Section 5.5) is cleared. If this bit is 0, the card-detect
resume functionality is disabled.
4
CDRESUME
R/W
0 = Card-detect resume is disabled (default).
1 = Card-detect resume is enabled.
3–2
1
RSVD
REGCONFIG
RSVD
R
R/W
R
Reserved. Bits 3 and 2 return 0s when read.
Register configuration on card removal. Bit 1 controls how the ExCA registers for the socket react to a card
removal event. This bit is encoded as:
0 = No change to ExCA registers on card removal (default)
1 = Reset ExCA registers on card removal
0
Reserved. Bit 0 returns 0 when read.
5–21
5.20 ExCA Global Control Register
The ExCA global control register controls the PC Card socket. The host interrupt mode bits in this register are retained
for Intel 82365SL-DF compatibility. See Table 5–15 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA global control
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
Type:
ExCA global control
CardBus socket address + 81Eh; ExCA offset 1Eh
Read-only, Read/Write
00h
Default:
Table 5–15. ExCA Global Control Register Description
FUNCTION
BIT
7–5
4
SIGNAL
RSVD
TYPE
R
Reserved. Bits 7–5 return 0s when read.
This bit has no assigned function.
No function
R/W
Level/edge interrupt mode select. Bit 3 selects the signaling mode for the PCI1410A host interrupt. This bit
is encoded as:
3
2
1
INTMODE
IFCMODE
CSCMODE
R/W
R/W
R/W
0 = Host interrupt is edge mode (default).
1 = Host interrupt is level mode.
Interrupt flag clear mode select. Bit 2 selects the interrupt flag clear mechanism for the flags in the ExCA
card status change register (ExCA offset 04h, see Section 5.5). This bit is encoded as:
0 = Interrupt flags are cleared by read of CSC register (default).
1 = Interrupt flags are cleared by explicit writeback of 1.
Card status change level/edge mode select. Bit 1 selects the signaling mode for the PCI1410A host interrupt
for card status changes. This bit is encoded as:
0 = Host interrupt is edge mode (default).
1 = Host interrupt is level mode.
Power-down mode select. When bit 0 is set to 1, the PCI1410A device is in power-down mode. In
power-down mode, the PCI1410A card outputs are high impedance until an active cycle is executed on the
card interface. Following an active cycle, the outputs are again high impedance. The PCI1410A device still
receives DMA requests, functional interrupts, and/or card status change interrupts; however, an actual card
access is required to wake up the interface. This bit is encoded as:
0
PWRDWN
R/W
0 = Power-down mode is disabled (default).
1 = Power-down mode is enabled.
5–22
5.21 ExCA I/O Windows 0 and 1 Offset-Address Low-Byte Registers
These registers contain the low byte of the 16-bit I/O window offset address for I/O windows 0 and 1. The 8 bits of
these registers correspond to the lower 8 bits of the offset address, and bit 0 always is 0.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA I/O windows 0 and 1 offset-address low-byte
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
Register:
Offset:
ExCA I/O window 0 offset-address low-byte
CardBus socket address + 836h; ExCA offset 36h
ExCA I/O window 1 offset-address low-byte
CardBus socket address + 838h; ExCA offset 38h
Read-only, Read/Write
Register:
Offset:
Type:
Default:
00h
5.22 ExCA I/O Windows 0 and 1 Offset-Address High-Byte Registers
These registers contain the high byte of the 16-bit I/O window offset address for I/O windows 0 and 1. The 8 bits of
these registers correspond to the upper 8 bits of the offset address.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA I/O windows 0 and 1 offset-address high-byte
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
ExCA I/O window 0 offset-address high-byte
CardBus socket address + 837h; ExCA offset 37h
ExCA I/O window 1 offset-address high-byte
CardBus socket address + 839h; ExCA offset 39h
Read/Write
Register:
Offset:
Type:
Default:
00h
5–23
5.23 ExCA Memory Windows 0–4 Page Register
The upper 8 bits of a 4-byte PCI memory address are compared to the contents of this register when decoding
addresses for 16-bit memory windows. Each window has its own page register, all of which default to 00h. By
programming this register to a nonzero value, host software can locate 16-bit memory windows in any 1 of 256
16-Mbyte regions in the 4-Gbyte PCI address space. These registers are accessible only when the ExCA registers
are memory-mapped; that is, these registers cannot be accessed using the index/data I/O scheme.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA memory windows 0–4 page
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
ExCA memory window 0 page
CardBus socket address + 840h
ExCA memory window 1 page
CardBus socket address + 841h
ExCA memory window 2 page
CardBus socket address + 842h
ExCA memory window 3 page
CardBus socket address + 843h
ExCA memory window 4 page
CardBus socket address + 844h
Read/Write
Register:
Offset:
Register:
Offset:
Register:
Offset:
Register:
Offset:
Type:
Default:
00h
5–24
6 CardBus Socket Registers
The PC Card Standard requires a CardBus socket controller to provide five 32-bit registers that report and control
socket-specific functions. The PCI1410A device provides the CardBus socket/ExCA base address register (PCI
offset 10h, see Section 4.12) to locate these CardBus socket registers in PCI memory address space (see
Figure 6–1). Table 6–1 gives the location of the socket registers in relation to the CardBus socket/ExCA base
address.
The PCI1410A device implements an additional register at offset 20h that provides power-management control for
the socket.
Host
Memory Space
PCI1410A Configuration Registers
Offset
00h
Offset
CardBus
Socket
Registers
10h
44h
CardBus Socket/ExCA Base Address
16-Bit Legacy-Mode Base Address
20h
800h
ExCA
Registers
844h
Figure 6–1. Accessing CardBus Socket Registers Through PCI Memory
Table 6–1. CardBus Socket Registers
REGISTER NAME
OFFSET
00h
Socket event
Socket mask
04h
Socket present state
Socket force event
Socket control
Reserved
08h
0Ch
10h
14h
Reserved
18h
Reserved
1Ch
20h
Socket power management
6–1
6.1 Socket Event Register
The socket event register indicates a change in socket status has occurred. These bits do not indicate what the
change is, only that one has occurred. Software must read the socket present state register (CardBus offset 08h, see
Section 6.3) for current status. Each bit in this register can be cleared by writing a 1 to that bit. The bits in this register
can be set to a 1 by software by writing a 1 to the corresponding bit in the socket force event register (CardBus offset
0Ch, see Section 6.4). All bits in this register are cleared by PCI reset. They can be set again immediately if, when
coming out of PC Card reset, the bridge finds the status unchanged (that is, CSTSCHG is reasserted or card detect
still is true). Software must clear this register before enabling interrupts. If it is not cleared when interrupts are enabled,
an interrupt is generated (but not masked) based on any bit that is set. See Table 6–2 for a complete description of
the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Socket event
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Socket event
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/C
0
R/C
0
R/C
0
R/C
0
Register:
Offset:
Type:
Socket event
CardBus socket address + 00h
Read-only, Read/Clear
0000 0000h
Default:
Table 6–2. Socket Event Register Description
FUNCTION
BIT
SIGNAL
TYPE
31–4
RSVD
R
Reserved. Bits 31–4 return 0s when read.
Power cycle. Bit 3 is set when the PCI1410A device detects that bit 3 (PWRCYCLE) in the socket present
state register (CardBus offset 08h, see Section 6.3) has changed state. This bit is cleared by writing a 1.
3
2
1
PWREVENT
CD2EVENT
CD1EVENT
R/C
R/C
R/C
CCD2. Bit 2 is set when the PCI1410A device detects that bit 2 (CDETECT2) in the socket present state
register (CardBus offset 08h, see Section 6.3) has changed state. This bit is cleared by writing a 1.
CCD1. Bit 3 is set when the PCI1410A device detects that bit 1 (CDETECT1) in the socket present state
register (CardBus offset 08h, see Section 6.3) has changed state. This bit is cleared by writing a 1.
CSTSCHG. Bit 0 is set when bit 0 (CARDSTS) in the socket present state register (CardBus offset 08h,
see Section 6.3) has changed state. For CardBus cards, bit 0 is set on the rising edge of CSTSCHG. For
16-bit PC Cards, bit 0 is set on both transitions of CSTSCHG. This bit is cleared by writing a 1.
0
CSTSEVENT
R/C
6–2
6.2 Socket Mask Register
The socket mask register allows software to control the CardBus card events that generate a status change interrupt.
The state of these mask bits does not prevent the corresponding bits from reacting in the socket event register
(CardBus offset 00h, see Section 6.1). See Table 6–3 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Socket mask
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Socket mask
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Socket mask
Read-only, Read/Write
Offset:
Default:
CardBus socket address + 04h
0000 0000h
Table 6–3. Socket Mask Register Description
FUNCTION
BIT
SIGNAL
TYPE
31–4
RSVD
R
Reserved. Bits 31–4 return 0s when read.
Power cycle. Bit 3 masks bit 3 (PWRCYCLE) in the socket present state register (CardBus offset 08h, see
Section 6.3) from causing a status change interrupt.
3
2–1
0
PWRMASK
CDMASK
R/W
R/W
R/W
0 = PWRCYCLE event does not cause CSC interrupt (default).
1 = PWRCYCLE event causes CSC interrupt.
Card detect mask. Bits 2 and 1 mask bits 1 and 2 (CDETECT1 and CDETECT2) in the socket present state
register (CardBus offset 08h, see Section 6.3) from causing a CSC interrupt.
00 = Insertion/removal does not cause CSC interrupt (default).
01 = Reserved (undefined)
10 = Reserved (undefined)
11 = Insertion/removal causes CSC interrupt.
CSTSCHG mask. Bit 0 masks bit 0 (CARDSTS) in the socket present state register (CardBus offset 08h,
see Section 6.3) from causing a CSC interrupt.
CSTSMASK
0 = CARDSTS event does not cause a CSC interrupt (default).
1 = CARDSTS event causes a CSC interrupt.
6–3
6.3 Socket Present State Register
The socket present state register reports information about the socket interface. Write transactions to the socket force
event register (CardBus offset 0Ch, see Section 6.4) are reflected here, as well as general socket-interface status.
Information about PC Card V
support and card type is updated only at each insertion. Also, note that the PCI1410A
CC
device uses CCD1 and CCD2 during card identification, and changes on these signals during this operation are not
reflected in this register. See Table 6–4 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Socket present state
R
0
R
0
R
1
R
1
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Socket present state
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
X
R
0
R
0
R
0
R
X
R
X
R
X
Register:
Offset:
Type:
Socket present state
CardBus socket address + 08h
Read-only
Default:
3000 00XXh
Table 6–4. Socket Present State Register Description
BIT
SIGNAL
TYPE
FUNCTION
YV socket. Bit 31 indicates whether or not the socket can supply V
device does not support Y.Y-V V ; therefore, this bit always is reset unless overridden by the socket force
CC
event register (CardBus offset 0Ch, see Section 6.4). This bit is hardwired to 0.
= Y.Y V to PC Cards. The PCI1410A
CC
31
YVSOCKET
R
XV socket. Bit 30 indicates whether or not the socket can supply V
device does not support X.X-V V ; therefore, this bit always is reset unless overridden by the socket force
CC
event register (CardBus offset 0Ch, see Section 6.4). This bit is hardwired to 0.
= X.X V to PC Cards. The PCI1410A
CC
30
29
28
XVSOCKET
3VSOCKET
5VSOCKET
R
R
R
3-V socket. Bit 29 indicates whether or not the socket can supply V
device does support 3.3-V V ; therefore, this bit always is set unless overridden by the socket force event
CC
register (CardBus offset 0Ch, see Section 6.4).
= 3.3 V to PC Cards. The PCI1410A
CC
5-V socket. Bit 28 indicates whether or not the socket can supply V
device does support 5-V V ; therefore, this bit always is set unless overridden by the socket force event
CC
register (CardBus offset 0Ch, see Section 6.4).
= 5 V to PC Cards. The PCI1410A
CC
27–14
13
RSVD
R
R
R
R
R
Reserved. Bits 27–14 return 0s when read.
YVCARD
XVCARD
3VCARD
5VCARD
YV card. Bit 13 indicates whether or not the PC Card inserted in the socket supports V
XV card. Bit 12 indicates whether or not the PC Card inserted in the socket supports V
= Y.Y V.
= X.X V.
= 3.3 V.
= 5 V.
CC
12
CC
11
3-V card. Bit 11 indicates whether or not the PC Card inserted in the socket supports V
CC
10
5-V card. Bit 10 indicates whether or not the PC Card inserted in the socket supports V
CC
Bad V
invalid voltage.
request. Bit 9 indicates that the host software has requested that the socket be powered at an
CC
9
8
7
BADVCCREQ
DATALOST
R
R
R
0 = Normal operation (default)
1 = Invalid V
CC
request by host software
Data lost. Bit 8 indicates that a PC Card removal event may have caused lost data because the cycle did
not terminate properly or because write data still resides in the PCI1410A device.
0 = Normal operation (default)
1 = Potential data loss due to card removal
Not a card. Bit 7 indicates that an unrecognizable PC Card is inserted in the socket. This bit is not updated
until a valid PC Card is inserted into the socket.
NOTACARD
0 = Normal operation (default)
1 = Unrecognizable PC Card detected
6–4
Table 6–4. Socket Present State Register Description (Continued)
BIT
SIGNAL
TYPE
FUNCTION
READY(IREQ)//CINT. Bit 6 indicates the current status of READY(IREQ)//CINT at the PC Card interface.
0 = READY(IREQ)//CINT low
6
IREQCINT
R
1 = READY(IREQ)//CINT high
CardBus card detected. Bit 5 indicates that a CardBus PC Card is inserted in the socket. This bit is not
updated until another card interrogation sequence occurs (card insertion).
5
4
CBCARD
R
R
16-bit card detected. Bit 4 indicates that a 16-bit PC Card is inserted in the socket. This bit is not updated
until another card interrogation sequence occurs (card insertion).
16BITCARD
Power cycle. Bit 3 indicates the status of each card powering request. This bit is encoded as:
0 = Socket powered down (default)
3
2
PWRCYCLE
CDETECT2
R
R
1 = Socket powered up
CCD2. Bit 2 reflects the current status of CCD2 at the PC Card interface. Changes to this signal during
card interrogation are not reflected here.
0 = CCD2 low (PC Card may be present)
1 = CCD2 high (PC Card not present)
CCD1. Bit 1 reflects the current status of CCD1 at the PC Card interface. Changes to this signal during
card interrogation are not reflected here.
1
0
CDETECT1
CARDSTS
R
R
0 = CCD1 low (PC Card may be present)
1 = CCD1 high (PC Card not present)
CSTSCHG. Bit 0 reflects the current status of CSTSCHG at the PC Card interface.
0 = CSTSCHG low
1 = CSTSCHG high
6–5
6.4 Socket Force Event Register
The socket force event register is used to force changes to the socket event register (CardBus offset 00h, see
Section 6.1) and the socket present state register (CardBus offset 08h, see Section 6.3). Bit 14 (CVSTEST) in this
register must be written when forcing changes that require card interrogation. See Table 6–5 for a complete
description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Socket force event
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Socket force event
R
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
R
0
W
0
W
0
W
0
W
0
W
0
W
0
Register:
Type:
Socket force event
Read-only, Write-only
Offset:
Default:
CardBus socket address + 0Ch
0000 0000h
Table 6–5. Socket Force Event Register Description
FUNCTION
BIT
SIGNAL
TYPE
31–15
RSVD
R
Reserved. Bits 31–15 return 0s when read.
Card VS test. When bit 14 is set, the PCI1410A device reinterrogates the PC Card, updates the socket
present state register (CardBus offset 08h, see Section 6.3), and enables the socket control register
(CardBus offset 10h, see Section 6.5).
14
13
12
11
10
CVSTEST
FYVCARD
FXVCARD
F3VCARD
F5VCARD
W
W
W
W
W
Force YV card. Write transactions to bit 13 cause bit 13 (YVCARD) in the socket present state register to
be written (CardBus offset 08h, see Section 6.3). When set, this bit disables the socket control register
(CardBus offset 10h, see Section 6.5).
Force XV card. Write transactions to bit 12 cause bit 12 (XVCARD) in the socket present state register to
be written (CardBus offset 08h, see Section 6.3). When set, this bit disables the socket control register
(CardBus offset 10h, see Section 6.5).
Force 3-V card. Write transactions to bit 11 cause bit 11 (3VCARD) in the socket present state register to
be written (CardBus offset 08h, see Section 6.3). When set, this bit disables the socket control register
(CardBus offset 10h, see Section 6.5).
Force 5-V card. Write transactions to bit 10 cause bit 10 (5VCARD) in the socket present state register to
be written (CardBus offset 08h, see Section 6.3). When set, this bit disables the socket control register
(CardBus offset 10h, see Section 6.5).
Force bad V
CC
request. Changes to bit 9 (BADVCCREQ) in the socket present state register (CardBus offset
08h, see Section 6.3) can be made by writing to bit 9.
9
8
FBADVCCREQ
FDATALOST
W
W
Force data lost. Write transactions to bit 8 cause bit 8 (DATALOST) in the socket present state register to
be written (CardBus offset 08h, see Section 6.3).
Force not a card. Write transactions to bit 7 cause bit 7 (NOTACARD) in the socket present state register
to be written (CardBus offset 08h, see Section 6.3).
7
6
5
FNOTACARD
RSVD
W
R
Reserved. Bit 6 returns 0 when read.
Force CardBus card. Write transactions to bit 5 cause bit 5 (CBCARD) in the socket present state register
to be written (CardBus offset 08h, see Section 6.3).
FCBCARD
W
Force 16-bit card. Write transactions to bit 4 cause bit 4 (16BITCARD) in the socket present state register
to be written (CardBus offset 08h, see Section 6.3).
4
F16BITCARD
W
6–6
Table 6–5. Socket Force Event Register Description (Continued)
BIT
SIGNAL
TYPE
FUNCTION
Force power cycle. Write transactions to bit 3 cause bit 3 (PWREVENT) in the socket event register to be
written (CardBus offset 00h, see Section 6.1), and bit 3 (PWRCYCLE) in the socket present state register
is unaffected (CardBus offset 08h, see Section 6.3).
3
FPWRCYCLE
W
Force CCD2. Write transactions to bit 2 cause bit 2 (CD2EVENT) in the socket event register to be written
(CardBus offset 00h, see Section 6.1), and bit 2 (CDETECT2) in the socket present state register is
unaffected (CardBus offset 08h, see Section 6.3).
2
1
0
FCDETECT2
FCDETECT1
FCARDSTS
W
W
W
Force CCD1. Write transactions to bit 1 cause bit 1 (CD1EVENT) in the socket event register to be written
(CardBus offset 00h, see Section 6.1), and bit 1 (CDETECT1) in the socket present state register is
unaffected (CardBus offset 08h, see Section 6.3).
Force CSTSCHG. Write transactions to bit 0 cause bit 0 (CSTSEVENT) in the socket event register to be
written (CardBus offset 00h, see Section 6.1), and bit 0 (CARDSTS) in the socket present state register is
unaffected (CardBus offset 08h, see Section 6.3).
6.5 Socket Control Register
The socket control register provides control of the voltages applied to the socket and instructions for CB CLKRUN
protocol. The PCI1410A device ensures that the socket is powered up only at acceptable voltages when a CardBus
card is inserted. See Table 6–6 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Socket control
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Socket control
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
Type:
Socket control
CardBus socket address + 10h
Read-only, Read/Write
0000 0000h
Default:
Table 6–6. Socket Control Register Description
FUNCTION
BIT
SIGNAL
TYPE
31–8
RSVD
R
Reserved. Bits 31–8 return 0s when read.
CB CLKRUN protocol instructions.
0 = CB CLKRUN protocol can only attempt to stop/slow the CB clock if the socket is idle and the
PCI CLKRUN protocol is preparing to stop/slow the PCI bus clock.
7
STOPCLK
R/W
1 = CB CLKRUN protocol can attempt to stop/slow the CB clock if the socket is idle.
V
CC
control. Bits 6–4 request card V
000 = Request power off (default)
001 = Reserved
changes.
CC
100 = Request V
101 = Request V
110 = Reserved
111 = Reserved
= X.X V
= Y.Y V
CC
CC
6–4
3
VCCCTRL
RSVD
R/W
R
010 = Request V
011 = Request V
= 5 V
= 3.3 V
CC
CC
Reserved. Bit 3 returns 0 when read.
control. Bits 2–0 request card V
V
changes.
PP
000 = Request power off (default)
PP
100 = Request V
101 = Request V
110 = Reserved
111 = Reserved
= X.X V
= Y.Y V
PP
PP
001 = Request V
010 = Request V
= 12 V
= 5 V
2–0
VPPCTRL
R/W
PP
PP
PP
011 = Request V
= 3.3 V
6–7
6.6 Socket Power Management Register
This register provides power-management control over the socket through a mechanism for slowing or stopping the
clock on the card interface when the card is idle. See Table 6–7 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Socket power management
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R/W
0
15
14
13
12
11
10
0
Name
Type
Default
Socket power management
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
Register:
Offset:
Type:
Socket power management
CardBus socket address + 20h
Read-only, Read/Write
0000 0000h
Default:
Table 6–7. Socket Power Management Register Description
BIT
SIGNAL
TYPE
FUNCTION
31–26
RSVD
R
R
Reserved. Bits 31–26 return 0s when read.
Socket access status. This bit indicates when a socket access has occurred. This bit is cleared by a read
access.
25
SKTACCES
0 = A PC card access has not occurred (default).
1 = A PC card access has occurred.
Socket mode status. This bit provides clock mode information.
0 = Clock is operating normally.
24
23–17
16
SKTMODE
RSVD
R
R
1 = Clock frequency has changed.
Reserved. Bits 23–17 return 0s when read.
CardBus clock control enable. When bit 16 is set, bit 0 (CLKCTRL) is enabled.
0 = Clock control is disabled (default).
CLKCTRLEN
RSVD
R/W
R
1 = Clock control is enabled.
15–1
Reserved. Bits 15–1 return 0s when read.
CardBus clock control. This bit determines whether the CB CLKRUN protocol stops or slows the CB clock
during idle states. Bit 16 (CLKCTRLEN) enables this bit.
0
CLKCTRL
R/W
0 = Allows CB CLKRUN protocol to stop the CB clock (default).
1 = Allows CB CLKRUN protocol to slow the CB clock by a factor of 16.
6–8
7 Distributed DMA (DDMA) Registers
The DMA base address, programmable in PCI configuration space as bits 15–4 (DMABASE field) of the socket DMA
register 1 (PCI offset 98h, see Section 4.36), points to a 16-byte region in PCI I/O space where the DMA registers
reside. The names and locations of these registers are summarized in Table 7–1. These PCI1410A register
definitions are identical in function to, but different in location from, those of the Intel 8237 DMA controller. The
similarity between the register models retains some level of compatibility with legacy DMA and simplifies the
translation required by the master DMA device when it forwards legacy DMA writes to DMA channels.
While the DMA register definitions are identical to those of the same name in the 8237 DMA controller, some register
bits defined in the 8237 DMA controller do not apply to distributed DMA in a PCI environment. In such cases, the
PCI1410A device implements these obsolete register bits as nonfunctional, read-only bits. The reserved registers
shown in Table 7–1 are implemented as read-only and return 0s when read. Write transactions to reserved registers
have no effect.
Table 7–1. Distributed DMA Registers
DMA BASE
REGISTER NAME
ADDRESS OFFSET
Current address
Reserved
Reserved
Page
00h
04h
08h
0Ch
Base address
Current count
Base count
Reserved
Reserved
Reserved
N/A
Mode
N/A
Status
Request
N/A
Command
Multichannel
Mask
Reserved
Master clear
7.1 DMA Current Address/Base Address Register
The DMA current address/base address register sets the starting (base) memory address of a DMA transfer. Read
transactions from this register indicate the current memory address of a direct memory transfer.
For the 8-bit DMA transfer mode, the current address register contents are presented on AD15–AD0 of the PCI bus
during the address phase. Bits 7–0 of the DMA page register (see Section 7.2) are presented on AD23–AD16 of the
PCI bus during the address phase.
For the 16-bit DMA transfer mode, the current address register contents are presented on AD16–AD1 of the PCI bus
during the address phase, and AD0 is driven to logic 0. Bits 7–1 of the DMA page register (see Section 7.2) are
presented on AD23–AD17 of the PCI bus during the address phase, and bit 0 is ignored.
Bit
15
14
13
12
11
10
9
8
Name
Type
Default
Bit
DMA current address/base address
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
2
1
0
Name
Type
Default
DMA current address/base address
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
Type:
DMA current address/base address
DMA base address + 00h
Read/Write
Default:
0000h
7–1
7.2 DMA Page Register
The DMA page register sets the upper byte of the address of a DMA transfer. Details of the address represented by
this register are explained in Section 7.1, DMA Current Address/Base Address Register.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
DMA page
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
Type:
DMA page
DMA base address + 02h
Read/Write
00h
Default:
7.3 DMA Current Count/Base Count Register
The DMA current count/base count register sets the total transfer count, in bytes, of a direct memory transfer. Read
transactions to this register indicate the current count of a direct memory transfer. In the 8-bit transfer mode, the count
is decremented by 1 after each transfer, and the count is decremented by 2 after each transfer in the 16-bit transfer
mode.
Bit
15
14
13
12
11
10
9
8
Name
Type
Default
Bit
DMA current count/base count
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
2
1
0
Name
Type
Default
DMA current count/base count
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
Type:
DMA current count/base count
DMA base address + 04h
Read/Write
Default:
0000h
7–2
7.4 DMA Command Register
The DMA command register enables and disables the DMA controller. Bit 2 (DMAEN) defaults to 0, enabling the DMA
controller. All other bits are reserved. See Table 7–2 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
DMA command
R
0
R
0
R
0
R
0
R
0
R/W
0
R
0
R
0
Register:
Offset:
Type:
DMA command
DMA base address + 08h
Read-only, Read/Write
00h
Default:
Table 7–2. DMA Command Register Description
FUNCTION
BIT
SIGNAL
TYPE
7–3
RSVD
R
Reserved. Bits 7–3 return 0s when read.
DMA controller enable. Bit 2 enables and disables the distributed DMA slave controller in the PCI1410A
device and defaults to the enabled state.
2
DMAEN
RSVD
R/W
R
0 = DMA controller is enabled (default).
1 = DMA controller is disabled.
1–0
Reserved. Bits 1 and 0 return 0s when read.
7.5 DMA Status Register
The DMA status register indicates the terminal count and DMA request (DREQ) status. See Table 7–3 for a complete
description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
DMA status
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Offset:
Type:
DMA status
DMA base address + 08h
Read-only
00h
Default:
Table 7–3. DMA Status Register Description
BIT
SIGNAL
TYPE
FUNCTION
Channel request. In the 8237 DMA controller, bits 7–4 indicate the status of DREQ of each DMA channel.
In the PCI1410A device, these bits indicate the DREQ status of the single socket being serviced by this
register. All four bits are set to 1 when the PC Card asserts DREQ and are cleared to 0 when DREQ is
deasserted. The status of bit 0 (MASKBIT) in the DMA multichannel/mask register (see Section 7.9) has
no effect on these bits.
7–4
DREQSTAT
R
Channel terminal count. The 8237 DMA controller uses bits 3–0 to indicate the TC status of each of its four
DMA channels. In the PCI1410A device, these bits report information about a single DMA channel;
therefore, all four of these register bits indicate the TC status of the single socket being serviced by this
register. All four bits are set to 1 when the TC is reached by the DMA channel. These bits are cleared to 0
when read or the DMA channel is reset.
3–0
TC
R
7–3
7.6 DMA Request Register
The DMA request register requests a DMA transfer through software. Any write to this register enables software
requests, and this register is to be used in block mode only.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
DMA request
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
Register:
Offset:
Type:
DMA request
DMA base address + 09h
Write-only
00h
Default:
7.7 DMA Mode Register
The DMA mode register sets the DMA transfer mode. See Table 7–4 for a complete description of the register
contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
DMA mode
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
Register:
Offset:
Type:
DMA mode
DMA base address + 0Bh
Read-only, Read/Write
00h
Default:
Table 7–4. DMA Mode Register Description
BIT
SIGNAL
TYPE
FUNCTION
Mode select. The PCI1410A device uses bits 7 and 6 to determine the transfer mode.
00 = Demand mode is selected (default).
01 = Single mode is selected.
7–6
DMAMODE
R/W
10 = Block mode is selected.
11 = Reserved
Address increment/decrement. The PCI1410A device uses bit 5 to select the memory address in the DMA
current address/base address register to increment or decrement after each data transfer. This is in
accordance with the 8237 DMA controller use of this register bit and is encoded as follows:
0 = Addresses increment (default).
5
4
INCDEC
R/W
R/W
1 = Addresses decrement.
Auto initialization
AUTOINIT
0 = Auto initialization is disabled (default).
1 = Auto initialization is enabled.
Transfer type. Bits 3 and 2 select the type of direct memory transfer to be performed. A memory write transfer
moves data from the PCI1410A PC Card interface to memory and a memory read transfer moves data from
memory to the PCI1410A PC Card interface. The field is encoded as:
00 = No transfer selected (default)
01 = Write transfer
3–2
1–0
XFERTYPE
RSVD
R/W
R
10 = Read transfer
11 = Reserved
Reserved. Bits 1 and 0 return 0s when read.
7–4
7.8 DMA Master Clear Register
The DMA master clear register resets the DMA controller and all DMA registers.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
DMA master clear
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
Register:
Offset:
Type:
DMA master clear
DMA base address + 0Dh
Write-only
Default:
00h
7.9 DMA Multichannel/Mask Register
The PCI1410A device uses only the least significant bit of this register to mask the PC Card DMA channel. The
PCI1410A device sets the mask bit to 1 when the PC Card is removed. Host software is responsible for either resetting
the socket’s DMA controller or enabling the mask bit. See Table 7–5 for a complete description of the register
contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
DMA multichannel/mask
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
Register:
Offset:
Type:
DMA multichannel/mask
DMA base address + 0Fh
Read-only, Read/Write
00h
Default:
Table 7–5. DMA Multichannel/Mask Register Description
FUNCTION
BIT
SIGNAL
TYPE
7–1
RSVD
R
Reserved. Bits 7–1 return 0s when read.
Mask select. Bit 0 masks incoming DREQ signals from the PC Card. When set to 1, the socket ignores DMA
requests from the card. When cleared (or reset to 0), incoming DREQ assertions are serviced normally.
0 = DMA service is provided on card DREQ.
0
MASKBIT
R/W
1 = Socket DREQ signal is ignored (default).
7–5
7–6
8 Electrical Characteristics
†
8.1 Absolute Maximum Ratings Over Operating Temperature Ranges
Supply voltage range, V
Clamping voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
V
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V
CCP, CCCB, CCI
Input voltage range, V : PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
+ 0.5 V
+ 0.5 V
+ 0.5 V
+ 0.5 V
+ 0.5 V
+ 0.5 V
+ 0.5 V
I
CCP
Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 to V
CCCB
Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 to V
CCI
Fail safe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
CC
CC
CC
CC
CC
Output voltage range, V : PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 to V
Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 to V
Fail safe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
OK
O O CC
Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
J
Virtual junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
†
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Applies for external input and bidirectional buffers. V > V
does not apply to fail-safe terminals. PCI terminals are measured with
I
CC
respect to V
respect to V
instead of V . PC Card terminals are measured with respect to V
. The limit specified applies for a dc condition.
. Miscellaneous signals are measured with
CCCB
CCP
CCI
CC
2. Applies for external output and bidirectional buffers. V > V
does not apply to fail-safe terminals. PCI terminals are measured
O
CC
with respect to V
with respect to V
instead of V . PC Card terminals are measured with respect to V
. The limit specified applies for a dc condition.
. Miscellaneous signals are measured
CCCB
CCP
CC
CCI
8–1
8.2 Recommended Operating Conditions (see Note 3)
OPERATION
MIN
NOM
3.3
3.3
5
MAX
3.6
UNIT
V
V
Commercial
Commercial
3.3 V
3.3 V
5 V
3
V
Core voltage
CC
3
4.75
3
3.6
V
V
V
PCI I/O clamp voltage
CCP
5.25
3.6
3.3 V
5 V
3.3
5
V
Commercial
Commercial
PCI
PC Card I/O clamp voltage
CCCB
CCI
4.75
3
5.25
3.6
3.3 V
5 V
3.3
5
V
Miscellaneous I/O clamp voltage
4.75
5.25
3.3 V
5 V
0.5 V
CCP
V
CCP
2
V
CCP
3.3 V
5 V
0.475 V
V
CCCB
CCCB
CCCB
PC Card
†
2.4
V
High-level input voltage
V
V
IH
‡
Miscellaneous
2
2
V
CCI
§
Fail safe
V
CC
||
CD terminals
2.4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
V
CC
3.3 V
5 V
0.3 V
CCP
PCI
0.8
0.325 V
3.3 V
5 V
CCCB
PC Card
†
0.8
0.8
Low-level input voltage
V
V
V
IL
‡
Miscellaneous
§
Fail safe
0.8
||
CD terminals
PCI
0.75
V
CCP
PC Card
V
CCCB
V
V
Input voltage
I
‡
‡
Miscellaneous
V
CCI
§
Fail safe
V
CC
CC
CC
CC
PCI
V
PC Card
V
V
V
¶
Output voltage
V
O
Miscellaneous
§
Fail safe
CC
4
PCI and PC Card
‡
t
t
Input transition time (t and t )
ns
Miscellaneous
and fail safe
r
f
0
6
§
T
Operating ambient temperature range
Virtual junction temperature
0
0
25
25
70
°C
°C
A
#
T
J
115
†
‡
Applies to external inputs and bidirectional buffers without hysteresis
Miscellaneous terminals are 70, 62, 59, 60, 61, 64, 65, 67, 68, 69, 73, 74, 71, and 72 for the PGE packaged device; L11, M9, L8, K8, N9, K9,
N10, L10, N11, M11, N13, M13, N12, and M12 for the GGU packaged device; and W12, U10, P9, W10, V10, P10, W11, U11, P11, R11, M18,
M19, V12, and U12 for the GHK packaged device (SUSPEND, SPKROUT, RI_OUT, multifunction terminals MFUNC0–MFUNC6, and
power-switch control terminals).
Fail-safe terminals are 75, 117, 131, and 137 for the PGE packaged device; L12, D9, C6, and A4 for the GGU packaged device; and L19, E13,
F11, and A9 for the GHK packaged device (card detect and voltage sense terminals).
§
¶
#
||
Applies to external output buffers
These junction temperatures reflect simulation conditions. The customer is responsible for verifying junction temperature.
CD terminals are 75 and 137 for the PGE packaged device; L12 and A4 for the GGU packaged device; and L19 and A9 for the GHK packaged
device.
NOTE 3: Unused terminals (input or I/O) must be held high or low to prevent them from floating.
8–2
8.3 Electrical Characteristics Over Recommended Operating Conditions (unless
otherwise noted)
PARAMETER
TERMINALS OPERATION TEST CONDITIONS
MIN
MAX
UNIT
I
I
I
I
I
I
I
I
I
I
I
I
= –0.5 mA
= –2 mA
= –0.15 mA
= –0.15 mA
= –12 mA
= –4 mA
= 1.5 mA
= 6 mA
0.9V
3.3 V
5 V
OH
OH
OH
OH
OH
OH
OL
OL
OL
OL
OL
OL
CC
2.4
PCI and
Misc1§
0.9V
3.3 V
5 V
CC
2.4
V
OH
PC Card
V
High-level output voltage (see Note 4)
2.1
2.1
Misc2¶
Misc3#
0.1V
3.3 V
5 V
CC
PCI and
Misc1§
0.55
= 0.7 mA
= 0.7 mA
= 12 mA
= 4 mA
0.1V
CC
3.3 V
5 V
Low-level output voltage
PC Card
V
OL
V
0.55
0.5
0.5
–1
–1
10
Misc2¶
Misc3#
3.6 V
5.25 V
3.6 V
V = V
I
Output
terminals
CC
CC
CC
3-state output, high-impedance state
output current
I
I
I
µA
µA
µA
OZL
OZH
IL
V = V
I
†
†
V = V
I
Output
terminals
3-state output, high-impedance state
output current
5.25 V
25
–1
V = V
I
CC
Input terminals
I/O terminals
V = GND
I
Low-level input current
High-level input current
V = GND
I
–10
10
‡
3.6 V
V = V
I
CC
Input
terminals
‡
‡
‡
5.25 V
3.6 V
20
10
25
V = V
I
CC
CC
CC
V = V
I
I/O terminals
5.25 V
V = V
I
I
IH
µA
Fail-safe
terminals
3.6 V
3.6 V
V = V
10
I
CC
V
CCD
terminals
V = V
300
I
CC
||
†
‡
§
For PCI terminals, V = V
For I/O terminals, input leakage (I and I ) includes I
. For PC Card terminals, V = V
. For miscellaneous terminals, V = V
I
CCP
I
CCCB CCI
I
leakage of the disabled output.
IL IH
OZ
Misc1 includes MFUNC6(69), MFUNC5(68), MFUNC4(67), MFUNC3(65), and MFUNC2(64)for the PGE packaged device; M11, N11, L10, N10,
and K9 for the GGU packaged device; and R11, P11, U11, W11, and P10 for the GHK packaged device.
Misc2 includes MFUNC1(61), MFUNC0(60), and SERR(35) for the PGE packaged device; N9, K8, and M1 for the GGU packaged device; and
V10, W10, and R3 for the GHK packaged device.
Misc3 includes SPKROUT(62) and RI_OUT(59) for the PGE packaged device; M9 and L8 for the GGU packaged device; and U10 and P9 for
the GHK packaged device.
¶
#
||
V
terminals include VCCD0(73) and VCCD1(74) for the PGE packaged device; N13 and M13 for the GGU packaged device; and M18 and
CCD
M19 for the GHK packaged device.
NOTE 4: PCI shared signals are AD31–AD0, C/BE3–C/BE0, FRAME, TRDY, IRDY, STOP, IDSEL, DEVSEL, and PAR.
8–3
8.4 PCI Clock/Reset Timing Requirements Over Recommended Ranges of Supply
Voltage and Operating Free-Air Temperature
ALTERNATE
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
t
t
t
Cycle time, PCLK
t
30
11
11
1
ns
ns
c
cyc
Pulse duration (width), PCLK high
Pulse duration (width), PCLK low
Slew rate, PCLK
t
high
wH
wL
t
ns
low
t , t
∆v/∆t
4
V/ns
ms
ms
r f
t
t
Pulse duration (width), RSTIN
Setup time, PCLK active at end of RSTIN
t
1
w
rst
t
100
su
rst-clk
8.5 PCI Timing Requirements Over Recommended Ranges of Supply Voltage and
Operating Free-Air Temperature
This data sheet uses the following conventions to describe time (t) intervals. The format is t , where subscript A
A
indicates the type of dynamic parameter being represented. The following are used: t = propagation delay time,
pd
t = delay time, t = setup time, and t = hold time.
d
su
h
ALTERNATE
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
2
MAX
UNIT
PCLK-to-shared signal
valid delay time
t
11
val
inv
C
= 50 pF,
L
t
pd
Propagation delay time (see Note 4)
ns
See Note 4
PCLK-to-shared signal
invalid delay time
t
2
Enable time, high
Delay time, t
Delay time, t
impedance-to-active
delay time from PCLK
t
2
ns
ns
en
on
t
d
Disable time,
active-to-high
impedance delay time
from PCLK
t
28
dis
off
t
t
Setup time before PCLK valid
Hold time after PCLK high
t
7
0
ns
ns
su
su
t
h
h
NOTE 4: PCI shared signals are AD31–AD0, C/BE3–C/BE0, FRAME, TRDY, IRDY, STOP, IDSEL, DEVSEL, and PAR.
8.6 PC Card Cycle Timing
The PC Card cycle timing is controlled by the wait-state bits in the Intel 82365SL-DF compatible memory and I/O
window registers. The PC Card cycle generator uses the PCI clock to generate the correct card address setup and
hold times and the PC Card command active (low) interval. This allows the cycle generator to output PC Card cycles
that are as close to the Intel 82365SL-DF timing as possible, while always slightly exceeding the Intel 82365SL-DF
values. This ensures compatibility with existing software and maximizes throughput.
The PC Card address setup and hold times are a function of the wait-state bits. Table 8–1 shows address setup time
in PCLK cycles and nanoseconds for I/O and memory cycles. Table 8–2 and Table 8–3 show command active time
in PCLK cycles and nanoseconds for I/O and memory cycles. Table 8–4 shows address hold time in PCLK cycles
and nanoseconds for I/O and memory cycles.
Table 8–1. PC Card Address Setup Time, t
, 8-Bit and 16-Bit PCI Cycles
su(A)
TS1 – 0 = 01
(PCLK/ns)
WAIT-STATE BITS
I/O
3/90
Memory
Memory
WS1
WS1
0
1
2/60
4/120
8–4
Table 8–2. PC Card Command Active Cycle Time, t
, 8-Bit PCI Cycles
c(A)
WAIT-STATE BITS
TS1 – 0 = 01
(PCLK/ns)
WS
0
ZWS
0
X
1
19/570
23/690
7/210
1
I/O
0
00
01
10
11
00
0
19/570
23/690
23/690
23/690
7/210
X
X
X
1
Memory
Table 8–3. PC Card Command Active Cycle Time, t
, 16-Bit PCI Cycles
c(A)
WAIT-STATE BITS
TS1 – 0 = 01
(PCLK/ns)
WS
0
ZWS
0
X
1
7/210
11/330
N/A
1
I/O
0
00
01
10
11
00
0
9/270
13/390
17/510
23/630
5/150
X
X
X
1
Memory
Table 8–4. PC Card Address Hold Time, t
, 8-Bit and 16-Bit PCI Cycles
h(A)
TS1 – 0 = 01
(PCLK/ns)
WAIT-STATE BITS
I/O
2/60
2/60
3/90
Memory
Memory
WS1
WS1
0
1
8–5
8–6
9 Mechanical Information
The PCI1410A device is packaged in either a 144-ball GGU MicroStar BGA or a 144-pin PGE package. It also is
packaged in a 209-ball GHK MicroStar BGA that is pin compatible with the TI PCI4410A device. The PCI4410A
device is a single-socket CardBus bridge with an integrated OHCI link. The following shows the mechanical
dimensions for the GGU, GHK, and PDV packages.
GGU (S-PBGA-N144)
PLASTIC BALL GRID ARRAY
9,60 TYP
12,10
11,90
SQ
0,80
N
M
L
K
J
H
G
F
E
D
C
B
A
0,80
1
2 3 4 5 6 7 8 9 10 11 12 13
0,95
0,85
1,40 MAX
Seating Plane
0,10
0,55
0,12
0,45
0,08
M
0,08
0,45
0,35
4073221/B 11/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. MicroStar BGA configuration
9–1
GHK (S-PBGA-N209)
PLASTIC BALL GRID ARRAY
16,10
15,90
SQ
14,40 TYP
0,80
W
V
U
T
R
P
N
M
L
K
J
H
G
F
0,80
E
D
C
B
A
1
3
5
7
9
11 13 15 17 19
10 12 14 16 18
2
4
6
8
0,95
0,85
1,40 MAX
Seating Plane
0,10
0,55
0,45
0,12
0,08
M
0,08
0,45
0,35
4145273–2/B 12/98
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. MicroStar BGA configuration.
9–2
PGE (S-PQFP-G144)
PLASTIC QUAD FLATPACK
108
73
109
72
0,27
M
0,08
0,17
0,50
0,13 NOM
144
37
1
36
Gage Plane
17,50 TYP
20,20
SQ
19,80
0,25
0,05 MIN
22,20
SQ
0°–ā7°
21,80
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040147/C 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
9–3
9–4
相关型号：
©2020 ICPDF网 联系我们和版权申明