PCI2050BIGHK [TI]
PCI-TO-PCI BRIDGE; PCI至PCI桥接器
| 型号： | PCI2050BIGHK |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | PCI-TO-PCI BRIDGE |
| 文件： | 总87页 (文件大小：406K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ꢀ ꢁ ꢂꢇ ꢈ ꢉꢇ ꢀ ꢁ ꢂ ꢆꢊ ꢋ ꢌꢍꢎ
Data Manual
October 2005
Connectivity Solutions
SCPS076F
IMPORTANT NOTICE
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Contents
Section
Title
Page
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−1
1.1
1.2
1.3
1.4
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−1
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−2
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−2
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−2
2
3
Terminal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−1
Feature/Protocol Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−1
3.1
Introduction to the PCI2050B Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−1
3.1.1
3.1.2
Write Combining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−2
66-MHz Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−2
3.2
3.3
3.4
3.5
3.6
PCI Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−2
Configuration Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−3
Special Cycle Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−5
Secondary Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−5
Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−6
3.6.1
3.6.2
3.6.3
Primary Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−6
Internal Secondary Bus Arbitration . . . . . . . . . . . . . . . . . . . . 3−6
External Secondary Bus Arbitration . . . . . . . . . . . . . . . . . . . 3−7
3.7
3.8
Decode Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−7
System Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−7
3.8.1
3.8.2
3.8.3
3.8.4
3.8.5
3.8.6
3.8.7
Posted Write Parity Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−7
Posted Write Time-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−7
Target Abort on Posted Writes . . . . . . . . . . . . . . . . . . . . . . . . 3−7
Master Abort on Posted Writes . . . . . . . . . . . . . . . . . . . . . . . 3−8
Master Delayed Write Time-Out . . . . . . . . . . . . . . . . . . . . . . 3−8
Master Delayed Read Time-Out . . . . . . . . . . . . . . . . . . . . . . 3−8
Secondary SERR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−8
3.9
Parity Handling and Parity Error Reporting . . . . . . . . . . . . . . . . . . . . . . 3−8
3.9.1
3.9.2
Address Parity Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−8
Data Parity Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−8
3.10 Master and Target Abort Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−8
3.11 Discard Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−9
3.12 Delayed Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−9
3.13 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−9
3.14 CompactPCI Hot-Swap Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−10
3.15 JTAG Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−11
3.15.1
Test Port Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−11
iii
Section
Title
Page
3.16 GPIO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−15
3.16.1
3.16.2
Secondary Clock Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−15
Transaction Forwarding Control . . . . . . . . . . . . . . . . . . . . . . . 3−15
3.17 PCI Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−16
3.17.1 Behavior in Low-Power States . . . . . . . . . . . . . . . . . . . . . . . . 3−16
Bridge Configuration Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−1
4
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−2
Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−2
Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−3
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−4
Revision ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−5
Class Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−5
Cache Line Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−5
Primary Latency Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−6
Header Type Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−6
4.10 BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−6
4.11 Base Address Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−7
4.12 Base Address Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−7
4.13 Primary Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−7
4.14 Secondary Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−8
4.15 Subordinate Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−8
4.16 Secondary Bus Latency Timer Register . . . . . . . . . . . . . . . . . . . . . . . . 4−8
4.17 I/O Base Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−9
4.18 I/O Limit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−9
4.19 Secondary Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−10
4.20 Memory Base Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−11
4.21 Memory Limit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−11
4.22 Prefetchable Memory Base Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−11
4.23 Prefetchable Memory Limit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−12
4.24 Prefetchable Base Upper 32 Bits Register . . . . . . . . . . . . . . . . . . . . . . 4−12
4.25 Prefetchable Limit Upper 32 Bits Register . . . . . . . . . . . . . . . . . . . . . . 4−13
4.26 I/O Base Upper 16 Bits Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−13
4.27 I/O Limit Upper 16 Bits Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−13
4.28 Capability Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−14
4.29 Expansion ROM Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . 4−14
4.30 Interrupt Line Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−14
4.31 Interrupt Pin Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−15
4.32 Bridge Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−15
Extension Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−1
5
5.1
5.2
5.3
Chip Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−1
Extended Diagnostic Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−2
Arbiter Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−3
iv
Section
Title
Page
5.4
5.5
5.6
5.7
5.8
5.9
P_SERR Event Disable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−4
GPIO Output Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−5
GPIO Output Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−5
GPIO Input Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−6
Secondary Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−7
P_SERR Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−8
5.10 Power-Management Capability ID Register . . . . . . . . . . . . . . . . . . . . . 5−8
5.11 Power-Management Next-Item Pointer Register . . . . . . . . . . . . . . . . . 5−9
5.12 Power-Management Capabilities Register . . . . . . . . . . . . . . . . . . . . . . 5−9
5.13 Power-Management Control/Status Register . . . . . . . . . . . . . . . . . . . . 5−10
5.14 PMCSR Bridge Support Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−11
5.15 Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−11
5.16 HS Capability ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−12
5.17 HS Next-Item Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−12
5.18 Hot-Swap Control Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−13
5.19 Diagnostics Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−14
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−1
6
6.1
6.2
6.3
Absolute Maximum Ratings Over Operating Temperature Ranges . 6−1
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 6−2
Electrical Characteristics Over Recommended Operating
Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−3
6.4
6.5
6.6
6.7
66-MHz PCI Clock Signal AC Parameters . . . . . . . . . . . . . . . . . . . . . . 6−4
66-MHz PCI Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−5
Parameter Measurement Information . . . . . . . . . . . . . . . . . . . . . . . . . . 6−6
PCI Bus Parameter Measurement Information . . . . . . . . . . . . . . . . . . . 6−7
7
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7−1
v
List of Illustrations
Figure
2−1
Title
Page
PCI2050B GHK/ZHK Terminal Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−1
PCI2050B PDV Terminal Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−2
PCI2050B PPM Terminal Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−3
System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−1
2−2
2−3
3−1
3−2
PCI AD31−AD0 During Address Phase of a Type 0 Configuration
Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−3
3−3
PCI AD31−AD0 During Address Phase of a Type 1 Configuration
Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−4
3−4
3−5
3−6
6−1
6−3
6−4
Bus Hierarchy and Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−4
Secondary Clock Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−6
Clock Mask Read Timing After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−15
PCI Clock Signal AC Parameter Measurements . . . . . . . . . . . . . . . . . . . . 6−4
Load Circuit and Voltage Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−6
RSTIN Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−7
vi
List of Tables
Table
Title
Page
2−1
2−2
2−3
2−4
2−5
2−6
2−7
2−8
2−9
208-Terminal PDV Signal Names Sorted by Terminal Number . . . . . . . . 2−4
208-Terminal PPM Signal Names Sorted by Terminal Number . . . . . . . . 2−5
257-Terminal GHK/ZHK Signal Names Sorted by Terminal Number . . . 2−6
208-Terminal PDV Signal Names Sorted Alphabetically . . . . . . . . . . . . . . 2−8
208-Terminal PPM Signal Names Sorted Alphabetically . . . . . . . . . . . . . . 2−9
257-Terminal GHK/ZHK Signal Names Sorted Alphabetically . . . . . . . . . 2−10
Primary PCI System Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−12
Primary PCI Address and Data Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . 2−12
Primary PCI Interface Control Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−13
2−10 Secondary PCI System Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−14
2−11 Secondary PCI Address and Data Terminals . . . . . . . . . . . . . . . . . . . . . . . 2−15
2−12 Secondary PCI Interface Control Terminals . . . . . . . . . . . . . . . . . . . . . . . . . 2−16
2−13 JTAG Interface Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−16
2−14 Miscellaneous Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−17
2−15 Power Supply Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−17
3−1
3−2
PCI Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−3
PCI S_AD31−S_AD16 During the Address Phase of a Type 0 Configuration
Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−5
3−3
3−4
3−5
3−6
4−1
4−2
4−3
4−4
4−5
5−1
5−2
5−3
5−4
5−5
5−6
5−7
5−8
5−9
Configuration via MS0 and MS1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−10
JTAG Instructions and Op Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−11
Boundary Scan Terminal Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−11
Clock Mask Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−15
Bridge Configuration Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−1
Command Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−3
Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−4
Secondary Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−10
Bridge Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−15
Chip Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−1
Extended Diagnostic Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . 5−2
Arbiter Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−3
P_SERR Event Disable Register Description . . . . . . . . . . . . . . . . . . . . . . . 5−4
GPIO Output Data Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−5
GPIO Output Enable Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . 5−5
GPIO Input Data Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−6
Secondary Clock Control Register Description . . . . . . . . . . . . . . . . . . . . . . 5−7
P_SERR Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−8
5−10 Power-Management Capabilities Register Description . . . . . . . . . . . . . . . 5−9
5−11 Power-Management Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . 5−10
vii
Table
Title
Page
5−12 PMCSR Bridge Support Register Description . . . . . . . . . . . . . . . . . . . . . . . 5−11
5−13 Hot-Swap Control Status Register Description . . . . . . . . . . . . . . . . . . . . . . 5−13
5−14 Diagnostics Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−14
viii
1 Introduction
The Texas Instruments PCI2050B PCI-to-PCI bridge provides a high performance connection path between two
peripheral component interconnect (PCI) buses operating at a maximum bus frequency of 66-MHz. Transactions
occur between masters on one and targets on another PCI bus, and the PCI2050B bridge allows bridged transactions
to occur concurrently on both buses. The bridge supports burst mode transfers to maximize data throughput, and the
two bus traffic paths through the bridge act independently.
The PCI2050B bridge is compliant with the PCI Local Bus Specification, and can be used to overcome the electrical
loading limits of 10 devices per PCI bus and one PCI device per extension slot by creating hierarchical buses. The
PCI2050B provides two-tier internal arbitration for up to nine secondary bus masters and may be implemented with
an external bus arbiter.
The CompactPCI hot-swap extended PCI capability makes the PCI2050B bridge an ideal solution for multifunction
compact PCI cards and adapting single function cards to hot-swap compliance.
The PCI2050B bridge is compliant with the PCI-to-PCI Bridge Specification (Revision 1.1). The PCI2050B bridge
provides compliance for PCI Bus Power Management Interface Specification (Revision 1.1). The PCI2050B bridge
has been designed to lead the industry in power conservation and data throughput. An advanced CMOS process
achieves low system power consumption while operating at PCI clock rates up to 66-MHz.
1.1 Features
The PCI2050B bridge supports the following features:
•
•
•
Two 32-bit, 66-MHz PCI buses
3.3-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments
Internal two-tier arbitration for up to nine secondary bus masters and supports an external secondary bus
arbiter
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Ten secondary PCI clock outputs
Independent read and write buffers for each direction
Burst data transfers with pipeline architecture to maximize data throughput in both directions
Supports write combing for enhanced data throughput
Up to three delayed transactions in both directions
Supports the frame-to-frame delay of only four PCI clocks from one bus to another
Bus locking propagation
Predictable latency per PCI Local Bus Specification
Architecture configurable for PCI Bus Power Management Interface Specification
CompactPCI hot-swap functionality
Secondary bus is driven low during reset
VGA/palette memory and I/O decoding options
Advanced submicron, low-power CMOS technology
208-terminal PDV, 208-terminal PPM, or 257-terminal MicroStar BGA package
1−1
1.2 Related Documents
•
•
•
•
•
•
Advanced Configuration and Power Interface (ACPI) Specification (Revision 1.0)
IEEE Standard Test Access Port and Boundary-Scan Architecture
PCI Local Bus Specification (Revision 2.2)
PCI-to-PCI Bridge Specification (Revision 1.1)
PCI Bus Power Management Interface Specification (Revision 1.1)
PICMG CompactPCI Hot-Swap Specification (Revision 1.0)
1.3 Trademarks
CompactPCI is a trademark of PICMG − PCI Industrial Computer Manufacturers Group, Inc.
Intel is a trademark of Intel Corporation.
MicroStar BGA and TI are trademarks of Texas Instruments.
Other trademarks are the property of their respective owners.
1.4 Ordering Information
ORDERING NUMBER
PCI2050BPDV
PCI2050BPPM
PCI2050BGHK
PCI2050BZHK
PCI2050BIPDV
PCI2050BIGHK
PCI2050BIZHK
VOLTAGE
TEMPERATURE
0°C to 70°C
PACKAGE
208 QFP
3.3-V, 5-V Tolerant I/Os
3.3-V, 5-V Tolerant I/Os
3.3-V, 5-V Tolerant I/Os
3.3-V, 5-V Tolerant I/Os
3.3-V, 5-V Tolerant I/Os
3.3-V, 5-V Tolerant I/Os
3.3-V, 5-V Tolerant I/Os
0°C to 70°C
208 QFP
0°C to 70°C
257 BGA
0°C to 70°C
257 RoHS BGA
208 QFP
−40°C to 85°C
−40°C to 85°C
−40°C to 85°C
257 BGA
257 RoHS BGA
1−2
2 Terminal Descriptions
The PCI2050B device is available in four packages, a 257-terminal GHK MicroStar BGA package, a 257-terminal
RoHS-compliant ZHK MicroStar BGA package, a 208-terminal PDV package, or a 208-terminal PPM package. The
GHK and ZHK packages are mechanically and electrically identical, but the ZHK is a RoHS-compliant design.
Throughout the remainder of this manual, only the GHK package designator is used for either the GHK or the ZHK
package. Figure 2−1 is the GHK-package terminal diagram. Figure 2−2 is the PDV-package terminal diagram.
Figure 2−3 is the PPM-package terminal diagram. Table 2−1 lists terminals on the PDV packaged device in
increasing numerical order with the signal name for each. Table 2−2 lists terminals on the PPM packaged device in
increasing alphanumerical order with the signal name for each. Table 2−3 lists terminals on the GHK packaged device
in increasing alphanumerical order with the signal name for each. Table 2−4, Table 2−5, and Table 2−6 list the signal
names in alphabetical order, with corresponding terminal numbers for each package type.
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
3
5
7
9
11 13 15 17 19
10 12 14 16 18
2
4
6
8
Figure 2−1. PCI2050B GHK/ZHK Terminal Diagram
2−1
PDV LOW-PROFILE QUAD FLAT PACKAGE
TOP VIEW
V
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
CC
GND
GND
S_AD11
GND
V
CC
P_M66ENA
P_AD10
GND
S_AD12
P_AD11
P_AD12
S_AD13
V
CC
S_AD14
S_AD15
GND
S_C/BE1
S_PAR
V
CC
P_AD13
P_AD14
GND
P_AD15
P_C/BE1
S_SERR
V
V
CC
CC
P_PAR
S_PERR
S_LOCK
S_STOP
GND
P_SERR
P_PERR
P_LOCK
GND
P_STOP
P_DEVSEL
P_TRDY
P_IRDY
S_DEVSEL
S_TRDY
S_IRDY
V
CC
S_FRAME
S_C/BE2
GND
S_AD16
S_AD17
V
CC
PCI2050B
P_FRAME
P_C/BE2
GND
V
P_AD16
P_AD17
CC
S_AD18
S_AD19
GND
V
CC
P_AD18
P_AD19
GND
S_AD20
S_AD21
V
P_AD20
P_AD21
CC
S_AD22
S_AD23
V
CC
P_AD22
P_AD23
GND
GND
S_C/BE3
S_AD24
V
P_IDSEL
P_C/BE3
P_AD24
CC
S_AD25
S_AD26
GND
V
CC
S_AD27
P_AD25
P_AD26
GND
S_AD28
V
CC
S_AD29
S_AD30
P_AD27
P_AD28
V
CC
GND
S_AD31
S_REQ0
P_AD29
GND
V
V
CC
CC
Figure 2−2. PCI2050B PDV Terminal Diagram
2−2
PPM QUAD FLAT PACKAGE
TOP VIEW
V
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
CC
GND
GND
S_AD11
GND
V
CC
P_M66ENA
P_AD10
GND
S_AD12
P_AD11
P_AD12
S_AD13
V
CC
S_AD14
S_AD15
GND
S_C/BE1
S_PAR
V
CC
P_AD13
P_AD14
GND
P_AD15
P_C/BE1
S_SERR
V
V
CC
CC
P_PAR
S_PERR
S_LOCK
S_STOP
GND
P_SERR
P_PERR
P_LOCK
GND
P_STOP
P_DEVSEL
P_TRDY
P_IRDY
S_DEVSEL
S_TRDY
S_IRDY
V
CC
S_FRAME
S_C/BE2
GND
S_AD16
S_AD17
V
CC
PCI2050B
P_FRAME
P_C/BE2
GND
V
P_AD16
P_AD17
CC
S_AD18
S_AD19
GND
V
CC
P_AD18
P_AD19
GND
S_AD20
S_AD21
V
P_AD20
P_AD21
CC
S_AD22
S_AD23
V
CC
P_AD22
P_AD23
GND
GND
S_C/BE3
S_AD24
V
P_IDSEL
P_C/BE3
P_AD24
CC
S_AD25
S_AD26
GND
V
CC
S_AD27
P_AD25
P_AD26
GND
S_AD28
V
CC
S_AD29
S_AD30
P_AD27
P_AD28
V
CC
GND
S_AD31
S_REQ0
P_AD29
GND
V
V
CC
CC
Figure 2−3. PCI2050B PPM Terminal Diagram
2−3
Table 2−1. 208-Terminal PDV Signal Names Sorted by Terminal Number
PDV
NO.
PDV
NO.
PDV
NO.
PDV
NO.
PDV
NO.
SIGNAL NAME
SIGNAL NAME
SIGNAL NAME
SIGNAL NAME
SIGNAL NAME
1
V
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
P_RST
BPCCE
P_CLK
P_GNT
P_REQ
GND
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
P_STOP
GND
127 HS_ENUM
128 HS_LED
129 TDI
169 S_SERR
170
CC
2
S_REQ1
S_REQ2
S_REQ3
S_REQ4
S_REQ5
S_REQ6
S_REQ7
S_REQ8
S_GNT0
S_GNT1
GND
V
CC
3
P_LOCK
P_PERR
P_SERR
P_PAR
171 S_PERR
172 S_LOCK
173 S_STOP
174 GND
4
130 TDO
5
131
V
CC
6
132 TMS
133 TCK
134 TRST
7
P_AD31
P_AD30
V
CC
175 S_DEVSEL
176 S_TRDY
177 S_IRDY
8
P_C/BE1
P_AD15
GND
9
V
CC
GND
135 S_V
CCP
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
136 GND
178
V
CC
V
CC
P_AD14
P_AD13
137 S_AD0
138 S_AD1
179 S_FRAME
180 S_C/BE2
181 GND
GND
S_GNT2
S_GNT3
S_GNT4
S_GNT5
S_GNT6
S_GNT7
S_GNT8
GND
P_AD29
V
CC
139
V
CC
V
CC
P_AD12
P_AD11
140 S_AD2
141 S_AD3
142 GND
182 S_AD16
183 S_AD17
P_AD28
P_AD27
GND
100 GND
184
V
CC
101 P_AD10
102 P_M66ENA
143 S_AD4
144 S_AD5
185 S_AD18
186 S_AD19
187 GND
P_AD26
P_AD25
103
104 GND
105
V
CC
145
V
CC
V
CC
146 S_AD6
147 S_AD7
148 GND
188 S_AD20
189 S_AD21
S_CLK
P_AD24
P_C/BE3
P_IDSEL
GND
V
CC
S_RST
106 MS1
190
V
CC
S_CFN
107 P_AD9
149 S_C/BE0
150 S_AD8
191 S_AD22
192 S_AD23
193 GND
HS_SWITCH/GPIO3
GPIO2
108
V
CC
P_AD23
P_AD22
109 P_AD8
110 P_C/BE0
111 GND
151
V
CC
V
CC
152 S_AD9
153 S_M66ENA
154 S_AD10
155 MS0
194 S_C/BE3
195 S_AD24
GPIO1
V
CC
GPIO0
P_AD21
P_AD20
GND
112 P_AD7
113 P_AD6
196
V
CC
S_CLKOUT0
S_CLKOUT1
GND
197 S_AD25
198 S_AD26
199 GND
114
V
CC
156 GND
P_AD19
P_AD18
115 P_AD5
116 P_AD4
117 GND
157
V
CC
S_CLKOUT2
S_CLKOUT3
158 GND
200 S_AD27
201 S_AD28
V
CC
159 S_AD11
160 GND
V
CC
P_AD17
P_AD16
GND
118 P_AD3
119 P_AD2
202
V
CC
S_CLKOUT4
S_CLKOUT5
GND
161 S_AD12
162 S_AD13
203 S_AD29
204 S_AD30
205 GND
120
V
CC
P_C/BE2
P_FRAME
121 P_AD1
122 P_AD0
123 GND
163
V
CC
S_CLKOUT6
S_CLKOUT7
164 S_AD14
165 S_AD15
166 GND
206 S_AD31
207 S_REQ0
V
CC
V
CC
P_IRDY
124 P_V
CCP
208
V
CC
S_CLKOUT8
S_CLKOUT9
P_TRDY
P_DEVSEL
125 CONFIG66
126 MSK_IN
167 S_C/BE1
168 S_PAR
2−4
Table 2−2. 208-Terminal PPM Signal Names Sorted by Terminal Number
PPM
NO.
PPM
NO.
PPM
NO.
PPM
NO.
PPM
NO.
SIGNAL NAME
SIGNAL NAME
SIGNAL NAME
SIGNAL NAME
SIGNAL NAME
1
V
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
P_RST
BPCCE
P_CLK
P_GNT
P_REQ
GND
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
P_STOP
GND
127 HS_ENUM
128 HS_LED
129 TDI
169 S_SERR
170
CC
2
S_REQ1
S_REQ2
S_REQ3
S_REQ4
S_REQ5
S_REQ6
S_REQ7
S_REQ8
S_GNT0
S_GNT1
GND
V
CC
3
P_LOCK
P_PERR
P_SERR
P_PAR
171 S_PERR
172 S_LOCK
173 S_STOP
174 GND
4
130 TDO
5
131
V
CC
6
132 TMS
133 TCK
134 TRST
7
P_AD31
P_AD30
V
CC
175 S_DEVSEL
176 S_TRDY
177 S_IRDY
8
P_C/BE1
P_AD15
GND
9
V
CC
GND
135 S_V
CCP
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
136 GND
178
V
CC
V
CC
P_AD14
P_AD13
137 S_AD0
138 S_AD1
179 S_FRAME
180 S_C/BE2
181 GND
GND
S_GNT2
S_GNT3
S_GNT4
S_GNT5
S_GNT6
S_GNT7
S_GNT8
GND
P_AD29
V
CC
139
V
CC
V
CC
P_AD12
P_AD11
140 S_AD2
141 S_AD3
142 GND
182 S_AD16
183 S_AD17
P_AD28
P_AD27
GND
100 GND
184
V
CC
101 P_AD10
102 P_M66ENA
143 S_AD4
144 S_AD5
185 S_AD18
186 S_AD19
187 GND
P_AD26
P_AD25
103
104 GND
105
V
CC
145
V
CC
V
CC
146 S_AD6
147 S_AD7
148 GND
188 S_AD20
189 S_AD21
S_CLK
P_AD24
P_C/BE3
P_IDSEL
GND
V
CC
S_RST
106 MS1
190
V
CC
S_CFN
107 P_AD9
149 S_C/BE0
150 S_AD8
191 S_AD22
192 S_AD23
193 GND
HS_SWITCH/GPIO3
GPIO2
108
V
CC
P_AD23
P_AD22
109 P_AD8
110 P_C/BE0
111 GND
151
V
CC
V
CC
152 S_AD9
153 S_M66ENA
154 S_AD10
155 MS0
194 S_C/BE3
195 S_AD24
GPIO1
V
CC
GPIO0
P_AD21
P_AD20
GND
112 P_AD7
113 P_AD6
196
V
CC
S_CLKOUT0
S_CLKOUT1
GND
197 S_AD25
198 S_AD26
199 GND
114
V
CC
156 GND
P_AD19
P_AD18
115 P_AD5
116 P_AD4
117 GND
157
V
CC
S_CLKOUT2
S_CLKOUT3
158 GND
200 S_AD27
201 S_AD28
V
CC
159 S_AD11
160 GND
V
CC
P_AD17
P_AD16
GND
118 P_AD3
119 P_AD2
202
V
CC
S_CLKOUT4
S_CLKOUT5
GND
161 S_AD12
162 S_AD13
203 S_AD29
204 S_AD30
205 GND
120
V
CC
P_C/BE2
P_FRAME
121 P_AD1
122 P_AD0
123 GND
163
V
CC
S_CLKOUT6
S_CLKOUT7
164 S_AD14
165 S_AD15
166 GND
206 S_AD31
207 S_REQ0
V
CC
V
CC
P_IRDY
124 P_V
CCP
208
V
CC
S_CLKOUT8
S_CLKOUT9
P_TRDY
P_DEVSEL
125 CONFIG66
126 MSK_IN
167 S_C/BE1
168 S_PAR
2−5
Table 2−3. 257-Terminal GHK/ZHK Signal Names Sorted by Terminal Number
GHK
NO.
GHK
NO.
GHK
NO.
GHK
NO.
GHK
NO.
SIGNAL NAME
SIGNAL NAME
SIGNAL NAME
SIGNAL NAME
SIGNAL NAME
A2
A3
A4
A5
A6
A7
A8
A9
NC
C8
V
F11 S_FRAME
F12 S_C/BE1
F13 GND
K14 TMS
K15
P10 P_C/BE2
P11 P_TRDY
P12 P_LOCK
P13 P_C/BE1
P14 P_AD12
CC
V
CC
C9 S_AD18
C10 NC
V
CC
S_AD31
S_AD28
S_AD25
GND
K17 TDO
K18 TDI
K19 NC
C11 S_IRDY
C12 S_LOCK
C13 S_PAR
F14 S_AD9
F15 S_AD10
F17 S_AD8
F18 GND
L1
L2
L3
L5
L6
S_CLKOUT0
P15
V
CC
S_AD20
C14
V
CC
S_CLKOUT1
NC
P17 P_AD7
P18 P_AD6
P19 P_AD5
R1 P_GNT
R2 NC
V
CC
C15 GND
C16 NC
C17 NC
C18 NC
C19 NC
D1 NC
F19 S_AD7
G1 S_GNT3
G2 S_GNT2
G3 GND
A10 S_C/BE2
A11 S_DEVSEL
A12 GND
S_CLKOUT2
GND
L14 HS_LED
L15 HS_ENUM
L17 MSK_IN
L18 CONFIG66
A13
V
CC
G5 S_REQ8
G6 S_REQ3
G14 S_AD6
G15 S_C/BE0
R3 P_AD31
R6 P_AD29
R7 P_AD26
R8 GND
A14 GND
A15 S_AD13
D2
V
CC
A16
V
CC
D3 NC
L19 P_V
CCP
A17 NC
A18 NC
D17 NC
G17
V
M1 S_CLKOUT3
M2
R9 P_AD19
R10 GND
CC
D18 NC
G18 S_AD5
G19 S_AD4
H1 S_GNT7
H2 S_GNT6
H3 S_GNT5
H5 S_GNT4
H6 S_GNT1
H14 S_AD3
H15 GND
V
CC
B1
B2
B3
B4
B5
B6
B7
B8
B9
NC
D19 GND
E1 S_REQ5
E2 S_REQ4
E3 S_REQ1
M3 S_CLKOUT4
M5 GND
R11 P_DEVSEL
R12 P_PERR
R13 P_AD14
R14 GND
NC
NC
M6 S_CLKOUT5
M14 P_AD4
S_REQ0
S_AD29
S_AD26
S_C/BE3
S_AD21
NC
†
E5
NC
M15
V
CC
R17 P_AD9
R18 P_C/BE0
R19 GND
E6 S_AD30
E7 GND
M17 P_AD1
M18 P_AD0
E8 S_AD23
E9 GND
M19 GND
T1
T2
T3
P_AD30
H17 S_AD2
N1 S_CLKOUT6
N2 S_CLKOUT7
V
CC
NC
B10 GND
B11 S_TRDY
B12 S_STOP
B13 S_SERR
B14 S_AD14
B15 S_AD12
B16 NC
E10 S_AD16
H18
V
CC
E11
V
CC
H19 S_AD1
N3
V
CC
T17 NC
T18
E12 S_PERR
E13 S_AD15
E14 S_AD11
E17 MS0
J1
J2
J3
J5
J6
S_GNT8
GND
N5 BPCCE
N6 S_CLKOUT8
N14 P_AD8
V
CC
T19 MS1
U1 GND
U2 NC
S_CLK
S_RST
S_CFN
N15
V
CC
E18 S_M66ENA
N17 GND
U3 NC
B17 NC
E19
F1
F2
F3
F5
F6
F7
F8
F9
V
J14 GND
N18 P_AD3
N19 P_AD2
P1 S_CLKOUT9
P2 P_RST
P3 P_CLK
P5 GND
U4 NC
CC
B18 NC
S_GNT0
S_REQ7
S_REQ6
S_REQ2
J15 S_AD0
U5 GND
U6 P_AD27
U7 P_AD24
U8 P_AD23
U9 GND
U10 P_AD16
U11 P_IRDY
U12 GND
B19 NC
J17 S_V
CCP
C1
C2
C3
C4
C5
C6
C7
NC
J18 TRST
NC
J19 TCK
NC
V
V
K1 HS_SWITCH/GPIO3
K2 GPIO2
CC
NC
P6 P_REQ
CC
GND
S_AD27
S_AD24
S_AD22
S_AD19
K3
V
CC
P7
P8
V
V
CC
K5 GPIO1
K6 GPIO0
CC
F10 S_AD17
P9 P_AD18
U13
V
CC
†
Terminal E5 is used as a key to indicate the location of the A1 corner. It is a no-connect terminal.
2−6
Table 2−3. 257-Terminal GHK/ZHK Signal Names Sorted by Terminal Number (Continued)
GHK
NO.
GHK
NO.
GHK
NO.
GHK
NO.
GHK
NO.
SIGNAL NAME
SIGNAL NAME
SIGNAL NAME
SIGNAL NAME
SIGNAL NAME
U14 P_AD13
U15 P_AD10
U16 NC
V4 NC
V13 P_PAR
V14 GND
W4
V
W13 P_SERR
W14 P_AD15
CC
V5 NC
W5 P_AD28
W6 P_AD25
W7 P_IDSEL
V6 GND
V15 P_AD11
W15
V
CC
U17 NC
V7 P_C/BE3
V8 P_AD22
V9 P_AD20
V10 P_AD17
V16
V
CC
W16 P_M66ENA
W17 NC
U18 NC
V17 NC
V18 NC
V19 NC
W2 NC
W3 NC
W8
W9 P_AD21
W10
V
CC
U19 NC
W18 NC
V1
V2
V3
NC
NC
NC
V
CC
V11
V
CC
W11 P_FRAME
W12 P_STOP
V12 NC
2−7
Table 2−4. 208-Terminal PDV Signal Names Sorted Alphabetically
PDV
NO.
PDV
NO.
PDV
NO.
PDV
NO.
PDV
NO.
SIGNAL NAME
BPCCE
SIGNAL NAME
SIGNAL NAME
SIGNAL NAME
SIGNAL NAME
44
125
12
P_AD0
122
121
119
118
116
115
113
112
109
107
101
99
P_LOCK
P_M66ENA
P_PAR
87
S_C/BE0
S_C/BE1
S_C/BE2
S_C/BE3
S_CFN
149
167
180
194
23
21
29
30
32
33
35
36
38
39
41
42
175
179
10
11
S_SERR
S_STOP
S_TRDY
169
173
176
135
133
129
130
132
134
1
CONFIG66
GND
P_AD1
102
90
P_AD2
GND
20
P_AD3
P_PERR
P_REQ
88
S_V
CCP
GND
31
P_AD4
47
TCK
TDI
GND
37
P_AD5
P_RST
43
S_CLK
GND
48
P_AD6
P_SERR
P_STOP
P_TRDY
89
S_CLKOUT0
S_CLKOUT1
S_CLKOUT2
S_CLKOUT3
S_CLKOUT4
S_CLKOUT5
S_CLKOUT6
S_CLKOUT7
S_CLKOUT8
S_CLKOUT9
S_DEVSEL
S_FRAME
S_GNT0
TDO
TMS
TRST
GND
52
P_AD7
85
GND
54
P_AD8
83
GND
59
P_AD9
P_V
CCP
124
137
138
140
141
143
144
146
147
150
152
154
159
161
162
164
165
182
183
185
186
188
189
191
192
195
197
198
200
201
203
204
206
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
GND
66
P_AD10
P_AD11
P_AD12
P_AD13
P_AD14
P_AD15
P_AD16
P_AD17
P_AD18
P_AD19
P_AD20
P_AD21
P_AD22
P_AD23
P_AD24
P_AD25
P_AD26
P_AD27
P_AD28
P_AD29
P_AD30
P_AD31
P_C/BE0
P_C/BE1
P_C/BE2
P_C/BE3
P_CLK
S_AD0
26
GND
72
S_AD1
34
GND
78
98
S_AD2
40
GND
86
96
S_AD3
51
GND
94
95
S_AD4
53
GND
100
104
111
117
123
136
142
148
156
158
160
166
174
181
187
193
199
205
28
93
S_AD5
56
GND
77
S_AD6
62
GND
76
S_AD7
69
GND
74
S_AD8
75
GND
73
S_AD9
S_GNT1
81
GND
71
S_AD10
S_AD11
S_AD12
S_AD13
S_AD14
S_AD15
S_AD16
S_AD17
S_AD18
S_AD19
S_AD20
S_AD21
S_AD22
S_AD23
S_AD24
S_AD25
S_AD26
S_AD27
S_AD28
S_AD29
S_AD30
S_AD31
S_GNT2
13
14
15
16
17
18
19
177
172
153
168
171
207
2
91
GND
70
S_GNT3
97
GND
68
S_GNT4
103
105
108
114
120
131
139
145
151
202
208
157
163
170
178
184
190
196
GND
67
S_GNT5
GND
63
S_GNT6
GND
61
S_GNT7
GND
60
S_GNT8
GND
58
S_IRDY
GND
57
S_LOCK
GND
55
S_M66ENA
S_PAR
GND
50
GND
49
S_PERR
GND
110
92
S_REQ0
GPIO0
GPIO1
GPIO2
HS_ENUM
HS_LED
HS_SWITCH/GPIO3
MS0
S_REQ1
27
79
S_REQ2
3
25
64
S_REQ3
4
127
128
24
45
S_REQ4
5
P_DEVSEL
P_FRAME
P_GNT
84
S_REQ5
6
80
S_REQ6
7
155
106
126
46
S_REQ7
8
MS1
P_IDSEL
P_IRDY
65
S_REQ8
9
MSK_IN
82
S_RST
22
2−8
Table 2−5. 208-Terminal PPM Signal Names Sorted Alphabetically
PPM
NO.
PPM
NO.
PPM
NO.
PPM
NO.
PPM
NO.
SIGNAL NAME
BPCCE
SIGNAL NAME
SIGNAL NAME
SIGNAL NAME
SIGNAL NAME
44
125
12
P_AD0
122
121
119
118
116
115
113
112
109
107
101
99
P_LOCK
P_M66ENA
P_PAR
87
S_C/BE0
S_C/BE1
S_C/BE2
S_C/BE3
S_CFN
149
167
180
194
23
21
29
30
32
33
35
36
38
39
41
42
175
179
10
11
S_SERR
S_STOP
S_TRDY
169
173
176
135
133
129
130
132
134
1
CONFIG66
GND
P_AD1
102
90
P_AD2
GND
20
P_AD3
P_PERR
P_REQ
88
S_V
CCP
GND
31
P_AD4
47
TCK
TDI
GND
37
P_AD5
P_RST
43
S_CLK
GND
48
P_AD6
P_SERR
P_STOP
P_TRDY
89
S_CLKOUT0
S_CLKOUT1
S_CLKOUT2
S_CLKOUT3
S_CLKOUT4
S_CLKOUT5
S_CLKOUT6
S_CLKOUT7
S_CLKOUT8
S_CLKOUT9
S_DEVSEL
S_FRAME
S_GNT0
TDO
TMS
TRST
GND
52
P_AD7
85
GND
54
P_AD8
83
GND
59
P_AD9
P_V
CCP
124
137
138
140
141
143
144
146
147
150
152
154
159
161
162
164
165
182
183
185
186
188
189
191
192
195
197
198
200
201
203
204
206
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
GND
66
P_AD10
P_AD11
P_AD12
P_AD13
P_AD14
P_AD15
P_AD16
P_AD17
P_AD18
P_AD19
P_AD20
P_AD21
P_AD22
P_AD23
P_AD24
P_AD25
P_AD26
P_AD27
P_AD28
P_AD29
P_AD30
P_AD31
P_C/BE0
P_C/BE1
P_C/BE2
P_C/BE3
P_CLK
S_AD0
26
GND
72
S_AD1
34
GND
78
98
S_AD2
40
GND
86
96
S_AD3
51
GND
94
95
S_AD4
53
GND
100
104
111
117
123
136
142
148
156
158
160
166
174
181
187
193
199
205
28
93
S_AD5
56
GND
77
S_AD6
62
GND
76
S_AD7
69
GND
74
S_AD8
75
GND
73
S_AD9
S_GNT1
81
GND
71
S_AD10
S_AD11
S_AD12
S_AD13
S_AD14
S_AD15
S_AD16
S_AD17
S_AD18
S_AD19
S_AD20
S_AD21
S_AD22
S_AD23
S_AD24
S_AD25
S_AD26
S_AD27
S_AD28
S_AD29
S_AD30
S_AD31
S_GNT2
13
14
15
16
17
18
19
177
172
153
168
171
207
2
91
GND
70
S_GNT3
97
GND
68
S_GNT4
103
105
108
114
120
131
139
145
151
202
208
157
163
170
178
184
190
196
GND
67
S_GNT5
GND
63
S_GNT6
GND
61
S_GNT7
GND
60
S_GNT8
GND
58
S_IRDY
GND
57
S_LOCK
GND
55
S_M66ENA
S_PAR
GND
50
GND
49
S_PERR
GND
110
92
S_REQ0
GPIO0
GPIO1
GPIO2
HS_ENUM
HS_LED
HS_SWITCH/GPIO3
MS0
S_REQ1
27
79
S_REQ2
3
25
64
S_REQ3
4
127
128
24
45
S_REQ4
5
P_DEVSEL
P_FRAME
P_GNT
84
S_REQ5
6
80
S_REQ6
7
155
106
126
46
S_REQ7
8
MS1
P_IDSEL
P_IRDY
65
S_REQ8
9
MSK_IN
82
S_RST
22
2−9
Table 2−6. 257-Terminal GHK/ZHK Signal Names Sorted Alphabetically
GHK
NO.
GHK
NO.
GHK
NO.
GHK
NO.
GHK
NO.
SIGNAL NAME
BPCCE
SIGNAL NAME
SIGNAL NAME
SIGNAL NAME
SIGNAL NAME
N5
L18
A7
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
A18
B1
NC
V19
W2
W3
P_FRAME
P_GNT
W11 S_AD29
B5
E6
CONFIG66
GND
NC
R1
W7
U11
P12
S_AD30
S_AD31
S_CFN
S_CLK
B2
NC
P_IDSEL
A4
GND
A12
A14
B10
C5
B3
NC
W17 P_IRDY
W18 P_LOCK
M18 P_M66ENA
M17 P_PAR
J6
GND
B9
NC
J3
GND
B16
B17
B18
B19
C1
P_AD0
P_AD1
P_AD2
P_AD3
P_AD4
P_AD5
P_AD6
P_AD7
P_AD8
P_AD9
P_AD10
P_AD11
P_AD12
P_AD13
P_AD14
P_AD15
P_AD16
P_AD17
P_AD18
P_AD19
P_AD20
P_AD21
P_AD22
P_AD23
P_AD24
P_AD25
P_AD26
P_AD27
P_AD28
P_AD29
P_AD30
P_AD31
P_CLK
P_C/BE0
P_C/BE1
P_C/BE2
P_C/BE3
P_DEVSEL
W16 S_CLKOUT0
L1
GND
V13
R12
P6
S_CLKOUT1
S_CLKOUT2
S_CLKOUT3
S_CLKOUT4
L2
GND
C15
D19
E7
N19
N18
P_PERR
P_REQ
L5
GND
M1
M3
M6
N1
N2
N6
P1
GND
M14 P_RST
P2
GND
E9
C2
P19
P18
P17
N14
R17
U15
V15
P14
U14
R13
P_SERR
P_STOP
P_TRDY
W13 S_CLKOUT5
W12 S_CLKOUT6
GND
F13
F18
G3
C3
GND
C4
P11
L19
J15
H19
H17
H14
G19
G18
G14
F19
F17
F14
F15
E14
B15
A15
B14
E13
E10
F10
C9
S_CLKOUT7
S_CLKOUT8
S_CLKOUT9
S_C/BE0
S_C/BE1
S_C/BE2
S_C/BE3
S_DEVSEL
S_FRAME
S_GNT0
S_GNT1
S_GNT2
S_GNT3
S_GNT4
S_GNT5
S_GNT6
S_GNT7
S_GNT8
S_IRDY
GND
C10
C16
C17
C18
C19
D1
P_V
CCP
GND
H15
J2
S_AD0
S_AD1
S_AD2
S_AD3
S_AD4
S_AD5
GND
G15
F12
A10
B7
GND
J14
L6
GND
GND
M5
GND
M19 NC
D3
A11
F11
F1
GND
N17
P5
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
D17
D18
E5
W14 S_AD6
GND
U10
V10
P9
S_AD7
GND
R8
S_AD8
H6
G2
G1
H5
H3
H2
H1
J1
GND
R10
R14
R19
U1
K19
L3
S_AD9
GND
R9
S_AD10
S_AD11
S_AD12
S_AD13
S_AD14
S_AD15
S_AD16
S_AD17
S_AD18
S_AD19
S_AD20
S_AD21
S_AD22
S_AD23
S_AD24
S_AD25
S_AD26
S_AD27
S_AD28
GND
R2
V9
GND
T3
W9
V8
GND
U5
T17
U2
GND
U9
U8
GND
U12
V6
U3
U7
GND
U4
W6
R7
C11
C12
E18
C13
E12
B4
GND
V14
K6
U16
U17
U18
U19
V1
S_LOCK
S_M66ENA
S_PAR
GPIO0
GPIO1
GPIO2
HS_ENUM
HS_LED
HS_SWITCH/GPIO3
MSK_IN
MS0
U6
K5
W5
R6
F9
K2
A8
S_PERR
S_REQ0
S_REQ1
S_REQ2
S_REQ3
S_REQ4
S_REQ5
S_REQ6
S_REQ7
L15
L14
K1
T1
B8
V2
R3
F8
E3
V3
P3
E8
F5
L17
E17
T19
A2
V4
R18
P13
P10
V7
C7
G6
E2
V5
A6
MS1
V12
V17
V18
B6
E1
NC
C6
F3
NC
A17
R11
A5
F2
2−10
Table 2−6. 257-Terminal GHK/ZHK Signal Names Sorted Alphabetically (Continued)
GHK
NO.
GHK
NO.
GHK
NO.
GHK
NO.
GHK
NO.
SIGNAL NAME
SIGNAL NAME
SIGNAL NAME
SIGNAL NAME
SIGNAL NAME
S_REQ8
S_RST
G5
J5
TMS
K14
J18
A3
V
E11
E19
F6
V
M2
N3
V
V11
V16
W4
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
TRST
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
S_SERR
S_STOP
S_TRDY
B13
B12
B11
J17
J19
K18
K17
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
N15
P7
A9
F7
W8
A13
A16
C8
M15
G17
H18
K3
P8
W10
W15
S_V
CCP
P15
T2
TCK
TDI
C14
D2
T18
U13
TDO
K15
2−11
The terminals are grouped in tables by functionality, such as PCI system function and power-supply function (see
Table 2−7 through Table 2−15). The terminal numbers also are listed for convenient reference.
Table 2−7. Primary PCI System Terminals
TERMINAL
PDV/ GHK/
I/O
DESCRIPTION
NAME
PPM
NO.
ZHK
NO.
Primary PCI bus clock. P_CLK provides timing for all transactions on the primary PCI bus. All primary PCI
signals are sampled at rising edge of P_CLK.
P_CLK
45
P3
I
I
PCI reset. When the primary PCI bus reset is asserted, P_RST causes the bridge to put all output buffers
in a high-impedance state and reset all internal registers. When asserted, the device is completely
nonfunctional. During P_RST, the secondary interface is driven low. After P_RST is deasserted, the bridge
is in its default state.
43
P2
P_RST
Table 2−8. Primary PCI Address and Data Terminals
TERMINAL
PDV/ GHK/
I/O
DESCRIPTION
NAME
PPM
NO.
ZHK
NO.
P_AD31
P_AD30
P_AD29
P_AD28
P_AD27
P_AD26
P_AD25
P_AD24
P_AD23
P_AD22
P_AD21
P_AD20
P_AD19
P_AD18
P_AD17
P_AD16
P_AD15
P_AD14
P_AD13
P_AD12
P_AD11
P_AD10
P_AD9
49
50
55
57
58
60
61
63
67
68
70
71
73
74
76
77
93
R3
T1
R6
W5
U6
R7
W6
U7
U8
V8
W9
V9
R9
P9
V10
U10
W14
R13
U14
P14
V15
U15
R17
N14
P17
P18
P19
M14
N18
N19
M17
M18
Primary address/data bus. These signals make up the multiplexed PCI address and data bus on the
primary interface. During the address phase of a primary bus PCI cycle, P_AD31−P_AD0 contain a
32-bit address or other destination information. During the data phase, P_AD31−P_AD0 contain data.
I/O
95
96
98
99
101
107
109
112
113
115
116
118
119
121
122
P_AD8
P_AD7
P_AD6
P_AD5
P_AD4
P_AD3
P_AD2
P_AD1
P_AD0
Primary bus commands and byte enables. These signals are multiplexed on the same PCI terminals.
During the address phase of a primary bus PCI cycle, P_C/BE3−P_C/BE0 define the bus command.
During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which byte
paths of the full 32-bit data bus carry meaningful data. P_C/BE0 applies to byte 0 (P_AD7−P_AD0),
P_C/BE1 applies to byte 1 (P_AD15−P_AD8), P_C/BE2 applies to byte 2 (P_AD23−P_AD16), and
P_C/BE3 applies to byte 3 (P_AD31−P_AD24).
64
79
92
V7
P_C/BE3
P_C/BE2
P_C/BE1
P_C/BE0
P10
P13
R18
I/O
110
2−12
Table 2−9. Primary PCI Interface Control Terminals
TERMINAL
PDV/ GHK/
I/O
DESCRIPTION
NAME
P_DEVSEL
P_FRAME
P_GNT
PPM
NO.
ZHK
NO.
Primary device select. The bridge asserts P_DEVSEL to claim a PCI cycle as the target device. As
a PCI master on the primary bus, the bridge monitors P_DEVSEL until a target responds. If no target
responds before time-out occurs, then the bridge terminates the cycle with a master abort.
84
80
46
R11
W11
R1
I/O
I/O
I
Primary cycle frame. P_FRAME is driven by the master of a primary bus cycle. P_FRAME is asserted
to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted.
When P_FRAME is deasserted, the primary bus transaction is in the final data phase.
Primary bus grant to bridge. P_GNT is driven by the primary PCI bus arbiter to grant the bridge access
to the primary PCI bus after the current data transaction has completed. P_GNT may or may not follow
a primary bus request, depending on the primary bus arbitration algorithm.
Primary initialization device select. P_IDSEL selects the bridge during configuration space accesses.
P_IDSEL can be connected to one of the upper 24 PCI address lines on the primary PCI bus.
P_IDSEL
65
W7
I
Note: There is no IDSEL signal interfacing the secondary PCI bus; thus, the entire configuration space
of the bridge can only be accessed from the primary bus.
Primary initiator ready. P_IRDY indicates ability of the primary bus master to complete the current data
phase of the transaction. A data phase is completed on a rising edge of P_CLK where both P_IRDY
and P_TRDY are asserted. Until P_IRDY and P_TRDY are both sampled asserted, wait states are
inserted.
P_IRDY
P_LOCK
P_PAR
82
87
90
U11
P12
V13
I/O
I/O
I/O
Primary PCI bus lock. P_LOCK is used to lock the primary bus and gain exclusive access as a bus
master.
Primary parity. In all primary bus read and write cycles, the bridge calculates even parity across the
P_AD and P_C/BE buses. As a bus master during PCI write cycles, the bridge outputs this parity
indicator with a one-P_CLK delay. As a target during PCI read cycles, the calculated parity is compared
to the parity indicator of the master; a miscompare can result in a parity error assertion (P_PERR).
Primary parity error indicator. P_PERR is driven by a primary bus PCI device to indicate that calculated
parity does not match P_PAR when P_PERR is enabled through bit 6 of the command register (PCI
offset 04h, see Section 4.3).
88
47
R12
P6
I/O
O
P_PERR
P_REQ
Primary PCI bus request. Asserted by the bridge to request access to the primary PCI bus as a master.
Primary system error. Output pulsed from the bridge when enabled through bit 8 of the command
register (PCI offset 04h, see Section 4.3) indicating a system error has occurred. The bridge needs
not be the target of the primary PCI cycle to assert this signal. When bit 6 is enabled in the bridge control
register (PCI offset 3Eh, see Section 4.32), this signal also pulses, indicating that a system error has
occurred on one of the subordinate buses downstream from the bridge.
P_SERR
89
W13
O
Primary cycle stop signal. This signal is driven by a PCI target to request that the master stop the
current primary bus transaction. This signal is used for target disconnects and is commonly asserted
by target devices which do not support burst data transfers.
P_STOP
P_TRDY
85
83
W12
P11
I/O
I/O
Primary target ready. P_TRDY indicates the ability of the primary bus target to complete the current
data phase of the transaction. A data phase is completed upon a rising edge of P_CLK where both
P_IRDY and P_TRDY are asserted. Until both P_IRDY and P_TRDY are asserted, wait states are
inserted.
2−13
Table 2−10. Secondary PCI System Terminals
TERMINAL
PDV/ GHK/
I/O
DESCRIPTION
NAME
PPM
NO.
ZHK
NO.
42
41
39
38
36
35
33
32
30
29
P1
N6
N2
N1
M6
M3
M1
L5
S_CLKOUT9
S_CLKOUT8
S_CLKOUT7
S_CLKOUT6
S_CLKOUT5
S_CLKOUT4
S_CLKOUT3
S_CLKOUT2
S_CLKOUT1
S_CLKOUT0
Secondary PCI bus clocks. Provide timing for all transactions on the secondary PCI bus. Each
secondary bus device samples all secondary PCI signals at the rising edge of its corresponding
S_CLKOUT input.
O
L2
L1
Secondary PCI bus clock input. This input synchronizes the PCI2050B device to the secondary bus
clocks.
21
J3
J6
I
I
S_CLK
Secondary external arbiter enable. When this signal is high, the secondary external arbiter is enabled.
When the external arbiter is enabled, the PCI2050B S_REQ0 terminal is reconfigured as a secondary
bus grant input to the bridge and S_GNT0 is reconfigured as a secondary bus master request to the
external arbiter on the secondary bus.
S_CFN
23
Secondary PCI reset. S_RST is a logical OR of P_RST and the state of the secondary bus reset bit
(bit 6) of the bridge control register (PCI offset 3Eh, see Section 4.32). S_RST is asynchronous with
respect to the state of the secondary interface CLK signal.
S_RST
22
J5
O
2−14
Table 2−11. Secondary PCI Address and Data Terminals
TERMINAL
PDV/ GHK/
I/O
DESCRIPTION
NAME
PPM
NO.
ZHK
NO.
206
204
203
201
200
198
197
195
192
191
189
188
186
185
183
182
165
164
162
161
159
154
152
150
147
146
144
143
141
140
138
137
A4
E6
B5
A5
C6
B6
A6
C7
E8
F8
B8
A8
F9
S_AD31
S_AD30
S_AD29
S_AD28
S_AD27
S_AD26
S_AD25
S_AD24
S_AD23
S_AD22
S_AD21
S_AD20
S_AD19
S_AD18
S_AD17
S_AD16
S_AD15
S_AD14
S_AD13
S_AD12
S_AD11
S_AD10
S_AD9
C9
F10
E10
E13
B14
A15
B15
E14
F15
F14
F17
F19
G14
G18
G19
H14
H17
H19
J15
Secondary address/data bus. These signals make up the multiplexed PCI address and data bus on
the secondary interface. During the address phase of a secondary bus PCI cycle, S_AD31−S_AD0
contain a 32-bit address or other destination information. During the data phase, S_AD31−S_AD0
contain data.
I/O
S_AD8
S_AD7
S_AD6
S_AD5
S_AD4
S_AD3
S_AD2
S_AD1
S_AD0
Secondary bus commands and byte enables. These signals are multiplexed on the same PCI
terminals. During the address phase of a secondary bus PCI cycle, S_C/BE3−S_C/BE0 define the bus
command. During the data phase, this 4-bit bus is used as byte enables. The byte enables determine
which byte paths of the full 32-bit data bus carry meaningful data. S_C/BE0 applies to byte 0
(S_AD7−S_AD0), S_C/BE1 applies to byte 1 (S_AD15−S_AD8), S_C/BE2 applies to byte 2
(S_AD23−S_AD16), and S_C/BE3 applies to byte 3 (S_AD31−S_AD24).
S_C/BE3
S_C/BE2
S_C/BE1
S_C/BE0
194
180
167
149
B7
A10
F12
G15
I/O
Secondary device select. The bridge asserts S_DEVSEL to claim a PCI cycle as the target device. As
a PCI master on the secondary bus, the bridge monitors S_DEVSEL until a target responds. If no target
responds before time-out occurs, then the bridge terminates the cycle with a master abort.
S_DEVSEL
S_FRAME
175
179
A11
F11
I/O
I/O
Secondary cycle frame. S_FRAME is driven by the master of a secondary bus cycle. S_FRAME is
asserted to indicate that a bus transaction is beginning and data transfers continue while S_FRAME
is asserted. When S_FRAME is deasserted, the secondary bus transaction is in the final data phase.
S_GNT8
S_GNT7
S_GNT6
S_GNT5
S_GNT4
S_GNT3
S_GNT2
S_GNT1
S_GNT0
19
18
17
16
15
14
13
11
10
J1
H1
H2
H3
H5
G1
G2
H6
F1
Secondary bus grant to the bridge. The bridge provides internal arbitration and these signals are used
to grant potential secondary PCI bus masters access to the bus. Ten potential masters (including the
bridge) can be located on the secondary PCI bus.
O
When the internal arbiter is disabled, S_GNT0 is reconfigured as an external secondary bus request
signal for the bridge.
2−15
Table 2−12. Secondary PCI Interface Control Terminals
TERMINAL
PDV/ GHK/
I/O
DESCRIPTION
NAME
PPM
NO.
ZHK
NO.
Secondary initiator ready. S_IRDY indicates the ability of the secondary bus master to complete the
current data phase of the transaction. A data phase is completed on a rising edge of S_CLK where both
S_IRDY and S_TRDY are asserted; until S_IRDY and S_TRDY are asserted, wait states are inserted.
S_IRDY
S_LOCK
177
172
C11
C12
I/O
I/O
Secondary PCI bus lock. S_LOCK is used to lock the secondary bus and gain exclusive access as a
master.
Secondary parity. In all secondary bus read and write cycles, the bridge calculates even parity across
the S_AD and S_C/BE buses. As a master during PCI write cycles, the bridge outputs this parity indicator
with a one-S_CLK delay. As a target during PCI read cycles, the calculated parity is compared to the
master parity indicator. A miscompare can result in a parity error assertion (S_PERR).
S_PAR
168
C13
I/O
I/O
Secondary parity error indicator. S_PERR is driven by a secondary bus PCI device to indicate that
calculated parity does not match S_PAR when enabled through the command register (PCI offset 04h,
see Section 4.3).
171
E12
S_PERR
S_REQ8
S_REQ7
S_REQ6
S_REQ5
S_REQ4
S_REQ3
S_REQ2
S_REQ1
S_REQ0
9
8
7
6
5
4
3
2
207
G5
F2
F3
E1
E2
G6
F5
E3
B4
Secondary PCI bus request signals. The bridge provides internal arbitration, and these signals are used
as inputs from secondary PCI bus masters requesting the bus. Ten potential masters (including the
bridge) can be located on the secondary PCI bus.
I
When the internal arbiter is disabled, the S_REQ0 signal is reconfigured as an external secondary bus
grant for the bridge.
Secondary system error. S_SERR is passed through the primary interface by the bridge if enabled
through the bridge control register (PCI offset 3Eh, see Section 4.32). S_SERR is never asserted by the
bridge.
169
173
176
B13
B12
B11
I
S_SERR
S_STOP
S_TRDY
Secondary cycle stop signal. S_STOP is driven by a PCI target to request that the master stop the current
secondary bus transaction. S_STOP is used for target disconnects and is commonly asserted by target
devices that do not support burst data transfers.
I/O
I/O
Secondary target ready. S_TRDY indicates the ability of the secondary bus target to complete the
current data phase of the transaction. A data phase is completed on a rising edge of S_CLK where both
S_IRDY and S_TRDY are asserted; until S_IRDY and S_TRDY are asserted, wait states are inserted.
Table 2−13. JTAG Interface Terminals
TERMINAL
PDV/ GHK/
I/O
DESCRIPTION
NAME
PPM
NO.
ZHK
NO.
TCK
TDI
133
J19
I
I
JTAG boundary-scan clock. TCK is the clock controlling the JTAG logic.
JTAG serial data in. TDI is the serial input through which JTAG instructions and test data enter the JTAG
interface. The new data on TDI is sampled on the rising edge of TCK.
129
K18
JTAG serial data out. TDO is the serial output through which test instructions and data from the test logic
leave the PCI2050B device.
TDO
TMS
130
132
134
K17
K14
J18
O
I
JTAG test mode select. TMS causes state transitions in the test access port controller.
JTAG TAP reset. When TRST is asserted low, the TAP controller is asynchronously forced to enter a
reset state and initialize the test logic.
TRST
I
2−16
Table 2−14. Miscellaneous Terminals
TERMINAL
PDV/ GHK/
I/O
DESCRIPTION
NAME
PPM
ZHK
NO.
NO.
Bus/power clock control management terminal. When this terminal is tied high and the
PCI2050B device is placed in the D3 power state, it enables the PCI2050B device to place the
secondary bus in the B2 power state. The PCI2050Bdevice disables the secondary clocks and
drives them to 0. When tied low, placing the PCI2050B device in the D3 power state has no
effect on the secondary bus clocks.
BPCCE
44
N5
I
Configure 66 MHz operation. This input-only terminal is used to specify if the PCI2050B device
is capable of running at 66 MHz. If this terminal is tied high, then device can be run at 66 MHz.
If this terminal is tied low, then the PCI2050B device can only function under the 33-MHz PCI
configuration.
CONFIG66
125
L18
I
I
GPIO3/HS_SWITCH
GPIO2
24
25
27
28
K1
K2
K5
K6
General-purpose I/O terminals
GPIO3 is HS_SWITCH in cPCI mode.
GPIO1
GPIO0
HS_SWITCH provides the status of the ejector handle switch to the cPCI logic.
HS_ENUM
HS_LED
MS0
127
128
155
L15
L14
E17
O
O
I
Hot-swap ENUM
Hot-swap LED output
Mode select 0
106
T19
I
Mode select 1
MS1
Primary interface 66 MHz enable. This input-only signal designates the primary interface bus
speed. This terminal must be pulled low for 33-MHz operation on the primary bus. In this case,
S_M66ENA signal will be driven low by the PCI2050B device, forcing the secondary bus to
run at 33 MHz. For 66-MHz operation, this terminal must be pulled high.
P_M66ENA
102
W16
I
Secondary 66 MHz enable. This signal designates the secondary bus speed. If the
P_M66ENA is driven low, then this signal is driven low by the PCI2050B device, forcing
secondary bus to run at 33 MHz. If the primary bus is running at 66 MHz (P_M66ENA is high),
then S_M66ENA is an input and must be externally pulled high for the secondary bus to
operate at 66 MHz or pulled low for secondary bus to operate at 33 MHz. Note that S_M66ENA
is an open drained output.
S_M66ENA
153
E18
I/O
Table 2−15. Power Supply Terminals
TERMINAL
PDV/PPM NO.
DESCRIPTION
GHK NO.
NAME
12, 20, 31, 37, 48, 52, 54,
59, 66, 72, 78, 86, 94, 100,
104, 111, 117, 123, 136,
142, 148, 156, 158, 160,
166, 174, 181, 187, 193,
199, 205
A7, A12, A14, B10, C5,
C15, D19, E7, E9, F13,
F18, G3, H15, J2, J14, L6,
Device ground terminals
M5, M19, N17, P5, R8,
R10, R14, R19, U1, U5, U9,
U12, V6, V14
GND
1, 26, 34, 40, 51, 53, 56, 62, A3, A9, A13, A16, C8, C14,
69, 75, 81, 91, 97, 103, 105, D2, E11, E19, F6, F7, M15,
108, 114, 120, 131, 139,
145, 151, 157, 163, 170,
178, 184, 190, 196, 202,
208
G17, H18, K3, K15, M2, N3,
N15, P7, P8, P15, T2, T18,
U13, V11, V16, W4, W8,
W10, W15
V
CC
Power-supply terminal for core logic (3.3 V)
Primary bus-signaling environment supply. P_V
protection circuitry on primary bus I/O signals.
is used in
CCP
(1)
CCP
P_V
124
135
L19
J17
Secondary bus-signaling environment supply. S_V
protection circuitry on secondary bus I/O signals.
is used in
CCP
(1)
S_V
CCP
NOTE 1: TI recommends that P_V
CCP
and S_V
CCP
be powered up first before applying power to V
.
CC
2−17
2−18
3 Feature/Protocol Descriptions
The following sections give an overview of the PCI2050B PCI-to-PCI bridge features and functionality. Figure 3−1
shows a simplified block diagram of a typical system implementation using the PCI2050B bridge.
Host Bus
Memory
CPU
Host
PCI
PCI
Bridge
Device
Device
PCI Bus 0
PCI Option Card
PCI Option Card
PCI2050B
PCI Bus 2
PCI Bus 1
PCI
Device
PCI
Device
(Option)
PCI2050B
PCI Option Slot
Figure 3−1. System Block Diagram
3.1 Introduction to the PCI2050B Bridge
The PCI2050B device is a bridge between two PCI buses and is compliant with both the PCI Local Bus Specification
and the PCI-to-PCI Bridge Specification. The bridge supports two 32-bit PCI buses operating at a maximum of
66 MHz. The primary and secondary buses operate independently in either 3.3-V or 5-V signaling environment. The
core logic of the bridge, however, is powered at 3.3 V to reduce power consumption.
For PCI2050B, the FIFO size is 32 DW for delayed responses (3 each direction) 64 DW posted write and delayed
request FIFO (1 each direction).
Host software interacts with the bridge through internal registers. These internal registers provide the standard PCI
status and control for both the primary and secondary buses. Many vendor-specific features that exist in the TI
extension register set are included in the bridge. The PCI configuration header of the bridge is only accessible from
the primary PCI interface.
The bridge provides internal arbitration for the nine possible secondary bus masters, and provides each with a
dedicated active low request/grant pair (REQ/GNT). The arbiter features a two-tier rotational scheme with the
PCI2050B bridge defaulting to the highest priority tier. The PCI2050B device also supports external arbitration.
Upon system power up, power-on self-test (POST) software configures the bridge according to the devices that exist
on subordinate buses, and enables performance-enhancing features of the PCI2050B bridge. In a typical system,
this is the only communication with the bridge internal register set.
3−1
3.1.1 Write Combining
The PCI2050B bridge supports write combining for upstream and downstream transactions. This feature combines
separate sequential memory write transactions into a single burst transaction. This feature can only be used if the
address of the next memory write transaction is the next sequential address after the address of the last double word
of the previous memory transaction. For example, if the current memory transaction ends at address X and next
memory transaction starts at address X+1, then the PCI2050B bridge combines both transactions into a single
transaction.
The write combining feature of the PCI2050B bridge is enabled by default on power on reset. It can also be disabled
by setting bit 0 of the TI diagnostics register at offset F0h to 1.
3.1.2 66-MHz Operation
The PCI2050B bridge supports two 32-bit PCI buses operating at a maximum frequency of 66 MHz. The 66-MHz
clocking requires three terminals: P_M66ENA, S_M66ENA, and CONFIG66. To enable 66-MHz operation, the
CONFIG66 terminal must be tied high on the board. This sets the 66-MHz capable bit in the primary and secondary
status register. The P_M66ENA and S_M66ENA must not be pulled high unless CONFIG66 is also high.
The P_M66ENA and S_M66ENA signals indicate whether the primary or secondary interfaces are working at
66 MHz. This information is needed to control the frequency of the secondary bus. Note that PCI Local Bus
Specification (Revision 2.2) restricts clock frequency changes above 33 MHz during reset only.
The following frequency combinations are supported on the primary and secondary buses in the PCI2050B device:
•
•
•
66-MHz primary bus, 66-MHz secondary bus
66-MHz primary bus, 33-MHz secondary bus
33-MHz primary bus, 33-MHz secondary bus
The PCI2050B bridge does not support 33-MHz primary/66-MHz secondary bus operation. If CONFIG66 is high and
P_M66ENA is low, then the PCI2050B bridge pulls down S_M66ENA to indicate that secondary bus is running at
33 MHz.
The PCI2050B bridge generates the clock signals S_CLKOUT[9:0] for the secondary bus devices and its own
interface. It divides the P_CLK by 2 to generate the secondary clock outputs whenever the primary bus is running
at 66 MHz and secondary bus is running at 33 MHz. The bridge detects this condition by polling P_M66ENA and
S_M66ENA.
3.2 PCI Commands
The bridge responds to PCI bus cycles as a PCI target device based on internal register settings and on the decoding
of each address phase. Table 3−1 lists the valid PCI bus cycles and their encoding on the command/byte enable
(C/BE) bus during the address phase of a bus cycle.
3−2
Table 3−1. PCI Command Definitions
COMMAND
Interrupt acknowledge
Special cycle
C/BE3−C/BE0
0000
0001
0010
0011
I/O read
I/O write
0100
0101
0110
Reserved
Reserved
Memory read
0111
Memory write
1000
1001
1010
1011
Reserved
Reserved
Configuration read
Configuration write
Memory read multiple
Dual address cycle
Memory read line
Memory write and invalidate
1100
1101
1110
1111
The bridge never responds as a PCI target to the interrupt acknowledge, special cycle, or reserved commands. The
bridge does, however, initiate special cycles on both interfaces when a type 1 configuration cycle issues the special
cycle request. The remaining PCI commands address either memory, I/O, or configuration space. The bridge accepts
PCI cycles by asserting DEVSEL as a medium-speed device, i.e., DEVSEL is asserted two clock cycles after the
address phase.
The PCI2050B bridge converts memory write and invalidate commands to memory write commands when forwarding
transactions from either the primary or secondary side of the bridge if the bridge cannot guarantee that an entire cache
line will be delivered.
3.3 Configuration Cycles
PCI Local Bus Specification defines two types of PCI configuration read and write cycles: type 0 and type 1. The
bridge decodes each type differently. Type 0 configuration cycles are intended for devices on the primary bus, while
type 1 configuration cycles are intended for devices on some hierarchically subordinate bus. The difference between
these two types of cycles is the encoding of the primary PCI (P_AD) bus during the address phase of the cycle.
Figure 3−2 shows the P_AD bus encoding during the address phase of a type 0 configuration cycle. The 6-bit register
number field represents an 8-bit address with the two lower bits masked to 0, indicating a doubleword boundary. This
results in a 256-byte configuration address space per function per device. Individual byte accesses may be selected
within a doubleword by using the P_C/BE signals during the data phase of the cycle.
31
11
10
8
7
2
1
0
0
0
Function
Number
Register
Number
Reserved
Figure 3−2. PCI AD31−AD0 During Address Phase of a Type 0 Configuration Cycle
The bridge claims only type 0 configuration cycles when its P_IDSEL terminal is asserted during the address phase
of the cycle and the PCI function number encoded in the cycle is 0. If the function number is 1 or greater, then the
bridge does not recognize the configuration command. In this case, the bridge does not assert P_DEVSEL, and the
configuration transaction results in a master abort. The bridge services valid type 0 configuration read or write cycles
by accessing internal registers from the bridge configuration header (see Table 4−1).
3−3
Because type 1 configuration cycles are issued to devices on subordinate buses, the bridge claims type 1 cycles
based on the bus number of the destination bus. The P_AD bus encoding during the address phase of a type 1 cycle
is shown in Figure 3−3. The device number and bus number fields define the destination bus and device for the cycle.
31
24
23
16
15
11
10
8
7
2
1
0
0
1
Device
Number
Function
Number
Register
Number
Reserved
Bus Number
Figure 3−3. PCI AD31−AD0 During Address Phase of a Type 1 Configuration Cycle
Several bridge configuration registers shown in Table 4−1 are significant when decoding and claiming type 1
configuration cycles. The destination bus number encoded on the P_AD bus is compared to the values programmed
in the bridge configuration registers 18h, 19h, and 1Ah, which are the primary bus number, secondary bus number,
and subordinate bus number registers, respectively. These registers default to 00h and are programmed by host
software to reflect the bus hierarchy in the system (see Figure 3−4 for an example of a system bus hierarchy and how
the PCI2050B bus number registers would be programmed in this case).
PCI Bus 0
PCI2050B
Primary Bus
Secondary Bus
Subordinate Bus
PCI2050B
Primary Bus
Secondary Bus
Subordinate Bus
00h
01h
02h
00h
03h
03h
PCI Bus 1
PCI Bus 3
PCI2050B
Primary Bus
Secondary Bus
Subordinate Bus
01h
02h
02h
PCI Bus 2
Figure 3−4. Bus Hierarchy and Numbering
When the PCI2050B bridge claims a type 1 configuration cycle that has a bus number equal to its secondary bus
number, the PCI2050B bridge converts the type 1 configuration cycle to a type 0 configuration cycle and asserts the
proper S_AD line as the IDSEL (see Table 3−2). All other type 1 transactions that access a bus number greater than
the bridge secondary bus number but less than or equal to its subordinate bus number are forwarded as type 1
configuration cycles.
3−4
Table 3−2. PCI S_AD31−S_AD16 During the Address
Phase of a Type 0 Configuration Cycle
SECONDARY IDSEL
S_AD31−S_AD16
S_AD
ASSERTED
DEVICE
NUMBER
0h
1h
0000 0000 0000 0001
0000 0000 0000 0010
0000 0000 0000 0100
0000 0000 0000 1000
0000 0000 0001 0000
0000 0000 0010 0000
0000 0000 0100 0000
0000 0000 1000 0000
0000 0001 0000 0000
0000 0010 0000 0000
0000 0100 0000 0000
0000 1000 0000 0000
0001 0000 0000 0000
0010 0000 0000 0000
0100 0000 0000 0000
1000 0000 0000 0000
0000 0000 0000 0000
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
−
2h
3h
4h
5h
6h
7h
8h
9h
Ah
Bh
Ch
Dh
Eh
Fh
10h−1Eh
3.4 Special Cycle Generation
The bridge is designed to generate special cycles on both buses through a type 1 cycle conversion. During a type 1
configuration cycle, if the bus number field matches the bridge secondary bus number, the device number field is 1Fh,
and the function number field is 07h, then the bridge generates a special cycle on the secondary bus with a message
that matches the type 1 configuration cycle data. If the bus number is a subordinate bus and not the secondary, then
the bridge passes the type 1 special cycle request through to the secondary interface along with the proper message.
Special cycles are never passed through the bridge. Type 1 configuration cycles with a special cycle request can
propagate in both directions.
3.5 Secondary Clocks
The PCI2050B bridge provides 10 secondary clock outputs (S_CLKOUT[0:9]). Nine are provided for clocking
secondary devices. The tenth clock must be routed back into the PCI2050B S_CLK input to ensure all secondary bus
devices see the same clock. Figure 3−5 is a block diagram of the secondary clock function.
3−5
S_CLK
PCI2050B
S_CLKOUT9
S_CLKOUT8
PCI
Device
PCI
Device
S_CLKOUT2
S_CLKOUT1
S_CLKOUT0
PCI
Device
PCI
Device
Figure 3−5. Secondary Clock Block Diagram
3.6 Bus Arbitration
The PCI2050B bridge implements bus request (P_REQ) and bus grant (P_GNT) terminals for primary PCI bus
arbitration. Nine secondary bus requests and nine secondary bus grants are provided on the secondary of the
PCI2050B bridge. Ten potential initiators, including the bridge, can be located on the secondary bus. The PCI2050B
bridge provides a two-tier arbitration scheme on the secondary bus for priority bus-master handling.
The two-tier arbitration scheme improves performance in systems in which master devices do not all require the same
bandwidth. Any master that requires frequent use of the bus can be programmed to be in the higher priority tier.
3.6.1 Primary Bus Arbitration
The PCI2050B bridge, acting as an initiator on the primary bus, asserts P_REQ when forwarding transactions
upstream to the primary bus. If a target disconnect, a target retry, or a target abort is received in response to a
transaction initiated on the primary bus by the PCI2050B bridge, then the device deasserts P_REQ for two PCI clock
cycles.
When the primary bus arbiter asserts P_GNT in response to a P_REQ from the PCI2050B bridge, the device initiates
a transaction on the primary bus during the next PCI clock cycle after the primary bus is sampled idle.
When P_REQ is not asserted and the primary bus arbiter asserts P_GNT to the PCI2050B bridge, the device
responds by parking the P_AD31−P_AD0 bus, the C/BE3−C/BE0 bus, and primary parity (P_PAR) by driving them
to valid logic levels. If the PCI2050B bridge is parking the primary bus and wants to initiate a transaction on the bus,
then it can start the transaction on the next PCI clock by asserting the primary cycle frame (P_FRAME) while P_GNT
is still asserted. If P_GNT is deasserted, then the bridge must rearbitrate for the bus to initiate a transaction.
3.6.2 Internal Secondary Bus Arbitration
S_CFN controls the state of the secondary internal arbiter. The internal arbiter can be enabled by pulling S_CFN low
or disabled by pulling S_CFN high. The PCI2050B bridge provides nine secondary bus request terminals and nine
3−6
secondary bus grant terminals. Including the bridge, there are a total of ten potential secondary bus masters. These
request and grant signals are connected to the internal arbiter. When an external arbiter is implemented,
S_REQ8−S_REQ1 and S_GNT8−S_GNT1 are placed in a high-impedance mode.
3.6.3 External Secondary Bus Arbitration
An external secondary bus arbiter can be used instead of the PCI2050B internal bus arbiter. When using an external
arbiter, the PCI2050B internal arbiter must be disabled by pulling S_CFN high.
When an external secondary bus arbiter is used, the PCI2050B bridge internally reconfigures the S_REQ0 and
S_GNT0 signals so that S_REQ0 becomes the secondary bus grant for the bridge and S_GNT0 becomes the
secondary bus request for the bridge. This is done because S_REQ0 is an input and can thus provide the grant input
to the bridge, and S_GNT0 is an output and can thus provide the request output from the bridge.
When an external arbiter is used, all unused secondary bus grant outputs (S_GNT8−S_GNT1) are placed in a high
impedance mode. Any unused secondary bus request inputs (S_REQ8−S_REQ1) must be pulled high to prevent
the inputs from oscillating.
3.7 Decode Options
The PCI2050B bridge supports positive decoding on the primary interface and negative decoding on the secondary
interface. Positive decoding is a method of address decoding in which a device responds only to accesses within an
assigned address range. Negative decoding is a method of address decoding in which a device responds only to
accesses outside of an assigned address range.
3.8 System Error Handling
The PCI2050B bridge can be configured to signal a system error (SERR) for a variety of conditions. The P_SERR
event disable register (offset 64h, see Section 5.4) and the P_SERR status register (offset 6Ah, see Section 5.9)
provide control and status bits for each condition for which the bridge can signal SERR. These individual bits enable
SERR reporting for both downstream and upstream transactions.
By default, the PCI2050B bridge will not signal SERR. If the PCI2050B bridge is configured to signal SERR by setting
bit 8 in the command register (offset 04h, see Section 4.3), then the bridge signals SERR if any of the error conditions
in the P_SERR event disable register occur and that condition is enabled. By default, all error conditions are enabled
in the P_SERR event disable register. When the bridge signals SERR, bit 14 in the secondary status register (offset
1Eh, see Section 4.19) is set.
3.8.1 Posted Write Parity Error
If bit 1 in the P_SERR event disable register (offset 64h, see Section 5.4) is 0, then parity errors on the target bus
during a posted write are passed to the initiating bus as a SERR. When this occurs, bit 1 of the P_SERR status register
(offset 6Ah, see Section 5.9) is set. The status bit is cleared by writing a 1.
3.8.2 Posted Write Time-Out
If bit 2 in the P_SERR event disable register (offset 64h, see Section 5.4) is 0 and the retry timer expires while
attempting to complete a posted write, then the PCI2050B bridge signals SERR on the initiating bus. When this
occurs, bit 2 of the P_SERR status register (offset 6Ah, see Section 5.9) is set. The status bit is cleared by writing
a 1.
3.8.3 Target Abort on Posted Writes
If bit 3 in the P_SERR event disable register (offset 64h, see Section 5.4) is 0 and the bridge receives a target abort
during a posted write transaction, then the PCI2050B bridge signals SERR on the initiating bus. When this occurs,
bit 3 of the P_SERR status register (offset 6Ah, see Section 5.9) is set. The status bit is cleared by writing a 1.
3−7
3.8.4 Master Abort on Posted Writes
If bit 4 in the P_SERR event disable register (PCI offset 64h, see Section 5.4) is 0 and a posted write transaction
results in a master abort, then the PCI2050B bridge signals SERR on the initiating bus. When this occurs, bit 4 of
the P_SERR status register (PCI offset 6Ah, see Section 5.9) is set. The status bit is cleared by writing a 1.
3.8.5 Master Delayed Write Time-Out
If bit 5 in the P_SERR event disable register (PCI offset 64h, see Section 5.4) is 0 and the retry timer expires while
attempting to complete a delayed write, then the PCI2050B bridge signals SERR on the initiating bus. When this
occurs, bit 5 of the P_SERR status register (PCI offset 6Ah, see Section 5.9) is set. The status bit is cleared by writing
a 1.
3.8.6 Master Delayed Read Time-Out
If bit 6 in the P_SERR event disable register (offset 64h, see Section 5.4) is 0 and the retry timer expires while
attempting to complete a delayed read, then the PCI2050B bridge signals SERR on the initiating bus. When this
occurs, bit 6 of the P_SERR status register (offset 6Ah, see Section 5.9) is set. The status bit is cleared by writing
a 1.
3.8.7 Secondary SERR
The PCI2050B bridge passes SERR from the secondary bus to the primary bus if it is enabled for SERR response,
that is, if bit 8 in the command register (PCI offset 04h, see Section 4.3) is set, and if bit 1 in the bridge control register
(PCI offset 3Eh, see Section 4.32) is set.
3.9 Parity Handling and Parity Error Reporting
When forwarding transactions, the PCI2050B bridge attempts to pass the data parity condition from one interface
to the other unchanged, whenever possible, to allow the master and target devices to handle the error condition.
3.9.1 Address Parity Error
If the parity error response bit (bit 6) in the command register (PCI offset 04h, see Section 4.3) is set, then the
PCI2050B bridge signals SERR on address parity errors and target abort transactions.
3.9.2 Data Parity Error
If the parity error response bit (bit 6) in the command register (PCI offset 04h, see Section 4.3) is set, then the
PCI2050B bridge signals PERR when it receives bad data. When the bridge detects bad parity, bit 15 (detected parity
error) in the status register (PCI offset 06h, see Section 4.4) is set.
If the bridge is configured to respond to parity errors via bit 6 in the command register (PCI offset 04h, see Section 4.3),
then bit 8 (data parity error detected) in the status register (PCI offset 06h, see Section 4.4) is set when the bridge
detects bad parity. The data parity error detected bit is also set when the bridge, as a bus master, asserts PERR or
detects PERR.
3.10 Master and Target Abort Handling
If the PCI2050B bridge receives a target abort during a write burst, then it signals target abort back on the initiator
bus. If it receives a target abort during a read burst, then it provides all of the valid data on the initiator bus and
disconnects. Target aborts for posted and nonposted transactions are reported as specified in the PCI-to-PCI Bridge
Specification.
Master aborts for posted and nonposted transactions are reported as specified in the PCI-to-PCI Bridge Specification.
If a transaction is attempted on the primary bus after a secondary reset is asserted, then the PCI2050B bridge follows
bit 5 (master abort mode) in the bridge control register (PCI offset 3Eh, see Section 4.32) for reporting errors.
3−8
3.11 Discard Timer
The PCI2050B bridge is free to discard the data or status of a delayed transaction that was completed with a delayed
10
15
transaction termination when a bus master has not repeated the request within 2 or 2 PCI clocks (approximately
15
30 µs and 993 µs, respectively). The PCI Local Bus Specification recommends that a bridge wait 2 PCI clocks
before discarding the transaction data or status.
The PCI2050B bridge implements a discard timer for use in delayed transactions. After a delayed transaction is
completed on the destination bus, the bridge may discard it under two conditions. The first condition occurs when
a read transaction is made to a region of memory that is inside a defined prefetchable memory region, or when the
command is a memory read line or a memory read multiple, implying that the memory region is prefetchable. The
other condition occurs when the master originating the transaction (either a read or a write, prefetchable or
10
15
nonprefetchable) has not retried the transaction within 2 or 2 clocks. The number of clocks is tracked by a timer
referred to as the discard timer. When the discard timer expires, the bridge is required to discard the data. The
15
10
PCI2050B default value for the discard timer is 2 clocks; however, this value can be set to 2 clocks by setting bit
9 in the bridge control register (offset 3Eh, see Section 4.32). For more information on the discard timer, see error
conditions in the PCI Local Bus Specification.
3.12 Delayed Transactions
The bridge supports delayed transactions as defined in PCI Local Bus Specification. A target must be able to complete
the initial data phase in 16 PCI clocks or less from the assertion of the cycle frame (FRAME), and subsequent data
phases must complete in eight PCI clocks or less. A delayed transaction consists of three phases:
•
•
•
An initiator device issues a request.
The target completes the request on the destination bus and signals the completion to the initiator.
The initiator completes the request on the originating bus.
If the bridge is the target of a PCI transaction and it must access a slow device to write or read the requested data,
and the transaction takes longer than 16 clocks, then the bridge must latch the address, the command, and the byte
enables, and then issue a retry to the initiator. The initiator must end the transaction without any transfer of data and
is required to retry the transaction later using the same address, command, and byte enables. This is the first phase
of the delayed transaction.
During the second phase, if the transaction is a read cycle, the bridge fetches the requested data on the destination
bus, stores it internally, and obtains the completion status, thus completing the transaction on the destination bus.
If it is a write transaction, then the bridge writes the data and obtains the completion status, thus completing the
transaction on the destination bus. The bridge stores the completion status until the master on the initiating bus retries
the initial request.
During the third phase, the initiator rearbitrates for the bus. When the bridge sees the initiator retry the transaction,
it compares the second request to the first request. If the address, command, and byte enables match the values
latched in the first request, then the completion status (and data if the request was a read) is transferred to the initiator.
At this point, the delayed transaction is complete. If the second request from the initiator does not match the first
request exactly, then the bridge issues another retry to the initiator.
The PCI supports up to three delayed transactions in each direction at any given time.
3.13 Mode Selection
Table 3−3 shows the mode selection via MS0 (PDV/PPM terminal 155, GHK/ZHK terminal E17) and MS1 (PDV/PPM
terminal 106, GHK/ZHK terminal T19).
3−9
Table 3−3. Configuration via MS0 and MS1
MS1
MODE
MS0
0
0
CompactPCI hot-swap friendly
PCI Bus Power Management Interface Specification (Revision 1.1)
HS_SWITCH/GPIO(3) functions as HS_SWITCH
0
1
1
CompactPCI hot-swap disabled
PCI Bus Power Management Interface Specification (Revision 1.1)
HS_SWITCH/GPIO(3) functions as GPIO(3)
X
Intel compatible
No cPCI hot swap
PCI Bus Power Management Interface Specification (Revision 1.0)
3.14 CompactPCI Hot-Swap Support
The PCI2050B bridge is hot-swap friendly silicon that supports all of the hot-swap capable features, contains support
for software control, and integrates circuitry required by the PICMG CompactPCI Hot-Swap Specification. To be
hot-swap capable, the PCI2050B bridge supports the following:
•
•
•
•
•
•
•
•
Compliance with PCI Local Bus Specification
Tolerance of V from early power
CC
Asynchronous reset
Tolerance of precharge voltage
I/O buffers that meet modified V/I requirements
Limited I/O terminal voltage at precharge voltage
Hot-swap control and status programming via extended PCI capabilities linked list
Hot-swap terminals: HS_ENUM, HS_SWITCH, and HS_LED
cPCI hot-swap defines a process for installing and removing PCI boards without adversely affecting a running system.
The PCI2050B bridge provides this functionality such that it can be implemented on a board that can be removed
and inserted in a hot-swap system.
The PCI2050B bridge provides three terminals to support hot-swap when configured to be in hot-swap mode:
HS_ENUM (output), HS_SWITCH (input), and HS_LED (output). The HS_ENUM output indicates to the system that
an insertion event occurred or that a removal event is about to occur. The HS_SWITCH input indicates the state of
a board ejector handle, and the HS_LED output lights a blue LED to signal insertion- and removal-ready status.
3−10
3.15 JTAG Support
The PCI2050B bridge implements a JTAG test port based on IEEE Standard 1149.1, IEEE Standard Test Access Port
and Boundary-Scan Architecture. The JTAG test port consists of the following:
•
•
•
•
•
A 5-wire test access port
A test access port controller
An instruction register
A bypass register
A boundary-scan register
3.15.1 Test Port Instructions
The PCI2050B bridge supports the following JTAG instructions:
•
•
•
EXTEST, BYPASS, and SAMPLE
HIGHZ and CLAMP
Private (various private instructions used by TI for test purposes)
Table 3−4 lists and describes the different test port instructions, and gives the op code of each one. The information
in Table 3−5 is for implementation of boundary scan interface signals to permit in-circuit testing.
Table 3−4. JTAG Instructions and Op Codes
INSTRUCTION
EXTEST
SAMPLE
CLAMP
OP CODE
00000
00001
00100
00101
11111
DESCRIPTION
External test: drives terminals from the boundary scan register
Sample I/O terminals
Drives terminals from the boundary scan register and selects the bypass register for shifts
Puts all outputs and I/O terminals except for the TDO terminal in a high-impedance state
Selects the bypass register for shifts
HIGHZ
BYPASS
Table 3−5. Boundary Scan Terminal Order
BOUNDARY SCAN
REGISTER NUMBER
PDV/PPM TERMINAL
NUMBER
GHK/ZHK
TERMINAL NUMBER
TERMINAL
NAME
GROUP DISABLE
REGISTER
BOUNDARY-SCAN
CELL TYPE
0
1
137
138
140
141
143
144
146
147
149
150
152
153
154
155
158
161
162
164
165
−
J15
H19
H17
H14
G19
G18
G14
F19
G15
F17
F14
E18
F15
E17
E14
B15
A15
B14
E13
−
S_AD0
S_AD1
S_AD2
S_AD3
S_AD4
S_AD5
S_AD6
S_AD7
S_C/BE0
S_AD8
S_AD9
S_M66ENA
S_AD10
MS0
19
19
19
19
19
19
19
19
19
19
19
19
19
−
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Input
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
S_AD11
S_AD12
S_AD13
S_AD14
S_AD15
−
19
19
19
19
19
−
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Control
3−11
Table 3−5. Boundary Scan Terminal Order (Continued)
BOUNDARY SCAN
REGISTER NUMBER
PDV/PPM TERMINAL
NUMBER
GHK/ZHK
TERMINAL NUMBER
TERMINAL
NAME
GROUP DISABLE
REGISTER
BOUNDARY-SCAN
CELL TYPE
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
167
168
169
171
172
173
−
F12
C13
B13
E12
C12
B12
−
S_C/BE1
S_PAR
19
19
−
Bidirectional
Bidirectional
Input
S_SERR
S_PERR
S_LOCK
S_STOP
−
26
26
26
−
Bidirectional
Bidirectional
Bidirectional
Control
175
176
177
179
180
182
183
185
186
188
189
191
192
194
195
197
198
200
201
203
204
−
A11
B11
C11
F11
A10
E10
F10
C9
F9
S_DEVSEL
S_TRDY
S_IRDY
S_FRAME
S_C/BE2
S_AD16
S_AD17
S_AD18
S_AD19
S_AD20
S_AD21
S_AD22
S_AD23
S_C/BE3
S_AD24
S_AD25
S_AD26
S_AD27
S_AD28
S_AD29
S_AD30
−
26
26
26
26
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
−
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Control
A8
B8
F8
E8
B7
C7
A6
B6
C6
A5
B5
E6
−
206
207
2
A4
S_AD31
S_REQ0
S_REQ1
S_REQ2
S_REQ3
S_REQ4
S_REQ5
S_REQ6
S_REQ7
S_REQ8
S_GNT0
S_GNT1
−
48
−
Bidirectional
Input
B4
E3
−
Input
3
F5
−
Input
4
G6
E2
−
Input
5
−
Input
6
E1
−
Input
7
F3
−
Input
8
F2
−
Input
9
G5
F1
−
Input
10
61
61
−
Output
11
H6
−
Output
−
Control
3−12
Table 3−5. Boundary Scan Terminal Order (Continued)
BOUNDARY SCAN
REGISTER NUMBER
PDV/PPM TERMINAL
NUMBER
GHK/ZHK
TERMINAL NUMBER
TERMINAL
NAME
GROUP DISABLE
REGISTER
BOUNDARY-SCAN
CELL TYPE
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
13
14
15
16
17
18
19
21
22
23
24
25
27
28
29
30
−
G2
G1
H5
H3
H2
H1
J1
S_GNT2
S_GNT3
S_GNT4
S_GNT5
S_GNT6
S_GNT7
S_GNT8
S_CLK
61
61
61
61
61
61
61
−
Output
Output
Output
Output
Output
Output
Output
J3
Input
J5
S_RST
78
−
Output
J6
S_CFN
Input
K1
K2
K5
K6
L1
GPIO3
78
78
78
78
−
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Output
GPIO2
GPIO1
GPIO0
S_CLKOUT0
S_CLKOUT1
−
L2
−
Output
−
−
Output
32
33
35
36
38
39
41
42
43
44
45
46
47
−
L5
S_CLKOUT2
S_CLKOUT3
S_CLKOUT4
S_CLKOUT5
S_CLKOUT6
S_CLKOUT7
S_CLKOUT8
S_CLKOUT9
P_RST
−
Output
M1
M3
M6
N1
N2
N6
P1
P2
N5
P3
R1
P6
−
−
Output
−
Output
−
Output
−
Output
−
Output
−
Output
−
Output
−
Input
BPCCE
−
Input
P_CLK
−
Input
P_GNT
−
Input
P_REQ
92
−
Output
−
Control
49
50
55
57
58
60
61
63
64
65
67
68
R3
T1
R6
W5
U6
R7
W6
U7
V7
W7
U8
V8
P_AD31
P_AD30
P_AD29
P_AD28
P_AD27
P_AD26
P_AD25
P_AD24
P_C/BE3
P_IDSEL
P_AD23
P_AD22
111
111
111
111
111
111
111
111
111
−
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Input
111
111
Bidirectional
Bidirectional
3−13
Table 3−5. Boundary Scan Terminal Order (Continued)
BOUNDARY SCAN
REGISTER NUMBER
PDV/PPM TERMINAL
NUMBER
GHK/ZHK
TERMINAL NUMBER
TERMINAL
NAME
GROUP DISABLE
REGISTER
BOUNDARY-SCAN
CELL TYPE
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
70
71
W9
V9
P_AD21
P_AD20
P_AD19
P_AD18
P_AD17
P_AD16
−
111
111
111
111
111
111
−
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Control
73
R9
74
P9
76
V10
U10
−
77
−
79
P10
W11
U11
P11
R11
W12
−
P_C/BE2
P_FRAME
P_IRDY
P_TRDY
P_DEVSEL
P_STOP
−
111
118
118
118
118
118
−
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Control
80
82
83
84
85
−
87
P12
R12
W13
V13
P13
W14
R13
U14
P14
V15
U15
T19
R17
N14
R18
P17
P18
P19
M14
N18
N19
M17
M18
−
P_LOCK
P_PERR
P_SERR
P_PAR
P_C/BE1
P_AD15
P_AD14
P_AD13
P_AD12
P_AD11
P_AD10
MS1
118
118
142
142
142
142
142
142
142
142
142
−
Input
88
Bidirectional
Output
89
90
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Input
92
93
95
96
98
99
101
106
107
109
110
112
113
115
116
118
119
121
122
−
P_AD9
P_AD8
P_C/BE0
P_AD7
P_AD6
P_AD5
P_AD4
P_AD3
P_AD2
P_AD1
P_AD0
−
142
142
142
142
142
142
142
142
142
142
142
−
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
−
126
−
L17
−
MSK_IN
−
−
Input
−
Control
127
128
L15
L14
HS_ENUM
HS_LED
144
144
Output
Output
3−14
3.16 GPIO Interface
The PCI2050B bridge implements a four-terminal general-purpose I/O interface. Besides functioning as a
general-purpose I/O interface, the GPIO terminals can read in the secondary clock mask and stop the bridge from
accepting I/O and memory transactions.
3.16.1 Secondary Clock Mask
The PCI2050B bridge uses GPIO0, GPIO2, and MSK_IN to shift in the secondary clock mask from an external shift
register. A secondary clock mask timing diagram is shown in Figure 3−6. Table 3−6 lists the format for clock mask
data.
MSK_IN
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
GPIO2
GPIO0
P_RST
S_RST
Figure 3−6. Clock Mask Read Timing After Reset
Table 3−6. Clock Mask Data Format
BIT
[0:1]
[2:3]
[4:5]
[6:7]
8
CLOCK
S_CLKOUT0
S_CLKOUT1
S_CLKOUT2
S_CLKOUT3
S_CLKOUT4
9
S_CLKOUT5
10
S_CLKOUT6
11
S_CLKOUT7
12
S_CLKOUT8
13
S_CLKOUT9 (PCI2050B S_CLK input)
Reserved
[14:15]
3.16.2 Transaction Forwarding Control
The PCI2050B bridge will stop forwarding I/O and memory transactions if bit 5 of the chip control register (offset 40h,
see Section 5.1) is set to 1 and GPIO3 is driven high. The bridge completes all queued posted writes and delayed
requests, but delayed completions are not returned until GPIO3 is driven low and transaction forwarding is resumed.
The bridge continues to accept configuration cycles in this mode. This feature is not available when in CompactPCI
hot-swap mode because GPIO3 is used as the HS_SWITCH input in this mode.
3−15
3.17 PCI Power Management
The PCI Power Management Specification establishes the infrastructure required to let the operating system control
the power of PCI functions. This is done by defining a standard PCI interface and operations to manage the power
of PCI functions on the bus. The PCI bus and the PCI functions can be assigned one of four software visible power
management states, which result in varying levels of power savings.
The four power management states of PCI functions are D0—fully on state, D1 and D2—intermediate states, and
D3—off state. Similarly, bus power states of the PCI bus are B0−B3. The bus power states B0−B3 are derived from
the device power state of the originating PCI2050B device.
For the operating system to manage the device power states on the PCI bus, the PCI function supports four power
management operations:
•
•
•
•
Capabilities reporting
Power status reporting
Setting the power state
System wake-up
The operating system identifies the capabilities of the PCI function by traversing the new capabilities list. The
presence of the new capabilities list is indicated by bit 4 in the status register (offset 06h, see Section 4.4) which
provides access to the capabilities list.
3.17.1 Behavior in Low-Power States
The PCI2050B bridge supports D0, D1, D2, and D3
power states when in TI mode. The PCI2050B bridge only
hot
supports D0 and D3 power states when in Intel mode. The PCI2050B bridge is fully functional only in D0 state. In the
lower power states, the bridge does not accept any memory or I/O transactions. These transactions are aborted by
the master. The bridge accepts type 0 configuration cycles in all power states except D3
. The bridge also accepts
cold
type 1 configuration cycles but does not pass these cycles to the secondary bus in any of the lower power states.
Type 1 configuration writes are discarded and reads return all 1s. All error reporting is done in the low power states.
When in D2 and D3
states, the bridge turns off all secondary clocks for further power savings.
hot
When going from D3
to D0, an internal reset is generated. This reset initializes all PCI configuration registers to
hot
their default values. The TI specific registers (40h − FFh) are not reset. Power management registers also are not
reset.
3−16
4 Bridge Configuration Header
The PCI2050B bridge is a single-function PCI device. The configuration header is in compliance with the PCI-to-PCI
Bridge Specification (Revision 1.1). Table 4−1 shows the PCI configuration header, which includes the predefined
portion of the bridge configuration space. The PCI configuration offset is shown in the right column under the OFFSET
heading.
Table 4−1. Bridge Configuration Header
REGISTER NAME
OFFSET
00h
Device ID
Status
Vendor ID
Command
04h
Class code
Header type
Revision ID
08h
BIST
Primary latency timer
Cache line size
0Ch
Base address 0
Base address 1
10h
14h
Secondary bus latency timer
Subordinate bus number
Secondary bus number
I/O limit
Primary bus number
I/O base
18h
Secondary status
1Ch
Memory limit
Memory base
20h
Prefetchable memory limit
Prefetchable memory base
24h
Prefetchable base upper 32 bits
Prefetchable limit upper 32 bits
28h
2Ch
I/O limit upper 16 bits
I/O base upper 16 bits
30h
Reserved
Expansion ROM base address
Interrupt pin
Capability pointer
34h
38h
Bridge control
Arbiter control
Interrupt line
Chip control
3Ch
Extended diagnostic
40h
Reserved
44h−60h
64h
GPIO input data
GPIO output enable
P_SERR status
GPIO output data
P_SERR event disable
Reserved
Secondary clock control
68h
Reserved
6Ch−D8h
DCh
E0h
Power management capabilities
PM next item pointer
PM capability ID
HS capability ID
Data
PMCSR bridge support
Hot swap control status
Power management control/status
Reserved
HS next item pointer
E4h
Reserved
E8h−ECh
Reserved
Diagnostics
F0h
Reserved
F4h−FFh
4−1
4.1 Vendor ID Register
This 16-bit value is allocated by the PCI Special Interest Group (SIG) and identifies TI as the manufacturer of this
device. The vendor ID assigned to TI is 104Ch.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Vendor ID
R
0
R
0
R
0
R
1
R
0
R
0
R
0
R
0
R
0
R
1
R
0
R
0
R
1
R
1
R
0
R
0
Register:
Type:
Offset:
Default:
Vendor ID
Read-only
00h
104Ch
4.2 Device ID Register
This 16-bit value is allocated by the vendor and identifies the PCI device. The device ID for the PCI2050B bridge is
AC28h.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Device ID
R
1
R
0
R
1
R
0
R
1
R
1
R
0
R
0
R
0
R
0
R
1
R
0
R
1
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
Device ID
Read-only
02h
AC28h
4−2
4.3 Command Register
The command register provides control over the bridge interface to the primary PCI bus. VGA palette snooping is
enabled through this register, and all other bits adhere to the definitions in the PCI Local Bus Specification. Table 4−2
describes the bit functions in the command register.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Command
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R
0
R/W
0
R/W
0
R
0
R
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Command
Read-only, Read/Write
Offset:
Default:
04h
0000h
Table 4−2. Command Register Description
BIT
15−10
9
TYPE
FUNCTION
R
Reserved
Fast back-to-back enable. This bit defaults to 0.
R/W
System error (SERR) enable. Bit 8 controls the enable for the SERR driver on the primary interface.
0 = Disable SERR driver on primary interface (default)
8
7
6
R/W
R
1 = Enable the SERR driver on primary interface
Wait cycle control. Bit 7 controls address/data stepping by the bridge on both interfaces. The bridge does not support
address/data stepping and this bit is hardwired to 0.
Parity error response enable. Bit 6 controls the bridge response to parity errors.
0 = Parity error response disabled (default)
R/W
1 = Parity error response enabled
VGA palette snoop enable. When set, the bridge passes I/O writes on the primary PCI bus with addresses 3C6h, 3C8h,
and 3C9h inclusive of ISA aliases (that is, only bits AD9−AD0 are included in the decode).
5
4
3
R/W
R
Memory write and invalidate enable. In a PCI-to-PCI bridge, bit 4 must be read-only and return 0 when read.
Special cycle enable. A PCI-to-PCI bridge cannot respond as a target to special cycle transactions, so bit 3 is defined as
read-only and must return 0 when read.
R
Bus master enable. Bit 2 controls the ability of the bridge to initiate a cycle on the primary PCI bus. When bit 2 is 0, the bridge
does not respond to any memory or I/O transactions on the secondary interface since they cannot be forwarded to the
primary PCI bus.
2
R/W
0 = Bus master capability disabled (default)
1 = Bus master capability enabled
Memory space enable. Bit 1 controls the bridge response to memory accesses for both prefetchable and nonprefetchable
memory spaces on the primary PCI bus. Only when bit 1 is set will the bridge forward memory accesses to the secondary
bus from a primary bus initiator.
1
0
R/W
R/W
0 = Memory space disabled (default)
1 = Memory space enabled
I/O space enable. Bit 0 controls the bridge response to I/O accesses on the primary interface. Only when bit 0 is set will
the bridge forward I/O accesses to the secondary bus from a primary bus initiator.
0 = I/O space disabled (default)
1 = I/O space enabled
4−3
4.4 Status Register
The status register provides device information to the host system. Bits in this register are cleared by writing a 1 to
the respective bit; writing a 0 to a bit location has no effect. Table 4−3 describes the status register.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Status
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
1
R/W
0
R
1
R
0
R
0
R
1
R
0
R
0
R
0
R
0
Register:
Type:
Status
Read-only, Read/Write
Offset:
Default:
06h
0290h
Table 4−3. Status Register Description
BIT
TYPE
FUNCTION
15
R/W
Detected parity error. Bit 15 is set when a parity error is detected.
Signaled system error (SERR). Bit 14 is set if SERR is enabled in the command register (offset 04h, see Section 4.3) and
the bridge signals a system error (SERR). See Section 3.8, System Error Handling.
0 = No SERR signaled (default)
14
13
12
R/W
1 = Signals SERR
Received master abort. Bit 13 is set when a cycle initiated by the bridge on the primary bus has been terminated by a master
abort.
R/W
R/W
0 = No master abort received (default)
1 = Master abort received
Received target abort. Bit 12 is set when a cycle initiated by the bridge on the primary bus has been terminated by a target
abort.
0 = No target abort received (default)
1 = Target abort received
Signaled target abort. Bit 11 is set by the bridge when it terminates a transaction on the primary bus with a target abort.
0 = No target abort signaled by the bridge (default)
11
R/W
R
1 = Target abort signaled by the bridge
DEVSEL timing. These read-only bits encode the timing of P_DEVSEL and are hardwired 01b, indicating that the bridge
asserts this signal at a medium speed.
10−9
Data parity error detected. Bit 8 is encoded as:
0 = The conditions for setting this bit have not been met. No parity error detected. (default)
1 = A data parity error occurred and the following conditions were met:
a. P_PERR was asserted by any PCI device including the bridge.
8
R/W
b. The bridge was the bus master during the data parity error.
c. The parity error response bit (bit 6) was set in the command register (offset 04h, see Section 4.3).
Fast back-to-back capable. The bridge supports fast back-to-back transactions as a target; therefore, bit 7 is hardwired to
1.
7
6
R
R
User-definable feature (UDF) support. The PCI2050B bridge does not support the user-definable features; therefore, bit
6 is hardwired to 0.
66-MHz capable. Bit 5 indicates whether the primary interface is 66-MHz capable. It reads as 0 when CONFIG66 is tied
low to indicate that the PCI2050B bridge is not 66 MHz capable and reads as 1 when CONFIG66 is tied high to indicate
that the primary bus is 66 MHz capable.
5
R
Capabilities list. Bit 4 is read-only and is hardwired to 1, indicating that capabilities additional to standard PCI are
implemented. The linked list of PCI power management capabilities is implemented by this function.
4
R
R
3−0
Reserved. Bits 3−0 return 0s when read.
4−4
4.5 Revision ID Register
The revision ID register indicates the silicon revision of the PCI2050B bridge.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Revision ID
R
0
R
0
R
0
R
0
R
0
R
0
R
1
R
0
Register:
Type:
Offset:
Default:
Revision ID
Read-only
08h
02h (reflects the current revision of the silicon)
4.6 Class Code Register
This register categorizes the PCI2050B bridge as a PCI-to-PCI bridge device (0604h) with a 00h programming
interface.
Bit
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Name
Class code
Base class
Sub class
Programming interface
Type
R
0
R
0
R
0
R
0
R
0
R
1
R
1
R
0
R
0
R
0
R
0
R
0
R
0
R
1
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Default
Register:
Type:
Offset:
Default:
Class code
Read-only
09h
06 0400h
4.7 Cache Line Size Register
The cache line size register is programmed by host software to indicate the system cache line size needed by the
bridge for memory read line, memory read multiple, and memory write and invalidate transactions. The PCI2050B
bridge supports cache line sizes up to and including 16 doublewords for memory write and invalidate. If the cache
line size is larger than 16 doublewords, the command is converted to a memory write command.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Cache line size
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Offset:
Default:
Cache line size
Read/Write
0Ch
00h
4−5
4.8 Primary Latency Timer Register
The latency timer register specifies the latency timer for the bridge in units of PCI clock cycles. When the bridge is
a primary PCI bus initiator and asserts P_FRAME, the latency timer begins counting from 0. If the latency timer expires
before the bridge transaction has terminated, then the bridge terminates the transaction when its P_GNT is
deasserted.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Latency timer
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Offset:
Default:
Latency timer
Read/Write
0Dh
00h
4.9 Header Type Register
The header type register is read-only and returns 01h when read, indicating that the PCI2050B configuration space
adheres to the PCI-to-PCI bridge configuration. Only the layout for bytes 10h−3Fh of configuration space is
considered.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Header type
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
1
Register:
Type:
Offset:
Default:
Header type
Read-only
0Eh
01h
4.10 BIST Register
The PCI2050B bridge does not support built-in self test (BIST). The BIST register is read-only and returns the value
00h when read.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
BIST
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
BIST
Read-only
0Fh
00h
4−6
4.11 Base Address Register 0
The bridge requires no additional resources. Base address register 0 is read-only and returns 0s when read.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Base address register 0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Base address register 0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Base address register 0
Read-only
Offset:
Default:
10h
0000 0000h
4.12 Base Address Register 1
The bridge requires no additional resources. Base address register 1 is read-only and returns 0s when read.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Base address register 1
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Base address register 1
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Base address register 1
Read-only
Offset:
Default:
14h
0000 0000h
4.13 Primary Bus Number Register
The primary bus number register indicates the primary bus number to which the bridge is connected. The bridge uses
this register, in conjunction with the secondary bus number and subordinate bus number registers, to determine when
to forward PCI configuration cycles to the secondary buses.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Primary bus number
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Offset:
Default:
Primary bus number
Read/Write
18h
00h
4−7
4.14 Secondary Bus Number Register
The secondary bus number register indicates the secondary bus number to which the bridge is connected. The
PCI2050B bridge uses this register, in conjunction with the primary bus number and subordinate bus number
registers, to determine when to forward PCI configuration cycles to the secondary buses. Configuration cycles
directed to the secondary bus are converted to type 0 configuration cycles.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Secondary bus number
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Offset:
Default:
Secondary bus number
Read/Write
19h
00h
4.15 Subordinate Bus Number Register
The subordinate bus number register indicates the bus number of the highest numbered bus beyond the primary bus
existing behind the bridge. The PCI2050B bridge uses this register, in conjunction with the primary bus number and
secondary bus number registers, to determine when to forward PCI configuration cycles to the subordinate buses.
Configuration cycles directed to a subordinate bus (not the secondary bus) remain type 1 cycles as the cycle crosses
the bridge.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Subordinate bus number
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Offset:
Default:
Subordinate bus number
Read/write
1Ah
00h
4.16 Secondary Bus Latency Timer Register
The secondary bus latency timer specifies the latency time for the bridge in units of PCI clock cycles. When the bridge
is a secondary PCI bus initiator and asserts S_FRAME, the latency timer begins counting from 0. If the latency timer
expires before the bridge transaction has terminated, then the bridge terminates the transaction when its S_GNT is
deasserted. The PCI-to-PCI bridge S_GNT is an internal signal and is removed when another secondary bus master
arbitrates for the bus.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Secondary bus latency timer
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Offset:
Default:
Secondary bus latency timer
Read/Write
1Bh
00h
4−8
4.17 I/O Base Register
The I/O base register is used in decoding I/O addresses to pass through the bridge. The bridge supports 32-bit I/O
addressing; thus, bits 3−0 are read-only and default to 0001b. The upper four bits are writable and correspond to
address bits AD15−AD12. The lower 12 address bits of the I/O base address are considered 0. Thus, the bottom of
the defined I/O address range is aligned on a 4K-byte boundary. The upper 16 address bits of the 32-bit I/O base
address corresponds to the contents of the I/O base upper 16 bits register (offset 30h, see Section 4.26).
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
I/O base
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R
0
R
1
Register:
Type:
I/O base
Read-only, Read/Write
Offset:
Default:
1Ch
01h
4.18 I/O Limit Register
The I/O limit register is used in decoding I/O addresses to pass through the bridge. The bridge supports 32-bit I/O
addressing; thus, bits 3−0 are read-only and default to 0001b. The upper four bits are writable and correspond to
address bits AD15−AD12. The lower 12 address bits of the I/O limit address are considered FFFh. Thus, the top of
the defined I/O address range is aligned on a 4K-byte boundary. The upper 16 address bits of the 32-bit I/O limit
address corresponds to the contents of the I/O limit upper 16 bits register (offset 32h, see Section 4.27).
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
I/O limit
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R
0
R
1
Register:
Type:
I/O limit
Read-only, Read/Write
Offset:
Default:
1Dh
01h
4−9
4.19 Secondary Status Register
The secondary status register is similar in function to the status register (offset 06h, see Section 4.4); however, its
bits reflect status conditions of the secondary interface. Bits in this register are cleared by writing a 1 to the respective
bit.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Secondary status
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
1
R/W
0
R
1
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Secondary status
Read-only, Read/Write
Offset:
Default:
1Eh
0280h
Table 4−4. Secondary Status Register Description
BIT
TYPE
FUNCTION
Detected parity error. Bit 15 is set when a parity error is detected on the secondary interface.
0 = No parity error detected on the secondary bus (default)
15
R/W
1 = Parity error detected on the secondary bus
Received system error. Bit 14 is set when the secondary interface detects S_SERR asserted. Note that the bridge never
asserts S_SERR.
14
13
12
R/W
0 = No S_SERR detected on the secondary bus (default)
1 = S_SERR detected on the secondary bus
Received master abort. Bit 13 is set when a cycle initiated by the bridge on the secondary bus has been terminated by a
master abort.
R/W
R/W
0 = No master abort received (default)
1 = Bridge master aborted the cycle
Received target abort. Bit 12 is set when a cycle initiated by the bridge on the secondary bus has been terminated by a target
abort.
0 = No target abort received (default)
1 = Bridge received a target abort
Signaled target abort. Bit 11 is set by the bridge when it terminates a transaction on the secondary bus with a target abort.
0 = No target abort signaled (default)
11
R/W
R
1 = Bridge signaled a target abort
DEVSEL timing. These read-only bits encode the timing of S_DEVSEL and are hardwired to 01b, indicating that the bridge
asserts this signal at a medium speed.
10−9
Data parity error detected.
0 = The conditions for setting this bit have not been met
1 = A data parity error occurred and the following conditions were met:
a. S_PERR was asserted by any PCI device including the bridge.
b. The bridge was the bus master during the data parity error.
c. The parity error response bit (bit 1) was set in the bridge control register (offset 3Eh, see Section 4.32).
8
R/W
7
6
R
R
R
R
Fast back-to-back capable. Bit 7 is hardwired to 1.
User-definable feature (UDF) support. Bit 6 is hardwired to 0.
66-MHz capable. Bit 5 is hardwired to 0.
5
4−0
Reserved. Bits 4−0 return 0s when read.
4−10
4.20 Memory Base Register
The memory base register defines the base address of a memory-mapped I/O address range used by the bridge to
determine when to forward memory transactions from one interface to the other. The upper 12 bits of this register
are read/write and correspond to the address bits AD31−AD20. The lower 20 address bits are considered 0s; thus,
the address range is aligned to a 1M-byte boundary. The bottom four bits are read-only and return 0s when read.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Memory base
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R
0
R
0
Register:
Type:
Memory base
Read-only, Read/Write
Offset:
Default:
20h
0000h
4.21 Memory Limit Register
The memory limit register defines the upper-limit address of a memory-mapped I/O address range used to determine
when to forward memory transactions from one interface to the other. The upper 12 bits of this register are read/write
and correspond to the address bits AD31−AD20. The lower 20 address bits are considered 1s; thus, the address
range is aligned to a 1M-byte boundary. The bottom four bits are read-only and return 0s when read.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Memory limit
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R
0
R
0
Register:
Type:
Memory limit
Read-only, Read/Write
Offset:
Default:
22h
0000h
4.22 Prefetchable Memory Base Register
The prefetchable memory base register defines the base address of a prefetchable memory address range used by
the bridge to determine when to forward memory transactions from one interface to the other. The upper 12 bits of
this register are read/write and correspond to the address bits AD31−AD20. The lower 20 address bits are considered
0; thus, the address range is aligned to a 1M-byte boundary. The bottom four bits are read-only and return 0s
when read.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Prefetchable memory base
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R
0
R
0
Register:
Type:
Prefetchable memory base
Read-only, Read/Write
Offset:
Default:
24h
0000h
4−11
4.23 Prefetchable Memory Limit Register
The prefetchable memory limit register defines the upper-limit address of a prefetchable memory address range used
to determine when to forward memory transactions from one interface to the other. The upper 12 bits of this register
are read/write and correspond to the address bits AD31−AD20. The lower 20 address bits are considered 1s; thus,
the address range is aligned to a 1M-byte boundary. The bottom four bits are read-only and return 0s when read.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Prefetchable memory limit
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R
0
R
0
Register:
Type:
Prefetchable memory limit
Read-only, Read/Write
Offset:
Default:
26h
0000h
4.24 Prefetchable Base Upper 32 Bits Register
The prefetchable base upper 32 bits register plus the prefetchable memory base register defines the base address
of the 64-bit prefetchable memory address range used by the bridge to determine when to forward memory
transactions from one interface to the other. The prefetchable base upper 32 bits register must be programmed to
all zeros when 32-bit addressing is being used.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Prefetchable base upper 32 bits
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Prefetchable base upper 32 bits
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Offset:
Default:
Prefetchable base upper 32 bits
Read/Write
28h
0000 0000h
4−12
4.25 Prefetchable Limit Upper 32 Bits Register
The prefetchable limit upper 32 bits register plus the prefetchable memory limit register defines the base address of
the 64-bit prefetchable memory address range used by the bridge to determine when to forward memory transactions
from one interface to the other. The prefetchable limit upper 32 bits register must be programmed to all zeros when
32-bit addressing is being used.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Prefetchable limit upper 32 bits
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Prefetchable limit upper 32 bits
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Offset:
Default:
Prefetchable limit upper 32 bits
Read/Write
2Ch
0000 0000h
4.26 I/O Base Upper 16 Bits Register
The I/O base upper 16 bits register specifies the upper 16 bits corresponding to AD31−AD16 of the 32-bit address
that specifies the base of the I/O range to forward from the primary PCI bus to the secondary PCI bus.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
I/O base upper 16 bits
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Offset:
Default:
I/O base upper 16 bits
Read/Write
30h
0000h
4.27 I/O Limit Upper 16 Bits Register
The I/O limit upper 16 bits register specifies the upper 16 bits corresponding to AD31−AD16 of the 32-bit address
that specifies the upper limit of the I/O range to forward from the primary PCI bus to the secondary PCI bus.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
I/O limit upper 16 bits
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Offset:
Default:
I/O limit upper 16 bits
Read/Write
32h
0000h
4−13
4.28 Capability Pointer Register
The capability pointer register provides the pointer to the PCI configuration header where the PCI power management
register block resides. The capability pointer provides access to the first item in the linked list of capabilities. The
capability pointer register is read-only and returns DCh when read, indicating the power management registers are
located at PCI header offset DCh.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Capability pointer register
R
1
R
1
R
0
R
1
R
1
R
1
R
0
R
0
Register:
Type:
Offset:
Default:
Capability pointer
Read-only
34h
DCh
4.29 Expansion ROM Base Address Register
The PCI2050B bridge does not implement the expansion ROM remapping feature. The expansion ROM base
address register returns all 0s when read.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Expansion ROM base address
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Expansion ROM base address
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
Expansion ROM base address
Read-only
38h
0000 0000h
4.30 Interrupt Line Register
The interrupt line register is read/write and is used to communicate interrupt line routing information. Since the bridge
does not implement an interrupt signal terminal, this register defaults to 00h.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Interrupt line
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Offset:
Default:
Interrupt line
Read/Write
3Ch
00h
4−14
4.31 Interrupt Pin Register
The bridge default state does not implement any interrupt terminals. Reads from bits 7−0 of this register return 0s.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Interrupt pin
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
Interrupt pin
Read-only
3Dh
00h
4.32 Bridge Control Register
The bridge control register provides many of the same controls for the secondary interface that are provided by the
command register for the primary interface. Some bits affect the operation of both interfaces.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Bridge control
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R/W
0
R/W
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Bridge control
Read-only, Read/Write
Offset:
Default:
3Eh
0000h
Table 4−5. Bridge Control Register Description
BIT
TYPE
FUNCTION
15−12
R
Reserved. Bits 15−12 return 0s when read.
Discard timer SERR enable.
11
10
R/W
0 = SERR signaling disabled for primary discard time-outs (default)
1 = SERR signaling enabled for primary discard time-outs
Discard timer status. Once set, this bit must be cleared by writing 1 to this bit.
0 = No discard timer error (default)
R/W
R/W
1 = Discard timer error. Either primary or secondary discard timer expired and a delayed transaction was discarded from
the queue in the bridge.
Secondary discard timer. Selects the number of PCI clocks that the bridge waits for a master on the secondary interface
to repeat a delayed transaction request.
9
15
0 = Secondary discard timer counts 2 PCI clock cycles (default)
10
1 = Secondary discard timer counts 2 PCI clock cycles
Primary discard timer. Selects the number of PCI clocks that the bridge waits for a master on the primary interface to repeat
a delayed transaction request.
8
7
6
R/W
R
15
0 = Primary discard timer counts 2 PCI clock cycles (default)
10
1 = Primary discard timer counts 2 PCI clock cycles
Fast back-to-back capable. The bridge never generates fast back-to-back transactions to different secondary devices. Bit
7 returns 0 when read.
Secondary bus reset. When bit 6 is set, the secondary reset signal (S_RST) is asserted. S_RST is deasserted by resetting
this bit. Bit 6 is encoded as:
R/W
0 = Do not force the assertion of S_RST (default).
1 = Force the assertion of S_RST.
4−15
Table 4−5. Bridge Control Register Description (continued)
BIT
TYPE
FUNCTION
Master abort mode. Bit 5 controls how the bridge responds to a master abort that occurs on either interface when the bridge
is the master. If this bit is set, the posted write transaction has completed on the requesting interface, and SERR enable
(bit 8) of the command register (offset 04h, see Section 4.3) is 1, then P_SERR is asserted when a master abort occurs.
If the transaction has not completed, then a target abort is signaled. If the bit is cleared, then all 1s are returned on reads
and write data is accepted and discarded when a transaction that crosses the bridge is terminated with master abort. The
default state of bit 5 after a reset is 0.
5
R/W
0 = Do not report master aborts (return FFFF FFFFh on reads and discard data on writes) (default).
1 = Report master aborts by signaling target abort if possible, or if SERR is enabled via bit 1 of this register, by
asserting SERR.
4
3
R
Reserved. Returns 0 when read. Writes have no effect.
VGA enable. When bit 3 is set, the bridge positively decodes and forwards VGA-compatible memory addresses in the video
frame buffer range 000A 0000h−000B FFFFh, I/O addresses in the range 03B0h−03BBh, and 03C0−03DFh from the
primary to the secondary interface, independent of the I/O and memory address ranges. When this bit is set, the bridge
blocks forwarding of these addresses from the secondary to the primary. Reset clears this bit. Bit 3 is encoded as:
0 = Do not forward VGA-compatible memory and I/O addresses from the primary to the secondary interface
(default).
R/W
1 = Forward VGA-compatible memory and I/O addresses from the primary to the secondary, independent of the I/O
and memory address ranges and independent of the ISA enable bit.
ISA enable. When bit 2 is set, the bridge blocks the forwarding of ISA I/O transactions from the primary to the secondary,
addressing the last 768 bytes in each 1K-byte block. This applies only to the addresses (defined by the I/O window registers)
that are located in the first 64K bytes of PCI I/O address space. From the secondary to the primary, I/O transactions are
forwarded if they address the last 768 bytes in each 1K-byte block in the address range specified in the I/O window registers.
Bit 2 is encoded as:
2
R/W
0 = Forward all I/O addresses in the address range defined by the I/O base and I/O limit registers (default).
1 = Block forwarding of ISA I/O addresses in the address range defined by the I/O base and I/O limit registers when
these I/O addresses are in the first 64K bytes of PCI I/O address space and address the top 768 bytes of each
1K-byte block.
SERR enable. Bit 1 controls the forwarding of secondary interface SERR assertions to the primary interface. Only when
this bit is set does the bridge forward S_SERR to the primary bus signal P_SERR. For the primary interface to assert SERR,
bit 8 of the command register (offset 04h, see Section 4.3) must be set.
0 = SERR disabled (default)
1
0
R/W
R/W
1 = SERR enabled
Parity error response enable. Bit 0 controls the bridge response to parity errors on the secondary interface. When this bit
is set, the bridge asserts S_PERR to report parity errors on the secondary interface.
0 = Ignore address and parity errors on the secondary interface (default).
1 = Enable parity error reporting and detection on the secondary interface.
4−16
5 Extension Registers
The TI extension registers are those registers that lie outside the standard PCI-to-PCI bridge device configuration
space (i.e., registers 40h−FFh in PCI configuration space in the PCI2050B bridge). These registers can be accessed
through configuration reads and writes. The TI extension registers add flexibility and performance benefits to the
standard PCI-to-PCI bridge. Mapping of the extension registers is contained in Table 4−1.
5.1 Chip Control Register
The chip control register contains read/write and read-only bits and has a default value of 00h. This register is used
to control the functionality of certain PCI transactions.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Chip control
R
0
R
0
R/W
0
R/W
0
R
0
R
0
R/W
0
R
0
Register:
Type:
Chip control
Read/Write, Read-only
Offset:
Default:
40h
00h
Table 5−1. Chip Control Register Description
BIT
TYPE
FUNCTION
7−6
R
Reserved. Bits 7−6 return 0s when read.
Transaction forwarding control for I/O and memory cycles.
5
R/W
0 = Transaction forwarding controlled by bits 0 and 1 of the command register (offset 04h, see Section 4.3) (default).
1 = Transaction forwarding is disabled if GPIO3 is driven high.
Memory read prefetch. When set, bit 4 enables the memory read prefetch.
0 = Upstream memory reads are disabled (default).
1 = Upstream memory reads are enabled
4
3−2
1
R/W
R
Reserved. Bits 3 and 2 return 0s when read.
Memory write and memory write and invalidate disconnect control.
0 = Disconnects on queue full or 4-KB boundaries (default)
R/W
R
1 = Disconnects on queue full, 4-KB boundaries and cacheline boundaries.
0
Reserved. Bit 0 returns 0 when read.
5−1
5.2 Extended Diagnostic Register
The extended diagnostic register is read or write and has a default value of 00h. Bit 0 of this register is used to reset
both the PCI2050B bridge and the secondary bus.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Extended diagnostic
R
0
R
0
R
0
R
0
R
0
R
0
R
0
W
0
Register:
Type:
Extended diagnostic
Read-only, Write-only
Offset:
Default:
41h
00h
Table 5−2. Extended Diagnostic Register Description
BIT
TYPE
FUNCTION
7−1
R
Reserved. Bits 7−1 return 0s when read.
Writing a 1 to this bit causes the PCI2050B bridge to set bit 6 of the bridge control register (offset 3Eh, see Section 4.32)
and then internally reset the PCI2050B bridge. Bit 6 of the bridge control register is not reset by the internal reset. Bit 0 is
self-clearing.
0
W
5−2
5.3 Arbiter Control Register
The arbiter control register is used for the bridge internal arbiter. The arbitration scheme used is a two-tier rotational
arbitration. The PCI2050B bridge is the only secondary bus initiator that defaults to the higher priority arbitration tier.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Arbiter control
R
0
R
0
R
0
R
0
R
0
R
0
R/W
1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Arbiter control
Read-only, Read/Write
Offset:
Default:
42h
0200h
Table 5−3. Arbiter Control Register Description
BIT
TYPE
FUNCTION
15−10
R
Reserved. Bits 15−10 return 0s when read.
Bridge tier select. This bit determines in which tier the PCI2250 bridge is placed in the two-tier arbitration scheme.
9
8
7
6
5
4
3
2
1
R/W
0 = Low priority tier
1 = High priority tier (default)
GNT8 tier select. This bit determines in which tier the S_GNT8 is placed in the arbitration scheme. This bit is encoded as:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0 = Low priority tier (default)
1 = High priority tier
GNT7 tier select. This bit determines in which tier the S_GNT7 is placed in the arbitration scheme. This bit is encoded as:
0 = Low priority tier (default)
1 = High priority tier
GNT6 tier select. This bit determines in which tier the S_GNT6 is placed in the arbitration scheme. This bit is encoded as:
0 = Low priority tier (default)
1 = High priority tier
GNT5 tier select. This bit determines in which tier the S_GNT5 is placed in the arbitration scheme. This bit is encoded as:
0 = Low priority tier (default)
1 = High priority tier
GNT4 tier select. This bit determines in which tier the S_GNT4 is placed in the arbitration scheme. This bit is encoded as:
0 = Low priority tier (default)
1 = High priority tier
GNT3 tier select. This bit determines in which tier the S_GNT3 is placed in the arbitration scheme. This bit is encoded as:
0 = Low priority tier (default)
1 = High priority tier
GNT2 tier select. This bit determines in which tier the S_GNT2 is placed in the arbitration scheme. This bit is encoded as:
0 = Low priority tier (default)
1 = High priority tier
GNT1 tier select. This bit determines in which tier the S_GNT1 is placed in the arbitration scheme. This bit is encoded as:
0 = Low priority tier (default)
1 = High priority tier
GNT0 tier select. This bit determines in which tier the S_GNT0 is placed in the arbitration scheme. This bit is encoded as:
0
R/W
0 = Low priority tier (default)
1 = High priority tier
5−3
5.4 P_SERR Event Disable Register
The P_SERR event disable register is used to enable/disable the SERR event on the primary interface. All events
are enabled by default.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
P_SERR event disable
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
Register:
Type:
P_SERR event disable
Read-only, Read/Write
Offset:
Default:
64h
00h
Table 5−4. P_SERR Event Disable Register Description
BIT
TYPE
FUNCTION
7
R
Reserved. Bit 7 returns 0 when read.
Master delayed read time-out.
24
6
5
R/W
0 = P_SERR signaled on a master time-out after 2 retries on a delayed read (default).
1 = P_SERR is not signaled on a master time-out.
Master delayed write time-out.
24
R/W
R/W
0 = P_SERR signaled on a master time-out after 2 retries on a delayed write (default).
1 = P_SERR is not signaled on a master time-out.
Master abort on posted write transactions. When set, bit 4 enables P_SERR reporting on master aborts on posted write
transactions.
4
0 = Master aborts on posted writes enabled (default)
1 = Master aborts on posted writes disabled
Target abort on posted writes. When set, bit 3 enables P_SERR reporting on target aborts on posted write transactions.
0 = Target aborts on posted writes enabled (default).
3
2
R/W
R/W
1 = Target aborts on posted writes disabled.
Master posted write time-out.
24
0 = P_SERR signaled on a master time-out after 2 retries on a posted write (default).
1 = P_SERR is not signaled on a master time-out.
Posted write parity error.
1
0
R/W
R
0 = P_SERR signaled on a posted write parity error (default).
1 = P_SERR is not signaled on a posted write parity error.
Reserved. Bit 0 returns 0 when read.
5−4
5.5 GPIO Output Data Register
The GPIO output data register controls the data driven on the GPIO terminals configured as outputs. If both an
output-high bit and an output-low bit are set for the same GPIO terminal, the output-low bit takes precedence. The
output data bits have no effect on a GPIO terminal that is programmed as an input.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
GPIO output data
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Offset:
Default:
GPIO output data
Read/Write
65h
00h
Table 5−5. GPIO Output Data Register Description
BIT
7
TYPE
FUNCTION
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
GPIO3 output high. Writing a 1 to this bit causes the GPIO signal to be driven high. Writing a 0 has no effect.
GPIO2 output high. Writing a 1 to this bit causes the GPIO signal to be driven high. Writing a 0 has no effect.
GPIO1 output high. Writing a 1 to this bit causes the GPIO signal to be driven high. Writing a 0 has no effect.
GPIO0 output high. Writing a 1 to this bit causes the GPIO signal to be driven high. Writing a 0 has no effect.
GPIO3 output low. Writing a 1 to this bit causes the GPIO signal to be driven low. Writing a 0 has no effect.
GPIO2 output low. Writing a 1 to this bit causes the GPIO signal to be driven low. Writing a 0 has no effect.
GPIO1 output low. Writing a 1 to this bit causes the GPIO signal to be driven low. Writing a 0 has no effect.
GPIO0 output low. Writing a 1 to this bit causes the GPIO signal to be driven low. Writing a 0 has no effect.
6
5
4
3
2
1
0
5.6 GPIO Output Enable Register
The GPIO output enable register controls the direction of the GPIO signal. By default all GPIO terminals are inputs.
If both an output-enable bit and an input-enable bit are set for the same GPIO terminal, the input-enable bit takes
precedence.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
GPIO output enable
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Offset:
Default:
GPIO output enable
Read/Write
66h
00h
Table 5−6. GPIO Output Enable Register Description
BIT
7
TYPE
FUNCTION
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
GPIO3 output enable. Writing a 1 to this bit causes the GPIO signal to be configured as an output. Writing a 0 has no effect.
GPIO2 output enable. Writing a 1 to this bit causes the GPIO signal to be configured as an output. Writing a 0 has no effect.
GPIO1 output enable. Writing a 1 to this bit causes the GPIO signal to be configured as an output. Writing a 0 has no effect.
GPIO0 output enable. Writing a 1 to this bit causes the GPIO signal to be configured as an output. Writing a 0 has no effect.
GPIO3 input enable. Writing a 1 to this bit causes the GPIO signal to be configured as an input. Writing a 0 has no effect.
GPIO2 input enable. Writing a 1 to this bit causes the GPIO signal to be configured as an input. Writing a 0 has no effect.
GPIO1 input enable. Writing a 1 to this bit causes the GPIO signal to be configured as an input. Writing a 0 has no effect.
GPIO0 input enable. Writing a 1 to this bit causes the GPIO signal to be configured as an input. Writing a 0 has no effect.
6
5
4
3
2
1
0
5−5
5.7 GPIO Input Data Register
The GPIO input data register returns the current state of the GPIO terminals when read.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
GPIO input data
R
X
R
X
R
X
R
X
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
GPIO input data
Read-only
67h
X0h
Table 5−7. GPIO Input Data Register Description
BIT
7−4
3−0
TYPE
FUNCTION
R
R
GPIO3−GPIO0 input data. These four bits return the current state of the GPIO terminals.
Reserved. Bits 3−0 return 0s when read.
5−6
5.8 Secondary Clock Control Register
The secondary clock control register is used to control the secondary clock outputs.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Secondary clock control
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Secondary clock control
Read-only, Read/Write
Offset:
Default:
68h
0000h
Table 5−8. Secondary Clock Control Register Description
BIT
TYPE
FUNCTION
15−14
R
Reserved. These bits return 0 when read.
S_CLKOUT9 disable.
0 = S_CLKOUT9 enabled (default).
1 = S_CLKOUT9 disabled and driven high.
13
12
11
10
9
R/W
S_CLKOUT8 disable.
0 = S_CLKOUT8 enabled (default).
1 = S_CLKOUT8 disabled and driven high.
R/W
R/W
R/W
R/W
S_CLKOUT7 disable.
0 = S_CLKOUT7 enabled (default).
1 = S_CLKOUT7 disabled and driven high.
S_CLKOUT6 disable.
0 = S_CLKOUT6 enabled (default).
1 = S_CLKOUT6 disabled and driven high.
S_CLKOUT5 disable.
0 = S_CLKOUT5 enabled (default).
1 = S_CLKOUT5 disabled and driven high.
S_CLKOUT4 disable.
8
R/W
R/W
R/W
R/W
R/W
0 = S_CLKOUT4 enabled (default).
1 = S_CLKOUT4 disabled and driven high.
S_CLKOUT3 disable.
7−6
5−4
3−2
1−0
00, 01, 10 = S_CLKOUT3 enabled (00 is the default).
11 = S_CLKOUT3 disabled and driven high.
S_CLKOUT2 disable.
00, 01, 10 = S_CLKOUT2 enabled (00 is the default).
11 = S_CLKOUT2 disabled and driven high.
S_CLKOUT1 disable.
00, 01, 10 = S_CLKOUT1 enabled (00 is the default).
11 = S_CLKOUT1 disabled and driven high.
S_CLKOUT0 disable.
00, 01, 10 = S_CLKOUT0 enabled (00 is the default).
11 = S_CLKOUT0 disabled and driven high.
5−7
5.9 P_SERR Status Register
The P_SERR status register indicates what caused a SERR event on the primary interface.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
P_SERR status
R/W R/W
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
0
0
Register:
Type:
P_SERR status
Read-only Read/Write
Offset:
Default:
6Ah
00h
Table 5−9. P_SERR Status Register Description
BIT
TYPE
FUNCTION
7
R
Reserved. Bit 7 returns 0 when read.
24
Master delayed read time-out. A 1 indicates that P_SERR was signaled because of a master time-out after 2 retries on
a delayed read.
6
5
R/W
24
Master delayed write time-out. A 1 indicates that P_SERR was signaled because of a master time-out after 2 retries on
R/W
a delayed write.
Master abort on posted write transactions. A 1 indicates that P_SERR was signaled because of a master abort on a posted
write.
4
3
2
R/W
R/W
R/W
Target abort on posted writes. A 1 indicates that P_SERR was signaled because of a target abort on a posted write.
24
Master posted write time-out. A 1 indicates that P_SERR was signaled because of a master time-out after 2 retries on
a posted write.
1
0
R/W
R
Posted write parity error. A 1 indicates that P_SERR was signaled because of parity error on a posted write.
Reserved. Bit 0 returns 0 when read.
5.10 Power-Management Capability ID Register
The power-management capability ID register identifies the linked list item as the register for PCI power management.
The power-management capability ID register returns 01h when read, which is the unique ID assigned by the PCI
SIG for the PCI location of the capabilities pointer and the value.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Power-management capability ID
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
1
Register:
Type:
Offset:
Default:
Power-management capability ID
Read-only
DCh
01h
5−8
5.11 Power-Management Next-Item Pointer Register
The power-management next-item pointer register is used to indicate the next item in the linked list of PCI
power-management capabilities. The next-item pointer returns E4h in CompactPCI mode, indicating that the
PCI2050B bridge supports more than one extended capability, but in all other modes returns 00h, indicating that only
one extended capability is provided.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Power-management next-item pointer
R
1
R
1
R
1
R
0
R
0
R
1
R
0
R
0
Register:
Type:
Power-management next-item pointer
Read-only
Offset:
Default:
DDh
E4h cPCI mode
00h All other modes
5.12 Power-Management Capabilities Register
The power management capabilities register contains information on the capabilities of the PCI2050B functions
related to power management. The PCI2050B function supports D0, D1, D2, and D3 power states when MS1 is low.
The PCI2050B bridge does not support any power states when MS1 is high.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Power-management capabilities
R
0
R
0
R
0
R
0
R
0
R
1
R
1
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
1
R
0
Register:
Type:
Offset:
Default:
Power-management capabilities
Read-only
DEh
0602h or 0001h
Table 5−10. Power-Management Capabilities Register Description
BIT
TYPE
FUNCTION
PME support. This five-bit field indicates the power states that the device supports asserting PME. A 0 for any of these bits
indicates that the PCI2050B bridge cannot assert PME from that power state. For the PCI2050B bridge, these five bits return
00000b when read, indicating that PME is not supported.
15−11
R
R
D2 support. This bit returns 1 when MS0 is 0, indicating that the bridge function supports the D2 device power state. This
bit returns 0 when MS0 is 1, indicating that the bridge function does not support the D2 device power state.
10
D1 support. This bit returns 1 when MS0 is 0, indicating that the bridge function supports the D1 device power state. This
bit returns 0 when MS0 is 1, indicating that the bridge function does not support the D1 device power state.
9
8−6
5
R
R
R
Reserved. Bits 8−6 return 0s when read.
Device specific initialization. This bit returns 0 when read, indicating that the bridge function does not require special
initialization (beyond the standard PCI configuration header) before the generic class device driver is able to use it.
4
3
R
R
Auxiliary power source. This bit returns a 0 when read because the PCI2050B bridge does not support PME signaling.
PMECLK. This bit returns a 0 when read because the PME signaling is not supported.
Version. This three-bit register returns the PCI Bus Power Management Interface Specification revision.
2−0
R
001 = Revision 1.0, MS0 = 1
010 = Revision 1.1, MS0 = 0
5−9
5.13 Power-Management Control/Status Register
The power-management control/status register determines and changes the current power state of the PCI2050B
bridge. The contents of this register are not affected by the internally generated reset caused by the transition from
D3
to D0 state.
hot
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Power-management control/status
R
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
Default
0
Register:
Type:
Power-management control/status
Read-only, Read/Write
Offset:
Default:
E0h
0000h
Table 5−11. Power-Management Control/Status Register
BIT
TYPE
FUNCTION
15
R
R
PME status. This bit returns a 0 when read because the PCI2050B bridge does not support PME.
Data scale. This 2-bit read-only field indicates the scaling factor to be used when interpreting the value of the data
register. These bits return only 00b, because the data register is not implemented.
14−13
Data select. This 4-bit field is used to select which data is to be reported through the data register and data-scale
field. These bits return only 0000b, because the data register is not implemented.
12−9
R
8
R
R
PME enable. This bit returns a 0 when read because the PCI2050B bridge does not support PME signaling.
Reserved. Bits 7−2 return 0s when read.
7−2
Power state. This 2-bit field is used both to determine the current power state of a function and to set the function
into a new power state. The definition of this is given below:
00 = D0
01 = D1
10 = D2
1−0
R/W
11 = D3
hot
5−10
5.14 PMCSR Bridge Support Register
The PMCSR bridge support register is required for all PCI bridges and supports PCI-bridge-specific functionality.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
PMCSR bridge support
R
X
R
X
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
PMCSR bridge support
Read-only
E2h
X0h
Table 5−12. PMCSR Bridge Support Register Description
BIT
TYPE
FUNCTION
Bus power control enable. This bit returns the value of the MS1/BCC input.
0 = Bus power/ clock control disabled.
7
R
1 = Bus power/clock control enabled.
B2/B3 support for D3 . This bit returns the value of MS1/BCC input. When this bit is 1, the secondary clocks
hot
are stopped when the device is placed in D3 . When this bit is 0, the secondary clocks remain on in all device
hot
states.
6
R
R
Note: If the primary clock is stopped, then the secondary clocks stop because the primary clock is used to
generate the secondary clocks.
5−0
Reserved.
5.15 Data Register
The data register is an optional, 8-bit read-only register that provides a mechanism for the function to report
state-dependent operating data such as power consumed or heat dissipation. The PCI2050B bridge does not
implement the data register.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Data
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
Data
Read-only
E3h
00h
5−11
5.16 HS Capability ID Register
The HS capability ID register identifies the linked list item as the register for cPCI hot-swap capabilities. The register
returns 06h when read, which is the unique ID assigned by the PICMG for PCI location of the capabilities pointer and
the value. In Intel-compatible mode, this register is read-only and defaults to 00h.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
HS capability ID
R
0
R
0
R
0
R
R
0
R
1
R
1
R
0
0
Register:
Type:
Offset:
Default:
HS capability ID
Read-only
E4h
06h TI mode
00h Intel-compatible mode
5.17 HS Next-Item Pointer Register
The HS next-item pointer register is used to indicate the next item in the linked list of cPCI hot swap capabilities.
Because this is the last extended capability that the PCI2050B bridge supports, the next-item pointer returns all 0s.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
HS next-item pointer
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
HS next-item pointer
Read-only
E5h
00h
5−12
5.18 Hot-Swap Control Status Register
The hot-swap control status register contains control and status information for cPCI hot swap resources.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Hot swap control status
R
0
R
0
R
0
R
0
R/W
0
R
0
R/W
0
R
0
Register:
Type:
Hot-swap control status
Read-only, Read/Write
Offset:
Default:
E6h
00h
Table 5−13. Hot-Swap Control Status Register Description
BIT
TYPE
FUNCTION
ENUM insertion status. When set, the ENUM output is driven by the PCI2050B bridge. This bit defaults to 0, and is set after
a PCI reset occurs, the pre-load of serial ROM is complete, the ejector handle is closed, and bit 6 is 0. Thus, this bit is set
following an insertion when the board implementing the PCI2050B bridge is ready for configuration. This bit cannot be set
under software control.
7
R
ENUM extraction status. When set, the ENUM output is driven by the PCI2050B bridge. This bit defaults to 0, and is set
when the ejector handle is opened and bit 7 is 0. Thus, this bit is set when the board implementing the PCI2050B bridge
is about to be removed. This bit cannot be set under software control.
6
R
R
5−4
Reserved. Bits 5 and 4 return 0s when read.
LED ON/OFF. This bit defaults to 0, and controls the external LED indicator (HS_LED) under normal conditions. However,
for a duration following a PCI_RST, the HS_LED output is driven high by the PCI2050B bridge and this bit is ignored. When
this bit is interpreted, a 1 causes HS_LED high and a 0 causes HS_LED low.
3
R/W
Following PCI_RST, the HS_LED output is driven high by the PCI2050B bridge until the ejector handle is closed. When
these conditions are met, the HS_LED is under software control via this bit.
2
1
0
R
R/W
R
Reserved. Bit 2 returns 0 when read.
ENUM interrupt mask. This bit allows the HS_ENUM output to be masked by software. Bits 6 and 7 are set independently
from this bit.
0 = Enable HS_ENUM output
1 = Mask HS_ENUM output
Reserved. Bit 0 returns 0 when read.
5−13
5.19 Diagnostics Register
The diagnostics register enables or disables posted write combing of the PCI2050B bridge.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Diagnostics
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
Register:
Type:
TI Diagnostics
Read-only, read/write (see individual bit descriptions)
Offset:
Default:
F0h
0000h
Table 5−14. Diagnostics Register Description
FUNCTION
BIT
TYPE
15−1
R
Reserved. Bits 15−1 return 0s when read.
Disable posted write combining.
0
R/W
0 = Enable posted write combining (default)
1 = Disable posted write combining
5−14
6 Electrical Characteristics
†
6.1 Absolute Maximum Ratings Over Operating Temperature Ranges
Supply voltage range: V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.6 V
CC
: P_V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6 V
CCP
: S_V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6 V
CCP
‡
Input voltage range, V : CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
I
+ 0.5 V
CC
§
Input voltage range, V : PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6 V
I
‡
Output voltage range, V : CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
O
Output voltage range, V : PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6 V
Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
(V < 0 or V > V ) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Storage temperature range, T
+ 0.5 V
CC
§
O
IK
I
I
CC
Output clamp current, I
OK
O O CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
J
Virtual junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
†
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡
§
CMOS terminals are 23−25, 27−30, 32, 33, 35, 36, 38, 39, 41, 42, 126−130, 132−134 for PDV- and PPM-packaged devices, and J6, J18, J19,
K1, K2, K5, K6. K14, K17, K18, L1, L2, L5, L14, L15, L17,M1, M3, M6, N1, N2, N6, P1 for the GHK- and ZHK-packaged devices.
All signal terminals other than CMOS terminals are PCI terminals.
NOTES: 1. Applies for external input and bidirectional buffers. PCI terminals are measured with respect to V
instead of V . The limit is
CC
CCP
specified for a dc condition.
2. Applies for external input and bidirectional buffers. PCI terminals are measured with respect to V
specified for a dc condition.
instead of V . The limit is
CC
CCP
6−1
6.2 Recommended Operating Conditions (see Note 3)
OPERATION
MIN
NOM
3.3
3.3
5
MAX
3.6
UNIT
V
Supply voltage (core)
Commercial
Commercial
3.3 V
3.3 V
5 V
3
3
V
CC
3.6
P_V
PCI primary bus I/O clamping rail voltage
V
V
CCP
CCP
4.75
3
5.25
3.6
3.3 V
5 V
3.3
5
S_V
PCI secondary bus I/O clamping rail voltage Commercial
PCI
4.75
5.25
3.3 V
5 V
0.5 V
V
CCP
2
CCP
V
CCP
CMOS
0.7 V
CC
V
CC
†
V
V
V
V
High-level input voltage
IH
¶
CLK
0.57V
CCP
V
V
CCP
P_RST_L
TRST_L
0.77V
CCP
CCP
0.9 V
V
CC
CC
0
3.3 V
5 V
0.3 V
CCP
0.8
PCI
0
0
0
†
Low-level input voltage
IL
0.2 V
CMOS
CC
¶
CLK
0.2 V
CCP
PCI
0
0
0
V
V
CCP
V
V
Input voltage
V
V
I
CMOS
CCP
‡
V
Output voltage
Output voltage
PCI
CC
O
1
0
4
6
Input transition time (t and t )
ns
t
t
r
f
CMOS
0
25
25
25
70
85
115
PCI2050B
PCI2050BI
Operating ambient temperature range
Virtual junction temperature
°C
°C
T
A
−40
0
§
T
J
NOTES: 3. Unused terminals (input or I/O) must be held high or low to prevent them from floating.
†
‡
§
¶
Applies to external input and bidirectional buffers without hysteresis
Applies to external output buffers
These junction temperatures reflect simulation conditions. The customer is responsible for verifying junction temperature.
CLK includes P_CLK and S_CLK terminals.
6−2
6.3 Electrical Characteristics Over Recommended Operating Conditions
PARAMETER
TERMINALS
OPERATION
3.3 V
TEST CONDITIONS
MIN
MAX
UNIT
0.9 V
CC
2.4
I
I
I
I
I
I
I
I
= −0.5 mA
OH
PCI
5 V
= −2 mA
= −4 mA
= −8 mA
= 1.5 mA
= −2 mA
= 4 mA
OH
OH
OH
OL
V
V
V
High-level output voltage
OH
†
‡
CMOS1
2.1
2.1
CMOS2
3.3 V
5 V
0.1 V
CC
PCI
0.55
OH
OH
OH
Low-level output voltage
V
OL
†
‡
0.5
0.5
10
CMOS1
CMOS2
= 8 mA
Input terminals
V = V
I
CCP
I
IH
High-level input current
Low-level input current
µA
§
I/O terminals
V = V
10
−1
I
CCP
Input terminals
V = GND
I
§
V = GND
I
−10
−60
10
I/O terminals
I
I
µA
µA
IL
¶
V = GND
I
Pu terminals
High-impedance output current Output terminals
V
O
= V or GND
CCP
OZ
†
‡
CMOS1 includes terminals 24, 25, 27, 28 for PDV- and PDM-packaged devices and K1, K2, K5, K6 for the GHK- and ZHK-packaged devices.
CMOS2 includes terminals 29, 30, 33, 35, 36, 38, 39, 41, 42, 128, 130 for PDV- and PDM-packaged devices and K17, L1, L2, L5, L14, M1, M3,
M6, N1, N2, N6, P1 for the GHK- and ZHK-packaged devices.
§
¶
For I/O terminals, the input leakage current (I and I ) includes the I
leakage of the disabled output.
Pu terminals include TDI, TMS, and TRST_L. These are pulled up with internal resistors.
IL IH OZ
6−3
6.4 66-MHz PCI Clock Signal AC Parameters
t
c
t
t
(l)
(h)
V
t(2)
t(3)
t(1)
P_CLK
V
V
t
t
f(SCLK)
r(SCLK)
t
t
s
s
t
t
(l)
(h)
V
t(1)
S_CLK
V
t(2)
V
t(3)
t
t
f(SCLK)
r(SCLK)
t
c
NOTE: V
= 2.0 V for 5-V clocks; 0.5 V
= 1.5 V for 5-V clocks; 0.4 V
= 0.8 V for 5-V clocks; 0.3 V
for 3.3-V clocks
for 3.3-V clocks
for 3.3-V clocks
t(1)
t(2)
t(3)
CC
CC
CC
V
V
Figure 6−1. PCI Clock Signal AC Parameter Measurements
PARAMETER
MIN
15
MAX
30
UNIT
ns
t
t
t
t
t
t
t
t
t
P_CLK, S_CLK cycle time
P_CLK, S_CLK high time
c
6
6
ns
(h)
P_CLK, S_CLK low time
ns
(l)
P_CLK, S_CLK slew rate (0.2 V
Delay from P_CLK to S_CLK
P_CLK rising to S_CLK rising
P_CLK falling to S_CLK falling
to 0.6 V
CC CC
)
1.5
0
4
7
V/ns
ns
(PSS)
d(SCLK)
r(SCLK)
f(SCLK)
d(skew)
sk
0
7
ns
0
7
ns
S_CLK0 duty cycle skew from P_CLK duty cycle
S_CLKx to SCLKy
0.750
0.500
ns
ns
6−4
6.5 66-MHz PCI Signal Timing
CLK
V
test
t
v
t
(inval)
Valid
Output
t
off
t
on
t
h
t
su
Valid
Input
NOTE: V
test
= 1.5 V for 5-V signals; 0.4 V
for 3.3-V signals
CC
Figure 6−2. PCI Signal Timing Measurement Conditions
PARAMETER
MIN
MAX
UNIT
ns
t
t
t
t
t
t
t
CLK to signal valid delay—bused signals (see Notes 4, 5, and 6)
CLK to signal valid delay—point-to-point (see Notes 4, 5, and 6)
Float to active delay (see Notes 4, 5, and 6)
2
6
v(bus)
v(ptp)
on
2
2
6
ns
ns
Active to float delay (see Notes 4, 5, and 6)
14
ns
off
Input setup time to CLK—bused signal (see Notes 4, 5, and 6)
Input setup time to CLK—point-to-point (see Notes 4, 5, and 6)
Input signal hold time from CLK (see Notes 4 and 5)
3
5
0
ns
su(bus)
su(ptp)
h
ns
ns
NOTES: 4. See Figure 6−2
5. All primary interface signals are synchronized to P_CLK and all secondary interface signals are synchronized to S_CLK.
6. Bused signals are as follows:
P_AD, P_C/BE, P_PAR, P_PERR, P_SERR, P_FRAME, P_IRDY, P_TRDY, P_LOCK, P_DEVSEL, P_STOP, P_IDSEL, S_AD,
S_C/BE, S_PAR, S_PERR, S_SERR, S_FRAME, S_IRDY, S_TRDY, S_LOCK, S_DEVSEL, S_STOP
Point-to-point signals are as follows:
P_REQ, S_REQx, P_GNT, S_GNTx
6−5
6.6 Parameter Measurement Information
LOAD CIRCUIT PARAMETERS
†
I
OL
TIMING
C
I
I
V
LOAD
(pF)
OL
OH
LOAD
(V)
PARAMETER
(mA)
(mA)
t
0
3
PZH
Test
Point
t
50
8
−8
en
t
t
t
PZL
PHZ
PLZ
From Output
Under Test
V
LOAD
t
t
50
50
8
8
−8
−8
1.5
‡
dis
pd
C
LOAD
†
‡
C
V
includes the typical load-circuit distributed capacitance.
LOAD
LOAD
I
OH
− V
OL
= 50 Ω, where V
= 0.6 V, I
OL
= 8 mA
OL
I
OL
LOAD CIRCUIT
V
Timing
Input
(see Note A )
CC
V
CC
50% V
CC
High-Level
Input
50% V
50% V
CC
CC
0 V
0 V
t
h
t
su
t
w
Data
Input
V
CC
90% V
CC
50% V
V
CC
50% V
CC
10% V
t
CC
CC
Low-Level
Input
0 V
50% V
50% V
CC
CC
t
f
r
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
INPUT RISE AND FALL TIMES
V
CC
Output
Control
(Low-Level
Enabling)
t
50% V
50% V
CC
CC
V
CC
0 V
Input
(see Note A)
50% V
CC
50% V
CC
PZL
t
PLZ
0 V
V
t
pd
V
CC
t
t
pd
pd
≈ 50% V
Waveform 1
(see Notes B and C)
CC
OH
CC
OL
50% V
CC
In-Phase
Output
V
+ 0.3 V
OL
50% V
CC
50% V
V
OL
V
t
PHZ
t
pd
t
PZH
V
OH
V
V
− 0.3 V
OH
OH
Out-of-Phase
Output
Waveform 2
(see Notes B and C)
50% V
CC
50% V
CC
50% V
CC
≈ 50% V
0 V
CC
V
OL
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by pulse generators having the
following characteristics: PRR = 1 MHz, Z = 50 Ω, t ≤ 6 ns, t ≤ 6 ns.
O
r
f
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. For t
PLZ
and t , V
PHZ OL
and V are measured values.
OH
Figure 6−3. Load Circuit and Voltage Waveforms
6−6
6.7 PCI Bus Parameter Measurement Information
PCLK
t
w
RSTIN
t
su
Figure 6−4. RSTIN Timing Waveforms
6−7
6−8
7 Mechanical Data
The PCI2050B device is packaged either in a GHK 257-ball MicroStar BGA, a 208-terminal PDV package, a
208-terminal PPM package, or a RoHS-compliant ZHK 257-ball MicroStar BGA. The following shows the
mechanical dimensions for the GHK, PDV, PPM, and ZHK packages. The GHK and ZHK packages are mechanically
identical; therefore, only the GHK mechanical drawing is shown.
GHK (S-PBGA-N257)
PLASTIC BALL GRID ARRAY
16,10
15,90
SQ
A1 Corner
0,95
0,85
Bottom View
1,40 MAX
Seating Plane
0,12
0,55
0,45
0,08
0,45
0,35
4145273-4/E 08/02
NOTES: D. All linear dimensions are in millimeters.
E. This drawing is subject to change without notice.
F. MicroStar BGA configuration.
MicroStar BGA is a trademark of Texas Instruments.
7−1
PDV (LF-PQFP-G208)
PLASTIC QUAD FLATPACK
156
105
157
104
0,27
0,17
M
0,08
0,50
0,13 NOM
208
53
1
52
Gage Plane
25,50 TYP
0,25
28,05
SQ
0,05 MIN
0°−ā7°
27,95
30,20
SQ
29,80
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4087729/D 11/98
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
7−2
PPM (S-PQFP-G208)
PLASTIC QUAD FLATPACK
156
105
157
104
0,27
0,17
M
0,08
0,50
208
53
0,16 NOM
1
52
25,50 TYP
28,20
SQ
27,80
Gage Plane
30,80
SQ
30,40
0,25
3,60
3,20
0,25 MIN
0°−ā7°
0,75
0,50
Seating Plane
0,08
4,10 MAX
4040025/B 03/95
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-143
7−3
7−4
PACKAGE OPTION ADDENDUM
www.ti.com
25-Oct-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
PCI2050BGHK
PCI2050BIGHK
PCI2050BIPDV
ACTIVE
ACTIVE
ACTIVE
BGA
GHK
257
257
208
90
90
TBD
TBD
Call TI
Call TI
Level-3-220C-168 HR
Level-3-220C-168 HR
BGA
GHK
LQFP
PDV
36 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCI2050BIZHK
ACTIVE
BGA MI
CROSTA
R
ZHK
257
90 Green (RoHS &
no Sb/Br)
SNAGCU
Level-3-260C-168 HR
PCI2050BPDV
ACTIVE
ACTIVE
LQFP
LQFP
QFP
PDV
PDV
208
208
36 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCI2050BPDVG4
36 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCI2050BPPM
PCI2050BZHK
ACTIVE
ACTIVE
PPM
ZHK
208
257
24
TBD
CU
Level-4-220C-72 HR
Level-3-260C-168 HR
BGA MI
CROSTA
R
90 Green (RoHS &
no Sb/Br)
SNAGCU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
相关型号：
PCI2050GHK
32-Bit, 33 MHz PCI-to-PCI Bridge, Compact PCI Hot-Swap Friendly, 9-Master, MicroStar Packaging 209-BGA MICROSTAR 0 to 70
TI
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