PCI4451 [TI]
PC CARD AND OHCI CONTROLLER; PC卡和OHCI控制器
| 型号： | PCI4451 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | PC CARD AND OHCI CONTROLLER |
| 文件： | 总216页 (文件大小：981K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀ ꢁ ꢂꢃ ꢃ ꢄ ꢅ ꢆ ꢇꢈ ꢉꢆ ꢊꢆ
ꢀꢁ ꢁ ꢋ ꢌꢍ ꢋ ꢎꢍ ꢏ ꢐ ꢁꢂ ꢁ ꢑ ꢎ ꢒꢌꢑ ꢓꢓꢔ ꢌ
Data Manual
2000
PCIBus Solutions
SCPS056
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products
or to discontinue any product or service without notice, and advise customers to obtain the latest
version of relevant information to verify, before placing orders, that information being relied on
is current and complete. All products are sold subject to the terms and conditions of sale supplied
at the time of order acknowledgement, including those pertaining to warranty, patent
infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the
time of sale in accordance with TI’s standard warranty. Testing and other quality control
techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing
of all parameters of each device is not necessarily performed, except those mandated by
government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE
POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR
ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR
PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR
USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY
AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and
operating safeguards must be provided by the customer to minimize inherent or procedural
hazards.
TI assumes no liability for applications assistance or customer product design. TI does not
warrant or represent that any license, either express or implied, is granted under any patent right,
copyright, mask work right, or other intellectual property right of TI covering or relating to any
combination, machine, or process in which such semiconductor products or services might be
or are used. TI’s publication of information regarding any third party’s products or services does
not constitute TI’s approval, warranty or endorsement thereof.
Copyright 2000, Texas Instruments Incorporated
Contents
Section
Title
Page
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
1.1
1.2
1.3
1.4
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3
2
3
Terminal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Feature/Protocol Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
2
3.1
3.2
3.3
I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
Clamping Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
Peripheral Component Interconnect (PCI) Interface . . . . . . . . . . . . . . 3–2
3.3.1
3.3.2
3.3.3
PCI Bus Lock (LOCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
PCI4451 EEPROM Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3
Loading The Subsystem Identification (EEPROM
Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4
3.3.4
Serial Bus EEPROM Application . . . . . . . . . . . . . . . . . . . . . . 3–6
3.4
PC Card Applications Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
3.4.6
3.4.7
3.4.8
3.4.9
3.4.10
3.4.11
PC Card Insertion/Removal and Recognition . . . . . . . . . . . 3–8
P C Power Switch Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9
2
Zoomed Video Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10
Zoomed Video Autodetect . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–11
Ultra Zoomed Video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–13
D3_STAT Terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–13
Internal Ring Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–13
Integrated Pullup Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . 3–14
SPKROUT Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–14
LED Socket Activity Indicators . . . . . . . . . . . . . . . . . . . . . . . . 3–15
PC Card 16 DMA Support . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15
3.5
3.6
Programmable Interrupt Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–16
3.5.1
3.5.2
3.5.3
PC Card Functional and Card Status Change Interrupts . 3–16
Interrupt Masks and Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–17
Using Parallel PCI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 3–18
Power Management Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–19
3.6.1
3.6.2
3.6.3
3.6.4
3.6.5
CLKRUN Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–19
CardBus PC Card Power Management . . . . . . . . . . . . . . . . 3–19
PCI Bus Power Management . . . . . . . . . . . . . . . . . . . . . . . . . 3–19
CardBus Device Class Power Management . . . . . . . . . . . . 3–19
Master List Of PME Context Bits and Global Reset Only
Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–20
iii
3.6.6
3.6.7
3.6.8
Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–22
Requirements for SUSPEND . . . . . . . . . . . . . . . . . . . . . . . . . 3–23
Ring Indicate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–23
4
PC Card Controller Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
PCI Configuration Registers (Functions 0 and 1) . . . . . . . . . . . . . . . . . 4–1
Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2
Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2
PCI Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4
Class Code and Revision ID Registers . . . . . . . . . . . . . . . . . . . . . . . . . 4–5
Cache Line Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5
Latency Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5
Header Type Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–6
4.10 BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–6
4.11 CardBus Socket Registers/ExCA Registers Base Address Register 4–6
4.12 Capability Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–7
4.13 Secondary Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8
4.14 PCI Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9
4.15 CardBus Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9
4.16 Subordinate Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9
4.17 CardBus Latency Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–10
4.18 CardBus Memory Base Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 4–10
4.19 CardBus Memory Limit Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 4–11
4.20 CardBus I/O Base Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–11
4.21 CardBus I/O Limit Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–12
4.22 Interrupt Line Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–12
4.23 Interrupt Pin Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–13
4.24 Bridge Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–14
4.25 Subsystem Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–15
4.26 Subsystem ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–15
4.27 PC Card 16-Bit I/F Legacy Mode Base Address Register . . . . . . . . . 4–16
4.28 System Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–17
4.29 Multimedia Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–20
4.30 General Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–21
4.31 General Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–22
4.32 General-Purpose Event Status Register . . . . . . . . . . . . . . . . . . . . . . . . 4–23
4.33 General-Purpose Event Enable Register . . . . . . . . . . . . . . . . . . . . . . . 4–24
4.34 General-Purpose Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–24
4.35 General-Purpose Output Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–25
4.36 Multifunction Routing Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . 4–26
4.37 Retry Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–28
4.38 Card Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–29
4.39 Device Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–30
4.40 Diagnostic Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–31
iv
4.41 Socket DMA Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–32
4.42 Socket DMA Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–33
4.43 Capability ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–34
4.44 Next Item Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–34
4.45 Power Management Capabilities Register . . . . . . . . . . . . . . . . . . . . . . 4–35
4.46 Power Management Control/Status Register . . . . . . . . . . . . . . . . . . . . 4–36
4.47 Power Management Control/Status Register Bridge Support
Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–37
4.48 GPE Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–38
ExCA Compatibility Registers (Functions 0 and 1) . . . . . . . . . . . . . . . . . . 5–1
5
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
ExCA Identification and Revision Register . . . . . . . . . . . . . . . . . . . . . . 5–5
ExCA Interface Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–6
ExCA Power Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–7
ExCA Interrupt and General Control Register . . . . . . . . . . . . . . . . . . . 5–8
ExCA Card Status-Change Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–9
ExCA Card Status-Change Interrupt Configuration Register . . . . . . . 5–10
ExCA Address Window Enable Register . . . . . . . . . . . . . . . . . . . . . . . . 5–11
ExCA I/O Window Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–12
ExCA I/O Windows 0 and 1 Start-Address Low-Byte Registers . . . . 5–13
5.10 ExCA I/O Windows 0 and 1 Start-Address High-Byte Registers . . . . 5–13
5.11 ExCA I/O Windows 0 and 1 End-Address Low-Byte Registers . . . . . 5–14
5.12 ExCA I/O Windows 0 and 1 End-Address High-Byte Registers . . . . 5–14
5.13 ExCA Memory Windows 0–4 Start-Address Low-Byte Registers . . . 5–15
5.14 ExCA Memory Windows 0–4 Start-Address High-Byte Registers . . . 5–16
5.15 ExCA Memory Windows 0–4 End-Address Low-Byte Registers . . . . 5–17
5.16 ExCA Memory Windows 0–4 End-Address High-Byte Registers . . . 5–18
5.17 ExCA Memory Windows 0–4 Offset-Address Low-Byte Registers . . 5–19
5.18 ExCA Memory Windows 0–4 Offset-Address High-Byte Registers . 5–20
5.19 ExCA I/O Windows 0 and 1 Offset-Address Low-Byte Registers . . . 5–21
5.20 ExCA I/O Windows 0 and 1 Offset-Address High-Byte Registers . . . 5–21
5.21 ExCA Card Detect and General Control Register . . . . . . . . . . . . . . . . 5–22
5.22 ExCA Global Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–23
5.23 ExCA Memory Windows 0–4 Page Registers . . . . . . . . . . . . . . . . . . . 5–24
CardBus Socket Registers (Functions 0 and 1) . . . . . . . . . . . . . . . . . . . . . . 6–1
6
7
6.1
6.2
6.3
6.4
6.5
6.6
Socket Event Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2
Socket Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3
Socket Present State Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4
Socket Force Event Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
Socket Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7
Socket Power Management Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8
Distributed DMA (DDMA) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–1
7.1
7.2
7.3
DMA Current Address/Base Address Register . . . . . . . . . . . . . . . 7–2
DMA Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–2
DMA Current Count/Base Count Register . . . . . . . . . . . . . . . . . . . 7–3
v
7.4
7.5
7.6
7.7
7.8
7.9
DMA Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–3
DMA Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–4
DMA Request Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–4
DMA Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–5
DMA Master Clear Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–5
DMA Multichannel Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–6
8
OHCI-Lynx Controller Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . 8–1
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–2
Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–3
Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–3
PCI Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–4
PCI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–5
Class Code and Revision ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . 8–6
Latency Timer and Class Cache Line Size Register . . . . . . . . . . . . . . 8–6
Header Type and BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–7
Open HCI Registers Base Address Register . . . . . . . . . . . . . . . . . . . . 8–7
8.10 TI Extension Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–8
8.11 Subsystem Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–8
8.12 Subsystem ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–9
8.13 PCI Power Management Capabilities Pointer Register . . . . . . . . . . . . 8–9
8.14 Interrupt Line and Interrupt Pin Registers . . . . . . . . . . . . . . . . . . . . . . . 8–9
8.15 MIN_GNT and MAX_LAT registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–10
8.16 PCI OHCI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–10
8.17 Capability ID And Next Item Pointer Registers . . . . . . . . . . . . . . . . . . . 8–11
8.18 Power Management Capabilities Register . . . . . . . . . . . . . . . . . . . . . . 8–12
8.19 Power Management Control and Status Register . . . . . . . . . . . . . . . . 8–13
8.20 Power Management Extension Register . . . . . . . . . . . . . . . . . . . . . . . . 8–13
8.21 PCI Miscellaneous Configuration Register . . . . . . . . . . . . . . . . . . . . . . 8–14
8.22 Link Enhancement Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–15
8.23 Subsystem Access Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–16
8.24 GPIO Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–17
8.25 Link Timer Adjustment Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–18
Open HCI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–1
9
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
OHCI Version Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–4
Global Unique ID ROM Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–5
Asynchronous Transmit Retries Register . . . . . . . . . . . . . . . . . . . . . . . 9–6
CSR Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–6
CSR Compare Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–7
CSR Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–7
Configuration ROM Header Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–8
Bus Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–8
Bus Options Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–9
9.10 Global Unique ID High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–10
vi
9.11 Global Unique ID Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–10
9.12 Configuration ROM Mapping Register . . . . . . . . . . . . . . . . . . . . . . . . . . 9–11
9.13 Posted Write Address Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–11
9.14 Posted Write Address High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–12
9.15 Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–12
9.16 Host Controller Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–13
9.17 Self ID Buffer Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–14
9.18 Self ID Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–14
9.19 Isochronous Receive Channel Mask High Register . . . . . . . . . . . . . . 9–15
9.20 Isochronous Receive Channel Mask Low Register . . . . . . . . . . . . . . . 9–16
9.21 Interrupt Event Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–17
9.22 Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–18
9.23 Isochronous Transmit Interrupt Event Register . . . . . . . . . . . . . . . . . . 9–19
9.24 Isochronous Transmit Interrupt Mask Register . . . . . . . . . . . . . . . . . . . 9–20
9.25 Isochronous Receive Interrupt Event Register . . . . . . . . . . . . . . . . . . . 9–20
9.26 Isochronous Receive Interrupt Mask Register . . . . . . . . . . . . . . . . . . . 9–21
9.27 Fairness Control Register (Optional Register) . . . . . . . . . . . . . . . . . . . 9–21
9.28 Link Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–22
9.29 Node Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–23
9.30 PHY Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–24
9.31 Isochronous Cycle Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–25
9.32 Asynchronous Request Filter High Register . . . . . . . . . . . . . . . . . . . . . 9–26
9.33 Asynchronous Request Filter Low Register . . . . . . . . . . . . . . . . . . . . . 9–28
9.34 Physical Request Filter High Register . . . . . . . . . . . . . . . . . . . . . . . . . . 9–29
9.35 Physical Request Filter Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . 9–31
9.36 Physical Upper Bound Register (Optional Register) . . . . . . . . . . . . . . 9–31
9.37 Asynchronous Context Control Register . . . . . . . . . . . . . . . . . . . . . . . . 9–32
9.38 Asynchronous Context Command Pointer Register . . . . . . . . . . . . . . 9–33
9.39 Isochronous Transmit Context Control Register . . . . . . . . . . . . . . . . . . 9–34
9.40 Isochronous Transmit Context Command Pointer Register . . . . . . . . 9–35
9.41 Isochronous Receive Context Control Register . . . . . . . . . . . . . . . . . . 9–36
9.42 Isochronous Receive Context Command Pointer Register . . . . . . . . 9–37
9.43 Isochronous Receive Context Match Register . . . . . . . . . . . . . . . . . . . 9–38
10 GPIO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–1
11 Serial EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–1
11.1 Serial Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–1
12 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–1
12.1 Absolute Maximum Ratings Over Operating Temperature Ranges . 12–1
12.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 12–2
12.3 Electrical Characteristics Over Recommended Operating Conditions 12–3
12.4 PCI Clock/Reset Timing Requirements Over Recommended Ranges
of Supply Voltage and Operating Free-Air Temperature . . . . . . . . . . 12–4
12.5 PCI Timing Requirements Over Recommended Ranges of Supply
Voltage and Operating Free-Air Temperature . . . . . . . . . . . . . . . . . . . 12–4
vii
12.6 Switching Characteristics For PHY-Link Interface . . . . . . . . . . . . . . . . 12–4
12.7 Parameter Measurement Information . . . . . . . . . . . . . . . . . . . . . . . . . . 12–5
12.8 PCI Bus Parameter Measurement Information . . . . . . . . . . . . . . . . . . . 12–6
12.9 PC Card Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–6
12.10 Timing Requirements Over Recommended Ranges of Supply
Voltage and Operating Free-Air Temperature, Memory Cycles
(for 100-ns Common Memory) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–8
12.11 Timing Requirements Over Recommended Ranges of Supply
Voltage and Operating Free-Air Temperature, I/O Cycles . . . . . . . . . 12–8
12.12 Switching Characteristics Over Recommended Ranges of Supply
Voltage and Operating Free-Air Temperature, Miscellaneous . . . . . 12–9
12.13 PC Card Parameter Measurement Information . . . . . . . . . . . . . . . . . . 12–9
13 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
viii
List of Illustrations
Figure
2–1
2–2
3–1
3–2
3–3
3–4
3–5
3–6
3–7
3–8
3–9
Title
Page
PCI1451 GFN Terminal Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
PCI1451 GJG Terminal Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
PCI4451 System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
3-State Bidirectional Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
Serial EEPROM Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5
EEPROM Interface Subsystem Data Collection . . . . . . . . . . . . . . . . . . . . . 3–5
Serial EEPROM Start/Stop Conditions and BIt Transfers . . . . . . . . . . . . . 3–6
Serial EEPROM Protocol – Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6
EEPROM Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8
TPS2206 Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10
TPS2206 Typical Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10
3–10 Zoomed Video Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–11
3–11 Zoomed Video with Autodetect Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–12
3–12 SPKROUT Connection to Speaker Driver . . . . . . . . . . . . . . . . . . . . . . . . . . 3–14
3–13 Test Circuit Simplified Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15
3–14 Two Sample LED Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15
3–15 System Diagram Implementing CardBus Device Class Power
Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–22
3–16 Suspend Functional Illustration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–22
3–17 RI_OUT Functional Illustration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–23
5–1
5–2
6–1
ExCA Register Access Through I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2
ExCA Register Access Through Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2
Accessing CardBus Socket Registers Through PCI Memory . . . . . . . . . . 6–1
10–1 BMC/GPIO0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–2
10–2 LPS/GPIO1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–2
10–3 GPIO2 and GPIO3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–2
12–1 Load Circuit and Voltage Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–5
12–2 PCLK Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–6
12–3 RSTIN Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–6
12–4 Shared Signals Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–6
12–5 PC Card Memory Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–9
12–6 PC Card I/O Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–10
12–7 Miscellaneous PC Card Delay Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–10
ix
List of Tables
Table
Title
Page
2–1
GFN Terminals Sorted Alphanumerically for CardBus // 16-Bit Signals
and OHCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
2–2
2–3
2–4
2–5
2–6
CardBus PC Card Signal Names Sorted Alphanumerically to GFN
Terminal Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
16-Bit PC Card Signal Names Sorted Alphanumerically to GFN
Terminal Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
GJG Terminals Sorted Alphanumerically for CardBus // 16-Bit Signals
and OHCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8
CardBus PC Card Signal Names Sorted Alphanumerically to GJG
Terminal Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–10
16-Bit PC Card Signal Names Sorted Alphanumerically to GJG
Terminal Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12
2–7
2–8
2–9
Power Supply Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14
PC Card Power Switch Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14
PCI System Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14
2–10 PCI Address and Data Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15
2–11 PCI Interface Control Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16
2–12 System Interrupt Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17
2–13 PC/PCI DMA Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17
2–14 Zoomed Video Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18
2–15 Miscellaneous Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19
2–16 16-Bit PC Card Address and Data Terminals (slots A and B) . . . . . . . . . . 2–20
2–17 16-Bit PC Card Interface Control Terminals (slots A and B) . . . . . . . . . . . 2–21
2–18 CardBus PC Card Interface System Terminals (slots A and B) . . . . . . . . 2–23
2–19 CardBus PC Card Address and Data Terminals (slots A and B) . . . . . . . 2–24
2–20 CardBus PC Card Interface Control Terminals (slots A and B) . . . . . . . . 2–25
2–21 IEEE 1394 PHY/Link Interface Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–26
3–1
3–2
3–3
3–4
3–5
3–6
3–7
3–8
3–9
4–1
4–2
4–3
EEPROM–OHCI Bit Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3
EEPROM–ExCA Bit Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4
PCI Registers and Bits Loadable Through Serial EEPROM . . . . . . . . . . . 3–7
PC Card – Card Detect and Voltage Sense Connections . . . . . . . . . . . . . 3–9
Distributed DMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–16
CardBus Socket Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–16
PC Card Interrupt Events and Description . . . . . . . . . . . . . . . . . . . . . . . . . . 3–17
PCI4451 Interrupt Masks and Flags Registers . . . . . . . . . . . . . . . . . . . . . . 3–18
Interrupt Terminal Register Cross Reference . . . . . . . . . . . . . . . . . . . . . . . 3–18
Functions 0 and 1 PCI Configuration Register Map . . . . . . . . . . . . . . . . . . 4–1
PCI Command Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3
Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4
x
4–4
4–5
4–6
4–7
4–8
4–9
Secondary Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8
Interrupt Pin Register Cross Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–13
Bridge Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–14
System Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–17
Multimedia Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–20
General Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–21
4–10 General Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–22
4–11 General-Purpose Event Status Register Description . . . . . . . . . . . . . . . . . 4–23
4–12 General-Purpose Event Enable Register Description . . . . . . . . . . . . . . . . 4–24
4–13 General-Purpose Input Register Description . . . . . . . . . . . . . . . . . . . . . . . . 4–24
4–14 General-Purpose Output Register Description . . . . . . . . . . . . . . . . . . . . . . 4–25
4–15 Multifunction Routing Status Register Description . . . . . . . . . . . . . . . . . . . 4–26
4–16 Retry Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–28
4–17 Card Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–29
4–18 Device Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–30
4–19 Diagnostic Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–31
4–20 Socket DMA Register 0 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–32
4–21 Socket DMA Register 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–33
4–22 Power Management Capabilities Register Description . . . . . . . . . . . . . . . 4–35
4–23 Power Management Control/Status Register Description . . . . . . . . . . . . . 4–36
4–24 Power Management Control/Status Register Bridge Support
Extensions Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–37
4–25 GPE Control/Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . 4–38
5–1
5–2
5–3
5–4
5–5
5–6
5–7
5–8
5–9
ExCA Registers and Offsets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3
ExCA Identification and Revision Register Description . . . . . . . . . . . . . . . 5–5
ExCA Interface Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . 5–6
ExCA Power Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . 5–7
ExCA Interrupt and General Control Register Description . . . . . . . . . . . . 5–8
ExCA Card Status-Change Register Description . . . . . . . . . . . . . . . . . . . . 5–9
ExCA Card Status-Change Interrupt Register Description . . . . . . . . . . . . 5–10
ExCA Address Window Enable Register Description . . . . . . . . . . . . . . . . 5–11
ExCA I/O Window Control Register Description . . . . . . . . . . . . . . . . . . . . . 5–12
5–10 ExCA Memory Windows 0–4 Start-Address High-Byte Registers
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–16
5–11 ExCA Memory Windows 0–4 End-Address High-Byte Registers
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–18
5–12 ExCA Memory Windows 0–4 Offset-Address High-Byte Registers
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–20
5–13 ExCA Card Detect and General Control Register Description . . . . . . . . . 5–22
5–14 ExCA Global Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . 5–23
6–1
6–2
6–3
6–4
6–5
CardBus Socket Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1
Socket Event Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2
Socket Mask Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3
Socket Present State Register Description . . . . . . . . . . . . . . . . . . . . . . . . . 6–4
Socket Force Event Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . 6–6
xi
6–6
6–7
7–1
7–2
7–3
7–4
7–5
8–1
8–2
8–3
8–4
8–5
8–6
8–7
8–8
8–9
Socket Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7
Socket Power Management Register Description . . . . . . . . . . . . . . . . . . . 6–8
Distributed DMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–1
DDMA Command Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–3
DMA Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–4
DDMA Mode Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–5
DDMA Multichannel Mask Register Description . . . . . . . . . . . . . . . . . . . . . 7–6
Bit Field Access Tag Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–1
PCI Configuration Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–2
PCI Command Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–4
PCI Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–5
Class Code and Revision ID Register Description . . . . . . . . . . . . . . . . . . . 8–6
Latency Timer and Class Cache Line Size Register Description . . . . . . . 8–6
Header Type and BIST Register Description . . . . . . . . . . . . . . . . . . . . . . . . 8–7
Open HCI Registers Base Address Register Description . . . . . . . . . . . . . 8–7
TI Extension Base Address Register Description . . . . . . . . . . . . . . . . . . . . 8–8
8–10 Interrupt Line and Interrupt Pin Registers Description . . . . . . . . . . . . . . . . 8–9
8–11 MIN_GNT and MAX_LAT Registers Description . . . . . . . . . . . . . . . . . . . . 8–10
8–12 Capability ID and Next Item Pointer Registers Description . . . . . . . . . . . . 8–11
8–13 Power Management Capabilities Register Description . . . . . . . . . . . . . . . 8–12
8–14 Power Management Control and Status Register Description . . . . . . . . . 8–13
8–15 Power Management Extension Register Description . . . . . . . . . . . . . . . . . 8–13
8–16 PCI Miscellaneous Configuration Register Description . . . . . . . . . . . . . . . 8–14
8–17 Link Enhancement Control Register Description . . . . . . . . . . . . . . . . . . . . 8–15
8–18 Subsystem Access Identification Register Description . . . . . . . . . . . . . . . 8–16
8–19 General-Purpose Input/Output Control Register Description . . . . . . . . . . 8–17
8–20 Link Timer Adjustment Register Description . . . . . . . . . . . . . . . . . . . . . . . . 8–18
9–1
9–2
9–3
9–4
9–5
9–6
9–7
9–8
9–9
Open HCI Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–1
OHCI Version Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–4
Global Unique ID ROM Register Description . . . . . . . . . . . . . . . . . . . . . . . 9–5
Asynchronous Transmit Retries Register Description . . . . . . . . . . . . . . . . 9–6
CSR Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–7
Configuration ROM Header Register Description . . . . . . . . . . . . . . . . . . . . 9–8
Bus Options Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–9
Configuration ROM Mapping Register Description . . . . . . . . . . . . . . . . . . . 9–11
Posted Write Address Low Register Description . . . . . . . . . . . . . . . . . . . . 9–11
9–10 Posted Write Address High Register Description . . . . . . . . . . . . . . . . . . . . 9–12
9–11 Host Controller Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . 9–13
9–12 Self ID Count Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–14
9–13 Isochronous Receive Channel Mask High Register Description . . . . . . . 9–15
9–14 Isochronous Receive Channel Mask Low Register Descriptions . . . . . . . 9–16
9–15 Interrupt Event Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–17
9–16 Interrupt Mask Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–18
9–17 Isochronous Transmit Interrupt Event Register Description . . . . . . . . . . . 9–19
xii
9–18 Isochronous Receive Interrupt Event Register Description . . . . . . . . . . . 9–20
9–19 Fairness Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–21
9–20 Link Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–22
9–21 Node Identification Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–23
9–22 PHY Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–24
9–23 Isochronous Cycle Timer Register Description . . . . . . . . . . . . . . . . . . . . . . 9–25
9–24 Asynchronous Request Filter High Register Description . . . . . . . . . . . . . 9–26
9–25 Asynchronous Request Filter Low Register Description . . . . . . . . . . . . . . 9–28
9–26 Physical Request Filter High Register Description . . . . . . . . . . . . . . . . . . . 9–29
9–27 Physical Request Filter Low Register Description . . . . . . . . . . . . . . . . . . . 9–31
9–28 Asynchronous Context Control Register Description . . . . . . . . . . . . . . . . . 9–32
9–29 Asynchronous Context Command Pointer Register Description . . . . . . . 9–33
9–30 Isochronous Transmit Context Control Register Description . . . . . . . . . . 9–34
9–31 Isochronous Receive Context Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–36
9–32 Isochronous Receive Context Match Register Description . . . . . . . . . . . . 9–38
11–1 OHCI Registers and Bits Loadable Through Serial EEPROM . . . . . . . . . 11–1
11–2 Serial EEPROM Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–2
12–1 PC Card Address Setup Time, t
, 8-Bit and 16-Bit PCI Cycles . . . . . 12–7
su(A)
12–2 PC Card Command Active Time, t
12–3 PC Card Command Active Time, t
, 8-Bit PCI Cycles . . . . . . . . . . . . . 12–7
, 16-Bit PCI Cycles . . . . . . . . . . . . 12–7
c(A)
c(A)
12–4 PC Card Address Hold Time, t
, 8-Bit and 16-Bit PCI Cycles . . . . . . . 12–7
h(A)
xiii
xiv
1 Introduction
1.1 Description
The Texas Instruments PCI4451 is an integrated dual-socket PC Card controller and IEEE 1394 Open HCI host
controller. This high-performance integrated solution provides the latest in both PC Card and IEEE 1394
technology.
The PCI4451 is a three-function PCI device compliant with PCI Local Bus Specification 2.2. Functions 0 and
1 provide the independent PC Card socket controllers compliant with the 1997 PC Card Standard. The PCI4451
provides features that make it the best choice for bridging between the PCI bus and PC Cards, and supports
any combination of 16-bit and CardBus PC Cards in the two sockets, powered at 5 V or 3.3 V, as required.
All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI4451
is register compatible with the Intel 82365SL–DF ExCA controller. The PCI4451 internal data path logic allows
the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent
buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting. The
PCI4451 can be programmed to accept posted writes to improve bus utilization.
Function 2 of the PCI4451 is compatible with IEEE 1394A and the latest 1394 open host controller interface
(OHCI) specifications. The chip provides the IEEE 1394 link function and is compatible with data rates of 100,
200, and 400 Mbits per second. Deep FIFOs are provided to buffer 1394 data and accommodate large host bus
latencies. The PCI4451 provides physical write posting and a highly tuned physical data path for SBP-2
performance. Multiple cache line burst transfers, advanced internal arbitration, and bus holding buffers on the
PHY/Link interface are other features that make the PCI4451 an excellent 1394 open HCI solution.
The PCI4451 provides an internally buffered zoomed video (ZV) path. This reduces the design effort of PC board
manufacturers to add a ZV-compatible solution and ensures compliance with the CardBus loading
specifications.
Various implementation specific functions and general-purpose inputs and outputs are provided through eight
multifunction terminals. These terminals present a system with options in PC/PCI DMA, PCI LOCK and parallel
interrupts, PC Card activity indicator LEDs, and other platform specific signals. ACPI-compliant
general-purpose events may be programmed and controlled through the multifunction terminals, and an
ACPI-compliant programming interface is included for the general-purpose inputs and outputs.
The PCI4451 is compliant with PCI Bus Power Management Specification 1.1, and provides several low-power
modes which enable the host power system to further reduce power consumption. The PC Card (CardBus)
Controller and IEEE 1394 Host Controller Device Class Specifications required for Microsoft OnNow Power
Management are supported. Furthermore, an advanced complementary metal-oxide semiconductor (CMOS)
process achieves low system power consumption.
1.2 Features
The PCI4451 supports the following features:
•
•
•
1997 PC Standard compliant
PCI Bus Power Management Interface Specification 1.1 compliant
ACPI 1.0 compliant
Intel is a trademark of Intel Corporation
Microsoft is a trademark of Microsoft Corporation
1–1
•
•
•
•
•
•
•
•
•
•
•
•
•
PCI Local Bus Specification Revision 2.1/2.2 compliant
PC 98/99 compliant
Compliant with the PCI Bus Interface Specification for PCI-to-CardBus Bridges
Ultra zoomed Video
Zoomed video auto-detect
Advanced filtering on card detect lines provides 90 microseconds of noise immunity.
Programmable D3 status terminal
Internal ring oscillator
3.3-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments
Mix-and-match 5-V/3.3-V PC Card16 cards and 3.3-V CardBus cards
Supports two PC Card or CardBus slots with hot insertion and removal
Uses serial interface to TI TPS2216 dual power switch
Supports 132 Mbyte/second burst transfers to maximize data throughput on both the PCI bus and the
CardBus bus
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Supports serialized IRQ with PCI interrupts
8 programmable multifunction terminals
Interrupt modes supported: serial ISA/serial PCI, serial ISA/parallel PCI, parallel PCI only.
Serial EEPROM interface for loading subsystem ID and subsystem vendor ID
Supports zoomed video with internal buffering
Dedicated terminal for PCI CLKRUN
Four general-purpose event registers
Multifunction PCI device with separate configuration space for each socket
Five PCI memory windows and two I/O windows available to each PC Card16 socket
Two I/O windows and two memory windows available to each CardBus socket
ExCA -compatible registers are mapped in memory or I/O space
Supports distributed DMA and PC/PCI DMA
Intel 82365SL-DF register compatible
Supports 16-bit DMA on both PC Card sockets
Supports ring indicate, SUSPEND, and PCI CLKRUN
Advanced submicron, low-power CMOS technology
Provides VGA/palette memory and I/O, and subtractive decoding options
LED activity terminals
Supports PCI bus lock (LOCK)
TI is a trademark of Texas Instruments Incorportated
1–2
•
•
•
•
•
•
•
Packaged in a 256-terminal BGA or 257-terminal MicroStar BGA
OHCI link function designed to IEEE 1394 Open Host Controller Interface (OHCI) Specification
Implements PCI burst transfers and deep FIFOs to tolerate large host latency
Supports physical write posting of up to three outstanding transactions
OHCI link function is IEEE 1394-1995 compliant and compatible with Proposal 1394a
Supports serial bus data rates of 100, 200, and 400 Mbits/second
Provides bus-hold buffers on the PHY-Link I/F for low-cost single capacitor isolation
1.3 Related Documents
•
•
•
•
•
•
•
•
•
•
•
•
1997 PC Card Standard
ACPI 1.0
IEEE 1394 Open Host Controller Interface (OHCI) Specification
P1394 Standard for a High Performance Serial Bus (IEEE 1394–1995)
P1394a Draft Standard for a High Performance Serial Bus (Supplement)
PC 98/99
PCI Bus Interface Specification for PCI-to-CardBus Bridges
PCI Bus Power Management Interface Specification 1.1
PCI Bus Power Management Specification for PCI to CardBus Bridges Specification
PCI Local Bus Specification Revision 2.1/2.2
PCMCIA CardBus Bridge Specification 7.0
Yenta Specification
1.4 Ordering Information
ORDERING NUMBER
NAME
PC Card and OHCI Controller
VOLTAGE
PACKAGE
256-Terminal GFN
257-Terminal GJG
PCI4451
3.3 V, 5-V Tolerant I/Os
MicroStar BGA is a trademark of Texas Instruments Incorportated
1–3
1–4
2 Terminal Descriptions
The PCI4451 is packaged in either a 256-terminal BGA (GFN) or 257-terminal MicroStar BGA package (GJG).
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
3
5
7
9
11 13 15 17 19
10 12 14 16 18 20
2
4
6
8
Figure 2–1. PCI1451 GFN Terminal Diagram
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
3
5
7
9
11 13 15 17 19
10 12 14 16 18
2
4
6
8
Figure 2–2. PCI1451 GJG Terminal Diagram
The following tables show the correspondence between signal names and their respective terminal assignments.
Table 2–1 through Table 2–3 are for the 256-terminal GFN configuration, and Table 2–4 through Table 2–6 are for
the 257-terminal GJG configuration.
In Table 2–1 and Table 2–4, entries are listed in alphanumeric order by terminal number, with signal names for
CardBus PC cards and 16-bit PC cards. In Table 2–2 and Table 2–5, entries are listed in alphanumeric order by
CardBus PC card signal names, with corresponding terminal numbers. In Table 2–3 and Table 2–6, entries are listed
in alphanumeric order by 16-bit PC card signal names, with corresponding terminal numbers.
2–1
Table 2–1. GFN Terminals Sorted Alphanumerically for CardBus // 16-Bit Signals and OHCI
SIGNAL NAME
CARDBUS 16-BIT
SIGNAL NAME
CARDBUS
SIGNAL NAME
CARDBUS 16-BIT
CCB
TERM.
NO.
TERM.
NO.
TERM.
NO.
16-BIT
A_ADDR11
A_ADDR10
A_DATA15
A_DATA13
A_DATA11
B_DATA2
B_DATA0
B_BVD2(SPKR)
B_ADDR0
B_REG
A1
A2
GND
GND
C4
C5
A_CAD12
A_CAD9
E19
E20
F1
V
V
CCB
A_CAD16
A_CAD11
A_CC/BE0
A_RSVD
A_CAD3
A_CAD1
A_CCD1
B_CAD29
B_CCLKRUN
A_ADDR17
A_OE
B_CAD9
B_ADDR10
A_ADDR24
A_ADDR12
A3
C6
A_CAD8
A_CAD17
A_CC/BE2
A4
A_CE1
C7
A_CAD6
F2
A5
A_DATA14
A_DATA5
A_DATA4
A_CD1
C8
A_CAD2
F3
V
V
V
V
V
V
CCA
CCA
A6
C9
B_RSVD
B_CAD27
B_CAUDIO
B_CAD26
B_CC/BE3
B_CAD22
B_CVS2
F4
CC
CC
A7
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
D1
F17
F18
F19
F20
G1
CC
CC
A8
B_CAD11
B_CC/BE0
B_CAD7
A_CVS2
A_CAD19
A_CAD18
A_CFRAME
B_CAD10
B_CAD8
B_RSVD
B_CAD5
A_CAD21
A_CRST
A_CAD20
GND
B_OE
A9
B_DATA1
B_WP(IOIS16)
B_CE1
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
B1
B_DATA7
A_VS2
B_CSTSCHG B_BVD1(STSCHG/RI)
B_ADDR4
B_VS2
B_CINT
B_READY(IREQ)
B_ADDR2
B_ADDR3
B_ADDR5
B_ADDR25
B_ADDR12
B_ADDR23
B_WE
G2
A_ADDR25
A_ADDR7
A_ADDR23
B_CE2
B_CAD24
B_CAD23
B_CAD21
B_CAD19
B_CC/BE2
B_CFRAME
B_CGNT
B_CSTOP
A_RSVD
B_CAD17
B_CTRDY
B_CBLOCK
B_RSVD
B_CAD14
A_CDEVSEL
A_CBLOCK
A_CPERR
GND
B_ADDR24
B_ADDR22
B_ADDR19
B_ADDR18
B_ADDR9
A_ADDR21
A_ADDR19
A_ADDR14
GND
G3
G4
G17
G18
G19
G20
H1
B_DATA15
B_DATA14
B_DATA6
A_ADDR5
A_RESET
A_ADDR6
GND
D2
B_ADDR20
A_ADDR18
A_ADDR9
A_IOWR
D3
H2
D4
H3
B2
A_CAD14
A_CAD15
A_CAD10
D5
A_CAD13
A_IORD
H4
B3
D6
V
V
CC
H17
H18
H19
H20
J1
GND
GND
CC
B4
A_CE2
D7
A_CAD7
GND
A_DATA7
GND
B_CAD6
B_CAD3
B_CAD4
A_CC/BE3
A_CAD23
A_CREQ
A_CAD22
B_CAD1
B_CAD2
B_CAD0
B_CCD1
A_CAD26
A_CAD24
A_CAD25
B_DATA13
B_DATA5
B_DATA12
A_REG
B5
V
V
CCA
D8
CCA
B6
A_CAD5
A_CAD4
A_CAD0
B_CAD30
B_CCD2
B_CSERR
B_CVS1
A_DATA6
A_DATA12
A_DATA3
B_DATA9
B_CD2
D9
B_CAD31
B_CAD28
B_DATA10
B_DATA8
B7
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
E1
B8
V
V
CC
J2
A_ADDR3
A_INPACK
A_ADDR4
B_DATA4
B_DATA11
B_DATA3
B_CD1
CC
B9
B_CAD25
GND
B_ADDR1
GND
J3
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
C1
J4
B_WAIT
B_VS1
B_CAD20
B_ADDR6
J17
J18
J19
J20
K1
V
V
CC
CC
V
V
CCB
B_CIRDY
GND
B_ADDR15
GND
CCB
B_CREQ
B_CRST
B_INPACK
B_RESET
B_ADDR7
B_ADDR16
B_ADDR21
B_ADDR14
B_ADDR13
A_WE
B_CC/BE1
B_CAD15
B_CAD13
A_CIRDY
A_CTRDY
A_CCLK
A_CSTOP
B_CAD16
B_CAD12
B_ADDR8
B_IOWR
A_ADDR0
A_ADDR2
A_ADDR1
B_CAD18
B_CCLK
K2
B_IORD
K3
B_CDEVSEL
B_CPERR
B_CPAR
A_ADDR15
A_ADDR22
A_ADDR16
A_ADDR20
B_ADDR17
B_ADDR11
K4
V
V
CC
CC
E2
K17
K18
K19
K20
L1
PCLK
PCLK
E3
CLKRUN
PRST
CLKRUN
PRST
GNT
A_CGNT
A_CPAR
E4
C2
A_ADDR13
A_ADDR8
E17
E18
GNT
C3
A_CC/BE1
A_CVS1
A_VS1
2–2
Table 2–1. GFN Terminals Sorted Alphanumerically for CardBus // 16-Bit Signals and OHCI (Continued)
SIGNAL NAME
CARDBUS 16-BIT
A_CINT
A_CSERR
SIGNAL NAME
CARDBUS 16-BIT
SIGNAL NAME
CARDBUS 16-BIT
TERM.
NO.
TERM.
NO.
TERM.
NO.
L2
L3
A_READY(IREQ)
A_WAIT
T17
T18
T19
T20
U1
IRDY
IRDY
V20
W1
FRAME
ZV_UV4
ZV_UV6
ZV_SCLK
ZV_MCLK
LPS
FRAME
ZV_UV4
ZV_UV6
ZV_SCLK
ZV_MCLK
LPS
AD16
AD16
L4
V
V
V
V
AD17
AD17
W2
CCA
CCA
L17
L18
L19
L20
M1
M2
M3
M4
M17
M18
M19
M20
N1
AD18
AD18
W3
CC
CC
AD31
AD31
ZV_Y4
ZV_Y6
ZV_UV2
GND
ZV_Y4
ZV_Y6
ZV_UV2
GND
W4
AD30
AD30
U2
W5
REQ
REQ
U3
W6
PHY_CTL1
PHY_DATA1
PHY_DATA4
MFUNC4
SCL
PHY_CTL1
PHY_DATA1
PHY_DATA4
MFUNC4
SCL
A_CAUDIO
A_CSTSCHG
A_CCLKRUN
A_CCD2
AD26
A_BVD2(SPKR)
A_BVD1(STSCHG/RI)
A_WP(IOIS16)
A_CD2
U4
W7
U5
ZV_SDATA
ZV_SDATA
W8
U6
V
V
CC
W9
CC
U7
PHY_CTL0
GND
PHY_CTL0
GND
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
Y1
AD26
U8
MFUNC0
LATCH
IRQSER
AD2
MFUNC0
LATCH
IRQSER
AD2
AD27
AD27
U9
PHY_DATA6
PHY_DATA6
AD28
AD28
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
V1
V
V
CC
CC
AD29
AD29
SUSPEND
CLOCK
GND
SUSPEND
CLOCK
GND
A_CAD27
A_CAD28
A_CAD29
GND
A_DATA0
A_DATA8
A_DATA1
GND
AD4
AD4
N2
C/BE0
C/BE0
N3
AD6
AD6
AD10
AD10
N4
V
V
CC
AD14
AD14
CC
N17
N18
N19
N20
P1
GND
GND
AD12
AD12
PAR
PAR
C/BE3
C/BE3
GND
GND
PERR
PERR
AD24
AD24
TRDY
TRDY
ZV_UV5
ZV_UV7
ZV_PCLK
MFUNC6
PHY_LREQ
LINKON
PHY_DATA2
PHY_DATA5
SDA
ZV_UV5
ZV_UV7
ZV_PCLK
MFUNC6
PHY_LREQ
LINKON
PHY_DATA2
PHY_DATA5
SDA
AD25
AD25
DEVSEL
C/BE2
DEVSEL
C/BE2
Y2
A_CAD30
A_RSVD
ZV_HREF
ZV_Y1
A_DATA9
A_DATA2
ZV_HREF
ZV_Y1
Y3
P2
ZV_Y7
ZV_Y7
Y4
P3
V2
ZV_UV1
ZV_UV3
ZV_LRCLK
MFUNC5
PHY_CLK
PHY_DATA0
PHY_DATA3
PHY_DATA7
MFUNC3
SPKROUT
DATA
ZV_UV1
ZV_UV3
ZV_LRCLK
MFUNC5
PHY_CLK
PHY_DATA0
PHY_DATA3
PHY_DATA7
MFUNC3
SPKROUT
DATA
Y5
P4
V3
Y6
P17
P18
P19
P20
R1
AD20
AD20
V4
Y7
AD23
AD23
V5
Y8
V
CCP
V
CCP
V6
Y9
IDSEL/MFUNC7 IDSEL/MFUNC7
V7
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
MFUNC2
MFUNC1
G_RST
RI_OUT
AD1
MFUNC2
MFUNC1
G_RST
RI_OUT
AD1
A_CAD31
ZV_VSYNC
ZV_Y2
A_DATA10
ZV_VSYNC
ZV_Y2
V8
R2
V9
R3
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
R4
V
V
CC
CC
CC
CC
R17
R18
R19
R20
T1
V
V
AD3
AD3
AD19
AD19
AD0
AD0
AD5
AD5
AD21
AD21
V
V
CCP
AD8
AD8
CCP
AD22
AD22
AD7
AD7
AD11
AD11
ZV_Y0
ZV_Y3
ZV_Y5
ZV_UV0
ZV_Y0
ZV_Y3
ZV_Y5
ZV_UV0
AD9
AD9
AD15
AD15
T2
AD13
C/BE1
STOP
AD13
C/BE1
STOP
SERR
SERR
T3
T4
2–3
Table 2–2. CardBus PC Card Signal Names Sorted Alphanumerically to GFN Terminal Number
TERM.
NO.
TERM.
NO.
TERM.
NO.
TERM.
NO.
SIGNAL NAME
A_CAD0
SIGNAL NAME
A_CFRAME
SIGNAL NAME
AD26
SIGNAL NAME
B_CC/BE3
B8
A7
C8
A6
B7
B6
C7
D7
C6
C5
B4
A3
C4
D5
B2
B3
A2
F1
G3
G2
H3
H1
J4
G4
C1
M17
M18
M19
M20
L19
L18
J19
J17
J18
H19
H20
G20
H18
F20
G18
E20
G17
F18
E18
D20
C20
D19
E17
C16
B16
A16
D14
A15
C14
A14
A13
D12
C12
C10
D10
A9
C13
J20
B10
B17
A10
B18
A18
A19
A12
D16
B20
B19
B14
B15
B11
A20
A11
C17
B12
C15
C9
A_CAD1
A_CGNT
A_CINT
A_CIRDY
A_CPAR
A_CPERR
A_CREQ
A_CRST
A_CSERR
A_CSTOP
A_CSTSCHG
A_CTRDY
A_CVS1
A_CVS2
A_RSVD
A_RSVD
A_RSVD
AD0
AD27
B_CCD1
B_CCD2
B_CCLK
B_CCLKRUN
B_CDEVSEL
B_CFRAME
B_CGNT
B_CINT
B_CIRDY
B_CPAR
B_CPERR
B_CREQ
B_CRST
B_CSERR
B_CSTOP
B_CSTSCHG
B_CTRDY
B_CVS1
B_CVS2
B_RSVD
B_RSVD
B_RSVD
C/BE0
A_CAD2
L2
AD28
A_CAD3
E1
AD29
A_CAD4
C2
AD30
A_CAD5
D3
AD31
A_CAD6
J3
B_CAD0
B_CAD1
B_CAD2
B_CAD3
B_CAD4
B_CAD5
B_CAD6
B_CAD7
B_CAD8
B_CAD9
B_CAD10
B_CAD11
B_CAD12
B_CAD13
B_CAD14
B_CAD15
B_CAD16
B_CAD17
B_CAD18
B_CAD19
B_CAD20
B_CAD21
B_CAD22
B_CAD23
B_CAD24
B_CAD25
B_CAD26
B_CAD27
B_CAD28
B_CAD29
B_CAD30
B_CAD31
B_CAUDIO
B_CBLOCK
B_CC/BE0
B_CC/BE1
B_CC/BE2
A_CAD7
H2
A_CAD8
L3
A_CAD9
E4
A_CAD10
A_CAD11
A_CAD12
A_CAD13
A_CAD14
A_CAD15
A_CAD16
A_CAD17
A_CAD18
A_CAD19
A_CAD20
A_CAD21
A_CAD22
A_CAD23
A_CAD24
A_CAD25
A_CAD26
A_CAD27
A_CAD28
A_CAD29
A_CAD30
A_CAD31
A_CAUDIO
A_CBLOCK
A_CC/BE0
A_CC/BE1
A_CC/BE2
A_CC/BE3
A_CCD1
M2
E2
L1
G1
A5
B1
P2
V13
Y14
W14
Y15
W15
Y16
U14
V15
Y17
V16
W17
Y18
U16
V17
W18
Y19
T18
T19
T20
R18
P17
R19
R20
P18
N19
N20
AD1
AD2
AD3
AD4
C19
G19
W16
V18
U20
N18
K18
U12
V12
U19
V20
A1
AD5
J2
AD6
K2
K3
K1
N1
N2
N3
P1
R1
M1
D2
A4
C3
F2
J1
AD7
C/BE1
AD8
C/BE2
AD9
C/BE3
AD10
CLKRUN
CLOCK
DATA
AD11
AD12
AD13
DEVSEL
FRAME
GND
AD14
AD15
AD16
GND
D4
AD17
GND
D8
AD18
GND
D13
D17
H4
AD19
B9
GND
AD20
D9
GND
A8
M4
E3
M3
D1
AD21
C11
C18
F19
D18
A17
GND
H17
N4
A_CCD2
AD22
GND
A_CCLK
AD23
GND
N17
U4
A_CCLKRUN
A_CDEVSEL
AD24
GND
AD25
GND
U8
2–4
Table 2–2. CardBus PC Card Signal Names Sorted Alphanumerically to GFN Terminal Number
(Continued)
TERM.
NO.
TERM.
NO.
TERM.
NO.
TERM.
NO.
SIGNAL NAME
GND
SIGNAL NAME
PHY_CTL0
SIGNAL NAME
SIGNAL NAME
ZV_MCLK
U13
U17
K20
Y12
P20
T17
W13
W12
Y6
U7
W6
V7
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
D6
D11
D15
F4
W4
Y3
W3
U5
T4
V2
U3
V3
W1
Y1
W2
Y2
R2
T1
P4
R3
T2
U1
T3
U2
V1
CC
GND
PHY_CTL1
PHY_DATA0
PHY_DATA1
PHY_DATA2
PHY_DATA3
PHY_DATA4
PHY_DATA5
PHY_DATA6
PHY_DATA7
PHY_LREQ
PRST
ZV_PCLK
ZV_SCLK
ZV_SDATA
ZV_UV0
ZV_UV1
ZV_UV2
ZV_UV3
ZV_UV4
ZV_UV5
ZV_UV6
ZV_UV7
ZV_VSYNC
ZV_Y0
CC
GNT
CC
GRST
W7
Y7
CC
IDSEL/MFUNC7
IRDY
F17
K4
CC
V8
CC
IRQSER
LATCH
W8
Y8
L17
R4
CC
CC
LINKON
LPS
U9
R17
U6
CC
W5
V9
CC
MFUNC0
MFUNC1
MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6
PAR
W11
Y11
Y10
V10
W9
Y5
U10
U15
B5
CC
K19
L20
Y13
W10
Y9
CC
REQ
CCA
CCA
CCA
CCB
CCB
CCP
CCP
RI_OUT
F3
SCL
L4
ZV_Y1
V5
SDA
B13
E19
P19
V14
P3
ZV_Y2
Y4
SERR
Y20
V11
V19
U11
U18
ZV_Y3
W19
K17
W20
V6
SPKROUT
STOP
ZV_Y4
PCLK
ZV_Y5
PERR
SUSPEND
TRDY
ZV_HREF
ZV_Y6
PHY_CLK
ZV_LRCLK
V4
ZV_Y7
2–5
Table 2–3. 16-Bit PC Card Signal Names Sorted Alphanumerically to GFN Terminal Number
TERM.
NO.
TERM.
NO.
TERM.
NO.
TERM.
NO.
SIGNAL NAME
A_ADDR0
SIGNAL NAME
A_DATA11
SIGNAL NAME
AD26
SIGNAL NAME
B_DATA5
K1
K3
K2
J2
C8
B7
M17
M18
M19
M20
L19
L18
C12
D12
A13
A14
C14
A15
D14
B16
D18
C20
E20
E18
A17
B20
B19
D16
B17
E17
C19
C18
A20
B18
C17
A18
C16
A16
A11
C11
J20
B10
F19
G17
C10
A9
H19
G20
F20
D10
B9
A_ADDR1
A_ADDR2
A_ADDR3
A_ADDR4
A_ADDR5
A_ADDR6
A_ADDR7
A_ADDR8
A_ADDR9
A_ADDR10
A_ADDR11
A_ADDR12
A_ADDR13
A_ADDR14
A_ADDR15
A_ADDR16
A_ADDR17
A_ADDR18
A_ADDR19
A_ADDR20
A_ADDR21
A_ADDR22
A_ADDR23
A_ADDR24
A_ADDR25
A_BVD1(STSCHG/RI)
A_BVD2(SPKR)
A_CD1
A_DATA12
A_DATA13
A_DATA14
A_DATA15
A_INPACK
A_IORD
A_IOWR
A_OE
AD27
B_DATA6
B_DATA7
B_DATA8
B_DATA9
B_DATA10
B_DATA11
B_DATA12
B_DATA13
B_DATA14
B_DATA15
B_INPACK
B_IORD
B_IOWR
B_OE
C7
AD28
A5
AD29
J4
C6
AD30
H1
H3
G3
C3
B2
C5
C4
F2
C2
D3
E1
E3
A2
B1
D2
E4
D1
E2
G4
F1
G2
M2
M1
A8
M4
A4
B4
N1
N3
P2
B8
A7
A6
B6
D7
N2
P1
R1
J3
AD31
D9
D5
B_ADDR0
B_ADDR1
B_ADDR2
B_ADDR3
B_ADDR4
B_ADDR5
B_ADDR6
B_ADDR7
B_ADDR8
B_ADDR9
B_ADDR10
B_ADDR11
B_ADDR12
B_ADDR13
B_ADDR14
B_ADDR15
B_ADDR16
B_ADDR17
B_ADDR18
B_ADDR19
B_ADDR20
B_ADDR21
B_ADDR22
B_ADDR23
B_ADDR24
B_ADDR25
B_BVD1(STSCHG/RI)
B_BVD2(SPKR)
B_CD1
J18
H20
H18
G19
G18
B14
D20
D19
F18
A12
C13
B15
B12
C15
B11
A19
A10
W16
V18
U20
N18
K18
U12
V12
U19
V20
A1
B3
A3
A_READY(IREQ)
A_REG
A_RESET
A_VS1
A_VS2
A_WAIT
A_WE
A_WP(IOIS16)
AD0
L2
J1
H2
L1
G1
L3
C1
B_READY(IREQ)
B_REG
B_RESET
B_VS1
M3
V13
Y14
W14
Y15
W15
Y16
U14
V15
Y17
V16
W17
Y18
U16
V17
W18
Y19
T18
T19
T20
R18
P17
R19
R20
P18
N19
N20
AD1
AD2
B_VS2
AD3
B_WAIT
B_WE
AD4
AD5
B_WP(IOIS16)
C/BE0
AD6
AD7
C/BE1
AD8
C/BE2
AD9
C/BE3
AD10
CLKRUN
CLOCK
DATA
AD11
A_CD2
AD12
A_CE1
AD13
DEVSEL
FRAME
GND
A_CE2
AD14
A_DATA0
AD15
A_DATA1
AD16
GND
D4
A_DATA2
AD17
GND
D8
A_DATA3
AD18
B_CD2
GND
D13
D17
H4
A_DATA4
AD19
B_CE1
GND
A_DATA5
AD20
B_CE2
GND
A_DATA6
AD21
B_DATA0
B_DATA1
B_DATA2
B_DATA3
B_DATA4
GND
H17
N4
A_DATA7
AD22
GND
A_DATA8
AD23
C9
GND
N17
U4
A_DATA9
AD24
J19
J17
GND
A_DATA10
AD25
GND
U8
2–6
Table 2–3. 16-Bit PC Card Signal Names Sorted Alphanumerically to GFN Terminal Number (Continued)
TERM.
NO.
TERM.
NO.
TERM.
NO.
TERM.
NO.
SIGNAL NAME
GND
SIGNAL NAME
PHY_CTL0
SIGNAL NAME
SIGNAL NAME
ZV_MCLK
U13
U17
K20
Y12
P20
T17
W13
W12
Y6
U7
W6
V7
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
D6
D11
D15
F4
W4
Y3
W3
U5
T4
V2
U3
V3
W1
Y1
W2
Y2
R2
T1
P4
R3
T2
U1
T3
U2
V1
CC
GND
PHY_CTL1
PHY_DATA0
PHY_DATA1
PHY_DATA2
PHY_DATA3
PHY_DATA4
PHY_DATA5
PHY_DATA6
PHY_DATA7
PHY_LREQ
PRST
ZV_PCLK
ZV_SCLK
ZV_SDATA
ZV_UV0
ZV_UV1
ZV_UV2
ZV_UV3
ZV_UV4
ZV_UV5
ZV_UV6
ZV_UV7
ZV_VSYNC
ZV_Y0
CC
GNT
CC
GRST
W7
Y7
CC
IDSEL/MFUNC7
IRDY
F17
K4
CC
V8
CC
IRQSER
LATCH
W8
Y8
L17
R4
CC
CC
LINKON
LPS
U9
R17
U6
CC
W5
V9
CC
MFUNC0
MFUNC1
MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6
PAR
W11
Y11
Y10
V10
W9
Y5
U10
U15
B5
CC
K19
L20
Y13
W10
Y9
CC
REQ
CCA
CCA
CCA
CCB
CCB
CCP
CCP
RI_OUT
F3
SCL
L4
ZV_Y1
V5
SDA
B13
E19
P19
V14
P3
ZV_Y2
Y4
SERR
Y20
V11
V19
U11
U18
ZV_Y3
W19
K17
W20
V6
SPKROUT
STOP
ZV_Y4
PCLK
ZV_Y5
PERR
SUSPEND
TRDY
ZV_HREF
ZV_Y6
PHY_CLK
ZV_LRCLK
V4
ZV_Y7
2–7
Table 2–4. GJG Terminals Sorted Alphanumerically for CardBus // 16-Bit Signals and OHCI
SIGNAL NAME
CARDBUS
16-BIT
SIGNAL NAME
CARDBUS
16-BIT
SIGNAL NAME
CARDBUS
16-BIT
TERM.
NO.
TERM.
NO.
TERM.
NO.
A2
A3
A_CC/BE1
GND
A_ADDR8
GND
D5
D6
A_CAD13
A_CC/BE0
A_CAD5
GND
A_IORD
A_CE1
F14
F15
F16
F18
F19
G1
B_CAD15
B_CAD12
B_CAD13
B_IOWR
B_ADDR11
B_IORD
A4
A_CAD12
A_CAD10
A_CAD8
A_CAD3
A_CAD0
B_CAD29
A_ADDR11
A_CE2
D7
A_DATA6
GND
A5
D8
V
CCB
V
CCB
A6
A_DATA15
A_DATA5
A_DATA3
B_DATA1
D9
B_RSVD
B_CCD2
B_CAD26
B_CAD24
B_CAD23
B_DATA2
B_CD2
B_CAD11
GND
B_OE
A7
D10
D11
D12
D13
D14
D15
D16
D18
D19
E1
GND
A8
B_ADDR0
B_ADDR2
B_ADDR3
G2
A_CAD18
A_CAD19
A_CAD17
A_CC/BE2
A_CAD4
B_CAD7
B_CAD10
B_CAD9
B_CC/BE0
B_CAD8
GND
A_ADDR7
A_ADDR25
A_ADDR24
A_ADDR12
A_DATA12
B_DATA7
B_CE2
A9
G4
A10
A11
A12
A13
A14
A15
A16
A17
A18
B1
B_CSTSCHG B_BVD1(STSCHG/RI)
G5
V
CC
V
CC
V
CC
V
CC
G6
B_CC/BE3
B_CREQ
B_CVS2
B_CAD17
GND
B_REG
B_CFRAME
B_CBLOCK
B_RSVD
B_ADDR23
B_ADDR19
B_ADDR18
B_ADDR8
G7
B_INPACK
B_VS2
G13
G14
G15
G16
G18
G19
H1
B_ADDR24
GND
B_CC/BE1
B_ADDR10
B_CE1
V
CC
V
CC
B_CCLK
B_ADDR16
E2
A_CCLK
A_CGNT
A_ADDR16
A_WE
B_DATA15
GND
B_CDEVSEL B_ADDR21
E4
A_CPAR
A_RSVD
A_CAD16
A_CAD15
A_CAD11
A_ADDR13
A_ADDR18
A_ADDR17
A_IOWR
E5
A_CDEVSEL A_ADDR21
A_CAD20
A_CRST
A_CAD21
A_CAD22
A_CVS2
B_CAD4
B_RSVD
B_CAD5
B_CAD6
B_CAD3
A_CAD23
A_CC/BE3
A_CREQ
A_CAD24
A_CAD25
A_ADDR6
A_RESET
A_ADDR5
A_ADDR4
A_VS2
B2
E6
V
CC
V
CC
H2
B3
E7
A_RSVD
A_CAD1
A_DATA14
A_DATA4
H4
B4
E8
H5
B5
A_OE
E9
B_CAD31
B_CAD27
B_CINT
B_DATA10
B_DATA0
H6
B6
V
CCA
V
CCA
E10
E11
E12
E13
E14
E15
E16
E18
E19
F1
H14
H15
H16
H18
H19
J1
B_DATA12
B_DATA14
B_DATA6
B_DATA13
B_DATA5
A_ADDR3
A_REG
B7
A_CAD6
A_CAD2
B_CAD30
A_DATA13
A_DATA11
B_DATA9
B_READY(IREQ)
B_ADDR1
B_ADDR5
B_ADDR25
B_ADDR12
B_ADDR17
B_ADDR9
B8
B_CAD25
B_CAD21
B_CAD19
B_CC/BE2
B_CAD16
B_CAD14
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
C1
B_CCLKRUN B_WP(IOIS16)
B_CVS1 B_VS1
V
CCB
V
CCB
J2
B_CAD22
B_CAD20
B_CAD18
B_CIRDY
B_CTRDY
B_CGNT
B_CSTOP
GND
B_ADDR4
B_ADDR6
B_ADDR7
B_ADDR15
B_ADDR22
B_WE
J4
A_INPACK
A_ADDR2
A_ADDR1
V
V
V
V
J5
CC
CC
J6
CCA
CCA
F2
A_CFRAME
A_CIRDY
A_CTRDY
A_CAD9
A_CAD7
A_CCD1
B_CAD28
B_CAUDIO
B_CSERR
GND
A_ADDR23
A_ADDR15
A_ADDR22
A_ADDR10
A_DATA7
A_CD1
J14
J15
J16
J18
J19
K1
V
CC
V
CC
F4
B_CAD1
B_CAD2
B_CAD0
B_CCD1
A_CVS1
A_CINT
B_DATA4
B_DATA11
B_DATA3
B_CD1
F5
B_ADDR20
GND
F6
F7
C2
A_CBLOCK
B_CPERR
B_CPAR
A_ADDR19
B_ADDR14
B_ADDR13
A_ADDR14
A_ADDR20
A_ADDR9
F8
A_VS1
C18
C19
D1
F9
B_DATA8
B_BVD2(SPKR)
B_WAIT
K2
A_READY(IREQ)
A_WAIT
F10
F11
F12
F13
K4
A_CSERR
A_CPERR
A_CSTOP
A_CAD14
K5
V
CCA
V
CCA
D2
GND
K6
A_CAD26
GNT
A_ADDR0
GNT
D4
B_CRST
B_RESET
K14
2–8
Table 2–4. GJG Terminals Sorted Alphanumerically for CardBus // 16-Bit Signals and OHCI (Continued)
SIGNAL NAME
CARDBUS
16-BIT
SIGNAL NAME
CARDBUS
16-BIT
SIGNAL NAME
CARDBUS
16-BIT
TERM.
NO.
TERM.
NO.
TERM.
NO.
K15
K18
K19
L1
PCLK
PCLK
P9
P10
P11
P12
P13
P14
P15
P16
P18
P19
R1
MFUNC2
MFUNC1
GRST
MFUNC2
MFUNC1
GRST
T18
T19
U1
FRAME
FRAME
CLKRUN
PRST
CLKRUN
PRST
IRDY
IRDY
ZV_UV3
ZV_UV6
TRDY
ZV_UV3
ZV_UV6
TRDY
A_CSTSCHG
A_CCLKRUN
A_CCD2
A_CAD27
A_CAUDIO
REQ
A_BVD1(STSCHG/RI)
A_WP(IOIS16)
A_CD2
IRQSER
AD6
IRQSER
AD6
U2
L2
U18
U19
V1
L4
AD9
AD9
DEVSEL
ZV_UV5
ZV_SCLK
ZV_LRCLK
ZV_PCLK
LPS
DEVSEL
ZV_UV5
ZV_SCLK
ZV_LRCLK
ZV_PCLK
LPS
L5
A_DATA0
A_BVD2(SPKR)
REQ
V
CC
V
CC
L6
AD19
AD19
V2
L14
L15
L16
L18
L19
M1
M2
M4
M5
M6
M14
M15
M16
M18
M19
N1
AD21
AD21
V3
AD31
AD31
AD20
AD20
V4
AD28
AD28
ZV_Y7
ZV_Y7
V5
AD30
AD30
R2
ZV_UV0
ZV_UV2
MFUNC6
PHY_LREQ
PHY_DATA0
PHY_DATA7
MFUNC3
SUSPEND
RI_OUT
AD2
ZV_UV0
ZV_UV2
MFUNC6
PHY_LREQ
PHY_DATA0
PHY_DATA7
MFUNC3
SUSPEND
RI_OUT
AD2
V6
PHY_CTL1
PHY_DATA1
PHY_DATA5
SCL
PHY_CTL1
PHY_DATA1
PHY_DATA5
SCL
AD29
AD29
R4
V7
A_CAD29
GND
A_DATA1
GND
R5
V8
R6
V9
A_CAD30
A_RSVD
A_CAD28
C/BE3
A_DATA9
A_DATA2
A_DATA8
C/BE3
R7
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12
W13
W14
W15
W16
W17
W18
V
CC
V
CC
R8
DATA
AD0
DATA
AD0
R9
R10
R11
R12
R13
R14
R15
R16
R18
R19
T1
V
CC
V
CC
AD27
AD27
GND
GND
AD26
AD26
AD11
AD11
AD25
AD25
AD5
AD5
AD14
AD14
AD24
AD24
AD8
AD8
PAR
PAR
ZV_HREF
ZV_VSYNC
ZV_Y0
ZV_HREF
ZV_VSYNC
ZV_Y0
AD16
AD16
PERR
PERR
N2
C/BE2
C/BE2
STOP
STOP
N4
AD18
AD18
ZV_UV7
ZV_MCLK
ZV_SDATA
MFUNC5
PHY_CTL0
PHY_DATA2
PHY_DATA4
SDA
ZV_UV7
ZV_MCLK
ZV_SDATA
MFUNC5
PHY_CTL0
PHY_DATA2
PHY_DATA4
SDA
N5
ZV_Y1
ZV_Y1
AD17
AD17
N6
ZV_Y2
ZV_Y2
ZV_UV1
ZV_UV4
GND
ZV_UV1
ZV_UV4
GND
N7
A_CAD31
AD3
A_DATA10
AD3
T2
N13
N14
N15
N16
N18
N19
P1
T4
AD22
AD22
T5
V
CC
V
CC
AD23
AD23
T6
PHY_CLK
GND
PHY_CLK
GND
GND
GND
T7
V
CCP
V
CCP
T8
PHY_DATA6
MFUNC4
SPKROUT
CLOCK
AD1
PHY_DATA6
MFUNC4
SPKROUT
CLOCK
AD1
MFUNC0
LATCH
MFUNC0
LATCH
IDSEL/MFUNC7 IDSEL/MFUNC7
T9
V
CC
V
CC
T10
T11
T12
T13
T14
T15
T16
GND
GND
P2
ZV_Y3
ZV_Y3
V
CCP
V
CCP
P4
ZV_Y4
ZV_Y4
AD7
AD7
P5
ZV_Y5
ZV_Y5
AD4
AD4
AD10
AD13
AD15
SERR
AD10
AD13
AD15
SERR
P6
ZV_Y6
ZV_Y6
C/BE0
C/BE0
P7
LINKON
PHY_DATA3
LINKON
PHY_DATA3
AD12
AD12
P8
C/BE1
C/BE1
2–9
Table 2–5. CardBus PC Card Signal Names Sorted Alphanumerically to GJG Terminal Number
TERM.
NO.
TERM.
NO.
TERM.
NO.
TERM.
NO.
SIGNAL NAME
A_CAD0
SIGNAL NAME
A_CFRAME
SIGNAL NAME
AD26
SIGNAL NAME
B_CC/BE3
A8
E8
B8
A7
G7
D7
B7
F7
A6
F6
A5
B5
A4
D5
D4
B4
B3
G5
G2
G4
H1
H4
H5
J1
F2
E4
M16
M15
L16
L19
L18
L15
J18
J15
J16
H19
H14
H16
H18
G13
G18
G15
G14
F19
F15
F16
E18
F14
E16
A15
B15
E14
B14
E13
B13
D13
D12
E12
D11
E10
F9
A12
J19
D10
A17
B10
A18
D15
B18
E11
B16
C19
C18
A13
F13
F11
B19
A10
B17
B11
A14
D9
A_CAD1
A_CGNT
A_CINT
A_CIRDY
A_CPAR
A_CPERR
A_CREQ
A_CRST
A_CSERR
A_CSTOP
A_CSTSCHG
A_CTRDY
A_CVS1
A_CVS2
A_RSVD
A_RSVD
A_RSVD
AD0
AD27
B_CCD1
B_CCD2
B_CCLK
B_CCLKRUN
B_CDEVSEL
B_CFRAME
B_CGNT
B_CINT
B_CIRDY
B_CPAR
B_CPERR
B_CREQ
B_CRST
B_CSERR
B_CSTOP
B_CSTSCHG
B_CTRDY
B_CVS1
B_CVS2
B_RSVD
B_RSVD
B_RSVD
C/BE0
A_CAD2
K2
AD28
A_CAD3
F4
AD29
A_CAD4
B1
AD30
A_CAD5
D1
AD31
A_CAD6
J4
B_CAD0
B_CAD1
B_CAD2
B_CAD3
B_CAD4
B_CAD5
B_CAD6
B_CAD7
B_CAD8
B_CAD9
B_CAD10
B_CAD11
B_CAD12
B_CAD13
B_CAD14
B_CAD15
B_CAD16
B_CAD17
B_CAD18
B_CAD19
B_CAD20
B_CAD21
B_CAD22
B_CAD23
B_CAD24
B_CAD25
B_CAD26
B_CAD27
B_CAD28
B_CAD29
B_CAD30
B_CAD31
B_CAUDIO
B_CBLOCK
B_CC/BE0
B_CC/BE1
B_CC/BE2
A_CAD7
H2
A_CAD8
K4
A_CAD9
D2
A_CAD10
A_CAD11
A_CAD12
A_CAD13
A_CAD14
A_CAD15
A_CAD16
A_CAD17
A_CAD18
A_CAD19
A_CAD20
A_CAD21
A_CAD22
A_CAD23
A_CAD24
A_CAD25
A_CAD26
A_CAD27
A_CAD28
A_CAD29
A_CAD30
A_CAD31
A_CAUDIO
A_CBLOCK
A_CC/BE0
A_CC/BE1
A_CC/BE2
A_CC/BE3
A_CCD1
L1
F5
K1
H6
B2
E7
M5
V12
T12
R12
N13
T13
R13
P13
W14
R14
P14
W15
V15
T15
W16
V16
W17
R15
R19
R18
P16
P19
P18
N14
N15
M19
M18
AD1
AD2
AD3
AD4
D18
H15
T14
T16
R16
M14
K18
T11
V11
U19
T18
A3
AD5
AD6
J5
AD7
C/BE1
J6
AD8
C/BE2
K6
L5
AD9
C/BE3
AD10
CLKRUN
CLOCK
DATA
M6
M1
M4
N7
L6
AD11
AD12
AD13
DEVSEL
FRAME
GND
AD14
AD15
C2
D6
A2
G6
J2
AD16
GND
A16
C1
AD17
GND
AD18
A9
GND
D8
AD19
B9
GND
F12
G1
AD20
E9
GND
F8
L4
AD21
F10
D16
G16
D19
E15
GND
G19
M2
A_CCD2
AD22
GND
A_CCLK
E2
L2
AD23
GND
N16
T4
A_CCLKRUN
A_CDEVSEL
AD24
GND
E5
AD25
GND
T7
2–10
Table 2–5. CardBus PC Card Signal Names Sorted Alphanumerically to GJG Terminal Number
(Continued)
TERM.
NO.
TERM.
NO.
TERM.
NO.
TERM.
NO.
SIGNAL NAME
GND
SIGNAL NAME
PHY_CTL0
SIGNAL NAME
SIGNAL NAME
ZV_PCLK
V14
W12
K14
P11
N19
T19
P12
W11
P7
W6
V6
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
A11
D14
E1
V4
V2
W4
R2
T1
R4
U1
T2
V1
U2
W2
N2
N4
N5
N6
P2
P4
P5
P6
R1
CC
GND
PHY_CTL1
PHY_DATA0
PHY_DATA1
PHY_DATA2
PHY_DATA3
PHY_DATA4
PHY_DATA5
PHY_DATA6
PHY_DATA7
PHY_LREQ
PRST
ZV_SCLK
ZV_SDATA
ZV_UV0
ZV_UV1
ZV_UV2
ZV_UV3
ZV_UV4
ZV_UV5
ZV_UV6
ZV_UV7
ZV_VSYNC
ZV_Y0
CC
GNT
R7
CC
GRST
V7
E6
CC
IDSEL/MFUNC7
IRDY
W7
P8
E19
J14
P1
CC
CC
IRQSER
LATCH
W8
V8
CC
P15
T5
CC
LINKON
LPS
T8
CC
V5
R8
V10
V13
B6
CC
MFUNC0
MFUNC1
MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6
PAR
W10
P10
P9
R6
CC
K19
L14
R11
V9
CCA
CCA
CCA
CCB
CCB
CCP
CCP
REQ
F1
R9
RI_OUT
K5
ZV_Y1
T9
SCL
B12
F18
N18
W13
N1
ZV_Y2
W5
R5
SDA
W9
W18
T10
V19
R10
U18
ZV_Y3
SERR
ZV_Y4
V17
K15
V18
T6
SPKROUT
STOP
ZV_Y5
PCLK
ZV_HREF
ZV_LRCLK
ZV_MCLK
ZV_Y6
PERR
SUSPEND
TRDY
V3
ZV_Y7
PHY_CLK
W3
2–11
Table 2–6. 16-Bit PC Card Signal Names Sorted Alphanumerically to GJG Terminal Number
TERM.
NO.
TERM.
NO.
TERM.
NO.
TERM.
NO.
SIGNAL NAME
A_ADDR0
SIGNAL NAME
A_DATA11
SIGNAL NAME
AD26
SIGNAL NAME
B_DATA5
K6
J6
B8
G7
M16
M15
L16
L19
L18
L15
D11
E12
D12
D13
B13
E13
B14
B15
D19
E18
G15
F15
E15
C19
C18
B16
A17
E16
D18
D16
B19
A18
B17
D15
A15
E14
A10
F10
J19
D10
G16
G14
E10
A9
H19
H16
G13
F9
A_ADDR1
A_ADDR2
A_ADDR3
A_ADDR4
A_ADDR5
A_ADDR6
A_ADDR7
A_ADDR8
A_ADDR9
A_ADDR10
A_ADDR11
A_ADDR12
A_ADDR13
A_ADDR14
A_ADDR15
A_ADDR16
A_ADDR17
A_ADDR18
A_ADDR19
A_ADDR20
A_ADDR21
A_ADDR22
A_ADDR23
A_ADDR24
A_ADDR25
A_BVD1(STSCHG/RI)
A_BVD2(SPKR)
A_CD1
A_DATA12
A_DATA13
A_DATA14
A_DATA15
A_INPACK
A_IORD
A_IOWR
A_OE
AD27
B_DATA6
B_DATA7
B_DATA8
B_DATA9
B_DATA10
B_DATA11
B_DATA12
B_DATA13
B_DATA14
B_DATA15
B_INPACK
B_IORD
B_IOWR
B_OE
J5
B7
AD28
J1
E7
AD29
H5
H4
H1
G2
A2
D4
F6
A4
G6
B1
D1
F4
E2
B3
B2
C2
D2
E5
F5
F2
G5
G4
L1
A6
AD30
B9
J4
AD31
E9
D5
B_ADDR0
B_ADDR1
B_ADDR2
B_ADDR3
B_ADDR4
B_ADDR5
B_ADDR6
B_ADDR7
B_ADDR8
B_ADDR9
B_ADDR10
B_ADDR11
B_ADDR12
B_ADDR13
B_ADDR14
B_ADDR15
B_ADDR16
B_ADDR17
B_ADDR18
B_ADDR19
B_ADDR20
B_ADDR21
B_ADDR22
B_ADDR23
B_ADDR24
B_ADDR25
B_BVD1(STSCHG/RI)
B_BVD2(SPKR)
B_CD1
J16
H14
H18
H15
G18
A13
F16
F14
F19
E11
A12
F13
B11
A14
F11
B18
B10
T14
T16
R16
M14
K18
T11
V11
U19
T18
A3
B4
B5
A_READY(IREQ)
A_REG
A_RESET
A_VS1
A_VS2
A_WAIT
A_WE
A_WP(IOIS16)
AD0
K2
J2
H2
K1
H6
K4
E4
B_READY(IREQ)
B_REG
B_RESET
B_VS1
L2
V12
T12
R12
N13
T13
R13
P13
W14
R14
P14
W15
V15
T15
W16
V16
W17
R15
R19
R18
P16
P19
P18
N14
N15
M19
M18
AD1
AD2
B_VS2
AD3
B_WAIT
B_WE
AD4
AD5
B_WP(IOIS16)
C/BE0
AD6
AD7
C/BE1
AD8
C/BE2
AD9
C/BE3
L6
AD10
CLKRUN
CLOCK
DATA
F8
L4
AD11
A_CD2
AD12
A_CE1
D6
A5
L5
AD13
DEVSEL
FRAME
GND
A_CE2
AD14
A_DATA0
AD15
A_DATA1
M1
M5
A8
E8
A7
D7
F7
M6
M4
N7
AD16
GND
A16
C1
A_DATA2
AD17
GND
A_DATA3
AD18
B_CD2
GND
D8
A_DATA4
AD19
B_CE1
GND
F12
G1
A_DATA5
AD20
B_CE2
GND
A_DATA6
AD21
B_DATA0
B_DATA1
B_DATA2
B_DATA3
B_DATA4
GND
G19
M2
A_DATA7
AD22
GND
A_DATA8
AD23
D9
GND
N16
T4
A_DATA9
AD24
J18
J15
GND
A_DATA10
AD25
GND
T7
2–12
Table 2–6. 16-Bit PC Card Signal Names Sorted Alphanumerically to GJG Terminal Number (Continued)
TERM.
NO.
TERM.
NO.
TERM.
NO.
TERM.
NO.
SIGNAL NAME
GND
SIGNAL NAME
PHY_CTL0
SIGNAL NAME
SIGNAL NAME
ZV_PCLK
V14
W12
K14
P11
N19
T19
P12
W11
P7
W6
V6
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
A11
D14
E1
V4
V2
W4
R2
T1
R4
U1
T2
V1
U2
W2
N2
N4
N5
N6
P2
P4
P5
P6
R1
CC
GND
PHY_CTL1
PHY_DATA0
PHY_DATA1
PHY_DATA2
PHY_DATA3
PHY_DATA4
PHY_DATA5
PHY_DATA6
PHY_DATA7
PHY_LREQ
PRST
ZV_SCLK
ZV_SDATA
ZV_UV0
ZV_UV1
ZV_UV2
ZV_UV3
ZV_UV4
ZV_UV5
ZV_UV6
ZV_UV7
ZV_VSYNC
ZV_Y0
CC
GNT
R7
CC
GRST
V7
E6
CC
IDSEL/MFUNC7
IRDY
W7
P8
E19
J14
P1
CC
CC
IRQSER
LATCH
W8
V8
CC
P15
T5
CC
LINKON
LPS
T8
CC
V5
R8
V10
V13
B6
CC
MFUNC0
MFUNC1
MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6
PAR
W10
P10
P9
R6
CC
K19
L14
R11
V9
CCA
CCA
CCA
CCB
CCB
CCP
CCP
REQ
F1
R9
RI_OUT
K5
ZV_Y1
T9
SCL
B12
F18
N18
W13
N1
ZV_Y2
W5
R5
SDA
W9
W18
T10
V19
R10
U18
ZV_Y3
SERR
ZV_Y4
V17
K15
V18
T6
SPKROUT
STOP
ZV_Y5
PCLK
ZV_HREF
ZV_LRCLK
ZV_MCLK
ZV_Y6
PERR
SUSPEND
TRDY
V3
ZV_Y7
PHY_CLK
W3
2–13
The terminals are grouped in tables by functionality such as PCI system function, power supply function, etc., for quick
reference (see Table 2–7 through Table 2–21). The terminal names and numbers are also listed for convenient
reference.
Table 2–7. Power Supply Terminals
TERMINAL
FUNCTION
NAME
GFN NO.
GJG NO.
A3, A16, C1, D8, F12, G1,
G19, M2, N16, T4, T7, V14,
W12
A1, D4, D8, D13, D17, H4, H17,
N4, N17, U4, U8, U13, U17
GND
Device ground terminals
D6, D11, D15, F4, F17, K4, L17,
R4, R17, U6, U10, U15
A11, D14, E1, E6, E19, J14,
P1, P15, T5, V10, V13
Power supply terminal for core logic (3.3 Vdc)
V
CC
Clamp voltage for PC Card A interface. Indicates Card A
signaling environment.
B5, F3, L4
B6, F1, K5
V
CCA
Clamp voltage for PC Card B interface. Indicates Card B
signaling environment.
B13, E19
P19, V14
B12, F18
N18, W13
V
V
CCB
Clamp voltage for PCI signaling (3.3 Vdc or 5 Vdc)
CCP
Table 2–8. PC Card Power Switch Terminals
TERMINAL
GFN NO.
I/O
FUNCTION
NAME
GJG NO.
3-line power switch clock. Information on the DATA line is sampled at the rising edge of
CLOCK. This terminal defaults as an input which means an external clock source must
be used. If the internal ring oscillator is used, then an external CLOCK source is not
required. The internal oscillator may be enabled by setting bit 27 (P2CCLK) of the system
control register (PCI offset 80h, see Section 4.28) to a 1b.
CLOCK
U12
T11
I/O
A 43 kW pulldown resistor should be tied to this terminal.
3-line power switch data. DATA is used to serially communicate socket power-control
information to the power switch.
DATA
V12
V11
O
O
3-line power switch latch. LATCH is asserted by the PCI4451 to indicate to the PC Card
power switch that the data on the DATA line is valid.
LATCH
W12
W11
Table 2–9. PCI System Terminals
TERMINAL
GFN NO.
I/O
I/O
I
FUNCTION
NAME
GJG NO.
PCI clock run. CLKRUN is used by the central resource to request permission to stop the
PCI clock or to slow it down, and the PCI4451 responds accordingly. If CLKRUN is not
implemented, then this terminal should be tied low. CLKRUN is enabled by default by bit 1
(KEEPCLK) in the system control register (PCI offset 80h, see Section 4.28).
K18
K17
K18
K15
CLKRUN
PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are
sampled at the rising edge of PCLK.
PCLK
PRST
PCI bus reset. When the PCI bus reset is asserted, PRST causes the PCI4451 to place all
output buffers in a high-impedance state and reset all internal registers. When PRST is
asserted, the device is completely nonfunctional. After PRST is deasserted, the PCI4451 is
in its default state. When the SUSPEND mode is enabled, the device is protected from the
PRST and the internal registers are preserved. All outputs are placed in a high-impedance
state, but the contents of the registers are preserved.
K19
Y12
K19
P11
I
I
Global reset. When the global reset is asserted, the GRST signal causes the PCI4451 to
place all output buffers in a high-impedance state and reset all internal registers. When
GRST is asserted, the device is completely in its default state. For systems that require
wake-up from D3, GRST will normally be asserted only during initial boot. PRST should be
asserted following initial boot so that PME context is retained when transitioning from D3 to
D0. For systems that do not require wake-up from D3, GRST should be tied to PRST.
GRST
2–14
Table 2–10. PCI Address and Data Terminals
TERMINAL
I/O
FUNCTION
NAME GFN NO. GJG NO.
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
L18
L19
L15
L18
M20
M19
M18
M17
N20
N19
P18
R20
R19
P17
R18
T20
T19
T18
Y19
W18
V17
U16
Y18
W17
V16
Y17
V15
U14
Y16
W15
Y15
W14
Y14
V13
L19
L16
M15
M16
M18
M19
N15
N14
P18
P19
P16
R18
R19
R15
W17
V16
W16
T15
V15
W15
P14
R14
W14
P13
R13
T13
N13
R12
T12
V12
PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the
primary interface. During the address phase of a primary bus PCI cycle, AD31–AD0 contain a 32-bit
address or other destination information. During the data phase, AD31–AD0 contain data.
I/O
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
PCI bus commands and byte enables. These signals are multiplexed on the same PCI terminals.
During the address phase of a primary bus PCI cycle, C/BE3–C/BE0 define the bus command.
During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which
byte paths of the full 32-bit data bus carry meaningful data. C/BE0 applies to byte 0 (AD7–AD0),
C/BE1 applies to byte 1 (AD15–AD8), C/BE2 applies to byte 2 (AD23–AD16), and C/BE3 applies to
byte 3 (AD31–AD24).
N18
U20
V18
W16
M14
R16
T16
T14
C/BE3
C/BE2
C/BE1
C/BE0
I/O
I/O
PCI bus parity. In all PCI bus read and write cycles, the PCI4451 calculates even parity across the
AD31–AD0 and C/BE3–C/BE0 buses. As an initiator during PCI cycles, the PCI4451 outputs this
parity indicator with a one-PCLK delay. As a target during PCI cycles, the calculated parity is
compared to the initiator’s parity indicator. A compare error results in the assertion of a parity error
(PERR).
PAR
W19
V17
2–15
Table 2–11. PCI Interface Control Terminals
TERMINAL
GFN NO. GJG NO.
I/O
FUNCTION
NAME
PCI device select. The PCI4451 asserts DEVSEL to claim a PCI cycle as the target device.
As a PCI initiator on the bus, the PCI4451 monitors DEVSEL until a target responds. If no
target responds before time-out occurs, then the PCI4451 terminates the cycle with an
initiator abort.
U19
U19
I/O
DEVSEL
PCI cycle frame. FRAME is driven by the initiator of a bus cycle. FRAME is asserted to
indicate that a bus transaction is beginning, and data transfers continue while this signal
is asserted. When FRAME is deasserted, the PCI bus transaction is in the final data phase.
V20
K20
T18
K14
I/O
I
FRAME
GNT
PCI bus grant. GNT is driven by the PCI bus arbiter to grant the PCI4451 access to the PCI
bus after the current data transaction has completed. GNT may or may not follow a PCI bus
request, depending on the PCI bus parking algorithm.
PCI bus lock. MFUNC7/LOCK can be configured as PCI LOCK and used to gain exclusive
access downstream. Since this functionality is not typically used, other functions may be
accessed through this terminal. MFUNC7/LOCK defaults to and can be configured
through the multifunction routing status register (PCI offset 8Ch, see Section 4.36).
LOCK
P20
P20
T17
N19
N19
T19
I/O
(MFUNC7)
Initialization device select. IDSEL selects the PCI4451 during configuration space
accesses. IDSEL can be connected to one of the upper 21 PCI address lines on the PCI
†
bus (AD31–AD11). If the LATCH terminal (GFN terminal W12/GJG terminal W11) has
IDSEL/MFUNC7
IRDY
I
an external pulldown resistor, then this terminal is configurable as MFUNC7 and IDSEL
defaults to the AD23 terminal.
PCI initiator ready. IRDY indicates the PCI bus initiator’s ability to complete the current data
phase of the transaction. A data phase is completed on a rising edge of PCLK where both
IRDY and TRDY are asserted. Until IRDY and TRDY are both sampled asserted, wait states
are inserted.
I/O
PCI parity error indicator. PERR is driven by a PCI device to indicate that calculated parity
does not match PAR when PERR is enabled through bit 6 of the command register (PCI
offset 04h, see Section 4.4).
W20
L20
V18
L14
I/O
O
PERR
REQ
PCI bus request. REQ is asserted by the PCI4451 to request access to the PCI bus as an
initiator.
PCI system error. SERR is an output that is pulsed from the PCI4451 when enabled through
bit 8 of the command register (PCI offset 04h, see Section 4.4), indicating a system error
has occurred. The PCI4451 need not be the target of the PCI cycle to assert this signal.
When SERR is enabled by bit 1 in the bridge control register (PCI offset 3Eh, see
Section 4.24), this signal also pulses, indicating that an address parity error has occurred
on a CardBus interface.
Y20
W18
O
SERR
PCI cycle stop signal. STOP is driven by a PCI target to request the initiator to stop the
current PCI bus transaction. STOP is used for target disconnects and is commonly asserted
by target devices that do not support burst data transfers.
V19
U18
V19
U18
I/O
I/O
STOP
TRDY
PCI target ready. TRDY indicates the primary bus target’s ability to complete the current
data phase of the transaction. A data phase is completed on a rising edge of PCLK when
both IRDY and TRDY are asserted. Until both IRDY and TRDY are asserted, wait states
are inserted.
†
Care must be exercised in selection of the address line that is used for connecting to IDSEL. Check each PCI component to avoid the use of
address lines that it may have reserved, because address lines used can vary from one device to another of the same device type. For example,
one commonly-used chipset uses lines AD11 and AD12, and assignment of IDSEL to either of those lines in an implementation using that chipset
would result in an address conflict.
2–16
Table 2–12. System Interrupt Terminals
TERMINAL
NAME GFN NO. GJG NO.
I/O
FUNCTION
Parallel PCI interrupt. INTA can be mapped to MFUNC0 when parallel PCI interrupts are
used.
INTA
W11
Y11
W10
P10
I/O
See Section 3.5, Programmable Interrupt Subsystem, for details on interrupt signaling.
MFUNC0/INTA defaults to a general-purpose input.
(MFUNC0)
Parallel PCI interrupt. INTB can be mapped to MFUNC1 when parallel PCI interrupts are
used.
INTB
I/O
See Section 3.5, Programmable Interrupt Subsystem, for details on interrupt signaling.
(MFUNC1)
MFUNC1/INTB defaults to a general-purpose input.
Parallel PCI interrupt. INTC can be mapped to MFUNC2 when parallel PCI interrupts are
used.
INTC
Y10
P9
I/O
I/O
See Section 3.5, Programmable Interrupt Subsystem, for details on interrupt signaling.
MFUNC2/INTC defaults to a general-purpose input.
(MFUNC2)
Serial interrupt signal. IRQSER provides the IRQSER-style serial interrupting scheme.
Serialized PCI interrupts can also be sent in the IRQSER stream. See Section 3.5,
Programmable Interrupt Subsystem, for details on interrupt signaling.
IRQSER
W13
P12
MFUNC6
MFUNC5
MFUNC4
MFUNC3
MFUNC2
MFUNC1
MFUNC0
Y4
V5
R5
W5
T9
Interrupt request/secondary functions multiplexed. The primary function of these terminals
is to provide programmable options supported by the PCI4451. These interrupt multiplexer
outputs can be mapped to various functions.
W9
All of these terminals have secondary functions, such as PCI interrupts, PC/PCI DMA, OHCI
LEDs, GPE request/grant, ring indicate output, and zoomed video status, that can be
selected with the appropriate programming of this register. When the secondary functions
are enabled, the respective terminals are not available for multifunction routing.
V10
Y10
Y11
W11
R9
O
O
P9
P10
W10
See Section 4.36, Multifunction Routing Status Register, for programming options.
Ring indicate out and power management event output. Terminal provides an output to the
system for ring-indicate or PME signals. Alternately, RI_OUT can be routed on MFUNC7.
RI_OUT/PME
Y13
R11
Table 2–13. PC/PCI DMA Terminals
TERMINAL
GFN NO. GJG NO.
I/O
FUNCTION
NAME
PCGNT
(MFUNC2)
Y10
V10
P20
W9
P9
R9
PC/PCI DMA grant. PCGNT is used to grant the DMA channel to a requester in a system
supporting the PC/PCI DMA scheme. PCGNT is available on MFUNC2 or MFUNC3.
I/O
O
PCGNT
(MFUNC3)
This terminal is also used for the serial EEPROM interface.
PCREQ
(MFUNC7)
N19
T9
PC/PCI DMA request. PCREQ is used to request DMA transfers as DREQ in a system
supporting the PC/PCI DMA scheme. PCREQ is available on MFUNC7, MFUNC4, or MFUNC0.
PCREQ
(MFUNC4)
This terminal is also used for the serial EEPROM interface.
PCREQ
(MFUNC0)
W11
W10
2–17
Table 2–14. Zoomed Video Terminals
TERMINAL
I/O AND MEMORY
I/O
FUNCTION
INTERFACE
SIGNAL
GFN
NO.
NAME
GJG NO.
P3
N1
N2
A10
A11
O
O
ZV_HREF
Horizontal sync to the zoomed video port
Vertical sync to the zoomed video port
R2
ZV_VSYNC
ZV_Y7
ZV_Y6
ZV_Y5
ZV_Y4
ZV_Y3
ZV_Y2
ZV_Y1
ZV_Y0
V1
U2
T3
U1
T2
R3
P4
T1
R1
P6
P5
P4
P2
N6
N5
N4
A20
A14
A19
A13
A18
A8
O
Video data to the zoomed video port in YV:4:2:2 format
A17
A9
ZV_UV7
ZV_UV6
ZV_UV5
ZV_UV4
ZV_UV3
ZV_UV2
ZV_UV1
ZV_UV0
Y2
W2
Y1
W1
V3
U3
V2
T4
W2
U2
V1
T2
U1
R4
T1
R2
A25
A12
A24
A15
A23
A16
A22
A21
O
Video data to the zoomed video port in YV:4:2:2 format
ZV_SCLK
ZV_MCLK
ZV_PCLK
ZV_LRCLK
ZV_SDATA
W3
W4
Y3
V4
U5
V2
W3
V4
A7
A6
O
O
O
O
O
Audio SCLK PCM
Audio MCLK PCM
IOIS16
INPACK
SPKR
Pixel clock to the zoomed video port
Audio LRCLK PCM
V3
W4
Audio SDATA PCM
2–18
Table 2–15. Miscellaneous Terminals
TERMINAL
I/O
FUNCTION
GFN
NO.
GJG
NO.
NAME
Multifunction terminal 0. Defaults as a general-purpose input (GPI0), and can be programmed
to perform various functions. See Section 4.36, Multifunction Routing Status Register, for
configuration details.
MFUNC0
W11
Y11
Y10
V10
W9
V5
W10
P10
P9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Multifunction terminal 1. Defaults as a general-purpose input (GPI1), and can be programmed
to perform various functions. See Section 4.36, Multifunction Routing Status Register, for
configuration details.
MFUNC1
MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6
Multifunction terminal 2. Defaults as a general-purpose input (GPI2), and can be programmed
to perform various functions. See Section 4.36, Multifunction Routing Status Register, for
configuration details.
Multifunction terminal 3. Defaults as a general-purpose input (GPI3), and can be programmed
to perform various functions. See Section 4.36, Multifunction Routing Status Register, for
configuration details.
R9
Multifunction terminal 4. Defaults as a high-impedance reserved input, and can be
programmed to perform various functions. See Section 4.36, Multifunction Routing Status
Register, for configuration details.
T9
Multifunction terminal 5. Defaults as a high-impedance reserved input, and can be
programmed to perform various functions. See Section 4.36, Multifunction Routing Status
Register, for configuration details.
W5
R5
Multifunction terminal 6. Defaults as a high-impedance reserved input, and can be
programmed to perform various functions. See Section 4.36, Multifunction Routing Status
Register, for configuration details.
Y4
IDSEL and multifunction terminal 7. Defaults as IDSEL, but may be used as a multifunction
terminal. See Section 4.36, Multifunction Routing Status Register and Section 3.4, PC Card
Applications Overview, for configuration details.
IDSEL/MFUNC7
P20
N19
Serial ROM clock. This terminal provides the SCL serial clock signaling in a two-wire serial
ROM implementation, and is sensed at reset for serial ROM detection.
SCL
SDA
W10
Y9
V9
I/O
I/O
Serial ROM data. This terminal provides the SDA serial data signaling in a two-wire serial ROM
implementation.
W9
Speaker output. SPKROUT is the output to the host system that can carry SPKR or CAUDIO
through the PCI4451 from the PC Card interface. SPKROUT is driven as the XOR combination
of card SPKR//CAUDIO inputs.
V11
U11
T10
R10
O
I
SPKROUT
SUSPEND
Suspend. SUSPEND is used to protect the internal registers from clearing when PRST is
asserted. See Section 3.6.6, Suspend Mode for details.
2–19
Table 2–16. 16-Bit PC Card Address and Data Terminals (slots A and B)
TERMINAL
GFN NO.
SLOT SLOT SLOT
GJG NO.
SLOT
I/O
FUNCTION
NAME
†
‡
†
‡
A
B
A
B
ADDR25
ADDR24
ADDR23
ADDR22
ADDR21
ADDR20
ADDR19
ADDR18
ADDR17
ADDR16
ADDR15
ADDR14
ADDR13
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
DATA15
DATA14
DATA13
DATA12
DATA11
DATA10
DATA9
G2
F1
G4
E2
D1
E4
D2
B1
A2
E3
E1
D3
C2
F2
C4
C5
B2
C3
G3
H3
H1
J4
A16
C16
A18
C17
B18
A20
C18
C19
E17
B17
D16
B19
B20
A17
E18
E20
C20
D18
B16
D14
A15
C14
A14
A13
D12
C12
G18
G19
H18
H20
J18
D9
G4
G5
F2
F5
E5
D2
C2
B2
B3
E2
F4
D1
B1
G6
A4
F6
D4
A2
G2
H1
H4
H5
J1
E14
A15
D15
B17
A18
B19
D16
D18
E16
A17
B16
C18
C19
E15
F15
G15
E18
D19
B15
B14
E13
B13
D13
D12
E12
D11
G18
H15
H18
H14
J16
E9
O
PC Card address. 16-bit PC Card address lines. ADDR25 is the most significant bit.
J2
K2
K3
K1
C6
A5
C7
B7
C8
R1
P1
N2
D7
B6
A6
A7
B8
P2
N3
N1
J5
J6
K6
A6
E7
B7
G7
B8
N7
M4
M6
F7
D7
A7
E8
A8
M5
M1
L5
B9
B9
DATA8
D10
F20
G20
H19
J17
J19
C9
F9
I/O
PC Card data. 16-bit PC Card data lines. DATA15 is the most significant bit.
DATA7
G13
H16
H19
J15
J18
D9
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
A9
A9
DATA0
C10
E10
†
‡
Terminal name for slot A is preceded with A_. For example, the full name for GFN terminal G2 is A_ADDR25.
Terminal name for slot B is preceded with B_. For example, the full name for GFN terminal A16 is B_ADDR25.
2–20
Table 2–17. 16-Bit PC Card Interface Control Terminals (slots A and B)
TERMINAL
GFN NO.
SLOT SLOT SLOT SLOT
GJG NO.
I/O
FUNCTION
NAME
†
‡
†
‡
A
B
A
B
Battery voltage detect 1. BVD1 is generated by 16-bit memory PC Cards that
include batteries. BVD1 and BVD2 indicate the condition of the batteries on a
memory PC Card. Both BVD1 and BVD2 are kept high when the battery is good.
When BVD2 is low and BVD1 is high, the battery is weak and should be replaced.
When BVD1 is low, the battery is no longer serviceable and the data in the memory
PC Card is lost. See Section 5.6, ExCA Card Status-Change Interrupt
Configuration Register, for the enable bits. See Section 5.5, ExCA Card
Status-Change Register and Section 5.2, ExCA Interface Status Register, for the
status bits for this signal.
BVD1
(STSCHG/RI)
M2
A11
L1
A10
I
Status change. STSCHG is used to alert the system to a change in the READY,
write protect, or battery voltage dead condition of a 16-bit I/O PC Card.
Ring indicate. RI is used by 16-bit modem cards to indicate a ring detection.
Battery voltage detect 2. BVD2 is generated by 16-bit memory PC Cards that
include batteries. BVD2 and BVD1 indicate the condition of the batteries on a
memory PC Card. Both BVD1 and BVD2 are high when the battery is good. When
BVD2 is low and BVD1 is high, the battery is weak and should be replaced. When
BVD1 is low, the battery is no longer serviceable and the data in the memory PC
Card is lost. See Section 5.6, ExCA Card Status-Change Interrupt Configuration
Register, for the enable bits. See Section 5.5, ExCA Card Status-Change Register
and Section 5.2, ExCA Interface Status Register, for the status bits for this signal.
BVD2
(SPKR)
M1
C11
L6
F10
I
Speaker. SPKR is an optional binary audio signal available only when the card and
socket have been configured for the 16-bit I/O interface. The audio signals from
cards A and B are combined by the PCI4451 and are output on SPKROUT.
DMA request. BVD2 can be used as the DMA request signal during DMA
operations to a 16-bit PC Card that supports DMA. The PC Card asserts BVD2 to
indicate a request for a DMA operation.
PC Card detect 1 and PC Card detect 2. CD1 and CD2 are internally connected to
ground on the PC Card. When a PC Card is inserted into a socket, CD1 and CD2
are pulled low. For signal status, see Section 5.2, ExCA Interface Status Register.
A8
J20
F8
L4
J19
CD1
CD2
I
M4
B10
D10
Card enable 1 and card enable 2. CE1 and CE2 enable even- and odd-numbered
address bytes. CE1 enables even-numbered address bytes, and CE2 enables
odd-numbered address bytes.
A4
B4
F19
G17
D6
A5
G16
G14
CE1
CE2
O
Input acknowledge. INPACK is asserted by the PC Card when it can respond to an
I/O read cycle at the current address.
INPACK
IORD
J3
B14
D20
J4
A13
F16
I
DMA request. INPACK can be used as the DMA request signal during DMA
operations from a 16-bit PC Card that supports DMA. If used as a strobe, then the
PC Card asserts this signal to indicate a request for a DMA operation.
I/O read. IORD is asserted by the PCI4451 to enable 16-bit I/O PC Card data output
during host I/O read cycles.
D5
D5
O
DMA write. IORD is used as the DMA write strobe during DMA operations from a
16-bit PC Card that supports DMA. The PCI4451 asserts IORD during DMA
transfers from the PC Card to host memory.
I/O write. IOWR is driven low by the PCI4451 to strobe write data into 16-bit I/O PC
Cards during host I/O write cycles.
B3
D19
B4
F14
O
IOWR
DMA read. IOWR is used as the DMA write strobe during DMA operations from a
16-bit PC Card that supports DMA. The PCI4451 asserts IOWR during transfers
from host memory to the PC Card.
†
‡
Terminal name for slot A is preceded with A_. For example, the full name for GFN terminal G2 is A_ADDR25.
Terminal name for slot B is preceded with B_. For example, the full name for GFN terminal A16 is B_ADDR25.
2–21
Table 2–17. 16-Bit PC Card Interface Control (slots A and B) (Continued)
TERMINAL
GFN NO.
GJG NO.
I/O
FUNCTION
NAME
SLOT SLOT SLOT SLOT
†
‡
†
‡
B
A
B
A
Output enable. OE is driven low by the PCI4451 to enable 16-bit memory PC Card
data output during host memory read cycles.
OE
A3
F18
B5
K2
F19
E11
O
DMA terminal count. OE is used as terminal count (TC) during DMA operations to
a 16-bit PC Card that supports DMA. The PCI4451 asserts OE to indicate TC for
a DMA write operation.
Ready. The ready function is provided by READY when the 16-bit PC Card and the
host socket are configured for the memory-only interface. READY is driven low by
the 16-bit memory PC Cards to indicate that the memory card circuits are busy
processing a previous write command. READY is driven high when the 16-bit
memory PC Card is ready to accept a new data transfer command.
READY
(IREQ)
L2
A12
I
Interrupt request. IREQ is asserted by a 16-bit I/O PC Card to indicate to the host
that a device on the 16-bit I /O PC Card requires service by the host software. IREQ
is high (deasserted) when no interrupt is requested.
Attribute memory select. REG remains high for all common memory accesses.
When REG is asserted, access is limited to attribute memory (OE or WE active) and
to the I/O space (IORD or IOWR active). Attribute memory is a separately accessed
section of card memory and is generally used to record card capacity and other
configuration and attribute information.
J1
C13
J2
A12
O
REG
DMA acknowledge. REG is used as a DMA acknowledge (DACK) during DMA
operations to a 16-bit PC Card that supports DMA. The PCI4451 asserts REG to
indicate a DMA operation. REG is used in conjunction with the DMA read (IOWR)
or DMA write (IORD) strobes to transfer data.
RESET
WAIT
H2
L3
B15
B11
H2
K4
F13
F11
O
I
PC Card reset. RESET forces a hard reset to a 16-bit PC Card.
Bus cycle wait. WAIT is driven by a 16-bit PC Card to delay the completion of (i.e.,
extend) the memory or I/O cycle in progress.
Write enable. WE is used to strobe memory write data into 16-bit memory PC Cards.
WE is also used for memory PC Cards that employ programmable memory
technologies.
WE
C1
A19
E4
B18
O
DMA terminal count. WE is used as TC during DMA operations to a 16-bit PC Card
that supports DMA. The PCI4451 asserts WE to indicate TC for a DMA read
operation.
Write protect. WP applies to 16-bit memory PC Cards. WP reflects the status of the
write-protect switch on 16-bit memory PC Cards. For 16-bit I/O cards, WP is used
for the 16-bit port (IOIS16) function.
I/O is 16 bits. IOIS16 applies to 16-bit I/O PC Cards. IOIS16 is asserted by the 16-bit
PC Card when the address on the bus corresponds to an address to which the 16-bit
PC Card responds, and the I/O port that is addressed is capable of 16-bit accesses.
WP
(IOIS16)
M3
A10
L2
B10
I
DMA request. WP can be used as the DMA request signal during DMA operations
to a 16-bit PC Card that supports DMA. If used, the PC Card asserts WP to indicate
a request for a DMA operation.
K1
H6
B11
A14
VS1
VS2
L1
G1
B12
C15
Voltage sense 1 and voltage sense 2. VS1 and VS2, when used in conjunction
with each other, determine the operating voltage of the 16-bit PC Card.
I/O
†
‡
Terminal name for slot A is preceded with A_. For example, the full name for terminal C1 is A_WE.
Terminal name for slot B is preceded with B_. For example, the full name for terminal A19 is B_WE.
2–22
Table 2–18. CardBus PC Card Interface System Terminals (slots A and B)
TERMINAL
GFN NO.
SLOT SLOT SLOT SLOT
GJG NO.
I/O
FUNCTION
NAME
†
‡
†
‡
A
B
A
B
CardBus PC Card clock. CCLK provides synchronous timing for all transactions on
the CardBus interface. All signals except CRST, CCLKRUN, CINT, CSTSCHG,
CAUDIO, CCD2, CCD1, and CVS2–CVS1 are sampled on the rising edge of CCLK,
and all timing parameters are defined with the rising edge of this signal. CCLK
operates at the PCI bus clock frequency, but it can be stopped in the low state or
slowed down for power savings.
CCLK
E3
B17
E2
A17
O
CardBus PC Card clock run. CCLKRUN is used by a CardBus PC Card to request
an increase in the CCLK frequency, and by the PCI4451 to indicate that the CCLK
frequency is decreased. CardBus clock run (CCLKRUN) follows the PCI clock run
(CLKRUN).
M3
H2
A10
B15
L2
B10
F13
O
CCLKRUN
CRST
CardBus PC Card reset. CRST is used to bring CardBus PC Card-specific registers,
sequencers, and signals to a known state. When CRST is asserted, all CardBus PC
Card signals must be placed in a high-impedance state, and the PCI4451 drives these
signals to a valid logic level. Assertion can be asynchronous to CCLK, but deassertion
must be synchronous to CCLK.
H2
I/O
†
‡
Terminal name for slot A is preceded with A_. For example, the full name for terminal E3 is A_CCLK.
Terminal name for slot B is preceded with B_. For example, the full name for terminal B17 is B_CCLK.
2–23
Table 2–19. CardBus PC Card Address and Data Terminals (slots A and B)
TERMINAL
GFN NO.
SLOT SLOT SLOT SLOT
GJG NO.
I/O
FUNCTION
NAME
†
‡
†
‡
A
B
A
B
CAD31
CAD30
CAD29
CAD28
CAD27
CAD26
CAD25
CAD24
CAD23
CAD22
CAD21
CAD20
CAD19
CAD18
CAD17
CAD16
CAD15
CAD14
CAD13
CAD12
CAD11
CAD10
CAD9
R1
P1
N3
N2
N1
K1
K3
K2
J2
D9
N7
M4
M1
M6
L5
E9
B9
B9
A9
A9
D10
C10
C12
D12
A13
A14
C14
A15
D14
A16
B16
C16
E17
D19
C20
D20
E18
F18
G17
E20
G18
F20
H18
G20
H20
H19
J18
J17
J19
F9
E10
D11
E12
D12
D13
B13
E13
B14
E14
B15
A15
E16
F14
E18
F16
F15
F19
G14
G15
G18
G13
H18
H16
H14
H19
J16
J15
J18
K6
J6
J5
J1
J4
H5
H4
H1
G4
G2
G5
B3
B4
D4
D5
A4
B5
A5
F6
A6
F7
B7
D7
G7
A7
B8
E8
A8
H1
H3
G2
G3
F1
A2
B3
B2
D5
C4
A3
B4
C5
C6
D7
C7
B6
B7
A6
C8
A7
B8
PC Card address and data. These signals make up the multiplexed CardBus address
and data bus on the CardBus interface. During the address phase of a CardBus cycle,
CAD31–CAD0 contain a 32-bit address. During the data phase of a CardBus cycle,
CAD31–CAD0 contain data. CAD31 is the most significant bit.
I/O
CAD8
CAD7
CAD6
CAD5
CAD4
CAD3
CAD2
CAD1
CAD0
CardBus bus commands and byte enables. CC/BE3–CC/BE0 are multiplexed on the
same CardBus terminals. During the address phase of
a CardBus cycle,
J1
F2
C3
A4
C13
A17
D18
F19
J2
G6
A2
D6
A12
E15
D19
G16
CC/BE3
CC/BE2
CC/BE1
CC/BE0
CC/BE3–CC/BE0 defines the bus command. During the data phase, this 4-bit bus is
used as byte enables. The byte enables determine which byte paths of the full 32-bit
data bus carry meaningful data. CC/BE0 applies to byte 0 (CAD7–CAD0), CC/BE1
applies to byte 1 (CAD15–CAD8), CC/BE2 applies to byte 2 (CAD23–CAD16), and
CC/BE3 applies to byte 3 (CAD31–CAD24).
I/O
I/O
CardBus parity. In all CardBus read and write cycles, the PCI4451 calculates even parity
across the CAD and CC/BE buses. As an initiator during CardBus cycles, the PCI4451
outputs CPAR with a one-CCLK delay. As a target during CardBus cycles, the calculated
parity is compared to the initiator’s parity indicator; a compare error results in a parity
error assertion.
CPAR
C2
B20
B1
C19
†
‡
Terminal name for slot A is preceded with A_. For example, the full name for terminal C2 is A_CPAR.
Terminal name for slot B is preceded with B_. For example, the full name for terminal B20 is B_CPAR.
2–24
Table 2–20. CardBus PC Card Interface Control Terminals (slots A and B)
TERMINAL
GFN NO.
SLOT SLOT SLOT SLOT
GJG NO.
I/O
FUNCTION
NAME
†
‡
†
‡
A
B
A
B
CardBus audio. CAUDIO is a digital input signal from a PC Card to the system
speaker. The PCI4451 supports the binary audio mode and outputs a binary signal
from the card to SPKROUT.
CAUDIO
CBLOCK
M1
D2
C11
C18
L6
F10
D16
I
C2
I/O
CardBus lock. CBLOCK is used to gain exclusive access to a target.
CardBus detect 1 and CardBus detect 2. CCD1 and CCD2 are used in conjunction
with CVS1 and CVS2 to identify card insertion and interrogate cards to determine the
operating voltage and card type.
CCD1
CCD2
A8
J20
F8
L4
J19
I
M4
B10
D10
CardBus device select. The PCI4451 asserts CDEVSEL to claim a CardBus cycle as
the target device. As a CardBus initiator on the bus, the PCI4451 monitors CDEVSEL
until a target responds. If no target responds before time-out occurs, then the
PCI4451 terminates the cycle with an initiator abort.
D1
G4
B18
A18
E5
F2
A18
D15
I/O
CDEVSEL
CFRAME
CardBus cycle frame. CFRAME is driven by the initiator of a CardBus bus cycle.
CFRAME is asserted to indicate that a bus transaction is beginning, and data
transfers continue while this signal is asserted. When CFRAME is deasserted, the
CardBus bus transaction is in the final data phase.
I/O
CardBus bus grant. CGNT is driven by the PCI4451 to grant a CardBus PC Card
access to the CardBus bus after the current data transaction has been completed.
C1
L2
A19
A12
E4
K2
B18
E11
I
I
CGNT
CINT
CardBus interrupt. CINT is asserted low by a CardBus PC Card to request interrupt
servicing from the host.
CardBus initiator ready. CIRDY indicates the ability of the CardBus initiator to
complete the current data phase of the transaction. A data phase is completed on a
rising edge of CCLK when both CIRDY and CTRDY are asserted. Until CIRDY and
CTRDY are both sampled asserted, wait states are inserted.
E1
D16
F4
B16
I/O
CIRDY
CardBus parity error. CPERR reports parity errors during CardBus transactions,
except during special cycles. It is driven low by a target two clocks following that data
when a parity error is detected.
D3
J3
B19
B14
D1
J4
C18
A13
I/O
I
CPERR
CREQ
CardBus request. CREQ indicates to the arbiter that the CardBus PC Card desires
use of the CardBus bus as an initiator.
CardBus system error. CSERR reports address parity errors and other system errors
that could lead to catastrophic results. CSERR is driven by the card synchronous to
CCLK, but deasserted by a weak pullup, and may take several CCLK periods. The
PCI4451 can report CSERR to the system by assertion of SERR on the PCI interface.
L3
B11
K4
F11
I
CSERR
CardBus stop. CSTOP is driven by a CardBus target to request the initiator to stop
the current CardBus transaction. CSTOP is used for target disconnects, and is
commonly asserted by target devices that do not support burst data transfers.
E4
A20
A11
D2
L1
B19
A10
I/O
I
CSTOP
CardBus status change. CSTSCHG alerts the system to a change in the card status
and is used as a wake-up mechanism.
M2
CSTSCHG
CardBus target ready. CTRDY indicates the ability of the CardBus target to complete
the current data phase of the transaction. A data phase is completed on a rising edge
of CCLK, when both CIRDY and CTRDY are asserted; until this time, wait states are
inserted.
E2
C17
F5
B17
I/O
I/O
CTRDY
CardBus voltage sense 1 and CardBus voltage sense 2. CVS1 and CVS2 are used
in conjunction with CCD1 and CCD2 to identify card insertion and interrogate cards
to determine the operating voltage and card type.
K1
H6
B11
A14
CVS1
CVS2
L1
G1
B12
C15
†
‡
Terminal name for slot A is preceded with A_. For example, the full name for terminal M1 is A_CAUDIO.
Terminal name for slot B is preceded with B_. For example, the full name for terminal C11 is B_CAUDIO.
2–25
Table 2–21. IEEE 1394 PHY/Link Interface Terminals
TERMINAL
GFN NO.
I/O
FUNCTION
NAME
GJG NO.
PHY-link interface control. These bidirectional signals control passage of
information between the PHY and link. The link can only drive these terminals
after the PHY has granted permission following a link request (LREQ).
PHY_CTL1
PHY_CTL0
W6
U7
V6
I/O
W6
V9
U9
Y8
W8
V8
Y7
W7
V7
R8
T8
PHY_DATA7
PHY_DATA6
PHY_DATA5
PHY_DATA4
PHY_DATA3
PHY_DATA2
PHY_DATA1
PHY_DATA0
V8
W8
P8
W7
V7
R7
PHY-link interface data. These bidirectional signals pass data between the PHY
and link. These terminals are driven by the link on transmissions and are driven
by the PHY on receptions. Only DATA1–DATA0 are valid for 100-Mbit speed.
DATA4–DATA0 are valid for 200-Mbit speed and DATA7–DATA0 are valid for
400-Mbit speed.
I/O
System clock. This input provides a 49.152 MHz clock signal for data
synchronization.
PHY_CLK
V6
Y5
T6
R6
I
Link request. This signal is driven by the link to initiate a request for the PHY to
perform some service.
O
PHY_LREQ
Y6
P7
V5
I
LINKON
LPS
1394 link on. This input from the PHY indicates that the link should turn on.
Link power status. LPS indicates that link is powered and fully functional.
W5
O
2–26
3 Feature/Protocol Descriptions
Figure 3–1 shows a simplified system implementation example using the PCI4451. The PCI interface includes all
address/data and control signals for PCI protocol. Highlighted in this diagram is the functionality supported by the
PCI4451. The PCI4451 supports PC/PCI DMA, PCI Way DMA (distributed DMA), PME wake-up from D3
through
cold
D0, four interrupt modes, an integrated zoomed video port, and 12 multifunction terminals (eight MFUNC and four
GPIO terminals) that can be programmed for a wide variety of functions.
PCI Bus
Activity LED’s
South Bridge
CLKRUN
IRQSER
TPS2216 or
Micrel 2564A
Power
PCI4451
Clock
2
ZV
Enable
DMA
PME
Switch
Embedded
Controller
23
4
4
PC Card
Socket A
Zoomed Video
68
VGA
23 for ZV†
Controller
19 Video
PC Card
Socket B
14
68
23 for ZV
Audio
Codec
OHCI-PHY
Interface
4 Audio
PHY
Interrupt Routing Options:
1) Serial ISA/Serial PCI
2) Serial ISA/Parallel PCI
1394 Ports
†
The PC Card interface is 68 terminals for CardBus and 16-bit PC Cards. In zoomed-video mode 23 terminals are used for routing the zoomed
video signals to the VGA controller and audio codec.
Figure 3–1. PCI4451 System Block Diagram
3.1 I/O Characteristics
Figure 3–2 shows a 3-state bidirectional buffer illustration for reference. Section 12.2, Recommended Operating
Conditions, provides the electrical characteristics of the inputs and outputs. The PCI4451 meets the ac specifications
of the 1995 PC Card Standard and the PCI Local Bus Specification.
3–1
V
CCP
Tied for Open Drain
OE
Pad
Figure 3–2. 3-State Bidirectional Buffer
3.2 Clamping Voltages
The I/O sites can be pulled through a clamping diode to a voltage rail for protection. The 3.3-V core power supply
is independent of the clamping voltages. The clamping (protection) diodes are required if the signaling environment
on an I/O is system dependent. For example, PCI signaling can be either 3.3 Vdc or 5.0 Vdc, and the PCI4451 must
reliably accommodate both voltage levels. This is accomplished by using a 3.3-V buffer with a clamping diode to V
.
CCP
If a system design requires a 5.0-V PCI bus, then V
must be connected to the 5.0-V power supply.
CCP
A standard die has only one clamping voltage for the sites as shown in Figure 3–2. After the terminal assignments
are fixed, the fabrication facility will support a design by splitting the clamping voltage for customization. The PCI4451
requires five separate clamping voltages since it supports a wide range of features. The five voltages are listed and
defined in Section 12.2, Recommended Operating Conditions.
3.3 Peripheral Component Interconnect (PCI) Interface
This section describes the PCI interface of the PCI4451, and how the device responds to and participates in PCI bus
cycles. The PCI4451 provides all required signals for PCI master/slave devices and may operate in either 5-V or 3.3-V
PCI signaling environments by connecting the V
terminals to the desired signaling level.
CCP
3.3.1 PCI Bus Lock (LOCK)
The bus locking protocol defined in the PCI Specification is not highly recommended, but is provided on the PCI4451
as an additional compatibility feature. The PCI LOCK terminal is multiplexed with GPIO2, and the terminal function
defaults to a general-purpose input (GPI). The use of LOCK is only supported by PCI-to-CardBus bridges in the
downstream direction (away from the processor).
PCI LOCK indicates an atomic operation that may require multiple transactions to complete. When LOCK is asserted,
nonexclusive transactions may proceed to an address that is not currently locked. A grant to start a transaction on
the PCI bus does not guarantee control of LOCK; control of LOCK is obtained under its own protocol. It is possible
for different initiators to use the PCI bus while a single master retains ownership of LOCK. To avoid confusion with
the PCI bus clock, the CardBus signal for this protocol is CBLOCK.
An agent may need to do an exclusive operation because a critical memory access to memory might be broken into
several transactions, but the master wants exclusive rights to a region of memory. The granularity of the lock is defined
by PCI to be 16 bytes aligned. The lock protocol defined by PCI allows a resource lock without interfering with
nonexclusive, real-time data transfer, such as video.
The PCI bus arbiter may be designed to support only complete bus locks using the LOCK protocol. In this scenario
the arbiter will not grant the bus to any other agent (other than the LOCK master) while LOCK is asserted. A complete
bus lock may have a significant impact on the performance of the video. The arbiter that supports complete bus lock
must grant the bus to the cache to perform a writeback due to a snoop to a modified line when a locked operation
is in progress.
The PCI4451 supports all LOCK protocol associated with PCI-to-PCI bridges, as also defined for PCI-to-CardBus
bridges. This includes disabling write posting while a locked operation is in progress, which can solve a potential
deadlock when using devices such as PCI-to-PCI bridges. The potential deadlock can occur if a CardBus target
3–2
supports delayed transactions and blocks access as the target until it completes a delayed read. This target
characteristic is prohibited by the PCI Specification Revision 2.2, and the issue is resolved by the PCI master using
LOCK.
3.3.2 PCI4451 EEPROM Map
Table 3–1 and Table 3–2 list the mapping of the bits that are loaded from EEPROM.
Table 3–1. EEPROM–OHCI Bit Mapping
PCI Offset/
EEPROM Offset
Register Bits Loaded from EEPROM
OHCI Offset
PCI 3Fh/3Eh
PCI 2Ch
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
MAX_LAT, bits 7–4 / MIN_GNT, bits 3–0
PCI subsystem identification (subsystem vendor ID), byte 0
PCI subsystem identification (subsystem vendor ID), byte 1
PCI subsystem identification (subsystem device ID), byte 2
PCI subsystem identification (subsystem device ID), byte 3
Link enhancement control, byte 0, bits 7, 2, 1
Mini ROM address
PCI 2Dh
PCI 2Eh
PCI 2Fh
PCI F4h
OHCI 24h
OHCI 25h
OHCI 26h
OHCI 27h
OHCI 28h
OHCI 29h
OHCI 2Ah
OHCI 2Bh
GUID high, byte 0
GUID high, byte 1
GUID high, byte 2
GUID high, byte 3
GUID low, byte 0
GUID low, byte 1
GUID low, byte 2
GUID low, byte 3
Checksum (Reserved—no bits loaded)
Link enhancement control, byte 1, bits 5, 4, 1, 0
PCI misccellaneous configuration, byte 0, bits 4, 2, 1, 0
PCI miscellaneous configuration, byte 1, bits 7, 5, 2
PCI F5h
PCI F0h
PCI F1h
3–3
Table 3–2. EEPROM–ExCA Bit Mapping
PCI Offset/
ExCA Offset
EEPROM Offset
Register Bits Loaded from EEPROM
Flag byte
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
PCI 43h
PCI 42h
PCI 41h
PCI 40h
PCI 80h
PCI 81h
PCI 82h
PCI 83h
PCI 86h
PCI 89h
PCI 8Bh
PCI 8Ch
PCI 8Dh
PCI 8Eh
PCI 8Fh
PCI 91h
PCI 92h
PCI 93h
PCI A3h
ExCA 00h
Subsystem ID, byte 1
Subsystem ID, byte 0
Subsystem vendor ID, byte 1
Subsystem vendor ID, byte 0
System control, byte 0, bits 6, 5, 4, 3, 1, 0
System control, byte 1, bits 7, 6
System control, byte 2, bits 6–0
System control, byte 3, bits 7, 6, 5, 3, 2, 0
General control, bits 3, 1, 0
General-purpose event enable, bits 7, 6, 3, 2, 1, 0
General-purpose output, bits 3–0
Multifunction routing status, byte 0
Multifunction routing status, byte 1
Multifunction routing status, byte 2
Multifunction routing status, byte 3
Card control, bits 7, 2, 1
Device control
Diagnostic, bits 7, 4–0
Power management capabilities, byte 1, bit 7
ExCA identification and revision
3.3.3 Loading The Subsystem Identification (EEPROM Interface)
The subsystem vendor ID register and subsystem ID register make up a double word of PCI configuration space
located at offset 40h for functions 0 and 1. This doubleword register, used for system and option card (mobile dock)
identification purposes, is required by some operating systems. Implementation of this unique identifier register is
a 1997 PC Card Standard requirement.
The PCI4451 offers two mechanisms to load a read-only value into the subsystem registers. The first mechanism
relies upon the system BIOS providing the subsystem ID value. The default access mode to the subsystem registers
is read-only, but the access mode may be made read/write by clearing the SUBSYSRW, bit 5 of the system control
register (PCI offset 80h, see Section4.28). Once this bit is cleared (0), the BIOS may write a subsystem identification
value into the registers at offset 40h. The BIOS must set the SUBSYSRW bit such that the subsystem vendor ID
register and subsystem ID register are limited to read-only access. This approach saves the added cost of
implementing the serial EEPROM.
In some conditions, such as in a docking environment, the subsystem vendor ID register and subsystem ID register
must be loaded with a unique identifier through a serial EEPROM interface. The PCI4451 loads the double-word of
data from the serial EEPROM after a reset of the primary bus. The SUSPEND input gates the PRST and G_RST from
the entire PCI4451 core, including the serial EEPROM state machine. See Section 3.6.6, Suspend Mode, for details
on using SUSPEND. The PCI4451 provides a two-line serial bus interface to the serial EEPROM.
The system designer must implement a pulldown resistor on the PCI4451 LATCH terminal to indicate the serial
EEPROM mode. Only when this pulldown resistor is present will the PCI4451 attempt to load data through the serial
EEPROM interface. The serial EEPROM interface is a two-terminal interface with one data signal (SDA) and one
clock signal (SCL). Figure 3–3 illustrates a typical PCI4451 application using the serial EEPROM interface.
3–4
V
CC
Serial
EEPROM
A0
SCL
SDA
A1 SCL
A2 SDA
PCI4451
Figure 3–3. Serial EEPROM Application
As stated above, when the PCI4451 is reset by G_RST, the subsystem data is read automatically from the EEPROM.
The PCI4451 masters the serial EEPROM bus and reads four bytes as described in Figure 3–4.
Slave Address
Word Address
Slave Address
S
b6 b5 b4 b3 b2 b1 b0
0
A
b7 b6 b5 b4 b3 b2 b1 b0
A
S
b6 b5 b4 b3 b2 b1 b0
1
A
Start
R/W
Restart
R/W
Data Byte 0
M
Data Byte 1
M
Data Byte 2
M
Data Byte 3
M
P
Stop
S/P – Start/Stop Condition
A – Slave Acknowledgment
M – Master Acknowledgment
Figure 3–4. EEPROM Interface Subsystem Data Collection
The EEPROM is addressed at word address A0h (1010 0000b), as indicated in Figure 3–4, and the address
auto-increments after each byte transfers according to the protocol. Thus, to provide the subsystem register with data
AABBCCDDh the EEPROM should be programmed with address 0 = AAh, 1 = BBh, 2 = CCh, and 3 = DDh.
The serial EEPROM is addressed at slave address 1010 000b by the PCI4451. All hardware address bits for the
EEPROM should be tied to the appropriate level to achieve this address. The serial EEPROM chip in the sample
application circuit, Figure 3–3, assumes the 1010b high address nibble. The lower three address bits are terminal
inputs to the chip, and the sample application shows these terminal inputs tied to GND.
The serial EEPROM interface signals require pullup resistors. The serial EEPROM protocol allows bidirectional
transfers. Both the SCL and SDA signals are placed in a high-impedance state and pulled high when the bus is not
active. When the SDA line transitions to a logic low, this signals a start condition (S). A low-to-high transition of SDA
while SCL is high is defined as the stop condition (P). One bit is transferred during each clock pulse. The data on the
SDA line must remain stable during the high period of the clock pulse, as changes in the data line at this time will be
interpreted as a control signal. Data is valid and stable during the clock high period. Figure 3–5 illustrates this protocol.
3–5
SDA
SCL
Start
Stop
Change of
Condition
Condition
Data Allowed
Data Line Stable,
Data Valid
Figure 3–5. Serial EEPROM Start/Stop Conditions and BIt Transfers
Each address byte and data transfer is followed by an acknowledge bit, as indicated in Figure 3–4. When the PCI4451
transmits the addresses, it returns the SDA signal to the high state and places the line in a high-impedance state.
The PCI4451 then generates an SCL clock cycle and expects the EEPROM to pull down the SDA line during the
acknowledge pulse. This procedure is referred to as a slave acknowledge with the PCI4451 transmitter and the
EEPROM receiver. Figure 3–6 illustrates general acknowledges.
During the data byte transfers from the serial EEPROM to the PCI4451, the EEPROM clocks the SCL signal. After
the EEPROM transmits the data to the PCI4451, it returns the SDA signal to the high state and places the line in a
high-impedance state. The EEPROM then generates an SCL clock cycle and expects the PCI4451 to pull down the
SDA line during the acknowledge pulse. This procedure is referred to as a master acknowledge with the EEPROM
transmitter and the PCI4451 receiver. Figure 3–6 illustrates general acknowledges.
SCL From
1
2
3
7
8
9
Master
SDA Output
By Transmitter
SDA Output
By Receiver
Figure 3–6. Serial EEPROM Protocol – Acknowledge
EEPROM interface status information is communicated through the general status register (PCI offset 85h, see
Section 4.30). Bit 2 (EEDETECT) in this register indicates whether or not the PCI4451 serial EEPROM circuitry
detects the pulldown resistor on LATCH. An error condition, such as a missing acknowledge, results in bit 1
(DATAERR) bit being set. Bit 0 (EEBUSY) bit is set while the subsystem ID register is loading (serial EEPROM
interface is busy).
3.3.4 Serial Bus EEPROM Application
When the PCI bus is reset and the serial bus interface is detected, the PCI4451 attempts to read the subsystem
identification and other register defaults from a serial EEPROM. The registers and corresponding bits that may be
loaded with defaults through the EEPROM are provided in Table 3–1.
3–6
Table 3–3. PCI Registers and Bits Loadable Through Serial EEPROM
EEPROM OFFSET
REFERENCE
PCI
OFFSET
BITS LOADED FROM EEPROM TO
CORRESPONDING BITS IN REGISTER
REGISTER NAME
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
PCI 43h
PCI 42h
PCI 41h
PCI 40h
PCI 80h
PCI 81h
PCI 82h
PCI 83h
PCI 86h
PCI 89h
PCI 8Bh
PCI 8Ch
PCI 8Dh
PCI 8Eh
PCI 8Fh
PCI 91h
PCI 92h
PCI 93h
PCI A2h
Subsystem ID (see Section 4.26)
Byte 1
Subsystem ID (see Section 4.26)
Byte 0
Subsystem vendor ID (see Section 4.25)
Subsystem vendor ID (see Section 4.25)
System control (see Section 4.28)
Byte 1
Byte 0
Byte 0, bits 6, 5, 4, 3, 1, 0
Byte 1, bits 7, 6
Byte 2, bits 6–0
Byte 3, bits 7, 6, 5, 3, 2, 0
No bits loaded
Bits 7, 6, 3, 2, 1, 0
Bits 3–0
System control (see Section 4.28)
System control (see Section 4.28)
System control (see Section 4.28)
Reserved
General-purpose event enable (see Section 4.33)
General-purpose output (see Section 4.35)
Multifunction routing status (see Section 4.36)
Multifunction routing status (see Section 4.36)
Multifunction routing status (see Section 4.36)
Multifunction routing status (see Section 4.36)
Card control (see Section 4.38)
Byte 0
Byte 1
Byte 2
Byte 3
Bits 7, 2, 1
Bits 7–0
Device control (see Section 4.39)
Diagnostic (see Section 4.40)
Bits 7, 4–0
Bit 15
Power management capabilities (see Section 4.45)
ExCA 00h ExCA identificaton and revision (see Section 5.1)
Bits 7–0
The EEPROM data format is detailed in Figure 3–7. This format must be followed for the PCI4451 to load initializations
properly from a serial EEPROM. Any undefined condition results in a terminated load and sets the DATAERR bit in
the general status register (see Section 4.30).
3–7
Slave Address = 1010 0000b
PCI Offset
Word Address 21h
Reference(0)
PCI Offset
Reference(n)
Byte 3 (0)
Byte 2 (0)
Byte 1 (0)
Byte 0 (0)
RSVD
Word Address 22h
Word Address 23h
Word Address 24h
Word Address 25h
Word Address 8 × (n+3) + 1
Byte 3 (n)
Byte 2 (n)
Byte 1 (n)
Byte 0 (n)
RSVD
Word Address 8 × (n+3) + 2
Word Address 8 × (n+3) + 3
Word Address 8 × (n+3) + 4
Word Address 8 × (n+3) + 5
RSVD
RSVD
RSVD
PCI Offset
Reference(1)
Word Address 29h
RSVD
EOL = FFh
Word Address 8 × (n+4) + 1
Figure 3–7. EEPROM Data Format
The byte at EEPROM word address 00h must contain either a valid PCI offset, as listed in Table 3–1, or an end-of-list
(EOL) indicator. The EOL indicator is a byte value of FFh, and indicates the end of the data to load from the EEPROM.
Only doubleword registers are loaded from the EEPROM, and all bit fields must be considered when programming
the EEPROM.
The serial EEPROM is addressed at slave address 1010 0000b by the PCI4451. All hardware addres bits for the
EEPROM should be tied to the appropriate level to achieve this address. The serial EEPROM chip in the sample
application circuit (Figure 3–3) assumes the 1010b high-address nibble. The lower three address bits are terminal
inputs to the chip, and the sample application shows these terminal inputs tied to GND.
When a valid offset reference is read, four bytes are read from the EEPROM, MSB first, as illustrated in Figure 3–4.
The address autoincrements after every byte transfer according to the doubleword read protocol. Note that the word
addresses align with the data format illustrated in Figure 3–7. The PCI4451 continues to load data from the serial
EEPROM until an end-of-list indicator is read. Three reserved bytes are stuffed to maintain eight-byte data structures.
Note that the eight-byte data structure is important to provide correct addressing per the doubleword read format
shown in Figure 3–4. In addition, the reference offsets must be loaded in the EEPROM in sequential order, that is,
01h, 02h, 03h, 04h. If the offsets are not sequential, the registers will be loaded incorrectly.
3.4 PC Card Applications Overview
This section describes the PC Card interfaces of the PCI4451. A discussion on PC Card recognition details the card
2
interrogation procedure. This section discusses the card powering procedure, including the protocol of the P C power
switch interface. The internal ZV buffering provided by the PCI4451 and programming model is detailed in this section.
Also, standard PC Card register models are described, as well as a brief discussion of the PC Card software protocol
layers.
3.4.1 PC Card Insertion/Removal and Recognition
The 1995 PC Card Standard addresses the card detection and recognition process through an interrogation
procedure that the socket must initiate upon card insertion into a cold, unpowered socket. Through this interrogation,
card voltage requirements and interface (16-bit vs. CardBus) are determined.
3–8
The scheme uses the CD1, CD2, VS1, and VS2 signals (CCD1, CCD2, CVS1, CVS2 for CardBus). A PC Card
designer connects these four terminals in a certain configuration depending on the type of card and the supply
voltage. The encoding scheme for this, defined in the 1997 PC Card Standard, is shown in Table 3–4.
Table 3–4. PC Card – Card Detect and Voltage Sense Connections
CD2//CCD2
Ground
CD1//CCD1
Ground
VS2//CVS2
Open
VS1//CVS1
Open
Key
5 V
5 V
Interface
Voltage
5 V
16-bit PC Card
16-bit PC Card
Ground
Ground
Open
Ground
5 V and 3.3 V
5 V, 3.3 V, and
X.X V
Ground
Ground
Ground
Ground
5 V
16-bit PC Card
Ground
Ground
Ground
Connect to CVS1
Ground
Open
Open
Ground
Connect to CCD1
Ground
LV
LV
LV
LV
16-bit PC Card
CardBus PC Card
16-bit PC Card
3.3 V
3.3 V
Ground
Ground
3.3 V and X.X V
3.3 V and X.X V
3.3 V, X.X V, and
Y.Y V
Connect to CVS2
Ground
Connect to CCD2
Ground
CardBus PC Card
Connect to CVS1
Ground
Ground
Connect to CCD2
LV
CardBus PC Card
Ground
Connect to CVS2
Ground
Ground
Ground
Ground
Connect to CCD2
Connect to CCD1
Open
Open
Open
LV
LV
LV
LV
16-bit PC Card
CardBus PC Card
CardBus PC Card
CardBus PC Card
Reserved
Y.Y V
Y.Y V
Connect to CVS2
Ground
Open
X.X V and Y.Y V
Y.Y V
Connect to CVS1
Ground
Connect to CCD2
Connect to CCD1
Ground
Connect to CVS1
Connect to CVS2
Ground
Ground
Connect to CCD1
Reserved
2
3.4.2 P C Power Switch Interface
2
A power switch with a PCMCIA-to-peripheral control (P C) interface is required for the PC Card powering interface.
2
The TI TPS2216, TPS2202/2206, or Micrel 2564A dual-slot PC card power-interface switch provides the P C
interface to the CLOCK, DATA, and LATCH terminals of the PCI4451. Figure 3–8 shows the terminal assignments
of the TPS2206. Figure 3–9 illustrates a typical application where the PCI4451 represents the PCMCIA controller.
There are two ways to provide a clock source to the power switch interface. The first method is to provide an external
clock source such as a 32 kHz real time clock to the CLOCK terminal. The second method is to use the internal ring
oscillator. If the internal ring oscillator is used, then the PCI4451 provides its own clock source for the PC Card
interrogation logic and the power switch interface. The mode of operation is determined by the setting of bit 27 of the
system control register (PCI offset 80h, see Section 4.28). This bit is encoded as follows:
0 = CLOCK terminal (GFN terminal U12, GJG terminal T11) is an input (default).
1 = CLOCK terminal is an output that utilizes the internal oscillator.
A 43-kW pulldown resistor should be tied to the CLOCK terminal.
3–9
1
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
5V
5V
5V
NC
NC
NC
NC
NC
12V
BVPP
BVCC
BVCC
BVCC
NC
OC
3.3V
3.3V
2
3
DATA
CLOCK
LATCH
RESET
12V
AVPP
AVCC
AVCC
AVCC
GND
4
5
6
7
8
9
10
11
12
13
14
15
NC
RESET
3.3V
NC – No internal connection
Figure 3–8. TPS2206 Terminal Assignments
Power Supply
PC Card A
PP1
TPS2206
V
12 V
5 V
12 V
5 V
AVPP
V
V
V
PP2
3.3 V
3.3 V
AVCC
AVCC
AVCC
CC
CC
Supervisor
RESET
PC Card B
V
PP1
BVPP
V
V
V
PP2
BVCC
BVCC
BVCC
CC
3
CC
PCI4451
Serial I/F
PC Card Interface (68 terminals/socket)
Figure 3–9. TPS2206 Typical Application
3.4.3 Zoomed Video Support
The zoomed video (ZV) port on the PCI4451 provides an internally buffered 16-bit ZV PC Card data path. This internal
routing is programmed through the multimedia control register. Figure 3–9 summarizes the zoomed video subsystem
implemented in the PCI4451, and details the bit functions found in the multimedia control register.
An output port (PORTSEL) is always selected. The PCI4451 defaults to socket 0 (see Multimedia Control Register,
Section 4.29). When ZVOUTEN is enabled, the zoomed video output terminals are enabled and allow the PCI4451
to route the zoomed video data. However, no data is transmitted unless either ZVEN0 or ZVEN1 is enabled in the
multimedia control register. If the PORTSEL maps to a card port that is disabled (ZVEN0 = 0 or ZVEN1 = 0), then
the zoomed video port is driven low (i.e., no data is transmitted).
3–10
Zoomed Video Subsystem
Card Output
Enable Logic
ZVEN0
ZVOUTEN
PC Card
PC Card
Socket 0
I/F
†
ZVSTAT
23
VGA
19 Video Signals
PORTSEL
PC Card
Socket 1
PC Card
I/F
Audio
Codec
4 Audio Signals
ZVEN1
Card Output
Enable Logic
†
ZVSTAT must be enabled through the GPIO Control Register.
Figure 3–10. Zoomed Video Subsystem
3.4.4 Zoomed Video Autodetect
Zoomed video autodetect, when enabled, allows the PCI4451 to automatically detect zoomed video data by sensing
the pixel clock from each socket and/or from a third zoomed video source that may exist on the motherboard. The
PCI4451 automatically switches the internal zoomed video MUX to route the zoomed video stream to the PCI4451
zoomed video output port. This eliminates the need for software to switch the internal MUX using bits 6 and 7 of the
multimedia control register (PCI offset 84h, see Section 4.29).
The PCI4451 can be programmed to switch a third zoomed video source by programming MFUNC2 or MFUNC3 as
a zoomed video pixel clock sense terminal and connecting this terminal to the pixel clock of the third zoomed video
source. ZVSTAT may then be programmed onto MFUNC4, MFUNC1, or MFUNC0 and this signal may switch the
zoomed video buffers from the third zoomed video source. To account for the possibility of several zoomed video
sources being enabled at the same time, a programmable priority scheme may be enabled.
3–11
Zoomed Video Subsystem
Card Output
Enable Logic
3rd Zoomed Video Source
ZVEN0
Pixel Clock Sense
Programmed on
23
MFUNC2 or MFUNC3
PC Card
I/F
PC Card
Socket 0
Buffers
Enable
23
ZVSTAT
Pixel Clock Sense
23
23
23
23
Auto Z/V Arbiter
and Buffer
VGA
19 Video Signals
ZV Data
Pixel Clock Sense
23
PC Card
Socket 1
Audio
Codec
PC Card
I/F
4 Audio Signals
ZVEN1
Card Output
Enable Logic
Figure 3–11. Zoomed Video with Autodetect Enabled
The PCI4451 defaults with zoomed video autodetect disabled so that it will function exactly like the PCI1250A and
PCI1450. To enable zoomed video autodetect and the programmable priority scheme, the following bits must be set:
•
•
Multimedia control register (PCI offset 84h) bit 5: Writing a 1b enables zoomed video auto-detect
Multimedia control register (PCI offset 84h) bits 4–2: Set the programmable priority scheme
000 = Slot A, Slot B, External Source
001 = Slot A, External Source, Slot B
010 = Slot B, Slot A, External Source
011 = Slot B, External Source, Slot A
100 = External Source, Slot A, Slot B
101 = External Source, Slot B, Slot A
110 = External Source, Slot B, Slot A
111 = Reserved
If it is desired to switch a third zoomed video source, then the following bits must also be set:
•
Multifunction routing register (PCI offset 8Ch), bits 14–12 or 10–8: Write 111b to program MFUNC3 or
MFUNC2, respectively, as a pixel clock input terminal.
•
Multifunction routing register (PCI offset 8Ch), bits 18–16, 6–4, or 2–0: Write 111b to program the MFUNC4,
MFUNC1, or MFUNC0 terminal, respectively.
3–12
3.4.5 Ultra Zoomed Video
Ultra zoomed video is an enhancement to the PCI4451 DMA engine and is intended to improve the 16-bit bandwidth
for MPEG I and MPEG II decoder PC Cards. This enhancement allows the PCI4451 to fetch 32 bits of data from
memory versus the 11XX/12XX 16-bit fetch capability. This enhancement allows a higher sustained throughput to
the 16-bit PC Card, because the PCI4451 prefetches an extra 16 bits (32 bits total) during each PCI read transaction.
If the PCI Bus becomes busy, then the PCI4451 has an extra 16 bits of data to perform back-to-back 16-bit
transactions to the PC Card before having to fetch more data. This feature is built into the DMA engine and software
is not required to enable this enhancement.
NOTE: The 11XX and 12XX families of CardBus controllers have enough 16-bit bandwidth to
support MPEG II PC Card decoders. But it was decided to improve the bandwidth even more
in the 44XX family CardBus controllers.
3.4.6 D3_STAT Terminal
Additional functionality in the PCI4451 compared with the 1250A/1251 series is the D3_STAT (D3 status) terminal.
This terminal is asserted under the following two conditions (both conditions must be true before D3_STAT is
asserted):
•
•
Function 0 and function 1 are placed in D3
PME is enabled on either function
The intent of including this feature in the PCI4451 is to use this terminal to switch an external V /V
switch. This
CC AUX
feature can be programmed on MFUNC7, MFUNC6, MFUNC2, or MFUNC1 by writing 100b to the appropriate
multifunction routing status register bits (PCI offset 8Ch, see Section 4.36).
3.4.7 Internal Ring Oscillator
The internal ring oscillator provides an internal clock source for the PCI4451 so that neither the PCI clock nor an
external clock is required in order for the PCI4451 to power down a socket or interrogate a PC Card. This internal
oscillator operates nominally at 16 kHz and can be enabled by setting bit 27 of the system control register (PCI offset
80h, see Section 4.28) to1b. This function is disabled by default.
3–13
3.4.8 Integrated Pullup Resistors
The 1997 PC Card Standard requires pullup resistors on various terminals to support both CardBus and 16-bit card
configurations. Unlike the PCI1450/4450 which required external pullup resistors, the PCI4451 has integrated all of
these pullup resistors, except for the WP(IOIS16)/CLKRUN pullup resistor.
GJG TERMINAL NUMBER GFN TERMINAL NUMBER
SIGNAL NAME
SOCKET A
SOCKET B
C18
E11
SOCKET A
D3
SOCKET
B19
A12
D16
J20
ADDR14/CPERR
READY/CINT
D1
K2
F4
F8
K1
C2
D2
E5
F5
H6
H2
K4
J4
L2
ADDR15/CIRDY
CD1/CCD1
B16
J19
E1
A8
VS1/CVS1
B11
L1
B12
C18
A20
B18
C17
C15
B15
B11
ADDR19/CBLOCK
ADDR20/CSTOP
ADDR21/CDEVSEL
ADDR22/CTRDY
VS2/CVS2
D16
B19
A18
B17
A14
F13
D2
E4
D1
E2
G1
RESET/CRST
H2
WAIT/CSERR
F11
L3
INPACK/CREQ
A13
F10
J3
B14
C11
A11
BVD2(SPKR)/CAUDIO
BVD1(STSCHG)/CSTSCHG
CD2/CCD2
L6
L1
L4
M1
M2
M4
A10
D10
B10
†
L2
†
B10
†
M3
†
A10
WP(IOIS16)/CLKRUN
†
This terminal requires pullup, but the PCI4451 lacks an integrated pullup resistor.
3.4.9 SPKROUT Usage
The SPKROUT signal carries the digital audio signal from the PC Card to the system. When a 16-bit PC Card is
configured for I/O mode, the BVD2 terminal becomes SPKR. This terminal, also used in CardBus applications, is
referred to as CAUDIO. SPKR passes a TTL level digital audio signal to the PCI4451. The CardBus CAUDIO signal
also can pass a single-amplitude binary waveform. The binary audio signals from the two PC Card sockets are
XOR’ed in the PCI4451 to produce SPKROUT. Figure 3–12 illustrates the SPKROUT connection.
Bit 1, Card Control Register (offset 91h)
Card A SPKROUT Enable
Card A SPKR
SPKROUT
Speaker
Driver
Bit 1, Card Control Register (offset 91h)
Card B SPKROUT Enable
Card B SPKR
Card A SPKROUT Enable
Card B SPKROUT Enable
Figure 3–12. SPKROUT Connection to Speaker Driver
The SPKROUT signal is typically driven only by PC modem cards. To verify the SPKROUT on the PCI4451, a sample
circuit was constructed, and a simplified schematic is provided in Figure 3–13. The PCI1130/1131 required a pullup
resistor on the SUSPEND/SPKROUT terminal. Since the PCI4451 does not multiplex any other function on
SPKROUT, this terminal does not require a pullup resistor.
3–14
V
CC
V
CC
SPKROUT
6
3
7
2
Speaker
1
8
+
–
4
LM386
Figure 3–13. Test Circuit Simplified Schematic
3.4.10 LED Socket Activity Indicators
The socket activity LEDs indicate when an access is occurring to a PC Card. The LED signals are programmable
via the MFUNC routing register. When configured for LED outputs, these terminals output an active high signal to
indicate socket activity. LEDA1 indicates socket 0 (card A) activity, and LEDA2 indicates socket 1 (card B) activity.
The active-high LED signal is driven for 64 ms. When the LED is not being driven high, then it is driven to a low state.
Either of the two circuits illustrated in Figure 3–14 can be implemented to provide the LED signaling, and it is left for
the board designer to implement the circuit to best fit the application.
Current Limiting
R ≈ 500 Ω
PCI4451
LED
Current Limiting
R ≈ 500 Ω
Application-
Specific Delay
PCI4451
LED
Figure 3–14. Two Sample LED Circuits
As indicated, the LED signals are driven for 64 ms, and this is accomplished by a counter circuit. To avoid the
possibility of the LEDs appearing to be stuck when the PCI clock is stopped, the LED signaling is cut off when either
the SUSPEND signal is asserted or when the PCI clock is to be stopped per the CLKRUN protocol.
Furthermore, if any additional socket activity occurs during this counter cycle, then the counter is reset and the LED
signal remains driven. If socket activity is frequent (at least once every 64 ms), then the LED signals will remain driven.
3.4.11 PC Card 16 DMA Support
The PCI4451 supports both PC/PCI (centralized) DMA and a distributed DMA slave engine for 16-bit PC Card DMA
support. The distributed DMA (DDMA) slave register set provides the programmability necessary for the slave DDMA
engine. Table 3–5 provides the DDMA register configuration.
3–15
Table 3–5. Distributed DMA Registers
REGISTER NAME
DMA BASE
ADDRESS OFFSET
TYPE
R
W
R
Current address
00h
04h
08h
0Ch
Reserved
Reserved
Page
Base address
Current count
Reserved
W
R
Base count
N/A
Mode
N/A
Status
Reserved
W
R
Request
Command
Multichannel
Mask
N/A
Reserved
Reserved
W
Master Clear
3.4.12 CardBus Socket Registers
The PCI4451 contains all registers for compatibility with PCI Specification 2.2 and PCMCIA CardBus Bridge
Specification 7.0. These registers exist as the CardBus socket registers, and are listed in Table 3–6.
Table 3–6. CardBus Socket Registers
REGISTER NAME
Socket event
OFFSET
00h
Socket mask
04h
Socket present state
Socket force event
Socket control
08h
0Ch
10h
Reserved
14h
Reserved
18h
Reserved
1Ch
20h
Socket power management
3.5 Programmable Interrupt Subsystem
Interrupts provide a way for I/O devices to signal the microprocessor that they require servicing. The dynamic nature
of PC Cards, and the abundance of PC Card I/O applications require substantial interrupt support from the PCI4451.
The PCI4451 provides several interrupt signaling schemes to accommodate the needs of a variety of platforms. The
different mechanisms for dealing with interrupts in this device are based upon various specifications and industry
standards. The ExCA register set provides interrupt control for some 16-bit PC Card functions, and the CardBus
socket register set provides interrupt control for the CardBus PC Card functions. The PCI4451 is therefore backward
compatible with existing interrupt control register definitions, and new registers have been defined where required.
The PCI4451 detects PC Card interrupts and events at the PC Card interface and notifies the host controller via one
of several interrupt signaling protocols. To simplify the discussion of interrupts in the PCI4451, PC Card interrupts
are classified as either card status change (CSC) or as functional interrupts.
The method by which any type of PCI4451 interrupt is communicated to the host interrupt controller varies from
system to system. The PCI4451 offers system designers the choice of using parallel PCI interrupt signaling or the
serialized ISA and/or PCI interrupt protocol. It is possible to use the parallel PCI interrupts in combination with
serialized IRQs via the multifunction routing status register (PCI offset 8Ch, see Section 4.36).
3.5.1 PC Card Functional and Card Status Change Interrupts
PC Card functional interrupts are defined as requests from a PC Card application for interrupt service. They are
indicated by asserting specially defined signals on the PC Card interface. Functional interrupts are generated by
16-bit I/O PC Cards and by CardBus PC Cards.
3–16
Card status change (CSC) type interrupts, defined as events at the PC Card interface which are detected by the
PCI4451, may warrant notification of host card and socket services software for service. CSC events include both
card insertion and removal from PC Card sockets, as well as transitions of certain PC Card signals.
Table 3–7 summarizes the sources of PC Card interrupts and the card types associated with them. CSC and
functional interrupt sources are dependent upon the type of card inserted in the PC Card socket. The three types of
cards that may be inserted into any PC Card socket are: 16-bit memory card, 16-bit I/O card, and CardBus cards.
Functional interrupt events are valid only for 16-bit I/O and CardBus cards, that is, the functional interrupts are not
valid for 16-bit memory cards. Furthermore, card insertion and removal type CSC interrupts are independent of the
card type.
Table 3–7. PC Card Interrupt Events and Description
CARD TYPE
EVENT
TYPE
SIGNAL
DESCRIPTION
BVD1 (STSCHG) //
CSTSCHG
A transition on the BVD1 signal indicates a change in the
PC Card battery conditions.
CSC
Battery conditions
(BVD1, BVD2)
A transition on the BVD2 signal indicates a change in the
PC Card battery conditions.
CSC
CSC
BVD2 (SPKR) // CAUDIO
READY (IREQ) // CINT
16-bit Memory
Wait states
(READY)
A transition on the READY signal indicates a change in the
ability of the memory PC Card to accept or provide data.
Change in card status
(STSCHG)
BVD1 (STSCHG) //
CSTSCHG
The assertion of the STSCHG signal indicates a status
change on the PC Card.
CSC
16-bit I/O
CardBus
Interrupt request
(IREQ)
The assertion of the IREQ signal indicates an interrupt
request from the PC Card.
Functional
CSC
READY (IREQ) // CINT
Change in card status
(CSTSCHG)
BVD1 (STSCHG) //
CSTSCHG
The assertion of the CSTSCHG signal indicates a status
change on the PC Card.
Interrupt request
(CINT)
The assertion of the CINT signal indicates an interrupt
request from the PC Card.
Functional
CSC
READY (IREQ) // CINT
N/A
An interrupt is generated when a PC Card power-up cycle
has completed.
Power cycle complete
A transition on either the CD1//CCD1 signal or the
CD2//CCD2 signal indicates an insertion or removal of a
16-bit // CardBus PC Card.
Card insertion or
removal
CD1 // CCD1,
CD2 // CCD2
CSC
CSC
All PC Cards
An interrupt is generated when a PC Card power-up cycle
has completed.
Power cycle complete
N/A
The signal naming convention for PC Card signals describes the function for 16-bit memory and I/O cards, as well
as CardBus. For example, the READY(IREQ)//CINT signal includes the READY signal for 16-bit memory cards, the
IREQ signal for 16-bit I/O cards, and the CINT signal for CardBus cards. The 16-bit memory card signal name is first,
with the I/O card signal name second enclosed in parentheses. The CardBus signal name follows after a forward
double slash (//).
The PC Card standard describes the power-up sequence that must be followed by the PCI4451 when an insertion
event occurs and the host requests that the socket V
and V
be powered. Upon completion of this power-up
CC
PP
sequence, the PCI4451 interrupt scheme may be used to notify the host system, as in indicated in Table 3–7, denoted
by the power cycle complete event. This interrupt source is considered a PCI4451 internal event because it does not
depend on a signal change at the PC Card interface, but rather the completion of applying power to the socket.
3.5.2 Interrupt Masks and Flags
Host software may individually mask, or disable, most of the potential interrupt sources listed in Table 3–8 by setting
the appropriate bits in the PCI4451. By individually masking the interrupt sources listed in these tables, software can
control which events will cause a PCI4451 interrupt. Host software has some control over which system interrupt the
PCI4451 will assert by programming the appropriate routing registers. The PCI4451 allows host software to route
PC Card CSC and PC Card functional interrupts to separate system interrupts. Interrupt routing is somewhat specific
to the interrupt signaling method used. This will be discussed in more detail in the following sections.
3–17
When an interrupt is signaled by the PCI4451, the interrupt service routine must be able to discern which of the events
in Table 3–8 caused the interrupt. Internal registers in the PCI4451 provide flags that report which of the interrupt
sources was the cause of an interrupt. By reading these status bits, the interrupt service routine can determine which
action is to be taken.
Table 3–8 details the registers and bits associated with masking and reporting potential interrupts. All interrupts may
be masked except the functional PC Card interrupts, and an interrupt status flag is available for all types of interrupts.
Table 3–8. PCI4451 Interrupt Masks and Flags Registers
CARD TYPE
EVENT
MASK
FLAG
Battery conditions
(BVD1, BVD2)
ExCA Offset 05h/45h/805h
Bits 1 & 0 (see Section 5.6)
ExCA Offset 04h/44h/804h
Bits 1 & 0 (see Section 5.5)
16-bit Memory
Wait states
(READY)
ExCA Offset 05h/45h/805h
Bit 2 (see Section 5.6)
ExCA Offset 04h/44h/804h
Bit 2 (see Section 5.5)
Change in card status
(STSCHG)
ExCA Offset 05h/45h/805h
Bit 0 (see Section 5.6)
ExCA Offset 04h/44h/804h
Bit 0 (see Section 5.5)
16-bit I/O
Interrupt request
(IREQ)
PCI Configuration Offset 91h
Bit 0 (see Section 4.38)
Always enabled
ExCA Offset 05h/45h/805h
Bit 3 (see Section 5.6)
ExCA Offset 04h/44h/804h
Bit 3 (see Section 5.5)
All 16-bit PC Cards
Power cycle complete
Change in card status
(CSTSCHG)
Socket mask register
Bit 0 (see Section 6.2)
Socket event register
Bit 0 (see Section 6.1)
Interrupt request
(CINT)
PCI Configuration Offset 91h
Bit 0 (see Section 4.38)
Always enabled
CardBus
Socket mask register
Bit 3 (see Section 6.2)
Socket event register
Bit 3 (see Section 6.1)
Power cycle complete
Socket mask register
Bits 2 & 1 (see Section 6.2)
Socket event register
Bits 2 & 1 (see Section 6.1)
Card insertion or removal
There is no mask bit to stop the PCI4451 from passing PC Card functional interrupts through to the appropriate
interrupt scheme. Functional interrupts should not be fired until the PC Card is initialized and powered.
There are various methods of clearing the interrupt flag bits listed in Table 3–8. The flag bits in the ExCA registers
(16-bit PC Card related interrupt flags) may be cleared by two different methods. One method is an explicit write of
1 to the flag bit to clear, and the other is a reading of the flag bit register. The selection of flag bit clearing is made
by bit 2 in the global control register (ExCA offset 1Eh/5Eh/81Eh, see Section 5.22), and defaults to the flag cleared
on read method.
The CardBus related interrupt flags can only be cleared by an explicit write of 1 to the interrupt flag in the socket event
register. Although some of the functionality is shared between the CardBus registers and the ExCA registers, software
should not program the chip through both register sets when a CardBus card is functioning.
3.5.3 Using Parallel PCI Interrupts
Parallel PCI interrupts are available when in pure parallel PCI interrupt mode and are routed on MFUNC0–MFUNC2.
The PCI interrupt signaling is dependent upon the interrupt mode and is summarized in Table 3–9. The interrupt mode
is selected in bits 1 and 2 of the device control register (PCI offset 92h, see Section 4.39).
Table 3–9. Interrupt Terminal Register Cross Reference
INTPIN
Function 0
INTPIN
Function 1
INTERRUPT SIGNALING MODE
Parallel PCI interrupts only
Reserved
01h (INTA)
01h (INTA)
01h (INTA)
01h (INTA)
02h (INTB)
02h (INTB)
01h (INTA)
02h (INTB)
IRQ serialized (IRQSER) & parallel PCI interrupts
IRQ & PCI serialized (IRQSER) interrupts (default)
3–18
3.6 Power Management Overview
In addition to the low-power CMOS technology process used for the PCI4451, various features are designed into the
device to allow implementation of popular power saving techniques. These features and techniques are discussed
in this section.
3.6.1 CLKRUN Protocol
CLKRUN is the primary method of power management on the PCI bus side of the PCI4451. Since some chipsets
do not implement CLKRUN, this is not always available to the system designer, and alternate power savings features
are provided.
If CLKRUN is not implemented, then the CLKRUN terminal should be tied low. CLKRUN is enabled by default via bit
1 (KEEPCLK) in the system control register (PCI offset 80h, see Section 4.28).
3.6.2 CardBus PC Card Power Management
The PCI4451 implements its own card power management engine that can turn off the CCLK to a socket when there
is no activity to the CardBus PC Card. The CCLK speed can also be divided by 16 rather than stopped. The CLKRUN
protocol is followed on the CardBus interface to control this clock management.
3.6.3 PCI Bus Power Management
The PCI Bus Power Management Interface Specification (PCIPM) establishes the infrastructure required to let the
operating system control the power of PCI functions. This is done by defining a standard PCI interface and operations
to manage the power of PCI functions on the bus. The PCI bus and the PCI functions can be assigned one of four
software visible power management states, which result in varying levels of power savings.
The four power management states of PCI functions are: D0 — fully on state, D1 and D2 — intermediate states, and
D3 — off state. Similarly, bus power states of the PCI bus are B0–B3. The bus power states B0–B3 are derived from
the device power state of the upstream bridge device.
For the operating system to manage the device power states on the PCI bus, the PCI function should support four
power management operations. The four operations are: capabilities reporting; power status reporting; setting the
power state; and system wake-up. The operating system identifies the capabilities of the PCI function by traversing
the new capabilities list. The presence of new capabilities is indicated by a 1b in bit 4 of the PCI status register (PCI
offset 06h, see Section 4.5). When software determines that the device has a capabilities list by seeing that bit 4 of
the PCI status register is set, it will read the capability pointer register (PCI offset 14h, see Section 4.12). This value
in the register points to the location in PCI configuration space of the capabilities linked list.
The first byte of each capability register block is required to be a unique ID of that capability. PCI power management
has been assigned an ID of 01h. The next byte is a pointer to the next pointer item in the list of capabilities. If there
are no more items in the list, then the next item pointer should be set to 0. The registers following the next item pointer
are specific to the function’s capability. The PCIPM capability implements the following register block:
Power Management Register Block
Power management capabilities (PMC)
Data PMCSR bridge support extensions
Next item pointer
Capability ID
Offset = 0
Offset = 4
Power management control status (CSR)
The power management capabilities (PMC) register is a static read-only register that provides information on the
capabilities of the function, related to power management. The PMCSR register enables control of power
management states and enables/monitors power management events. The data register is an optional register that
provides a mechanism for state-dependent power measurements such as power consumed or heat dissipation.
3.6.4 CardBus Device Class Power Management
The PCI Bus Interface Specification for PCI-to-CardBus Bridges was approved by PCMCIA in December of 1997.
This specification follows the device and bus state definitions provided in the PCI Bus Power Management Interface
3–19
Specification published by the PCI Special Interest Group (SIG). The main issue addressed in the PCI Bus Interface
Specification for PCI-to-CardBus Bridges is wake-up from D3 or D3
PME context).
without losing wake-up context (also called
hot
cold
The specific issues addressed by the PCI Bus Interface Specification for PCI-to-CardBus Bridges for D3 wake-up
are as follows:
•
Preservation of device context: The PCI Power Management Specification version 1.0 states that PRST
must be asserted when transitioning from D3 to D0. Some method to preserve wake-up context must
cold
be implemented so that PRST does not clear the PME context registers.
Power source in D3 if wake-up support is required from this state.
•
cold
The Texas Instruments PCI4451 addresses these D3 wake-up issues in the following manner:
•
Preservation of device context: When PRST is asserted, bits required to preserve PME context are not
cleared. To clear all bits in the PCI4451, another reset terminal is defined: G_RST (global reset). G_RST
is normally only asserted during the initial power-on sequence. After the initial boot, PRST should be
asserted so that PME context is retained for D3-to-D0 transitions. Bits cleared by G_RST, but not cleared
by PRST (if the PME enable bit is set), are referred to as PME context bits. See the master list of PME
context bits in the next section.
•
Power source in D3
auxiliary power source must be switched to the PCI4451 V
make-before-break type of switch, so that V
if wake-up support is required from this state. Since V
is removed in D3
, an
cold
CC
cold
terminals. This switch should be a
CC
to the PCI4451 is not interrupted.
CC
3.6.5 Master List Of PME Context Bits and Global Reset Only Bits
PME context bit means that the bit is cleared only by the assertion of G_RST when the PME enable bit, bit 8 of the
power management control/status register (PCI offset A4h, see Section 4.46) is set. If PME is not enabled, then these
bits are cleared when either PRST or G_RST is asserted.
Global reset only bits, as the name implies, are only cleared by G_RST. These bits are never cleared by PRST
regardless of the setting of the PME enable bit. The G_RST signal is gated only by the SUSPEND signal. This means
that assertion of SUSPEND blocks the G_RST signal internally, thus preserving all register contents.
3–20
Global reset only bits:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Subsystem ID/subsystem vendor ID (PCI offset 40h, see Section 4.25): bits 31–0
PC Card 16-bit legacy mode base address register (PCI offset 44h, see Section 4.27): bits 31–1
System control register (PCI offset 80h, see Section 4.28): bits 31–29, 27–24, 22–14, 6–3, 1, 0
Multimedia control register (PCI offset 84h, see Section 4.29): bits 7–0
General status register (PCI offset 85h, see Section 4.30): bits 2–0
General-purpose event status register (PCI offset 88h, see Section 4.32): bits 7, 6, 3–0
General-purpose event enable register (PCI offset 89h, see Section 4.33): bits 7, 6, 3–0
General-purpose input register (PCI offset 8Ah, see Section 4.34): bits 3–0
General-purpose output register (PCI offset 8Bh, see Section 4.35): bits 3–0
Multifunction routing status register (PCI offset 8Ch, see Section 4.36): bits 31–0
Retry status register (PCI offset 90h, see Section 4.37): bits 7–1
Card control register (PCI offset 91h, see Section 4.38): bits 7, 6, 2, 1, 0
Device control register (PCI offset 92h, see Section 4.39): bits 7–0
Diagnostic register (PCI offset 93h, see Section 4.40): bits 7–0
Socket DMA register 0 (PCI offset 94h, see Section 4.41): bits 1–0
Socket DMA register 1 (PCI offset 98h, see Section 4.42): bits 15–0
GPE control/status register (PCI offset A8h, see Section 4.48): bits 10, 9, 8, 2, 1, 0
PME context bits
•
•
•
•
•
•
•
•
•
•
Bridge control register (PCI offset 3Eh, see Section 4.24): bit 6
Power management capabilities register (PCI offset A2h, see Section 4.45): bit 15
Power management control/status register (PCI offset A4h, see Section 4.46): bits 15, 8
ExCA power control register (ExCA 802h/842h, see Section 5.3): bits 7, 4, 3, 1, 0
ExCA interrupt and general control (ExCA 803h/843h, see Section 5.4): bit 6, 5
ExCA card status-change register (ExCA 804h/844h, see Section 5.5): bits 3–0
ExCA card status-change interrupt register (ExCA 805h/845h, see Section 5.6): bits 3–0
Socket event register (CardBus offset 00h, see Section 6.1): bits 3–0
Socket mask register (CardBus offset 04h, see Section 6.2): bits 3–0
Socket control register (CardBus offset 10h, see Section 6.5): bits 6, 5, 4, 2, 1, 0
3–21
PCI Bus
Real Time
‡
Clock
PRST
South Bridge
†
G_RST
Clock
2
CLKRUN
PME
TPS2216
Power
Switch
PCI4451
Embedded
Controller
Vcc
System Vcc
PC Card
Socket A
68
D3
Status
V
aux
PC Card
Socket B
Make Before
Break Switch
68
†
‡
The system connection to GRST is implementation specific. GRST should be applied whenever V is applied to the PCI4451. PRST should be
cc
applied for subsequent warm resets.
Not required if internal oscillator is used.
Figure 3–15. System Diagram Implementing CardBus Device Class Power Management
3.6.6 Suspend Mode
The SUSPEND signal, provided for backward compatibility, gates the PRST (PCI reset) signal and the G_RST (global
reset) signal from the PCI4451. Besides gating PRST and G_RST, SUSPEND also gates PCLK inside the PCI4451
in order to minimize power consumption.
Gating PCLK does not create any issues with respect to the power switch interface in the PCI4451. This is because
the PCI4451 does not depend on the PCI clock to clock the power switch interface. There are two methods to clock
the power switch interface in the PCI4451:
•
•
Use an external clock to the PCI4451 CLOCK terminal
Use the internal oscillator
It should also be noted that asynchronous signals, such as card status change interrupts and RI_OUT, can be passed
to the host system without a PCI clock. However, if card status change interrupts are routed over the serial interrupt
stream, then the PCI clock will have to be restarted in order to pass the interrupt, because neither the internal oscillator
nor an external clock is routed to the serial interrupt state machine.
PRST
G_RST
PCI4451
Core
SUSPEND
GNT
PCLK
Figure 3–16. Suspend Functional Illustration
3–22
3.6.7 Requirements for SUSPEND
A requirement for implementing suspend mode is that the PCI bus must not be parked on the PCI4451 when
SUSPEND is asserted. The PCI4451 responds to SUSPEND being asserted by placing the REQ terminal in a
high-impedance state. The PCI4451 will also gate the internal clock and reset.
The GPIOs, MFUNC signals, and RI_OUT signals are all active during SUSPEND, unless they are disabled in the
appropriate PCI4451 registers.
3.6.8 Ring Indicate
The RI_OUT output is an important feature used in legacy power management. It is used so that a system can go
into a suspended mode and wake up on modem rings and other card events. The RI_OUT signal on the PCI4451
may be asserted under any of the following conditions:
•
•
•
A 16-bit PC Card modem in a powered socket asserts RI to indicate an incoming call to the system.
A powered down CardBus card asserts CSTSCHG (CBWAKE) requesting system and interface wake up.
A card status change (CSC) event, such as insertion/removal of cards, battery voltage levels, occurs.
A CSTSCHG signal from a powered CardBus card is indicated as a CSC event, not as a CBWAKE event. These two
RI_OUT events are enabled separately. The following figure details various enable bits for the PCI4451 RI_OUT
function; however, it does not illustrate the masking of CSC events. See Interrupt Masks and Flags, Section 3.5.2,
for a detailed description of CSC interrupt masks and flags.
RI_OUT is multiplexed on the same terminal with PME. The default is for RI_OUT to be signaled on this terminal.
In PCI power managed systems, the PME signal should be enabled by setting bit 0 (RI_OUT/PME) in the system
control register (PCI offset 80h, see Section 4.28) and clearing bit 7 (RIENB) in the card control register (PCI offset
91h, see Section 4.38).
RI_OUT Function
PC Card
Socket 0
Card
I/F
Card
Bus
16-bit
RI
CSC
CBWAKE
RIENB
RICSC(A)
RICSC(B)
RI_OUT
CSC
CBWAKE
RI
PC Card
Socket 1
Card
I/F
Card
Bus
16-bIt
Figure 3–17. RI_OUT Functional Illustration
Routing of CSC events to the RI_OUT signal, enabled on a per-socket basis, is programmed by the RICSC bit in the
card control register (PCI offset 91h, see Section 4.38). This bit is socket-dependent (not shared), as illustrated in
Figure 3–17.
3–23
The RI signal from the 16-bit PC Card interface is masked by the ExCA control bit RINGEN in the ExCA interrupt and
general control register (PCI offset 86h, see Section 4.31). This is programmed on a per-socket basis, and is only
applicable when a 16-bit card is powered in the socket.
The CBWAKE signaling to RI_OUT is enabled through the same mask as the CSC event for CSTSCHG. The mask
bit, CSTSMASK, is programmed through the socket mask register (offset 04h, see Section 6.2) in the CardBus socket
registers.
3–24
4 PC Card Controller Programming Model
This chapter describes the PCI4451 PCI configuration registers that make up the 256-byte PCI configuration header
for each PCI4451 function. As noted below, some bits are global in nature and should be accessed only through
function 0.
Registers containing one or more global bits are denoted by a §.
Any bit followed by a † is not cleared by the assertion of PRST (see CardBus Device Class Power Management,
Section 3.6.4, for more details) if PME is enabled (PCI offset A4h, bit 8). In this case, these bits are only cleared by
GRST. If PME is not enabled, then these bits are cleared by GRST or PRST. These bits are sometimes referred to
as PME context bits and are implemented to allow PME context to be preserved when transitioning from D3
or
hot
D3
to D0. If the PME context PRST functionality is not desired, then the PRST and GRST signals should be tied
cold
together.
If a bit is followed by a †, then this bit is only cleared by GRST in all cases (not conditional on PME being enabled).
These bits are intended to maintain device context such as interrupt routing and MFUNC programming during warm
resets.
4.1 PCI Configuration Registers (Functions 0 and 1)
The PCI4451 is a multifunction PCI device, and the PC Card controller is integrated as PCI functions 0 and 1. The
configuration header, compliant with the PCI Specification as a CardBus bridge header, is PC97/PC98 compliant as
well. Table 4–1 illustrates the PCI configuration header, which includes both the predefined portion of the
configuration space and the user definable registers.
Table 4–1. Functions 0 and 1 PCI Configuration Register Map
REGISTER NAME
OFFSET
00h
Device ID
Status
Vendor ID
PCI command
04h
Class code
Header type
Revision ID
08h
BIST
Latency timer
Cache line size
0Ch
10h
CardBus socket registers/ExCA registers base address
Reserved
Secondary status
Capability pointer
PCI bus number
14h
CardBus latency timer
Subordinate bus number
CardBus bus number
18h
CardBus memory base register 0
1Ch
20h
CardBus memory limit register 0
CardBus memory base register 1
CardBus memory limit register 1
CardBus I/O base register 0
CardBus I/O limit register 0
CardBus I/O base register 1
CardBus I/O limit register 1
Interrupt pin
24h
28h
2Ch
30h
34h
38h
†
Bridge control
Interrupt line
3Ch
40h
‡
Subsystem ID
Subsystem vendor ID‡
PC Card 16-bit I/F legacy mode base address‡
44h
Reserved
48h–7Fh
†
‡
One or more bits in the register are PME context bits and can only be cleared by the assertion of GRST when PME is enabled. If PME is not
enabled, then these bits are cleared by the assertion of PRST or GRST.
One or more bits in this register are only cleared by the assertion GRST.
4–1
Table 4–1. Functions 0 and 1 PCI Configuration Register Map (Continued)
REGISTER NAME
OFFSET
80h
‡ §
System control
‡
† §
Reserved
General control
General status
Multimedia control
‡
General-purpose event status
84h
‡
‡
‡
General-purpose output
General-purpose input
General-purpose event enable
88h
Multifunction routing status†
‡ §
8Ch
90h
‡ §
Diagnostic
‡ §
Retry status
Device control
Card control‡ §
Socket DMA register 0 ‡
Socket DMA register 1 ‡
Reserved
94h
98h
9Ch
A0h
†
Power management capabilities
Next item pointer
Capability ID
Power management
control/status register
bridge support extensions
†
Data (Reserved)
A4h
Power management control/status
†
GPE control/status
Reserved
A8h
†
‡
One or more bits in the register are PME context bits and can only be cleared by the assertion of GRST when PME is enabled. If PME is not
enabled, then these bits are cleared by the assertion of PRST or GRST.
One or more bits in this register are only cleared by the assertion GRST.
4.2 Vendor ID Register
The vendor ID register contains a value allocated by the PCI SIG that identifies the manufacturer of the PCI device.
The vendor ID assigned to Texas Instruments is 104Ch.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Vendor ID
R
0
R
0
R
0
R
1
R
0
R
0
R
0
R
0
R
0
R
1
R
0
R
0
R
1
R
1
R
0
R
0
Register:
Type:
Vendor ID
Read-only
Offset:
Default:
00h (Functions 0, 1)
104Ch
4.3 Device ID Register
The device ID register contains a value assigned to the PCI4451 by Texas Instruments. The device identification for
the PCI4451 is AC42.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Device ID
R
1
R
0
R
1
R
0
R
1
R
1
R
0
R
0
R
0
R
1
R
0
R
0
R
0
R
0
R
1
R
0
Register:
Type:
Device ID
Read-only
Offset:
Default:
02h (Functions 0, 1)
AC42h
4–2
4.4 PCI Command Register
The command register provides control over the PCI4451 interface to the PCI bus. All bit functions adhere to the
definitions in the PCI Local Bus Specification, see Table 4–2. None of the bit functions in this register are shared
between the two PCI4451 PCI functions. Two command registers exist in the PCI4451, one for each function.
Software manipulates the two PCI4451 functions as separate entities when enabling functionality through the
command register. The SERR_EN and PERR_EN enable bits in this register are internally wired OR between the
two functions, and these control bits appear separate per function to software.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
PCI command
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R
0
R/W
0
R/W
0
R
0
R
0
R/W
0
R/W
0
R/W
0
Register:
Type:
PCI command
Read-only, Read/Write
Offset:
Default:
04h
0000h
Table 4–2. PCI Command Register Description
FUNCTION
BIT
SIGNAL
TYPE
15–10
RSVD
R
Bits 15–10 return 0s when read.
Fast back-to-back enable. The PCI4451 will not generate fast back-to-back transactions; therefore, this bit
is read-only. This bit returns a 0 when read.
9
8
7
6
FBB_EN
SERR_EN
STEP_EN
PERR_EN
R
System error (SERR) enable. This bit controls the enable for the SERR driver on the PCI interface. SERR
can be asserted after detecting an address parity error on the PCI bus. Both this bit and bit 6 must be set
for the PCI4451 to report address parity errors.
R/W
R
0 = Disables the SERR output driver (default)
1 = Enables the SERR output driver
Address/data stepping control. The PCI4451 does not support address/data stepping, and this bit is
hardwired to 0. Writes to this bit have no effect.
Parity error response enable. This bit controls the PCI4451 response to parity errors through the PERR
signal. Data parity errors are indicated by asserting PERR, while address parity errors are indicated by
asserting SERR.
R/W
0 = PCI4451 ignores detected parity error (default).
1 = PCI4451 responds to detected parity errors.
VGA palette snoop. When set to 1, palette snooping is enabled (i.e., the PCI4451 does not respond to palette
register writes and snoops the data). When the bit is 0, the PCI4451 will treat all palette accesses like all
other accesses.
5
4
3
2
VGA_EN
MWI_EN
SPECIAL
MAST_EN
R/W
R
Memory write and invalidate enable. This bit controls whether a PCI initiator device can generate memory
write-and-invalidate commands. The PCI4451 controller does not support memory write-and-invalidate
commands, it uses memory write commands instead; therefore, this bit is hardwired to 0. This bit returns
0 when read. Writes to this bit have no effect.
Special cycles. This bit controls whether or not a PCI device ignores PCI special cycles. The PCI4451 does
not respond to special cycle operations; therefore, this bit is hardwired to 0. This bit returns 0 when read.
Writes to this bit have no effect.
R
Bus master control. This bit controls whether or not the PCI4451 can act as a PCI bus initiator (master). The
PCI4451 can take control of the PCI bus only when this bit is set.
R/W
0 = Disables the PCI4451 ability to generate PCI bus accesses (default)
1 = Enables the PCI4451 ability to generate PCI bus accesses
Memory space enable. This bit controls whether or not the PCI4451 may claim cycles in PCI memory space.
0 = Disables the PCI4451 response to memory space accesses (default)
1
0
MEM_EN
IO_EN
R/W
R/W
1 = Enables the PCI4451 response to memory space accesses
I/O space control. This bit controls whether or not the PCI4451 may claim cycles in PCI I/O space.
0 = Disables the PCI4451 from responding to I/O space accesses (default)
1 = Enables the PCI4451 to respond to I/O space accesses
4–3
4.5 Status Register
The status register provides device information to the host system. Bits in this register may be read normally. A bit
in the status register is reset when a 1 is written to that bit location; a 0 written to a bit location has no effect. All bit
functions adhere to the definitions in the PCI Bus Specification, as seen in the bit descriptions. PCI bus status is shown
through each function. See Table 4–3 for a complete description of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Status
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
1
R/W
0
R
0
R
0
R
0
R
1
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
Status
Read-only, Read/Write
06h (Functions 0, 1)
0210h
Table 4–3. Status Register Description
BIT
SIGNAL
TYPE
FUNCTION
Detected parity error. This bit is set when a parity error is detected, either address or data parity errors. Write
a 1 to clear this bit.
15
PAR_ERR
R/W
Signaled system error. This bit is set when SERR is enabled and the PCI4451 signaled a system error to
the host. Write a 1 to clear this bit.
14
13
SYS_ERR
MABORT
R/W
R/W
R/W
R/W
R
Received master abort. This bit is set when a cycle initiated by the PCI4451 on the PCI bus has been
terminated by a master abort. Write a 1 to clear this bit.
Received target abort. This bit is set when a cycle initiated by the PCI4451 on the PCI bus was terminated
by a target abort. Write a 1 to clear this bit.
12
TABT_REC
TABT_SIG
PCI_SPEED
Signaled target abort. This bit is set by the PCI4451 when it terminates a transaction on the PCI bus with
a target abort. Write a 1 to clear this bit.
11
DEVSEL timing. These bits encode the timing of DEVSEL and are hardwired to 01b indicating that the
PCI4451 asserts this signal at a medium speed on nonconfiguration cycle accesses.
10–9
Data parity error detected. Write a 1 to clear this bit.
0 = The conditions for setting this bit have not been met.
1 = A data parity error occurred and the following conditions were met:
a. PERR was asserted by any PCI device including the PCI4451.
b. The PCI4451 was the bus master during the data parity error.
c. The parity error response bit is set in the command register.
8
DATAPAR
R/W
Fast back-to-back capable. The PCI4451 cannot accept fast back-to-back transactions; thus, this bit is
hardwired to 0.
7
6
5
FBB_CAP
UDF
R
R
R
UDF supported. The PCI4451 does not support the user definable features; therefore, this bit is hardwired
to 0.
66-MHz capable. The PCI4451 operates at a maximum PCLK frequency of 33 MHz; therefore, this bit is
hardwired to 0.
66MHZ
Capabilities list. This bit returns 1 when read. This bit indicates that capabilities in addition to standard PCI
capabilities are implemented. The linked list of PCI power management capabilities is implemented in this
function.
4
CAPLIST
RSVD
R
R
3–0
These bits return 0s when read.
4–4
4.6 Class Code and Revision ID Registers
The class code and revision ID register recognizes the PCI4451 functions 0 and 1 as a bridge device (06h) and
CardBus bridge device (07h) with a 00h programming interface. Furthermore, the TI chip revision is indicated in the
least significant byte (00h).
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Class code and revision ID
R
0
R
0
R
0
R
0
R
0
R
1
R
1
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
1
2
R
1
1
R
1
0
15
14
13
12
11
10
Name
Type
Default
Class code and revision ID
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Class code and revision ID
Read-only
Offset:
Default:
08h (Functions 0, 1)
0607 0000h
4.7 Cache Line Size Register
The cache line size register is programmed by host software to indicate the system cache line size.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Cache line size
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Cache line size
Read/Write
Offset:
Default:
0Ch (Functions 0, 1)
00h
4.8 Latency Timer Register
The latency timer register specifies the latency timer for the PCI4451, in units of PCI clock cycles. When the PCI4451
is a PCI bus initiator and asserts FRAME, the latency timer begins counting from zero. If the latency timer expires
before the PCI4451 transaction has terminated, then the PCI4451 terminates the transaction when its GNT is
deasserted.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Latency timer
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Offset:
Default:
Latency timer
Read/Write
0Dh
00h
4–5
4.9 Header Type Register
The header type register returns 82h when read, indicating that the PCI4451 functions 0 and 1 configuration spaces
adhere to the CardBus bridge PCI header. The CardBus bridge PCI header ranges from PCI register 0 to 7Fh, and
80h–FFh is user definable extension registers.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Header type
R
1
R
0
R
0
R
0
R
0
R
0
R
1
R
0
Register:
Type:
Header type
Read-only
Offset:
Default:
0Eh (Functions 0, 1)
82h
4.10 BIST Register
Since the PCI4451 does not support a built-in self-test (BIST), this register returns the value of 00h when read. This
register returns 0s for the two PCI4451 functions.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
BIST
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
BIST
Read-only
Offset:
Default:
0Fh (Functions 0, 1)
00h
4.11 CardBus Socket Registers/ExCA Registers Base Address Register
This register is programmed with a base address referencing the CardBus socket registers and the memory-mapped
ExCA register set. Bits 31–12 are read/write, and allow the base address to be located anywhere in the 32-bit PCI
memory address space on a 4-Kbyte boundary. Bits 11–0 are read-only, returning 0s when read. When software
writes all ones to this register, the value read back will be FFFF F000h, indicating that at least 4K bytes of memory
address space are required. The CardBus registers start at offset 000h, and the memory mapped ExCA registers
begin at offset 800h. This register is not shared by functions 0 and 1, so the system maps each socket control register
separately.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
CardBus socket registers/ExCA registers base address
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
CardBus socket registers/ExCA registers base address
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
CardBus socket registers/ExCA registers base address
Read-only, Read/Write
10h
0000 0000h
4–6
4.12 Capability Pointer Register
The capability pointer register provides a pointer into the PCI configuration header where the PCI power management
register block resides. PCI header doublewords at A0h and A4h provide the power management (PM) registers. Each
socket has its own capability pointer register. This register is read-only and returns A0h when read.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Capability pointer
R
1
R
0
R
1
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
Capability pointer
Read-only
14h
A0h
4–7
4.13 Secondary Status Register
The secondary status register is compatible with the PCI-PCI bridge secondary status register. It indicates CardBus
related device information to the host system. This register is very similar to the PCI status register (offset 06h), and
status bits are cleared by a writing a 1. This register is not shared by the two socket functions, but is accessed on
a per socket basis. See Table 4–4 for a complete description of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Secondary status
RC
0
RC
0
RC
0
RC
0
RC
0
R
0
R
1
RC
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Secondary status
Read-only, Read/2Clear
Offset:
Default:
16h
0200h
Table 4–4. Secondary Status Register Description
BIT
SIGNAL
TYPE
FUNCTION
Detected parity error. This bit is set when a CardBus parity error is detected, either address or data parity
errors. Write a 1 to clear this bit.
15
CBPARITY
RC
Signaled system error. This bit is set when CSERR is signaled by a CardBus card. The PCI4451 does not
assert the CSERR signal. Write a 1 to clear this bit.
14
13
CBSERR
CBMABORT
REC_CBTA
SIG_CBTA
CB_SPEED
RC
RC
RC
RC
R
Received master abort. This bit is set when a cycle initiated by the PCI4451 on the CardBus bus has been
terminated by a master abort. Write a 1 to clear this bit.
Received target abort. This bit is set when a cycle initiated by the PCI4451 on the CardBus bus was
terminated by a target abort. Write a 1 to clear this bit.
12
Signaled target abort. This bit is set by the PCI4451 when it terminates a transaction on the CardBus bus
with a target abort. Write a 1 to clear this bit.
11
CDEVSEL timing. These bits encode the timing of CDEVSEL and are hardwired to 01b indicating that the
PCI4451 asserts this signal at a medium speed.
10–9
CardBus data parity error detected. Write a 1 to clear this bit.
0 = The conditions for setting this bit have not been met.
1 = A data parity error occurred and the following conditions were met:
a. CPERR was asserted on the CardBus interface.
8
CB_DPAR
RC
b. The PCI4451 was the bus master during the data parity error.
c. The parity error response enable bit (bit 0) is set in the bridge control register (offset 3Eh, see
Section 4.24).
Fast back-to-back capable. The PCI4451 cannot accept fast back-to-back transactions; therefore, this bit
is hardwired to 0.
7
6
CBFBB_CAP
CB_UDF
R
R
User definable feature support. The PCI4451 does not support the user definable features; therefore, this
bit is hardwired to 0.
66-MHz capable. The PCI4451 CardBus interface operates at a maximum CCLK frequency of 33 MHz;
therefore, this bit is hardwired to 0.
5
CB66MHZ
RSVD
R
R
4–0
These bits return 0s when read.
4–8
4.14 PCI Bus Number Register
The PCI bus number register is programmed by the host system to indicate the bus number of the PCI bus to which
the PCI4451 is connected. The PCI4451 uses this register, in conjunction with the CardBus bus number and
subordinate bus number registers, to determine when to forward PCI configuration cycles to its secondary buses.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
PCI bus number
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
PCI bus number
Read/Write
Offset:
Default:
18h (Functions 0, 1)
00h
4.15 CardBus Bus Number Register
The CardBus bus number register is programmed by the host system to indicate the bus number of the CardBus bus
to which the PCI4451 is connected. The PCI4451 uses this register, in conjunction with the PCI bus number and
subordinate bus number registers, to determine when to forward PCI configuration cycles to its secondary buses.
This register is separate for each PCI4451 controller function.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
CardBus bus number
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Offset:
Default:
CardBus bus number
Read/Write
19h
00h
4.16 Subordinate Bus Number Register
The subordinate bus number register is programmed by the host system to indicate the highest numbered bus below
the CardBus bus. The PCI4451 uses this register, in conjunction with the PCI bus number and CardBus bus number
registers, to determine when to forward PCI configuration cycles to its secondary buses. This register is separate for
each CardBus controller function.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Subordinate bus number
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Offset:
Default:
Subordinate bus number
Read/Write
1Ah
00h
4–9
4.17 CardBus Latency Timer Register
The CardBus latency timer register is programmed by the host system to specify the latency timer for the PCI4451
CardBus interface, in units of CCLK cycles. When the PCI4451 is a CardBus initiator and asserts CFRAME, the
CardBus latency timer begins counting. If the latency timer expires before the PCI4451 transaction has terminated,
then the PCI4451 terminates the transaction at the end of the next data phase. A recommended minimum value for
this register of 20h allows most transactions to be completed.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
CardBus latency timer
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
CardBus latency timer
Read/Write
Offset:
Default:
1Bh (Functions 0, 1)
00h
4.18 CardBus Memory Base Registers 0, 1
These registers indicate the lower address of a PCI memory address range. They are used by the PCI4451 to
determine when to forward a memory transaction to the CardBus bus, and likewise, when to forward a CardBus cycle
to PCI. Bits 31–12 of these registers are read/write and allow the memory base to be located anywhere in the 32-bit
PCI memory space on 4-Kbyte boundaries. Bits 11–0 are read-only and always return 0s. Writes to these bits have
no effect. Bits 8 and 9 of the bridge control register (offset 3Eh, see Section 4.24) specify whether memory windows
0 and 1 are prefetchable or nonprefetchable. The memory base register or the memory limit register must be nonzero
in order for the PCI4451 to claim any memory transactions through CardBus memory windows (i.e., these windows
are not enabled by default to pass the first 4K bytes of memory to CardBus).
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Memory base registers 0, 1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Memory base registers 0, 1
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
Memory base registers 0, 1
Read-only, Read/Write
1Ch, 24h
0000 0000h
4–10
4.19 CardBus Memory Limit Registers 0, 1
These registers indicate the upper address of a PCI memory address range. They are used by the PCI4451 to
determine when to forward a memory transaction to the CardBus bus, and likewise, when to forward a CardBus cycle
to PCI. Bits 31–12 of these registers are read/write and allow the memory base to be located anywhere in the 32-bit
PCI memory space on 4-Kbyte boundaries. Bits 11–0 are read-only and always return 0s. Writes to these bits have
no effect. Bits 8 and 9 of the bridge control register (offset 3Eh, see Section 4.24) specify whether memory windows
0 and 1 are prefetchable or nonprefetchable. The memory base register or the memory limit register must be nonzero
in order for the PCI4451 to claim any memory transactions through CardBus memory windows (i.e., these windows
are not enabled by default to pass the first 4K bytes of memory to CardBus).
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Memory limit registers 0, 1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Memory limit registers 0, 1
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
Memory limit registers 0, 1
Read-only, Read/Write
20h, 28h
0000 0000h
4.20 CardBus I/O Base Registers 0, 1
These registers indicate the lower address of a PCI I/O address range. They are used by the PCI4451 to determine
when to forward an I/O transaction to the CardBus bus, and likewise, when to forward a CardBus cycle to the PCI
bus. The lower 16 bits of this register locate the bottom of the I/O window within a 64-Kbyte page, and the upper 16
bits (31–16) are all 0s which locate this 64-Kbyte page in the first page of the 32-bit PCI I/O address space. Bits 31–16
and bits 1–0 are read-only and always return 0s, forcing I/O windows to be aligned on a natural doubleword boundary
in the first 64-Kbyte page of PCI I/O address space. These I/O windows are enabled when either the I/O base register
or the I/O limit register is nonzero. The I/O windows are not enabled by default to pass the first doubleword of I/O to
CardBus.
Either the I/O base or the I/O limit register must be nonzero to enable any I/O transactions.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
I/O base registers 0, 1
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
I/O base registers 0, 1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
Register:
Type:
Offset:
Default:
I/O base registers 0, 1
Read-only, Read/Write
2Ch, 34h
0000 0000h
4–11
4.21 CardBus I/O Limit Registers 0, 1
These registers indicate the upper address of a PCI I/O address range. They are used by the PCI4451 to determine
when to forward an I/O transaction to the CardBus bus, and likewise, when to forward a CardBus cycle to PCI. The
lower 16 bits of this register locate the top of the I/O window within a 64-Kbyte page, and the upper 16 bits are a page
register which locates this 64-Kbyte page in 32-bit PCI I/O address space. Bits 15–2 are read/write and allow the I/O
limit address to be located anywhere in the 64-Kbyte page (indicated by bits 31–16 of the appropriate I/O base
register) on doubleword boundaries.
Bits 31–16 are read-only and always return 0s when read. The page is set in the I/O base register. Bits 1–0 are
read-only and always return 0s, forcing I/O windows to be aligned on a natural doubleword boundary. Writes to
read-only bits have no effect. The PCI4451 assumes that the lower two bits of the limit address are ones.
These I/O windows are enabled when either the I/O base register or the I/O limit register is nonzero. The I/O windows
are not enabled by default to pass the first doubleword of I/O to CardBus.
Either the I/O base or the I/O limit register must be nonzero to enable any I/O transactions.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
I/O limit registers 0, 1
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
I/O limit registers 0, 1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
Register:
Type:
Offset:
Default:
I/O limit registers 0, 1
Read-only, Read/Write
30h, 38h
0000 0000h
4.22 Interrupt Line Register
The interrupt line register communicates interrupt line routing information to the host system. This register is not used
by the PCI4451, since there are many programmable interrupt signaling options. This register is considered reserved;
however, host software may read and write to this register. Each PCI4451 function has an interrupt line register.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Interrupt line
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Register:
Type:
Offset:
Default:
Interrupt line
Read/Write
3Ch
FFh
4–12
4.23 Interrupt Pin Register
The value read from this register is function dependent. The value depends on interrupt tie bits 28 and 29 (INTRTIE
and TIEALL) in the system control register (offset 80h, See Section 4.28). INTRTIE is compatible with other TI
CardBus controllers and ties INTA to INTB internally. The TIEALL bit ties INTA, INTB, and INTC together internally.
The internal interrupt connections set by INTRTIE and TIEALL are communicated to host software through this
standard register interface. Refer to Table 4–5 for a complete description of the register contents.
PCI function 0
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Interrupt pin – PCI function 0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
1
PCI function 1
Bit
7
6
5
4
3
2
1
0
Name
Interrupt pin – PCI function 1
Type
R
0
R
0
R
0
R
0
R
0
R
0
R
1
R
0
Default
Register:
Type:
Offset:
Default:
Interrupt pin
Read-only
3Dh
The default depends on the interrupt signaling mode.
Table 4–5. Interrupt Pin Register Cross Reference
INTRTIE
BIT
TIEALL
BIT
INTPIN
FUNCTION 0
INTPIN
FUNCTION 1
INTPIN
FUNCTION 2
03h (INTC)
03h (INTC)
01h (INTA)
0
1
x
0
0
1
01h (INTA)
01h (INTA)
01h (INTA)
02h (INTB)
01h (INTA)
01h (INTA)
4–13
4.24 Bridge Control Register
The bridge control register provides control over various PCI4451 bridging functions. Some bits in this register are
global in nature and should be accessed only through function 0. See Table 4–6 for a complete description of the
register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Bridge control
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
1
R/W
1
R/W
0
R/W
1
R/W
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Offset:
Default:
Bridge control
Read-only, Read/Write
3Eh (Function 0, 1)
0340h
Table 4–6. Bridge Control Register Description
FUNCTION
BIT
SIGNAL
TYPE
15–11
RSVD
R
These bits return 0s when read.
Write posting enable. Enables write posting to and from the CardBus sockets. Write posting enables
posting of write data on burst cycles. Operating with write posting disabled will inhibit performance on burst
cycles. Note that burst write data can be posted, but various write transactions may not. This bit is socket
dependent and is not shared between functions 0 and 1.
10
9
POSTEN
PREFETCH1
PREFETCH0
INTR
R/W
R/W
R/W
R/W
Memory window 1 type. This bit specifies whether or not memory window 1 is prefetchable. This bit is
socket dependent. This bit is encoded as:
0 = Memory window 1 is nonprefetchable.
1 = Memory window 1 is prefetchable (default).
Memory window 0 type. This bit specifies whether or not memory window 0 is prefetchable. This bit is
encoded as:
8
0 = Memory window 0 is nonprefetchable.
1 = Memory window 0 is prefetchable (default).
PCI Interrupt – IREQ routing enable. This bit is used to select whether PC Card functional interrupts are
routed to PCI interrupts or to the IRQ specified in the ExCA registers.
0 = Functional interrupts are routed to PCI interrupts (default).
7
1 = Functional interrupts are routed by ExCA registers.
CardBus reset. When this bit is set, the CRST signal is asserted on the CardBus interface. The CRST
signal may also be asserted by passing a PRST assertion to CardBus.
0 = CRST is deasserted.
6
CRST
R/W
R/W
1 = CRST is asserted (default).
This bit will not be cleared by the assertion of PRST. It will only be cleared by the assertion of GRST.
Master abort mode. This bit controls how the PCI4451 responds to a master abort when the PCI4451 is
an initiator on the CardBus interface. This bit is common between each socket.
0 = Master aborts not reported (default).
†
5
MABTMODE
1 = Signal target abort on PCI and signal SERR, if enabled.
4
RSVD
R
This bit returns 0 when read.
VGA enable. This bit affects how the PCI4451 responds to VGA addresses. When this bit is set, accesses
to VGA addresses will be forwarded.
3
VGAEN
R/W
ISA mode enable. This bit affects how the PCI4451 passes I/O cycles within the 64-Kbyte ISA range. This
bit is not common between sockets. When this bit is set, the PCI4451 will not forward the last 768 bytes
of each 1K I/O range to CardBus.
2
ISAEN
R/W
R/W
CSERR enable. This bit controls the response of the PCI4451 to CSERR signals on the CardBus bus. This
bit is separate for each socket.
1
CSERREN
0 = CSERR is not forwarded to PCI SERR (default)
1 = CSERR is forwarded to PCI SERR.
†
This bit is global in nature and should be accessed only through function 0.
4–14
Table 4–6. Bridge Control Register Description (Continued)
BIT
SIGNAL
TYPE
FUNCTION
CardBus parity error response enable. This bit controls the response of the PCI4451 to CardBus parity
errors. This bit is separate for each socket.
0
CPERREN
R/W
0 = CardBus parity errors are ignored (default).
1 = CardBus parity errors are reported using CPERR.
4.25 Subsystem Vendor ID Register
The subsystem vendor ID register, used for system and option card identification purposes, may be required for
certain operating systems. This register is read-only or read/write, depending on the setting of bit 5 (SUBSYSRW)
in the system control register (offset 80h, See Section 4.28). When bit 5 is 0, this register is read/write; when bit 5
is 1, this register is read-only. The default mode is read-only.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Subsystem vendor ID
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Subsystem vendor ID
Read-only, (Read/Write when bit 5 in the system control register is 0)
Offset:
Default:
40h (Functions 0, 1)
0000h
4.26 Subsystem ID Register
The subsystem ID register, used for system and option card identification purposes, may be required for certain
operating systems. This register is read-only or read/write, depending on the setting of bit 5 (SUBSYSRW) in the
system control register (offset 80h, See Section 4.28). When bit 5 is 0, this register is read/write; when bit 5 is 1, this
register is read-only. The default mode is read-only.
If an EEPROM is present, then the subsystem ID and subsystem vendor ID will be loaded from EEPROM after a reset.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Subsystem ID
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Subsystem ID
Read-only, (Read/Write when bit 5 in the system control register is 0)
Offset:
Default:
42h (Functions 0, 1)
0000h
4–15
4.27 PC Card 16-Bit I/F Legacy Mode Base Address Register
The PCI4451 supports the index/data scheme of accessing the ExCA registers, which is mapped by this register. An
address written to this register is the address for the index register and the address+1 is the data address. Using this
access method, applications requiring index/data ExCA access can be supported. The base address can be mapped
anywhere in 32-bit I/O space on a word boundary; hence, bit 0 is read-only returning 1 when read. As specified in
the Yenta specification, this register is shared by functions 0 and 1. See the ExCA register set description in Section 5
for register offsets.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
PC Card 16-bit I/F legacy mode base address
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
PC Card 16-bit I/F legacy mode base address
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
1
Register:
Type:
PC Card 16-bit I/F legacy mode base address
Read-only, Read/Write
Offset:
Default:
44h (Functions 0, 1)
0000 0001h
4–16
4.28 System Control Register
System level initializations are performed through programming this doubleword register. Some of the bits are global
in nature and should be accessed only through function 0. See Table 4–7 for a complete description of the register
contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
System control
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
7
R/W
1
R/W
0
R/W
0
R/W
0
R/W
1
R/W
0
R/W
0
15
14
13
12
11
10
9
8
6
5
4
3
2
1
0
Name
Type
Default
System control
R/W
1
R/W
0
R
0
R
1
R
0
R
0
R
0
R
0
R
0
R/W
1
R/W
1
R/W
0
R/W
0
R
0
R/W
0
R/W
0
Register:
Type:
Offset:
Default:
System control
Read-only, Read/Write
80h (Functions 0, 1)
0000 0020h
Table 4–7. System Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
Serialized PCI interrupt routing step. These bits are used to configure the serialized PCI interrupt stream
signaling and accomplish an even distribution of interrupts signaled on the four PCI interrupt slots. These
bits are global to both PCI4451 functions.
§
00 = INTA/INTB/INTC signal in INTA/INTB/INTC slots (default)
01 = INTA/INTB/INTC signal in INTB/INTC/INTD slots
31–30
SER_STEP
R/W
10 = INTA/INTB/INTC signal in INTC/INTD/INTA slots
11 = INTA/INTB/INTC signal in INTD/INTA/INTB slots
Tie internal PCI interrupts. When this bit is set, the INTA and INTB signals are tied together internally and
are signaled as INTA. INTA may then be shifted by using the SER_STEP bits. This bit is global to both
PCI4451 functions. This bit has no effect on INTC.
§
29
INTRTIE
TIEALL
R/W
R/W
0 = INTA and INTB are not tied together internally (default).
1 = INTA and INTB are tied together internally.
This bit ties INTA, INTB, and INTC internally (to INTA) and reports this through the interrupt pin register
(offset 3Dh, see Section 4.23).
28
P2C power switch CLOCK. This bit determines whether the CLOCK terminal (GFN terminal U12, GJG
terminal T11) is an input that requires an external clock source or if this terminal is an output that uses the
internal oscillator. Bit 27 can be set to enable the PCI4451 to generate and drive CLOCK from the PCI
clock.
§
27
P2CCLK
R/W
0 = CLOCK privided externally, input to PCI4451 (default)
1 = CLOCK generated by PCI clock and driven by PCI4451
A 43-kW pulldown resistor should be tied to this terminal.
SMI interrupt routing. This bit is shared between functions 0 and 1, and selects whether IRQ2 or CSC is
signaled when a write occurs to power a PC Card socket.
§
26
SMIROUTE
SMISTATUS
SMIENB
R/W
R/W
R/W
0 = PC Card power change interrupts routed to IRQ2 (default).
1 = A CSC interrupt is generated on PC Card power changes.
SMI interrupt status. This socket-dependent bit is set when a write occurs to set the socket power, and
the SMIENB bit is set. Writing a 1 to this bit clears the status.
0 = SMI interrupt is signaled.
25
1 = SMI interrupt is not signaled.
SMI interrupt mode enable. When this bit is set, the SMI interrupt signaling generates an interrupt when
a write to the socket power control occurs. This bit is shared and defaults to 0 (disabled).
0 = SMI interrupt mode is disabled (default).
§
24
1 = SMI interrupt mode is enabled.
§
These bits are global in nature and should be accessed only through function 0.
4–17
Table 4–7. System Control Register Description (continued)
BIT
SIGNAL
TYPE
FUNCTION
23
RSVD
R
Reserved
CardBus reserved terminals signaling. When this bit is set, the RSVD CardBus terminals are driven
low when a CardBus card is inserted. When this bit is low, these signals are placed in a high-impedance
state.
22
CBRSVD
R/W
0 = Place the CardBus RSVD terminals in a high-impedance state
1 = Drive the Cardbus RSVD terminals low (default).
V
protection enable. This bit is socket dependent.
CC
0 = V
21
20
VCCPROT
R/W
R/W
protection is enabled for 16-bit cards (default).
protection is disabled for 16-bit cards.
CC
CC
1 = V
Reduced zoomed video enable. When this bit is enabled, AD25–AD22 of the card interface for PC Card
16 cards is placed in the high impedance state. This bit is encoded as:
0 = Reduced zoomed video is disabled (default).
REDUCEZV
1 = Reduced zoomed video is enabled.
PC/PCI DMA card enable. When this bit is set, the PCI4451 allows 16-bit PC Cards to request PC/PCI
DMA using the DREQ signaling. DREQ is selected through the socket DMA register 0 (offset 94h, see
Section 4.41).
19
CDREQEN
R/W
0 = Ignore DREQ signaling from PC Cards (default).
1 = Signal DMA request on DREQ.
PC/PCI DMA channel assignment. These bits are encoded as:
0–3 = 8-bit DMA channels
18–16
CDMACHAN
MRBURSTDN
MRBURSTUP
R/W
R/W
R/W
4 = PCI master; not used (default)
5–7 = 16-bit DMA channels
Memory read burst enable downstream. When this bit is set, memory read transactions are allowed
to burst downstream.
§
15
14
0 = MRBURSTDN downstream is disabled.
1 = MRBURSTDN downstream is enabled (default).
Memory read burst enable upstream. When this bit is set, the PCI4451 allows memory read
transactions to burst upstream.
§
0 = MRBURSTUP upstream is disabled (default).
1 = MRBURSTUP upstream is enabled.
Socket activity status. When set, this bit indicates access has been performed to or from a PC Card.
Reading this bit causes it to be cleared. This bit is socket dependent.
0 = No socket activity (default)
13
12
SOCACTIVE
RSVD
R
R
1 = Socket activity
Reserved. This bit returns 1 when read. This is the power rail bit in functions 0 and 1.
Power stream in progress status bit. When set, this bit indicates that a power stream to the power switch
is in progress and a powering change has been requested. When this bit is clear, it indicates that the
power stream is complete.
11
10
PWRSTREAM
DELAYUP
R
R
0 = Power stream is complete, delay has expired (default).
1 = Power stream is in progress.
Power-up delay in progress status bit. When set, this bit indicates that a power-up stream has been
sent to the power switch, and proper power may not yet be stable. This bit is cleared when the power-up
delay has expired.
0 = Power-up delay has expired (default).
1 = Power-up stream sent to switch. Power might not be stable.
Power-down delay in progress status bit. When set, this bit indicates that a power-down stream has
been sent to the power switch, and proper power may not yet be stable. This bit is cleared when the
power-down delay has expired.
9
8
DELAYDOWN
R
R
0 = Power-down delay has expired (default).
1 = Power-down stream sent to switch. Power might not be stable.
Interrogation in progress. When set, this bit indicates an interrogation is in progress, and clears when
the interrogation completes. This bit is socket-dependent.
0 = Interrogation not in progress (default)
INTERROGATE
1 = Interrogation in progress
§
These bits are global in nature and should be accessed only through function 0.
4–18
Table 4–7. System Control Register Description (continued)
BIT
SIGNAL
TYPE
FUNCTION
7
RSVD
R
Reserved. This bit returns 0 when read.
Power savings mode enable. When this bit is set, the PCI4451 will consume less power with no
performance loss. This bit is shared between the two PCI4451 functions.
0 = Power savings mode disabled
§
6
5
PWRSAVINGS
R/W
1 = Power savings mode enabled (default)
Subsystem ID (SS ID), subsystem vendor ID (SS VID), and the ExCA identification and revision
registers read/write enable. This bit is shared by functions 0 and 1. This bit does not control read/write
of function 2, subsystem ID register.
§
0 = Subsystem ID, subsystem vendor ID, and the ExCA identification and revision registers are
read/write.
1 = Subsystem ID, subsystem vendor ID, and the ExCA identification and revision registers are
read-only (default).
SUBSYSRW
CB_DPAR
R/W
R/W
CardBus data parity SERR signaling enable.
§
§
4
0 = CardBus data parity not signaled on PCI SERR signal (default)
1 = CardBus data parity signaled on PCI SERR signal
PC/PCI DMA enable. Enables PC/PCI DMA when set. When PC/PCI DMA is enabled, PCREQ and
PCGNT should be routed to a multifunction routing terminal. See multifunction routing status register
(offset 8Ch, see Section 4.36) for options.
3
CDMA_EN
RSVD
R/W
R
0 = Centralized DMA disabled (default)
1 = Centralized DMA enabled
2
Reserved. This bit returns 0 when read.
Keep clock. When this bit is set, the PCI4451 will always follow CLKRUN protocol to maintain the
system PCLK and the CCLK (CardBus clock). This bit is global to the PCI4451 functions.
0 = Allow system PCLK and CCLK to stop (default)
§
1
1 = Never allow system PCLK or CCLK clock to stop
KEEPCLK
R/W
Note that the functionality of this bit has changed relative to that of the PCI12XX family of TI CardBus
controllers. In these CardBus controllers, setting this bit would only maintain the PCI clock, not the
CCLK. In the PCI4451, setting this bit will maintain both the PCI clock and the CCLK.
PME/RI_OUT select bit. When this bit is 1, the PME signal is routed on to pin Y13 (PME/RI_OUT pin).
When this bit is 0 and bit 7 (RIENB) of the card control register is 1, the RI_OUT signal is routed on
to pin Y13 (GFN) or pin R11 (GJG). If this bit is 0 and bit 7 (RIENB) of the card control register is 0, then
the output (Y13 or R11) will be placed in a high-impedance state. This pin is encoded as:
0 = RI_OUT signal is routed to pin Y13 (GFN) or pin R11 (GJG) if bit 7 of the card control register
is 1. (default)
§
0
RIMUX
R/W
1 = PME signal is routed on pin Y13 (GFN) or pin R11 (GJG) of the PCI4451 controller.
NOTE: If this bit (bit 0) is 0 and bit 7 of the card control register (offset 91h, see Section 4.38) is 0, then
the output on pin Y13 (GFN) or pin R11 (GJG) is placed in a high-impedance state.
§
These bits are global in nature and should be accessed only through function 0.
4–19
4.29 Multimedia Control Register
The multimedia control register provides port mapping for the PCI4451 zoomed video/data ports. See Section 3.4.3,
Zoomed Video Support, for details on the PCI4451 zoomed video support. Access this register only through
function 0. See Table 4–8 for a complete description of the register contents.
BIT
Name
Type
7
6
5
4
3
2
1
0
Multimedia control
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Default
Register:
Type:
Multimedia control
Read/Write
Offset:
Default:
84h (Functions 0, 1)
00h
Table 4–8. Multimedia Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
ZV output enable. This bit enables the output for the PCI4451 outsourcing ZV terminals. When this bit
is reset, 0, these terminals are in a high impedance state.
0 = PCI4451 ZV output terminals disabled (default)
7
ZVOUTEN
R/W
1 = PCI4451 ZV output terminals enabled
ZV port select. This bit controls the multiplexing controller over which PC Card ZV port data will be driven
to the outsourcing PCI4451 ZV port.
6
5
PORTSEL
ZVAUTO
R/W
R/W
0 = Output card 0 if ZV is enabled (default)
1 = Output card 1 if ZV is enabled
Zoomed video autodetect. This bit enables the zoomed video autodetect feature. This bit is encoded as:
0 = Zoomed video autodetect disabled (default)
1 = Zoomed video autodetect enabled
Autodetect priority encoding. These bits have meaning only if zoomed video autodetect is enabled in
bit 5 of this register. If autodetect is enabled, then bits 4–2 are encoded as follows:
000 = Slot A, slot B, external source
001 = Slot A, external source, slot B
010 = Slot B, slot A, external source
011 = Slot B, external source, slot A
4–2
AUTODETECT
R/W
100 = External source, slot A, slot B
101 = External source, slot B, slot A
110 = Reserved
111 = Reserved
PC Card 1 ZV mode enable. Enables the zoomed video mode for socket 1. When set, the PCI4451 inputs
ZV data from the PC Card interface, and disables output drivers on ZV terminals.
0 = PC Card 1 ZV disabled (default)
1
0
ZVEN1
ZVEN0
R/W
R/W
1 = PC Card 1 ZV enabled
PC Card 0 ZV mode enable. Enables the zoomed video mode for socket 0. When set, the PCI4451 inputs
ZV data from the PC Card interface, and disables output drivers on ZV terminals.
0 = PC Card 0 ZV disabled (default)
1 = PC Card 0 ZV enabled
4–20
4.30 General Status Register
The general status register provides the general device status information. The status of the serial EEPROM interface
is provided through this register. See Table 4–9 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
General status
R/U
0
R
0
R
0
R
0
R
0
R/U
X
R
0
R
0
Register:
Type:
Offset:
Default:
General status
Read/Update, Read–only
85h (Functions 0)
00h
Table 4–9. General Status Register Description
FUNCTION
BIT
7
SIGNAL
IDSEL_DET
RSVD
TYPE
R/U
R
When this bit is set, the IDSEL/MFUNC7 terminal functions as an IDSEL input.
Reserved. These bits return 0s when read.
6–3
Serial EEPROM detect. Serial EEPROM is detected by sampling a logic high on SCL or PRST. When this
bit is set, the serial ROM is detected. This status bit is encoded as:
0 = EEPROM not detected (default)
§
2
§
1
§
0
EEDETECT
DATAERR
EEBUSY
R/U
R
1 = EEPROM detected
Serial EEPROM data error status. This bit indicates when a data error occurs on the serial EEPROM
interface. This bit may be set due to a missing acknowledge. This bit is cleared by a writing a 1.
0 = No error detected. (default)
1 = Data error detected.
Serial EEPROM busy status. This bit indicates the status of the PCI4451 serial EEPROM circuitry. This bit
is set during the loading of the subsystem ID value.
R
0 = Serial EEPROM circuitry is not busy (default).
1 = Serial EEPROM circuitry is busy.
§
This bit is global in nature and should only be accessed through function 0.
4–21
4.31 General Control Register
The general control register provides top level PCI arbitration control. See Table 4–10 for a complete description of
the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
General control
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
General control
Read-only, Read/Write
Offset:
Default:
86h
00h
Table 4–10. General Control Register Description
BIT
7–4
3
SIGNAL
RSVD
TYPE
FUNCTION
R
Reserved. These bits return 0s when read.
DISABLE_OHCI
GP2IIC
R/W
R/W
When this bit is set, the open HCI 1394 controller function is completely inaccessible and nonfunctional.
When this bit is set, the GPO0 and GPO1 signals are routed to SDA and SCL, respectively.
2
Controls top level PCI arbitration.
00 = 1394 open HCI priority
01 = CardBus priority
1–0
ARB_CTRL
R/W
10 = Fair round robin
11 = Reserved (fair round robin)
4–22
4.32 General-Purpose Event Status Register
The general-pupose event status register contains status bits that are set when general events occur and may be
programmed to generate general-purpose event signalling through GPE. See Table 4–11 for a complete description
of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
General-purpose event status
RCU
0
RCU
0
R
0
R
0
RCU
0
RCU
0
RCU
0
RCU
0
Register:
Type:
General-purpose event status
Read/Clear/Update, Read-only
Offset:
Default:
88h
00h
Table 4–11. General-Purpose Event Status Register Description
BIT
SIGNAL
TYPE
FUNCTION
7
PWR_STS
RCU
Power change status. This bit is set when software changes the V
or V
PP
power state of either socket.
level to or from 12 V
CC
12V V
for either socket.
request status. This bit is set when software has changed the requested V
PP
PP
6
5–4
3
VPP12_STS
RSVD
RCU
R
Reserved. These bits return 0 when read. A write has no effect.
GPI3 status. This bit is set on a change in status of the MFUNC3 terminal input level if configured as a
general-purpose input, GPI3.
GP3_STS
RCU
GPI2 status. This bit is set on a change in status of the MFUNC2 terminal input level if configured as a
general-purpose input, GPI2.
2
1
0
GP2_STS
GP1_STS
GP0_STS
RCU
RCU
RCU
GPI1 status. This bit is set on a change in status of the MFUNC1 terminal input level if configured as a
general-purpose input, GPI1.
GPI0 status. This bit is set on a change in status of the MFUNC0 terminal input level if configured as a
general-purpose input, GPI0.
4–23
4.33 General-Purpose Event Enable Register
The general-purpose event enable register contains bits that are set to enable GPE signals. See Table 4–12 for a
complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
General-purpose event enable
R/W
0
R/W
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
General-purpose event enable
Read-only, Read/Write
Offset:
Default:
89h
00h
Table 4–12. General-Purpose Event Enable Register Description
BIT
7
SIGNAL
PWR_EN
VPP12_EN
RSVD
TYPE
R/W
R/W
R
FUNCTION
Power change GPE enable. When this bit is set, GPE is signaled on PWR_STS events.
12-Volt V GPE enable. When this bit is set, GPE is signaled on VPP12_STS events.
6
PP
5–4
3
Reserved. These bits return 0 when read. A write has no effect.
GP3_EN
GP2_EN
GP1_EN
GP0_EN
R/W
R/W
R/W
R/W
GPI3 GPE enable. When this bit is set, GPE is signaled on GP3_STS events.
GPI2 GPE enable. When this bit is set, GPE is signaled on GP2_STS events.
GPI1 GPE enable. When this bit is set, GPE is signaled on GP1_STS events.
GPI0 GPE enable. When this bit is set, GPE is signaled on GP0_STS events.
2
1
0
4.34 General-Purpose Input Register
The general-purpose input register contains GPI terminal status. See Table 4–13 for a complete description of the
register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
General-purpose input
R
0
R
0
R
0
R
0
RU
X
RU
X
RU
X
RU
X
Register:
Type:
General-purpose input
Read/Update, Read-only
Offset:
Default:
8Ah
0Xh
Table 4–13. General-Purpose Input Register Description
FUNCTION
BIT
7–4
3
SIGNAL
RSVD
TYPE
R
Reserved. These bits return 0s when read. Writes have no effect.
GPI3_DATA
GPI2_DATA
GPI1_DATA
GPI0_DATA
RU
RU
RU
RU
GPI3 data input. This bit represents the logical value of the data input from GPI3.
GPI2 data input. This bit represents the logical value of the data input from GPI2.
GPI1 data input. This bit represents the logical value of the data input from GPI1.
GPI0 data input. This bit represents the logical value of the data input from GPI0.
2
1
0
4–24
4.35 General-Purpose Output Register
The general-purpose output register is used to drive the GPO3–GPO0 outputs. See Table 4–14 for a complete
description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
General-purpose output
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
General-purpose output
Read-only, Read/Write
Offset:
Default:
8Bh
00h
Table 4–14. General-Purpose Output Register Description
BIT
7–4
3
SIGNAL
RSVD
TYPE
FUNCTION
Reserved. These bits return 0s when read. Writes have no effect.
This bit represents the logical value of the data driven to GPO3.
This bit represents the logical value of the data driven to GPO2.
This bit represents the logical value of the data driven to GPO1.
This bit represents the logical value of the data driven to GPO0.
R
GPO3_DATA
GPO2_DATA
GPO1_DATA
GPO0_DATA
R/W
R/W
R/W
R/W
2
1
0
4–25
4.36 Multifunction Routing Status Register
The multifunction routing status register is used to configure MFUNC7–MFUNC0 terminals. These terminals may be
configured for various functions. This register is intended to be programmed once at power-on initialization. The
default value for this register may also be loaded through a serial ROM. See Table 4–15 for a complete description
of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Multifunction routing status
R
0
R/W
0
R/W
0
R/W
0
R
0
R/W
0
R/W
0
R/W
0
R
0
7
R/W
0
R/W
0
R/W
0
R
0
3
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
6
5
4
2
1
0
Name
Type
Default
Multifunction routing status
R
0
R/W
0
R/W
0
R/W
0
R
0
R/W
0
R/W
0
R/W
0
R
0
R/W
0
R/W
0
R/W
0
R
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Offset:
Default:
Multifunction routing status
Read/Write
8Ch
0000 0000h
Table 4–15. Multifunction Routing Status Register Description
BIT
SIGNAL
TYPE
FUNCTION
31
RSVD
R
Reserved. This bit returns 0 when read. Writes have no effect.
MFUNC7 select. These bits control the mapping of MFUNC7 as follows:
000 = IDSEL
100 = D3_STAT
101 = LOCK
110 = RSVD
111 = RSVD
30–28
27
MFUNC7_SEL
RSVD
R/W
R
001 = RI_OUT
010 = OHCI_LED
011 = PCREQ
Reserved. This bit returns 0 when read. Writes have no effect.
MFUNC6 select. These bits control the mapping of MFUNC6 as follows:
000 = RSVD
001 = RSVD
010 = OHCI_LED
011 = RSVD
100 = D3_STAT
101 = RI_OUT
110 = CAUDPWM
111 = PCGNT
26–24
23
MFUNC6_SEL
RSVD
R/W
R
Reserved. This bit returns 0 when read. Writes have no effect.
MFUNC5 select. These bits control the mapping of MFUNC5 as follows:
000 = RSVD
001 = RSVD
010 = OHCI_LED
011 = RSVD
100 = RSVD
101 = GPE
110 = CAUDPWM
111 = PCREQ
22–20
19
MFUNC5_SEL
RSVD
R/W
R
Reserved. This bit returns 0 when read. Writes have no effect.
MFUNC4 select. These bits control the mapping of MFUNC4 as follows:
000 = RSVD
001 = RSVD
010 = LEDA1
011 = PCREQ
100 = RSVD
101 = GPE
110 = RSVD
111 = ZV_STAT
18–16
15
MFUNC4_SEL
RSVD
R/W
R
Reserved. This bit returns 0 when read. Writes have no effect.
MFUNC3 select. These bits control the mapping of MFUNC3 as follows:
000 = GPI3
100 = RSVD
101 = LOCK
110 = RSVD
111 = C_ZVCLK
14–12
MFUNC3_SEL
R/W
001 = GPO3
010 = LEDA2
011 = PCGNT
4–26
Table 4–15. Multifunction Routing Status Register Description (continued)
BIT
SIGNAL
TYPE
FUNCTION
11
RSVD
R
Reserved. This bit returns 0 when read. Writes have no effect.
MFUNC2 select. These bits control the mapping of MFUNC2 as follows:
000 = GPI2
001 = GPO2
010 = INTC
011 = PCGNT
100 = D3_STAT
101 = RSVD
110 = RSVD
10–8
7
MFUNC2_SEL
RSVD
R/W
R
111 = C_ZVCLK
Reserved. This bit returns 0 when read. Writes have no effect.
MFUNC1 select. These bits control the mapping of MFUNC1 as follows:
000 = GPI1
001 = GPO1
010 = INTB
100 = D3_STAT
101 = LOCK
110 = CAUDPWM
111 = ZV_STAT
6–4
3
MFUNC1_SEL
RSVD
R/W
R
011 = TEST_MUX
Reserved. This bit returns 0 when read. Writes have no effect.
MFUNC0 select. These bits control the mapping of MFUNC0 as follows:
000 = GPI0
001 = GPO0
010 = INTA
011 = PCREQ
100 = RSVD
101 = GPE
110 = RSVD
111 = ZV_STAT
2–0
MFUNC0_SEL
R/W
4–27
4.37 Retry Status Register
The contents of the retry status register enable the retry time-out counters and display the retry expiration status. The
15
flags are set when the PCI4451 retries a PCI or CardBus master request, and the master does not return within 2
PCI clock cycles. The flags are cleared by writing a 1 to the bit. These bits are expected to be incorporated into the
PCI command register, status register, and bridge control register (offset 3Eh, see Section 4.24) by the PCI SIG.
Access this register only through function 0. See Table 4–16 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Retry status
R/W
1
R/W
1
RC
0
R
0
RC
0
R
0
RC
0
R
0
Register:
Type:
Offset:
Default:
Retry status
Read-only, Read/Write, Read/Clear
90h (Functions 0, 1)
C0h
Table 4–16. Retry Status Register Description
BIT
SIGNAL
TYPE
FUNCTION
PCI retry time-out counter enable. This bit is encoded as:
0 = PCI retry counter disabled
7
PCIRETRY
R/W
1 = PCI retry counter enabled (default)
CardBus retry time-out counter enable. This bit is encoded as:
0 = CardBus retry counter disabled
§
6
CBRETRY
R/W
1 = CardBus retry counter enabled (default)
CardBus target B retry expired. Write a 1 to clear this bit.
0 = Inactive (default)
5
TEXP_CBB
RSVD
RC
R
1 = Retry has expired.
4
Reserved. This bit returns 0 when read.
CardBus target A retry expired. Write a 1 to clear this bit.
0 = Inactive (default)
§
3
TEXP_CBA
RSVD
RC
R
1 = Retry has expired.
2
1
0
Reserved. This bit returns 0 when read.
PCI target retry expired. Write a 1 to clear this bit.
TEXP_PCI
RC
0 = Inactive (default)
1 = Retry has expired.
RSVD
R
Reserved. This bit returns 0 when read.
§
These bits are global in nature and should be accessed only through function 0.
4–28
4.38 Card Control Register
The card control register is provided for PCI1130 compatibility. The contents provide the PC Card function interrupt
flag (IFG) and an alias for the ZVEN0 and ZVEN1 bits found in the PCI4451 multimedia control register. When this
register is accessed by function 0, the ZVEN0 bit will alias with ZVENABLE. When this register is accessed by function
1, the ZVEN1 bit will alias with ZVENABLE. Setting ZVENABLE only places the PC Card socket interface ZV terminals
in a high impedance state, but does not enable the PCI4451 to drive ZV data onto the ZV terminals. See Table 4–17
for a complete description of the register contents.
The RI_OUT signal is enabled through this register, and the enable bit is shared between functions 0 and 1.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Card control
R/W
0
R/W
0
R/W
0
R
0
R
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Card control
Read-only, Read/Write
Offset:
Default:
91h
00h
Table 4–17. Card Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
Ring indicate enable. When this bit is 1, the RI_OUT output is enabled. This bit is global in nature and
should be accessed only through function 0. This bit defaults to 0.
§
7
RIENB
R/W
Compatibility ZV mode enable. When this bit is 1, the corresponding PC Card socket interface ZV
terminals will enter a high impedance state. This bit defaults to 0.
6
ZVENABLE
R/W
5
RSVD
RSVD
R/W
R
Reserved.
4–3
Reserved. These bits default to 0.
CardBus Audio-to-MFUNC. When this bit is set, the CAUDIO CardBus signal must be routed through an
MFUNC terminal. If this bit is set for both functions, then function 0 gets routed.
2
1
AUD2MUX
R/W
0 = CAUDIO set to CAUDPWM on MFUNC terminal (default)
1 = CAUDIO is not routed.
Speaker output enable. When this bit is 1, it enables SPKR on the PC Card and routes it to SPKROUT
on the PCI bus. The SPKR signal from socket 0 is XOR’ed with the SPKR signal from socket 1 and sent
to SPKROUT. The SPKROUT terminal only drives data when either functions SPKROUTEN bit is set. This
bit is encoded as:
SPKROUTEN
R/W
0 = SPKR to SPKROUT not enabled (default)
1 = SPKR to SPKROUT enabled
Interrupt flag. This bit is the interrupt flag for 16-bit I/O PC Cards and for CardBus cards. This bit is set when
a functional interrupt is signaled from a PC Card interface, and is socket dependent (i.e., not global). Write
back a 1 to clear this bit.
0
IFG
R/W
0 = No PC Card functional interrupt detected (default)
1 = PC Card functional interrupt detected
§
These bits are global in nature and should be accessed only through function 0.
4–29
4.39 Device Control Register
The device control register is provided for PCI1130 compatibility. It contains bits which are shared between functions
0 and 1. The interrupt mode select is programmed through this register. The socket capable force bits are also
programmed through this register. See Table 4–18 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Device control
R/W
0
R/W
1
R/W
1
R
0
R/W
0
R/W
1
R/W
1
R/W
0
Register:
Type:
Offset:
Default:
Device control
Read-only, Read/Write
92h (Functions 0, 1)
66h
Table 4–18. Device Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
Socket power lock bit. When this bit is set to 1, software will not be able to power down the PC Card
socket while in D3. This may be necessary to support Wake on LAN or RING if the operating system
is programmed to power down a socket when the CardBus controller is placed in the D3 state.
7
SKTPWR_LOCK
R/W
3-V socket capable force bit.
0 = Not 3-V capable
§
6
3VCAPABLE
R/W
1 = 3-V capable (default)
5
IO16R2
RSVD
TEST
R/W
R
Diagnostic bit. This bit defaults to 1.
4
Reserved. This bit returns 0 when read. A write has no effect.
TI test bit. Write only 0 to this bit. This bit can be set to shorten the interrogation counter.
§
3
R/W
Interrupt mode. These bits select the interrupt signaling mode. The interrupt mode bits are encoded:
00 = Parallel PCI interrupts only
§
01 = Reserved
2–1
INTMODE
R/W
10 = IRQ serialized interrupts and parallel PCI interrupts INTA and INTB
11 = IRQ & PCI serialized interrupts (default)
Reserved. NAND tree enable bit. There is a NAND tree diagnostic structure in the PCI4451, and it tests
only the pins that are inputs or I/Os. Any output-only terminal on the PCI4451 is excluded from the
NAND tree test.
§
0
RSVD
R/W
§
These bits are global in nature and should be accessed only through function 0.
4–30
4.40 Diagnostic Register
The diagnostic register is provided for internal Texas Instruments test purposes. See Table 4–19 for a complete
description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Diagnostic
R/W
0
R/W
1
R/W
1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
Register:
Type:
Diagnostic
Read/Write
Offset:
Default:
93h (Functions 0, 1)
61h
Table 4–19. Diagnostic Register Description
FUNCTION
BIT
SIGNAL
TRUE_VAL
RSVD
TYPE
R/W
This bit defaults to 0. This bit is encoded as:
§
7
0 = Reads true values in PCI vendor ID and PCI device ID registers (default).
1 = Reads all ones in reads to the PCI vendor ID and PCI device ID registers.
6
R/W
Reserved.
CSC interrupt routing control
0 = CSC interrupts routed to PCI if ExCA 803 bit 4 = 1.
1 = CSC Interrupts routed to PCI if ExCA 805 bits 7–4 = 0000b (default). In this case, the setting of
ExCA 803 bit 4 is a don’t care.
5
CSC
R/W
§
4
3
2
1
DIAG
DIAG
DIAG
DIAG
R/W
R/W
R/W
R/W
Diagnostic RETRY_DIS. Delayed transaction disable.
§
§
§
Diagnostic RETRY_EXT. Extends the latency from 16 to 64.
10
15
15
Diagnostic DISCARD_TIM_SEL_CB. Set = 2 , Reset = 2
10
Diagnostic DISCARD_TIM_SEL_PCI. Set = 2 , Reset = 2
Asynchronous interrupt generation.
§
0
ASYNC_CSC
R/W
0 = CSC interrupt not generated asynchronously
1 = CSC interrupt is generated asynchronously (default)
These bits are global in nature and should be accessed only through function 0.
§
4–31
4.41 Socket DMA Register 0
This register provides control over the PC Card DREQ (DMA request) signaling. See Table 4–20 for a complete
description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Socket DMA register 0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Socket DMA register 0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
Register:
Type:
Offset:
Default:
DMA socket register 0
Read-only, Read/Write
94h (Functions 0, 1)
0000 0000h
Table 4–20. Socket DMA Register 0 Description
FUNCTION
BIT
SIGNAL
TYPE
31–2
RSVD
R
Reserved. These bits return 0s when read.
DMA request (DREQ) pin. These bits indicate which pin on the 16-bit PC Card interface will use the DREQ
signal during DMA transfers. This field is encoded as:
00 = Socket not configured for DMA (default)
01 = DREQ uses SPKR
1–0
DREQPIN
R/W
10 = DREQ uses IOIS16
11 = DREQ uses INPACK
4–32
4.42 Socket DMA Register 1
The contents of this register provide control over the distributed DMA (DDMA) registers and the PCI portion of DMA
transfers. The DMA base address locates the DDMA registers in a 16-byte region within the first 64K bytes of PCI
I/O address space. Note that 32-bit transfers to the 16-bit PC Card interface are not supported; the maximum transfer
possible to the PC Card interface is 16-bits. However, 32 bits of data are prefetched from the PCI bus, thus allowing
back-to-back 16-bit transfers to the PC Card interface. See Table 4–21 for a complete description of the register
contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Socket DMA register 1
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Socket DMA register 1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Offset:
Default:
DMA socket register 1
Read-only, Read/Write
98h (Functions 0, 1)
0000 0000h
Table 4–21. Socket DMA Register 1 Description
FUNCTION
BIT
SIGNAL
TYPE
31–16
RSVD
R
Reserved. These bits return 0s when read.
DMA base address. Locates the socket DMA registers in PCI I/O space. This field represents a 16-bit PCI
I/O address. The upper 16 bits of the address are hardwired to 0, forcing this window to within the lower 64K
bytes of I/O address space. The lower four bits are hardwired to 0, and are included in the address decode.
Thus, the window is aligned to a natural 16-byte boundary.
15–4
DMABASE
EXTMODE
R/W
R
3
Extended addressing. This feature is not supported by the PCI4451, and always returns a 0.
Transfer size. These bits specify the width of the DMA transfer on the PC Card interface, and are encoded
as:
00 = Transfers are 8 bits (default).
01 = Transfers are 16 bits.
10 = Reserved
2–1
XFERSIZE
DDMAEN
R/W
R/W
11 = Reserved
DDMA registers decode enable. Enables the decoding of the distributed DMA registers based upon the
value of DMABASE.
0
0 = Disabled (default)
1 = Enabled
4–33
4.43 Capability ID Register
The capability ID register identifies the linked list item as the register for PCI power management. The register returns
01h when read, which is the unique ID assigned by the PCI SIG for the PCI location of the capabilities pointer and
the value.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Capability ID
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
1
Register:
Type:
Offset:
Default:
Capability ID
Read-only
A0h
01h
4.44 Next Item Pointer Register
The contents of this register indicate the next item in the linked list of the PCI power management capabilities. Since
the PCI4451 functions only include one capabilities item, this register returns 0s when read.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Next item pointer
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
Next item pointer
Read-only
A1h
00h
4–34
4.45 Power Management Capabilities Register
The power management capabilities register contains information on the capabilities of the PC Card function related
to power management. Both PCI4451 CardBus bridge functions support D0, D1, D2, and D3 power states. Default
register value is FE12h for operation in accordance with PCI Bus Power Management Interface Specification revision
1.1, or FE11h for operation in accordance with PCI Bus Power Management Interface Specification revision 1.0. See
Table 4–22 for a complete description of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Power management capabilities
R/W
1
R
1
R
1
R
1
R
1
R
1
R
1
R
0
R
0
R
0
R
0
R
1
R
0
R
0
R
1
R
0
Register:
Type:
Offset:
Default:
Power management capabilities
Read-only, Read/Write
A2h (Functions 0, 1)
FE12h
Table 4–22. Power Management Capabilities Register Description
BIT
SIGNAL
TYPE
FUNCTION
This 5-bit field indicates the power states from which the PCI4451 device functions may assert PME. A
0b (zero) for any bit indicates that the function cannot assert the PME signal while in that power state.
These five bits return 0Fh when read. Each of these bits is described below:
15
R/W
R
Bit 15 – defaults to a 1 indicating the PME signal can be asserted from the D3
because wake-up support from D3
cold
state. This bit is read/write
is contingent on the system providing an auxiliary power source
cold
to the V
terminals for D3
cold
terminals. If the system designer chooses not to provide an auxiliary power source to the V
PME support
CC
CC
wake-up support, then BIOS should write a 0 to this bit.
14–11
Bit 14 – contains the value 1 to indicate that the PME signal can be asserted from the D3 state.
hot
Bit 13 – contains the value 1 to indicate that the PME signal can be asserted from the D2 state.
Bit 12 – contains the value 1 to indicate that the PME signal can be asserted from the D1 state.
Bit 11 – contains the value 1 to indicate that the PME signal can be asserted from the D0 state.
10
9
D2_Support
D1_Support
RSVD
R
R
R
R
This bit returns a 1 when read, indicating that the function supports the D2 device power state.
This bit returns a 1 when read, indicating that the function supports the D1 device power state.
Reserved. These bits return 000b when read.
8–6
5
DSI
Device specific initialization. This bit returns 0 when read.
Auxiliary power source. This bit is meaningful only if bit 15 (D3
supporting PME) is set. When this bit
cold
requires auxiliary power supplied by the system by way
is set, it indicates that support for PME in D3
of a proprietary delivery vehicle.
cold
4
AUX_PWR
R
A 0 (zero) in this bit field indicates that the function supplies its own auxiliary power source.
If the function does not support PME while in the D3
0.
state (bit 15=0), then this field must always return
cold
When this bit is 1, it indicates that the function relies on the presence of the PCI clock for PME operation.
When this bit is 0, it indicates that no PCI clock is required for the function to generate PME.
3
PMECLK
Version
R
R
Functions that do not support PME generation in any state must return 0 for this field.
These 3 bits return 010b when read, indicating that there are 4 bytes of general-purpose power
management (PM) registers as described in the draft revision 1.1 PCI Bus Power Management Interface
Specification. However, 001b supports PCI Bus Power Management Interface Specification revision 1.0.
2–0
4–35
4.46 Power Management Control/Status Register
The power management control/status register determines and changes the current power state of the PCI4451
CardBus function. The contents of this register are not affected by the internally generated reset caused by the
transition from the D3
to D0 state. See Table 4–23 for a complete description of the register contents.
hot
All PCI registers, ExCA registers, and CardBus registers are reset as a result of a D3 -to-D0 state transition, with
hot
the exception of the PME context bits (if PME is enabled) and the GRST only bits.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Power management control/status
R/WC
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
Register:
Type:
Power management control/status
Read-only, Read/Write, Read/Write to Clear
Offset:
Default:
A4h (Functions 0, 1)
0000h
Table 4–23. Power Management Control/Status Register Description
BIT
SIGNAL
TYPE
FUNCTION
PME status. This bit is set when the CardBus function would normally assert the PME signal, independent
15
PMESTAT
R/WC of the state of the PME_EN bit. This bit is cleared by a write back of 1, and this also clears the PME signal
if PME was asserted by this function. Writing a 0 to this bit has no effect.
This 2-bit field returns 0s when read. The CardBus function does not return any dynamic data, as indicated
by the DYN_DATA bit.
14–13
12–9
DATASCALE
DATASEL
R
Data select. This 4-bit field returns 0s when read. The CardBus function does not return any dynamic data,
as indicated by the DYN_DATA bit.
R
This bit enables the function to assert PME. If this bit is cleared, then assertion of PME is disabled. This
bit will not be cleared by the assertion of PRST. It will only be cleared by the assertion of GRST.
8
PME enable
RSVD
R/W
7–2
R
Reserved. These bits return 0s when read.
Power state. This 2-bit field is used both to determine the current power state of a function and to set the
function into a new power state. This field is encoded as:
00 = D0
01 = D1
10 = D2
1–0
PWRSTATE
R/W
11 = D3
hot
4–36
4.47 Power Management Control/Status Bridge Support Extensions Register
This register supports PCI bridge specific functionality. It is required for all PCI-to-PCI bridges. See Table 4–24 for
a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Power management control/status bridge support extensions
R
1
R
1
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Power management control/status bridge support extensions
Read-only
Offset:
Default:
A6h (Functions 0, 1)
C0h
Table 4–24. Power Management Control/Status Bridge Support Extensions Register
BIT
SIGNAL
TYPE
FUNCTION
Bus power/clock control enable. This bit returns 1 when read. This bit is encoded as:
0 = Bus power/clock control is disabled.
1 = Bus power/clock control is enabled (default).
A 0 indicates that the bus power/clock control policies defined in the PCI Power Management specification
are disabled. When the bus power/clock control enable mechanism is disabled, the bridge’s PMCSR
powerstate field cannot be used by the system software to control the power or the clock of the bridge’s
secondary bus. A 1 indicates that the bus power/clock control mechanism is enabled. When bus
power/clock control is disabled, the bridge’s PMCSR power state field cannot be used by the system
software to control power or the clock of the bridge’s secondary bus.
7
BPCC_Enable
R
B2/B3 support for D3 . The state of this bit determines the action that is to occur as a direct result
hot
of programming the function to D3 . This bit is only meaningful if bit 7 (BPCC_Enable) is a 1. This bit is
hot
encoded as:
6
B2_B3
RSVD
R
R
0 = When the bridge is programmed to D3 , its secondary bus will have its power removed (B3).
1 = When the bridge function is programmed to D3 , its secondary bus PCI clock is stopped (B2)
hot
hot
(default).
5–0
Reserved. These bits return 0s when read.
4–37
4.48 GPE Control/Status Register
If the GPE (general-purpose event) function is programmed onto the MFUNC5 pin by writing 101b to bits 22–20 of
the multifunction routing status register (PCI offset 8Ch, see Section 4.36), then this register may be used to program
which events will cause GPE to be asserted and report the status. See Table 4–25 for a complete description of the
register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
GPE control/status
R
0
R
0
R
0
R
0
R
0
RC
0
RC
0
RC
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
Register:
Type:
GPE control/status
Read-only, Read/Write, Read/Clear
Offset:
Default:
A8h
0001h
Table 4–25. GPE Control/Status Register Description
BIT
15–11
10
SIGNAL
TYPE
FUNCTION
RSVD
R
Reserved. These bits return 0s when read.
ZV1_STS
ZV0_STS
RC
RC
PC Card socket 1 status. This bit is set on a change in status of the ZVENABLE bit in function 1.
PC Card socket 0 status. This bit is set on a change in status of the ZVENABLE bit in function 0.
9
12-volt V
PP
request status. This bit is set when software has changed the requested V
from 12 volts from either socket.
level to or
PP
8
7–3
2
VPP12_STS
RSVD
RC
R
Reserved. These bits return 0s when read.
PC Card socket 1 zoomed video event enable. When this bit is set, GPE is signaled on a change in
status of the ZVENABLE bit in function 1 of the PC Card controller.
ZV1_EN
R/W
PC Card socket 0 zoomed video event enable. When this bit is set, GPE is signaled on a change in
status of the ZVENABLE bit in function 0 of the PC Card controller.
1
0
ZV0_EN
R/W
R/W
12 Volt V
request event enable. When this bit is set, a GPE is signaled when software has changed
level to or from 12 Volts for either socket.
PP
VPP12_EN
the requested V
PP
4–38
5 ExCA Compatibility Registers (Functions 0 and 1)
The ExCA (exchangeable card architecture) registers implemented in the PCI4451 are register-compatible with the
Intel 82365SL-DF PCMCIA controller. ExCA registers are identified by an offset value, which is compatible with the
legacy I/O index/data scheme used on the Intel 82365 ISA controller. The ExCA registers are accessed through this
scheme by writing the register offset value into the index register (I/O base), and reading or writing the data register
(I/O base + 1). The I/O base address used in the index/data scheme is programmed in the PC Card 16-bit I/F legacy
mode base address register, which is shared by both card sockets. The offsets from this base address run contiguous
from 00h to 3Fh for socket A, and from 40h to 7Fh for socket B. Refer to Figure 5–1 for an ExCA I/O mapping
illustration. Table 5–1 identifies each ExCA register and its respective ExCA offset.
The TI PCI4451 also provides a memory-mapped alias of the ExCA registers by directly mapping them into PCI
memory space. They are located through the CardBus socket registers/ExCA registers base address register (PCI
register 10h) at memory offset 800h. Each socket has a separate base address programmable by function. Refer to
Figure 5–2 for an ExCA memory mapping illustration. Note that memory offsets are 800h–844h for both functions
0 and 1. This illustration also identifies the CardBus socket register mapping, which is mapped into the same 4K
window at memory offset 0h.
The interrupt registers, as defined by the 82365SL specification, in the ExCA register set control such card functions
as reset, type, interrupt routing, and interrupt enables. Special attention must be paid to the interrupt routing registers
and the host interrupt signaling method selected for the PCI4451 to ensure that all possible PCI4451 interrupts can
potentially be routed to the programmable interrupt controller. The ExCA registers that are critical to the interrupt
signaling are at memory address ExCA offsets 803h and 805h.
Access to I/O mapped 16-bit PC Cards is available to the host system via two ExCA I/O windows. These are regions
of host I/O address space into which the card I/O space is mapped. These windows are defined by start, end, and
offset addresses programmed in the ExCA registers described in this section. I/O windows have byte granularity.
Access to memory mapped 16-bit PC Cards is available to the host system via five ExCA memory windows. These
are regions of host memory space into which the card memory space is mapped. These windows are defined by start,
end, and offset addresses programmed in the ExCA registers described in this section. Memory windows have
4-Kbyte granularity.
A bit location followed by a ‡ means that this bit is not cleared by the assertion of PRST. This bit will only be cleared
by the assertion of GRST. This is necessary to retain device context when transitioning from D3 to D0.
5–1
Offset
00h
Host I/O Space
PCI4451 Configuration Registers
PC Card A
ExCA
Registers
Card Bus Socket / ExCA Base Address 10h
Index
Data
3Fh
40h
16–bit Legacy Mode Base Address
44h
PC Card B
ExCA
Registers
7Fh
Note: The 16–bit legacy mode base address
register is shared by function 0 and 1 as
indicated by the shading.
Offset of desired register is placed in the Index register and
the data from that location is returned in the data register.
Figure 5–1. ExCA Register Access Through I/O
Host
Host
Memory Space
Memory Space
PCI4451 Configuration Registers
Offset
Offset
00h
.
.
.
CardBus
Socket A
Registers
10h
44h
CardBus Socket/ExCA Base Address
20h
Offset
00h
.
.
CardBus
Socket B
Registers
800h
ExCA
Registers
Card A
16-bit Legacy-Mode Base Address
20h
.
.
844h
.
800h
ExCA
Registers
Card B
Note: The CardBus Socket/ExCA Base
Address Mode Register is separate for
functions 0 and 1.
844h
Offsets are from the CardBus socket/ExCA base
Address register’s base address
Figure 5–2. ExCA Register Access Through Memory
5–2
Table 5–1. ExCA Registers and Offsets
CARDBUS SOCKET EXCA OFFSET EXCA OFFSET
REGISTER NAME
ADDRESS OFFSET
(CARD A)
(CARD B)
Identification and revision
Interface status
800
801
802†
803†
804†
805†
806
807
808
809
80A
80B
80C
80D
80E
80F
810
811
00
40
01
41
†
Power control
02
42
†
Interrupt and general control
03
43
†
Card status change
04
44
†
Card status change interrupt configuration
05
45
Address window enable
06
46
I / O window control
07
47
I / O window 0 start-address low-byte
I / O window 0 start-address high-byte
I / O window 0 end-address low-byte
I / O window 0 end-address high-byte
I / O window 1 start-address low-byte
I / O window 1 start-address high-byte
I / O window 1 end-address low-byte
I / O window 1 end-address high-byte
Memory window 0 start-address low-byte
Memory window 0 start-address high-byte
Memory window 0 end-address low-byte
Memory window 0 end-address high-byte
08
48
09
49
0A
0B
0C
0D
0E
0F
10
4A
4B
4C
4D
4E
4F
50
11
51
812
813
814
815
816
817
818
819
81A
81B
81C
81D
81E
81F
820
821
822
823
824
825
12
52
13
53
Memory window 0 offset-address low-byte
Memory window 0 offset-address high-byte
Card detect and general control
14
54
15
55
16
56
Reserved
17
57
Memory window 1 start-address low-byte
Memory window 1 start-address high-byte
Memory window 1 end-address low-byte
Memory window 1 end-address high-byte
Memory window 1 offset-address low-byte
Memory window 1 offset-address high-byte
Global control
18
58
19
59
1A
1B
1C
1D
1E
1F
20
5A
5B
5C
5D
5E
5F
60
Reserved
Memory window 2 start-address low-byte
Memory window 2 start-address high-byte
Memory window 2 end-address low-byte
Memory window 2 end-address high-byte
Memory window 2 offset-address low-byte
Memory window 2 offset-address high-byte
21
61
22
62
23
63
24
64
25
65
†
One or more bits in this register are cleared only by the assertion of GRST when PME is enabled. If PME is NOT enabled, then this bit is cleared
by the assertion of PRST or GRST.
5–3
Table 5–1. ExCA Registers and Offsets (continued)
CARDBUS SOCKET EXCA OFFSET EXCA OFFSET
ADDRESS OFFSET
REGISTER NAME
(CARD A)
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
–
(CARD B)
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
–
Reserved
826
827
828
829
82A
82B
82C
82D
82E
82F
830
831
832
833
834
835
836
837
838
839
83A
83B
83C
83D
83E
83F
840
841
842
843
844
Reserved
Memory window 3 start-address low-byte
Memory window 3 start-address high-byte
Memory window 3 end-address low-byte
Memory window 3 end-address high-byte
Memory window 3 offset-address low-byte
Memory window 3 offset-address high-byte
Reserved
Reserved
Memory window 4 start-address low-byte
Memory window 4 start-address high-byte
Memory window 4 end-address low-byte
Memory window 4 end-address high-byte
Memory window 4 offset-address low-byte
Memory window 4 offset-address high-byte
I/O window 0 offset-address low-byte
I/O window 0 offset-address high-byte
I/O window 1 offset-address low-byte
I/O window 1 offset-address high-byte
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Memory window page register 0
Memory window page register 1
Memory window page register 2
Memory window page register 3
Memory window page register 4
–
–
–
–
–
–
–
–
5–4
5.1 ExCA Identification and Revision Register
This register provides host software with information on 16-bit PC Card support and 82365SL-DF compatibility. See
Table 5–2 for a complete description of the register contents.
NOTE: If bit 5 (SUBSYRW) in the system control register is 1, then this register is read-only.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA identification and revision
R
1
R
0
R/W
0
R/W
0
R/W
0
R/W
1
R/W
0
R/W
0
Register:
Type:
ExCA identification and revision
Read/Write, Read-only
Offset:
CardBus Socket Address + 800h:
Card A ExCA Offset 00h
Card B ExCA Offset 40h
Default:
84h
Table 5–2. ExCA Identification and Revision Register Description
BIT
7–6
5–4
3–0
SIGNAL
IFTYPE
RSVD
TYPE
FUNCTION
Interface type. These bits, which are hardwired as 10b, identify the 16-bit PC Card support provided by the
PCI4451. The PCI4451 supports both I/O and memory 16-bit PC Cards.
R
R/W
R/W
These bits can be used for 82365SL emulation.
82365SL revision. This field stores the 82365SL revision supported by the PCI4451. Host software may read
this field to determine compatibility to the 82365SL register set. This field defaults to 0100b upon reset.
365REV
5–5
5.2 ExCA Interface Status Register
This register provides information on current status of the PC Card interface. An X in the default bit values indicates
that the value of the bit after reset depends on the state of the PC Card interface. See Table 5–3 for a complete
description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA interface status
R
0
R
0
R
X
R
X
R
X
R
X
R
X
R
X
Register:
Type:
ExCA interface status
Read-only
Offset:
CardBus Socket Address + 801h:
Card A ExCA Offset 01h
Card B ExCA Offset 41h
Default:
00XX XXXXb
Table 5–3. ExCA Interface Status Register Description
BIT
SIGNAL
TYPE
FUNCTION
This bit returns 0 when read. A write has no effect.
7
RSVD
R
CARDPWR. Card power. This bit indicates the current power status of the PC Card socket. This bit reflects
how the ExCA power control register has been programmed. The bit is encoded as:
6
5
CARDPWR
READY
R
0 = V
1 = V
and V
and V
to the socket is turned off (default).
to the socket is turned on.
CC
CC
PP
PP
This bit indicates the current status of the READY signal at the PC Card interface.
R
R
0 = PC Card is not ready for a data transfer.
1 = PC Card is ready for a data transfer.
Card write protect. This bit indicates the current status of the WP signal at the PC Card interface. This signal
reports to the PCI4451 whether or not the memory card is write protected. Further, write protection for an
entire PCI4451 16-bit memory window is available by setting the appropriate bit in the ExCA memory
window offset-address high-byte register.
4
CARDWP
0 = WP signal is 0. PC Card is R/W.
1 = WP signal is 1. PC Card is read-only.
Card detect 2. This bit indicates the status of the CD2 signal at the PC Card interface. Software may use
this and CDETECT1 to determine if a PC Card is fully seated in the socket.
3
2
CDETECT2
CDETECT1
R
R
0 = CD2 signal is 1. No PC Card inserted.
1 = CD2 signal is 0. PC Card at least partially inserted.
Card detect 1. This bit indicates the status of the CD1 signal at the PC Card interface. Software may use
this and CDETECT2 to determine if a PC Card is fully seated in the socket.
0 = CD1 signal is 1. No PC Card inserted.
1 = CD1 signal is 0. PC Card at least partially inserted.
Battery voltage detect. When a 16-bit memory card is inserted, the field indicates the status of the battery
voltage detect signals (BVD1, BVD2) at the PC Card interface, where bit 0 reflects the BVD1 status, and
bit 1 reflects BVD2.
00 = Battery is dead.
01 = Battery is dead.
10 = Battery is low; warning.
11 = Battery is good.
1–0
BVDSTAT
R
When a 16-bit I/O card is inserted, this field indicates the status of the SPKR (bit 1) signal and the STSCHG
(bit 0) at the PC Card interface. In this case, the two bits in this field directly reflect the current state of these
card outputs.
5–6
5.3 ExCA Power Control Register
This register provides PC Card power control. Bit 7 of this register controls the 16-bit output enables on the socket
interface, and can be used for power management in 16-bit PC Card applications. See Table 5–4 for a complete
description of the register contents.
Bit
7
6
5
4†
3†
2
1†
0†
Name
Type
Default
ExCA power control
R/W
0
R
0
R
0
R/W
0
R/W
0
R
0
R/W
0
R/W
0
Register:
Type:
ExCA power control
Read-only, Read/Write
Offset:
CardBus Socket Address + 802h:
Card A ExCA Offset 02h
Card B ExCA Offset 42h
Default:
00h
Table 5–4. ExCA Power Control Register Description
BIT
SIGNAL
COE
TYPE
R/W
R
FUNCTION
Card output enable. This bit controls the state of all of the 16-bit outputs on the PCI4451. This bit is encoded
as:
†
7
0 = 16-bit PC Card outputs are disabled (default).
1 = 16-bit PC Card outputs are enabled.
6–5
RSVD
Reserved. These bits return 0s when read. Writes have no effect.
V
CC
. These bits are used to request changes to card V . This field is encoded as:
CC
00 = 0 V (default)
01 = 0 V Reserved
10 = 5 V
†
4–3
EXCAVCC
RSVD
R/W
R
11 = 3 V
2
This bit returns 0 when read. A write has no effect.
V
. These bits are used to request changes to card V . The PCI4451 ignores this field unless V
to
PP PP CC
the socket is enabled (i.e., 5 Vdc or 3.3 Vdc). This field is encoded as:
00 = 0 V (default)
†
1–0
EXCAVPP
R/W
01 = V
CC
10 = 12 V
11 = 0 V Reserved
†
This bit is cleared only by the assertion of GRST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST
or GRST.
5–7
5.4 ExCA Interrupt and General Control Register
This register controls interrupt routing for I/O interrupts as well as other critical 16-bit PC Card functions. See
Table 5–5 for a complete description of the register contents.
Bit
7
6†
5†
4
3
2
1
0
Name
Type
Default
ExCA interrupt and general control
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
ExCA interrupt and general control
Read/Write
Offset:
CardBus Socket Address + 803h:
Card A ExCA Offset 03h
Card B ExCA Offset 43h
Default:
00h
Table 5–5. ExCA Interrupt and General Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
Card ring indicate enable. Enables the ring indicate function of the BVD1/RI pins. This bit is encoded as:
7
RINGEN
R/W
0 = Ring indicate disabled (default)
1 = Ring indicate enabled
Card reset. This bit controls the 16-bit PC Card RESET signal, and allows host software to force a card
reset. This bit affects 16-bit cards only. This bit is encoded as:
†
6
5
RESET
R/W
R/W
0 = RESET signal asserted (default)
1 = RESET signal deasserted.
Card type. This bit indicates the PC Card type. This bit is encoded as:
†
CARDTYPE
0 = Memory PC Card is installed (default)
1 = I/O PC Card is installed
PCI interrupt – CSC routing enable bit. This bit has meaning only if the CSC interrupt routing control bit
(PCI offset 93h, bit 5) is 0b. In this case, when this bit is set (high), the card status change interrupts are
routed to PCI interrupts. When low, the card status change interrupts are routed using bits 7–4 in the ExCA
card status-change interrupt configuration register (ExCA offset 805h, see Section 5.6). This bit is encoded
as:
4
CSCROUTE
R/W
0 = CSC interrupts routed by ExCA registers (default)
1 = CSC interrupts routed to PCI interrupts
If the CSC interrupt routing control bit (PCI offset 93h, bit 5) is set to 1b, this bit has no meaning which is
the default case.
Card interrupt select for I/O PC Card functional interrupts. These bits select the interrupt routing for I/O
PC Card functional interrupts. This field is encoded as:
0000 = No ISA interrupt routing (default). CSC interrupts routed to PCI Interrupts.
0001 = IRQ1 enabled
0010 = SMI enabled
0011 = IRQ3 enabled
0100 = IRQ4 enabled
0101 = IRQ5 enabled
0110 = IRQ6 enabled
0111 = IRQ7 enabled
3–0
INTSELECT
R/W
1000 = IRQ8 enabled
1001 = IRQ9 enabled
1010 = IRQ10 enabled
1011 = IRQ11 enabled
1100 = IRQ12 enabled
1101 = IRQ13 enabled
1110 = IRQ14 enabled
1111 = IRQ15 enabled
†
This bit is cleared only by the assertion of GRST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST
or GRST.
5–8
5.5 ExCA Card Status-Change Register
This register reflects the status of PC Card CSC interrupt sources. The ExCA card status change interrupt
configuration register enables these interrupt sources to generate an interrupt to the host. When the interrupt source
is disabled, the corresponding bit in this register always reads as 0. When an interrupt source is enabled and that
particular event occurs, the corresponding bit in this register is set to indicate the interrupt source. After generating
the interrupt to the host, the interrupt service routine must read this register to determine the source of the interrupt.
The interrupt service routine is responsible for resetting the bits in this register, as well. Resetting a bit is accomplished
by one of two methods: a read of this register, or an explicit write back of 1 to the status bit. The choice of these two
methods is based on the interrupt flag clear mode select, bit 2, in the ExCA global control register. See Table 5–6
for a complete description of the register contents.
Bit
7
6
5
4
3†
2†
1†
0†
Name
Type
Default
ExCA card status-change
R
0
R
0
R
0
R
0
RC
0
RC
0
RC
0
RC
0
Register:
Type:
ExCA card status-change
Read/Clear, Read-only
Offset:
CardBus Socket Address + 804h:
Card A ExCA Offset 04h
Card B ExCA Offset 44h
Default:
00h
Table 5–6. ExCA Card Status-Change Register Description
BIT
SIGNAL
TYPE
FUNCTION
7–4
RSVD
R
Reserved. These bits return 0s when read. Writes have no effect.
Card detect change. This bit indicates whether a change on the CD1 or CD2 signals occurred at the
PC Card interface. A read of this bit or writing a 1 to this bit clears it. This bit is encoded as:
†
3
2
CDCHANGE
RC
RC
0 = No change detected on either CD1 or CD2.
1 = A change was detected on either CD1 or CD2.
Ready change. When a 16-bit memory is installed in the socket, this bit includes whether the source
of a PCI4451 interrupt was due to a change on the READY signal at the PC Card interface indicating
that PC Card is now ready to accept new data. A read of this bit or writing a 1 to this bit clears it. This
bit is encoded as:
†
READYCHANGE
0 = No low-to-high transition detected on READY (default)
1 = Detected a low-to-high transition on READY
When a 16-bit I/O card is installed, this bit is always 0.
Battery warning change. When a 16-bit memory card is installed in the socket, this bit indicates whether
the source of a PCI4451 interrupt was due to a battery low warning condition. A read of this bit or writing
a 1 to this bit clears it. This bit is encoded as:
†
1
0
BATWARN
BATDEAD
RC
RC
0 = No battery warning condition (default)
1 = Detected a battery warning condition
When a 16-bit I/O card is installed, this bit is always 0.
Battery dead or status change. When a 16-bit memory card is installed in the socket, this bit indicates
whether the source of a PCI4451 interrupt was due to a battery dead condition. A read of this bit or
writing a 1 to this bit clears it. This bit is encoded as:
†
0 = STSCHG deasserted (default)
1 = STSCHG asserted
Ring indicate. When the PCI4451 is configured for ring indicate operation this bit indicates the status
of the RI terminal.
†
This bit is cleared only by the assertion of GRST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST
or GRST.
5–9
5.6 ExCA Card Status-Change Interrupt Configuration Register
This register controls interrupt routing for CSC interrupts, as well as masks/unmasks CSC interrupt sources. See
Table 5–7 for a complete description of the register contents.
Bit
7
6
5
4
3†
2†
1†
0†
Name
Type
Default
ExCA card status-change interrupt configuration
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
ExCA card status-change interrupt configuration
Read/Write
Offset:
CardBus Socket Address + 805h:
Card A ExCA Offset 05h
Card B ExCA Offset 45h
Default:
00h
Table 5–7. ExCA Card Status-Change Interrupt Register Description
BIT
SIGNAL
TYPE
FUNCTION
Interrupt select for card status change. These bits select the interrupt routing for card status change
interrupts. This field is encoded as:
0000 = CSC interrupts routed to PCI interrupts if bit 5 of the diagnostic register (PCI offset 93h) is set
to 1b.
In this case bit 4 of ExCA 803 is a don’t care. This is the default setting.
0000 = No ISA interrupt routing if bit 5 of the diagnostic register (PCI offset 93h) is set to 0b. In this case,
CSC interrupts are routed to PCI interrupts by setting bit 4 of ExCA 803h to 1b.
0001 = IRQ1 enabled
0010 = SMI enabled
0011 = IRQ3 enabled
0100 = IRQ4 enabled
0101 = IRQ5 enabled
7–4
CSCSELECT
R/W
0110 = IRQ6 enabled
0111 = IRQ7 enabled
1000 = IRQ8 enabled
1001 = IRQ9 enabled
1010 = IRQ10 enabled
1011 = IRQ11 enabled
1100 = IRQ12 enabled
1101 = IRQ13 enabled
1110 = IRQ14 enabled
1111 = IRQ15 enabled
Card detect enable. Enables interrupts on CD1 or CD2 changes. This bit is encoded as:
†
†
3
CDEN
R/W
R/W
0 = Disables interrupts on CD1 or CD2 line changes (default)
1 = Enable interrupts on CD1 or CD2 line changes
Ready enable. This bit enables/disables a low-to-high transition on the PC Card READY signal to generate
a host interrupt. This interrupt source is considered a card status change. This bit is encoded as:
2
READYEN
0 = Disables host interrupt generation (default)
1 = Enables host interrupt generation
Battery warning enable. This bit enables/disables a battery warning condition to generate a CSC interrupt.
This bit is encoded as:
†
1
0
BATWARNEN
BATDEADEN
R/W
R/W
0 = Disables host interrupt generation (default)
1 = Enables host interrupt generation
Battery dead enable. This bit enables/disables a battery dead condition on a memory PC Card or assertion
of the STSCHG I/O PC Card signal to generate a CSC interrupt.
†
0 = Disables host interrupt generation (default)
1 = Enables host interrupt generation
†
This bit is cleared only by the assertion of GRST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST
or GRST.
5–10
5.7 ExCA Address Window Enable Register
This register enables/disables the memory and I/O windows to the 16-bit PC Card. By default, all windows to the card
are disabled. The PCI4451 will not acknowledge PCI memory or I/O cycles to the card if the corresponding enable
bit in this register is 0, regardless of the programming of the ExCA memory and I/O window start/end/offset address
registers. See Table 5–8 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA address window enable
R/W
0
R/W
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
ExCA address window enable
Read-only, Read/Write
Offset:
CardBus Socket Address + 806h:
Card A ExCA Offset 06h
Card B ExCA Offset 46h
Default:
00h
Table 5–8. ExCA Address Window Enable Register Description
BIT
SIGNAL
TYPE
FUNCTION
I/O window 1 enable. This bit enables/disables I/O window 1 for the card. This bit is encoded as:
7
IOWIN1EN
R/W
0 = I/O window 1 disabled (default)
1 = I/O window 1 enabled
I/O window 0 enable. This bit enables/disables I/O window 0 for the card. This bit is encoded as:
6
5
IOWIN0EN
RSVD
R/W
R
0 = I/O window 0 disabled (default)
1 = I/O window 0 enabled
This bit returns 0 when read. A write has no effect.
Memory window 4 enable. This bit enables/disables memory window 4 for the card. This bit is encoded
as:
4
3
2
1
0
MEMWIN4EN
MEMWIN3EN
MEMWIN2EN
MEMWIN1EN
MEMWIN0EN
R/W
R/W
R/W
R/W
R/W
0 = memory window 4 disabled (default)
1 = memory window 4 enabled
Memory window 3 enable. This bit enables/disables memory window 3 for the card. This bit is encoded
as:
0 = memory window 3 disabled (default)
1 = memory window 3 enabled
Memory window 2 enable. This bit enables/disables memory window 2 for the card. This bit is encoded
as:
0 = memory window 2 disabled (default)
1 = memory window 2 enable
Memory window 1 enable. This bit enables/disables memory window 1 for the PC Card. This bit is encoded
as:
0 = memory window 1 disabled (default)
1 = memory window 1 enabled
Memory window 0 enable. This bit enables/disables memory window 0 for the PC Card. This bit is encoded
as:
0 = memory window 0 disabled (default)
1 = memory window 0 enabled
5–11
5.8 ExCA I/O Window Control Register
This register contains parameters related to I/O window sizing and cycle timing. See Table 5–9 for a complete
description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA I/O window control
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
ExCA I/O window control
Read/Write
Offset:
CardBus Socket Address + 807h:
Card A ExCA Offset 07h
Card B ExCA Offset 47h
Default:
SIGNAL
00h
Table 5–9. ExCA I/O Window Control Register Description
BIT
TYPE
FUNCTION
I/O window 1 wait-state. This bit controls the I/O window 1 wait-state for 16-bit I/O accesses. This bit has
no effect on 8-bit accesses. This wait-state timing emulates the ISA wait-state used by the 82365SL-DF.
This bit is encoded as:
7
WAITSTATE1
R/W
R/W
0 = 16-bit cycles have standard length (default)
1 = 16-bit cycles extended by one equivalent ISA wait state
I/O window 1 zero wait-state. This bit controls the I/O window 1 wait-state for 8-bit I/O accesses. This bit
has no effect on 16-bit accesses. This wait-state timing emulates the ISA wait-state used by the
82365SL-DF.
6
ZEROWS1
0 = 8-bit cycles have standard length (default)
1 = 8-bit cycles reduced to equivalent of three ISA cycles
I/O window 1 IOIS16 source. This bit controls the I/O window automatic data sizing feature which used
the IOIS16 signal from the PC Card to determine the data width of the I/O data transfer.
5
4
IOSIS16W1
DATASIZE1
R/W
R/W
0 = Data width determined by DATASIZE1, bit 4 (default)
1 = Window data width determined by IOIS16
I/O window 1 data size. This bit controls the I/O window 1 data size. This bit is ignored if the I/O window
1 IOIS16 source bit (bit 5) is set. This bit is encoded as:
0 = Window data width is 8 bits (default)
1 = Window data width is 16 bits
I/O window 0 wait-state. This bit controls the I/O window 0 wait-state for 16-bit I/O accesses. This bit has
no effect on 8-bit accesses. This wait-state timing emulates the ISA wait-state used by the 82365SL-DF.
This bit is encoded as:
3
2
WAITSTATE0
ZEROWS0
R/W
R/W
0 = 16-bit cycles have standard length (default)
1 = 16-bit cycles extended by one equivalent ISA wait state
I/O window 0 zero wait-state. This bit controls the I/O window 0 wait-state for 8-bit I/O accesses. This bit
has no effect on 16-bit accesses. This wait-state timing emulates the ISA wait-state used by the
82365SL-DF.
0 = 8-bit cycles have standard length (default)
1 = 8-bit cycles reduced to equivalent of three ISA cycles
I/O window 0 IOIS16 source. This bit controls the I/O window automatic data sizing feature which used
the IOIS16 signal from the PC Card to determine the data width of the I/O data transfer.
1
0
IOIS16W0
R/W
R/W
0 = Data width determined by DATASIZE0, bit 0 (default)
1 = Window data width determined by IOIS16
I/O window 0 data size. This bit controls the I/O window 1 data size. This bit is ignored if the I/O window
1 IOIS16 source bit (bit 1) is set. This bit is encoded as:
DATASIZE0
0 = Window data width is 8 bits (default)
1 = Window data width is 16 bits
5–12
5.9 ExCA I/O Windows 0 and 1 Start-Address Low-Byte Registers
These registers contain the low byte of the 16-bit I/O window start address for I/O windows 0 and 1. The eight bits
of these registers correspond to the lower eight bits of the start address.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA I/O windows 0 and 1 start-address low-byte
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
ExCA I/O window 0 start-address low-byte
CardBus Socket Address + 808h:
Card A ExCA Offset 08h
Card B ExCA Offset 48h
Register:
Offset:
ExCA I/O window 1 start-address low-byte
CardBus Socket Address + 80Ch:
Card A ExCA Offset 0Ch
Card B ExCA Offset 4Ch
Type:
Default:
Size:
Read/Write
00h
One byte
5.10 ExCA I/O Windows 0 and 1 Start-Address High-Byte Registers
These registers contain the high byte of the 16-bit I/O window start address for I/O windows 0 and 1. The eight bits
of these registers correspond to the upper eight bits of the start address.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA I/O windows 0 and 1 start-address high-byte
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
ExCA I/O window 0 start-address high-byte
CardBus Socket Address + 809h:
Card A ExCA Offset 09h
Card B ExCA Offset 49h
Register:
Offset:
ExCA I/O window 1 start-address high-byte
CardBus Socket Address + 80Dh:
Card A ExCA Offset 0Dh
Card B ExCA Offset 4Dh
Type:
Default:
Size:
Read/Write
00h
One byte
5–13
5.11 ExCA I/O Windows 0 and 1 End-Address Low-Byte Registers
These registers contain the low byte of the 16-bit I/O window end address for I/O windows 0 and 1. The eight bits
of these registers correspond to the lower eight bits of the start address.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA I/O windows 0 and 1 end-address low-byte
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
ExCA I/O window 0 end-address low-byte
CardBus Socket Address + 80Ah:
Card A ExCA Offset 0Ah
Card B ExCA Offset 4Ah
Register:
Offset:
ExCA I/O window 1 end-address low-byte
CardBus Socket Address + 80Eh:
Card A ExCA Offset 0Eh
Card B ExCA Offset 4Eh
Type:
Default:
Size:
Read/Write
00h
One byte
5.12 ExCA I/O Windows 0 and 1 End-Address High-Byte Registers
These registers contain the high byte of the 16-bit I/O window end address for I/O windows 0 and 1. The eight bits
of these registers correspond to the upper eight bits of the end address.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA I/O windows 0 and 1 end-address high-byte
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
ExCA I/O window 0 end-address high-byte
CardBus Socket Address + 80Bh:
Card A ExCA Offset 0Bh
Card B ExCA Offset 4Bh
Register:
Offset:
ExCA I/O window 1 end-address high-byte
CardBus Socket Address + 80Fh:
Card A ExCA Offset 0Fh
Card B ExCA Offset 4Fh
Type:
Default:
Size:
Read/Write
00h
One byte
5–14
5.13 ExCA Memory Windows 0–4 Start-Address Low-Byte Registers
These registers contain the low byte of the 16-bit memory window start address for memory windows 0, 1, 2, 3, and 4.
The eight bits of these registers correspond to bits A19–A12 of the start address.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA memory windows 0–4 start-address low-byte
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
ExCA memory window 0 start-address low-byte
CardBus Socket Address + 810h:
Card A ExCA Offset 10h
Card B ExCA Offset 50h
Register:
Offset:
ExCA memory window 1 start-address low-byte
CardBus Socket Address + 818h: Card A ExCA Offset 18h
Card B ExCA Offset 58h
ExCA memory window 2 start-address low-byte
CardBus Socket Address + 820h: Card A ExCA Offset 20h
Card B ExCA Offset 60h
ExCA memory window 3 start-address low-byte
CardBus Socket Address + 828h: Card A ExCA Offset 28h
Card B ExCA Offset 68h
ExCA memory window 4 start-address low-byte
Register:
Offset:
Register:
Offset:
Register:
Offset:
CardBus Socket Address + 830h:
Card A ExCA Offset 30h
Card B ExCA Offset 70h
Type:
Default:
Size:
Read/Write
00h
One byte
5–15
5.14 ExCA Memory Windows 0–4 Start-Address High-Byte Registers
These registers contain the high nibble of the 16-bit memory window start address for memory windows 0, 1, 2, 3,
and 4. The lower four bits of these registers correspond to bits A23–A20 of the start address. In addition, the memory
window data width and wait states are set in this register. See Table 5–10 for a complete description of the register
contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA memory windows 0–4 start-address high-byte
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
ExCA memory window 0 start-address high-byte
CardBus Socket Address + 811h:
Card A ExCA Offset 11h
Card B ExCA Offset 51h
Register:
Offset:
ExCA memory window 1 start-address high-byte
CardBus Socket Address + 819h: Card A ExCA Offset 19h
Card B ExCA Offset 59h
ExCA memory window 2 start-address high-byte
CardBus Socket Address + 821h: Card A ExCA Offset 21h
Card B ExCA Offset 61h
ExCA memory window 3 start-address high-byte
CardBus Socket Address + 829h: Card A ExCA Offset 29h
Card B ExCA Offset 69h
ExCA memory window 4 start-address high-byte
Register:
Offset:
Register:
Offset:
Register:
Offset:
CardBus Socket Address + 831h:
Card A ExCA Offset 31h
Card B ExCA Offset 71h
Type:
Default:
Size:
Read/Write
00h
One byte
Table 5–10. ExCA Memory Windows 0–4 Start-Address High-Byte Registers Description
BIT
TYPE
FUNCTION
DATASIZE. This bit controls the memory window data width. This bit is encoded as:
7
R/W
0 = Window data width is 8 bits (default)
1 = Window data width is 16 bits
ZEROWAIT. Zero wait-state. This bit controls the memory window wait state for 8- and 16-bit accesses. This wait-state
timing emulates the ISA wait state used by the 82365SL-DF. This bit is encoded as:
6
R/W
0 = 8- and 16-bit cycles have standard length (default).
1 = 8-bit cycles reduced to equivalent of three ISA cycles
16-bit cycles reduced to the equivalent of two ISA cycles.
5–4
3–0
R/W
R/W
SCRATCH. Scratch pad bits. These bits have no effect on memory window operation.
STAHN. Start address high-nibble. These bits represent the upper address bits A23–A20 of the memory window start
address.
5–16
5.15 ExCA Memory Windows 0–4 End-Address Low-Byte Registers
These registers contain the low byte of the 16-bit memory window end address for memory windows 0, 1, 2, 3, and 4.
The eight bits of these registers correspond to bits A19–A12 of the end address.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA memory windows 0–4 end-address low-byte
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
ExCA memory window 0 end-address low-byte
CardBus Socket Address + 812h:
Card A ExCA Offset 12h
Card B ExCA Offset 52h
Register:
Offset:
ExCA memory window 1 end-address low-byte
CardBus Socket Address + 81Ah: Card A ExCA Offset 1Ah
Card B ExCA Offset 5Ah
ExCA memory window 2 end-address low-byte
CardBus Socket Address + 822h: Card A ExCA Offset 22h
Card B ExCA Offset 62h
ExCA memory window 3 end-address low-byte
CardBus Socket Address + 82Ah: Card A ExCA Offset 2Ah
Card B ExCA Offset 68h
ExCA memory window 4 end-address low-byte
Register:
Offset:
Register:
Offset:
Register:
Offset:
CardBus Socket Address + 832h:
Card A ExCA Offset 32h
Card B ExCA Offset 72h
Type:
Default:
Size:
Read/Write
00h
One byte
5–17
5.16 ExCA Memory Windows 0–4 End-Address High-Byte Registers
These registers contain the high nibble of the 16-bit memory window end address for memory windows 0, 1, 2, 3,
and 4. The lower 4 bits of these registers correspond to bits A23–A20 of the end address. In addition, the memory
window wait states are set in this register. See Table 5–11 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA memory windows 0–4 end-address high-byte
R/W
0
R/W
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
ExCA memory window 0 end-address high-byte
CardBus Socket Address + 813h:
Card A ExCA Offset 13h
Card B ExCA Offset 53h
Register:
Offset:
ExCA memory window 1 end-address high-byte
CardBus Socket Address + 81Bh: Card A ExCA Offset 1Bh
Card B ExCA Offset 5Bh
ExCA memory window 2 end-address high-byte
CardBus Socket Address + 823h: Card A ExCA Offset 23h
Card B ExCA Offset 63h
ExCA memory window 3 end-address high-byte
CardBus Socket Address + 82Bh: Card A ExCA Offset 2Bh
Card B ExCA Offset 6Bh
ExCA Memory window 4 end-address high-byte
Register:
Offset:
Register:
Offset:
Register:
Offset:
CardBus Socket Address + 833h:
Card A ExCA Offset 33h
Card B ExCA Offset 73h
Type:
Read/Write, Read-only
Default:
Size:
00h
One byte
Table 5–11. ExCA Memory Windows 0–4 End-Address High-Byte Registers Description
BIT
7–6
5–4
3–0
TYPE
R/W
R
FUNCTION
MEMWS. Wait state. These bits specify the number of equivalent ISA wait states to be added to 16-bit memory accesses.
The number of wait states added is equal to the binary value of these two bits.
Reserved. These bits return 0s when read. Writes have no effect.
ENDHN. End-address high nibble. These bits represent the upper address bits A23–A20 of the memory window and
R/W
address.
5–18
5.17 ExCA Memory Windows 0–4 Offset-Address Low-Byte Registers
These registers contain the low byte of the 16-bit memory window offset address for memory windows 0, 1, 2, 3,
and 4. The eight bits of these registers correspond to bits A19–A12 of the offset address.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA memory windows 0–4 offset-address low-byte
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
ExCA memory window 0 offset-address low-byte
CardBus Socket Address + 814h:
Card A ExCA Offset 14h
Card B ExCA Offset 54h
Register:
Offset:
ExCA memory window 1 offset-address low-byte
CardBus Socket Address + 81Ch: Card A ExCA Offset 1Ch
Card B ExCA Offset 5Ch
ExCA memory window 2 offset-address low-byte
CardBus Socket Address + 824h: Card A ExCA Offset 24h
Card B ExCA Offset 64h
ExCA memory window 3 offset-address low-byte
CardBus Socket Address + 82Ch: Card A ExCA Offset 2Ch
Card B ExCA Offset 6Ch
ExCA memory window 4 offset-address low-byte
Register:
Offset:
Register:
Offset:
Register:
Offset:
CardBus Socket Address + 834h:
Card A ExCA Offset 34h
Card B ExCA Offset 74h
Type:
Default:
Size:
Read/Write
00h
One byte
5–19
5.18 ExCA Memory Windows 0–4 Offset-Address High-Byte Registers
These registers contain the high six bits of the 16-bit memory window offset address for memory windows 0, 1, 2,
3, and 4. The lower six bits of these registers correspond to bits A25–A20 of the offset address. In addition, the write
protection and common/attribute memory configurations are set in this register. See Table 5–12 for a complete
description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA memory window 0–4 offset-address high-byte
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
ExCA memory window 0 offset-address high-byte
CardBus Socket Address + 815h:
Card A ExCA Offset 15h
Card B ExCA Offset 55h
Register:
Offset:
ExCA memory window 1 offset-address high-byte
CardBus Socket Address + 81Dh: Card A ExCA Offset 1Dh
Card B ExCA Offset 5Dh
ExCA memory window 2 offset-address high-byte
CardBus Socket Address + 825h: Card A ExCA Offset 25h
Card B ExCA Offset 65h
ExCA memory window 3 offset-address high-byte
CardBus Socket Address + 82Dh: Card A ExCA Offset 2Dh
Card B ExCA Offset 6Dh
ExCA memory window 4 offset-address high-byte
Register:
Offset:
Register:
Offset:
Register:
Offset:
CardBus Socket Address + 835h:
Card A ExCA Offset 35h
Card B ExCA Offset 75h
Type:
Default:
Size:
Read/Write
00h
One byte
Table 5–12. ExCA Memory Windows 0–4 Offset-Address High-Byte Registers Description
BIT
TYPE
FUNCTION
WINWP. Write protect. This bit specifies whether write operations to this memory window are enabled.
This bit is encoded as:
7
R/W
0 = Write operations are allowed (default).
1 = Write operations are not allowed.
REG. This bit specifies whether this memory window is mapped to card attribute or common memory.
This bit is encoded as:
6
R/W
R/W
0 = Memory window is mapped to common memory (default).
1 = Memory window is mapped to attribute memory.
OFFHB. Offset-address high byte. These bits represent the upper address bits A25–A20 of the memory window offset
address.
5–0
5–20
5.19 ExCA I/O Windows 0 and 1 Offset-Address Low-Byte Registers
These registers contain the low byte of the 16-bit I/O window offset address for I/O windows 0 and 1. The eight bits
of these registers correspond to the lower eight bits of the offset address, and bit 0 is always 0.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA I/O windows 0 and 1 offset-address low-byte
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
ExCA I/O window 0 offset-address low-byte
CardBus Socket Address + 836h:
Card A ExCA Offset 36h
Card B ExCA Offset 76h
Register:
Offset:
ExCA I/O window 1 offset-address low-byte
CardBus Socket Address + 838h:
Card A ExCA Offset 38h
Card B ExCA Offset 78h
Type:
Default:
Size:
Read/Write
00h
One byte
5.20 ExCA I/O Windows 0 and 1 Offset-Address High-Byte Registers
These registers contain the high byte of the 16-bit I/O window offset address for I/O windows 0 and 1. The eight bits
of these registers correspond to the upper eight bits of the offset address.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA I/O windows 0 and 1 offset-address high-byte
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Offset:
ExCA I/O window 0 offset-address high-byte
CardBus Socket Address + 837h:
Card A ExCA Offset 37h
Card B ExCA Offset 77h
Register:
Offset:
ExCA I/O window 1 offset-address high-byte
CardBus Socket Address + 839h:
Card A ExCA Offset 39h
Card B ExCA Offset 79h
Type:
Default:
Size:
Read/Write
00h
One byte
5–21
5.21 ExCA Card Detect and General Control Register
This register controls how the ExCA registers for the socket respond to card removal. It also reports the status of the
VS1 and VS2 signals at the PC Card interface. Table 5–13 describes each bit in the ExCA card detect and general
control register.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA card detect and general control
R
X
R
X
W
0
R/W
0
R
0
R
0
R/W
0
R
0
Register:
Type:
Offset:
ExCA card detect and general control
Read-only, Write-only, Read/Write
CardBus Socket Address + 816h:
Card A ExCA Offset 16h
Card B ExCA Offset 56h
Default:
XX00 0000b
Table 5–13. ExCA Card Detect and General Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
VS2. This bit reports the current state of the VS2 signal at the PC Card interface, and, therefore, does not
have a default value.
7
VS2STAT
R
0 = VS2 is low
1 = VS2 is high
VS1. This bit reports the current state of the VS1 signal at the PC Card interface, and, therefore, does not
have a default value.
6
5
VS1STAT
SWCSC
R
0 = VS1 is low
1 = VS1 is high
Software card detect interrupt. If card detect enable, bit 3 in the ExCA card status change interrupt
configuration register (ExCA offset 805h, see Section is 5.6) set, then writing a 1 to this bit causes a
card-detect card-status-change interrupt for the associated card socket.
If the card-detect enable bit is cleared to 0 in the ExCA card status-change interrupt configuration register
(ExCA offset 805h, see Section 5.6), then writing a 1 to the software card-detect interrupt bit has no effect.
This bit is write-only.
W
A read operation of this bit always returns 0. Writing a 1 to this bit also clears it. If bit 2 of the ExCA global
control register (ExCA offset 81Eh, see Section 5.22) is set and a 1 is written to clear bit 3 of the ExCA
card status change interrupt register, then this bit also gets cleared.
Card detect resume enable. If this bit is set to 1 and a card detect change has been detected on the CD1
and CD2 inputs, then the RI_OUT output will go from high to low. The RI_OUT remains low until the card
status change bit in the ExCA card status-change register (ExCA offset 804h, see Section 5.5) is cleared.
If this bit is a 0, then the card detect resume functionality is disabled.
4
CDRESUME
R/W
0 = Card detect resume disabled (default)
1 = Card detect resume enabled
3–2
1
RSVD
REGCONFIG
RSVD
R
R/W
R
These bits return 0s when read. Writes have no effect.
Register configuration upon card removal. This bit controls how the ExCA registers for the socket react
to a card removal event. This bit is encoded as:
0 = No change to ExCA registers upon card removal (default)
1 = Reset ExCA registers upon card removal
0
This bit returns 0 when read. A write has no effect.
5–22
5.22 ExCA Global Control Register
This register controls both PC Card sockets, and is not duplicated for each socket. The host interrupt mode bits in
this register are retained for 82365SL compatibility. See Table 5–14 for a complete description of the register
contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA global control
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
ExCA global control
Read-only, Read/Write
Offset:
CardBus Socket Address + 81Eh:
Card A ExCA Offset 1Eh
Card B ExCA Offset 5Eh
Default:
00h
Table 5–14. ExCA Global Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
These bits return 0s when read. Writes have no effect.
7–5
RSVD
R
Level/edge interrupt mode select – card B. This bit selects the signaling mode for the PCI4451 host
interrupt for card B interrupts. This bit is encoded as:
4
3
2
1
INTMODEB
INTMODEA
IFCMODE
CSCMODE
R/W
0 = Host interrupt is edge mode (default).
1 = Host interrupt is level mode.
Level/edge interrupt mode select – card A. This bit selects the signaling mode for the PCI4451 host
interrupt for card A interrupts. This bit is encoded as:
R/W
R/W
R/W
0 = Host interrupt is edge mode (default).
1 = Host interrupt is level mode.
Interrupt flag clear mode select. This bit selects the interrupt flag clear mechanism for the flags in the ExCA
card status change register. This bit is encoded as:
0 = Interrupt flags cleared by read of CSC register (default)
1 = Interrupt flags cleared by explicit writeback of 1
Card status change level/edge mode select. This bit selects the signaling mode for the PCI4451 host
interrupt for card status changes. This bit is encoded as:
0 = Host interrupt is edge mode (default).
1 = Host interrupt is level mode.
PWRDWN mode select. When the bit is set to 1, the PCI4451 is in power-down mode. In power-down
mode the PCI4451 card outputs are placed in a high-impedance state until an active cycle is executed on
the card interface. Following an active cycle the outputs are again placed in a high-impedance state. The
PCI4451 still receives DMA requests, functional interrupts and/or card status change interrupts; however,
an actual card access is required to wake up the interface. This bit is encoded as:
0
PWRDWN
R/W
0 = Power-down mode disabled (default)
1 = Power-down mode enabled
5–23
5.23 ExCA Memory Windows 0–4 Page Registers
The upper eight bits of a 4-byte PCI memory address are compared to the contents of this register when decoding
addresses for 16-bit memory windows. Each window has its own page register, all of which default to 00h. By
programming this register to a nonzero value, host software may locate 16-bit memory windows in any one of 256
16-Mbyte regions in the 4-gigabyte PCI address space. These registers are only accessible when the ExCA registers
are memory-mapped, that is, these registers may not be accessed using the index/data I/O scheme.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
ExCA memory windows 0–4 page
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
ExCA memory windows 0–4 page
Read/Write
Offset:
Default:
CardBus Socket Address + 840h, 841h, 842h, 843h, 844h
00h
5–24
6 CardBus Socket Registers (Functions 0 and 1)
The PCMCIA CardBus Bridge Specification requires a CardBus socket controller to provide five 32-bit registers which
report and control the socket-specific functions. The PCI4451 provides the CardBus socket/ExCA base address
register (PCI offset 10h) to locate these CardBus socket registers in PCI memory address space. Each socket has
a separate base address register for accessing the CardBus socket registers, see Figure 6–1 below. Table 6–1
illustrates the location of the socket registers in relation to the CardBus socket/ExCA base address.
Table 6–1. CardBus Socket Registers
REGISTER NAME
OFFSET
00h
†
Socket event
Socket mask
†
04h
†
Socket present state
08h
Socket force event
0Ch
10h
†
Socket control
Reserved
14h
Reserved
18h
Reserved
1Ch
20h
Socket power management
†
One or more bits in this register are cleared only by the assertion of GRST when PME is enabled. If PME is not enabled, then this bit is cleared
by the assertion of PRST or GRST.
Host
Host
Memory Space
Memory Space
PCI4451 Configuration Registers
Offset
00h
.
.
CardBus
Socket A
Registers
.
10h
44h
CardBus Socket/ExCA Base Address
20h
Offset
00h
.
.
CardBus
Socket B
Registers
800h
ExCA
Registers
Card A
16-bit Legacy-Mode Base Address
20h
.
.
844h
800h
.
ExCA
Registers
Card B
Note: The CardBus Socket/ExCA Base
Address Mode Register is separate for
functions 0 and 1.
844h
Figure 6–1. Accessing CardBus Socket Registers Through PCI Memory
6–1
6.1 Socket Event Register
This register indicates a change in socket status has occurred. These bits do not indicate what the change is, only
that one has occurred. Software must read the socket present state register for current status. Each bit in this register
can be cleared by writing a 1 to that bit. The bits in this register can be set to a 1 by software through writing a 1 to
the corresponding bit in the socket force event register. All bits in this register are cleared by PCI reset. They may
be immediately set again, if, when coming out of PC Card reset, the bridge finds the status unchanged (i.e.,
CSTSCHG reasserted or card detect is still true). Software needs to clear this register before enabling interrupts. If
it is not cleared and interrupts are enabled, then an interrupt is generated based on any bit set and not masked. See
Table 6–2 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Socket event
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
R
0
R
0
R
0
15
14
13
12
11
10
3†
2†
1†
0†
Name
Type
Default
Socket event
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/WC R/WC R/WC R/WC
0
0
0
0
Register:
Type:
Offset:
Default:
Socket event
Read-only, Read/Write to Clear
CardBus Socket Address + 00h
0000 0000h
Table 6–2. Socket Event Register Description
FUNCTION
BIT
SIGNAL
TYPE
31–4
RSVD
R
These bits return 0s when read.
Power cycle. This bit is set when the PCI4451 detects that the PWRCYCLE bit in the socket present state
register (offset 08h, see Section 6.3) has changed. This bit is cleared by writing a 1.
†
3
†
2
†
1
PWREVENT
CD2EVENT
CD1EVENT
R/WC
R/WC
R/WC
CCD2. This bit is set when the PCI4451 detects that the CDETECT2 field in the socket present state
register (offset 08h, see Section 6.3) has changed. This bit is cleared by writing a 1.
CCD1. This bit is set when the PCI4451 detects that the CDETECT1 field in the socket present state
register (offset 08h, see Section 6.3) has changed. This bit is cleared by writing a 1.
CSTSCHG. This bit is set when the CARDSTS field in the socket present state register (offset 08h, see
Section 6.3) has changed state. For CardBus cards, this bit is set on the rising edge of the CSTSCHG
signal. For 16-bit PC Cards, this bit is set on both transitions of the CSTSCHG signal. This bit is reset by
writing a 1.
†
0
CSTSEVENT
R/WC
†
This bit is cleared only by the assertion of GRST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST
or GRST.
6–2
6.2 Socket Mask Register
This register allows software to control the CardBus card events which generate a status change interrupt. Table 6–3
below describes each bit in this register. The state of these mask bits does not prevent the corresponding bits from
reacting in the socket event register.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Socket mask
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
R
0
R
0
R
0
15
14
13
12
11
10
3†
2†
1†
0†
Name
Type
Default
Socket mask
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Socket mask
Read-only, Read/Write
Offset:
Default:
CardBus Socket Address + 04h
0000 0000h
Table 6–3. Socket Mask Register Description
FUNCTION
BIT
SIGNAL
TYPE
31–4
RSVD
R
These bits return 0s when read.
Power cycle. This bit masks the PWRCYCLE bit in the socket present state register (offset 08h, see
Section 6.3) from causing a status change interrupt.
†
3
PWRMASK
CDMASK
R/W
R/W
R/W
0 = PWRCYCLE event will not cause a CSC interrupt (default).
1 = PWRCYCLE event will cause a CSC interrupt.
Card detect mask. These bits mask the CDETECT1 and CDETECT2 bits in the socket present state
register (offset 08h, see Section 6.3) from causing a CSC interrupt.
00 = Insertion/removal will not cause CSC interrupt (default).
01 = Reserved (undefined)
10 = Reserved (undefined)
†
2–1
11 = Insertion/removal will cause CSC interrupt.
CSTSCHG mask. This bit masks the CARDSTS field in the socket present state register (offset 08h, see
Section 6.3) from causing a CSC interrupt.
†
0
CSTSMASK
0 = CARDSTS event will not cause CSC interrupt (default).
1 = CARDSTS event will cause CSC interrupt.
†
This bit is cleared only by the assertion of GRST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST
or GRST.
6–3
6.3 Socket Present State Register
This register reports information about the socket interface. Writes to the socket force event register (offset 0Ch, see
Section 6.4) are reflected here as well as general socket interface status. Information about PC Card V
support
CC
and card type is only updated at each insertion. Also note that the PCI4451 uses the CCD1 and CCD2 signals during
card identification, and changes on these signals during this operation are not reflected in this register.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Socket present state
R
0
R
0
R
1
R
1
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Socket present state
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
X
R
0
R
0
R
0
R
X
R
X
R
X
Register:
Type:
Socket present state
Read-only
Offset:
Default:
CardBus Socket Address + 08h
3000 00XXh
Table 6–4. Socket Present State Register Description
BIT
SIGNAL
TYPE
FUNCTION
YV socket. This bit indicates whether or not the socket can supply V
PCI4451 does not support Y.YV V ; therefore, this bit is always reset unless overridden by the socket
CC
force event register (offset 0Ch, see Section 6.4). This bit defaults to 0.
= Y.YV to PC Cards. The
CC
31
YVSOCKET
R
R
R
XV socket. This bit indicates whether or not the socket can supply V
PCI4451 does not support X.XV V ; therefore, this bit is always reset unless overridden by the socket
CC
force event register (offset 0Ch, see Section 6.4). This bit defaults to 0.
= X.XV to PC Cards. The
CC
30
29
XVSOCKET
3VSOCKET
3-V socket. This bit indicates whether or not the socket can supply V
PCI4451 does support 3.3 V V ; therefore, this bit is always set unless overridden by the socket force
CC
event register (offset 0Ch, see Section 6.4).
= 3.3 Vdc to PC Cards. The
CC
5-V socket. This bit indicates whether or not the socket can supply V
PCI4451 does support 5.0 V V ; therefore, this bit is always set unless overridden by bit 6 0f the
CC
device control register (PCI offset 92h, see Section 4.39).
= 5.0 Vdc to PC Cards. The
CC
28
27–14
13
5VSOCKET
RSVD
R
R
R
These bits return 0s when read.
YV card. This bit indicates whether or not the PC Card inserted in the socket supports V
CC
This bit can be set by writing to the corresponding bit in the socket force event register (offset 0Ch, see
Section 6.4).
= Y.Y Vdc.
YVCARD
XV card. This bit indicates whether or not the PC Card inserted in the socket supports V
CC
= X.X Vdc.
12
11
10
XVCARD
3VCARD
5VCARD
R
R
R
This bit can be set by writing to the corresponding bit in the socket force event register (offset 0Ch, see
Section 6.4).
3-V card. This bit indicates whether or not the PC Card inserted in the socket supports V
CC
This bit can be set by writing to the corresponding bit in the socket force event register (offset 0Ch, see
Section 6.4).
= 3.3 Vdc.
5-V card. This bit indicates whether or not the PC Card inserted in the socket supports V
CC
This bit can be set by writing to the corresponding bit in the socket force event register (offset 0Ch, see
Section 6.4).
= 5.0 Vdc.
Bad V
CC
request. This bit indicates that the host software has requested that the socket be powered
at an invalid voltage.
9
BADVCCREQ
R
0 = Normal operation (default)
1 = Invalid V
request by host software
CC
6–4
Table 6–4. Socket Present State Register Description (continued)
BIT
SIGNAL
TYPE
FUNCTION
Data lost. This bit indicates that a PC Card removal event may have caused lost data because the cycle
did not terminate properly or because write data still resides in the PCI4451.
8
DATALOST
R
0 = Normal operation (default)
1 = Potential data loss due to card removal
Not a card. This bit indicates that an unrecognizable PC Card has been inserted in the socket. This bit is
not updated until a valid PC Card is inserted into the socket.
7
6
NOTACARD
IREQCINT
R
R
0 = Normal operation (default)
1 = Unrecognizable PC Card detected
READY(IREQ)//CINT. This bit indicates the current status of the READY(IREQ)//CINT signal at the PC
Card interface.
0 = READY(IREQ)//CINT is low.
1 = READY(IREQ)//CINT is high.
CardBus card detected. This bit indicates that a CardBus PC Card is inserted in the socket. This bit is not
updated until another card interrogation sequence occurs (card insertion).
5
4
CBCARD
R
R
16-bit card detected. This bit indicates that a 16-bit PC Card is inserted in the socket. This bit is not
updated until another card interrogation sequence occurs (card insertion).
16BITCARD
Power cycle. This bit indicates the status of each card powering request. This bit is encoded as:
3
2
PWRCYCLE
CDETECT2
R
R
0 = Socket is powered down (default).
1 = Socket is powered up.
CCD2. This bit reflects the current status of the CCD2 signal at the PC Card interface. Changes to this
signal during card interrogation are not reflected here.
0 = CCD2 is low (PC Card may be present)
1 = CCD2 is high (PC Card not present)
CCD1. This bit reflects the current status of the CCD1 signal at the PC Card interface. Changes to this
signal during card interrogation are not reflected here.
1
0
CDETECT1
CARDSTS
R
R
0 = CCD1 is low (PC Card may be present).
1 = CCD1 is high (PC Card not present).
CSTSCHG. This bit reflects the current status of the CSTSCHG signal at the PC Card interface.
0 = CSTSCHG is low.
1 = CSTSCHG is high.
6.4 Socket Force Event Register
This register is used to force changes to the socket event register and the socket present state register (offset 08h,
see Section 6.3). The CVSTEST bit in this register must be written when forcing changes that require card
interrogation. See Table 6–5 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Socket force event
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Socket force event
R
X
W
X
W
X
W
X
W
X
W
X
W
X
W
X
W
X
R
X
W
X
W
X
W
X
W
X
W
X
W
X
Register:
Type:
Socket force event
Read-only, Write-only
Offset:
Default:
CardBus Socket Address + 0Ch
0000 XXXXh
6–5
Table 6–5. Socket Force Event Register Description
BIT
SIGNAL
TYPE
FUNCTION
31–15
RSVD
R
These bits return 0s when read.
Card VS test. When this bit is set, the PCI4451 reinterrogates the PC Card, updates the socket present
state register (offset 08h, see Section 6.3), and re-enables the socket power control.
14
13
12
11
10
9
CVSTEST
FYVCARD
W
Force YV card. Writes to this bit cause the YVCARD bit in the socket present state register (offset 08h,
see Section 6.3) to be written. When set, this bit disables the socket power control.
W
W
W
W
W
W
Force XV card. Writes to this bit cause the XVCARD bit in the socket present state register (offset 08h,
see Section 6.3) to be written. When set, this bit disables the socket power control.
FXVCARD
Force 3-V card. Writes to this bit cause the 3VCARD bit in the socket present state register (offset 08h,
see Section 6.3) to be written. When set, this bit disables the socket power control.
F3VCARD
Force 5-V card. Writes to this bit cause the 5VCARD bit in the socket present state register (offset 08h,
see Section 6.3) to be written. When set, this bit disables the socket power control.
F5VCARD
Force BadVccReq. Changes to the BADVCCREQ bit in the socket present state register (offset 08h,
see Section 6.3) can be made by writing this bit.
FBADVCCREQ
FDATALOST
Force data lost. Writes to this bit cause the DATALOST bit in the socket present state register
(offset 08h, see Section 6.3) to be written.
8
Force not a card. Writes to this bit cause the NOTACARD bit in the socket present state register (offset
08h, see Section 6.3) to be written.
7
6
5
FNOTACARD
RSVD
W
R
This bit returns 0 when read.
Force CardBus card. Writes to this bit cause the CBCARD bit in the socket present state register (offset
08h, see Section 6.3) to be written.
FCBCARD
W
Force 16-bit card. Writes to this bit cause the 16BITCARD bit in the socket present state register (offset
08h, see Section 6.3) to be written.
4
3
F16BITCARD
FPWRCYCLE
W
W
Force power cycle. Writes to this bit cause the PWREVENT bit in the socket event register (offset 00h,
see Section 6.1) to be written, and the PWRCYCLE bit in the socket present state register (offset 08h,
see Section 6.3) is unaffected.
Force CCD2. Writes to this bit cause the CD2EVENT bit in the socket event register (offset 00h, see
Section 6.1) to be written, and the CDETECT2 bit in the socket present state register (offset 08h, see
Section 6.3) is unaffected.
2
1
0
FCDETECT2
FCDETECT1
FCARDSTS
W
W
W
Force CCD1. Writes to this bit cause the CD1EVENT bit in the socket event register (offset 00h, see
Section 6.1) to be written, and the CDETECT1 bit in the socket present state register (offset 08h, see
Section 6.3) is unaffected.
Force CSTSCHG. Writes to this bit cause the CSTSEVENT bit in the socket event register (offset 00h,
see Section 6.1) to be written. The CARDSTS bit in the socket present state register (offset 08h, see
Section 6.3) is unaffected.
6–6
6.5 Socket Control Register
This register provides control of the voltages applied to the socket’s V and V . The PCI4451 ensures that the
PP
CC
socket is powered up only at acceptable voltages when a CardBus card is inserted. See Table 6–6 for a complete
description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Socket control
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
R
0
R
0
R
0
3
R
0
R
0
R
0
15
14
13
12
11
10
6†
5†
4†
2†
1†
0†
Name
Type
Default
Socket control
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Socket control
Read-only, Read/Write
Offset:
Default:
CardBus Socket Address + 10h
0000 0000h
Table 6–6. Socket Control Register Description
FUNCTION
BIT
SIGNAL
TYPE
31–8
RSVD
R
These bits return 0s when read.
This bit controls how the CardBus clock run state machine decides when to stop the CardBus clock to the
CardBus card:
0 = The PCI4451 clock run master will try to stop the clock to the CardBus card under the following two
conditions:
The CardBus interface is idle for 8 clocks and
There is a request from the PCI master to stop the PCI clock.
7
STOPCLK
R/W
1 = The PCI4451 clock run master will try to stop the clock to the CardBus card under the following
condition:
The CardBus interface is idle for 8 clocks.
In summary, if this bit is set to1, then the CardBus controller will try to stop the clock to the CardBus card
independent of the PCI clock run signal. The only condition that has to be satisfied in this case is the
CardBus interface sampled idle for 8 clocks.
V
CC
control. These bits are used to request card V changes.
CC
000 = Request power off (default)
001 = Reserved
010 = Request V
= 5.0 V
= 3.3 V
= X.X V
= Y.Y V
CC
CC
CC
CC
†
6–4
VCCCTRL
RSVD
R/W
011 = Request V
100 = Request V
101 = Request V
110 = Reserved
111 = Reserved
3
R
This bit returns 0 when read.
control. These bits are used to request card V
V
changes.
PP
PP
000 = Request power off (default)
001 = Request V
010 = Request V
011 = Request V
= 12.0 V
= 5.0 V
= 3.3 V
= X.X V
= Y.Y V
PP
PP
PP
†
2–0
VPPCTRL
R/W
100 = Request V
101 = Request V
110 = Reserved
111 = Reserved
PP
PP
†
This bit is cleared only by the assertion of GRST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST
or GRST.
6–7
6.6 Socket Power Management Register
This register provides power management control over the socket through a mechanism for slowing or stopping the
clock on the card interface when the card is idle. See Table 6–7 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Socket power management
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R/W
0
15
14
13
12
11
10
0
Name
Type
Default
Socket power management
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
Register:
Type:
Offset:
Default:
Socket power management
Read-only, Read/Write
CardBus Socket Address + 20h
0000 0000h
Table 6–7. Socket Power Management Register Description
BIT
SIGNAL
TYPE
FUNCTION
31–26
RSVD
R
Reserved. These bits return 0s when read.
Socket access status. This bit provides information on when a socket access has occurred. This bit is
cleared by a read access.
25
SKTACCES
R
0 = No PC Card access has occurred (default).
1 = PC Card has been accessed.
Socket mode status. This bit provides clock mode information.
24
23–17
16
SKTMODE
RSVD
R
R
0 = Normal clock operation
1 = Clock frequency has changed.
These bits return 0s when read.
CardBus clock control enable. This bit, when set, enables clock control according to bit 0 (CLKCTRL).
CLKCTRLEN
RSVD
R/W
R
0 = Clock control disabled (default)
1 = Clock control enabled
15–1
These bits return 0s when read.
CardBus clock control. This bit determines whether the CardBus CLKRUN protocol will attempt to stop or
slow the CardBus clock during idle states. The CLKCTRLEN bit enables this bit.
0
CLKCTRL
R/W
0 = Allows the CardBus CLKRUN protocol to attempt to stop the CardBus clock (default)
1 = Allows the CardBus CLKRUN protocol to attempt to slow the CardBus clock by a factor of 16
6–8
7 Distributed DMA (DDMA) Registers
The DMA base address, programmable in PCI configuration space at offset 98h, points to a 16-byte region in PCI
I/O space where the DDMA registers reside. Table 7–1 summarizes the names and locations of these registers.
These registers are identical in function, but different in location from the Intel 8237 DMA controller. The similarity
between the register models retains some level of compatibility with legacy DMA and simplifies the translation
required by the master DMA device when forwarding legacy DMA writes to DMA channels.
These PCI4451 DMA register definitions are identical to those registers of the same name in the 8237 DMA controller;
however, some register bits defined in the 8237 do not apply to distributed DMA in a PCI environment. In such cases,
the PCI4451 will implement these obsolete register bits as nonfunctional, read-only bits. The reserved registers
shown in Table 7–1 are implemented as read-only, and return 0s when read. Writes to reserved registers have no
effect.
Table 7–1. Distributed DMA Registers
DMA BASE ADDRESS
REGISTER NAME
OFFSET
Current address
Base address
Current count
Base count
00h
04h
08h
0Ch
Reserved
Reserved
Page
Reserved
Reserved
Reserved
N/A
Mode
N/A
Status
Request
N/A
Command
Multichannel
Mask
Reserved
Master clear
7–1
7.1 DMA Current Address/Base Address Register
This register is used to set the starting (base) memory address of a DMA transfer. Reads from this register indicate
the current memory address of a direct memory transfer.
For the 8-bit DMA transfer mode, the DMA current address register contents are presented on AD15–AD0 of the PCI
bus during the address phase. Bits 7–0 of the DMA page register are presented on AD23–AD16 of the PCI bus during
the address phase.
For the 16-bit DMA transfer mode, the DMA current address register contents are presented on AD16–AD1 of the
PCI bus during the address phase, and AD0 is driven to logic 0. Bits 7–1 of the DMA page register are presented on
AD23–AD17 of the PCI bus during the address phase, and bit 0 is ignored.
Bit
15
14
13
12
11
10
9
8
Name
Type
Default
Bit
DMA current address/base address
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
2
1
0
Name
Type
Default
DMA current address/base address
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
DMA current address/base address
Read/Write
Offset:
Default:
DMA Base Address + 00h
0000h
7.2 DMA Page Register
This register is used to set the upper byte of the address of a DMA transfer. Details of the address represented by
this register are explained in the DMA current address/base address register, above.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
DMA page
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
DMA page
Read/Write
Offset:
Default:
DMA Base Address + 02h
00h
7–2
7.3 DMA Current Count/Base Count Register
This register is used to set the total transfer count, in bytes, of a direct memory transfer. Reads from this register
indicate the current count of a direct memory transfer. In the 8-bit transfer mode, the count is decremented by 1 after
each transfer. Likewise, the count is decremented by 2 in 16-bit transfer mode.
Bit
15
14
13
12
11
10
9
8
Name
Type
Default
Bit
DMA current count/base count
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
2
1
0
Name
Type
Default
DMA current count/base count
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
DMA current count/base count
Read/Write
Offset:
Default:
DMA Base Address + 04h
0000h
7.4 DMA Command Register
Bit 2 of this register is used to enable and disable the controller; all other bits are reserved. See Table 7–2 for a
complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
DMA command
R
0
R
0
R
0
R
0
R
0
R/W
0
R
0
R
0
Register:
Type:
Offset:
Default:
DMA command
Read-only, Read/Write
DMA Base Address + 08h
00h
Table 7–2. DDMA Command Register Description
FUNCTION
BIT
SIGNAL
TYPE
7–3
RSVD
R
These bits return 0s when read.
DMA controller enable. This bit enables and disables the distributed DMA slave controller in the PCI4451, and
defaults to the enabled state.
2
DMAEN
RSVD
R/W
R
0 = DMA controller enabled (default)
1 = DMA controller disabled
1–0
These bits return 0s when read.
7–3
7.5 DMA Status Register
This register indicates the terminal count and DMA request (DREQ) status. See Table 7–3 for a complete description
of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
DMA status
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
DMA status
Read-only
Offset:
Default:
DMA Base Address + 08h
00h
Table 7–3. DMA Status Register Description
BIT
SIGNAL
TYPE
FUNCTION
Channel request. In the 8237, these bits indicate the status of the DREQ signal of each DMA channel. In
the PCI4451, these bits indicate the DREQ status of the single socket being serviced by this register. All
four bits are set when the PC Card asserts its DREQ signal, and are reset when DREQ is deasserted. The
status of the mask bit in the DMA multichannel mask register has no effect on these bits.
7–4
DREQSTAT
R
Channel terminal count. The 8327 uses these bits to indicate the TC status of each of its four DMA
channels. In the PCI4451, these bits report information about just a single DMA channel; therefore, all four
of these register bits indicate the TC status of the single socket being serviced by this register. All four bits
are set when the terminal count (TC) is reached by the DMA channel. These bits are reset when read or
when the DMA channel is reset.
3–0
TC
R
7.6 DMA Request Register
This register is used to request a DDMA transfer through software. Any write to this register enables software
requests. This register is to be used in block mode only.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
DMA request
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
Register:
Type:
DMA request
Write-only
Offset:
Default:
DMA Base Address + 09h
00h
7–4
7.7 DMA Mode Register
This register is used to set the DMA transfer mode. See Table 7–4 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
DMA mode
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
Register:
Type:
Offset:
Default:
DMA mode
Read-only, Read/Write
DMA Base Address + 0Bh
00h
Table 7–4. DDMA Mode Register Description
BIT
SIGNAL
TYPE
FUNCTION
Mode select bits. The PCI4451 uses these bits to determine the transfer mode.
00 = Demand mode select (default)
01 = Single mode select
10 = Block mode select
11 = Reserved
7–6
DMAMODE
R/W
Address increment/decrement. The PCI4451 uses this register bit to select the memory address in the
DMA current address/base address register to increment or decrement after each data transfer. This is
in accordance with the 8237 use of this register bit, and is encoded as follows:
5
4
INCDEC
R/W
R/W
0 = Addresses increment (default)
1 = Addresses decrement
Auto-initialization bit.
AUTOINIT
0 = Auto-initialization disabled (default)
1 = Auto-initialization enabled
Transfer type. These bits select the type of direct memory transfer to be performed. A memory write
transfer moves data from the PCI4451 PC Card interface to memory, and a memory read transfer moves
data from memory to the PCI4451 PC Card interface. The field is encoded as:
3–2
1–0
XFERTYPE
RSVD
R/W
R
00 = No transfer selected (default)
01 = Write transfer
10 = Read transfer
11 = Reserved
These bits return 0s when read.
7.8 DMA Master Clear Register
This register is used to reset the DDMA controller, and resets all DDMA registers.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
DMA master clear
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
Register:
Type:
DMA master clear
Write-only
Offset:
Default:
DMA Base Address + 0Dh
00h
7–5
7.9 DMA Multichannel Mask Register
The PCI4451 uses only the least significant bit of this register to mask the PC Card DMA channel. The PCI4451 sets
the mask bit when the PC Card is removed. Host software is responsible for either resetting the socket DMA controller
or re-enabling the mask bit. See Table 7–5 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
DMA multichannel mask
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
1
Register:
Type:
Offset:
Default:
Size:
DMA multichannel mask
Read-only, Read/Write
DMA Base Address + 0Fh
00h
One byte
Table 7–5. DDMA Multichannel Mask Register Description
BIT
SIGNAL
TYPE
FUNCTION
7–1
RSVD
R
These bits return 0s when read.
Mask select bit. This bit masks incoming DREQ signals from the PC Card. When set, the socket ignores
DMA requests from the card. When cleared (or when reset), incoming DREQ assertions are serviced
normally.
0
MASKBIT
R/W
0 = DDMA service provided on card DREQ
1 = Socket DREQ signal ignored (default)
7–6
8 OHCI-Lynx Controller Programming Model
This chapter describes the internal registers used to program the link function, including both PCI configuration
registers and Open HCI registers. All registers are detailed in the same format. A brief description is provided for each
register, followed by the register offset and a bit table describing the reset state for each register.
A bit description table, typically included when a register contains bits of more than one type or purpose, indicates
bit field names, a detailed field description, and field access tags, which appear in the type column of the bit description
table. Table 8–1 describes the field access tags.
A bit description table is typically included that indicates bit field names, a detailed field description, and field access
tags. Table 8–1 describes the field access tags.
Table 8–1. Bit Field Access Tag Descriptions
ACCESS TAG
NAME
Read
Write
Set
MEANING
R
W
S
Field may be read by software.
Field may be written by software to any value.
Field may be set by a write of 1. Writes of 0 have no effect.
Field may be cleared by a write of 1. Writes of 0 have no effect.
Field may be autonomously updated by the PCI4451.
C
U
Clear
Update
8–1
8.1 PCI Configuration Registers
The PCI4451 link function configuration header is compliant with the PCI Specification as a standard header.
Table 8–2 illustrates the PCI configuration header which includes both the predefined portion of the configuration
space and the user definable registers. The registers that are labeled Reserved are read-only returning 0 when read
and are not applicable to the link function or have been reserved by the PCI Specification for future use.
Table 8–2. PCI Configuration Register Map
REGISTER NAME
OFFSET
00h
Device ID
Vendor ID
PCI Status
PCI Command
04h
Class code
Header type
Open HCI registers base address
Revision ID
08h
BIST
Latency timer
Cache line size
0Ch
10h
TI extension base address
Reserved
14h
18h
Reserved
1Ch
20h
Reserved
Reserved
24h
Reserved
28h
Subsystem ID
Subsystem vendor ID
2Ch
30h
Reserved
Power management
capabilites pointer
Reserved
34h
Reserved
38h
3Ch
MAX_LAT
MIN_GNT
Interrupt pin
Interrupt line
PCI OHCI control
40h
Power management capabilities
Power management extension
Next item pointer
Capability ID
44h
Power management control and status
48h
Reserved
4Ch–ECh
F0h
PCI miscellaneous configuration
Link_enhancements
F4h
Subsystem ID alias
Subsystem vendor ID alias
GPIO1 GPIO0
F8h
GPIO3
GPIO2
FCh
Reserved
100h–C0Ch
C10h
Link timer adjustment
8–2
8.2 Vendor ID Register
This 16-bit read-only register contains a value allocated by the PCI SIG and identifies the manufacturer of the PCI
device. The vendor ID assigned to Texas Instruments is 104Ch.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Vendor ID
R
0
R
0
R
0
R
1
R
0
R
0
R
0
R
0
R
0
R
1
R
0
R
0
R
1
R
1
R
0
R
0
Register:
Type:
Offset:
Default:
Vender ID
Read-only
00h
104Ch
8.3 Device ID Register
This 16-bit read-only register contains a value assigned to the PCI4451 by Texas Instruments. The device
identification for the PCI4451 OHCI controller function is 8027h.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Device ID
R
1
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
1
R
0
R
0
R
1
R
1
R
1
Register:
Type:
Offset:
Default:
Device ID register
Read-only
02h
8027h
8–3
8.4 PCI Command Register
The command register provides control over the PCI4451 link interface to the PCI bus. All bit functions adhere to the
definitions in the PCI Local Bus Specification, as seen in the following bit descriptions.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
PCI command
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R
0
R/W
0
R
0
R/W
0
R
0
R/W
0
R/W
0
R
0
Register:
Type:
PCI command
Read-only, Read/Write
Offset:
Default:
04h
0000h
Table 8–3. PCI Command Register Description
BIT
SIGNAL
TYPE
FUNCTION
15–10
RSVD
R
Reserved. These bits return 0s when read.
Fast back-to-back enable. The PCI4451 will not generate fast back-to-back transactions, thus this bit
returns 0 when read.
9
8
7
6
5
4
FBB_ENB
SERR_ENB
STEP_ENB
PERR_ENB
VGA_ENB
MWI_ENB
R
R/W
R
SERR enable. When set, the PCI4451 SERR driver is enabled. SERR can be asserted after detecting an
address parity error on the PCI bus.
Address/data stepping control. The PCI4451 does not support address/data stepping, and this bit is
hardwired to 0.
Parity error enable. When set, the PCI4451 is enabled to drive PERR response to parity errors through the
PERR signal.
R/W
R
VGA palette snoop enable. The PCI4451 does not feature VGA palette snooping. This bit returns 0 when
read.
Memory write and invalidate enable. When set, the PCI4451 is enabled to generate MWI PCI bus
commands. If reset, the PCI4451 will generate memory write commands instead.
R/W
Special cycle enable. The PCI4451 function does not respond to special cycle transactions. This bit
returns 0 when read.
3
2
1
SPECIAL
R
MASTER_ENB
MEMORY_ENB
R/W
R/W
Bus master enable. When set, the PCI4451 is enabled to initiate cycles on the PCI bus.
Memory response enable. Setting this bit enables the PCI4451 to respond to memory cycles on the PCI
bus. This bit must be set to access OHCI registers.
I/O space enable. The PCI4451 link does not implement any I/O mapped functionality; thus, this bit
returns 0 when read.
0
IO_ENB
R
8–4
8.5 PCI Status Register
The PCI status register provides device information to the host system. Bits in this register may be read normally. All
bit functions adhere to the definitions in the PCI Local Bus Specification. PCI bus status is shown through each
function. See Table 8–4 for a complete description of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
PCI status
RCU RCU RCU RCU RCU
R
0
R
1
RCU
R
0
R
0
R
0
R
1
R
0
R
0
R
0
R
0
0
0
0
0
0
0
Register:
Type:
PCI status
Read-only, Read/Clear/Update
Offset:
Default:
06h
0210h
Table 8–4. PCI Status Register Description
BIT
SIGNAL
TYPE
FUNCTION
15
PAR_ERR
RCU
Detected parity error. This bit is set when a parity error is detected, either address or data parity errors.
Signaled system error. This bit is set when SERR is enabled and the PCI4451 signaled a system error to
the host.
14
13
SYS_ERR
MABORT
RCU
RCU
RCU
RCU
R
Received master abort. This bit is set when a cycle initiated by the PCI4451 on the PCI bus has been
terminated by a master abort.
Received target abort. This bit is set when a cycle initiated by the PCI4451 on the PCI bus was
terminated by a target abort.
12
TABORT_REC
TABORT_SIG
PCI_SPEED
Signaled target abort. This bit is set by the PCI4451 when it terminates a transaction on the PCI bus with
a target abort.
11
DEVSEL timing. These bits encode the timing of DEVSEL and are hardwired 01b indicating that the
PCI4451 asserts this signal at a medium speed on non-configuration cycle accesses.
10–9
Data parity error detected. This bit is set when the following conditions have been met:
a. PERR was asserted by any PCI device including the PCI4451
b. The PCI4451 was the bus master during the data parity error
c. The parity error response enable bit is set in the PCI command register (offset 04h,
see Section 4.4).
8
DATAPAR
RCU
Fast back-to-back capable. The PCI4451 cannot accept fast back-to-back transactions; thus, this bit is
hardwired to 0.
7
6
5
FBB_CAP
UDF
R
R
R
UDF supported. The PCI4451 does not support the user definable features; thus, this bit is hardwired to
0.
66-MHz capable. The PCI4451 operates at a maximum PCLK frequency of 33 MHz; therefore, this bit is
hardwired to 0.
66MHZ
Capabilities list. This bit returns 1 when read, and indicates that capabilities additional to standard
PCI are implemented. The linked list of PCI power management capabilities is implemented in this
function.
4
CAPLIST
RSVD
R
R
3–0
Reserved. These bits return 0s when read.
8–5
8.6 Class Code and Revision ID Register
This read-only register categorizes the PCI4451 as a serial bus controller (0Ch), controlling an IEEE1394 bus (00h),
with an OHCI programming model (10h). Furthermore, the TI chip revision is indicated in the lower byte. See
Table 8–5 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Class code and revision ID
R
0
R
0
R
0
R
0
R
1
R
1
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Class code and revision ID
R
0
R
0
R
0
R
1
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
Class code and revision ID
Read-only
08h
0C00 1000h
Table 8–5. Class Code and Revision ID Register Description
BIT
SIGNAL
TYPE
FUNCTION
Base class. This field returns 0Ch when read, which broadly classifies the function as a serial bus
controller.
31–24
BASECLASS
R
Sub class. This field returns 00h when read, which specifically classifies the function as controlling a
IEEE1394 serial bus.
23–16
SUBCLASS
R
Programming interface. This field returns 10h when read, which indicates that the programming model is
compliant with the 1394 OHCI specification.
15–8
7–0
PGMIF
R
R
CHIPREV
Silicon revision. This field returns the silicon revision of the PCI4451.
8.7 Latency Timer and Class Cache Line Size Register
This register is programmed by host BIOS to indicate system cache line size and the latency timer associated with
the PCI4451. See Table 8–6 for a complete description of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Latency timer and class cache line size
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Offset:
Default:
Latency timer and class cache line size
Read/Write
0Ch
0000h
Table 8–6. Latency Timer and Class Cache Line Size Register Description
BIT
SIGNAL
TYPE
FUNCTION
PCI latency timer. The value in this register specifies the latency timer for the PCI4451, in units of PCI
clock cycles. When the PCI4451 is a PCI bus initiator and asserts FRAME, the latency timer will
begin counting from zero. If the latency timer expires before the PCI4451 transaction has
terminated, then the PCI4451 will terminate the transaction when its GNT is deasserted.
15–8
LATENCY_TIMER
R/W
Cache line size. This value is used by the PCI4451 during memory write and invalidate, memory
read line, and memory read multiple transactions.
7–0
CACHELINE_SZ
R/W
8–6
8.8 Header Type and BIST Register
This register indicates that this function is part of a multifunction device and has a standard PCI header type and
indicates no built-in self-test. See Table 8–7 for a complete description of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Header type and BIST
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
Header type and BIST
Read-only
0Eh
0000h
Table 8–7. Header Type and BIST Register Description
BIT
SIGNAL
TYPE
FUNCTION
Built-in self-test. The PCI4451 does not include a built-in self-test, and this field returns 00h when
read.
15–8
BIST
R
PCI header type. The PCI4451 includes the standard PCI header, and this is communicated by
returning 00h when this field is read.
7–0
HEADER_TYPE
R
8.9 Open HCI Registers Base Address Register
This register is programmed with a base address referencing the memory mapped OHCI control. When BIOS writes
all 1s to this register, the value read back is FFFF F800h, indicating that at least 2 Kbytes of memory address space
are required for the OHCI registers. See Table 8–8 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Open HCI registers base address
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Open HCI registers base address
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
Open HCI registers base address
Read-only, Read/Write
10h
0000 0000h
Table 8–8. Open HCI Registers Base Address Register Description
BIT
SIGNAL
TYPE
FUNCTION
31–11
OHCIREG_PTR
R/W
Open HCI register pointer. Specifies the upper 21 bits of the 32-bit OHCI register base address.
Open HCI register size. This field returns 0s when read, and indicates that the OHCI registers
require a 2-Kbyte region of memory.
10–4
3
OHCI_SZ
R
R
R
OHCI_PF
OHCI register prefetch. This bit returns 0, indicating the OHCI registers are nonprefetchable.
Open HCI memory type. This field returns 0s when read, and indicates that the base register is
32 bits wide and mapping can be done anywhere in the 32-bit memory space.
2–1
OHCI_MEMTYPE
OHCI memory indicator. This bit returns 0, indicating the OHCI registers are mapped into system
memory space.
0
OHCI_MEM
R
8–7
8.10 TI Extension Base Address Register
This register is programmed with a base address referencing the memory mapped TI extension registers. See
Table 8–9 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
TI extension base address
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
TI extension base address
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
TI extension base address
Read/Write, Read-only
14h
0000 0000h
Table 8–9. TI Extension Base Address Register Description
BIT
SIGNAL
TYPE
FUNCTION
TI extension register pointer. Specifies the upper 20 bits of the 32-bit TI extension register base
address.
31–11
TI_EXTREG_PTR
TI_SZ
R/W
TI extension register size. This field returns 0s when read, and indicates that the TI extension
registers require a 2-Kbyte region of memory.
10–4
3
R
R
R
R
TI extension register prefetch. This bit returns 0, indicating the TI extension registers are
nonprefetchable.
TI_PF
TI memory type. This field returns 0s when read, and indicates that the base register is 32 bits wide
and mapping can be done anywhere in the 32-bit memory space.
2–1
0
TI_MEMTYPE
TI_MEM
TI memory indicator. This bit returns 0, indicating the TI extension registers are mapped into system
memory space.
8.11 Subsystem Vendor ID Register
This register is used for subsystem and option card identification purposes, and identifies the subsystem vendor. This
register can be initialized from the serial EEPROM or can be written using the subsystem access identification
register.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Subsystem vendor ID
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
Register:
Type:
Offset:
Default:
Subsystem vendor ID
Read/Update
2Ch
0000 0000h
8–8
8.12 Subsystem ID Register
This register is used for subsystem and option card identification purposes, and identifies the subsystem device. This
register can be initialized from the serial EEPROM or can be written using the subsystem access identification
register.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Subsystem ID
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
Register:
Type:
Offset:
Default:
Subsystem ID
Read/Update
2Eh
0000 0000h
8.13 PCI Power Management Capabilities Pointer Register
This register provides a pointer into the PCI configuration header where the PCI power management register block
resides. PCI4451 configuration header doublewords at 44h and 48h provide the power management registers. This
register is read-only and returns 44h when read.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
PCI power management capabilities pointer
R
0
R
1
R
0
R
0
R
0
R
1
R
0
R
0
Register:
Type:
Offset:
Default:
PCI power management capabilities pointer
Read-only
34h
44h
8.14 Interrupt Line and Interrupt Pin Registers
This register is used to communicate interrupt line routing information. See Table 8–10 for a complete description of
the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Interrupt line and interrupt pin
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Interrupt line and interrupt pin
Read-only, Read/Write
Offset:
Default:
3Ch
0000h
Table 8–10. Interrupt Line and Interrupt Pin Registers Description
BIT
SIGNAL
TYPE
FUNCTION
Interrupt pin register. This register returns 01h, 02h, or 03h when read, indicating that the PCI4451
link function signals interrupts on INTA, INTB, or INTC terminal.
15–8
INTR_PIN
R
Interrupt line register. This register is programmed by the system and indicates to the software
which interrupt line the PCI4451 INTA is connected to.
7–0
INTR_LINE
R/W
8–9
8.15 MIN_GNT and MAX_LAT registers
This register is used to communicate to the system the desired setting of the latency timer register. If a serial ROM
is detected, then the contents of this register are loaded through the serial ROM interface after a PCI reset. If no serial
ROM is detected, then this register returns a default value that corresponds to the MIN_GNT = 2, MAX_LAT = 2. See
Table 8–11 for a complete description of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
MIN_GNT and MAX_LAT
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
1
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
1
RU
0
Register:
Type:
Offset:
Default:
MIN_GNT and MAX_LAT
Read/Update
3Eh
0202h
Table 8–11. MIN_GNT and MAX_LAT Registers Description
BIT
SIGNAL
TYPE
FUNCTION
Maximum latency. The contents of this register may be used by host BIOS to assign an arbitration
priority-level to the PCI4451. The default for this register indicates that the PCI4451 may need to access the
PCI bus as often as every 1/4 µs; thus, an extremely high priority level is requested. The contents of this
field may also be loaded through the serial ROM.
15–8
MAX_LAT
RU
RU
Minimum grant. The contents of this register may be used by host BIOS to assign a latency timer register
value to the PCI4451. The default for this register indicates that the PCI4451 may need to sustain burst
transfers for nearly 64 µs; thus, requesting a large value be programmed in bits 15–8 of the PCI4451
latency timer register (offset 0Ch, see Section 8.7).
7–0
MIN_GNT
8.16 PCI OHCI Control Register
This register contains IEEE 1394 open HCI specific control bits. All bits in this register are read-only and return 0s,
since no OHCI specific control bits have been implemented.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
PCI OHCI control
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
PCI OHCI control
Read-only
40h
0000h
8–10
8.17 Capability ID And Next Item Pointer Registers
This register identifies the linked list capability item, and provides a pointer to the next capability item. See Table 8–12
for a complete description of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Capability ID and next item pointer
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
1
Register:
Type:
Offset:
Default:
Capability ID and next item pointer
Read-only
44h
0001h
Table 8–12. Capability ID and Next Item Pointer Registers Description
BIT
SIGNAL
TYPE
FUNCTION
Next item pointer. The PCI4451 supports only one additional capability that is communicated to
the system through the extended capabilities list; thus, this field returns 00h when read.
15–8
NEXT_ITEM
R
Capability identification. This field returns 01h when read, which is the unique ID assigned by the PCI
SIG for PCI power management capability.
7–0
CAPABILITY_ID
R
8–11
8.18 Power Management Capabilities Register
This register indicates the capabilities of the PCI4451 related to PCI power management. In summary, the D0, D2,
and D3 device states are supported. See Table 8–13 for a complete description of the register contents.
hot
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Power management capabilities
RU
0
RU
1
RU
1
RU
0
RU
0
R
1
R
0
R
0
R
0
R
0
R
0
R
1
R
0
R
0
R
0
R
1
Register:
Type:
Offset:
Default:
Power management capabilities
Read/Update
46h
6411h
Table 8–13. Power Management Capabilities Register Description
BIT
SIGNAL
TYPE
FUNCTION
PME support from D3
is dependent upon PCI4451 V
aux
PCI miscellaneous configuration register.
. When set, PCI4451 generates a PME wake event from D3
. This bit state
cold cold
15
PME_D3COLD
RU
implementation and may be configured by host software using the
PME support. This four-bit field indicates the power states from which the PCI4451 may assert
PME. These four bits return a value of 1100b by default, indicating that PME may be asserted from the
14–11
PME_SUPPORT
RU
D3
and D2 power states. Bit 13 may be modified by host software using the PCI miscellaneous
hot
configuration register (offset F0h, see Section 8.21).
10
9
D2_SUPPORT
D1_SUPPORT
R
R
D2 support. This bit returns a 1 when read, indicating that the PCI4451 supports the D2 power state.
D1 support. This bit returns a 0 when read, indicating that the PCI4451 does not support the D1 power
state.
Dynamic data support. This bit returns a 0 when read, indicating that the PCI4451 does not report
dynamic power consumption data.
8
DYN_DATA
RSVD
R
R
7–6
Reserved. These bits return 0s when read.
Device specific initialization. This bit returns 0 when read, indicating that the PCI4451 does not
require special initialization beyond the standard PCI configuration header before a generic class
driver is able to use it.
5
DSI
R
Auxiliary power source. Since the PCI4451 supports PME generation in the D3
cold
device state and
4
3
AUX_PWR
PME_CLK
R
R
requires V
aux
, this bit returns 1 when read.
PME clock. This bit returns 0 when read indicating that no host bus clock is required for the PCI4451 to
generate PME.
Power management version. This field returns 010b when read, indicating that the PCI4451
is compatible with the registers described in revision 1.1 of the PCI Bus Power Management
Specification. However, 001b supports PCI Bus Power Management Interface Specification revision
1.0.
2–0
PM_VERSION
R
8–12
8.19 Power Management Control and Status Register
This register implements the control and status of the PCI power management function. This register is not affected
by the internally generated reset caused by the transition from the D3
dexcription of the register contents.
to D0 state. See Table 8–14 for a complete
hot
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Power management control and status
RC
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
Register:
Type:
Power management control and status
Read-only, Read/Write, Read/Clear
Offset:
Default:
48h
0000h
Table 8–14. Power Management Control and Status Register Description
BIT
SIGNAL
TYPE
FUNCTION
This bit is set when the PCI4451 would normally be asserting the PME signal, independent of the state of the
PME_ENB bit. When this bit is cleared, the PME signal driven by the PCI4451 will also be cleared.
15
PME_STS
RC
14–9
8
DYN_CTRL
PME_ENB
RSVD
R
R/W
R
Dynamic data control. This bit field returns 0s when read since the PCI4451 does not report dynamic data.
PME enable. This bit enables the function to assert PME. If the bit is cleared assertion of PME is disabled.
Reserved. These bits return 0s when read.
7–5
4
DYN_DATA
RSVD
R
Dynamic data. This bit returns 0 when read since the PCI4451 does not report dynamic data.
Reserved. These bits return 0s when read.
3–2
R
Power state. This two-bit field is used to set the PCI4451 device power state, and is encoded as follows:
00 = Current power state is D0
01 = Current power state is D1
1–0
PWR_STATE
R/W
10 = Current power state is D2
11 = Current power state is D3
hot
8.20 Power Management Extension Register
This register provides extended power management features not applicable to the PCI4451, thus it is read-only and
returns 0 when read. See Table 8–15 for a complete description of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Power management extension
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
Power management extension
Read-only
4Ah
0000h
Table 8–15. Power Management Extension Register Description
BIT
SIGNAL
TYPE
FUNCTION
Power management data. This bit field returns 0s when read since the PCI4451 does not report dynamic
data.
15–8
PM_DATA
R
Power management CSR – bridge support extensions. This field returns 0s since the PCI4451 does not
provide P-to-P bridging.
7–0
PMCSR_BSE
R
8–13
8.21 PCI Miscellaneous Configuration Register
This register provides miscellaneous PCI-related configuration. See Table 8–16 for a complete description of the
register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
PCI miscellaneous configuration
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
PCI miscellaneous configuration
R/W
0
R
0
R/W
1
R
0
R
0
R/W
1
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Offset:
Default:
PCI miscellaneous configuration
Read-only, Read/Write
F0h
0000 2400h
Table 8–16. PCI Miscellaneous Configuration Register Description
BIT
SIGNAL
TYPE
FUNCTION
Reserved. Bits 31–16 return 0s when read.
PME support from D3 . This bit is used to program the corresponding read-only value read
from power management capabilities. This bit retains state through PCI reset and D3–D0
transitions.
31–16
RSVD
PME_D3COLD
RSVD
R
cold
15
14
R/W
R
Reserved. Bit 14 returns 0 when read.
PME support. This bit is used to program the corresponding read-only value read from power
management capabilities. If wake from the D2 power state implemented in PCI4451 is not
desired, then this bit may be cleared to indicate to power management software that wake-up
from D2 is not supported. This bit retains state through PCI reset and D3–D0 transitions.
13
12–11
10
PME_SUPPORT_D2
RSVD
R/W
R
Reserved. Bits 12 and 11 return 0s when read.
D2 support. This bit is used to program the corresponding read-only value read from power
management capabilities. If the D2 power state implemented in PCI4451 is not desired, then
this bit may be cleared to indicate to power management software that D2 is not supported.
This bit retains state through PCI reset and D3–D0 transitions.
D2_SUPPORT
R/W
9–4
3
RSVD
R
Reserved. Bits 9–4 return 0s when read.
RSVD
R/W
R/W
R/W
Reserved. Bit 3 defaults to 0.
2
DISABLE_SCLKGATE
DISABLE_PCIGATE
When set, the internal SCLK runs identically with the chip input.
When set, the internal PCI clock runs identically with the chip input.
1
When set, the PCI clock is always kept running through the CLKRUN protocol. When cleared, the
PCI clock may be stopped using CLKRUN.
0
KEEP_PCLK
R/W
8–14
8.22 Link Enhancement Control Register
This register implements TI proprietary bits that are initialized by software or by a serial EEPROM if present. After
these bits are set, their functionality is enabled only if the aPhyEnhanceEnable bit (bit 22) in the host controller control
register (offset 50h/54h, see Section 9.16) is set. See Table 8–17 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Link enhancement control
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Link enhancement control
R
0
R
0
R/W
0
R/W
1
R
0
R
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R
0
Register:
Type:
Offset:
Default:
Link enhancement control
Read-only, Read/Write
F4h
0000 1000h
Table 8–17. Link Enhancement Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
Reserved. These bits return 0s when read.
31–14
RSVD
R
This bit field sets the initial AT threshold value, which is used until the AT FIFO is underrun. When
PCI4451 retries the packet, it uses a 2K-byte threshold resulting in store-and-forward operation.
00 = Threshold ~ 2 Kbytes resulting in store-and-forward operation
01 = Threshold ~ 1.7 Kbytes (default)
10 = Threshold ~ 1 Kbyte
13–12
atx_thresh
R/W
11 = Threshold ~ 512 bytes
11–10
RSVD
R
Reserved. This bit returns 0 when read.
Enable audio/music CIP timestamp enhancement. When this bit is set, the enhancement is
enabled for audio/music CIP transmit streams (FMT = 10h).
9
enab_audio_ts
R/W
Enable DV CIP timestamp enhancement. When this bit is set, the enhancement is enabled for DV
CIP transmit streams (FMT = 00h).
8
7
enab_dv_ts
enab_unfair
R/W
R/W
Enable asynchronous priority requests. OHCI-Lynx (TSB12LV22) compatible
This reserved field will not be assigned in PCI4451 follow-on products since this bit location loaded
by the serial ROM from the enhancements field corresponds to the programPhyEnable bit (bit 23)
in the host controller control register (offset 50h/54h, see Section 9.16) in open HCI register space.
6
RSVD
R
5–3
2
RSVD
enab_insert_idle
enab_accel
RSVD
R
Reserved. Bits 5–3 return 0s when read.
R/W
R/W
R
Enable insert idle. OHCI-Lynx (TSB12LV22) compatible
Enable acceleration enhancements. OHCI-Lynx (TSB12LV22) compatible
Reserved. This bit returns 0 when read.
1
0
8–15
8.23 Subsystem Access Identification Register
This register is used for system and option card identification purposes. The contents of this register are aliased to
subsystem identification register at address 2Ch. See Table 8–18 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Subsystem access identification
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Subsystem access identification
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Offset:
Default:
Subsystem access identification
Read/Write
F8h
0000 0000h
Table 8–18. Subsystem Access Identification Register Description
BIT
31–16
15–0
SIGNAL
TYPE
R/W
FUNCTION
SUBDEV_ID
SUBVEN_ID
Subsystem device ID. This field indicates the subsystem device ID.
Subsystem vendor ID. This field indicates the subsystem vendor ID.
R/W
8–16
8.24 GPIO Control Register
This register has the control and status bits for GPIO0, GPIO1, GPIO2 and GPIO3 ports. Upon reset, GPIO0 and
GPIO1 default to bus manager contender (BMC) and link power status terminals, respectively. The BMC terminal can
be configured as GPIO0 by setting the disable_BMC bit to 1. The LPS terminal can be configured as GPIO1 by setting
the disable_LPS bit to 1. See Table 8–19 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
GPIO control
R
0
R
0
R/W
0
R/W
0
R
0
R
0
R
0
9
R/W
0
R
0
7
R
0
6
R/W
0
R/W
0
R
0
3
R
0
2
R
0
1
R/W
0
15
14
13
12
11
10
8
5
4
0
Name
Type
Default
GPIO control
R/W
0
R
0
R/W
0
R/W
1
R
0
R
0
R
0
R/W
0
R/W
0
R
0
R/W
0
R/W
1
R
0
R
0
R
0
R/W
0
Register:
Type:
Offset:
Default:
GPIO control
Read-only, Read/Write
FCh
0000 1010h
Table 8–19. General-Purpose Input/Output Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
31–30
RSVD
R
Reserved. These bits return 0s when read.
GPIO3 polarity invert. This bit controls the input/output polarity control of GPIO3.
29
28
GPIO_INV3
GPIO_ENB3
R/W
R/W
0 = noninverted (default)
1 = inverted
GPIO3 enable control. This bit controls the output enable for GPIO3
0 = high-impedance output (default)
1 = output enabled
27–25
24
RSVD
GPIO_DATA3
RSVD
R
R/W
R
Reserved. These bits return 0s when read.
GPIO3 data. When GPIO3 output is enabled, the value written to this bit represents the logical data
driven to the GPIO3 terminal.
23–22
Reserved. These bits return 0s when read.
GPIO2 polarity invert. This bit controls the input/output polarity control of GPIO2.
21
20
GPIO_INV2
GPIO_ENB2
R/W
R/W
0 = noninverted (default)
1 = inverted
GPIO2 enable control. This bit controls the output enable for GPIO2.
0 = high-impedance output (default)
1 = output enabled
19–17
RSVD
R
Reserved. These bits return 0s when read.
GPIO2 data. When GPIO2 output is enabled, the value written to this bit represents the logical data
driven to the GPIO2 terminal.
16
GPIO_DATA2
R/W
Disable link power status (LPS). This bit configures this terminal as
15
14
DISABLE_LPS
RSVD
R/W
R
0 = LPS (default)
1 = GPIO1
Reserved. This bit returns 0 when read.
GPIO1 polarity invert. When DISABLE_LPS bit is set to 1, this bit controls the input output polarity control
of GPIO1
13
12
GPIO_INV1
GPIO_ENB1
R/W
R/W
0 = noninverted (default)
1 = inverted
GPIO1 enable control. When DISABLE_LPS bit is set to 1, this bit controls the output enable for GPIO1
0 = high-impedance output
1 = output enabled (default)
8–17
Table 8–19. General-Purpose Input/Output Control Register Description (Continued)
BIT
SIGNAL
TYPE
FUNCTION
11–9
RSVD
R
Reserved. These bits return 0s when read.
GPIO1 data. When DISABLE_LPS bit is set to 1 and GPIO1 output is enabled, the value written to this bit
represents the logical data driven to the GPIO1 terminal.
8
GPIO_DATA1
R/W
Disable bus manager contender (BMC). This bit configures this terminals as bus master contender or
GPIO.
7
6
5
DISABLE_BMC
RSVD
R/W
R
0 = BMC (default)
1 = GPIO0
Reserved. This bit returns 0 when read.
GPIO0 polarity invert. When DISABLE_BMC bit is set to 1, this bit controls the input/output polarity
control of for GPIO0.
0 = non-inverted (default)
1 = inverted
GPIO_INV0
R/W
GPIO0 enable control. When DISABLE_BMC bit is set to 1, this bit controls the output enable for GPIO0.
4
GPIO_ENB0
R/W
0 = high-impedance output
1 = output enabled (default)
3–1
RSVD
R
Reserved. These bits return 0s when read.
GPIO0 data. When DISABLE_BMC bit is set to 1 and GPIO0 output is enabled, the value written to
this bit represents the logical data driven to the GPIO0 terminal.
0
GPIO_DATA0
R/W
8.25 Link Timer Adjustment Register
This register is used to control the link rollover value, and should be programmed with a nonzero value only when
PCI4451 is the 1394 cycle master. See Table 8–20 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Link timer adjustment
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Link timer adjustment
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Offset:
Default:
Link timer adjustment
Read-only, Read/Write
C10h
0000 0000h
Table 8–20. Link Timer Adjustment Register Description
BIT
SIGNAL
TYPE
FUNCTION
31–8
RSVD
R
Reserved. These bits return 0s when read.
This bit indicates that the timer adjust request is active, but not completed. This bit is set whenever
the timer adjust field is written, and is cleared when the actual adjustment is made.
7
TIMER_ADJ_REQ
RSVD
R
R
6–4
3–0
Reserved. These bits return 0s when read.
Cycle timer adjustment value. This four bit signed value is used to adjust the PCI4451 cycle timer.
The cycle timer offset field may be adjusted from +7 to –8 using this register.
TIMER_ADJ_VAL
R/W
8–18
9 Open HCI Registers
The open HCI registers defined by the IEEE1394 Open HCI Specification are memory mapped into a 2-Kbyte region
of memory pointed to by the OHCI base address register at offset 10h in PCI configuration space. These registers
are the primary interface for controlling the PCI4451 IEEE1394 link function.
This section provides the register interface and bit descriptions. There are several set and clear register pairs in this
programming model, which are implemented to solve various issues with typical read-modify-write control registers.
There are two addresses for a set/clear register: RegisterSet and RegisterClear. Refer to Table 9–1 for an illustration.
A 1 written to RegisterSet causes the corresponding bit in the set/clear register to be set, while a 0 leaves the
corresponding bit unaffected. A 1 written to RegisterClear causes the corresponding bit in the set/clear register to
be reset, while a 0 leaves the corresponding bit in the set/clear register unaffected.
Typically, a read from either RegisterSet or RegisterClear returns the value of the set/clear register. However,
sometimes reading the RegisterClear will provide a masked version of the set/clear register. The interrupt event
register (offset 80h/84h, see Section 9.21) is an example of this behavior.
Table 9–1. Open HCI Register Map
DMA CONTEXT
REGISTER NAME
ABBREVIATION
OFFSET
00h
—
OHCI version
Version
Global unique ID ROM
Asynchronous transmit retries
CSR data
GUID_ROM
ATRetries
04h
08h
CSRData
0Ch
10h
CSR compare
CSRCompareData
CSRControl
ConfigROMhdr
BusID
CSR control
14h
Configuration ROM header
Bus identification
Bus options
18h
1Ch
20h
BusOptions
GUIDHi
Global unique ID high
Global unique ID low
Reserved
24h
GUIDLo
28h
—
2Ch
30h
Reserved
—
Configuration ROM mapping
Posted write address low
Posted write address high
Vendor ID
ConfigROMmap
PostedWriteAddressLo
PostedWriteAddressHi
VendorID
34h
38h
3Ch
40h
Reserved
—
44h – 4Ch
9–1
Table 9–1. Open HCI Register Map (Continued)
DMA CONTEXT
REGISTER NAME
Host controller control
ABBREVIATION
OFFSET
50h
—
HCControlSet
HCControlClr
54h
Reserved
—
58h
Reserved
—
5Ch
Self ID
Reserved
—
60h
Self ID buffer pointer
Self ID count
Reserved
SelfIDBuffer
64h
SelfIDCount
68h
—
6Ch
—
IRChannelMaskHiSet
IRChannelMaskHiClear
IRChannelMaskLoSet
IRChannelMaskLoClear
IntEventSet
70h
Isochronous receive channel mask high
Isochronous receive channel mask low
Interrupt event
74h
78h
7Ch
80h
IntEventClear
84h
IntMaskSet
88h
Interrupt mask
IntMaskClear
8Ch
IsoXmitIntEventSet
IsoXmitIntEventClear
IsoXmitIntMaskSet
IsoXmitIntMaskClear
IsoRecvIntEventSet
IsoRecvIntEventClear
IsoRecvIntMaskSet
IsoRecvIntMaskClear
90h
Isochronous transmit interrupt event
Isochronous transmit interrupt mask
Isochronous receive interrupt event
Isochronous receive interrupt mask
94h
98h
9Ch
—
A0h
A4h
A8h
ACh
B0–D8h
DCh
E0h
Reserved
Fairness control
FairnessControl
LinkControlSet
Link control
LinkControlClear
E4h
Node identification
PHY control
NodeID
E8h
PhyControl
ECh
F0h
Isochronous cycle timer
Reserved
IsoCycleTimer
—
F4h – FCh
100h
104h
108h
10Ch
110h
114h
118h
11Ch
120h
124h – 17Ch
AsyncRequestFilterHiSet
AsyncRequestFilterHiClear
AsyncRequestFilterLoSet
AsyncRequestFilterloClear
PhysicalRequestFilterHiSet
PhysicalRequestFilterHiClear
PhysicalRequestFilterLoSet
PhysicalRequestFilterLoClear
PhysicalUpperBound
—
Asynchronous request filter high
Asynchronous request filter low
Physical request filter high
Physical request filter low
Physical upper bound
Reserved
9–2
Table 9–1. Open HCI Register Map (Continued)
DMA CONTEXT
REGISTER NAME
Asynchronous context control
ABBREVIATION
OFFSET
180h
ContextControlSet
ContextControlClear
—
184h
Asychronous request
transmit
Reserved
188h
[ ATRQ ]
Asynchronous context command pointer
Reserved
CommandPtr
—
18Ch
190h – 19Ch
1A0h
ContextControlSet
ContextControlClear
—
Asynchronous context control
1A4h
Asychronous response
transmit
Reserved
1A8h
[ ATRS ]
Asynchronous context command pointer
Reserved
CommandPtr
—
1ACh
1B0h – 1BCh
1C0h
ContextControlSet
ContextControlClear
—
Asynchronous context control
1C4h
Asychronous request
receive
Reserved
1C8h
[ ARRQ ]
Asynchronous context command pointer
Reserved
CommandPtr
—
1CCh
1D0h – 1DCh
1E0h
ContextControlSet
ContextControlClear
—
Asynchronous context control
1E4h
Asychronous response
receive
Reserved
1E8h
[ ARRS ]
Asynchronous context command pointer
Reserved
CommandPtr
—
1ECh
1F0h – 1FCh
200h + 16*n
204h + 16*n
208h + 16*n
20Ch + 16*n
280h – 3FFh
400h + 32*n
404h + 32*n
408h + 32*n
40Ch + 32*n
410h + 32*n
ContextControlSet
ContextControlClear
—
Isochronous transmit context control
Isochronous transmit
context n
Reserved
n = 0, 1, 2, 3, … , 7
Isochronous transmit context command pointer
Reserved
CommandPtr
—
ContextControlSet
ContextControlClear
—
Isochronous receive context control
Isochronous receive
context n
Reserved
n = 0, 1, 2, 3, 4
Isochronous receive context command pointer
Isochronous receive context match
CommandPtr
ContextMatch
9–3
9.1 OHCI Version Register
This register indicates the OHCI version support, and whether or not the serial ROM is present. See Table 9–2 for
a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
OHCI version
R
0
R
0
R
0
R
0
R
X
R
X
R
X
9
R
X
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
1
0
15
14
13
12
11
10
Name
Type
Default
OHCI version
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
OHCI version
Read-only
00h
0X01 0000h
Table 9–2. OHCI Version Register Description
BIT
SIGNAL
TYPE
FUNCTION
31–25
RSVD
R
Reserved. These bits return 0s when read.
The PCI4451 sets this bit if the serial ROM is detected. If the serial ROM is present, then the
Bus_Info_Block will be automatically loaded on hardware reset.
24
GUID_ROM
R
Major version of the open HCI. The PCI4451 is compliant with the OHCI specification version 1.00; thus,
this field reads 01h.
23–16
15–8
7–0
version
RSVD
R
R
R
Reserved. These bits return 0s when read.
Minor version of the Open HCI. The PCI4451 is compliant with the OHCI specification version 1.00; thus,
this field reads 00h.
revision
9–4
9.2 Global Unique ID ROM Register
This register is used to access the serial ROM, and is only applicable if the GUID_ROM bit (bit 24) in the OHCI version
register (offset 00h, see Section 9.1) is set. See Table 9–3 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Global unique ID ROM
RSU
0
R
0
R
0
R
0
R
0
R
0
RSU
R
0
8
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
0
15
14
13
12
11
10
9
7
6
5
4
3
2
1
0
Name
Type
Default
Global unique ID ROM
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Global Unique ID ROM
Read-only, Read/Set/Update, Read/Update
Offset:
Default:
04h
00XX 0000h
Table 9–3. Global Unique ID ROM Register Description
BIT
31
SIGNAL
addrReset
RSVD
TYPE
RSU
R
FUNCTION
Software sets this bit to reset the GUID ROM address to 0. When the PCI4451 completes the reset,
it clears this bit. The PCI4451 does not automatically fill rdData with the 0 byte.
th
30–26
25
Reserved. These bits return 0s when read.
A read of the currently addressed byte is started when this bit is set. This bit is automatically cleared
when the PCI4451 completes the read of the currently addressed GUID ROM byte.
rdStart
RSU
24
RSVD
rdData
RSVD
R
RU
R
Reserved. ThIs bit returns 0 when read.
23–16
15–0
This field represents the data read from the GUID ROM.
Reserved. These bits return 0s when read.
9–5
9.3 Asynchronous Transmit Retries Register
This register indicates the number of times the PCI4451 will attempt a retry for asynchronous DMA request transmit
and for asynchronous physical and DMA response transmit. See Table 9–4 for a complete description of the register
contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Asynchronous transmit retries
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Asynchronous transmit retries
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Offset:
Default:
Asynchronous transmit retries
Read-only, Read/Write
08h
0000 0000h
Table 9–4. Asynchronous Transmit Retries Register Description
BIT
SIGNAL
TYPE
FUNCTION
The second limit field returns 0s when read, since outbound dual-phase retry is not
implemented.
31–29
secondLimit
R
28–16
15–12
cycleLimit
RSVD
R
R
The cycle limit field returns 0s when read, since outbound dual-phase retry is not implemeted.
Reserved. These bits return 0s when read.
The maxPhysRespRetries field tells the physical response unit how many times to attempt to
retry the transmit operation for the response packet when a busy acknowledge or
ack_data_error is received from the target node.
11–8
7–4
3–0
maxPhysRespRetries
maxATRespRetries
maxATReqRetries
R/W
R/W
R/W
The maxATRespRetries field tells the asynchronous transmit response unit how many times
to attempt to retry the transmit operation for the response packet when a busy acknowledge
or ack_data_error is received from the target node.
The maxATReqRetries field tells the asynchronous transmit DMA request unit how many
times to attempt to retry the transmit operation for the response packet when a busy
acknowledge or ack_data_error is received from the target node.
9.4 CSR Data Register
This register is used to access the bus management CSR registers from the host through compare-swap operations.
This register contains the data to be stored in a CSR if the compare is successful.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
CSR data
R
X
R
X
R
X
R
X
R
X
R
X
R
X
9
R
X
8
R
X
7
R
X
6
R
X
5
R
X
4
R
X
3
R
X
2
R
X
1
R
X
0
15
14
13
12
11
10
Name
Type
Default
CSR data
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
Register:
Type:
Offset:
Default:
CSR data
Read-only
0Ch
XXXX XXXXh
9–6
9.5 CSR Compare Register
This register is used to access the bus management CSR registers from the host through compare-swap operations.
This register contains the data to be compared with the existing value of the CSR resource.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
CSR compare
R
X
R
X
R
X
R
X
R
X
R
X
R
X
9
R
X
8
R
X
7
R
X
6
R
X
5
R
X
4
R
X
3
R
X
2
R
X
1
R
X
0
15
14
13
12
11
10
Name
Type
Default
CSR compare
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
Register:
Type:
Offset:
Default:
CSR compare
Read-only
10h
XXXX XXXXh
9.6 CSR Control Register
This register is used to access the bus management CSR registers from the host through compare-swap operations.
This register is used to control the compare-swap operation and select the CSR resource. See Table 9–5 for a
complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
CSR control
RU
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
CSR control
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
X
R/W
X
Register:
Type:
CSR control
Read-only, Read/Update, Read/Write
Offset:
Default:
14h
0000 0000h
Table 9–5. CSR Control Register Description
BIT
31
SIGNAL
csrDone
RSVD
TYPE
RU
FUNCTION
This bit is set by the PCI4451 when a compare-swap operation is complete. It is reset whenever this
register is written.
30–2
R
Reserved. These bits return 0s when read.
This field selects the CSR resource as follows:
00 = BUS_MANAGER_ID
1–0
csrSel
R/W
01 = BANDWIDTH_AVAILABLE
10 = CHANNELS_AVAILABLE_HI
11 = CHANNELS_AVAILABLE_LO
9–7
9.7 Configuration ROM Header Register
This register externally maps to the first quadlet of the 1394 configuration ROM, offset FFFF F000 0400h. See
Table 9–6 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Configuration ROM header
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Configuration ROM header
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
Register:
Type:
Configuration ROM header
Read/Write
Offset:
Default:
18h
0000 XXXXh
Table 9–6. Configuration ROM Header Register Description
BIT
SIGNAL
TYPE
FUNCTION
IEEE 1394 bus management field. Must be valid when the linkEnable bit (bit 17) of the host controller
control register (offset 50h/54h, see Section 9.16) is set.
31–24
info_length
R/W
IEEE 1394 bus management field. Must be valid when the linkEnable bit (bit 17) of the host controller
control register (offset 50h/54h, see Section 9.16) is set.
23–16
15–0
crc_length
R/W
R/W
IEEE 1394 bus management field. Must be valid at any time the linkEnable bit (bit 17) of the host
controller control register (offset 50h/54h, see Section 9.16) is set. The reset value is undefined if no
serial ROM is present. If a serial ROM is present, then this field is loaded from the serial ROM.
rom_crc_value
9.8 Bus Identification Register
This register externally maps to the first quadlet in the Bus_Info_Block, and contains the constant 3133 3934h, which
is the ASCII value of 1394.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Bus identification
R
0
R
0
R
1
R
1
R
0
R
0
R
0
9
R
1
8
R
0
7
R
0
6
R
1
5
R
1
4
R
0
3
R
0
2
R
1
1
R
1
0
15
14
13
12
11
10
Name
Type
Default
Bus identification
R
0
R
0
R
1
R
1
R
1
R
0
R
0
R
1
R
0
R
0
R
1
R
1
R
0
R
1
R
0
R
0
Register:
Type:
Bus identification
Read-only
Offset:
Default:
1Ch
3133 3934h
9–8
9.9 Bus Options Register
This register externally maps to the second quadlet of the Bus_Info_Block. See Table 9–7 for a complete description
of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Bus options
R/W
X
R/W
X
R/W
X
R/W
X
R/W
0
R
0
R
0
9
R
0
8
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
15
14
13
12
11
10
7
6
5
4
3
2
1
0
Name
Type
Default
Bus options
R/W
1
R/W
0
R/W
1
R/W
0
R
0
R
0
R
0
R
0
R/W
X
R/W
X
R
0
R
0
R
0
R
0
R
1
R
0
Register:
Type:
Offset:
Default:
Bus options
Read-only, Read/Write
20h
X0XX A0X2h
Table 9–7. Bus Options Register Description
BIT
SIGNAL
TYPE
FUNCTION
Isochronous resource manager capable. IEEE 1394 bus management field. Must be valid when the
linkEnable bit (bit 17) of the host controller control register (offset 50h/54h, see Section 9.16) is set.
31
irmc
R/W
Cycle master capable. IEEE 1394 bus management field. Must be valid when the linkEnable bit (bit 17)
of the host controller control register (offset 50h/54h, see Section 9.16) is set.
30
29
28
cmc
isc
R/W
R/W
R/W
Isochronous support capable. IEEE 1394 bus management field. Must be valid when the linkEnable bit
(bit 17) of the host controller control register (offset 50h/54h, see Section 9.16) is set.
Bus manager capable. IEEE 1394 bus management field. Must be valid when the linkEnable bit (bit 17)
of the host controller control register (offset 50h/54h, see Section 9.16) is set.
bmc
IEEE 1394 bus management field. Must be valid when the linkEnable bit (bit 17) of the host controller
control register (offset 50h/54h, see Section 9.16) is set.
27
pmc
RSVD
R/W
R
26–24
23–16
Reserved. These bits return 0s when read.
Cycle master clock accuracy, in parts per million. IEEE 1394 bus management field. Must be valid when
the linkEnable bit (bit 17) of the host controller control register (offset 50h/54h, see Section 9.16) is set.
cyc_clk_acc
R/W
IEEE 1394 bus management field. Hardware shall initialize max_rec to indicate the maximum number
of bytes in a block request packet that is supported by the implementation. This value, max_rec_bytes
must be 512 or greater, and is calculated by 2^(max_rec + 1). Software may change max_rec; however,
this field must be valid at any time the linkEnable bit (bit 17) of the host controller control register (offset
50h/54h, see Section 9.16) is set. A received block write request packet with a length greater than
max_rec_bytes may generate an ack_type_error. This field is not affected by a soft reset, and defaults
to value indicating 2048 bytes on hard reset.
15–12
max_rec
R/W
11–8
7–6
5–3
2–0
RSVD
g
R
R/W
R
Reserved. These bits return 0s when read.
Generation counter. This field shall be incremented is any portion the configuration ROM has incremented
since the prior bus reset.
RSVD
Lnk_spd
Reserved. These bits return 0s when read.
Link speed. This field returns 010, indicating that the link speeds of 100, 200 and 400 Mbits/s are
supported.
R
9–9
9.10 Global Unique ID High Register
This register represents the upper quadlet in a 64-bit global unique ID (GUID) which maps to the third quadlet in the
Bus_Info_Block. This register contains node_vendor_ID and chip_ID_hi fields. This register initializes to 0s on a
hardware reset, which is an illegal GUID value. If a serial ROM is detected, then the contents of this register are loaded
through the serial ROM interface after a PCI reset. At that point, the contents of this register cannot be changed. If
no serial ROM is detected, then this register may be written once to set the value of this register. At that point, the
contents of this register cannot be changed.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Global unique ID high
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Global unique ID high
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Global Unique ID high
Read-only
Offset:
Default:
24h
0000 0000h
9.11 Global Unique ID Low Register
This register represents the lower quadlet in a 64-bit global unique ID (GUID) which maps to chip_ID_lo in the
Bus_Info_Block. This register initializes to 0s on a hardware reset, and behaves identically to the GUID high register.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Global unique ID low
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Global unique ID low
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Global Unique ID low
Read-only
Offset:
Default:
28h
0000 0000h
9–10
9.12 Configuration ROM Mapping Register
This register contains the start address within system memory that will map to the start address of 1394 configuration
ROM for this node. See Table 9–8 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Configuration ROM mapping
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Configuration ROM mapping
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
Configuration ROM mapping
Read-only, Read/Write
34h
0000 0000h
Table 9–8. Configuration ROM Mapping Register Description
BIT
31–10
9–0
SIGNAL
configROMaddr
RSVD
TYPE
R/W
R
FUNCTION
If a quadlet read request to 1394 offset FFFF F000 0400h through offset FFFF F000 07FFh
is received, then the low-order 10 bits of the offset are added to this register to determine the host
memory address of the read request.
Reserved. These bits return 0s when read.
9.13 Posted Write Address Low Register
This register is used to communicate error information if a write request is posted and an error occurs while writing
the posted data packet. See Table 9–9 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Posted write address low
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Posted write address low
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
Register:
Type:
Offset:
Default:
Posted write address low
Read/Update
38h
XXXX XXXXh
Table 9–9. Posted Write Address Low Register Description
BIT
SIGNAL
TYPE
FUNCTION
The lower 32 bits of the 1394 destination offset of the write request that failed.
31–0
offsetLo
RU
9–11
9.14 Posted Write Address High Register
This register is used to communicate error information if a write request is posted and an error occurs while writing
the posted data packet. See Table 9–10 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Posted write address high
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Posted write address high
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
Register:
Type:
Posted write address high
Read/Update
Offset:
Default:
3Ch
XXXX XXXXh
Table 9–10. Posted Write Address High Register Description
BIT
31–16
15–0
SIGNAL
sourceID
offsetHi
TYPE
RU
FUNCTION
This bus and node number of the node that issued the write request that failed.
The upper 16 bits of the 1394 destination offset of the write request that failed.
RU
9.15 Vendor ID Register
The vendor ID register holds the company ID of an organization that specifies any vendor-unique registers. The
PCI4451 does not implement Texas Instruments unique behavior with regards to Open HCI. Thus this register is
read-only and returns 0s when read.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Vendor ID
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Vendor ID
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
Vendor ID
Read-only
40h
0000 0000h
9–12
9.16 Host Controller Control Register
This set/clear register pair provides flags for controlling the PCI4451 link function. See Table 9–11 for a complete
description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Host controller control
RSC
0
R
X
R
0
R
0
R
0
R
0
R
0
9
R
0
8
RC
0
RSC
R
0
5
R
0
4
RSC
RSC
X
RSC RSCU
0
0
0
0
15
14
13
12
11
10
7
6
3
2
1
0
Name
Type
Default
Host controller control
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Host controller control
Read/Set/Clear/Update, Read/Set/Clear, Read/Clear, Read-only
Offset:
50h
54h
set register
clear register
Default:
X00X 0000h
Table 9–11. Host Controller Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
Reserved. These bits return 0s when read.
31
RSVD
noByteSwapData
RSVD
R
This bit is used to control whether physical accesses to locations outside the PCI4451 itself as
well as any other DMA data accesses should be swapped.
30
RSC
R
29–24
Reserved. These bits return 0s when read.
This bit informs upper level software that lower level software has consistently configured the
p1394a enhancements in the link and PHY. When 1, generic software such as the OHCI driver
is responsible for configuring p1394a enhancements in the PHY and the aPhyEnhanceEnable
bit in the PCI4451. When 0, the generic software may not modify the p1394a enhancements in
the PCI4451 or PHY and cannot interpret the setting of aPhyEnhanceEnable. This bit can
be initialized from serial EEPROM.
23
22
programPhyEnable
RC
When the programPhyenable is 1 and linkEnable is 1, the OHCI driver can set this bit to use all
p1394a enhancements. When programPhyEnable is set 0, the software will not change PHY
enhancements or the aPhyEnhanceEnable bit.
aPhyEnhanceEnable
RSC
21–20
RSVD
LPS
R
Reserved. These bits return 0s when read.
This bit is used to control the link power status. Software must set LPS to 1 to permit the link-PHY
communication. A 0 prevents link-PHY communication.
19
RSC
This bit is used to enable (1) or disable (0) posted writes. Software should change this bit only
when linkEnable is 0.
18
17
postedWriteEnable
linkEnable
RSC
RSC
This bit is cleared to 0 by a hardware reset or software reset. Software must set this bit to 1 when
the system is ready to begin operation and then force a bus reset. This bit is necessary to keep
other nodes from sending transactions before the local system is ready. When this bit is clear
the PCI4451 is logically and immediately disconnected from the 1394 bus; no packets will
be received or processed nor will packets be transmitted.
When set to 1, the PCI4451 state is reset, all FIFO’s are flushed, and all OHCI registers are set
to their hardware reset values unless otherwise specified. PCI registers are not affected by this
bit. This bit remains set to 1 while the softReset is in progress and reverts back to 0 when the reset
has completed.
16
SoftReset
RSVD
RSCU
R
15–0
Reserved. These bits return 0s when read.
9–13
9.17 Self ID Buffer Pointer Register
This register points to the 2-Kbyte aligned base address of the buffer in host memory where the self ID packets will
be stored during bus initialization. Bits 31–11 are read/write accessible.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Self ID buffer pointer
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Self ID buffer pointer
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R
X
R
X
R
X
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
Self ID buffer pointer
Read-only, Read/Write
64h
XXXX XX00h
9.18 Self ID Count Register
This register keeps a count of the number of times the bus self ID process has occurred, flags self ID packet errors,
and keeps a count of the amount of self ID data in the self ID buffer. See Table 9–12 for a complete description of
the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Self ID count
RU
X
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
15
14
13
12
11
10
7
6
5
4
3
2
1
0
Name
Type
Default
Self ID count
R
0
R
0
R
0
R
0
R
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
RU
0
R
0
R
0
Register:
Type:
Offset:
Default:
Self ID count
Read/Update, Read-only
68h
X0XX 0000h
Table 9–12. Self ID Count Register Description
BIT
SIGNAL
TYPE
FUNCTION
When this bit is 1, an error was detected during the most recent self ID packet reception. The contents
of the self ID buffer are undefined. This bit is cleared after a self ID reception in which no errors are
detected. Note that an error can be a hardware error or a host bus write error.
31
selfIDError
RU
30–24
23–16
15–11
RSVD
selfIDGeneration
RSVD
R
RU
R
Reserved. These bits return 0s when read.
The value in this field increments each time a bus reset is detected. This field rolls over to 0 after
reaching 255.
Reserved. These bits return 0s when read.
This field indicates the number of quadlets that have been written into the self ID buffer for the current
selfIDGeneration. This includes the header quadlet and the self ID data. This field is cleared to 0
when the self ID reception begins.
10–2
1–0
selfIDSize
RSVD
RU
R
Reserved. These bits return 0s when read.
9–14
9.19 Isochronous Receive Channel Mask High Register
This set/clear register is used to enable packet receives from the upper 32 isochronous data channels. A read from
either the set register or clear register returns the value of the IRChannelMaskHi register. See Table 9–13 for a
complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Isochronous receive channel mask high
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Isochronous receive channel mask high
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
Register:
Type:
Isochronous receive channel mask high
Read/Set/Clear
Offset:
70h
74h
set register
clear register
Default:
XXXX XXXXh
Table 9–13. Isochronous Receive Channel Mask High Register Description
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
SIGNAL
TYPE
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
FUNCTION
isoChannel63
isoChannel62
isoChannel61
isoChannel60
isoChannel59
isoChannel58
isoChannel57
isoChannel56
isoChannel55
isoChannel54
isoChannel53
isoChannel52
isoChannel51
isoChannel50
isoChannel49
isoChannel48
isoChannel47
isoChannel46
isoChannel45
isoChannel44
isoChannel43
isoChannel42
isoChannel41
isoChannel40
When set, the PCI4451 is enabled to receive from iso channel number 63.
When set, the PCI4451 is enabled to receive from iso channel number 62.
When set, the PCI4451 is enabled to receive from iso channel number 61.
When set, the PCI4451 is enabled to receive from iso channel number 60.
When set, the PCI4451 is enabled to receive from iso channel number 59.
When set, the PCI4451 is enabled to receive from iso channel number 58.
When set, the PCI4451 is enabled to receive from iso channel number 57.
When set, the PCI4451 is enabled to receive from iso channel number 56.
When set, the PCI4451 is enabled to receive from iso channel number 55.
When set, the PCI4451 is enabled to receive from iso channel number 54.
When set, the PCI4451 is enabled to receive from iso channel number 53.
When set, the PCI4451 is enabled to receive from iso channel number 52.
When set, the PCI4451 is enabled to receive from iso channel number 51.
When set, the PCI4451 is enabled to receive from iso channel number 50.
When set, the PCI4451 is enabled to receive from iso channel number 49.
When set, the PCI4451 is enabled to receive from iso channel number 48.
When set, the PCI4451 is enabled to receive from iso channel number 47.
When set, the PCI4451 is enabled to receive from iso channel number 46.
When set, the PCI4451 is enabled to receive from iso channel number 45.
When set, the PCI4451 is enabled to receive from iso channel number 44.
When set, the PCI4451 is enabled to receive from iso channel number 43.
When set, the PCI4451 is enabled to receive from iso channel number 42.
When set, the PCI4451 is enabled to receive from iso channel number 41.
When set, the PCI4451 is enabled to receive from iso channel number 40.
8
9–15
Table 9–13. Isochronous Receive Channel Mask High Register Description (Continued)
BIT
7
SIGNAL
TYPE
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
FUNCTION
isoChannel39
isoChannel38
isoChannel37
isoChannel36
isoChannel35
isoChannel34
isoChannel33
isoChannel32
When set, the PCI4451 is enabled to receive from iso channel number 39.
When set, the PCI4451 is enabled to receive from iso channel number 38.
When set, the PCI4451 is enabled to receive from iso channel number 37.
When set, the PCI4451 is enabled to receive from iso channel number 36.
When set, the PCI4451 is enabled to receive from iso channel number 35.
When set, the PCI4451 is enabled to receive from iso channel number 34.
When set, the PCI4451 is enabled to receive from iso channel number 33.
When set, the PCI4451 is enabled to receive from iso channel number 32.
6
5
4
3
2
1
0
9.20 Isochronous Receive Channel Mask Low Register
This set/clear register is used to enable packet receives from the lower 32 isochronous data channels. See
Table 9–14 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Isochronous receive channel mask low
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Isochronous receive channel mask low
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
Register:
Type:
Isochronous receive channel mask low
Read/Set/Clear
Offset:
78h
7Ch
set register
clear register
Default:
XXXX XXXXh
Table 9–14. Isochronous Receive Channel Mask Low Register Descriptions
BIT
31
30
L
SIGNAL
isoChannel31
isoChannel30
L
TYPE
RSC
RSC
L
FUNCTION
When set, the PCI4451 is enabled to receive from iso channel number 31.
When set, the PCI4451 is enabled to receive from iso channel number 30.
Bits 29 through 2 follow the same pattern.
1
isoChannel1
isoChannel0
RSC
RSC
When set, the PCI4451 is enabled to receive from iso channel number 1.
When set, the PCI4451 is enabled to receive from iso channel number 0.
0
9–16
9.21 Interrupt Event Register
This set/clear register reflects the state of the various PCI4451 interrupt sources. The interrupt bits are set by an
asserting edge of the corresponding interrupt signal, or by writing a 1 in the corresponding bit in the set register. The
only mechanism to clear the bits in this register is to write a 1 to the corresponding bit in the clear register. See
Table 9–15 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
Interrupt event
RSCU RSCU RSCU RSCU RSCU RSCU RSCU RSCU
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
R
0
R
X
R
0
R
0
R
0
R
0
2
RSCU RSCU
X
X
X
X
X
X
X
X
X
X
15
14
13
12
11
10
9
8
7
6
5
4
3
1
0
Name
Type
Default
Interrupt event
R
0
R
0
R
0
R
0
R
0
R
0
RSCU RSCU
RU
X
RU
X
RSCU RSCU RSCU RSCU RSCU RSCU
X
X
X
X
X
X
X
X
Register:
Type:
Interrupt event
Read/Set/Clear/Update, Read/Update, Read-only
Offset:
80h
84h
set register
clear register [returns IntEvent and IntMask when read]
Default:
XXXX 0XXXh
Table 9–15. Interrupt Event Register Description
BIT
31
SIGNAL
RSVD
TYPE
FUNCTION
R
R
R
Reserved. This bit returns 0 when read.
Vendor defined.
30
vendorSpecific
RSVD
29–27
26
Reserved. These bits return 0s when read.
phyRegRcvd
RSCU The PCI4451 has received a PHY register data byte which can be read from the PHY control register.
If the cycleMaster bit (bit 21) of the link control register (offset E0h/E4h, see Section 9.28) is set, this
RSCU indicates that over 125 µs elapsed between the start of sending a cycle start packet and the end of
a subaction gap. The cycleMaster bit is cleared by this event.
25
24
23
cycleTooLong
This event occurs when the PCI4451 encounters any error that forces it to stop operations on any or
unrecoverableError RSCU all of its subunits for example, when a DMA context sets its dead bit. While unrecoverableError is set,
all normal interrupts for the context(s) that caused this interrupt will be blocked from being set.
A cycle start was received that had cycleSeconds (bits 31–25) and cycleCount (bits 24–12) of the
RSCU isochronous cycle timer register (offset F0h, see Section 9.31) different from the value in the
CycleTimer register.
cycleInconsistent
A lost cycle is indicated when no cycle_start packet is sent/received between two successive
cycleSynch events. A lost cycle can be predicted when a cycle_start packet does not immediately
follow the first subaction gap after the cycleSynch event or if an arbitration reset gap is detected after
a cycleSynch event without an intervening cycle start. CycleLost may be set either when a lost cycle
occurs or when logic predicts that one will occur.
22
cycleLost
RSCU
th
21
20
cycle64Seconds
cycleSynch
RSCU Indicates that the 7 bit of the cycle second counter has changed.
Indicates that a new isochronous cycle has started and is set when the low order bit of the cycle count
RSCU
toggles.
19
18
17
phy
RSCU Indicates the PHY requests an interrupt through a status transfer.
RSVD
R
Reserved. These bits return 0s when read.
busReset
RSCU Indicates that the PHY chip has entered bus reset mode.
A selfID packet stream has been received. It will be generated at the end of the bus initialization
process. This bit is turned off simultaneously when busReset (bit 17) is turned on.
16
15–10
9
selfDcomplete
RSVD
RSCU
R
Reserved. These bits return 0s when read.
Indicates that the PCI4451 sent a lock response for a lock request to a serial bus register, but did not
receive an ack_complete.
lockRespErr
RSCU
9–17
Table 9–15. Interrupt Event Register Description (Continued)
BIT
SIGNAL
TYPE
FUNCTION
Indicates that a host bus error occurred while the PCI4451 was trying to write a 1394 write request,
which had already been given an ack_complete, into system memory.
8
postedWriteErr
RSCU
Isochronous receive DMA interrupt. Indicates that one or more isochronous receive contexts have
generated an interrupt. This is not a latched event, it is the ORing of all bits in the isochronous receive
interrupt event (offset A0h/A4h, see Section 9.25) and isochronous receive interrupt mask (offset
A8h/ACh, see Section 9.26) registers. The isochronous receive interrupt event register indicates
which contexts have interrupted.
7
6
isochRx
iscohTx
RU
RU
Isochronous transmit DMA interrupt. Indicates that one or more isochronous transmit contexts have
generated an interrupt. This is not a latched event, it is the ORing of all bits in the isochronous transmit
interrupt event (offset 90h/94h, see Section 9.23) and isochronous transmit interrupt mask (offset
98h/9Ch, see Section 9.24) registers. The isochronous transmit interrupt event register indicates
which contexts have interrupted.
Indicates that a packet was sent to an asynchronous receive response context buffer and the
descriptor xferStatus and resCount fields have been updated.
5
4
3
2
1
0
RSPkt
RQPkt
RSCU
RSCU
RSCU
RSCU
RSCU
RSCU
Indicates that a packet was sent to an asynchronous receive request context buffer and the descriptor
xferStatus and resCount fields have been updated.
Async receive response DMA interrupt. This bit is conditionally set upon completion of an ARRS
context command descriptor.
ARRS
Async receive request DMA interrupt. This bit is conditionally set upon completion of an ARRQ DMA
context command descriptor.
ARRQ
Asynchronous response transmit DMA interrupt. This bit is conditionally set upon completion of an
ATRS DMA command.
respTxComplete
reqTxComplete
Asynchronous request transmit DMA interrupt. This bit is conditionally set upon completion of an
ATRQ DMA command.
9.22 Interrupt Mask Register
This set/clear register is used to enable the various PCI4451 interrupt sources. Reads from either the set register or
the clear register always return IntMask. In all cases except masterIntEnable (bit 31), the enables for each interrupt
event align with the event register bits detailed in Table 9–15. See Table 9–16 for a description of bit 31.
Bit
31
30
29
28
27
26
25
24
Interrupt mask
RSCU RSCU RSCU RSCU RSCU RSCU RSCU RSCU
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
RSC
0
R
X
R
0
R
0
R
0
R
0
2
RSCU RSCU
X
X
X
X
X
X
X
X
X
X
15
14
13
12
11
10
9
8
7
6
5
4
3
1
0
Name
Type
Default
Interrupt mask
R
0
R
0
R
0
R
0
R
0
R
0
RSCU RSCU
RU
X
RU
X
RSCU RSCU RSCU RSCU RSCU RSCU
X
X
X
X
X
X
X
X
Register:
Type:
Interrupt mask
Read/Set/Clear
Offset:
88h
8Ch
set register
clear register
Default:
XXXX 0XXXh
Table 9–16. Interrupt Mask Register Description
BIT
31
SIGNAL
TYPE
FUNCTION
When set, external interrupts will be generated in accordance with the IntMask register. If clear, no
external interrupts will be generated.
masterIntEnable
RSC
30–0
See Table 9–15.
9–18
9.23 Isochronous Transmit Interrupt Event Register
This set/clear register reflects the interrupt state of the isochronous transmit contexts. An interrupt is generated on
behalf of an isochronous transmit context if an OUTPUT_LAST command completes and its interrupt bits are set.
Upon determining an interrupt has occurred that set the isochTx bit (bit 6) in the interrupt event register (offset
80h/84h, see Section 9.21), software can check this register to determine which context(s) caused the interrupt. The
interrupt bits are set by an asserting edge of the corresponding interrupt signal, or by writing a 1 in the corresponding
bit in the set register. The only mechanism to clear the bits in this register is to write a 1 to the corresponding bit in
the clear register. See Table 9–17 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Isochronous transmit interrupt event
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Isochronous transmit interrupt event
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
Register:
Type:
Isochronous transmit interrupt event
Read/Set/Clear, Read-only
Offset:
90h
94h
set register
clear register [returns IsoXmitEvent and IsoXmitMask when read]
Default:
0000 00XXh
Table 9–17. Isochronous Transmit Interrupt Event Register Description
BIT
SIGNAL
RSVD
TYPE
R
FUNCTION
31–8
Reserved. These bits return 0s when read.
7
6
5
4
3
2
1
0
isoXmit7
isoXmit6
isoXmit5
isoXmit4
isoXmit3
isoXmit2
isoXmit1
isoXmit0
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
Isochronous transmit channel 7 caused the isochTx interrupt.
Isochronous transmit channel 6 caused the isochTx interrupt.
Isochronous transmit channel 5 caused the isochTx interrupt.
Isochronous transmit channel 4 caused the isochTx interrupt.
Isochronous transmit channel 3 caused the isochTx interrupt.
Isochronous transmit channel 2 caused the isochTx interrupt.
Isochronous transmit channel 1 caused the isochTx interrupt.
Isochronous transmit channel 0 caused the isochTx interrupt.
9–19
9.24 Isochronous Transmit Interrupt Mask Register
This set/clear register is used to enable the isochTx interrupt source on a per-channel basis. Reads from either the
set register or the clear register always return IsoXmitIntMask. In all cases the enables for each interrupt event align
with the event register bits detailed in Table 9–17.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Isochronous transmit interrupt mask
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Isochronous transmit interrupt mask
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
Register:
Type:
Isochronous transmit interrupt mask
Read/Set/Clear
Offset:
98h
9Ch
set register
clear register
Default:
0000 00XXh
9.25 Isochronous Receive Interrupt Event Register
This set/clear register reflects the interrupt state of the isochronous receive contexts. An interrupt is generated on
behalf of an isochronous receive context if an INPUT_* command completes and its interrupt bits are set. Upon
determining an interrupt has occurred that set the isochRx bit (bit 7) in the interrupt event register (offset 80h/84h,
see Section 9.21), software can check this register to determine which context(s) caused the interrupt. The interrupt
bits are set by an asserting edge of the corresponding interrupt signal, or by writing a 1 in the corresponding bit in
the set register. The only mechanism to clear the bits in this register is to write a 1 to the corresponding bit in the clear
register. See Table 9–18 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Isochronous receive interrupt event
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Isochronous receive interrupt event
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
RSC
X
RSC
X
RSC
X
RSC
X
Register:
Type:
Isochronous receive interrupt event
Read/Set/Clear, Read-only
Offset:
A0h
A4h
set register
clear register [returns IsoRecvEvent and IsoRecvMask when read]
Default:
0000 000Xh
Table 9–18. Isochronous Receive Interrupt Event Register Description
BIT
SIGNAL
RSVD
TYPE
R
FUNCTION
31–4
Reserved. These bits return 0s when read.
3
2
1
0
isoRecv3
isoRecv2
isoRecv1
isoRecv0
RSC
RSC
RSC
RSC
Isochronous receive channel 3 caused the isochRx interrupt.
Isochronous receive channel 2 caused the isochRx interrupt.
Isochronous receive channel 1 caused the isochRx interrupt.
Isochronous receive channel 0 caused the isochRx interrupt.
9–20
9.26 Isochronous Receive Interrupt Mask Register
This set/clear register is used to enable the isochRx interrupt source on a per channel basis. Reads from either the
set register or the clear register always return IsoRecvIntMask. In all cases the enables for each interrupt event align
with the event register bits detailed in Table 9–18.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Isochronous receive interrupt mask
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Isochronous receive interrupt mask
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
RSC
X
RSC
X
RSC
X
RSC
X
Register:
Type:
Isochronous receive interrupt mask
Read/Set/Clear, Read-only
Offset:
A8h
ACh
set register
clear register
Default:
0000 000Xh
9.27 Fairness Control Register (Optional Register)
This register provides a mechanism by which software can direct the host controller to transmit multiple asynchronous
requests during a fairness interval. See Table 9–19 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Fairness control
R
X
R
X
R
X
R
X
R
X
R
X
R
X
9
R
X
8
R
X
7
R
X
6
R
X
5
R
X
4
R
X
3
R
X
2
R
X
1
R
X
0
15
14
13
12
11
10
Name
Type
Default
Fairness control
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Fairness control
Read-only
Offset:
Default:
DCh
XXXX XX00h
Table 9–19. Fairness Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
31–8
RSVD
R
Reserved.
This field specifies the maximum number of priority arbitration requests for asynchronous request
packets that the link is permitted to make of the PHY during fairness interval.
7–0
pri_req
R
9–21
9.28 Link Control Register
This set/clear register provides the control flags that enable and configure the link core protocol portions of the
PCI4451. It contains controls for the receiver and cycle timer. See Table 9–20 for a complete description of the register
contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Link control
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
R
0
7
RSC RSCU RSC
R
0
3
R
0
2
R
0
1
R
0
0
0
X
X
X
15
14
13
12
11
10
8
6
5
4
Name
Type
Default
Link control
R
0
R
0
R
0
R
0
R
0
RSC
X
RSC
X
R
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
0
Register:
Type:
Link control
Read/Set/Clear/Update, Read/Set/Clear, Read-only
Offset:
E0h
E4h
set register
clear register
Default:
00X0 0X00h
Table 9–20. Link Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
Reserved. These bits return 0s when read.
31–23
RSVD
R
When 1, the cycle timer will use an external source (CYCLEIN) to determine when to roll over the
cycle timer. When 0, the cycle timer rolls over when the timer reaches 3072 cycles of the
24.576-MHz clock (125 µs).
22
21
20
cycleSource
RSC
When set, and the PHY has notified the PCI4451 that it is root, the PCI4451 will generate a cycle
start packet every time the cycle timer rolls over, based on the setting of the cycleSource bit.
When 0, the OHIC-Lynx will accept received cycle start packets to maintain synchronization with
the node which is sending them. This bit is automatically reset when the cycleTooLong event
occurs and cannot be set until the cycleTooLong bit (bit 25) of the interrupt event register (offset
80h/84h, see Section 9.21) is cleared.
cycleMaster
RSCU
RSC
When 1, the cycle timer offset will count cycles of the 24.576-MHz clock and roll over at the
appropriate time based on the settings of the above bits. When 0, the cycle timer offset will not
count.
CycleTimerEnable
19–11
RSVD
R
Reserved. These bits return 0s when read.
When 1, the receiver will accept incoming PHY packets into the AR request context if the
AR request context is enabled. This does not control receipt of self-identification packets.
10
RcvPhyPkt
RSC
When 1, the receiver will accept incoming self-identification packets. Before setting this bit to 1,
software must ensure that the self ID buffer pointer register contains a valid address.
9
RcvSelfID
RSVD
RSC
R
8–0
Reserved. These bits return 0s when read.
9–22
9.29 Node Identification Register
This register contains the address of the node on which the OHIC-Lynx chip resides, and indicates the valid node
number status. The 16-bit combination of busNumber and NodeNumber is referred to as the node ID. See Table 9–21
for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Node identification
RU
0
RU
0
R
0
R
0
RU
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Node identification
RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
1
1
1
1
1
1
1
1
1
1
Register:
Type:
Node identification
Read/Write/Update, Read/Update, Read-only
Offset:
Default:
E8h
0000 11XXh
Table 9–21. Node Identification Register Description
BIT
SIGNAL
TYPE
FUNCTION
This bit indicates whether or not the PCI4451 has a valid node number. It is cleared when a 1394 bus
reset is detected and set when the PCI4451 receives a new node number from the PHY.
31
iDValid
RU
30
root
RSVD
CPS
RU
R
This bit is set during the bus reset process if the attached PHY is root.
Reserved. These bits return 0s when read.
29–28
27
RU
R
Set if the PHY is reporting that cable power status is OK (VP 8V).
Reserved. These bits return 0s when read.
26–16
RSVD
This number is used to identify the specific 1394 bus the PCI4451 belongs to when multiple
1394-compatiable buses are connected via a bridge.
15–6
5–0
busNumber
RWU
This number is the physical node number established by the PHY during self-identification. It is
automatically set to the value received from the PHY after the self-identification phase. If the PHY
sets the nodeNumber to 63, software should not set the run bit (bit 15) of the asynchronous context
control register (see Section 9.37) for either the ATRQ (offset 180h/184h) or ATRS (offset 1A0h/1A4h)
DMA context.
NodeNumber
RU
9–23
9.30 PHY Control Register
This register is used to read or write a PHY register. See Table 9–22 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
PHY control
RU
X
R
0
R
0
R
0
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
PHY control
RWU RWU
R
0
R
0
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
0
0
Register:
Type:
PHY control
Read/Write/Update, Read/Update, Read-only
Offset:
Default:
ECh
XXXX 0XXXh
Table 9–22. PHY Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
This bit is cleared to 0 by the PCI4451 when either rdReg or wrReg is set to 1. This bit is set to 1 when
a register transfer is received from the PHY.
31
rdDone
RU
30–28
27–24
23–16
RSVD
rdAddr
rdData
R
Reserved. These bits return 0s when read.
RU
RU
This is the address of the register most recently received from the PHY.
This field is the contents of a PHY register which has been read.
This bit is set by software to initiate a read request to a PHY register, and is cleared by hardware
when the request has been sent. The wrReg and rdReg bits must be used exclusively.
15
14
rdReg
wrReg
RWU
RWU
This bit is set by software to initiate a write request to a PHY register, and is cleared by hardware
when the request has been sent. The wrReg and rdReg bits must be used exclusively.
13–12
11–8
7–0
RSVD
regAddr
wrData
R
Reserved. These bits return 0s when read.
R/W
R/W
This field is the address of the PHY register to be written or read.
This field is the data to be written to a PHY register, and is ignored for reads.
9–24
9.31 Isochronous Cycle Timer Register
This read/write register indicates the current cycle number and offset. When the PCI4451 is cycle master, this register
is transmitted with the cycle start message. When the PCI4451 is not cycle master, this register is loaded with the
data field in an incoming cycle start. In the event that the cycle start message is not received, the fields can continue
incrementing on their own (if programmed) to maintain a local time reference. See Table 9–23 for a complete
description of the register contents.
Bit
31
30
29
28
27
26
25
Isochronous cycle timer
RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Isochronous cycle timer
RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Register:
Type:
Offset:
Default:
Isochronous cycle timer
Read/Write/Update
F0h
XXXX XXXXh
Table 9–23. Isochronous Cycle Timer Register Description
BIT
SIGNAL
cycleSeconds
cycleCount
TYPE
RWU
RWU
FUNCTION
This field counts seconds (cycleCount rollovers) modulo 128.
This field counts cycles (cycleOffset rollovers) modulo 8000.
31–25
24–12
This field counts 24.576-MHz clocks modulo 3072, i.e., 125 µs. If an external 8-kHz clock configuration
is being used, then cycleOffset must be set to 0 at each tick of the external clock.
11–0
cycleOffset
RWU
9–25
9.32 Asynchronous Request Filter High Register
This set/clear register is used to enable asynchronous receive requests on a per-node basis, and handles the upper
node IDs. When a packet is destined for either the physical request context or the ARRQ context, the source node
ID is examined. If the bit corresponding to the node ID is not set in this register, then the packet is not acknowledged
and the request is not queued. The node ID comparison is done if the source node is on the same bus as the PCI4451.
Nonlocal bus sourced packets are not acknowledged unless bit 31 in this register is set. See Table 9–24 for a
complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Asynchronous request filter high
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Asynchronous request filter high
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
Register:
Type:
Asynchronous request filter high
Read/Set/Clear
Offset:
100h set register
104h clear register
0000 0000h
Default:
Table 9–24. Asynchronous Request Filter High Register Description
BIT
SIGNAL
TYPE
FUNCTION
If set to 1, all asynchronous requests received by the PCI4451 from nonlocal bus nodes will be
accepted.
31
asynReqAllBuses
asynReqResource62
asynReqResource61
asynReqResource60
asynReqResource59
asynReqResource58
asynReqResource57
asynReqResource56
asynReqResource55
asynReqResource54
asynReqResource53
asynReqResource52
RSC
If set to 1 for local bus node number 62, asynchronous requests received by the PCI4451 from that
node will be accepted.
30
29
28
27
26
25
24
23
22
21
20
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
If set to 1 for local bus node number 61, asynchronous requests received by the PCI4451 from that
node will be accepted.
If set to 1 for local bus node number 60, asynchronous requests received by the PCI4451 from that
node will be accepted.
If set to 1 for local bus node number 59, asynchronous requests received by the PCI4451 from that
node will be accepted.
If set to 1 for local bus node number 58, asynchronous requests received by the PCI4451 from that
node will be accepted.
If set to 1 for local bus node number 57, asynchronous requests received by the PCI4451 from that
node will be accepted.
If set to 1 for local bus node number 56, asynchronous requests received by the PCI4451 from that
node will be accepted.
If set to 1 for local bus node number 55, asynchronous requests received by the PCI4451 from that
node will be accepted.
If set to 1 for local bus node number 54, asynchronous requests received by the PCI4451 from that
node will be accepted.
If set to 1 for local bus node number 53, asynchronous requests received by the PCI4451 from that
node will be accepted.
If set to 1 for local bus node number 52, asynchronous requests received by the PCI4451 from that
node will be accepted.
9–26
Table 9–24. Asynchronous Request Filter High Register Description (Continued)
BIT
SIGNAL
TYPE
FUNCTION
If set to 1 for local bus node number 51, asynchronous requests received by the PCI4451 from that
node will be accepted.
19
asynReqResource51
RSC
If set to 1 for local bus node number 50, asynchronous requests received by the PCI4451 from that
node will be accepted.
18
17
16
15
14
13
12
11
10
9
asynReqResource50
asynReqResource49
asynReqResource48
asynReqResource47
asynReqResource46
asynReqResource45
asynReqResource44
asynReqResource43
asynReqResource42
asynReqResource41
asynReqResource40
asynReqResource39
asynReqResource38
asynReqResource37
asynReqResource36
asynReqResource35
asynReqResource34
asynReqResource33
asynReqResource32
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
If set to 1 for local bus node number 49, asynchronous requests received by the PCI4451 from that
node will be accepted.
If set to 1 for local bus node number 48, asynchronous requests received by the PCI4451 from that
node will be accepted.
If set to 1 for local bus node number 47, asynchronous requests received by the PCI4451 from that
node will be accepted.
If set to 1 for local bus node number 46, asynchronous requests received by the PCI4451 from that
node will be accepted.
If set to 1 for local bus node number 45, asynchronous requests received by the PCI4451 from that
node will be accepted.
If set to 1 for local bus node number 44, asynchronous requests received by the PCI4451 from that
node will be accepted.
If set to 1 for local bus node number 43, asynchronous requests received by the PCI4451 from that
node will be accepted.
If set to 1 for local bus node number 42, asynchronous requests received by the PCI4451 from that
node will be accepted.
If set to 1 for local bus node number 41, asynchronous requests received by the PCI4451 from that
node will be accepted.
If set to 1 for local bus node number 40, asynchronous requests received by the PCI4451 from that
node will be accepted.
8
If set to 1 for local bus node number 39, asynchronous requests received by the PCI4451 from that
node will be accepted.
7
If set to 1 for local bus node number 38, asynchronous requests received by the PCI4451 from that
node will be accepted.
6
If set to 1 for local bus node number 37, asynchronous requests received by the PCI4451 from that
node will be accepted.
5
If set to 1 for local bus node number 36, asynchronous requests received by the PCI4451 from that
node will be accepted.
4
If set to 1 for local bus node number 35, asynchronous requests received by the PCI4451 from that
node will be accepted.
3
If set to 1 for local bus node number 34, asynchronous requests received by the PCI4451 from that
node will be accepted.
2
If set to 1 for local bus node number 33, asynchronous requests received by the PCI4451 from that
node will be accepted.
1
If set to 1 for local bus node number 32, asynchronous requests received by the PCI4451 from that
node will be accepted.
0
9–27
9.33 Asynchronous Request Filter Low Register
This set/clear register is used to enable asynchronous receive requests on a per-node basis, and handles the lower
node IDs. Other than filtering different node IDs, this register behaves identically to the asynchronous request filter
high register. See Table 9–25 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Asynchronous request filter low
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Asynchronous request filter low
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
Register:
Type:
Asynchronous request filter low
Read/Set/Clear
Offset:
108h set register
10Ch clear register
0000 0000h
Default:
Table 9–25. Asynchronous Request Filter Low Register Description
BIT
SIGNAL
TYPE
FUNCTION
If set to 1 for local bus node number 31, asynchronous requests received by the PCI4451 from that
node will be accepted.
31
asynReqResource31
RSC
If set to 1 for local bus node number 30, asynchronous requests received by the PCI4451 from that
node will be accepted.
30
L
asynReqResource30
RSC
L
L
Bits 29 through 2 follow the same pattern.
If set to 1 for local bus node number 1, asynchronous requests received by the PCI4451 from that
node will be accepted.
1
asynReqResource1
RSC
If set to 1 for local bus node number 0, asynchronous requests received by the PCI4451 from that
node will be accepted.
0
asynReqResource0
RSC
9–28
9.34 Physical Request Filter High Register
This set/clear register is used to enable physical receive requests on a per-node basis, and handles the upper node
IDs. When a packet is destined for the physical request context, and the node ID has been compared against the
ARRQ registers, then the comparison is done again with this register. If the bit corresponding to the node ID is not
set in this register, then the request will be handled by the ARRQ context instead of the physical request context. See
Table 9–26 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Physical request filter high
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Physical request filter high
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
Register:
Type:
Physical request filter high
Read/Set/Clear
Offset:
110h set register
114h clear register
0000 0000h
Default:
Table 9–26. Physical Request Filter High Register Description
BIT
SIGNAL
TYPE
FUNCTION
If set to 1, then all asynchronous requests received by the PCI4451 from nonlocal bus nodes will
be accepted.
31
physReqAllBusses
physReqResource62
physReqResource61
physReqResource60
physReqResource59
physReqResource58
physReqResource57
physReqResource56
physReqResource55
physReqResource54
physReqResource53
physReqResource52
physReqResource51
RSC
If set to 1 for local bus node number 62, then physical requests received by the PCI4451 from that
node will be handled through the physical request context.
30
29
28
27
26
25
24
23
22
21
20
19
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
If set to 1 for local bus node number 61, then physical requests received by the PCI4451 from that
node will be handled through the physical request context.
If set to 1 for local bus node number 60, then physical requests received by the PCI4451 from that
node will be handled through the physical request context.
If set to 1 for local bus node number 59, then physical requests received by the PCI4451 from that
node will be handled through the physical request context.
If set to 1 for local bus node number 58, then physical requests received by the PCI4451 from that
node will be handled through the physical request context.
If set to 1 for local bus node number 57, then physical requests received by the PCI4451 from that
node will be handled through the physical request context.
If set to 1 for local bus node number 56, then physical requests received by the PCI4451 from that
node will be handled through the physical request context.
If set to 1 for local bus node number 55, then physical requests received by the PCI4451 from that
node will be handled through the physical request context.
If set to 1 for local bus node number 54, then physical requests received by the PCI4451 from that
node will be handled through the physical request context.
If set to 1 for local bus node number 53, then physical requests received by the PCI4451 from that
node will be handled through the physical request context.
If set to 1 for local bus node number 52, then physical requests received by the PCI4451 from that
node will be handled through the physical request context.
If set to 1 for local bus node number 51, then physical requests received by the PCI4451 from that
node will be handled through the physical request context.
9–29
Table 9–26. Physical Request Filter High Register Description (Continued)
BIT
SIGNAL
TYPE
FUNCTION
If set to 1 for local bus node number 50, then physical requests received by the PCI4451 from that
node will be handled through the physical request context.
18
physReqResource50
RSC
If set to 1 for local bus node number 49, then physical requests received by the PCI4451 from that
node will be handled through the physical request context.
17
16
15
14
13
12
11
10
9
physReqResource49
physReqResource48
physReqResource47
physReqResource46
physReqResource45
physReqResource44
physReqResource43
physReqResource42
physReqResource41
physReqResource40
physReqResource39
physReqResource38
physReqResource37
physReqResource36
physReqResource35
physReqResource34
physReqResource33
physReqResource32
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
If set to 1 for local bus node number 48, then physical requests received by the PCI4451 from that
node will be handled through the physical request context.
If set to 1 for local bus node number 47, then physical requests received by the PCI4451 from that
node will be handled through the physical request context.
If set to 1 for local bus node number 46, then physical requests received by the PCI4451 from that
node will be handled through the physical request context.
If set to 1 for local bus node number 45, then physical requests received by the PCI4451 from that
node will be handled through the physical request context.
If set to 1 for local bus node number 44, then physical requests received by the PCI4451 from that
node will be handled through the physical request context.
If set to 1 for local bus node number 43, then physical requests received by the PCI4451 from that
node will be handled through the physical request context.
If set to 1 for local bus node number 42, then physical requests received by the PCI4451 from that
node will be handled through the physical request context.
If set to 1 for local bus node number 41, then physical requests received by the PCI4451 from that
node will be handled through the physical request context.
If set to 1 for local bus node number 40, then physical requests received by the PCI4451 from that
node will be handled through the physical request context.
8
If set to 1 for local bus node number 39, then physical requests received by the PCI4451 from that
node will be handled through the physical request context.
7
If set to 1 for local bus node number 38, then physical requests received by the PCI4451 from that
node will be handled through the physical request context.
6
If set to 1 for local bus node number 37, then physical requests received by the PCI4451 from that
node will be handled through the physical request context.
5
If set to 1 for local bus node number 36, then physical requests received by the PCI4451 from that
node will be handled through the physical request context.
4
If set to 1 for local bus node number 35, then physical requests received by the PCI4451 from that
node will be handled through the physical request context.
3
If set to 1 for local bus node number 34, then physical requests received by the PCI4451 from that
node will be handled through the physical request context.
2
If set to 1 for local bus node number 33, then physical requests received by the PCI4451 from that
node will be handled through the physical request context.
1
If set to 1 for local bus node number 32, then physical requests received by the PCI4451 from that
node will be handled through the physical request context.
0
9–30
9.35 Physical Request Filter Low Register
This set/clear register is used to enable physical receive requests on a per-node basis, and handles the lower node
IDs. When a packet is destined for the physical request context, and the node ID has been compared against the
asynchronous request filter registers, then the node ID comparison is done again with this register. If the bit
corresponding to the node ID is not set in this register, then the request will be handled by the asynchronous request
context instead of the physical request context. See Table 9–27 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Physical request filter low
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Physical request filter low
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
RSC
0
Register:
Type:
Physical request filter low
Read/Set/Clear
Offset:
118h set register
11Ch clear register
0000 0000h
Default:
Table 9–27. Physical Request Filter Low Register Description
BIT
SIGNAL
TYPE
FUNCTION
If set to 1 for local bus node number 31, then physical requests received by the PCI4451 from
that node will be handled through the physical request context.
31
physReqResource31
RSC
If set to 1 for local bus node number 30, then physical requests received by the PCI4451 from
that node will be handled through the physical request context.
30
L
physReqResource30
RSC
L
L
Bits 29 through 2 follow the same pattern.
If set to 1 for local bus node number 1, then physical requests received by the PCI4451 from
that node will be handled through the physical request context.
1
physReqResource1
RSC
If set to 1 for local bus node number 0, then physical requests received by the PCI4451 from
that node will be handled through the physical request context.
0
physReqResource0
RSC
9.36 Physical Upper Bound Register (Optional Register)
This register is an optional register and is not implemented. This register is read-only and returns all 0s.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Physical upper bound
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Physical upper bound
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Physical upper bound
Read-only
Offset:
Default:
120h
0000 0000h
9–31
9.37 Asynchronous Context Control Register
This set/clear register controls the state and indicates status of the DMA context. See Table 9–28 for a complete
description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Asynchronous context control
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Asynchronous context control
RSCU
0
R
0
R
0
RSU
X
RU
0
RU
0
R
0
R
0
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
Register:
Type:
Offset:
Asynchronous context control
Read/Set/Clear/Update, Read/Set/Update, Read/Update, Read-only
180h set register [ATRQ]
184h clear register [ATRQ]
1A0h set register [ATRS]
1A4h clear register [ATRS]
1C0h set register [ARRQ]
1C4h clear register [ARRQ]
1E0h set register [ARRS]
1E4h clear register [ARRS]
0000 X0XXh
Default:
Table 9–28. Asynchronous Context Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
31–16
RSVD
R
Reserved. These bits return 0s when read.
This bit is set by software to enable descriptor processing for the context and cleared by software to stop
descriptor processing. The PCI4451 will only change this bit on a hardware or software reset.
15
14–13
12
run
RSCU
R
RSVD
wake
Reserved. These bits return 0s when read.
Software sets this bit to cause the PCI4451 to continue or resume descriptor processing. The PCI4451 will
clear this bit on every descriptor fetch.
RSU
The PCI4451 sets this bit when it encounters a fatal error and clears the bit when software resets the run
bit.
11
dead
RU
10
active
RSVD
RU
R
The PCI4451 sets this bit to 1 when it is processing descriptors.
Reserved. These bits return 0s when read.
9–8
This field indicates the speed at which a packet was received or transmitted, and only contains meaningful
information for receive contexts. This field is encoded as:
7–5
4–0
spd
RU
RU
000b = 100 Mbits/sec,
001b = 200 Mbits/sec, and
010b = 400 Mbits/sec. All other values are reserved.
This field holds the acknowledge sent by the link core for this packet or an internally generated error code
if the packet was not transferred successfully.
eventcode
9–32
9.38 Asynchronous Context Command Pointer Register
This register contains a pointer to the address of the first descriptor block that the PCI4451 will access when software
enables the context by setting the run bit (bit 15) of the asynchronous context control register (see Section 9.37) at
offset 180h/184h (ATRQ), 1A0h/1A4h (ATRS), 1C0h/1C4h (ARRQ), or 1E0h/1E4h (ARRS). See Table 9–29 for a
complete description of the register contents.
Bit
31
30
29
28
27
26
Asynchronous context command pointer
RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Asynchronous context command pointer
RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Register:
Type:
Offset:
Asynchronous context command pointer
Read/Write/Update
18Ch [ATRQ]
1ACh [ATRS]
1CCh [ARRQ]
1ECh [ARRS]
Default:
XXXX XXXXh
Table 9–29. Asynchronous Context Command Pointer Register Description
BIT
SIGNAL
TYPE
FUNCTION
Contains the upper 28 bits of the address of a 16-byte-aligned descriptor block.
31–4
descriptorAddress
RWU
Indicates the number of contiguous descriptors at the address pointed to by the descriptor
address. If Z is 0, it indicates that the descriptorAddress is not valid.
3–0
Z
RWU
9–33
9.39 Isochronous Transmit Context Control Register
This set/clear register controls options, state, and status for the isochronous transmit DMA contexts. The n value in
the following register addresses indicates the context number (n = 0, 1, 2, 3, …, 7). See Table 9–30 for a complete
description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Isochronous transmit context control
RSCU RSC
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC RSC
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
RSC
X
X
X
X
X
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Isochronous transmit context control
RSC
0
R
0
R
0
RSU
X
RU
0
RU
0
R
0
R
0
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
Register:
Type:
Isochronous transmit context control
Read/Set/Clear/Update, Read/Set/Clear, Read/Set/Update, Read/Update, Read-only
Offset:
200h + (16 * n)
204h + (16 * n)
XXXX X0XXh
set register
clear register
Default:
Table 9–30. Isochronous Transmit Context Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
When set to 1, processing will occur such that the packet described by the first descriptor block
of the context will be transmitted in the cycle whose number is specified in the cycleMatch field of
this register. The 13-bit cycleMatch field must match the 13-bit cycleCount field in the cycle start
packet that is sent or received immediately before isochronous transmission begins.
31
cycleMatchEnable
RSCU
Contains a 15-bit value, corresponding to the lower order 2 bits of cycleSeconds and 13-bit
cycleCount field. If cycleMatchEnable is set, then this IT DMA context will become enabled for
transmits when the bus cycleCount value equals the cycleMatch value.
30–16
cycleMatch
run
RSC
RSC
This bit is set by software to enable descriptor processing for the context and cleared by software
to stop descriptor processing. The PCI4451 will only change this bit on a hardware or software
reset.
15
14–13
RSVD
wake
R
Reserved. These bits return 0s when read.
Software sets this bit to cause the PCI4451 to continue or resume descriptor processing. The
PCI4451 will clear this bit on every descriptor fetch.
12
RSU
The PCI4451 sets this bit when it encounters a fatal error, and clears the bit when software resets
the run bit.
11
dead
RU
10
active
RSVD
spd
RU
R
The PCI4451 sets this bit to 1 when it is processing descriptors.
Reserved. These bits return 0s when read.
9–8
7–5
RU
This field in not meaningful for isochronous transmit contexts.
Following an OUTPUT_LAST* command, the error code is indicated in this field. Possible values
are: ack_complete, evt_descriptor_read, evt_data_read, and evt_unknown.
4–0
event code
RU
9–34
9.40 Isochronous Transmit Context Command Pointer Register
This register contains a pointer to the address of the first descriptor block that the PCI4451 will access when software
enables an ISO transmit context by setting the run bit (bit 15) in the isochronous transmit context control register
(offset 200h/204h + (16 * n), see Section 9.39). The n value in the following register addresses indicates the context
number (n = 0, 1, 2, 3, …, 7).
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Isochronous transmit context command pointer
R
X
R
X
R
X
R
X
R
X
R
X
R
X
9
R
X
8
R
X
7
R
X
6
R
X
5
R
X
4
R
X
3
R
X
2
R
X
1
R
X
0
15
14
13
12
11
10
Name
Type
Default
Isochronous transmit context command pointer
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
Register:
Type:
Isochronous transmit context command pointer
Read-only
Offset:
Default:
20Ch + (16 * n)
XXXX XXXXh
9–35
9.41 Isochronous Receive Context Control Register
This set/clear register controls options, state, and status for the isochronous receive DMA contexts. The n value in
the following register addresses indicates the context number (n = 0, 1, 2, 3, 4). See Table 9–31 for a complete
description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Ischronous receive context control
RSC
X
RSC
X
RSCU
X
RSC
X
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
15
14
13
12
11
10
Name
Type
Default
Ischronous receive context control
RSCU
0
R
0
R
0
RSU
X
RU
0
RU
0
R
0
R
0
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
RU
X
Register:
Type:
Ischronous receive context control
Read/Set/Clear/Update, Read/Set/Clear, Read/Set/Update, Read/Update, Read-only
Offset:
400h + (32 * n)
404h + (32 * n)
X000 X0XXh
set register
clear register
Default:
Table 9–31. Isochronous Receive Context Control
BIT
SIGNAL
TYPE
FUNCTION
When set, received packets are placed back-to-back to completely fill each receive buffer.
When clear, each received packet is placed in a single buffer. If the multiChanMode bit is set
to 1, this bit must also be set to 1. The value of bufferFill must not be changed while active or run
is set.
31
bufferFill
RSC
When set to 1, received isochronous packets will include the complete 4-byte isochronous packet
header seen by the link layer. The end of the packet will be marked with an xferStatus in the first
doublet, and a 16-bit timeStamp indicating the time of the most recently received (or sent)
cycleStart packet. When clear, the packet header is stripped from received isochronous packets.
The packet header, if received, immediately precedes the packet payload. The value of
isochHeader must not be changed while active or run is set.
30
29
isochHeader
RSC
When set, the context will begin running only when the 13-bit cycleMatch field in the contextMatch
register matches the 13-bit cycleCount in the cycleStart packet. The effects of this bit, however,
are impacted by the values of other bits in this register. Once the context has become
active, hardware clears the cycleMatchEnable bit. The value of cycleMatchEnable must not be
changed while active or run is set.
cycleMatchEnable
multiChanMode
RSCU
When set, the corresponding isochronous receive DMA context will receive packets for all
isochronous channels enabled in the IRChannelMaskHi and IRChannelMaskLo registers. The
isochronous channel number specified in the IRDMA context match register is ignored. When 0,
the IRDMA context will receive packets for that single channel. Only one IRDMA context may
use the IRChannelMask registers. If more that one IRDMA context control register has the
multiChanMode bit set, results are undefined. The value of multiChanMode must not be
changed while active or run is set.
28
RSC
R
27–16
RSVD
run
Reserved. These bits return 0s when read.
This bit is set by software to enable descriptor processing for the context and cleared by software
RSCU to stop descriptor processing. The PCI4451 will only change this bit on a hardware or software
reset.
15
14–13
RSVD
wake
R
Reserved. These bits return 0s when read.
Software sets this bit to cause the PCI4451 to continue or resume descriptor processing. The
PCI4451 will clear this bit on every descriptor fetch.
12
RSU
The PCI4451 sets this bit when it encounters a fatal error, and clears the bit when software resets
the run bit.
11
10
dead
RU
RU
active
The PCI4451 sets this bit to 1 when it is processing descriptors.
9–36
Table 9–31. Isochronous Receive Context Control (Continued)
BIT
SIGNAL
TYPE
FUNCTION
Reserved. These bits return 0s when read.
9–8
RSVD
R
This field indicates the speed at which the packet was received.
000b = 100 Mbits/sec,
7–5
4–0
spd
RU
RU
001b = 200 Mbits/sec, and
010b = 400 Mbits/sec. All other values are reserved.
event code
Following an INPUT* command, the error code is indicated in this field.
9.42 Isochronous Receive Context Command Pointer Register
This register contains a pointer to the address of the first descriptor block that the PCI4451 will access when software
enables an ISO receive context by setting the run bit (bit 15) in the isochronous receive context control register (offset
400h/404h + (32 * n), see Section 9.41). The n value in the following register addresses indicates the context number
(n = 0, 1, 2, 3, 4).
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Isochronous receive context command pointer
R
X
R
X
R
X
R
X
R
X
R
X
R
X
9
R
X
8
R
X
7
R
X
6
R
X
5
R
X
4
R
X
3
R
X
2
R
X
1
R
X
0
15
14
13
12
11
10
Name
Type
Default
Isochronous receive context command pointer
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
Register:
Type:
Isochronous receive context command pointer
Read-only
Offset:
Default:
40Ch + (32 * n)
XXXX XXXXh
9–37
9.43 Isochronous Receive Context Match Register
This register is used to start an isochronous receive context running on a specified cycle number, to filter incoming
isochronous packets based on tag values, and to wait for packets with a specified sync value. The n value in the
following register addresses indicates the context number (n = 0, 1, 2, 3, 4). See Table 9–32 for a complete description
of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Isochronous receive context match
R
X
R
X
R
X
R
X
R
0
R
0
R
0
9
R
X
8
R
X
7
R
X
6
R
X
5
R
X
4
R
X
3
R
X
2
R
X
1
R
X
0
15
14
13
12
11
10
Name
Type
Default
Isochronous receive context match
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
0
R
X
R
X
R
X
R
X
R
X
R
X
R
X
Register:
Type:
Isochronous receive context match
Read/Write
Offset:
Default:
410Ch + (32 * n)
XXXX XXXXh
Table 9–32. Isochronous Receive Context Match Register Description
BIT
31
SIGNAL
tag3
TYPE
R/W
R/W
R/W
R/W
R
FUNCTION
If set, this context will match on iso receive packets with a tag field of 11b.
If set, this context will match on iso receive packets with a tag field of 10b.
If set, this context will match on iso receive packets with a tag field of 01b.
If set, this context will match on iso receive packets with a tag field of 00b.
Reserved. These bits return 0s when read.
30
tag2
29
tag1
28
tag0
27–25
RSVD
Contains a 13-bit value, corresponding to the 13-bit cycleCount field in the cycleStart packet. If
cycleMatchEnable is set, then this context is enabled for receives when the bus cycleCount value
equals the cycleMatch value.
24–12
cycleMatch
R/W
This field contains the 4-bit field which is compared to the sync field of each iso packet for this channel
when the command descriptor w field is set to 11b.
11–8
sync
R/W
R
7
RSVD
Reserved. These bits return 0s when read.
If set and the tag1 bit is set , then packets with tag 01b will be accepted into the context if the two
most significant bits of the packets sync field are 00b. Packets with tag values other than 01b are
filtered according to tag0, tag2 and tag3 without any additional restrictions.
6
tag1SyncFilter
R/W
R/W
If clear, this context will match on isochronous receive packets as specified in the tag0–3 bits with no
additional restrictions.
This 6-bit field indicates the isochronous channel number for which this IR DMA context will accept
packets.
5–0
channelNumber
9–38
10 GPIO Interface
The GPIO interface consists of four general-purpose input/output ports. On power reset, GPIO0 and GPIO1 are
enabled and are configured as bus manager contender (BMC) and link power status (LPS), respectively. BMC and
LPS outputs can be configured via the GPIO control register in PCI configuration space, as GPIO0 and GPIO1.
Figure 10–1 shows the schematic for GPIO0 implementation. Figure 10–2 shows the schematic for GPIO1
implementation.
GPIO2 and GPIO3 power up as general-purpose inputs and are programmable via the GPIO control register.
Figure 10–3 shows the schematic for GPIO2 and GPIO3 implementation.
10–1
GPIO Read Data
GPIO Write Data
GPIO Port
D
Q
BMC
GPIO_Invert
GPIO Enable
Disable BMC
Figure 10–1. BMC/GPIO0
GPIO Read Data
GPIO Write Data
GPIO Port
D
Q
LPS
GPIO_Invert
GPIO Enable
Disable LPS
Figure 10–2. LPS/GPIO1
GPIO Read Data
GPIO Write Data
GPIO Port
D
Q
GPIO_Invert
GPIO Enable
Figure 10–3. GPIO2 and GPIO3
10–2
11 Serial EEPROM
11.1 Serial Bus Interface
The PCI4451 provides a serial bus interface to initialize the 1394 global unique ID register and a few PCI configuration
registers through a serial EEPROM. The PCI4451 communicates with the serial EEPROM via the 2-wire serial
interface.
After power-up the serial interface initializes the locations listed in Table 11–1. While the PCI4451 is accessing the
serial ROM, all incoming PCI slave accesses are terminated with retry status. Table 11–2 shows the serial ROM
memory map required for initializing the PCI4451 registers.
Table 11–1. OHCI Registers and Bits Loadable Through Serial EEPROM
BITS LOADED FROM
OFFSET
REGISTER
EEPROM
31–0
31–0
23
OHCI register (24h)
OHCI register(28h)
OHCI register (50h)
PCI register (2Ch)
PCI register (2Eh)
PCI register (3Eh)
PCI register (F4h)
Global unique ID high (see Section 9.10)
Global unique ID low (see Section 9.11)
Host controller control (see Section 9.16)
Subsytem vendor ID (see Section 8.11)
Subsystem ID (see Section 8.12)
15–0
15–0
15–0
7, 2, 1
MIN_GNT and MAX_LAT (see Section 8.15)
Link enhancement control (see Section 8.22)
11–1
Table 11–2. Serial EEPROM Map
BYTE
ADDRESS
BYTE DESCRIPTION
00
01
02
03
04
05
PCI maximum latency (0h)
PCI_Minimum grant (0h)
PCI vendor ID
PCI vendor ID (ms byte)
PCI subsytem ID (ls byte)
PCI subsytem ID
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Link_enhancement
Control.enab_unfair
HCControl.
RSVD
RSVD
RSVD
Link_enhancement
Control.enab_
insert_idle
Link_enhancement
Control.enab_accel
RSVD
ProgramPhy
Enable
06
07
08
09
0A
0B
0C
0D
0E
Reserved
1394 GlobalUniqueIDHi (ls byte 0)
1394 GlobalUniqueIDHi (byte 1)
1394 GlobalUniqueIDHi (byte 2)
1394 GlobalUniqueIDHi (ms byte 3)
1394 GlobalUniqueIDLo (ls byte 0)
1394 GlobalUniqueIDLo (byte 1)
1394 GlobalUniqueIDLo (byte 2)
1394 GlobalUniqueIDLo (ms byte 3)
11–2
12 Electrical Characteristics
†
12.1 Absolute Maximum Ratings Over Operating Temperature Ranges
Supply voltage range, V
Clamping voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
V
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V
CCP, CCA, CCB
Input voltage range, V : PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
+ 0.5 V
+ 0.5 V
+ 0.5 V
+ 0.5 V
+ 0.5 V
+ 0.5 V
+ 0.5 V
+ 0.5 V
+ 0.5 V
I
CCP
CCA
CCB
Card A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
Card B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
ZV, TTl, Fail safe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
Miscellaneous and PHY I/F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 to V
CC
CC
Output voltage range, V : PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
CC
CCA
CCB
Card A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
Card B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
ZV, TTL, Fail safe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
Miscellaneous and PHY I/F . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 to V
CC
CC
Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
I
CC
Output clamp current, I
Storage temperature range, T
(V < 0 or V > V ) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
OK
O O CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
Virtual junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
J
†
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Applies for external input and bidirectional buffers. V > V
does not apply to fail-safe terminals. PCI terminals are measured with
or V . ZV terminals and TTL signals are
I
CC
respect to V
instead of V . PC Card terminals are measured with respect to V
CC CCA
CCP
CCB
measured with respect to V . The limit specified applies for a dc condition.
CC
2. Applies for external output and bidirectional buffers. V > V
does not apply to fail-safe terminals. PCI terminals are measured
O
CC
with respect to V
instead of V . PC Card terminals are measured with respect to V
or V
. ZV terminals and TTL signals
CCP
CC CCA
CCB
are measured with respect to V . The limit specified applies for a dc condition.
CC
12–1
12.2 Recommended Operating Conditions (see Note 3)
OPERATION
MIN
3
NOM
3.3
3.3
5
MAX
3.6
UNIT
V
V
Core voltage
Commercial
Commercial
3.3 V
3.3 V
5 V
V
CC
3
3.6
PCI I/O voltage, ZV Port I/O voltage
V
V
CCP
4.5
3
5.5
3.3 V
5 V
3.3
5
3.6
V
V
PC Card I/O voltage
Commercial
PCI
CC(A/B)
CC(A/B)
4.75
5.25
3.3 V
5 V
0.5 V
CCP
V
CCP
2
V
CCP
3.3 V
5 V
0.475 V
V
CCA/B
CCA/B
CCA/B
PC Card
PHY I/F
†
2.4
V
V
High-level Input voltage
V
IH
2
V
CC
V
CC
V
CC
‡
TTL
2
2.4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
§
Fail safe
3.3 V
5 V
0.3 V
CCP
PCI
0.8
3.3 V
5 V
0.325 V
CCA/B
PC Card
PHY I/F
†
0.8
V
IL
Low-level input voltage
V
0.8
0.8
0.8
‡
TTL
§
Fail safe
PCI
3.3 V
5 V
V
CCP
PC Card
PHY I/F
V
CCA/B
V
CC
V
V
Input voltage
V
I
‡
TTL
V
V
V
V
V
V
V
CC
CC
CC
CC
CC
CC
§
Fail safe
PCI
3.3 V
5 V
PC Card
PHY I/F
¶
Output voltage
V
O
‡
TTL
§
Fail safe
CC
4
PCI and PC Card
TTL and fail safe
t
t
Input transition times (t and t )
ns
r
f
6
T
A
Operating ambient temperature range
Virtual junction temperature
25
25
70
_C
_C
#
T
J
115
†
‡
Applies to external inputs and bidirectional buffers without hysteresis
TTL 4 mA pins are A_CVS1//A_VS1, A_CVS2//A_VS2, B_CVS1//B_VS1, B_CVS2//B_VS2, CLOCK, DATA, LATCH, SPKROUT,
MFUNC4–MFUNC0, SCL, SDA, ZV_UVx, ZV_PCLK, ZV_SDATA, ZV_LRCLK, ZV_MCLK, ZV_VSYNC, ZV_HREF, ZV_SCLK, ZV_Yx,
SUSPEND, LPS, PHY_LREQ.
TTL 8 mA pins are MFUNC6, MFUNC5, PHY_CTL0, PHY_CTL1, PHY_DATAx, and LINKON.
Fail-safe pin is RI_OUT (open drain).
Applies to external output buffers
§
¶
#
These junction temperatures reflect simulation conditions. The customer is responsible for verifying junction temperature.
NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating.
12–2
12.3 Electrical Characteristics Over Recommended Operating Conditions (unless
otherwise noted)
PARAMETER
PINS
OPERATION TEST CONDITIONS
MIN
MAX
UNIT
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
= –0.5 mA
= –2 mA
= –0.15 mA
= –0.15 mA
= –4 mA
= –8 mA
= –4 mA
= –8 mA
= 1.5 mA
= 6 mA
0.9 V
3.3 V
5 V
OH
OH
OH
OH
OH
OL
OH
OH
OL
OL
OL
OL
OL
OL
OL
OL
OL
CC
2.4
PCI
0.9 V
3.3 V
5 V
CC
2.4
PC Card
PHY I/F
TTL
V
OH
V
High-level output voltage (see Note 4)
2.8
3.3 V
3.3 V
V
CC
V
CC
V
CC
–0.6
–0.6
–0.6
0.1 V
3.3 V
5 V
CC
PCI
0.55
= 0.7 mA
= 0.7 mA
= 4 mA
0.1 V
CC
3.3 V
5 V
PC Card
PHY I/F
0.55
0.5
0.5
0.5
0.5
0.5
–1
3.3 V
3.3 V
V
OL
V
Low-level output voltage
= 8 mA
= 4 mA
TTL
= 8 mA
= 8 mA
SERR
3.6 V
5.25 V
3.6 V
V = V
I
CC
CC
CC
3-state output, high-impedance state
current (see Note 4)
I
I
Output pins
µA
µA
OZL
V = V
–1
I
†
†
10
V = V
I
3-state output, high-impedance state
current
Output pins
OZH
5.25 V
25
–1
V = V
I
CC
Input pins
I/O pins
Latch
V = GND
I
I
I
V = GND
I
–10
–2
µA
µA
Low-level input current
IL
V = GND
I
‡
3.6 V
10
V = V
I
CC
Input pins
‡
‡
‡
5.25 V
3.6 V
20
10
25
10
V = V
I
CC
CC
CC
CC
High-level input current (see Note 5)
IH
V = V
I
I/O pins
5.25 V
3.6 V
V = V
I
Fail-safe pins
V = V
I
†
‡
For PCI terminals, V = V
For I/O terminals, input leakage (I and I ) includes I
. For PC Card terminals, V = V
. For ZV pins, V = V . For miscellaneous terminals, V = V .
CC CC
I
CCP
I
CC(A/B)
I
I
leakage of the disabled output.
IL
IH
OZ
NOTES: 4. V
and I are not tested on SERR (GFN terminal Y20, GJG terminal W18) and RI_OUT (GFN terminal Y13, GJG terminal R11)
OH
OL
because they are open-drain outputs. Other terminals may or may not be tested.
is not tested on LATCH (GFN terminal W12, GJG terminal W11) because it is pulled up with an internal resistor. Other terminals
5.
I
IH
may or may not be tested.
12–3
12.4 PCI Clock/Reset Timing Requirements Over Recommended Ranges of Supply
Voltage and Operating Free-Air Temperature (see Figure 12–2 and Figure 12–3)
ALTERNATE
SYMBOL
TEST
CONDITIONS
PARAMETER
MIN
MAX
UNIT
t
t
t
Cycle time, PCLK
t
30
11
11
1
ns
ns
c
cyc
Pulse duration, PCLK high
Pulse duration, PCLK low
Slew rate, PCLK
t
high
wH
wL
t
ns
low
t , t
∆v/∆t
4
V/ns
ms
ms
r f
t
t
Pulse duration, RSTIN
t
1
w
rst
Setup time, PCLK active at end of RSTIN
t
100
su
rst-clk
12.5 PCI Timing Requirements Over Recommended Ranges of Supply Voltage and
Operating Free-Air Temperature (see Note 7, Figure 12–1, and Figure 12–4)
ALTERNATE
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
PCLK-to-shared signal
valid delay time
t
11
val
inv
C
= 50 pF,
L
t
Propagation delay time, See Note 6
ns
pd
See Note 7
PCLK-to-shared signal
invalid delay time
t
2
2
t
t
t
t
Enable time, high impedance-to-active delay time from PCLK
Disable time, active-to-high impedance delay time from PCLK
Setup time before PCLK valid
t
ns
ns
ns
ns
en
dis
su
h
on
t
28
off
t
7
0
su
Hold time after PCLK high
t
h
NOTES: 6. PCI shared signals are AD31–AD0, C/BE3–C/BE0, FRAME, TRDY, IRDY, STOP, IDSEL, DEVSEL, and PAR.
7. This data sheet uses the following conventions to describe time ( t ) intervals. The format is t , where subscript A indicates the type
A
of dynamic parameter being represented. One of the following is used: t = propagation delay time, t = delay time, t = setup time,
pd
d
su
and t = hold time.
h
12.6 Switching Characteristics for PHY-Link Interface
PARAMETER
MEASURED
–50% to 50%
–50% to 50%
–50% to 50%
MIN
TYP
MAX
UNIT
t
t
t
Setup time, Dn, CTLn, LREQ to PHY_CLK
Hold time, Dn, CTLn, LREQ before PHY_CLK
Delay time, PHY_CLK to Dn, CTLn
6
su
1
2
ns
h
11
d
12–4
12.7 Parameter Measurement Information
LOAD CIRCUIT PARAMETERS
I
†
‡
OL
TIMING
PARAMETER
C
I
I
V
LOAD
(pF)
OL
OH
LOAD
(V)
(mA)
(mA)
t
0
3
PZH
Test
Point
t
50
8
–8
en
t
t
t
PZL
PHZ
PLZ
From Output
Under Test
V
LOAD
t
t
50
50
8
8
–8
–8
1.5
dis
pd
‡
C
LOAD
†
‡
C
V
includes the typical load-circuit distributed capacitance.
LOAD
LOAD
I
OH
– V
OL
= 50 Ω, where V
= 0.6 V, I
OL
= 8 mA
OL
I
OL
LOAD CIRCUIT
V
Timing
Input
(see Note A)
CC
V
CC
50% V
CC
High-Level
Input
50% V
50% V
CC
CC
0 V
0 V
t
h
t
su
t
w
V
CC
90% V
Data
CC
V
CC
50% V
Input
50% V
CC
10% V
CC
CC
Low-Level
Input
0 V
50% V
50% V
CC
CC
t
t
f
r
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
Output
Control
(low-level
enabling)
V
CC
50% V
50% V
CC
CC
V
0 V
CC
Input
(see Note A)
t
50% V
50% V
CC
PZL
CC
t
PLZ
0 V
t
pd
V
t
CC
50% V
pd
V
Waveform 1
(see Notes B
and C)
CC
CC
OH
50% V
CC
In-Phase
Output
V
+ 0.3 V
OL
50% V
50% V
CC
CC
V
OL
V
OL
t
PHZ
t
pd
t
PZH
t
pd
V
OH
V
OH
Waveform 2
(see Notes B
and C)
V
– 0.3 V
OH
Out-of-Phase
Output
50% V
CC
50% V
50% V
CC
CC
50% V
V
OL
0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by pulse generators having the
following characteristics: PRR = 1 MHz, Z = 50 Ω, t = 6 ns.
O
r
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. For t
PLZ
and t , V
PHZ OL
and V are measured values.
OH
Figure 12–1. Load Circuit and Voltage Waveforms
12–5
12.8 PCI Bus Parameter Measurement Information
t
high
t
low
2 V
0.8 V
2 V MIN Peak-to-Peak
t
f
t
r
t
cyc
Figure 12–2. PCLK Timing Waveform
PCLK
t
rst
RSTIN
t
srst-clk
Figure 12–3. RSTIN Timing Waveforms
PCLK
1.5 V
t
t
inv
val
1.5 V
Valid
PCI Output
PCI Input
t
t
on
off
Valid
t
su
t
h
Figure 12–4. Shared Signals Timing Waveforms
12.9 PC Card Cycle Timing
The PC Card cycle timing is controlled by the wait-state bits in the Intel 82365SL-DF compatible memory and I/O
window registers. The PC Card cycle generator uses the PCI clock to generate the correct card address setup and
hold times and the PC Card command active (low) interval. This allows the cycle generator to output PC Card cycles
that are as close to the Intel 82365SL-DF timing as possible, while always slightly exceeding the Intel 82365SL-DF
values. This ensures compatibility with existing software and maximizes throughput.
The PC Card address setup and hold times are a function of the wait-state bits. Table 12–1 shows address setup time
in PCLK cycles and nanoseconds for I/O and memory cycles. Table 12–2 and Table 12–3 show command active time
in PCLK cycles and nanoseconds for I/O and memory cycles. Table 12–4 shows address hold time in PCLK cycles
and nanoseconds for I/O and memory cycles.
12–6
Table 12–1. PC Card Address Setup Time, t
, 8-Bit and 16-Bit PCI Cycles
su(A)
TS1 – 0 = 01
(PCLK/ns)
WAIT-STATE BITS
I/O
3/90
Memory
Memory
WS1
WS1
0
1
2/60
4/120
Table 12–2. PC Card Command Active Time, t
, 8-Bit PCI Cycles
c(A)
WAIT-STATE BITS
TS1 – 0 = 01
(PCLK/ns)
WS
0
ZWS
0
X
1
19/570
23/690
7/210
1
I/O
0
00
01
10
11
00
0
19/570
23/690
23/690
23/690
7/210
X
X
X
1
Memory
Table 12–3. PC Card Command Active Time, t
, 16-Bit PCI Cycles
c(A)
WAIT-STATE BITS
TS1 – 0 = 01
(PCLK/ns)
WS
0
ZWS
0
X
1
7/210
11/330
N/A
1
I/O
0
00
01
10
11
00
0
9/270
13/390
17/510
23/630
5/150
X
X
X
1
Memory
Table 12–4. PC Card Address Hold Time, t
, 8-Bit and 16-Bit PCI Cycles
h(A)
TS1 – 0 = 01
(PCLK/ns)
WAIT-STATE BITS
I/O
2/60
2/60
3/90
Memory
Memory
WS1
WS1
0
1
12–7
12.10 Timing Requirements Over Recommended Ranges of Supply Voltage and
Operating Free-Air Temperature, Memory Cycles (for 100-ns Common Memory) (see
Note 8 and Figure 12–5)
ALTERNATE
SYMBOL
MIN
MAX
UNIT
t
t
t
t
t
t
t
t
t
t
t
t
Setup time, CE1 and CE2 before WE/OE low
Setup time, CA25–CA0 before WE/OE low
T1
60
+2PCLK
90
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
su
su
su
pd
w
T2
t
su(A)
Setup time, REG before WE/OE low
T3
Propagation delay time, WE/OE low to WAIT low
Pulse duration, WE/OE low
T4
T5
200
120
Hold time, WE/OE low after WAIT high
T6
h
Hold time, CE1 and CE2 after WE/OE high
Setup time (read), CDATA15–CDATA0 valid before OE high
Hold time (read), CDATA15–CDATA0 valid after OE high
Hold time, CA25–CA0 and REG after WE/OE high
Setup time (write), CDATA15–CDATA0 valid before WE low
Hold time (write), CDATA15–CDATA0 valid after WE low
T7
h
T8
su
h
T9
0
+1PCLK
60
T10
T11
T12
t
h(A)
h
su
h
240
NOTE 8: These times are dependent on the register settings associated with ISA wait states and data size. They are also dependent on cycle
type (read/write, memory/I/O) and WAIT from PC Card. The times listed here represent absolute minimums (the times that would be
observed if programmed for zero wait state, 16-bit cycles) with a 33-MHz PCI clock.
12.11 Timing Requirements Over Recommended Ranges of Supply Voltage and
Operating Free-Air Temperature, I/O Cycles (see Figure 12–6)
ALTERNATE
MIN
MAX
UNIT
SYMBOL
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
T26
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Setup time, REG before IORD/IOWR low
60
60
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
su
su
su
pd
pd
w
Setup time, CE1 and CE2 before IORD/IOWR low
Setup time, CA25–CA0 valid before IORD/IOWR low
Propagation delay time, IOIS16 low after CA25–CA0 valid
Propagation delay time, IORD low to WAIT low
Pulse duration, IORD/IOWR low
t
+2PCLK
su(A)
35
35
T
cA
Hold time, IORD low after WAIT high
h
Hold time, REG low after IORD high
0
h
Hold time, CE1 and CE2 after IORD/IOWR high
Hold time, CA25–CA0 after IORD/IOWR high
Setup time (read), CDATA15–CDATA0 valid before IORD high
Hold time (read), CDATA15–CDATA0 valid after IORD high
Setup time (write), CDATA15–CDATA0 valid before IOWR low
Hold time (write), CDATA15–CDATA0 valid after IOWR high
120
h
t
+1PCLK
h
h(A)
10
0
su
h
90
90
su
h
12–8
12.12 Switching Characteristics Over Recommended Ranges of Supply Voltage and
Operating Free-Air Temperature, Miscellaneous (see Figure 12–7)
ALTERNATE
SYMBOL
PARAMETER
MIN
MAX
UNIT
BVD2 low to SPKROUT low
BVD2 high to SPKROUT high
IREQ to IRQ15–IRQ3
30
30
30
30
T27
t
pd
Propagation delay time
ns
T28
STSCHG to IRQ15–IRQ3
12.13 PC Card Parameter Measurement Information
CA25–CA0
T10
REG
CE1, CE2
T1
T5
T7
WE, OE
WAIT
T3
T6
T2
T4
T12
T9
T11
CDATA15–CDATA0
(write)
T8
CDATA15–CDATA0
(read)
With no wait state
With wait state
Figure 12–5. PC Card Memory Cycle
12–9
CA25–CA0
T16
T22
IOIS16
REG
T20
T21
CE1, CE2
T14
T18
IORD, IOWR
WAIT
T13
T15
T19
T17
T26
T24
T25
CDATA15–CDATA0
(write)
T23
CDATA15–CDATA0
(read)
With no wait state
With wait state
Figure 12–6. PC Card I/O Cycle
BVD2
SPKROUT
IREQ
T27
T28
IRQ15–IRQ3
Figure 12–7. Miscellaneous PC Card Delay Times
12–10
13 Mechanical Data
GFN (S-PBGA-N256)
PLASTIC BALL GRID ARRAY
27,20
SQ
SQ
24,13 TYP
26,80
24,70
24,00
1,27
0,635
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
3
5
7
9
11 13 15 17 19
10 12 14 16 18 20
2
4
6
8
2,32
1,92
0,40
0,30
Seating Plane
0,15
0,80
0,60
M
0,10
0,70
0,50
4040185-2/B 11/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
13–1
GJG (S-PBGA-N257)
PLASTIC BALL GRID ARRAY
16,10
15,90
SQ
14,40 TYP
0,80
W
V
U
T
R
P
N
M
L
K
J
H
G
F
0,80
E
D
C
B
A
1
3
5
7
9
11 13 15 17 19
10 12 14 16 18
2
4
6
8
0,95
0,85
1,40 MAX
Seating Plane
0,10
0,55
0,45
0,12
0,08
M
0,08
0,45
0,35
4173511/A 08/98
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. MicroStar BGA configuration
MicroStar is a trademark of Texas Instruments Incorporated.
13–2
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