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PCM1608KY/2KG4 [TI]

SERIAL INPUT LOADING, 24-BIT DAC, PQFP48, GREEN, PLASTIC, LQFP-48;
PCM1608KY/2KG4
型号： PCM1608KY/2KG4
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

SERIAL INPUT LOADING, 24-BIT DAC, PQFP48, GREEN, PLASTIC, LQFP-48

输入元件 转换器
文件： 总46页 (文件大小：1011K)
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PCM1608  
SBAS164B–DECEMBER 2000–REVISED JULY 2005  
24-Bit, 192-kHz Sampling, 8-Channel, Enhanced Multilevel,  
Delta-Sigma Digital-to-Analog Converter  
FEATURES  
•
Dual-Supply Operation:  
– 5-V Analog  
•
24-Bit Resolution  
•
Analog Performance:  
– 3.3-V Digital  
– Dynamic Range:  
•
•
5-V Tolerant Digital Logic Inputs  
Package: LQFP-48  
• 100 dB, Typical (PCM1608Y)  
• 105 dB, Typical (PCM1608KY)  
– SNR:  
APPLICATIONS  
•
•
•
•
•
•
•
Integrated A/V Receivers  
DVD Movie and Audio Players  
HDTV Receivers  
• 100 dB, Typical (PCM1608Y)  
• 105 dB, Typical (PCM1608KY)  
– THD+N:  
Car Audio Systems  
• 0.003%, Typical (PCM1608Y)  
• 0.002%, Typical (PCM1608KY)  
– Full-Scale Output: 3.1 Vp-p, Typical  
4×/8× Oversampling Interpolation Filter:  
– Stop-Band Attenuation: –55 dB  
– Pass-Band Ripple: ±0.03 dB  
Sampling Frequency:  
DVD Add-On Cards for High-End PCs  
Digital Audio Workstations  
Other Multichannel Audio Systems  
•
•
DESCRIPTION  
The PCM1608 is a CMOS, monolithic integrated  
circuit that features eight 24-bit audio digital-to-analog  
converters (DACs) and support circuitry in a small  
LQFP-48 package. The DACs use Texas Instruments'  
enhanced multilevel, delta-sigma architecture that  
employs fourth-order noise shaping and 8-level ampli-  
tude quantization to achieve excellent signal-to-noise  
performance and a high tolerance to clock jitter.  
– 5 kHz to 200 kHz (Channels 1, 2, 7, and 8)  
– 5 kHz to 100 kHz (Channels 3, 4, 5, and 6)  
Accepts 16-, 18-, 20-, and 24-Bit Audio Data  
Data Formats: Standard, I2S, and  
Left-Justified  
•
•
The PCM1608 accepts industry-standard audio data  
formats with 16- to 24-bit audio data. Sampling rates  
up to 200 kHz (channels 1, 2, 7, and 8) or 100 kHz  
(channels 3, 4, 5, and 6) are supported. A full set of  
user-programmable functions is accessible through a  
4-wire serial control port that supports register write  
and read functions.  
•
•
System Clock: 128 fS, 192 fS, 256 fS, 384 fS,  
512 fS, or 768 fS  
User-Programmable Functions:  
– Digital Attenuation: 0 dB to –63 dB,  
0.5 dB/Step  
– Soft Mute  
– Zero Flags Can Be Used As General-  
Purpose Logic Output  
– Digital De-Emphasis  
– Digital Filter Rolloff: Sharp or Slow  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
FilterPro is a trademark of Texas Instruments.  
System Two, Audio Precision are trademarks of Audio Precision, Inc.  
All trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2000–2005, Texas Instruments Incorporated  
PCM1608  
www.ti.com  
SBAS164B–DECEMBER 2000–REVISED JULY 2005  
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated  
circuits be handled with appropriate precautions. Failure to observe proper handling and installation  
procedures can cause damage.  
ESD damage can range from subtle performance degradation to complete device failure. Precision  
integrated circuits may be more susceptible to damage because very small parametric changes could  
cause the device not to meet its published specifications.  
ABSOLUTE MAXIMUM RATINGS(1)  
over operating free-air temperature range (unless otherwise noted)  
VDD  
–0.3 V to 4 V  
–0.3 V to 6.5 V  
VCC – VDD < 3 V  
±0.1 V  
Power supply voltage  
VCC  
VCC, VDD  
Supply voltage difference  
Ground voltage differences  
Digital input voltage  
–0.3 V to 6.5 V  
±10 mA  
Input current (except power supply pins)  
Operating temperature under bias  
Storage temperature  
–40°C to 125°C  
–55°C to 150°C  
150°C  
Junction temperature  
Lead temperature (soldering)  
Package temperature (IR reflow, peak)  
260°C, 5 s  
235°C  
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings  
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating  
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
RECOMMENDED OPERATING CONDITIONS  
over operating free-air temperature range  
MIN  
3
NOM  
3.3  
5
MAX  
3.6  
UNIT  
V
Digital supply voltage, VDD  
Analog supply voltage, VCC  
Digital input logic family  
4.5  
5.5  
V
TTL  
System clock  
8.192  
32  
36.864  
192  
MHz  
kHz  
Digital input clock frequency  
Sampling clock, VOUT1, VOUT2  
Sampling clock, VOUT3, VOUT4, VOUT5, VOUT  
6
32  
96  
Analog output load resistance  
Analog output load capacitance  
Digital output load capacitance  
Operating free-air temperature, TA  
5
kΩ  
pF  
pF  
°C  
50  
20  
85  
–25  
2
PCM1608  
www.ti.com  
SBAS164B–DECEMBER 2000–REVISED JULY 2005  
ELECTRICAL CHARACTERISTICS  
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, system clock = 384 fS (fS = 44.1 kHz), and 24-bit data, unless  
otherwise noted  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
RESOLUTION  
24  
Bits  
DATA FORMAT  
Audio data interface formats  
Audio data bit length  
Audio data format  
Standard, I2S, left-justified  
16-, 18-, 20-, 24-bit, selectable  
MSB-first, binary 2s complement  
VOUT1, VOUT2, VOUT7, VOUT  
VOUT3, VOUT4, VOUT5, VOUT  
8
6
5
5
200  
fS  
Sampling frequency  
kHz  
100  
128 fS, 192 fS, 256 fS,  
384 fS, 512 fS, 768 fS  
System clock frequency  
DIGITAL INPUT/OUTPUT  
Logic family  
TTL-compatible  
2
VIH  
Input logic level  
VIL  
Vdc  
µA  
0.8  
10  
(1)  
IIH  
VIN = VDD  
VIN = 0 V  
(1)  
IIL  
–10  
100  
–10  
Input logic current  
(2)  
IIH  
VIN = VDD  
VIN = 0 V  
65  
(2)  
IIL  
VOH  
IOH = –4 mA  
IOL = 4 mA  
2.4  
Output logic level  
VOL  
Vdc  
1
(3)(4)  
DYNAMIC PERFORMANCE  
PCM1608Y  
VOUT = 0 dB, fS = 44.1 kHz  
VOUT = 0 dB, fS = 96 kHz  
VOUT = 0 dB, fS = 192 kHz  
0.003%  
0.005%  
0.006%  
1.25%  
1.4%  
0.01%  
THD+N  
Total harmonic distortion + noise  
VOUT = –60 dB, fS = 44.1 kHz  
VOUT = –60 dB, fS = 96 kHz  
VOUT = –60 dB, fS = 192 kHz  
EIAJ, A-weighted, fS = 44.1 kHz  
A-weighted, fS = 96 kHz  
A-weighted, fS = 192 kHz  
EIAJ, A-weighted, fS = 44.1 kHz  
A-weighted, fS = 96 kHz  
A-weighted, fS = 192 kHz  
fS = 44.1 kHz  
1.65%  
94  
94  
91  
100  
99  
Dynamic range  
dB  
dB  
98  
100  
99  
SNR  
Signal-to-noise ratio  
98  
98  
Channel separation  
Level linearity error  
fS = 96 kHz  
97  
dB  
dB  
fS = 192 kHz  
96  
VOUT = –90 dB  
±0.5  
(1) Pins 31, 38, 40, 41, 45–47 (DATA4, SCKI, BCK, LRCK, DATA1, DATA2, DATA3)  
(2) Pins 34–37 (MDI, MC, ML, RST)  
(3) Analog performance specifications are tested using a System Two™ Cascade audio measurement system by Audio Precision™ with  
400-Hz HPF on, 30-kHz LPF on, average mode with 20-kHz bandwidth limiting. The load connected to the analog output is 5 kΩ or  
larger, via capacitive loading.  
(4) Conditions in 192-kHz operation are: system clock = 128 fS, DAC3 through DAC6 disabled in register 8, and oversampling rate = 64 fS  
in register 12.  
3
PCM1608  
www.ti.com  
SBAS164B–DECEMBER 2000–REVISED JULY 2005  
ELECTRICAL CHARACTERISTICS (continued)  
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, system clock = 384 fS (fS = 44.1 kHz), and 24-bit data, unless  
otherwise noted  
PARAMETER  
PCM1608KY  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
VOUT = 0 dB, fS = 44.1 kHz  
VOUT = 0 dB, fS = 96 kHz  
VOUT = 0 dB, fS = 192 kHz  
VOUT = –60 dB, fS = 44.1 kHz  
VOUT = –60 dB, fS = 96 kHz  
VOUT = –60 dB, fS = 192 kHz  
EIAJ, A-weighted, fS = 44.1 kHz  
A-weighted, fS = 96 kHz  
A-weighted, fS = 192 kHz  
EIAJ, A-weighted, fS = 44.1 kHz  
A-weighted, fS = 96 kHz  
A-weighted, fS = 192 kHz  
fS = 44.1 kHz  
0.002%  
0.004%  
0.005%  
0.7%  
0.9%  
1%  
0.008%  
THD+N  
Total harmonic distortion + noise  
98  
98  
94  
105  
Dynamic range  
103  
dB  
dB  
102  
105  
SNR  
Signal-to-noise ratio  
103  
102  
103  
Channel separation  
Level linearity error  
fS = 96 kHz  
101  
dB  
dB  
fS = 192 kHz  
100  
VOUT = –90 dB  
±0.5  
DC ACCURACY  
Gain error  
±1  
±1  
±6 % of FSR  
±3 % of FSR  
Gain mismatch, channel-to-channel  
Bipolar zero error  
VOUT = 0.5 VCC at bipolar zero  
Full scale (–0 dB)  
AC load  
±30  
±60  
mV  
ANALOG OUTPUT  
Output voltage  
Center voltage  
0.62 VCC  
0.5 VCC  
Vp-p  
Vdc  
kΩ  
Load impedance  
5
DIGITAL FILTER PERFORMANCE  
Group delay time  
20/fS  
De-emphasis error  
Filter Characteristics 1, Sharp Rolloff  
Pass band  
±0.1  
dB  
±0.03 dB  
0.454 fS  
0.487 fS  
Pass band  
–3 dB  
Stop band  
0.546 fS  
Pass-band ripple  
±0.03  
dB  
dB  
dB  
Stop-band attenuation  
Stop-band attenuation  
Filter Characteristics 2, Slow Rolloff  
Pass band  
Stop band = 0.546 fS  
Stop band = 0.567 fS  
–50  
–55  
±0.5 dB  
0.198 fS  
0.39 fS  
Pass band  
–3 dB  
Stop band  
0.884 fS  
–40  
Pass-band ripple  
±0.5  
dB  
dB  
Stop-band attenuation  
ANALOG FILTER PERFORMANCE  
Stop band = 0.884 fS  
f = 20 kHz  
f = 44 kHz  
–0.03  
–0.2  
Frequency response  
dB  
4
PCM1608  
www.ti.com  
SBAS164B–DECEMBER 2000–REVISED JULY 2005  
ELECTRICAL CHARACTERISTICS (continued)  
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, system clock = 384 fS (fS = 44.1 kHz), and 24-bit data, unless  
otherwise noted  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
(5)  
POWER-SUPPLY REQUIREMENTS  
VDD  
3
3.3  
5
3.6  
5.5  
25  
Voltage range  
VCC  
Vdc  
4.5  
fS = 44.1 kHz  
18  
(6)  
IDD  
fS = 96 kHz  
fS = 192 kHz  
fS = 44.1 kHz  
fS = 96 kHz  
fS = 192 kHz  
fS = 44.1 kHz  
fS = 96 kHz  
fS = 192 kHz  
40  
40  
Supply current  
mA  
33  
46  
ICC  
36  
36  
224  
312  
312  
313  
Power dissipation  
mW  
TEMPERATURE RANGE  
TA  
Operation temperature  
Thermal resistance  
–25  
85  
°C  
θJA  
100  
°C/W  
(5) Conditions in 192-kHz operation are: system clock = 128 fS, DAC3 through DAC6 disabled in register 8, and oversampling rate = 64 fS  
in register 12.  
(6) SCKO is disabled.  
5
PCM1608  
www.ti.com  
SBAS164B–DECEMBER 2000–REVISED JULY 2005  
FUNCTIONAL BLOCK DIAGRAM  
V
1
2
3
4
5
6
7
8
Output Amp and  
Low-Pass Filter  
OUT  
DAC  
DAC  
BCK  
LRCK  
Output Amp and  
Low-Pass Filter  
V
V
V
V
V
V
OUT  
OUT  
OUT  
OUT  
OUT  
OUT  
OUT  
Serial  
Input  
I/F  
DATA1 (1, 2)  
DATA2 (3, 4)  
DATA3 (5, 6)  
DATA4 (7, 8)  
Output Amp and  
Low-Pass Filter  
DAC  
4× / 8×  
Output Amp and  
Low-Pass Filter  
DAC  
DAC  
DAC  
DAC  
DAC  
Oversampling  
Digital Filter  
with  
Function  
Controller  
Enhanced  
Multilevel  
Delta-Sigma  
Modulator  
Output Amp and  
Low-Pass Filter  
TEST  
RST  
ML  
Output Amp and  
Low-Pass Filter  
Function  
Control  
I/F  
Output Amp and  
Low-Pass Filter  
MC  
MDI  
MDO  
V
V
Output Amp and  
Low-Pass Filter  
COM  
System Clock  
System Clock  
Manager  
SCKI  
Zero Detect  
Power Supply  
B0033-03  
6
PCM1608  
www.ti.com  
SBAS164B–DECEMBER 2000–REVISED JULY 2005  
PT PACKAGE  
(TOP VIEW)  
36 35 34 33 32 31 30 29 28 27 26 25  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
RST  
SCKI  
SCKO  
BCK  
V
3
CC  
AGND3  
V
CC  
4
AGND4  
LRCK  
TEST  
V
OUT  
8
AGND6  
PCM1608  
V
DD  
V
CC  
5
DGND  
DATA1  
DATA2  
DATA3  
ZEROA  
AGND5  
V
V
V
V
7
OUT  
COM  
1
OUT  
2
OUT  
1
2
3
4
5
6
7
8
9
10 11 12  
P0028-02  
TERMINAL FUNCTIONS  
TERMINAL  
I/O  
DESCRIPTION  
NAME  
NO.  
27  
25  
23  
21  
17  
19  
40  
45  
46  
47  
31  
44  
41  
35  
34  
33  
AGND1  
AGND2  
AGND3  
AGND4  
AGND5  
AGND6  
BCK  
–
–
–
–
–
–
I
Analog ground  
Analog ground  
Analog ground  
Analog ground  
Analog ground  
Analog ground  
(1)  
Shift clock input for serial audio data. Clock must be one of 32 fS, 48 fS, or 64 fS.  
(1)  
DATA1  
DATA2  
DATA3  
DATA4  
DGND  
LRCK  
I
Serial audio data input for VOUT1 and VOUT  
Serial audio data input for VOUT3 and VOUT  
Serial audio data input for VOUT5 and VOUT  
Serial audio data input for VOUT7 and VOUT  
Digital ground  
2
4
6
8
(1)  
(1)  
(1)  
I
I
I
–
I
(1)  
Left and right clock input. This clock is equal to the sampling rate, fS.  
(2)  
MC  
I
Shift clock for serial control port  
(2)  
MDI  
I
Serial data input for serial control port  
(3)  
MDO  
O
Serial data output for serial control port  
(1) Schmitt-trigger input, 5-V tolerant  
(2) Schmitt-trigger input with internal pulldown, 5-V tolerant  
(3) 3-state output  
7
PCM1608  
www.ti.com  
SBAS164B–DECEMBER 2000–REVISED JULY 2005  
TERMINAL FUNCTIONS (continued)  
TERMINAL  
I/O  
DESCRIPTION  
NAME  
ML  
NO.  
36  
(2)  
I
–
I
Latch enable for serial control port  
No connection  
NC  
7, 8, 29  
37  
(2)  
RST  
SCKI  
System reset, active-low  
(1)  
38  
I
System clock input. Input frequency is one of 128 fS, 192 fS, 256 fS, 384 fS, 512 fS, or 768 fS.  
Buffered clock output. Output frequency is one of 128 fS, 192 fS, 256 fS, 384 fS, 512 fS, or 768  
fS, or one-half of 128 fS, 192 fS, 256 fS, 384 fS, 512 fS, or 768 fS.  
SCKO  
TEST  
39  
O
(2)  
42  
28  
26  
24  
22  
18  
15  
43  
14  
13  
12  
11  
10  
9
–
–
Test pin. This pin should be connected to DGND.  
VCC  
VCC  
VCC  
VCC  
VCC  
1
2
3
4
5
Analog power supply, 5-V  
–
Analog power supply, 5-V  
–
Analog power supply, 5-V  
–
Analog power supply, 5-V  
–
Analog power supply, 5-V  
VCOM  
VDD  
O
–
Common voltage output. This pin should be bypassed with a 10-µF capacitor to AGND.  
Digital power supply, 3.3-V  
VOUT  
VOUT  
VOUT  
VOUT  
VOUT  
VOUT  
VOUT  
VOUT  
1
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Voltage output of audio signal corresponding to Lch on DATA1. Up to 192 kHz.  
Voltage output of audio signal corresponding to Rch on DATA1. Up to 192 kHz.  
Voltage output of audio signal corresponding to Lch on DATA2. Up to 96 kHz.  
Voltage output of audio signal corresponding to Rch on DATA2. Up to 96 kHz.  
Voltage output of audio signal corresponding to Lch on DATA3. Up to 96 kHz.  
Voltage output of audio signal corresponding to Rch on DATA3. Up to 96 kHz.  
Voltage output of audio signal corresponding to Lch on DATA4. Up to 192 kHz.  
Voltage output of audio signal corresponding to Rch on DATA4. Up to 192 kHz.  
Zero-data flag for VOUT1. Can also be used as GPO pin.  
Zero-data flag for VOUT2. Can also be used as GPO pin.  
Zero-data flag for VOUT3. Can also be used as GPO pin.  
Zero-data flag for VOUT4. Can also be used as GPO pin.  
Zero-data flag for VOUT5. Can also be used as GPO pin.  
Zero-data flag for VOUT6. Can also be used as GPO pin.  
2
3
4
5
6
7
8
16  
20  
1
ZERO1/GPO1  
ZERO2/GPO2  
ZERO3/GPO3  
ZERO4/GPO4  
ZERO5/GPO5  
ZERO6/GPO6  
ZERO7  
2
3
4
5
6
30  
32  
48  
Zero-data flag for VOUT  
Zero-data flag for VOUT  
7
8
ZERO8  
ZEROA  
Zero-data flag. Logical AND of ZERO1 through ZERO6  
8
PCM1608  
www.ti.com  
SBAS164B–DECEMBER 2000–REVISED JULY 2005  
TYPICAL PERFORMANCE CURVES  
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, fS = 44.1 kHz, system clock = 384 fS, and 24-bit input data, unless  
otherwise noted  
Digital Filter (De-Emphasis Off)  
FREQUENCY RESPONSE (SHARP ROLLOFF)  
PASS-BAND FREQUENCY RESPONSE (SHARP ROLLOFF)  
0
−20  
0.05  
0.04  
0.03  
−40  
0.02  
0.01  
−60  
0.00  
−80  
−0.01  
−0.02  
−0.03  
−0.04  
−0.05  
−100  
−120  
−140  
0
1
2
3
4
0.0  
0.1  
0.2  
0.3  
0.4  
0.5  
Frequency [× f ]  
Frequency [× f ]  
S
S
G001  
G002  
Figure 1.  
Figure 2.  
FREQUENCY RESPONSE (SLOW ROLLOFF)  
TRANSITION CHARACTERISTICS (SLOW ROLLOFF)  
0
−20  
5
4
3
−40  
2
1
−60  
0
−80  
−1  
−2  
−3  
−4  
−5  
−100  
−120  
−140  
0
1
2
3
4
0.0  
0.1  
0.2  
0.3  
0.4  
0.5  
Frequency [× f ]  
Frequency [× f ]  
S
S
G003  
G004  
Figure 3.  
Figure 4.  
9
PCM1608  
www.ti.com  
SBAS164B–DECEMBER 2000–REVISED JULY 2005  
TYPICAL PERFORMANCE CURVES (continued)  
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, fS = 44.1 kHz, system clock = 384 fS, and 24-bit input data, unless  
otherwise noted  
Digital Filter (De-Emphasis Curves)  
DE-EMPHASIS (fS = 32 kHz)  
DE-EMPHASIS ERROR (fS = 32 kHz)  
0
−1  
−2  
−3  
−4  
−5  
−6  
−7  
−8  
−9  
−10  
0.5  
0.4  
0.3  
0.2  
0.1  
0.0  
−0.1  
−0.2  
−0.3  
−0.4  
−0.5  
0
0
0
2
4
6
8
10  
12  
14  
0
0
0
2
4
6
8
10  
12  
14  
f − Frequency − kHz  
f − Frequency − kHz  
G005  
G006  
Figure 5.  
Figure 6.  
DE-EMPHASIS (fS = 44.1 kHz)  
DE-EMPHASIS ERROR (fS = 44.1 kHz)  
0
−1  
−2  
−3  
−4  
−5  
−6  
−7  
−8  
−9  
−10  
0.5  
0.4  
0.3  
0.2  
0.1  
0.0  
−0.1  
−0.2  
−0.3  
−0.4  
−0.5  
2
4
6
8
10  
12  
14  
16  
18  
20  
2
4
6
8
10  
12  
14  
16  
18  
20  
f − Frequency − kHz  
f − Frequency − kHz  
G007  
G008  
Figure 7.  
Figure 8.  
DE-EMPHASIS (fS = 48 kHz)  
DE-EMPHASIS ERROR (fS = 48 kHz)  
0
−1  
−2  
−3  
−4  
−5  
−6  
−7  
−8  
−9  
−10  
0.5  
0.4  
0.3  
0.2  
0.1  
0.0  
−0.1  
−0.2  
−0.3  
−0.4  
−0.5  
2
4
6
8
10 12 14 16 18 20 22  
2
4
6
8
10 12 14 16 18 20 22  
f − Frequency − kHz  
f − Frequency − kHz  
G009  
G010  
Figure 9.  
Figure 10.  
10  
PCM1608  
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SBAS164B–DECEMBER 2000–REVISED JULY 2005  
TYPICAL PERFORMANCE CURVES (continued)  
ANALOG DYNAMIC PERFORMANCE  
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, and 24-bit input data, unless otherwise noted. Conditions in 192-kHz  
operation are system clock = 128 fS, DAC3 through DAC6 disabled in register 8, and oversampling rate = 64 fS (set by OVER  
bit in register 12).  
Supply-Voltage Characteristics  
TOTAL HARMONIC DISTORTION + NOISE  
DYNAMIC RANGE  
vs  
VCC (VDD = 3.3 V)  
vs  
VCC (VDD = 3.3 V)  
110  
108  
106  
104  
102  
100  
98  
10  
−60dB/192kHz, 128f  
−60dB/96kHz, 384f  
S
S
44.1kHz, 384f  
S
1
0.1  
−60dB/44.1kHz, 384f  
S
96kHz, 384f  
S
0dB/192kHz, 128f  
S
0dB/96kHz, 384f  
S
0.01  
192kHz, 128f  
S
0.001  
0dB/44.1kHz, 384f  
S
96  
0.0001  
4.0  
4.5  
5.0  
5.5  
6.0  
4.0  
4.5  
5.0  
5.5  
6.0  
V
CC  
− Supply Voltage − V  
G012  
V
CC  
− Supply Voltage − V  
G011  
Figure 11.  
Figure 12.  
SIGNAL-TO-NOISE RATIO  
vs  
CHANNEL SEPARATION  
vs  
VCC (VDD = 3.3 V)  
VCC (VDD = 3.3 V)  
110  
108  
106  
104  
102  
100  
98  
110  
108  
106  
104  
102  
100  
98  
44.1kHz, 384f  
S
96kHz, 384f  
S
44.1kHz, 384f  
S
96kHz, 384f  
S
192kHz, 128f  
S
192kHz, 128f  
S
96  
96  
4.0  
4.5  
5.0  
5.5  
6.0  
4.0  
4.5  
5.0  
5.5  
6.0  
V
CC  
− Supply Voltage − V  
V
CC  
− Supply Voltage − V  
G013  
G014  
Figure 13.  
Figure 14.  
11  
PCM1608  
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SBAS164B–DECEMBER 2000–REVISED JULY 2005  
TYPICAL PERFORMANCE CURVES (continued)  
ANALOG DYNAMIC PERFORMANCE (continued)  
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, and 24-bit input data, unless otherwise noted. Conditions in 192-kHz  
operation are system clock = 128 fS, DAC3 through DAC6 disabled in register 8, and oversampling rate = 64 fS (set by OVER  
bit in register 12).  
Temperature Characteristics  
TOTAL HARMONIC DISTORTION + NOISE  
DYNAMIC RANGE  
vs  
TEMPERATURE (TA)  
vs  
TEMPERATURE (TA)  
110  
108  
106  
104  
102  
100  
98  
10  
−60dB/96kHz, 384f  
−60dB/192kHz, 128f  
S
S
44.1kHz, 384f  
S
1
0.1  
96kHz, 384f  
S
−60dB/44.1kHz, 384f  
S
0dB/192kHz, 128f  
S
0dB/96kHz, 384f  
S
192kHz, 128f  
S
0.01  
0.001  
0dB/44.1kHz, 384f  
S
96  
0.0001  
−50  
−25  
0
25  
50  
75  
100  
−50  
−25  
0
25  
50  
75  
100  
T
A
− Free-Air Temperature − °C  
G016  
T
A
− Free-Air Temperature − °C  
G015  
Figure 15.  
Figure 16.  
SIGNAL-TO-NOISE RATIO  
vs  
CHANNEL SEPARATION  
vs  
TEMPERATURE (TA)  
TEMPERATURE (TA)  
110  
108  
106  
104  
102  
100  
98  
110  
108  
106  
104  
102  
100  
98  
44.1kHz, 384f  
S
44.1kHz, 384f  
96kHz, 384f  
S
S
96kHz, 384f  
S
192kHz, 128f  
S
192kHz, 128f  
S
96  
96  
−50  
−25  
0
25  
50  
75  
100  
−50  
−25  
0
25  
50  
75  
100  
T
A
− Free-Air Temperature − °C  
T
A
− Free-Air Temperature − °C  
G017  
G018  
Figure 17.  
Figure 18.  
12  
PCM1608  
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SBAS164B–DECEMBER 2000–REVISED JULY 2005  
SYSTEM CLOCK AND RESET FUNCTIONS  
SYSTEM CLOCK INPUT  
The PCM1608 requires a system clock for operating the digital interpolation filters and multilevel delta-sigma  
modulators. The system clock is applied at the SCKI input (pin 38). Table 1 shows examples of system clock  
frequencies for common audio sampling rates.  
Figure 19 shows the timing requirements for the system clock input. For optimal performance, it is important to  
use a clock source with low phase jitter and noise. The PLL170x multiclock generator from Texas Instruments is  
an excellent choice for providing the PCM1608 system clock.  
The 192-kHz sampling frequency operation is available on DATA1 for VOUT1 and VOUT2 and on DATA4 for VOUT  
7
and VOUT8. It is recommended that VOUT3, VOUT4, VOUT5, and VOUT6 be disabled when operating with  
fS = 192 kHz. This can be done by setting the DAC3, DAC4, DAC5, and DAC6 bits of register 8 to a logic-1 state.  
Table 1. System Clock Rates for Common Audio Sampling Frequencies  
SAMPLING FREQUENCY  
(kHz)  
SYSTEM CLOCK FREQUENCY (fSCLK) (MHz)  
128 fS  
192 fS  
256 fS  
2.048  
384 fS  
3.072  
512 fS  
4.096  
768 fS  
6.144  
(1)  
(1)  
8
16  
(1)  
(1)  
(1)  
(1)  
(1)  
(1)  
(1)  
(1)  
(1)  
(1)  
4.096  
6.144  
8.192  
12.288  
24.576  
33.8688  
32  
8.192  
12.288  
16.9344  
18.432  
16.384  
22.5792  
24.576  
44.1  
48  
11.2896  
12.288  
36.864  
(1)  
96  
24.576  
36.864  
49.152  
(1)  
(1)  
(1)  
(1)  
192  
24.576  
36.864  
(1) This system clock is not supported for the given sampling frequency.  
t
w(SCKH)  
H
2 V  
System Clock  
0.8 V  
L
System Clock  
Pulse Cycle  
t
w(SCKL)  
(1)  
Time  
T0005A08  
SYMBOL  
tw(SCKH)  
tw(SCKL)  
PARAMETER  
MIN  
7
MAX  
UNIT  
ns  
System clock pulse duration, HIGH  
System clock pulse duration, LOW  
7
ns  
(1) 1/128 fS, 1/256 fS, 1/384 fS, 1/512 fS, and 1/768 fS.  
Figure 19. System Clock Timing  
SYSTEM CLOCK OUTPUT  
A buffered version of the system clock input is available at the SCKO output (pin 39). SCKO can operate at  
either full (fSCKI) or half (fSCKI/2) rate. The SCKO output frequency can be programmed using the CLKD bit of  
register 9. The SCKO output pin can also be enabled or disabled using the CLKE bit of register 9. If the SCKO  
output is not required, it is recommended to disable it using the CLKE bit. The default is SCKO enabled.  
13  
 
 
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SBAS164B–DECEMBER 2000–REVISED JULY 2005  
POWER-ON AND EXTERNAL RESET FUNCTIONS  
The PCM1608 includes a power-on-reset function, as shown in Figure 20. With the system clock active, and VDD  
> 2 V (typical, 1.6 V to 2.4 V), the power-on-reset function is enabled. The initialization sequence requires 1024  
system clocks from the time VDD > 2 V. After the initialization period, the PCM1608 is set to its reset default  
state, as described in the Mode Control Registers section of this data sheet.  
The PCM1608 also includes an external reset capability using the RST input (pin 37). This allows an external  
controller or master reset circuit to force the PCM1608 to initialize to its reset default state. For normal operation,  
RST should be set to a logic-1.  
The external reset operation and timing is shown in Figure 21. The RST pin is set to logic-0 for a minimum of  
20 ns. After the initialization sequence is completed, the PCM1608 is set to its reset default state, as described in  
the Mode Control Registers section of this data sheet.  
During the reset period (1024 system clocks), the analog outputs are forced to the bipolar zero level (or VCC/2).  
After the reset period, the internal registers are initialized in the next 1/fS period and, if SCKI, BCK, and LRCK  
are provided continuously, the PCM1608 provides proper analog output with the group delay time given in the  
Electrical Characteristics section of this data sheet.  
The external reset is especially useful in applications where there is a delay between PCM1608 power-up and  
system-clock activation. In this case, the RST pin should be held at a logic-0 level until the system clock has  
been activated.  
2.4 V  
2 V  
1.6 V  
V
DD  
0 V  
Reset  
Reset Removal  
Internal Reset  
System Clock  
Don’t Care  
1024 System Clocks  
T0014-08  
Figure 20. Power-On-Reset Timing  
RST  
Reset  
Reset Removal  
Internal Reset  
System Clock  
1024 System Clocks  
T0015-06  
Figure 21. External Reset Timing  
14  
 
 
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SBAS164B–DECEMBER 2000–REVISED JULY 2005  
AUDIO SERIAL INTERFACE  
The audio serial interface for the PCM1608 consists of a 5-wire synchronous serial port. It includes LRCK  
(pin 41), BCK (pin 40), DATA1 (pin 45), DATA2 (pin 46), DATA3 (pin 47), and DATA4 (pin 31). BCK is the serial  
audio bit clock, and is used to clock the serial data present on DATA1, DATA2, DATA3, and DATA4 into the  
audio interface serial shift register. Serial data is clocked into the PCM1608 on the rising edge of BCK. LRCK is  
the serial audio left/right word clock. It is used to latch serial data into the serial audio interface internal registers.  
Both LRCK and BCK must be synchronous to the system clock. Ideally, it is recommended that LRCK and BCK  
be derived from the system clock input, SCKI. LRCK is operated at the sampling frequency (fS). BCK can be  
operated at 32, 48, or 64 times the sampling frequency (I2S format does not support BCK = 32 fS).  
Internal operation of the PCM1608 is synchronized with LRCK. Accordingly, internal operation of the device is  
suspended when the sampling rate clock (LRCK) is changed, or when SCKI and/or BCK is interrupted at least for  
a 3-bit clock cycle. If SCKI, BCK, and LRCK are provided continuously after this suspended state, the internal  
operation is resynchronized automatically within a period of less than 3/fS. During this resynchronization period  
and for a 3/fS time thereafter, the analog outputs are forced to the bipolar zero level, VCC/2. External resetting is  
not required.  
AUDIO DATA FORMATS AND TIMING  
The PCM1608 supports industry-standard audio data formats, including standard, I2S, and left-justified (see  
Figure 22). Data formats are selected using the format bits, FMT[2:0], in register 9. The default data format is  
24-bit standard. All formats require binary 2s complement, MSB-first audio data. See Figure 23 for a detailed  
timing diagram of the serial audio interface.  
DATA1, DATA2, DATA3, and DATA4 each carry two audio channels, designated as the left and right channels.  
The left-channel data always precedes the right-channel data in the serial data stream for all data formats.  
Table 2 shows the mapping of the digital input data to the analog output pins.  
15  
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SBAS164B–DECEMBER 2000–REVISED JULY 2005  
(1) Standard Data Format; L-Channel = HIGH, R-Channel = LOW  
1/f  
S
LRCK  
BCK  
L-Channel  
R-Channel  
(= 32 f , 48 f or 64 f  
S,  
)
S
S
16-Bit Right-Justified, BCK = 32 f  
S
DATA 14 15 16  
1
2
3
14 15 16  
1
2
3
14 15 16  
LSB  
MSB  
LSB  
MSB  
16-Bit Right-Justified, BCK = 48 f or 64 f  
S
S
DATA 14 15 16  
1
3
2
3
14 15 16  
LSB  
1
3
2
3
14 15 16  
LSB  
MSB  
MSB  
18-Bit Right-Justified  
DATA 16 17 18  
1
3
2
16 17 18  
LSB  
1
3
2
16 17 18  
LSB  
MSB  
MSB  
20-Bit Right-Justified  
18 19 20  
1
3
2
18 19 20  
LSB  
1
3
2
18 19 20  
LSB  
DATA  
MSB  
MSB  
24-Bit Right-Justified  
22 23 24  
1
2
22 23 24  
LSB  
1
2
22 23 24  
LSB  
DATA  
MSB  
MSB  
2
(2) I S Data Format; L-Channel = LOW, R-Channel = HIGH  
1/f  
S
LRCK  
BCK  
L-Channel  
R-Channel  
(= 48 f or 64 f  
S,  
)
S
N–2 N–1  
N–2 N–1  
1
2
3
N
1
2
3
N
1
2
DATA  
MSB  
LSB  
MSB  
LSB  
(3) Left-Justified Data Format; L-Channel = HIGH, R-Channel = LOW  
1/f  
S
LRCK  
BCK  
L-Channel  
R-Channel  
(= 48 f or 64 f  
S,  
)
S
N–2 N–1  
N–2 N–1  
DATA  
1
2
3
N
1
2
3
N
1
2
MSB  
LSB  
MSB  
LSB  
T0009-05  
Figure 22. Audio Data Input Formats  
16  
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SBAS164B–DECEMBER 2000–REVISED JULY 2005  
1.4 V  
LRCK  
t
t
t
(BCL)  
(LB)  
(BCH)  
1.4 V  
BCK  
t
t
(BL)  
(BCY)  
DATA1, DATA2,  
DATA3, DATA4  
1.4 V  
t
(DS)  
t
(DH)  
T0010-07  
SYMBOL  
t(BCY)  
t(BCH)  
t(BCL)  
t(BL)  
PARAMETER  
MIN  
1/(64 fS  
35  
MAX  
UNITS  
(1)  
BCK pulse cycle time  
BCK high-level time  
)
ns  
ns  
ns  
ns  
ns  
ns  
BCK low-level time  
35  
BCK rising edge to LRCK edge  
10  
t(LB)  
LRCK falling edge to BCK rising edge  
DATA setup time  
10  
t(DS)  
10  
t(DH)  
DATA hold time  
10  
(1) fS is the sampling frequency (e.g., 44.1 kHz, 48 kHz, 96 kHz, etc.)  
Figure 23. Audio Interface Timing  
Table 2. Audio Input Data to Analog Output Mapping  
DATA INPUT  
DATA1  
DATA1  
DATA2  
DATA2  
DATA3  
DATA3  
DATA4  
DATA4  
CHANNEL  
Left  
ANALOG OUTPUT  
(1)  
VOUT  
VOUT  
VOUT  
VOUT  
VOUT  
VOUT  
VOUT  
VOUT  
1
2
3
4
5
6
7
8
(1)  
(2)  
(2)  
(2)  
(2)  
(1)  
(1)  
Right  
Left  
Right  
Left  
Right  
Left  
Right  
(1) Up to 192 kHz  
(2) Up to 96 kHz, forced to bipolar zero when fS = 192 kHz.  
17  
PCM1608  
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SBAS164B–DECEMBER 2000–REVISED JULY 2005  
SERIAL CONTROL INTERFACE  
The serial control interface is a 4-wire synchronous serial port that operates asynchronously to the serial audio  
interface. The serial control interface is used to program and read the on-chip mode registers. The control  
interface includes MDO (pin 33), MDI (pin 34), MC (pin 35), and ML (pin 36). MDO is the serial data output, used  
to read back the values of the mode registers; MDI is the serial data input, used to program the mode registers;  
MC is the serial bit clock, used to shift data in and out of the control port; and ML is the control port latch clock.  
REGISTER WRITE OPERATION  
All write operations for the serial control port use 16-bit data words. Figure 24 shows the control data word  
format. The most significant bit is the read/write (R/W) bit. When set to 0, this bit indicates a write operation.  
Seven bits, labeled IDX[6:0], set the register index (or address) for the write operation. The least significant eight  
bits, D[7:0], contain the data to be written to the register specified by IDX[6:0].  
Figure 25 shows the functional timing diagram for writing to the serial control port. ML is held at a logic-1 state  
until a register is to be written. To start the register write cycle, ML is set to logic-0. Sixteen clocks are then  
provided on MC, corresponding to the 16 bits of the control data word on MDI. After the sixteenth clock cycle has  
completed, ML is set to logic-1 to latch the data into the indexed mode control register.  
MSB  
R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0  
LSB  
D0  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
Register Index (or Address)  
Register Data  
Read/Write Operation  
0 = Write Operation  
1 = Read Operation (Register Index is Ignored)  
R0001-02  
Figure 24. Control Data Word Format for MDI  
ML  
MC  
MDI  
X
R/W  
D7 D6 D5 D4 D3 D2  
D1 D0  
X
X
R/W  
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0  
IDX6  
T0048-02  
Figure 25. Write Operation Timing  
SINGLE REGISTER READ OPERATION  
Read operations use the 16-bit control word format shown in Figure 24. For read operations, the R/W bit is set  
to 1. Read operations ignore the index bits, IDX[6:0], of the control data word. Instead, the REG[6:0] bits in  
control register 11 are used to set the index of the register that is to be read during the read operation. Bits  
IDX[6:0] should be set to 00h for read operations.  
The details of the read operation are shown in Figure 26. First, control register 11 must be written with the index  
of the register to be read back. Additionally, the INC bit must be set to logic-0 in order to disable the  
auto-increment read function. The read cycle is then initiated by setting ML to logic-0 and setting the R/W bit of  
the control data word to logic-1, indicating a read operation. MDO remains in a high-impedance state until the  
last eight bits of the 16-bit read cycle, which correspond to the eight data bits of the register indexed by the  
REG[6:0] bits of control register 11. The read cycle is completed when ML is set to 1, immediately after the MC  
clock cycle for the least-significant bit of the indexed control register has completed.  
18  
 
 
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SBAS164B–DECEMBER 2000–REVISED JULY 2005  
INC = 1 (Auto-Increment Read)  
ML  
MC  
1
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
MDI  
High Impedance  
D7 D6 D5 D4 D3 D2 D1 D0  
INDEX “N”  
MDO  
ML  
MC  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
MDI  
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 High Impedance  
INDEX “N + 1” INDEX “Y”  
MDO  
INC = 0 (Single-Register Read)  
ML  
MC  
MDI  
1
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
High Impedance  
D7 D6 D5 D4 D3 D2 D1 D0  
INDEX “N”  
MDO  
T0075-01  
NOTES: X = Don’t care  
w
Y = Last register to be read  
w
In single-register read (INC = 0), the index which indicates the resister to be read in read operation can be set by  
REG[6:0] in register 11. For example, setting REG[6:0] = 000 1001b means reading from register 9.  
In auto-increment read (INC = 1), the index REG[6:0] indicates the first register to be read. For example, setting  
REG[6:0] = 000 1001b means reading registers from 9 to Y. Y is determined by the low-to-high transition of ML in  
serial mode control.  
Figure 26. Read Operation Timing  
AUTO-INCREMENT READ OPERATION  
The auto-increment read function allows for multiple registers to be read sequentially. The auto-increment read  
function is enabled by setting the INC bit of control register 11 to 1. The sequence always starts with the register  
indexed by the REG[6:0] bits in control register 11, and ends by the ML setting to 1 after MC clock cycle for the  
least-significant bit of last register.  
19  
 
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SBAS164B–DECEMBER 2000–REVISED JULY 2005  
Figure 26 shows the timing of the auto-increment read operation. The operation begins by writing control register  
11, setting INC to 1, and setting REG[6:0] to the first register to be read in the sequence. The actual read  
operation starts on the next HIGH-to-LOW transition of the ML pin.  
The read cycle starts by setting the R/W bit of the control word to 1, and setting all of the IDX[6:0] bits to 0. All  
subsequent bits input on MDI are ignored while ML is set to 0. For the first eight clocks of the read cycle, MDO is  
set to the high-impedance state. This is followed by a sequence of 8-bit words, each corresponding to the data  
contained in control registers N through Y, where N is defined by the REG[6:0] bits in control register 11, and  
where Y is the last register to be read. The read cycle is completed when ML is set to 1, immediately after the  
MC clock cycle for the least-significant bit of the last register has completed. If ML is held low and the MC clock  
continues beyond the last physical register (register 19), the read operation returns to control register 1 and  
subsequent control registers, continuing until ML is set to 1.  
CONTROL INTERFACE TIMING REQUIREMENTS  
Figure 27 shows a detailed timing diagram for the serial control interface. Pay special attention to the setup and  
hold times, as well as t(MLS) and t(MLH), which define minimum delays between the edges of the ML and MC  
clocks. These timing parameters are critical for proper control-port operation.  
t
(MHH)  
ML  
MC  
1.4 V  
t
t
(MCL)  
(MLS)  
t
t
(MCH)  
(MLH)  
1.4 V  
t
(MCY)  
LSB  
LSB  
MDI  
1.4 V  
t
(MDS)  
t
t
(MOS)  
(MDH)  
MDO  
50% of V  
DD  
T0013-05  
SYMBOL  
t(MCY)  
t(MCL)  
PARAMETER  
MIN  
100  
50  
MAX  
UNITS  
ns  
MC pulse cycle time  
MC low-level time  
MC high-level time  
ML high-level time  
ns  
t(MCH)  
t(MHH)  
t(MLS)  
50  
ns  
300  
20  
ns  
ML falling edge to MC rising edge  
ML hold time (1)  
ns  
t(MLH)  
20  
ns  
t(MDH)  
t(MDS)  
t(MOS)  
MDI hold time  
15  
ns  
MDL setup time  
20  
ns  
MC falling edge to MDO stable  
30  
ns  
(1) MC rising edge for LSB to ML rising edge.  
Figure 27. Control Interface Timing  
20  
 
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MODE CONTROL REGISTERS  
User-Programmable Mode Controls  
The PCM1608 includes a number of user-programmable functions that are accessed via control registers. The  
registers are programmed using the serial control interface that is previously discussed in this data sheet.  
Table 3 lists the available mode control functions, along with their reset default conditions and associated register  
index.  
Table 3. User-Programmable Mode Controls  
CONTROL  
REGISTER  
FUNCTION  
RESET DEFAULT  
BIT(S), INDEX  
AT1[7:0], AT2[7:0],  
AT3[7:0], AT4[7:0],  
AT5[7:0], AT6[7:0],  
AT7[7:0], AT8[7:0]  
1 through 6, 16,  
17  
Digital attenuation control, 0 dB to –63 dB in 0.5-dB steps  
0 dB, no attenuation  
Soft mute control  
Mute disabled  
7, 18  
MUT[8:1]  
DAC[8:1]  
FMT[2:0]  
FLT  
DAC1–DAC8 operation control  
Audio data format control  
Digital filter rolloff control  
SCKO frequency selection  
SCKO output enable  
DAC1–DAC8 enabled  
24-bit standard format  
Sharp rolloff  
8, 19  
9
9
9
9
Full rate (= fSCKI  
SCKO enabled  
)
CLKD  
CLKE  
De-emphasis, all channels  
disabled  
De-emphasis all-channel function control  
10  
DMC  
De-emphasis all-channel sample rate selection  
Output phase select  
44.1 kHz  
10  
10  
10  
11  
11  
12  
12  
12  
DMF[1:0]  
DREV  
Normal phase  
High  
Zero-flag polarity select  
ZREV  
Read-register index control  
REG[6:0] = 01h  
Auto-increment disabled  
Zero-flag enabled  
Disabled  
REG[6:0]  
INC  
Read auto-increment control  
General-purpose output enable  
General-purpose output bits (GPO1–GPO6)  
Oversampling rate control  
GPOE  
GPO[6:1]  
OVER  
64×  
21  
 
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Reserved Registers  
Registers 00h and 0Dh through 0Fh are reserved for factory use. To ensure proper operation, the user should  
not write to or read from these registers.  
Register Map  
The mode control register map is shown in Table 4. Each register includes an R/W bit that determines whether a  
register read (R/W = 1) or write (R/W = 0) operation is performed. Each register also includes an index (or  
address) indicated by the IDX[6:0] bits.  
Table 4. Mode Control Register Map  
IDX  
(B14–B8)  
REGIS- B15 B14  
TER  
B13  
B12  
B11  
B10  
B9  
B8  
B7  
B6  
B5  
B4  
B3  
B2  
B1  
B0  
01h  
02h  
03h  
04h  
05h  
06h  
07h  
08h  
09h  
0Ah  
0Bh  
0Ch  
10h  
11h  
12h  
13h  
1
2
R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0  
R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0  
R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0  
R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0  
R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0  
R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0  
AT17  
AT27  
AT37  
AT47  
AT57  
AT67  
AT16  
AT26  
AT36  
AT46  
AT56  
AT66  
AT15  
AT25  
AT35  
AT45  
AT55  
AT65  
AT14  
AT24  
AT34  
AT44  
AT54  
AT64  
MUT5  
DAC5  
CLKD  
AT13  
AT23  
AT33  
AT43  
AT53  
AT63  
MUT4  
DAC4  
CLKE  
DMF0  
REG3  
AT12  
AT22  
AT32  
AT42  
AT52  
AT62  
MUT3  
DAC3  
FMT2  
DMC  
REG2  
AT11  
AT21  
AT31  
AT41  
AT51  
AT61  
MUT2  
DAC2  
FMT1  
DMC  
REG1  
AT10  
AT20  
AT30  
AT40  
AT50  
AT60  
MUT1  
DAC1  
FMT0  
DMC  
REG0  
3
4
5
6
7
R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV(1) RSV(1) MUT6  
R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV(1) RSV(1) DAC6  
8
9
R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV(1) RSV(1)  
R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV(1) ZREV  
FLT  
10  
11  
12  
16  
17  
18  
19  
DREV DMF1  
REG5 REG4  
R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0  
INC  
REG6  
R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 OVER GPOE GPO6 GPO5 GPO4 GPO3 GPO2 GPO1  
R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0  
R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0  
AT77  
AT87  
AT76  
AT86  
AT75  
AT85  
AT74  
AT84  
AT73  
AT83  
AT72  
AT82  
AT71  
AT81  
AT70  
AT80  
MUT7  
DAC7  
R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV(1) RSV(1) RSV(1) RSV(1) RSV(1) RSV(1) MUT8  
R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV(1) RSV(1) RSV(1) RSV(1) RSV(1) RSV(1) DAC8  
(1) Reserved for test operation. It should be set to 0 during normal operation.  
22  
 
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REGISTER DEFINITIONS  
B15 B14 B13 B12 B11 B10  
B9  
B8  
B7  
B6  
B5  
B4  
B3  
B2  
B1  
B0  
REGISTER 1  
REGISTER 2  
REGISTER 3  
REGISTER 4  
REGISTER 5  
REGISTER 6  
R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT17 AT16 AT15 AT14 AT13 AT12 AT11 AT10  
R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT27 AT26 AT25 AT24 AT23 AT22 AT21 AT20  
R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT37 AT36 AT35 AT34 AT33 AT32 AT31 AT30  
R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT47 AT46 AT45 AT44 AT43 AT42 AT41 AT40  
R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT57 AT56 AT55 AT54 AT53 AT52 AT51 AT50  
R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT67 AT66 AT65 AT64 AT63 AT62 AT61 AT60  
REGISTER 16 R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT77 AT76 AT75 AT74 AT73 AT72 AT71 AT70  
REGISTER 17 R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT87 AT86 AT85 AT84 AT83 AT82 AT81 AT80  
R/W – Read/Write Mode Select  
When R/W = 0, a write operation is performed.  
When R/W = 1, a read operation is performed.  
Default value: 0  
ATx[7:0] – Digital Attenuation Level Setting  
where x = 1 through 8, corresponding to the DAC output VOUTx.  
These bits are read/write.  
Default value: 1111 1111b  
Each DAC output, VOUT1 through VOUT8, includes a digital attenuator function. The attenuation level can be set  
from 0 dB to –63 dB in 0.5-dB steps. Changes in attenuation levels are made by incrementing or decrementing  
by one step (0.5 dB) for every 8/fS time interval until the programmed attenuator setting is reached. Alternatively,  
the attenuation level can be set to infinite attenuation, or mute.  
The attenuation level is calculated using the following formula:  
Attenuation level (dB) = 0.5 (ATx[7:0]DEC – 255)  
where ATx[7:0]DEC = 0 through 255.  
For ATx[7:0]DEC = 0 through 128, the attenuator is set to infinite attenuation.  
The following table shows attenuation levels for various settings.  
ATx[7:0]  
1111 1111b  
1111 1110b  
1111 1101b  
:
DECIMAL VALUE  
ATTENUATOR LEVEL SETTING  
255  
254  
253  
:
0 dB, no attenuation (default)  
–0.5 dB  
–1 dB  
:
1000 0011b  
1000 0010b  
1000 0001b  
1000 0000b  
:
131  
130  
129  
128  
:
–62 dB  
–62.5 dB  
–63 dB  
Mute  
:
0000 0000b  
0
Mute  
23  
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SBAS164B–DECEMBER 2000–REVISED JULY 2005  
B15 B14 B13 B12 B11 B10  
B9  
B8  
B7  
B6  
B5  
B4  
B3  
B2  
B1  
B0  
REGISTER 7  
R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV  
RSV MUT6 MUT5 MUT4 MUT3 MUT2 MUT1  
REGISTER 18 R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV  
RSV  
RSV  
RSV  
RSV  
RSV MUT8 MUT7  
R/W – Read/Write Mode Select  
When R/W = 0, a write operation is performed.  
When R/W = 1, a read operation is performed.  
Default value: 0  
MUTx – Soft Mute Control  
Where x = 1 through 8, corresponding to the DAC output VOUTx.  
These bits are read/write.  
Default value: 0  
MUTx = 0  
MUTx = 1  
Mute disabled (default)  
Mute enabled  
The mute bits, MUT1 through MUT8, are used to enable or disable the soft mute function for the corresponding  
DAC outputs, VOUT1 through VOUT8. The soft mute function is incorporated into the digital attenuators. When  
mute is disabled (MUTx = 0), the attenuator and DAC operate normally. When mute is enabled by setting  
MUTx = 1, the digital attenuator for the corresponding output is decreased from the current setting to the infinite  
attenuation setting, one attenuator step (0.5 dB) at a time. This provides a quiet, pop-free muting of the DAC  
output. On returning from soft mute, by setting MUTx = 0, the attenuator is increased one step at a time to the  
previously programmed attenuation level.  
B15 B14 B13 B12 B11 B10  
B9  
B8  
B7  
B6  
B5  
B4  
B3  
B2  
B1  
B0  
REGISTER 8  
R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV  
RSV DAC6 DAC5 DAC4 DAC3 DAC2 DAC1  
REGISTER 19 R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV  
RSV  
RSV  
RSV  
RSV  
RSV DAC8 DAC7  
R/W – Read/Write Mode Select  
When R/W = 0, a write operation is performed.  
When R/W = 1, a read operation is performed.  
Default value: 0  
DACx – DAC Operation Control  
Where x = 1 through 8, corresponding to the DAC output VOUTx.  
These bits are read/write.  
Default value: 0  
DACx = 0  
DACx = 1  
DAC operation enabled (default)  
DAC operation disabled  
The DAC operation controls are used to enable and disable the DAC outputs, VOUT1 through VOUT8. When  
DACx = 0, the output amplifier input is connected to the DAC output. When DACx = 1, the output amplifier input  
is switched to the dc common-mode voltage (VCOM), equal to VCC/2.  
24  
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B15 B14 B13 B12 B11 B10  
B9  
B8  
B7  
B6  
B5  
B4  
B3  
B2  
B1  
B0  
REGISTER 9  
R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV  
RSV  
FLT  
CLKD CLKE FMT2 FMT1 FMT0  
R/W – Read/Write Mode Select  
When R/W = 0, a write operation is performed.  
When R/W = 1, a read operation is performed.  
Default value: 0  
FLT – Digital Filter Rolloff Control  
This bit is read/write.  
Default value: 0  
FLT = 0  
FLT = 1  
Sharp rolloff (default)  
Slow rolloff  
The FLT bit allows users to select the digital filter rolloff that is best suited to their application. Two filter rolloff  
selections are available: sharp or slow. The filter responses for these selections are shown in the Typical  
Performance Curves section of this data sheet.  
CLKD – SCKO Frequency Selection  
This bit is read/write.  
Default value: 0  
CLKD = 0  
CLKD = 1  
Full-rate, fSCKO = fSCKI (default)  
Half-rate, fSCKO = fSCKI/2  
The CLKD bit is used to determine the clock frequency at the system clock output pin, SCKO.  
CLKE – SCKO Output Enable  
This bit is read/write.  
Default value: 0  
CLKE = 0  
CLKE = 1  
SCKO enabled (default)  
SCKO disabled  
The CLKE bit is used to enable or disable the system clock output pin, SCKO. When SCKO is enabled, it outputs  
either a full- or half-rate clock, based on the setting of the CLKD bit. When SCKO is disabled, it is set to a LOW  
level.  
FMT[2:0] – Audio Interface Data Format  
These bits are read/write.  
Default value: 000b  
FMT[2:0]  
000  
Audio Data Format Selection  
24-bit standard format, right-justified data (default)  
20-bit standard format, right-justified data  
18-bit standard format, right-justified data  
16-bit standard format, right-justified data  
I2S format, 16- to 24-bit  
001  
010  
011  
100  
101  
Left-justified format, 16- to 24-bit  
Reserved  
110  
111  
Reserved  
The FMT[2:0] bits are used to select the data format for the serial audio interface.  
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SBAS164B–DECEMBER 2000–REVISED JULY 2005  
B15 B14 B13 B12 B11 B10  
B9  
B8  
B7  
B6  
B5  
B4  
B3  
B2  
B1  
B0  
REGISTER 10 R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV ZREV DREV DMF1 DMF0 DMC  
DMC DMC  
R/W – Read/Write Mode Select  
When R/W = 0, a write operation is performed.  
When R/W = 1, a read operation is performed.  
Default value: 0  
ZREV – Zero-Flag Polarity Select  
Default value: 0  
ZREV = 0  
ZREV = 1  
Zero-flag pins HIGH at a zero detect (default)  
Zero-flag pins LOW at a zero detect  
The ZREV bit allows the user to select the polarity of zero-flag pins.  
DREV – Output Phase Select  
Default value: 0  
DREV = 0  
DREV = 1  
Normal output (default)  
Inverted output  
The DREV bit allows the user to select the phase of analog output signal.  
DMF[1:0] – Sampling Frequency Selection for the De-Emphasis Function  
These bits are read/write.  
Default value: 00b  
DMF[1:0]  
De-Emphasis Sample Rate Selection  
00  
01  
10  
11  
44.1 kHz (default)  
48 kHz  
32 kHz  
Reserved  
The DMF[1:0] bits are used to select the sampling frequency used for the digital de-emphasis function when it is  
enabled. The de-emphasis curves are shown in the Typical Performance Curves section of this data sheet. The  
preceding table shows the available sampling frequencies.  
DMC – Digital De-Emphasis, All-Channel Function Control  
This bit is read/write.  
Default value: 0  
DMC = 0  
DMC = 1  
De-emphasis disabled for all channels (default)  
De-emphasis enabled for all channels  
The DMC bits are used to enable or disable the de-emphasis function for all channels. The three DMC bits are  
ORed together. Setting any one DMC bit, any combination of two DMC bits, or all three DMC bits to 1 enables  
digital de-emphasis for all channels. Setting all three DMC bits to 0 disables digital de-emphasis for all channels.  
26  
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SBAS164B–DECEMBER 2000–REVISED JULY 2005  
B15 B14 B13 B12 B11 B10  
B9  
B8  
B7  
B6  
B5  
B4  
B3  
B2  
B1  
B0  
REGISTER 11 R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 INC  
REG6 REG5 REG4 REG3 REG2 REG1 REG0  
R/W – Read/Write Mode Select  
When R/W = 0, a write operation is performed.  
When R/W = 1, a read operation is performed.  
Default value: 0  
INC – Auto-Increment Read Control  
This bit is read/write.  
Default value: 0  
INC = 0  
INC = 1  
Auto-increment read disabled (default)  
Auto-increment read enabled  
The INC bit is used to enable or disable the auto-increment read feature of the serial control interface. See the  
Serial Control Interface section of this data sheet for details regarding auto-increment read operation.  
REG[6:0] – Read Register Index  
These bits are read/write.  
Default value: 01h  
The REG[6:0] bits are used to set the index of the register to be read when performing the single-register read  
operation. In the case of an auto-increment read operation, the REG[6:0] bits indicate the index of the last  
register to be read in the auto-increment read sequence. For example, if registers 1 through 6 are to be read  
during an auto-increment read operation, the REG[6:0] bits would be set to 06h. See the Serial Control Interface  
section of this data sheet for details regarding the single-register and auto-increment read operations.  
27  
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B15 B14 B13 B12 B11 B10  
B9  
B8  
B7  
B6  
B5  
B4  
B3  
B2  
B1  
B0  
REGISTER 12 R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 OVER GPOE GPO6 GPO5 GPO4 GPO3 GPO2 GPO1  
R/W – Read/Write Mode Select  
When R/W = 0, a write operation is performed.  
When R/W = 1, a read operation is performed.  
Default value: 0  
OVER – Oversampling Rate Control  
This bit is read/write.  
Default value: 0  
x
System clock rate = 256 fS, 384 fS, 512 fS, or 768 fS:  
OVER = 0  
OVER = 1  
64× oversampling (default)  
128× oversampling  
x
System clock rate = 128 fS or 192 fS:  
OVER = 0  
OVER = 1  
32× oversampling (default)  
64× oversampling  
The OVER bit is used to control the oversampling rate of the delta-sigma DACs. The OVER = 1 setting is  
recommended when the oversampling rate is 192 kHz (system clock rate is 128 fS or 192 fS).  
GPOE – General-Purpose Output Enable  
This bit is read/write.  
Default value: 0  
GPOE = 0  
General-purpose outputs disabled (default)  
Pins default to zero-flag function (ZERO1 through ZERO6).  
GPOE = 1  
General-purpose outputs enabled  
Data written to GPO1 through GPO6 appears at the corresponding pins.  
GPOx – General-Purpose Logic Output  
Where: x = 1 through 6, corresponding pins GPO1 through GPO6.  
These bits are read/write.  
Default value: 0  
GPOx = 0  
GPOx = 1  
Set GPOx to 0 (default)  
Set GPOx to 1  
The general-purpose output pins, GPO1 through GPO6, are enabled by setting GPOE = 1. These pins are used  
as general-purpose outputs for controlling user-defined logic functions. When general-purpose outputs are  
disabled (GPOE = 0), they default to the zero-flag function, ZERO1 through ZERO6.  
28  
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ANALOG OUTPUTS  
The PCM1608 includes eight independent output channels, VOUT1 through VOUT8. These are unbalanced  
outputs, each capable of driving 3.1 Vp-p typical into a 5-kΩ ac load with VCC = 5 V. The internal output  
amplifiers for VOUT1 through VOUT8 are dc-biased to the common-mode (or bipolar zero) voltage, equal to VCC/2.  
The output amplifiers include an RC continuous-time filter, which helps to reduce the out-of-band noise energy  
present at the DAC outputs due to the noise-shaping characteristics of the PCM1608 delta-sigma DACs. The  
frequency response of this filter is shown in Figure 28. By itself, this filter is not enough to attenuate the  
out-of-band noise to an acceptable level for most applications. An external low-pass filter is required to provide  
sufficient out-of-band noise rejection. Further discussion of DAC post-filter circuits is provided in the Application  
Information section of this data sheet.  
20  
0
−20  
−40  
−60  
−80  
−100  
1
10  
100  
1k  
10k  
100k  
1M  
10M  
f − Frequency − Hz  
G019  
Figure 28. Output-Filter Frequency Response  
VCOM OUTPUT  
One unbuffered, common-mode voltage output pin, VCOM (pin 15), is brought out for decoupling purposes. This  
pin is nominally biased to a dc voltage level equal to VCC/2. If this pin is to be used to bias external circuitry, a  
voltage follower is required for buffering purposes. Figure 29 shows an example of using the VCOM pin for  
external biasing applications.  
PCM1608  
4
–
VCC  
2
1
VBIAS  
+
OPA337  
+
15  
3
V
COM  
+
10 µF  
S0054-03  
Figure 29. Biasing External Circuits Using the VCOM Pin  
29  
 
 
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ZERO FLAG  
Zero-Detect Condition  
Zero detection for each output channel is independent from the others. If the data for a given channel remains at  
a 0 level for 1024 sample periods (or LRCK clock periods), a zero-detect condition exists for that channel.  
Zero Output Flags  
Given that a zero-detect condition exists for one or more channels, the zero-flag pins for those channels are set  
to a logic-1 state. Each channel, ZERO1 through ZERO6 (pins 1 through 6), ZERO7 (pin 30), and ZERO8 (pin  
32), has zero-flag pins. In addition, all eight zero flags are logically ANDed together, and the result is provided at  
the ZEROA pin (pin 48), which is set to a logic-1 state when all channels indicate a zero-detect condition. The  
zero-flag pins can be used to operate external mute circuits. ZERO1 through ZERO6 can be used as status  
indicators for a microcontroller, audio signal processor, or other digitally controlled function.  
The active polarity of the zero-flag output can be inverted by setting to 1 the ZREV bit of control register 10. The  
reset default is active-high output, or ZREV = 0.  
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APPLICATION INFORMATION  
CONNECTION DIAGRAMS  
A basic connection diagram with the necessary power-supply bypassing and decoupling components is shown in  
Figure 30. Texas Instruments recommends using the component values shown in Figure 30 for all designs.  
ML  
PLL170x  
Microcontroller  
MC  
MD  
SCKO3  
ZERO7, 8  
DATA4  
+5V Power Supply  
10 µF  
Regulator  
36 35 34 33 32 31 30 29 28 27 26 25  
RST  
37 RST  
38 SCKI  
V
3
24  
CC  
AGND3 23  
SCKO  
V 4  
CC  
39  
22  
BCK  
40 BCK  
AGND4 21  
V
V
8
7
LRCK  
LPF  
LPF  
LRCK  
TEST  
V
8
41  
42  
43  
44  
45  
46  
47  
48  
20  
19  
18  
17  
16  
15  
14  
13  
OUT  
OUT  
AGND6  
PCM1608  
V
DD  
V
5
CC  
10 µF  
DGND  
DATA1  
DATA2  
DATA3  
AGND5  
DATA1  
V
OUT  
7
OUT  
10 µF  
DATA2  
DATA3  
ZEROA  
V
COM  
V
V
1
2
LPF  
LPF  
V
V
1
OUT  
OUT  
2
OUT  
OUT  
ZEROA  
1
2
3
4
5
6
7
8
9
10 11 12  
LPF  
LPF  
LPF  
LPF  
V
OUT  
V
OUT  
V
OUT  
V
OUT  
3
4
5
6
ZERO1−6  
S0090-02  
Figure 30. Basic Connection Diagram  
31  
 
PCM1608  
www.ti.com  
SBAS164B–DECEMBER 2000–REVISED JULY 2005  
APPLICATION INFORMATION (continued)  
+
+
+
+
+
+
+
+
+
V
OUT  
V
OUT  
V
OUT  
V
OUT  
3
4
5
6
AGND2  
V 2  
CC  
AGND1  
V 1  
CC  
NC  
NC  
NC  
Zero-Flag  
Zero-Flag  
ZERO7  
DATA4  
ZERO8  
MDO  
MDI  
ZERO6/GPO6  
ZERO5/GPO5  
ZERO4/GPO4  
ZERO3/GPO3  
ZERO2/GPO2  
ZERO1/GPO1  
MC  
ML  
(1) Serial control and reset functions can be provided by DSP/decoder GPIO pins.  
(2) Actual clock output used is determined by the application.  
32  
PCM1608  
www.ti.com  
SBAS164B–DECEMBER 2000–REVISED JULY 2005  
APPLICATION INFORMATION (continued)  
(3) RS = 22 Ω to 100 Ω.  
(4) See the Application Information section of this data sheet for more information.  
Figure 31. Typical Application Diagram  
A typical application diagram is shown in Figure 31. The REG1117-3.3 from Texas Instruments is used to  
generate 3.3 V for VDD from the 5-V analog power supply. The PLL170x from Texas Instruments is used to  
generate the system clock input at SCKI, as well as generating the clock for the audio signal processor.  
Series resistors (22-Ω to 100-Ω) are recommended for SCKI, LRCK, BCK, DATA1, DATA2, DATA3, and DATA4.  
The series resistor combines with the stray PCB and device input capacitance to form a low-pass filter which  
removes high-frequency noise from the digital signal, thus reducing high-frequency emission.  
POWER SUPPLIES AND GROUNDING  
The PCM1608 requires a 5-V analog supply and a 3.3-V digital supply. The 5-V supply is used to power the DAC  
analog and output filter circuitry, whereas the 3.3-V supply is used to power the digital filter and serial interface  
circuitry. For best performance, the 3.3-V supply should be derived from the 5-V supply using a linear regulator  
(see Figure 31).  
Two capacitors are required for supply bypassing (see Figure 30). These capacitors should be located as close  
as possible to the PCM1608 package. The 10-µF capacitors should be tantalum or aluminum electrolytic,  
whereas the 0.1-µF capacitors are ceramic (X7R type is recommended for surface-mount applications).  
DAC OUTPUT FILTER CIRCUITS  
Delta-sigma DACs use noise-shaping techniques to improve in-band signal-to-noise ratio (SNR) performance at  
the expense of generating increased out-of-band noise above the Nyquist frequency, or fS/2. The out-of-band  
noise must be low-pass filtered in order to provide optimal converter performance. This is accomplished by a  
combination of on-chip and external low-pass filtering.  
Figure 32 and Figure 33 show the recommended external low-pass active filter circuits for dual- and  
single-supply applications. These circuits are second-order Butterworth filters using the multiple feedback (MFB)  
circuit arrangement, which reduces sensitivity to passive component variations over frequency and temperature.  
For more information regarding MFB active filter design, see the FilterPro™ MFB and Sallen-Key Low-Pass Filter  
Design Program application report (SBFA001), available from the TI Web site (www.ti.com).  
Because the overall system performance is defined by the quality of the DACs and their associated analog  
output circuitry, high-quality audio operational amplifiers are recommended for the active filters. The OPA2134  
and OPA2353 dual operational amplifiers from Texas Instruments are shown in Figure 32 and Figure 33, and are  
recommended for use with the PCM1608.  
R
2
C
1
R
1
R
3
2
R
4
–
V
IN  
1
OPA2134  
V
OUT  
3
C
2
+
R2  
R1  
AV + *  
S0053-02  
Figure 32. Dual-Supply Filter Circuit  
33  
 
 
PCM1608  
www.ti.com  
SBAS164B–DECEMBER 2000–REVISED JULY 2005  
APPLICATION INFORMATION (continued)  
R2  
R1  
AV + *  
C
1
R
2
R
1
R
3
2
3
R
4
–
V
IN  
1
OPA2134  
V
OUT  
C
2
+
PCM1608  
+
V
COM  
To Additional  
Low-Pass  
Filter Circuits  
OPA337  
−
+
C
3
10 µF  
S0056-03  
Figure 33. Single-Supply Filter Circuit  
PCB LAYOUT GUIDELINES  
A typical PCB floor plan for the PCM1608 is shown in Figure 34. A ground plane is recommended, with the  
analog and digital sections being isolated from one another using a split or cut in the circuit board. The PCM1608  
should be oriented with the digital I/O pins facing the ground plane split/cut to allow for short, direct connections  
to the digital audio interface and control signals originating from the digital section of the board.  
Digital Power  
+V DGND  
Analog Power  
AGND +5V +V  
−V  
S
D
A
S
REG  
V
CC  
Digital Logic  
and  
Audio  
Processor  
V
DD  
Output  
Circuits  
DGND  
PCM1608  
AGND  
Digital  
Ground  
Analog  
Ground  
Digital Section  
Analog Section  
Return Path for Digital Signals  
B0031-04  
Figure 34. Recommended PCB Layout  
34  
 
PCM1608  
www.ti.com  
SBAS164B–DECEMBER 2000–REVISED JULY 2005  
PCB LAYOUT GUIDELINES (continued)  
Separate power supplies are recommended for the digital and analog sections of the board. This prevents the  
switching noise present on the digital supply from contaminating the analog power supply and degrading the  
dynamic performance of the DACs. In cases where a common 5-V supply must be used for the analog and  
digital sections, an inductance (RF choke, ferrite bead) should be placed between the analog and digital 5-V  
supply connections to avoid coupling of the digital switching noise into the analog circuitry. Figure 35 shows the  
recommended approach for single-supply applications.  
Power Supplies  
RF Choke or Ferrite Bead  
+5V AGND  
+V  
S
−V  
S
REG  
V
CC  
V
DD  
Digital Logic  
and  
Audio  
Processor  
V
DD  
Output  
Circuits  
DGND  
PCM1608  
AGND  
Common  
Ground  
Digital Section  
Analog Section  
B0032-04  
Figure 35. Single-Supply PCB Layout  
35  
 
PCM1608  
www.ti.com  
SBAS164B–DECEMBER 2000–REVISED JULY 2005  
THEORY OF OPERATION  
The DAC section of the PCM1608 is based on a multi-bit delta-sigma architecture. This architecture uses a  
fourth-order noise shaper and an 8-level amplitude quantizer, followed by an analog low-pass filter. A block  
diagram of the delta-sigma modulator is shown in Figure 36. This architecture has the advantage of stability and  
improved jitter tolerance, when compared to traditional 1-bit (2-level) delta-sigma designs.  
−
+
+
−
+
+
+
IN  
+
+
+
+
–1  
–1  
–1  
–1  
Z
Z
Z
Z
8 f  
S
+ +  
+
+
8-Level Quantizer  
OUT  
64 f  
S
B0008-03  
Figure 36. Eight-Level Delta-Sigma Modulator  
The combined oversampling rate of the digital interpolation filter and the delta-sigma modulator is 32 fS, 64 fS, or  
128 fS. The total oversampling rate is determined by the desired sampling frequency. If fS ≤ 96 kHz, then the  
OVER bit in register 12 can be set to an oversampling rate of 64 fS or 128 fS. If fS > 96 kHz, then the OVER bit  
can be used to set the oversampling rate to 32 fS or 64 fS. Figure 37 shows the out-of-band quantization-noise  
plots for both the 64× and 128× oversampling scenarios. Notice that the 128× oversampling plot shows  
significantly improved out-of-band noise performance, allowing for a simplified low-pass filter to be used at the  
output of the DAC.  
36  
 
PCM1608  
www.ti.com  
SBAS164B–DECEMBER 2000–REVISED JULY 2005  
THEORY OF OPERATION (continued)  
QUANTIZATION NOISE SPECTRUM  
QUANTIZATION NOISE SPECTRUM  
(64× OVERSAMPLING)  
vs  
(128× OVERSAMPLING)  
0
−20  
0
−20  
−40  
−40  
−60  
−60  
−80  
−80  
−100  
−120  
−140  
−160  
−180  
−100  
−120  
−140  
−160  
−180  
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
Frequency [f ]  
Frequency [f ]  
S
S
G021  
G022  
Figure 37. Quantization-Noise Spectrum  
Figure 38 illustrates the simulated jitter sensitivity of the PCM1608. To achieve best performance, the system  
clock jitter should be less than 300 picoseconds. This is easily achieved using a quality clock generation IC, like  
the PLL170x from Texas Instruments.  
JITTER DEPENDENCE  
(64× OVERSAMPLING)  
125  
120  
115  
110  
105  
100  
95  
90  
0
100  
200  
300  
400  
500  
600  
Jitter − ps  
G020  
Figure 38. Jitter Sensitivity  
37  
 
PCM1608  
www.ti.com  
SBAS164B–DECEMBER 2000–REVISED JULY 2005  
KEY PERFORMANCE PARAMETERS AND MEASUREMENT  
This section provides information on how to measure key dynamic performance parameters for the PCM1608. In  
all cases, a System Two Cascade audio measurement system by Audio Precision or equivalent is used to  
perform the testing.  
TOTAL HARMONIC DISTORTION + NOISE  
Total harmonic distortion + noise (THD+N) is a significant figure of merit for audio DACs, because it takes into  
account both harmonic distortion and all noise sources within a specified measurement bandwidth. The true rms  
value of the distortion and noise is referred to as THD+N. The test setup for THD+N measurements is shown in  
Figure 39.  
Evaluation Board  
DEM-DAI1608  
2nd-Order  
S/PDIF  
PCM1608  
Low-Pass  
Filter  
Receiver  
f
= 54 kHz  
–3 dB  
Analyzer  
and  
Display  
Digital  
Generator  
Band Limit  
Notch Filter  
S/PDIF  
Output  
(1)  
100% Full-Scale  
24-Bit, 1-kHz  
Sine Wave  
rms Mode  
HPF = 22 Hz  
LPF = 30 kHz  
Option = 20-kHz Apogee Filter  
f
C
= 1 kHz  
(2)  
(1)  
B0062-02  
(1) There is little difference in measured THD+N when using the various settings for these filters.  
(2) Required for THD+N test  
Figure 39. Test Setup for THD+N Measurements  
For the PCM1608 DACs, THD+N is measured with a full-scale, 1-kHz digital sine wave as the test stimulus at the  
input of the DAC. The digital generator is set to a 24-bit audio word length and a sampling frequency of 44.1 kHz  
or 96 kHz. The digital generator output is taken from the unbalanced S/PDIF connector of the measurement  
system. The S/PDIF data is transmitted via coaxial cable to the digital audio receiver on the DEM-DAI1602  
demonstration board. The receiver is then configured to output 24-bit data in either I2S or left-justified data  
format. The DAC audio interface format is programmed to match the receiver output format. The analog output is  
then taken from the DAC post filter and connected to the analog analyzer input of the measurement system. The  
analog input is band-limited, using filters resident in the analyzer. The resulting THD+N is measured by the  
analyzer and displayed by the measurement system.  
DYNAMIC RANGE  
Dynamic range is specified as A-weighted THD+N measured with a –60-dBFS, 1-kHz digital sine wave stimulus  
at the input of the DAC. This measurement is designed to give a good indication of how the DAC performs, given  
a low-level input signal.  
The measurement setup for the dynamic range measurement is shown in Figure 40, and is similar to the THD+N  
test setup discussed previously. The differences include the band-limit filter selection, the additional A-weighting  
filter, and the –60-dBFS input level.  
38  
 
PCM1608  
www.ti.com  
SBAS164B–DECEMBER 2000–REVISED JULY 2005  
KEY PERFORMANCE PARAMETERS AND MEASUREMENT (continued)  
Evaluation Board  
DEM-DAI1608  
2nd-Order  
Low-Pass  
Filter  
S/PDIF  
(1)  
Receiver  
PCM1608  
f
= 54 kHz  
–3 dB  
Analyzer  
and  
Display  
Digital  
Generator  
A-Weight  
Filter  
(1)  
S/PDIF  
Output  
Band Limit  
Notch Filter  
0% Full-Scale,  
Dither Off (SNR)  
–60 dB FS,  
rms Mode  
HPF = 22 Hz  
LPF = 22 kHz  
Option = A-Weighting  
f = 1 kHz  
C
(2)  
1-kHz Sine Wave  
(Dynamic Range)  
B0063-02  
(1) Infinite-zero-detect mute disabled  
(2) Results without A-weighting are approximately 3 dB worse.  
Figure 40. Test Setup for Dynamic Range and SNR Measurements  
IDLE-CHANNEL SIGNAL-TO-NOISE RATIO  
The SNR test provides a measure of the noise of the DAC. The input to the DAC is in all-0s data, and the DAC  
infinite-zero-detect mute function must be disabled (default condition at power up for the PCM1608). This  
ensures that the delta-sigma modulator output is connected to the output amplifier circuit so that idle tones (if  
present) can be observed at the output. The dither function of the digital signal generator must also be disabled  
to ensure an all-0s data stream at the input of the DAC.  
The measurement setup for SNR is identical to that used for dynamic range, with the exception of the input  
signal level (see the notes provided in Figure 40).  
39  
 
PCM1608  
www.ti.com  
SBAS164B–DECEMBER 2000–REVISED JULY 2005  
Revision History  
DATE  
REV  
PAGE  
SECTION  
DESCRIPTION  
11 JUL 05  
B
–
2
Global  
Changed to new format  
Absolute Maximum  
Ratings  
Changed values for power supply voltage, digital input voltage, lead  
temperature, and package temperature, added supply voltage difference,  
VCC – VDD < 3 V.  
2
2
Recommended  
Operating Conditions  
New table added to data sheet  
Package/Ordering In-  
formation  
Table removed from page 2, reformatted, and inserted at end of data sheet.  
In Figure 11 through Figure 18, corrected condition for 192 kHz.  
In text, corrected register number from 9 to 8.  
11, 12  
Typical Performance  
Curves  
13  
15  
System Clock Input  
Audio Serial Interface  
In text, corrected clock numbers from "one clock cycle" to "3-bit clock  
cycle".  
16, 17  
Audio Data Formats  
and Timing  
In Figure 22, Audio Data Input Formats, removed 32-fS availability from  
left-justified format, corrected relative relation between BCK and DATA. In  
Figure 23, Audio Interface Timing, corrected specification for BCK pulse  
cycle time, changed transition voltage.  
19, 20  
Serial Control Interface In Figure 26, Read Operation Timing, corrected index numbers for INC = 1  
(auto-increment read) , corrected description of notes. In text,  
auto-increment read operation, corrected wrong descriptions and numbers  
so that it describes right operation along with Figure 26. In Figure 27,  
Control Interface Timing, corrected transition voltage.  
22  
32  
Mode Control Registers In text, Reserved Registers, added description as reserved registers for  
register 00h and 0Dh to 0Fh. In table 4, Mode Control Register Map,  
removed row for register 00h.  
Application Information In Figure 31, Typical Application Diagram, corrected connections to pins  
25–29 and capacitance of C10  
.
24 MAY  
01  
A
*
Changes unknown  
15 DEC  
00  
–
–
Original version  
40  
PACKAGE OPTION ADDENDUM  
www.ti.com  
24-Jan-2013  
PACKAGING INFORMATION  
Orderable Device  
PCM1608KY  
Status Package Type Package Pins Package Qty  
Eco Plan Lead/Ball Finish  
MSL Peak Temp  
Op Temp (°C)  
Top-Side Markings  
Samples  
Drawing  
(1)  
(2)  
(3)  
(4)  
NRND  
LQFP  
LQFP  
LQFP  
LQFP  
LQFP  
LQFP  
LQFP  
LQFP  
PT  
48  
48  
48  
48  
48  
48  
48  
48  
250  
2000  
2000  
250  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
PCM1608KY  
PCM1608KY  
PCM1608KY  
PCM1608KY  
PCM1608Y  
PCM1608Y  
PCM1608Y  
PCM1608Y  
PCM1608KY/2K  
PCM1608KY/2KG4  
PCM1608KYG4  
PCM1608Y  
NRND  
NRND  
NRND  
NRND  
NRND  
NRND  
NRND  
PT  
PT  
PT  
PT  
PT  
PT  
PT  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
250  
Green (RoHS  
& no Sb/Br)  
PCM1608Y/2K  
PCM1608Y/2KG4  
PCM1608YG4  
2000  
2000  
250  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
24-Jan-2013  
(4) Only one of markings shown within the brackets will appear on the physical device.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
26-Jan-2013  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
PCM1608KY/2K  
PCM1608Y/2K  
LQFP  
LQFP  
PT  
PT  
48  
48  
2000  
2000  
330.0  
330.0  
16.4  
16.4  
9.6  
9.6  
9.6  
9.6  
1.9  
1.9  
12.0  
12.0  
16.0  
16.0  
Q1  
Q1  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
26-Jan-2013  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
PCM1608KY/2K  
PCM1608Y/2K  
LQFP  
LQFP  
PT  
PT  
48  
48  
2000  
2000  
367.0  
367.0  
367.0  
367.0  
38.0  
38.0  
Pack Materials-Page 2  
MECHANICAL DATA  
MTQF003A – OCTOBER 1994 – REVISED DECEMBER 1996  
PT (S-PQFP-G48)  
PLASTIC QUAD FLATPACK  
0,27  
0,17  
M
0,08  
0,50  
36  
25  
37  
24  
48  
13  
0,13 NOM  
1
12  
5,50 TYP  
7,20  
SQ  
6,80  
Gage Plane  
9,20  
SQ  
8,80  
0,25  
0,05 MIN  
0°–7°  
1,45  
1,35  
0,75  
0,45  
Seating Plane  
0,10  
1,60 MAX  
4040052/C 11/96  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Falls within JEDEC MS-026  
D. This may also be a thermally enhanced plastic package with leads conected to the die pads.  
1
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