PCM1725 [TI]
DIGITAL-TO-ANALOG CONVERTER;
| 型号： | PCM1725 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DIGITAL-TO-ANALOG CONVERTER |
| 文件： | 总14页 (文件大小：638K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Not Recommended For New Designs
®
PCM1725
PCM1725
TM
Stereo Audio
DIGITAL-TO-ANALOG CONVERTER
16 Bits, 96kHz Sampling
FEATURES
● COMPLETE STEREO DAC: Includes Digital
DESCRIPTION
The PCM1725 is a complete low cost stereo audio
digital-to-analog converter (DAC), operating off of a
256fS or 384fS system clock. The DAC contains a 3rd-
order ∆Σ modulator, a digital interpolation filter, and
an analog output amplifier. The PCM1725 accepts
16-bit input data in either normal or I2S formats.
Filter and Output Amp
● DYNAMIC RANGE: 95dB
● MULTIPLE SAMPLING FREQUENCIES:
16kHz to 96kHz
● 8X OVERSAMPLING DIGITAL FILTER
● SYSTEM CLOCK: 256fS /384fS
● NORMAL OR I2S DATA INPUT FORMATS
The digital filter performs an 8X interpolation function
and includes de-emphasis at 44.1kHz. The PCM1725
can accept digital audio sampling frequencies from
16kHz to 96kHz, always at 8X oversampling.
● SMALL 14-PIN SOIC PACKAGE
The PCM1725 is ideal for low-cost, CD-quality con-
sumer audio applications.
Multi-level
Delta-Sigma
Modulator
VOUT
L
BCKIN
Serial
Low-pass
Filter
DAC
DAC
LRCIN
Input
I/F
DIN
8X Oversampling
Digital Filter
CAP
VOUT
Multi-level
Delta-Sigma
Modulator
R
Low-pass
Filter
Mode
Control
I/F
FORMAT
DM
Power Supply
256fS/384fS
SCKI
VCC
GND
International Airport Industrial Park
•
Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/
•
FAXLine: (800) 548-6133 (US/Canada Only)
•
Cable: BBRCORP
•
Telex: 066-6491
•
FAX: (520) 889-1510
•
Immediate Product Info: (800) 548-6132
© 1997 Burr-Brown Corporation
PDS-1373C
Printed in U.S.A. January, 1998
SBAS067
Not Recommended For New Designs
SPECIFICATIONS
All specifications at +25°C, +VCC = +5V, fS = 44.1kHz, and 16-bit input data, SYSCLK = 384fS, unless otherwise noted.
PCM1725
TYP
PARAMETER
CONDITIONS
MIN
16
MAX
UNITS
RESOLUTION
16
Bits
DATA FORMAT
Audio Data Interface Format
Audio Data Format
Sampling Frequency (fS)
Internal System Clock Frequency
Standard/I2S
Binary Two’s Complement
96
kHz
256fS/384fS
DIGITAL INPUT/OUTPUT
Logic Level
TTL
Input Logic Level
(1)
VIH
2.0
VDC
VDC
µA
(1)
VIL
0.8
(1)
Input Logic Current: IIN
±0.8
DYNAMIC PERFORMANCE(2)
f = 991kHz
THD+N at FS (0dB)
THD+N at –60dB
Dynamic Range
–83
–32
95
–78
dB
dB
dB
dB
dB
A-weighted
A-weighted
90
90
88
Signal-to-Noise Ratio
Channel Separation
97
95
DC ACCURACY
Gain Error
±1.0
±1.0
±20
±5.0
±5.0
±50
% of FSR
% of FSR
mV
Gain Mismatch, Channel-to-Channel
Bipolar Zero Error
VOUT = VCC/2 at BPZ
ANALOG OUTPUT
Output Voltage
Full Scale (0dB)
AC Load
0.62 x VCC
VCC/2
Vp-p
VDC
kΩ
Center Voltage
Load Impedance
10
DIGITAL FILTER PERFORMANCE
Passband
0.445
fS
fS
Stopband
0.555
–35
Passband Ripple
Stopband Attenuation
Delay Time
±0.17
dB
dB
sec
11.125/fS
INTERNAL ANALOG FILTER
–3dB Bandwidth
100
kHz
dB
Passband Response
f = 20kHz
–0.16
POWER SUPPLY REQUIREMENTS
Voltage Range
4.5
5
5.5
18
90
VDC
mA
mW
Supply Current
Power Dissipation
13
65
TEMPERATURE RANGE
Operation
–25
–55
+85
°C
°C
Storage
+125
NOTES: (1) Pins 1, 2, 3, 12, 13: LRCIN, DIN, BCKIN, DM, FORMAT (Schmitt Trigger Input); Pin 14: SCKI. (2) Dynamic performance specs are tested with 20kHz
low pass filter and THD+N specs are tested with 30kHz LPF, 400Hz HPF, Average-Mode.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
2
PCM1725
Not Recommended For New Designs
PIN CONFIGURATION
PIN ASSIGNMENTS
TOP VIEW
SOIC
PIN
NAME
I/O
FUNCTION
1(1)
LRCIN
IN
Sample Rate Clock Input
2(1)
3(1)
4
DIN
BCKIN
NC
IN
IN
—
—
Audio Data Input
Bit Clock Input for Audio Data.
No Connection
LRCIN
DIN
1
2
3
4
5
6
7
14 SCKI
13 FORMAT
12 DM
5
CAP
Common Pin of Analog Output Amp
6
VOUT
R
OUT Right-Channel Analog Output
BCKIN
NC
7
GND
VCC
—
—
Ground
11 NC
PCM1725
8
Power Supply
CAP
10 NC
9
VOUT
NC
L
OUT Left-Channel Analog Output
VOUT
R
9
8
VOUT
VCC
L
10
11
12(2)
—
—
IN
No Connection
No Connection
NC
GND
DM
De-emphasis Control
HIGH: De-emphasis ON
LOW: De-emphasis OFF
13(2) FORMAT
—
Audio Data Format Select
HIGH: I2S Data Format
LOW: Standard Data Format
PACKAGE INFORMATION
14
SCKI
IN
System Clock Input (256fS or 384fS)
NOTES: (1) Schmitt Trigger input. (2) Schmitt Trigger input with internal
pull-up.
PACKAGE DRAWING
NUMBER(1)
PRODUCT
PACKAGE
PCM1725U
14 Pin SOIC
235
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ABSOLUTE MAXIMUM RATINGS
Power Supply Voltage....................................................................... +6.5V
+VCC to +VDD Difference ................................................................... ±0.1V
Input Logic Voltage .................................................. –0.3V to (VDD + 0.3V)
Power Dissipation .......................................................................... 290mW
Operating Temperature Range ......................................... –25°C to +85°C
Storage Temperature ...................................................... –55°C to +125°C
Lead Temperature (soldering, 5s) .................................................. +260°C
Thermal Resistance, θJA .............................................................. +90°C/W
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
®
3
PCM1725
Not Recommended For New Designs
TYPICAL PERFORMANCE CURVES
At TA = +25°C, +VCC = +5V, fS = 44.1kHz, SYSCLK = 256fS, unless otherwise noted.
DYNAMIC PERFORMANCE
SNR, DYNAMIC RANGE vs TEMPERATURE
SNR
THD+N vs TEMPERATURE
99
98
97
96
95
94
93
99
98
97
96
95
94
93
3.2
3.1
3.0
2.9
2.8
2.7
2.6
2.5
2.4
2.3
0.009
0.008
0.007
0.006
0.005
0.004
0.003
0.002
0.001
0
0dB
–60dB
Dynamic Range
–25
0
25
50
75 85
100
–25
0
25
50
75 85
100
Temperature (°C)
Temperature (°C)
THD+N vs POWER SUPPLY
SNR, DYNAMIC RANGE vs POWER SUPPLY
0.009
0.008
0.007
0.006
0.005
0.004
0.003
0.002
0.001
0
3.2
3.1
3.0
2.9
2.8
2.7
2.6
2.5
2.4
2.3
99
99
98
97
96
95
94
93
98
97
96
95
94
93
SNR
0dB
Dynamic Range
–60dB
4.75
4.5
5.0
5.25
5.5
4.5
4.75
5.0
5.25
5.5
VCC (V)
VCC (V)
SNR, DYNAMIC RANGE vs SAMPLING RATE
SNR
THD+N vs SAMPLING RATE
98
97
96
95
94
93
92
91
90
89
88
98
97
96
95
94
93
92
91
90
89
88
0.016
0.014
0.012
0.01
5.2
4.7
4.2
3.7
3.2
2.7
2.2
0dB
Dynamic Range
0.008
0.006
0.004
–60dB
96
44.1
48
88.2
96
44.1
48
88.2
Sampling Rate (kHz)
Sampling Rate (kHz)
®
4
PCM1725
Not Recommended For New Designs
TYPICAL PERFORMANCE CURVES
At TA = +25°C, +VCC = +VDD = +5V, fS = 44.1kHz, and 16-bit input data, SYSCLK = 384fS, unless otherwise noted.
DIGITAL FILTER
OVERALL FREQUENCY CHARACTERISTIC
PASSBAND RIPPLE CHARACTERISTIC
0
–20
0
–0.2
–0.4
–0.6
–0.8
–1
–40
–60
–80
–100
0
0.4536fS
1.3605fS
2.2675fS
3.1745fS
4.0815fS
0
0.1134fS
0.2268fS
0.3402fS
0.4535fS
Frequency (Hz)
Frequency (Hz)
DE-EMPHASIS FREQUENCY RESPONSE (44.1kHz)
DE-EMPHASIS FREQUENCY ERROR (44.1kHz)
0
–2
0.6
0.4
–4
0.2
–6
0.0
–8
–0.2
–0.4
–0.6
–10
–12
0
5
10
15
20
25
0
4999.8375
9999.675
14999.5125
19999.35
Frequency (kHz)
Frequency (kHz)
®
5
PCM1725
Not Recommended For New Designs
1/fs
L_ch
R_ch
LRCIN (pin 1)
BCKIN (pin 3)
AUDIO DATA WORD = 16-BIT
DIN (pin 2)
14 15 16
LSB
14 15 16
LSB
14 15 16
1
2
3
1
2
3
MSB
MSB
FIGURE 1. “Normal” Data Input Timing.
1/fs
L_ch
R_ch
LRCIN (pin 1)
BCKIN (pin 3)
AUDIO DATA WORD = 16-BIT
DIN (pin 2)
1
2
3
14 15 16
LSB
1
2
3
14 15 16
LSB
1
2
MSB
MSB
FIGURE 2. “I2S” Data Input Timing.
LRCKIN
1.4V
1.4V
tBCH
tBCL
tLB
BCKIN
tBL
tBCY
1.4V
DIN
tDS
tDH
BCKIN Pulse Cycle Time
BCKIN Pulse Width High
BCKIN Pulse Width Low
: tBCY
: tBCH
: tBCL
: 100ns (min)
: 50ns (min)
: 50ns (min)
: 30ns (min)
: 30ns (min)
: 30ns (min)
: 30ns (min)
BCKIN Rising Edge to LRCIN Edge : tBL
LRCIN Edge to BCKIN Rising Edge : tLB
DIN Set-up Time
DIN Hold Time
: tDS
: tDH
FIGURE 3. Audio Data Input Timing.
SYSTEM CLOCK
tSCKIH
The system clock for PCM1725 must be either 256fS or
384fS, where fS is the audio sampling frequency (LRCIN),
typically 32kHz, 44.1kHz or 48kHz. The system clock is
used to operate the digital filter and the noise shaper. The
system clock input (SCKI) is at pin 14. Timing conditions
for SCKI are shown in Figure 4.
2.0V
0.8V
SCKI
tSCKIL
System Clock Pulse Width High
System Clock Pulse Width Low
tSCKIH
tSCKIL
13ns (min)
13ns (min)
FIGURE 4. System Clock Timing Requirements.
®
6
PCM1725
Not Recommended For New Designs
PCM1725 has a system clock detection circuit which auto-
FORMAT
matically detects the frequency, either 256fS or 384fS. The
system clock should be synchronized with LRCIN (pin 1),
but PCM1725 can compensate for phase differences. If the
phase difference between LRCIN and system clock is greater
than ±6 bit clocks (BCKIN), the synchronization is per-
formed automatically. The analog outputs are forced to a
bipolar zero state (VCC/2) during the synchronization func-
tion. Table I shows the typical system clock frequency
inputs for the PCM1725.
0
1
Normal Format (MSB-first, right-justified)
I2S Format (Philips serial data protocol)
TABLE II. Input Format Selection.
RESET
PCM1725 has an internal power-on reset circuit. The internal
power-on reset initializes (resets) when the supply voltage
VCC > 2.2V (typ). The power-on reset has an initialization
period equal to 1024 system clock periods after VCC > 2.2V.
During the initialization period, the outputs of the DAC are
invalid, and the analog outputs are forced to VCC/2. Figure 6
illustrates the power-on reset and reset-pin reset timing.
SYSTEM CLOCK
FREQUENCY (MHz)
SAMPLING
RATE (LRCIN)
256fS
384fS
32kHz
44.1kHz
48kHz
8.192
11.2896
12.288
12.288
16.9340
18.432
DE-EMPHASIS CONTROL
Pin 12 (DM) enables PCM1725’s de-emphasis function. De-
emphasis operates only at 44.1kHz.
TABLE I. System Clock Frequencies vs Sampling Rate.
TYPICAL CONNECTION DIAGRAM
DM
Figure 5 illustrates the typical connection diagram for
PCM1725 used in a stand-alone application.
0
1
DEM OFF
DEM ON (44.1kHz)
TABLE III. De-Emphasis Control Selection.
INPUT DATA FORMAT
PCM1725 can accept input data in either normal (MSB-first,
right-justified) or I2S formats. When pin 13 (FORMAT) is
LOW, normal data format is selected; a HIGH on pin 13
selects I2S format.
+5V Analog
7
8
GND
VCC
2
3
1
9
Post
LPF
DIN
VOUTL
Lch Analog Out
Rch Analog Out
5
PCM
Audio Data
Processor
BCKIN
LRCIN
CAP
+
10µF
6
Post
LPF
PCM1725
V
OUTR
13
12
14
SCKI
FORMAT
DM
Mode Control
256fS/384fS CLK
FIGURE 5. Typical Connection Diagram.
2.6V
2.2V
1.8V
VCC
Reset
Reset Removal
Internal Reset
1024 system (= SCKI) clocks
SCKI Clock
FIGURE 6. Internal Power-On Reset Timing.
®
7
PCM1725
Not Recommended For New Designs
APPLICATION
CONSIDERATIONS
INTERNAL ANALOG FILTER FREQUENCY RESPONSE
(20Hz~24kHz, Expanded Scale)
DELAY TIME
1.0
0.5
There is a finite delay time in delta-sigma converters. In A/D
converters, this is commonly referred to as latency. For a
delta-sigma D/A converter, delay time is determined by the
order number of the FIR filter stage, and the chosen sampling
rate. The following equation expresses the delay time of
PCM1725:
0
TD = 11.125 x 1/fS
–0.5
–1.0
For fS = 44.1kHz, TD = 11.125/44.1kHz = 251.4µs
Applications using data from a disc or tape source, such as
CD audio, CD-Interactive, Video CD, DAT, Minidisc,
etc., generally are not affected by delay time. For some
professional applications such as broadcast audio for stu-
dios, it is important for total delay time to be less than 2ms.
20
100
1k
10k
24k
Frequency (Hz)
FIGURE 7. Low Pass Filter Frequency Response.
OUTPUT FILTERING
For testing purposes all dynamic tests are done on the
PCM1725 using a 20kHz low pass filter. This filter limits
the measured bandwidth for THD+N, etc. to 20kHz. Failure
to use such a filter will result in higher THD+N and lower
SNR and Dynamic Range readings than are found in the
specifications. The low pass filter removes out of band
noise. Although it is not audible, it may affect dynamic
specification numbers.
INTERNAL ANALOG FILTER FREQUENCY RESPONSE
(10Hz~10MHz)
10
5
0
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
The performance of the internal low pass filter from DC to
24kHz is shown in Figure 7. The higher frequency rolloff of
the filter is shown in Figure 8. If the user’s application has
the PCM1725 driving a wideband amplifier, it is recom-
mended to use an external low pass filter. A simple 3rd-
order filter is shown in Figure 9. For some applications, a
passive RC filter or 2nd-order filter may be adequate.
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
BYPASSING POWER SUPPLIES
The power supplies should be bypassed as close as possible
to the unit. It is also recommended to include a 0.1µF ceramic
capacitor in parallel with the 10µF tantalum bypass capacitor.
FIGURE 8. Low Pass Filter Wideband Frequency Response.
GAIN vs FREQUENCY
90
6
Gain
–14
–34
–54
–74
–94
0
1500pF
OPA134
–90
+
10kΩ
10kΩ
10kΩ
–180
Phase
VSIN
680pF
100pF
–
–270
–360
100
1k
10k
100k
1M
Frequency (Hz)
FIGURE 9. 3rd-Order LPF.
®
8
PCM1725
Not Recommended For New Designs
+
–
+
+
+
+
+
Z–1
Z–1
Z–1
In
8fS
18-Bit
–
+
+
+
5-level Quantizer
4
3
2
1
0
Out
48fS (384fS)
64fS (256fS)
FIGURE 10. 5-Level ∆Σ Modulator Block Diagram.
THEORY OF OPERATION
5-LEVEL ∆Σ MODULATOR
The delta-sigma section of PCM1725 is based on a 5-level
amplitude quantizer and a 3rd-order noise shaper. This
section converts the oversampled input data to 5-level delta-
sigma format. A block diagram of the 5-level delta-sigma
modulator is shown in Figure 10. This 5-level delta-sigma
modulator has the advantage of stability and clock jitter over
the typical one-bit (2-level) delta-sigma modulator.
20
0
–20
–40
–60
–80
–100
–120
–140
–160
The combined oversampling rate of the delta-sigma modu-
lator and the internal 8X interpolation filter is 96fS for a
384fS system clock, and 64fS for a 256fS system clock. The
theoretical quantization noise performance of the 5-level
delta-sigma modulator is shown in Figure 11.
0
5
10
15
20
25
Frequency (kHz)
FIGURE 11. Quantization Noise Spectrum.
®
9
PCM1725
PACKAGE OPTION ADDENDUM
www.ti.com
27-Aug-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
PCM1725D
PCM1725DG4
PCM1725DR
NRND
NRND
NRND
NRND
NRND
NRND
NRND
NRND
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
D
D
D
D
D
D
D
D
14
14
14
14
14
14
14
14
50
50
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
2000
2000
50
Green (RoHS
& no Sb/Br)
PCM1725DRG4
PCM1725U
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
PCM1725U/2K
PCM1725U/2KG4
PCM1725UG4
2000
2000
50
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
27-Aug-2011
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
PCM1725DR
SOIC
SOIC
D
D
14
14
2000
2000
330.0
330.0
16.4
16.4
6.5
6.5
9.0
9.0
2.1
2.1
8.0
8.0
16.0
16.0
Q1
Q1
PCM1725U/2K
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
PCM1725DR
SOIC
SOIC
D
D
14
14
2000
2000
367.0
367.0
367.0
367.0
38.0
38.0
PCM1725U/2K
Pack Materials-Page 2
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