PCM1804DB [TI]
具有差分输入的 112dB SNR 立体声 ADC | DB | 28 | -10 to 70;
| 型号： | PCM1804DB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有差分输入的 112dB SNR 立体声 ADC | DB | 28 | -10 to 70 |
| 文件： | 总39页 (文件大小：692K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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PCM1804
SLES022C–DECEMBER 2001–REVISED OCTOBER 2007
FULL DIFFERENTIAL ANALOG INPUT 24-BIT, 192-kHz
STEREO A/D CONVERTER
1
FEATURES
APPLICATIONS
•
•
•
•
•
AV Amplifier
MD Player
Digital VTR
Digital Mixer
Digital Recorder
23
•
24-Bit Delta-Sigma Stereo A/D Converter
•
High Performance:
–
–
–
Dynamic Range: 112 dB (Typical)
SNR: 111 dB (Typical)
THD+N: –102 dB (Typical)
•
High-Performance Linear Phase Antialias
Digital Filter:
DESCRIPTION
The PCM1804 is a high-performance, single-chip
stereo A/D converter with fully differential analog
–
–
Pass-Band Ripple: ±0.005 dB
Stop-Band Attenuation: –100 dB
voltage input. The PCM1804 uses
a precision
delta-sigma modulator and includes a linear phase
antialias digital filter and high-pass filter (HPF) that
removes dc offset from the input signal. The
PCM1804 is suitable for a wide variety of mid- to
high-grade consumer and professional applications,
where excellent performance and 5-V analog supply
and 3.3-V digital power-supply operation are required.
The PCM1804 can achieve both PCM audio and
DSD format due to the precision delta-sigma
modulator. The PCM1804 is fabricated using an
advanced CMOS process and is available in a small
28-pin SSOP package.
•
•
Fully Differential Analog Input: ±2.5 V
Audio Interface: Master- or Slave-Mode
Selectable
Data Formats: Left-Justified, I2S, Standard
24-Bit, and DSD
•
•
Function:
–
–
Peak Detection
High-Pass Filter (HPF): –3 dB at 1 Hz,
fS = 48 kHz
•
•
Sampling Rate up to 192 kHz
System Clock: 128 fS, 256 fS, 384 fS,
512 fS, or 768 fS
•
Dual Power Supplies:
–
–
5 V for Analog
3.3 V for Digital
•
•
•
Power Dissipation: 225 mW
Small 28-Pin SSOP
DSD Output: 1 Bit, 64 fS
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
System Two, Audio Precision are trademarks of Audio Precision, Inc.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2001–2007, Texas Instruments Incorporated
PCM1804
www.ti.com
SLES022C–DECEMBER 2001–REVISED OCTOBER 2007
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields.
These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to
MIL-STD-883C, Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than
maximum-rated voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together
or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriate logic
voltage level, preferably either VCC or ground. Specific guidelines for handling devices of this type are contained in the publication
Electrostatic Discharge (ESD) (SSYA008), available from Texas Instruments.
PIN ASSIGNMENTS
PCM1804 PACKAGE
(TOP VIEW)
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
L
V
R
REF
REF
2
AGNDL
AGNDR
3
V
COM
L
L+
L−
V
V
V
R
R+
R−
COM
4
V
V
IN
IN
IN
5
IN
6
FMT0
FMT1
S/M
OSR0
OSR1
OSR2
BYPAS
DGND
AGND
7
V
CC
8
OVFL
OVFR
RST
SCKI
LRCK/DSDBCK
BCK/DSDL
DATA/DSDR
9
10
11
12
13
14
V
DD
P0007-02
2
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Copyright © 2001–2007, Texas Instruments Incorporated
Product Folder Link(s): PCM1804
PCM1804
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SLES022C–DECEMBER 2001–REVISED OCTOBER 2007
FUNCTIONAL BLOCK DIAGRAM
OSR0
OSR1
OSR2
CLK
Control
SCKI
V
L+
IN
Delta-Sigma
Modulator (L)
Decimation
Filter (L)
HPF
S/M
V
L−
IN
FMT0
FMT1
V
COM
L
AGNDL
V L
REF
V
L
REF
LRCK/DSDBCK
BCK/DSDL
Serial
Output
Interface
V
REF
R
V R
REF
DATA/DSDR
AGNDR
V R
COM
V
R+
Decimation
Filter (R)
IN
Delta-Sigma
Modulator (R)
OVFL
OVFR
HPF
V
R−
IN
BYPAS
RST
Power Supply
V
CC
AGND
DGND
V
DD
B0029-01
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SLES022C–DECEMBER 2001–REVISED OCTOBER 2007
Terminal Functions
TERMINAL
I/O
DESCRIPTIONS
NAME
PIN
23
2
AGND
–
–
–
Analog ground
AGNDL
Analog ground for VREF
Analog ground for VREF
L
AGNDR
BCK/DSDL
BYPAS
27
16
12
15
R
(1)
I/O Bit clock input/output in PCM mode. L-channel audio data output in DSD mode.
(1)
I
HPF bypass control. High: HPF disabled, Low: HPF enabled
DATA/DSDR
O
L-channel and R-channel audio data output in PCM mode. R-channel audio data output in DSD mode. (DSD
output, when in DSD mode)
DGND
FMT0
FMT1
LRCK/DSDBCK
OSR0
OSR1
OSR2
OVFL
OVFR
RST
13
6
–
I
Digital ground
(2)
Audio data format 0. See Table 5.
(2)
7
I
Audio data format 1. See Table 5.
(1)
17
9
I/O Sampling clock input/output in PCM and DSD modes.
(2)
I
I
Oversampling ratio 0. See Table 1 and Table 2.
Oversampling ratio 1. See Table 1 and Table 2.
Oversampling ratio 2. See Table 1 and Table 2.
(2)
(2)
10
11
21
20
19
18
8
I
O
O
I
Overflow signal of L-channel in PCM mode. This is available in PCM mode only.
Overflow signal of R-channel in PCM mode. This is available in PCM mode only.
(2)
Reset, power-down input, active-low
(3)
SCKI
I
System clock input; 128 fS, 256 fS, 384 fS, 512 fS, or 768 fS.
(2)
S/M
I
Slave/master mode selection. See Table 4.
VCC
22
3
–
–
–
–
I
Analog power supply
VCOM
VCOM
VDD
L
L-channel analog common-mode voltage (2.5 V)
R-channel analog common-mode voltage (2.5 V)
Digital power supply
R
26
14
5
VINL–
VINL+
VINR–
VINR+
L-channel analog input, negative pin
4
I
L-channel analog input, positive pin
24
25
1
I
R-channel analog input, negative pin
I
R-channel analog input, positive pin
VREF
VREF
L
–
–
L-channel voltage reference output, requires capacitors for decoupling to AGND
R-channel voltage reference output, requires capacitors for decoupling to AGND
R
28
(1) Schmitt-trigger input
(2) Schmitt-trigger input with internal pulldown (51 kμ typically), 5-V tolerant.
(3) Schmitt-trigger input, 5-V tolerant.
4
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SLES022C–DECEMBER 2001–REVISED OCTOBER 2007
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
VCC
–0.3 V to 6.5 V
–0.3 V to 4 V
±0.1 V
Supply voltage
VDD
Ground voltage differences
Supply voltage difference
AGND, AGNDL, AGNDR, DGND
VCC, VDD
VCC – VDD < 3 V
FMT0, FMT1, S/M, OSR0, OSR1, OSR2, SCKI, RST
–0.3 V to 6.5 V
–0.3 V to (VDD + 0.3 V)
–0.3 V to (VCC + 0.3 V)
±10 mA
Digital input voltage
BYPAS, DATA/DSDR, BCK/DSDL, LRCK/DSDBCK, OVFL, OVFR
VREFL, VREFR, VCOML, VCOMR, VINL+, VINR+, VINL–, VINR–
Analog input voltage
Input current (any pins except supplies)
Ambient temperature under bias
Storage temperature
TA
–40°C to 125°C
–55°C to 150°C
150°C
Tstg
TJ
Junction temperature
Lead temperature (soldering)
Package temperature (IR reflow, peak)
260°C, 5 s
260°C
(1) Stresses beyond those listed under "absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range
MIN
4.75
3
NOM
MAX
5.25
3.6
UNIT
V
Analog supply voltage, VCC
5
Digital supply voltage, VDD
3.3
5
V
Analog input voltage, full-scale (–0 dB), differential input
Digital input logic family
Vp-p
TTL compatible
System clock
Digital input clock frequency
8.192
32
36.864
192
10
MHz
kHz
pF
Sampling clock
Digital output load capacitance
Operating free-air temperature, TA
–10
70
°C
Copyright © 2001–2007, Texas Instruments Incorporated
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SLES022C–DECEMBER 2001–REVISED OCTOBER 2007
ELECTRICAL CHARACTERISTICS
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, single-speed mode, fS = 48 kHz, system clock = 256 fS,
24-bit data, unless otherwise noted.
PCM1804DB
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
Resolution
24
Bits
DATA FORMAT
Audio data interface format
Audio data bit length
Standard, I2S, left-justified
24
Bits
MSB first,
2s complement, DSD
Audio data format
DIGITAL INPUT/OUTPUT
Logic family
TTL compatible
2
(1) (2)
(3)
5.5
VIH
VIL
High-level input voltage
Low-level input voltage
Vdc
Vdc
2
VDD
0.8
(1) (2) (3)
(1)
(2)
VIN = VDD
VIN = VDD
VIN = VDD
VIN = 0 V
VIN = 0 V
65
100
±10
±100
±10
±50
IIH
High-level input current
μA
(3)
(1) (2)
(3)
IIL
Low-level input current
μA
(4)
VOH
VOL
High-level output voltage
Low-level output voltage
IOH = –1 mA
2.4
32
Vdc
Vdc
(4)
IOL = 1 mA
0.4
CLOCK FREQUENCY
fS Sampling frequency
192
kHz
(5)
256 fS, single rate
384 fS, single rate
512 fS, single rate
768 fS, single rate
12.288
18.432
24.576
36.864
24.576
36.864
24.576
36.864
(5)
(5)
(5)
System clock frequency
MHz
(6)
256 fS, dual rate
384 fS, dual rate
128 fS, quad rate
192 fS, quad rate
(6)
(7)
(7)
DC ACCURACY
Gain mismatch, channel-
±3 % of FSR
to-channel
Gain error (VIN = –0.5 dB)
Bipolar zero error
±4 % of FSR
% of FSR
HPF bypass
±0.2
(1) Pins 6–11, 19: FMT0, FMT1, S/M, OSR0, OSR1, OSR2, RST [Schmitt-trigger input with internal pulldown (51 kμ typically), 5-V tolerant]
(2) Pin 18: SCKI (Schmitt-trigger input, 5-V tolerant)
(3) Pins 12, 16–17: BYPAS, BCK/DSDL, LRCK/DSDBCK (in slave mode, Schmitt-trigger input)
(4) Pins 15–17, 20, and 21: DATA/DSDR, BCK/DSDL, LRCK/DSDBCK (in master mode), OVFR, OVFL
(5) Single rate, fS = 48 kHz
(6) Dual rate, fS = 96 kHz
(7) Quad rate, fS = 192 kHz
6
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SLES022C–DECEMBER 2001–REVISED OCTOBER 2007
ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, single-speed mode, fS = 48 kHz, system clock = 256 fS,
24-bit data, unless otherwise noted.
PCM1804DB
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
(8)
DYNAMIC PERFORMANCE
VIN = –0.5 dB
VIN = –60 dB
VIN = –0.5 dB
VIN = –60 dB
VIN = –0.5 dB
VIN = –60 dB
–102
–49
–101
–47
–101
–47
–100
112
112
112
112
111
111
111
111
109
107
107
–95
fS = 48 kHz, system clock = 256 fS
fS = 96 kHz, system clock = 256 fS
fS = 192 kHz, system clock = 128 fS
Total harmonic distortion
plus noise
THD+N
dB
VIN = –0.5 dB DSD mode
fS = 48 kHz, system clock = 256 fS
106
105
97
VIN = –60 dB fS = 96 kHz, system clock = 256 fS
fS = 192 kHz, system clock = 128 fS
DSD mode
Dynamic range
(A-weighted)
dB
fS = 48 kHz, system clock = 256 fS
fS = 96 kHz, system clock = 256 fS
fS = 192 kHz, system clock = 128 fS
DSD mode
SNR (A-weighted)
Channel separation
dB
dB
fS = 48 kHz, system clock = 256 fS
fS = 96 kHz, system clock = 256 fS
fS = 192 kHz, system clock = 128 fS
ANALOG INPUT
Input voltage
Differential input
Single-ended
±2.5
2.5
10
V
Center voltage
Input impedance
Vdc
kμ
DIGITAL FILTER PERFORMANCE
Pass-band edge
Single rate, dual rate
Single rate, dual rate
Single rate, dual rate
Single rate, dual rate
0.453 fS
±0.005
Hz
Hz
dB
dB
Stop-band edge
0.547 fS
–100
Pass-band ripple
Stop-band attenuation
Pass-band edge (–0.005
dB)
Quad rate
0.375 fS
0.49 fS
Hz
Pass-band edge (–3 dB)
Stop-band edge
Quad rate
Quad rate
Quad rate
Quad rate
Single rate, dual rate
Quad rate
–3 dB
Hz
Hz
dB
dB
s
0.77 fS
–135
Pass-band ripple
Stop-band attenuation
Group delay
±0.005
37/fS
9.5/fS
Group delay
s
HPF frequency response
fS/48000
Hz
(8) fIN = 1 kHz, using System Two™ audio measurement system by Audio Precision™ in RMS mode, with 20-kHz LPF and 400-Hz HPF in
calculation for single rate, or with 40-kHz LPF in calculation for dual and quad rates.
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SLES022C–DECEMBER 2001–REVISED OCTOBER 2007
ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, single-speed mode, fS = 48 kHz, system clock = 256 fS,
24-bit data, unless otherwise noted.
PCM1804DB
PARAMETER
TEST CONDITIONS
UNIT
Vdc
mA
MIN
TYP
MAX
POWER SUPPLY REQUIREMENTS
VCC
4.75
3
5
3.3
35
5.25
3.6
45
Supply voltage range
VDD
(9) (10) (11)
ICC
VCC = 5 V
(9) (12)
VDD = 3.3 V
VDD = 3.3 V
VDD = 3.3 V
15
20
Supply current
IDD
(10) (12)
(11) (12)
27
18
(9) (12)
Operation, VCC = 5 V, VDD = 3.3 V
Operation, VCC = 5 V, VDD = 3.3 V
Operation, VCC = 5 V, VDD = 3.3 V
225
265
235
5
290
(10) (12)
(11) (12)
PD
Power dissipation
mW
Power down, VCC = 5 V, VDD = 3.3 V
TEMPERATURE RANGE
Operation temperature
Thermal resistance
–10
70
°C
θJA
100
°C/W
(9) Single rate, fS = 48 kHz
(10) Dual rate, fS = 96 kHz
(11) Quad rate, fS = 192 kHz
(12) Minimum load on DATA/DSDR (pin 15)
8
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SLES022C–DECEMBER 2001–REVISED OCTOBER 2007
TYPICAL PERFORMANCE CURVES - SINGLE RATE
All specifications at TA = 25°C, VCC = 3.3 V, VDD = 5 V, master mode, fS = 48 kHz, system clock = 256 fS, 24-bit data, unless
otherwise noted.
TOTAL HARMONIC DISTORTION + NOISE
DYNAMIC RANGE AND SNR
vs
vs
TEMPERATURE
TEMPERATURE
120
115
110
105
100
−35
−40
−45
−50
−55
−90
−95
Dynamic Range
SNR
−100
−105
−110
−0.5 dB
−60 dB
−20
0
20
40
60
80
−20
0
20
40
60
80
T − Temperature − °C
G001
T − Temperature − °C
G002
Figure 1.
Figure 2.
TOTAL HARMONIC DISTORTION + NOISE
DYNAMIC RANGE AND SNR
vs
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
120
115
110
105
100
−35
−40
−45
−50
−55
−90
−95
Dynamic Range
SNR
−100
−105
−110
−0.5 dB
−60 dB
4.50
4.75
5.00
5.25
5.50
4.50
4.75
5.00
5.25
5.50
V
CC
− Supply Voltage − V
G003
V
CC
− Supply Voltage − V
G004
Figure 3.
Figure 4.
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SLES022C–DECEMBER 2001–REVISED OCTOBER 2007
TYPICAL PERFORMANCE CURVES - SINGLE RATE (continued)
All specifications at TA = 25°C, VCC = 3.3 V, VDD = 5 V, master mode, fS = 48 kHz, system clock = 256 fS, 24-bit data, unless
otherwise noted.
TOTAL HARMONIC DISTORTION + NOISE
DYNAMIC RANGE AND SNR
vs
SAMPLING FREQUENCY
vs
SAMPLING FREQUENCY
120
115
110
105
100
−35
−40
−45
−50
−55
−90
−95
Dynamic Range
SNR
−100
−105
−110
−0.5 dB
−60 dB
32
44.1
48
32
44.1
48
f
− Sampling Frequency − kHz
S
G005
f
S
− Sampling Frequency − kHz
G006
Figure 5.
Figure 6.
TOTAL HARMONIC DISTORTION + NOISE
vs
SIGNAL LEVEL
0
−20
−40
−60
−80
−100
−120
−100
−80
−60
−40
−20
0
Signal Level − dB
G009
Figure 7.
10
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SLES022C–DECEMBER 2001–REVISED OCTOBER 2007
TYPICAL PERFORMANCE CURVES - SINGLE RATE (continued)
All specifications at TA = 25°C, VCC = 3.3 V, VDD = 5 V, master mode, fS = 48 kHz, system clock = 256 fS, 24-bit data, unless
otherwise noted.
AMPLITUDE
vs
FREQUENCY
AMPLITUDE
vs
FREQUENCY
0
−20
0
−20
Output Spectrum:
−0.5 dB,
N = 8192
−40
−40
Output Spectrum:
−60 dB,
−60
−60
N = 8192
−80
−80
−100
−120
−140
−160
−100
−120
−140
−160
0
12000
24000
0
12000
24000
f − Frequency − Hz
f − Frequency − Hz
G008
G007
Figure 8.
Figure 9.
TYPICAL PERFORMANCE CURVES - DUAL RATE
All specifications at TA = 25°C, VCC = 3.3 V, VDD = 5 V, master mode, and 24-bit data, unless otherwise noted.
AMPLITUDE
vs
FREQUENCY
AMPLITUDE
vs
FREQUENCY
0
−20
0
−20
f
= 96 kHz,
f = 96 kHz,
S
System Clock = 256 f
S
System Clock = 256 f
S
S
−40
−40
Output Spectrum:
−0.5 dB,
Output Spectrum:
−60 dB,
−60
−60
N = 8192
N = 8192
−80
−80
−100
−120
−140
−160
−100
−120
−140
−160
0
24000
48000
0
24000
48000
f − Frequency − Hz
f − Frequency − Hz
G010
G011
Figure 10.
Figure 11.
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SLES022C–DECEMBER 2001–REVISED OCTOBER 2007
TYPICAL PERFORMANCE CURVES - QUAD RATE
All specifications at TA = 25°C, VCC = 3.3 V, VDD = 5 V, master mode, 24-bit data, unless otherwise noted.
AMPLITUDE
vs
FREQUENCY
AMPLITUDE
vs
FREQUENCY
0
−20
0
−20
f
= 192 kHz,
f = 192 kHz,
S
System Clock = 128 f
S
System Clock = 128 f
S
S
−40
−40
Output Spectrum:
−0.5 dB,
Output Spectrum:
−60 dB,
−60
−60
N = 8192
N = 8192
−80
−80
−100
−120
−140
−160
−100
−120
−140
−160
0
48000
96000
0
48000
96000
f − Frequency − Hz
f − Frequency − Hz
G012
G013
Figure 12.
Figure 13.
TYPICAL PERFORMANCE CURVES - DSD MODE
All specifications at TA = 25°C, VCC = 3.3 V, VDD = 5 V, master mode, fS = 44.1 kHz, system clock = 16.9344 MHz, unless
otherwise noted.
AMPLITUDE
vs
FREQUENCY
AMPLITUDE
vs
FREQUENCY
0
−20
0
−20
−40
−40
−60
−60
Output Spectrum:
Output Spectrum:
−80
−80
−0.5 dB,
N = 8192
−60 dB,
N = 8192
−100
−120
−140
−160
−100
−120
−140
−160
0
11025
22050
0
11025
22050
f − Frequency − Hz
f − Frequency − Hz
G014
G015
Figure 14.
Figure 15.
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TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER
LINEAR PHASE ANTIALIAS DIGITAL FILTER FREQUENCY RESPONSE - Single-Rate
OVERALL CHARACTERISTICS
FOR SINGLE-RATE FILTER
STOP-BAND ATTENUATION CHARACTERISTICS
FOR SINGLE-RATE FILTER
50
0
0
−10
f
S
= 48 kHz
f = 48 kHz
S
−20
−30
−40
−50
−50
−60
−70
−80
−100
−150
−200
−90
−100
−110
−120
−130
−140
−150
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0.00
0.25
0.50
0.75
1.00
Normalized Frequency − y f
Normalized Frequency − y f
S
S
G016
G017
Figure 16.
Figure 17.
PASS-BAND RIPPLE CHARACTERISTICS
FOR SINGLE-RATE FILTER
TRANSIENT BAND CHARACTERISTICS
FOR SINGLE-RATE FILTER
0.02
0.00
0
−1
−2
−3
−4
−5
−6
−7
−8
−9
−10
f
= 48 kHz
S
f
S
= 48 kHz
−0.02
−0.04
−0.06
−0.08
−0.10
−6.04 dB at 0.5 f
S
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.45
0.47
0.49
0.51
0.53
0.55
Normalized Frequency − y f
Normalized Frequency − y f
S
S
G018
G019
Figure 18.
Figure 19.
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TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER (continued)
LINEAR PHASE ANTIALIAS DIGITAL FILTER FREQUENCY RESPONSE - Dual-Rate
OVERALL CHARACTERISTICS
FOR DUAL-RATE FILTER
STOP-BAND ATTENUATION CHARACTERISTICS
FOR DUAL-RATE FILTER
50
0
0
−10
f
S
= 96 kHz
f
S
= 96 kHz
−20
−30
−40
−50
−50
−60
−70
−80
−100
−150
−200
−90
−100
−110
−120
−130
−140
−150
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
0.00
0.25
0.50
0.75
1.00
Normalized Frequency − y f
Normalized Frequency − y f
S
S
G020
G021
Figure 20.
Figure 21.
PASS-BAND RIPPLE CHARACTERISTICS
FOR DUAL-RATE FILTER
TRANSIENT BAND CHARACTERISTICS
FOR DUAL-RATE FILTER
0.02
0.00
0
−1
−2
−3
−4
−5
−6
−7
−8
−9
−10
f
S
= 96 kHz
f = 96 kHz
S
−0.02
−0.04
−0.06
−0.08
−0.10
−6.02 dB at 0.5 f
S
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.45
0.47
0.49
0.51
0.53
0.55
Normalized Frequency − y f
Normalized Frequency − y f
S
S
G022
G023
Figure 22.
Figure 23.
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TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER (continued)
LINEAR PHASE ANTIALIAS DIGITAL FILTER FREQUENCY RESPONSE - Quad-Rate
OVERALL CHARACTERISTICS
FOR QUAD-RATE FILTER
STOP-BAND ATTENUATION CHARACTERISTICS
FOR QUAD-RATE FILTER
50
0
0
−10
f
S
= 192 kHz
f
S
= 192 kHz
−20
−30
−40
−50
−50
−60
−70
−80
−100
−150
−200
−90
−100
−110
−120
−130
−140
−150
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
0.00
0.25
0.50
0.75
1.00
Normalized Frequency − y f
Normalized Frequency − y f
S
S
G024
G025
Figure 24.
Figure 25.
PASS-BAND RIPPLE CHARACTERISTICS
FOR QUAD-RATE FILTER
TRANSIENT BAND CHARACTERISTICS
FOR QUAD-RATE FILTER
0.02
0.00
0
−1
−2
−3
−4
−5
−6
−7
−8
−9
−10
f
S
= 192 kHz
f
= 192 kHz
S
−0.02
−0.04
−0.06
−0.08
−0.10
−3.9 dB at 0.5 f
S
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.45
0.47
0.49
0.51
0.53
S
0.55
Normalized Frequency − y f
Normalized Frequency − y f
S
G026
G027
Figure 26.
Figure 27.
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TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER (continued)
HIGH-PASS FILTER (HPF) FREQUENCY RESPONSE
STOP-BAND CHARACTERISTICS
PASS-BAND CHARACTERISTICS
0.2
0.0
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−0.2
−0.4
−0.6
−0.8
−1.0
0.0
0.1
0.2
0.3
0.4
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Normalized Frequency − y f /1000
Normalized Frequency − y f /1000
S
S
G028
G029
Figure 28.
Figure 29.
PRINCIPLES OF OPERATION
THEORY OF OPERATION
The PCM1804 consists of a band-gap reference, a delta-sigma modulator with full-differential architecture for
L-channel and R-channel, a decimation filter with a high-pass filter, and a serial interface circuit. Figure 30
illustrates the total architecture of the PCM1804. An on-chip, high-precision reference with 10-μF external
capacitor(s) provides all the reference voltage needed in the PCM1804, and it defines the full-scale voltage range
of both channels. Full-differential architecture provides a wide dynamic range and excellent power-supply
rejection performance. The input signal is sampled at ×128, ×64, and ×32 oversampling rates according to the
overasmpling ratio control, OSR[0:2]. The single rate, dual rate, and quad rate eliminate the external sample-hold
amplifier. Figure 31 illustrates how for each oversampling ratio the PCM1804 decimates the modulator output
down to PCM data when the modulator is running at 6.144 MHz. The delta-sigma modulation randomizes the
modulator outputs and reduces the idle tone level. The oversampled data stream from the delta-sigma modulator
is converted to a 1-fS, 24-bit digital signal, while removing high-frequency noise components using a decimation
filter. The dc components of the signal are removed by the HPF, and the HPF output is converted to a
time-multiplexed serial signal through the serial interface, which provides flexible serial formats and master/slave
modes. The PCM1804 also has a DSD output mode. The PCM1804 can output the signal directly from the
modulators to DSDL (pin 16) and DSDR (pin 15).
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PRINCIPLES OF OPERATION (continued)
OSR0
OSR1
OSR2
CLK
Control
SCKI
V
L+
IN
Delta-Sigma
Modulator (L)
Decimation
Filter (L)
HPF
S/M
V
L−
IN
FMT0
FMT1
V
COM
L
AGNDL
V L
REF
V
L
REF
LRCK/DSDBCK
BCK/DSDL
Serial
Output
Interface
V
REF
R
V R
REF
DATA/DSDR
AGNDR
V R
COM
V
R+
Decimation
Filter (R)
IN
Delta-Sigma
Modulator (R)
OVFL
OVFR
HPF
V
R−
IN
BYPAS
RST
Power Supply
V
CC
AGND
DGND
V
DD
B0029-01
Figure 30. Total Block Diagram of PCM1804
0
Quad-Rate Filter
−20
−40
Dual-Rate Filter
−60
Modulator
Single-
−80
−100
−120
−140
−160
Rate
Filter
0
48
96
144
192
f − Frequency − kHz
G030
Figure 31. Spectrum of Modulator Output and Decimation Filter
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PRINCIPLES OF OPERATION (continued)
SYSTEM CLOCK INPUT
The PCM1804 supports 128 fS, 192 fS (only in master mode at quad rate), 256 fS, 384 fS, 512 fS, and 768 fS as a
system clock, where fS is the audio sampling frequency. The system clock must be supplied on SCKI (pin 18).
Table 3 shows the relationship of typical sampling frequency and the system clock frequency, and Figure 32
shows system clock timing. In master mode, the system clock rate is selected by OSR2 (pin 11), OSR1 (pin 10),
and OSR0 (pin 9) as shown in Table 1. In slave mode, the system clock rate is automatically detected. In DSD
mode, OSR2 (pin 11), OSR1 (pin 10), OSR0 (pin 9), and the system clock frequency are fixed as shown in
Table 1 and Table 3.
t
t
w(SCKL)
w(SCKH)
SCKI
2 V
SCKI
0.8 V
T0005B07
PARAMETER
MIN UNIT
tw(SCKH)
tw(SCKL)
System clock pulse duration, HIGH
System clock pulse duration, LOW
11
11
ns
ns
Figure 32. System Clock Input Timing
POWER-ON AND RESET FUNCTIONS
The PCM1804 has both an internal power-on-reset circuit and RST (pin 19). For internal power-on reset,
initialization (reset) is performed automatically at the time when the power supply VDD exceeds 2 V (typical) and
VCC exceeds 4 V (typical). RST accepts external forced reset, and a low level on RST initiates the reset
sequence. Because an internal pulldown resistor terminates RST, no connection of RST is equivalent to a
low-level input. Because the system clock is used as a clock signal for the reset circuit, the system clock must be
supplied as soon as power is supplied; more specifically, at least three system clocks are required prior to VDD
>
2 V, VCC > 4 V, and RST = high. While VDD < 2 V (typical), VCC < 4 V (typical), or RST = low, and 1/fS (maximum)
count after VDD > 2 V (typical),VCC > 4 V (typical) and RST = high, the PCM1804 stays in the reset state and the
digital output is forced to zero. The digital output is valid after the reset state is released and the time of 1116/fS
has passed. Figure 33 and Figure 34 illustrate the internal power-on-reset and external-reset timing, respectively.
Figure 35 illustrates the digital output for power-on reset and RST control. The PCM1804 needs RST = low when
control pins are changed or in slave mode when SCKI, LRCK, and BCK are changed.
POWER-DOWN FUNCTION
The PCM1804 has a power-down feature that is controlled by RST (pin 19). Entering the power-down mode is
done by keeping the RST input level low for more than 65536/fS. In the master mode, the SCKI (pin 18) is used
as the clock signal for the power-down counter. While in the slave mode, SCKI (pin 18) and LRCK (pin 17) are
used as the clock signal. The clock(s) must be supplied until the power-down sequence completes. As soon as
RST goes high, the PCM1804 starts the reset-release sequence described in the Power-On and Reset Functions
section.
OVERSAMPLING RATIO
The oversampling ratio is selected by OSR2 (pin 11), OSR1 (pin 10), and OSR0 (pin 9) as shown in Table 1 and
Table 2. The PCM1804 needs RST = low when logic levels on the OSR2, OSR1, and OSR0 pins are changed.
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Table 1. Oversampling Ratio in Master Mode
OSR2
Low
OSR1
Low
Low
High
High
Low
Low
High
High
Low
Low
OSR0
Low
High
Low
High
Low
High
Low
High
Low
High
OVERSAMPLING RATIO
Single rate (× 128 fS)
Single rate (× 128 fS)
Single rate (× 128 fS)
Single rate (× 128 fS)
Dual rate (× 64 fS)
SYSTEM CLOCK RATE
768 fS
512 fS
384 fS
256 fS
384 fS
256 fS
192 fS
128 fS
384 fS
256 fS
Low
Low
Low
High
High
High
High
High
High
Dual rate (× 64 fS)
Quad rate (× 32 fS)
Quad rate (× 32 fS)
DSD mode (× 64 fS)
DSD mode (× 64 fS)
Table 2. Oversampling Ratio in Slave Mode
OSR2
Low
OSR1
Low
OSR0
Low
OVERSAMPLING RATIO
Single rate (× 128 fS)
Dual rate (× 64 fS)
Quad rate (× 32 fS)(1)
Reserved
SYSTEM CLOCK RATE
Automatically detected
Low
Low
High
Low
Automatically detected
Low
High
High
Low
Automatically detected
Low
High
Low
–
–
–
–
–
High
High
High
High
Reserved
Low
High
Low
Reserved
High
High
Reserved
High
Reserved
(1) Only at the 128-fS system clock rate
Table 3. Sampling Frequency and System Clock Frequency
SYSTEM CLOCK FREQUENCY (MHz)
SAMPLING
FREQUENCY (kHz)
OVERSAMPLING RATIO
Single rate(2)
(1)
128 fS
192 fS
256 fS
8.192
11.2896
12.288
22.5792
24.576
–
384 fS
12.288
16.9344
18.432
33.8688
36.864
–
512 fS
768 fS
32
44.1
48
–
–
–
–
–
–
16.384
24.576
–
22.5792
33.8688
–
24.576
36.864
88.2
96
–
–
–
–
–
–
–
–
–
–
–
–
Dual rate(3)
176.4
192
44.1
22.5792
24.576
–
33.8688
36.864
–
Quad rate(4)
DSD mode(3)
–
–
11. 2896
16.9344
(1) Only available in master mode at the quad rate
(2) Modulator is running at 128 fS.
(3) Modulator is running at 64 fS.
(4) Modulator is running at 32 fS.
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4.4 V / 2.2 V
V , V
CC DD
4 V / 2 V
3.6 V / 1.8 V
Reset
Reset Removal
Internal Reset
System Clock
1024 System Clock + 1/f (Max)
S
T0014-07
Figure 33. Internal Power-On-Reset Timing
RST
RST Pulse Duration (t ) = 40 ns (Min)
(RST)
t
(RST)
Reset
Reset Removal
Internal Reset
System Clock
1/f (Max)
S
T0015-05
Figure 34. External Reset Timing
Power ON
RST ON
Reset Removal
Ready / Operation
Internal Reset
Reset
1116/f
S
(1)
(2)
Data
Converted Data
Zero Data
T0051-01
(1) In the DSD mode, DSDL is also controlled like DSDR.
(2) The HPF transient response appears initially.
Figure 35. ADC Digital Output for Power-On Reset and RST Control
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AUDIO DATA INTERFACE
The PCM1804 interfaces the audio system through BCK/DSDL (pin 16), LRCK/DSDBCK (pin 17), and
DATA/DSDR (pin 15). The PCM1804 needs RST = low when in the interface mode and/or the data format are
changed.
INTERFACE MODE
The PCM1804 supports master mode and slave mode as interface modes, which are selected by S/M (pin 8) as
shown in Table 4. In master mode, the PCM1804 provides the timing of the serial audio data communications
between the PCM1804 and the digital audio processor or external circuit. While in slave mode, the PCM1804
receives the timing for data transfer from an external controller. Slave mode is not available for DSD.
Table 4. Interface Mode
S/M
Low
High
MODE
Master mode
Slave mode
DATA FORMAT
The PCM1804 supports four audio data formats in both master and slave modes, and these data formats are
selected by FMT0 (pin 6) and FMT1 (pin 7) as shown in Table 5.
Table 5. Data Format
FMT1
Low
FMT0
Low
FORMAT
PCM, left-justified, 24-bit
PCM, I2S, 24-bit
MASTER
Yes
SLAVE
Yes
Yes
Yes
–
Low
High
Low
Yes
High
High
PCM, standard, 24-bit
DSD
Yes
High
Yes
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INTERFACE TIMING FOR PCM
Figure 36 through Figure 38 illustrate the interface timing for PCM.
(1) Left-Justified Data Format; L-Channel = High, R-Channel = Low
1/f
S
LRCK
L-Channel
R-Channel
BCK
DATA
1
2
3
22 23 24
1
2
3
22 23 24
1 2
(2) I2S Data Format; L-Channel = Low, R-Channel = High
1/f
S
L-Channel
R-Channel
LRCK
BCK
1
2
3
22 23 24
1
2
3
22 23 24
1 2
DATA
(3) Standard Data Format; L-Channel = High, R-Channel = Low
1/f
S
L-Channel
R-Channel
LRCK
BCK
22 23 24
1
2
3
22 23 24
1
2
3
22 23 24
DATA
T0009-03
NOTE: LRCK and BCK work as outputs in master mode and as inputs in slave mode.
Figure 36. Audio Data Format for PCM
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t
(LRCP)
0.5 V
LRCK
DD
t
w(BCKL)
t
(CKLR)
t
w(BCKH)
0.5 V
BCK
DD
t
t
t
(CKDO)
(LRDO)
(BCKP)
0.5 V
DATA
DD
T0018-03
PARAMETERS
MIN
TYP
1/(64 fS)(3)
MAX
UNIT
t(BCKP)
tw(BCKH)
tw(BCKL)
t(CKLR)
t(LRCP)
t(CKDO)
t(LRDO)
tr
BCK period
BCK pulse duration, HIGH
BCK pulse duration, LOW
32
ns
ns
ns
32
–5
Delay time, BCK falling edge to LRCK valid
LRCK period
15
1/fS
Delay time, BCK falling edge to DATA valid
Delay time, LRCK edge to DATA valid
Rising time of all signals(1)(2)
–5
–5
15
15
10
10
ns
ns
ns
ns
tf
Falling time of all signals(1)(2)
(1) Rising and falling times are measured from 10% to 90% of IN/OUT signal swing.
(2) Load capacitance of all signals is 10 pF.
(3) t(BCKP) is fixed at 1/(64 fS) in case of master mode.
Figure 37. Audio Data Interface Timing for PCM (Master Mode: LRCK and BCK Work as Outputs)
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t
(LRCP)
1.4 V
LRCK
t
t
(LRSU)
w(BCKL)
t
t
(LRHD)
w(BCKH)
1.4 V
BCK
t
t
(LRDO)
t
(CKDO)
(BCKP)
0.5 V
DATA
DD
T0017-03
PARAMETERS
MIN
1/(64 fS)
32
TYP
MAX
UNIT
t(BCKP)
BCK period
1/(48 fS)
tw(BCKH)
tw(BCKL)
t(LRSU)
t(LRHD)
t(LRCP)
t(CKDO)
t(LRDO)
tr
BCK pulse duration, HIGH
BCK pulse duration, LOW
ns
ns
ns
ns
32
LRCK setup time to BCK rising edge
LRCK hold time to BCK rising edge
LRCK period
12
12
1/fS
Delay time, BCK falling edge to DATA valid
Delay time, LRCK edge to DATA valid
Rising time of all signals(1)(2)
5
5
25
25
10
10
ns
ns
ns
ns
tf
Falling time of all signals(1)(2)
(1) Rising and falling times are measured from 10% to 90% of IN/OUT signals swing.
(2) Load capacitance of DATA/DSDR signal is 10 pF.
Figure 38. Audio Data Interface Timing for PCM (Slave Mode: LRCK and BCK Work as Inputs)
INTERFACE TIMING FOR DSD
Figure 39 and Figure 40 illustrate the interface timing for DSD.
DSDBCK
DSDL
DSDR
D
D
D
D
D
D
D
D
D
D
D
D
D
D
n−3
n−2
n−1
n
n+1
n+2
n+3
n−3
n−2
n−1
n
n+1
n+2
n+3
T0052−01
Figure 39. Audio Data Format
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t
t
w(BCKL)
w(BCKH)
t
(CKDO)
DSDBCK
0.5 V
0.5 V
DD
t
(BCKP)
DSDL
DSDR
DD
T0053−01
PARAMETERS
MIN
TYP
354
MAX
UNIT
ns
t(BCKP)
DSDBCK period
tw(BCKH)
tw(BCKL)
t(CKDO)
tr
DSDBCK pulse duration, HIGH
DSDBCK pulse duration, LOW
177
177
ns
ns
Delay time DSDBCK falling edge to DSDL, DSDR valid
Rising time of all signals(1)(2)
Falling time of all signals(1)(2)
–5
15
ns
10
10
ns
tf
ns
(1) Rising and falling times are measured from 10% to 90% of IN/OUT signal swing.
(2) Load capacitance of DSDBCK/DSDL/DSDR signal is 10 pF.
Figure 40. Audio Data Interface Timing for DSD (Master Mode Only)
SYNCHRONIZATION WITH DIGITAL AUDIO SYSTEM FOR PCM
In slave mode, the PCM1804 operates under LRCK synchronized with the system clock SCKI. The PCM1804
does not need a specific phase relationship between LRCK and SCKI, but does require the synchronization of
LRCK and SCKI.
If the relationship between LRCK and SCKI changes more than ±6 BCK during one sample period due to LRCK
or SCKI jitter, internal operation of the ADC halts within 1/fS and digital output is forced into BPZ code until
resynchronization between LRCK and SCKI is completed.
In case of changes less than ±5 BCK, resynchronization does not occur and the previously described digital
output control and discontinuity do not occur.
Figure 41 illustrates ADC digital output for loss of synchronization and resynchronization. During undefined data,
the PCM1804 may generate some noise in the audio signal. Also, the transitions of normal to undefined data and
undefined or zero data to normal cause a discontinuity of data on the digital output. This can generate noise in
the audio signal. In master mode, synchronization loss never occurs.
HIGH-PASS FILTER (HPF) BYPASS CONTROL FOR PCM
The built-in function for dc component rejection can be bypassed by BYPAS (pin 12) control. In bypass mode,
the dc component of the input analog signal and the internal dc offset are also converted and output in the digital
output data.
HPF Bypass Control
BYPAS PIN
Low
HPF MODE
Normal (high-pass) mode
Bypass (through) mode
High
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PCM1804
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SLES022C–DECEMBER 2001–REVISED OCTOBER 2007
OVERFLOW FLAG FOR PCM
The PCM1804 has two overflow flag pins, OVFR (pin 20) and OVFL (pin 21). The pins go to high as soon as the
analog input goes across the full-scale range. The high level is held for 1.016 s at maximum, and returns to low if
the analog input does not go across the full-scale range for the period.
Resynchronization
Synchronization Lost
Synchronous
Asynchronous
Synchronous
State of Synchronization
1/f
S
90/f
S
Undefined
Data
(1)
(2)
DATA
Normal Data
Zero Data
Converted Data
T0020-06
(1) Applies only for slave mode; the loss of synchronization never occurs in master mode.
(2) The HPF transient response appears initially.
Figure 41. ADC Digital Output for Loss of Synchronization and Resynchronization
26
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Product Folder Link(s): PCM1804
PCM1804
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SLES022C–DECEMBER 2001–REVISED OCTOBER 2007
TYPICAL CIRCUIT CONNECTION DIAGRAM
Figure 42 illustrates a typical circuit connection diagram in the PCM data format operation.
PCM1804
C
C
1
2
+
+
28 +
1
2
3
4
V
L
V
R
REF
REF
27
26
25
24
23
AGNDL
AGNDR
C
4
C
3
+
V
V
V
L
V
COM
R
COM
L+
L−
V
R+
R−
+
−
+
−
IN
IN
IN
L-Channel In
Format [1:0]
R-Channel In
5
6
V
IN
FMT0
FMT1
S/M
AGND
5 V
C
6
7
8
22
21
20
19
+
V
CC
OVFL
OVFR
RST
Master/Slave
Overflow
9
OSR0
OSR1
OSR2
Control
10
11
12
13
14
Oversampling
Ratio [2:0]
Reset
18
17
16
15
SCKI
System Clock
BYPAS LRCK/DSDBCK
HPF Bypass
3.3 V
L/R Clock
Data Clock
Data Out
Audio Data
Processor
DGND
BCK/DSDL
C
5
+
V
DD
DATA/DSDR
S0058-01
A. C1, C2, C5, and C6: Bypass capacitors, 0.1-μF ceramic and 10-μF tantalum, depending on layout and power supply
B. C3, C4: Bypass capacitor, 0.1-μF tantalum, depending on layout and power supply
Figure 42. Typical Circuit Connection Diagram for PCM
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PCM1804
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SLES022C–DECEMBER 2001–REVISED OCTOBER 2007
Figure 43 illustrates a typical circuit connection diagram in the DSD data format operation.
PCM1804
C
C
1
2
+
28 +
1
2
3
4
V
L
V
R
REF
REF
27
26
25
24
23
AGNDL
AGNDR
C
4
C
3
+
+
V
V
V
L
V
COM
R
COM
L+
L−
V
R+
R−
+
−
+
−
IN
IN
IN
L-Channel In
Format [1:0]
R-Channel In
5
6
V
IN
FMT0
FMT1
S/M
AGND
5 V
C
6
7
22
21
20
19
+
V
CC
8
9
OVFL
OVFR
RST
Master/Slave
Overflow
OSR0
OSR1
OSR2
Control
10
11
12
13
14
Oversampling
Ratio [2:0]
Reset
18
17
16
15
SCKI
System Clock
BYPAS LRCK/DSDBCK
HPF Bypass
3.3 V
Data Clock
Audio Data
Processor
DGND
BCK/DSDL
L-Channel Data Out
R-Channel Data Out
C
5
+
V
DD
DATA/DSDR
S0058-02
A. C1, C2, C5, and C6: Bypass capacitors, 0.1-μF ceramic and 10-μF tantalum, depending on layout and power supply
B. C3 and C4: Bypass capacitors, 0.1-μF tantalum, depending on layout and power supply
Figure 43. Typical Circuit Connection Diagram for DSD
28
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Product Folder Link(s): PCM1804
PCM1804
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SLES022C–DECEMBER 2001–REVISED OCTOBER 2007
APPLICATION INFORMATION
BOARD DESIGN AND LAYOUT CONSIDERATIONS
VCC, VDD Pins
The digital and analog power supply lines to the PCM1804 should be bypassed to the corresponding ground pins
with 0.1-μF ceramic and 10-μF tantalum capacitors placed as close to the pins as possible to maximize the
dynamic performance of the ADC. Although the PCM1804 has two power lines to maximize the potential of
dynamic performance, using one common power supply is recommended to avoid unexpected power-supply
trouble like latch-up or power-supply sequence.
VIN Pins
Use of 0.01-μF film capacitors between VINL+ and VINL– and between VINR+ and VINR– is strongly
recommended to remove higher-frequency noise from the delta-sigma input section.
VREFX, VCOMX Inputs
Use 0.1-μF ceramic and 10-μF tantalum capacitors between VREFL, VREFR, and corresponding AGNDx, to ensure
low-source impedance at ADC references. Use 0.1-μF tantalum capacitors between VCOML, VCOMR and
corresponding AGNDx to ensure low source impedance of common voltage. These capacitors should be located
as close as possible to the VREFL, VREFR, VCOML, and VCOMR pins to reduce dynamic errors on references and
common voltage. The dc voltage level of these pins is 2.5 V.
DATA/DSDR, BCK/DSDL, and LRCK/DSDBCK Pins
The DATA/DSDR, BCK/DSDL, and LRCK/DSDBCK pins in master mode have large load drive capability.
Locating the buffer near the PCM1804 and minimizing the load capacitance, minimizes the digital-analog
crosstalk and maximizes the dynamic performance of the ADC.
System Clock
The quality of the system clock can influence dynamic performance, as the PCM1804 operates based on a
system clock. Therefore, it might be necessary to consider the system clock duty, jitter, and the time difference
between system clock transition and BCK/DSDL or LRCK/DSDBCK transition in slave mode.
Reset Control
If capacitors larger than 10 μF are used on VREFL and VREFR, an external reset control with a delay time
corresponding to the VREFL and VREFR response is required. Also, it works as a power-down control.
APPLICATION CIRCUIT FOR SINGLE-ENDED INPUT
An application diagram for a single-ended input circuit is shown in Figure 44. The maximum signal input voltage
and differential gain of this circuit is designed as Vinmax = 8.28 Vpp, Ad = 0.3. Differential gain (Ad) is given by
R3/R1(R4/R2) in a circuit configured as a normal inverted-gain amplifier. Resistor R5(R6) in the feedback loop
gives low-impedance drive operation and noise filtering for the analog input of the PCM1804. The circuit
technique using R5(R6) is recommended.
Copyright © 2001–2007, Texas Instruments Incorporated
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PCM1804
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SLES022C–DECEMBER 2001–REVISED OCTOBER 2007
R = 1 kΩ
3
(1)
C
4.7 kΩ
PCM1804
4.7 kΩ
10 µF
_
+
R = 3.3 kΩ
1
Analog In
_
R = 47 Ω
5
+
V −
IN
+
OPA2134 1/2
OPA2134 1/2
V
COM
0.01 µF
R = 1 kΩ
4
0.1 µF
(1)
C
10 µF
R = 3.3 kΩ
2
_
R = 47 Ω
6
+
V +
IN
+
OPA2134 1/2
S0059-01
(1) A capacitor value of 1800 pF is recommended, unless an input signal greater than –6 dBFS at 100 kHz or higher is
applied in the DSD mode. In that case, 3300 pF is recommended.
Figure 44. Application Circuit for Single-Ended Input Circuit (PCM)
V +
IN
∆Σ Modulator
V −
IN
_
+
V
COM
V
REF
BGR
_
+
S0060-01
Figure 45. Equivalent Circuit of Internal Reference (VCOM, VREF
)
30
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Product Folder Link(s): PCM1804
PACKAGE OPTION ADDENDUM
www.ti.com
26-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PCM1804DB
PCM1804DBG4
PCM1804DBR
PCM1804DBRG4
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
SSOP
SSOP
SSOP
DB
DB
DB
DB
28
28
28
28
47
47
RoHS & Green
RoHS & Green
Call TI | NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-10 to 70
-10 to 70
-10 to 70
-10 to 70
PCM1804
Samples
Samples
Samples
Samples
Call TI
Call TI | NIPDAU
Call TI
PCM1804
PCM1804
PCM1804
2000 RoHS & Green
2000 RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
26-Oct-2022
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF PCM1804 :
Automotive : PCM1804-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Jul-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
PCM1804DBR
SSOP
DB
28
2000
330.0
16.4
8.2
10.5
2.5
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Jul-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SSOP DB 28
SPQ
Length (mm) Width (mm) Height (mm)
356.0 356.0 35.0
PCM1804DBR
2000
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Jul-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
PCM1804DB
PCM1804DB
DB
DB
DB
DB
DB
DB
DB
DB
SSOP
SSOP
SSOP
SSOP
SSOP
SSOP
SSOP
SSOP
28
28
28
28
28
28
28
28
47
47
530
530
530
530
530
530
530
530
10.5
10.5
10.5
10.5
10.5
10.5
10.5
10.5
4000
4000
4000
4000
4000
4000
4000
4000
4.1
4.1
4.1
4.1
4.1
4.1
4.1
4.1
PCM1804DB
47
PCM1804DBG4
PCM1804DBG4
PCM1804DBG4
PCM1804DBR
PCM1804DBRG4
47
47
47
2000
2000
Pack Materials-Page 3
PACKAGE OUTLINE
DB0028A
SSOP - 2 mm max height
S
C
A
L
E
1
.
5
0
0
SMALL OUTLINE PACKAGE
C
8.2
7.4
TYP
A
0.1 C
SEATING
PIN 1 INDEX AREA
PLANE
26X 0.65
28
1
2X
10.5
9.9
8.45
NOTE 3
14
15
0.38
0.22
28X
0.15
C A B
5.6
5.0
B
NOTE 4
2 MAX
0.25
GAGE PLANE
(0.15) TYP
SEE DETAIL A
0.95
0.55
0.05 MIN
0 -8
A
15
DETAIL A
TYPICAL
4214853/B 03/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-150.
www.ti.com
EXAMPLE BOARD LAYOUT
DB0028A
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
SYMM
28X (1.85)
(R0.05) TYP
28
1
28X (0.45)
26X (0.65)
SYMM
14
15
(7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4214853/B 03/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DB0028A
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
28X (1.85)
SYMM
(R0.05) TYP
28
1
28X (0.45)
26X (0.65)
SYMM
14
15
(7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4214853/B 03/2018
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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