PCM1820IRTER [TI]
PCM182x Stereo Channel, 32-Bit, 192-kHz, Burr-BrownTM Audio ADC;
| 型号： | PCM1820IRTER |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | PCM182x Stereo Channel, 32-Bit, 192-kHz, Burr-BrownTM Audio ADC PC |
| 文件： | 总41页 (文件大小：3291K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PCM1820, PCM1821
SBASA61A – DECEMBER 2020 – REVISED JUNE 2021
PCM182x Stereo Channel, 32-Bit, 192-kHz, Burr-BrownTM Audio ADC
1 Features
3 Description
•
Stereo high-performance ADC:
– 2-channel analog microphones or line-in
ADC line and microphone differential input
performance:
The PCM182x is a high-performance, Burr-Brown™
audio analog-to-digital converter (ADC) that supports
simultaneous sampling of up to two analog channels.
The device supports differential line and microphone
inputs with a 2-VRMS full-scale signal. The device
•
– PCM1820 dynamic range:
integrates
a
phase-locked loop (PLL),
a
DC
•
•
123-dB, dynamic range enhancer enabled
113-dB, dynamic range enhancer disabled
removal high-pass filter (HPF), and supports sample
rates up to 192 kHz. The device supports time-
division multiplexing (TDM) or I2S audio formats,
selectable with the hardware pin level. Additionally,
the PCM182x supports master and slave mode
selection for the audio bus interface operation.
These integrated high-performance features, along
with the ability to be powered from a single supply
of 3.3 V, make the device an excellent choice for cost-
sensitive, space-constrained audio systems in far-field
microphone recording applications.
– PCM1821 dynamic range: 106 dB
– THD+N: –95 dB
•
•
•
•
•
ADC differential 2-VRMS full-scale input
ADC sample rate (fS) = 8 kHz to 192 kHz
Hardware pin control configurations
Linear-phase or low-latency filter selection
Flexible audio serial data interface:
– Master or slave interface selection
– 32-bits, 2-channel TDM
– 32-bits, 2-channel I2S
•
•
•
•
•
Automatic power-down upon loss of audio clocks
Integrated high-performance audio PLL
Single-supply operation: 3.3 V
I/O-supply operation: 3.3 V or 1.8 V
Power consumption for 3.3-V AVDD supply:
– 19.6 mW/channel at 16-kHz sample rate
– 21.3 mW/channel at 48-kHz sample rate
The PCM182x is specified from –40°C to +125°C, and
is offered in a 20-pin WQFN package.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
3.00 mm × 3.00 mm with
0.5-mm pitch
PCM182x
WQFN (20)
(1) For all available packages, see the package option
addendum at the end of the data sheet.
2 Applications
•
•
•
•
•
Smart speakers
DVD recorders and players
AV receivers
Video conference systems
IP network cameras
Simplified Block Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
PCM1820, PCM1821
SBASA61A – DECEMBER 2020 – REVISED JUNE 2021
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings ....................................... 5
7.2 ESD Ratings .............................................................. 5
7.3 Recommended Operating Conditions ........................5
7.4 Thermal Information ...................................................6
7.5 Electrical Characteristics ............................................6
7.6 Timing Requirements: TDM, I2S or LJ Interface ........ 8
7.7 Switching Characteristics: TDM, I2S or LJ
8.2 Functional Block Diagram.........................................13
8.3 Feature Description...................................................14
8.4 Device Functional Modes..........................................27
9 Application and Implementation..................................28
9.1 Application Information............................................. 28
9.2 Typical Application.................................................... 28
10 Power Supply Recommendations..............................31
11 Layout...........................................................................32
11.1 Layout Guidelines................................................... 32
11.2 Layout Example...................................................... 32
12 Device and Documentation Support..........................33
12.1 Receiving Notification of Documentation Updates..33
12.2 Support Resources................................................. 33
12.3 Trademarks.............................................................33
12.4 Electrostatic Discharge Caution..............................33
12.5 Glossary..................................................................33
13 Mechanical, Packaging, and Orderable
Interface ....................................................................... 8
7.8 Typical Characteristics................................................9
8 Detailed Description......................................................13
8.1 Overview...................................................................13
Information.................................................................... 33
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (December 2020) to Revision A (June 2021)
Page
•
Changed document status from advance information to production data.......................................................... 1
Copyright © 2021 Texas Instruments Incorporated
2
Submit Document Feedback
Product Folder Links: PCM1820 PCM1821
PCM1820, PCM1821
SBASA61A – DECEMBER 2020 – REVISED JUNE 2021
www.ti.com
5 Device Comparison Table
FEATURE
Control interface
PCM1821
PCM1820
TLV320ADC3120
TLV320ADC5120
I2C
TLV320ADC6120
Pin control
TDM or I2S
Digital audio serial interface
Audio analog channel
TDM or I2S or left-justified (LJ)
2
Digital microphone channel
Programmable MICBIAS voltage
Dynamic range (DRE disabled)
Dynamic range (DRE enabled)
ADC SNR with DRE
Not available
N/A
4
Yes
106 dB
113 dB
123 dB
123 dB
2.5 kΩ
106 dB
Not available
N/A
108 dB
113 dB
123 dB
123 dB
Not available
N/A
120 dB
120 dB
Input impedance
10 kΩ
2.5 kΩ, 10 kΩ, 20 kΩ
Compatibility
Pin-to-pin, package, drop-in replacements of
each other
Pin-to-pin, package, and control registers compatible; drop-in
replacements of each other
Package
WQFN (RTE), 20-pin, 3.00 mm × 3.00 mm (0.5-mm pitch)
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
3
Product Folder Links: PCM1820 PCM1821
PCM1820, PCM1821
SBASA61A – DECEMBER 2020 – REVISED JUNE 2021
www.ti.com
6 Pin Configuration and Functions
20
VSS
VSS
15
IN1P
1
14
13
12
11
DREG
MSZ
MD0
MD1
IN1M
IN2P
IN2M
2
3
4
Thermal Pad (VSS)
5
VSS
VSS
10
Not to scale
Figure 6-1. RTW Package, 24-Pin WQFN With Exposed Thermal Pad, Top View
Table 6-1. Pin Functions
PIN
TYPE
DESCRIPTION
NO.
1
NAME
IN1P
IN1M
IN2P
Analog input
Analog input
Analog input
Analog input
Analog supply
Digital output
Digital I/O
Analog input 1P pin.
Analog input 1M pin.
Analog input 2P pin.
Analog input 2M pin.
2
3
4
IN2M
VSS
5
Short this pin directly to the board ground plane.
Audio serial data interface bus output.
6
SDOUT
BCLK
FSYNC
IOVDD
VSS
7
Audio serial data interface bus bit clock.
8
Digital I/O
Audio serial data interface bus frame synchronization signal.
Digital I/O power supply (1.8 V or 3.3 V, nominal).
Short this pin directly to the board ground plane.
Device configuration mode select 1 pin.
9
Digital supply
Analog supply
Digital input
Digital input
Digital input
Digital supply
Analog supply
Analog supply
Analog supply
Analog
10
11
12
13
14
15
16
17
18
19
20
MD1
MD0
Device configuration mode select 0 pin.
MSZ
Audio interface bus master or slave select pin.
Digital regulator output voltage for digital core supply (1.5 V, nominal).
Short this pin directly to the board ground plane.
Analog power (3.3 V, nominal).
DREG
VSS
AVDD
AREG
VREF
FMT0
VSS
Analog on-chip regulator output voltage for analog supply (1.8 V, nominal).
Analog reference voltage filter output.
Digital input
Analog supply
Audio interface format select pin referred to AVDD supply.
Short this pin directly to the board ground plane.
Thermal pad shorted to internal device ground. Short thermal pad directly to board
ground plane.
Thermal Pad (VSS)
Ground supply
Copyright © 2021 Texas Instruments Incorporated
4
Submit Document Feedback
Product Folder Links: PCM1820 PCM1821
PCM1820, PCM1821
SBASA61A – DECEMBER 2020 – REVISED JUNE 2021
www.ti.com
7 Specifications
7.1 Absolute Maximum Ratings
over the operating ambient temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–40
MAX
UNIT
AVDD to AVSS
3.9
Supply voltage
AREG to AVSS
2.0
3.9
V
IOVDD to VSS (thermal pad)
AVSS to VSS (thermal pad)
Analog input pins voltage to AVSS
Digital input pins voltage to VSS (thermal pad)
Operating ambient, TA
Ground voltage differences
Analog input voltage
Digital input voltage
0.3
V
V
V
AVDD + 0.3
IOVDD + 0.3
125
Temperature
Junction, TJ
–40
150
°C
Storage, Tstg
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
7.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
NOM
MAX
UNIT
POWER
AVDD,
Analog supply voltage AVDD to AVSS (AREG is generated using onchip regulator) -
AVDD 3.3-V operation
3.0
3.3
3.6
V
V
AREG(1)
IO supply voltage to VSS (thermal pad) - IOVDD 3.3-V operation
IO supply voltage to VSS (thermal pad) - IOVDD 1.8-V operation
3.0
3.3
1.8
3.6
IOVDD
1.65
1.95
INPUTS
Analog input pins and FMT0 voltage to VSS
0
0
AVDD
V
V
Digital input pins voltage(except FMT0) to VSS (thermal pad)
IOVDD
TEMPERATURE
TA
Operating ambient temperature
–40
125
°C
OTHERS
Digital input pin used as MCLK input clock frequency
Digital output load capacitance
36.864
50
MHz
pF
CL
20
(1) AVSS and VSS (thermal pad): all ground pins must be tied together and must not differ in voltage by more than 0.2 V.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
5
Product Folder Links: PCM1820 PCM1821
PCM1820, PCM1821
www.ti.com
UNIT
SBASA61A – DECEMBER 2020 – REVISED JUNE 2021
7.4 Thermal Information
PCM182x
RTE (WQFN)
20 PINS
55.9
THERMAL METRIC(1)
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
33.1
23.4
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.6
ψJB
23.3
RθJC(bot)
16.7
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, fIN = 1-kHz sinusoidal signal, fS = 48 kHz, 32-bit audio data, BCLK = 256 × fS,
TDM slave mode (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ADC CONFIGURATION
AC input impedance
(PCM1820)
2.5
10
kΩ
kΩ
Input pins INxP or INxM
AC input impedance
(PCM1821)
PCM1820: ADC PERFORMANCE FOR LINE, MICROPHONE INPUT RECORDING : AVDD 3.3-V OPERATION
Differential input full-scale
AC-coupled input
2
122
112
123
113
–95
–95
VRMS
AC signal voltage
IN1 differential input selected and AC signal shorted to
ground, DRE enabled (DRE_LVL =
–36 dB, DRE_MAXGAIN = 24 dB)
115
Signal-to-noise ratio, A-
weighted(1) (2)
SNR
DR
dB
IN1 differential input selected and AC signal shorted to
ground, DRE disabled
106
IN1 differential input selected and –60-dB full-scale
AC signal input, DRE enabled (DRE_LVL = –36 dB,
DRE_MAXGAIN = 24 dB)
Dynamic range, A-
weighted(2)
dB
dB
IN1 differential input selected and –60-dB full-scale AC
signal input, DRE disabled
IN1 differential input selected and –1-dB full-scale AC
signal input, DRE enabled (DRE_LVL =
–36 dB, DRE_MAXGAIN = 24 dB)
–80
Total harmonic distortion(2)
THD+N
(3)
IN1 differential input selected and –1-dB full-scale AC
signal input, DRE disabled
PCM1821: ADC PERFORMANCE FOR LINE, MICROPHONE INPUT RECORDING : AVDD 3.3-V OPERATION
Differential input full-scale
AC-coupled input
2
106
106
–95
VRMS
dB
AC signal voltage
Signal-to-noise ratio, A-
weighted(1) (2)
IN1 differential input selected and AC signal shorted to
ground
SNR
DR
100
Dynamic range, A-
weighted(1) (2)
IN1 differential input selected and –60-dB full-scale AC
signal input
dB
Total harmonic distortion(2) IN1 differential input selected and –1-dB full-scale AC
THD+N
dB
(3)
signal input
ADC OTHER PARAMETERS
Output data sample rate
7.35
192
32
kHz
Bits
Output data sample word
length
–1-dB full-scale AC-signal input to non measurement
channel
Interchannel isolation
–124
0.1
dB
dB
Interchannel gain mismatch –6-dB full-scale AC-signal input
Copyright © 2021 Texas Instruments Incorporated
6
Submit Document Feedback
Product Folder Links: PCM1820 PCM1821
PCM1820, PCM1821
SBASA61A – DECEMBER 2020 – REVISED JUNE 2021
www.ti.com
7.5 Electrical Characteristics (continued)
at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, fIN = 1-kHz sinusoidal signal, fS = 48 kHz, 32-bit audio data, BCLK = 256 × fS,
TDM slave mode (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Gain drift(4)
Across temperature range -40°C to 125°C
40.5
ppm/°C
Interchannel phase
mismatch
1-kHz sinusoidal signal
0.02
0.0005
102
Degrees
1-kHz sinusoidal signal, across temperature range -40°C
to 125°C
Phase drift(5)
Degrees/°C
Power-supply rejection
ratio
100-mVPP, 1-kHz sinusoidal signal on AVDD, differential
input selected, 0-dB channel gain
PSRR
dB
dB
dB
PCM1820:
CMRR
Common-mode rejection
ratio
Differential microphone input selected, 100-mVPP, 1-kHz
signal on both pins and measure level at output
45
PCM1821:
CMRR
Common-mode rejection
ratio
Differential microphone input selected, 100-mVPP, 1-kHz
signal on both pins and measure level at output
60
DIGITAL I/O
0.30 ×
IOVDD
All digital pins except FMT0, IOVDD 1.8-V operation
–0.3
V
Low-level digital input logic
voltage threshold
VIL
All digital pins except FMT0, IOVDD 3.3-V operation
FMT0 Pin
–0.3
–0.3
0.8
0.8
V
V
V
V
All digital pins except FMT0, IOVDD 1.8-V operation
All digital pins except FMT0, IOVDD 3.3-V operation
FMT0 Pin
0.7 × IOVDD
2.1
IOVDD + 0.3
IOVDD + 0.3
AVDD + 0.3
0.45
High-level digital input logic
voltage threshold
VIH
2.1
All digital pins, IOL = –2 mA, IOVDD 1.8-V operation
All digital pins, IOL = –2 mA, IOVDD 3.3-V operation
Low-level digital output
voltage
VOL
0.4
IOVDD –
0.45
All digital pins, IOH = 2 mA, IOVDD 1.8-V operation
All digital pins, IOH = 2 mA, IOVDD 3.3-V operation
All digital pins, input = IOVDD
High-level digital output
voltage
VOH
V
2.4
–5
Input logic-high leakage for
digital inputs
IIH
0.1
0.1
5
5
5
µA
µA
pF
Input logic-low leakage for
digital inputs
IIL
All digital pins, input = 0 V
All digital pins
–5
Input capacitance for digital
inputs
CIN
Pulldown resistance for
digital I/O pins when
asserted on
RPD
20
kΩ
TYPICAL SUPPLY CURRENT CONSUMPTION
IAVDD
AVDD = 3.3 V, internal AREG
0.5
0.5
mA
µA
Current consumption with
all Clocks disabled
IIOVDD
IIOVDD
IAVDD
All external clocks stopped, IOVDD = 3.3 V
All external clocks stopped, IOVDD = 1.8 V
AVDD = 3.3 V, internal AREG
IOVDD = 3.3 V
0.3
Current consumption with
ADC 2-channel operating
at fS 16-kHz, BCLK = 256
× fS and DRE disabled
11.9
0.05
0.02
12.9
0.1
IIOVDD
IIOVDD
IAVDD
mA
mA
mA
IOVDD = 1.8 V
Current consumption with
ADC 2-channel operating
at fS 48-kHz, BCLK = 256
× fS and DRE disabled
AVDD = 3.3 V, internal AREG
IOVDD = 3.3 V
IIOVDD
IIOVDD
IAVDD
IOVDD = 1.8 V
0.05
14
AVDD = 3.3 V, internal AREG
IOVDD = 3.3 V
Current consumption with
ADC 2-channel operating
at fS 48-kHz, BCLK = 256
× fS and DRE enabled
IIOVDD
IIOVDD
0.1
IOVDD = 1.8 V
0.05
(1) Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with the AC signal input shorted to ground, measured
A-weighted over a 20-Hz to 20-kHz bandwidth using an audio analyzer.
(2) All performance measurements done with a 20-kHz, low-pass filter and, where noted, an A-weighted filter. Failure to use such a filter
may result in higher THD and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values.
(3) For best distortion performance, use input AC-coupling capacitors with a low-voltage-coefficient.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
7
Product Folder Links: PCM1820 PCM1821
PCM1820, PCM1821
SBASA61A – DECEMBER 2020 – REVISED JUNE 2021
www.ti.com
(4) Gain drift =gain_variation(in temperature range)/ typical gain value(gain at room temperature) / temperature range × 106 measured
with gain in linear scale.
(5) Phase drift =phase_deviation(in temperature range)/ (temperature range).
7.6 Timing Requirements: TDM, I2S or LJ Interface
at TA = 25°C, IOVDD = 3.3 V or 1.8 V and 20-pF load on all outputs (unless otherwise noted)
MIN
40
25
25
8
NOM
MAX
UNIT
ns
t(BCLK)
BCLK period
tH(BCLK)
tL(BCLK)
tSU(FSYNC)
tHLD(FSYNC)
tr(BCLK)
BCLK high pulse duration (1)
BCLK low pulse duration (1)
FSYNC setup time
FSYNC hold time
BCLK rise time
ns
ns
ns
8
ns
10% - 90% rise time(2)
90% - 10% fall time(2)
10
10
ns
tf(BCLK)
BCLK fall time
ns
(1) The BCLK minimum high or low pulse duration must be higher than 25 ns (to meet the timing specifications), if the SDOUT data line is
latched on the opposite BCLK edge polarity than the edge used by the device to transmit SDOUT data.
(2) BCLK maximum rise and fall time can be relaxed to 13ns if BCLK frequency used in the system is below 20 MHz. This can cause
noise increase due to higher clock jitter.
7.7 Switching Characteristics: TDM, I2S or LJ Interface
at TA = 25°C, IOVDD = 3.3 V or 1.8 V and 20-pF load on all outputs (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
td(SDOUT-BCLK)
td(SDOUT-FSYNC)
BCLK to SDOUT delay
50% of BCLK to 50% of SDOUT
3
18
ns
FSYNC to SDOUT delay in TDM
or LJ mode (for MSB data with
TX_OFFSET = 0)
50% of FSYNC to 50% of
SDOUT
18
ns
BCLK output clock frequency:
master mode (1)
f(BCLK)
24.576
MHz
ns
BCLK high pulse duration: master
mode
tH(BCLK)
tL(BCLK)
td(FSYNC)
14
14
3
BCLK low pulse duration: master
mode
ns
BCLK to FSYNC delay: master
mode
50% of BCLK to 50% of FSYNC
18
ns
tr(BCLK)
tf(BCLK)
BCLK rise time: master mode
BCLK fall time: master mode
10% - 90% rise time
90% - 10% fall time
8
8
ns
ns
(1) The BCLK output clock frequency must be lower than 18.5 MHz (to meet the timing specifications), if the SDOUT data line is latched
on the opposite BCLK edge polarity than the edge used by the device to transmit SDOUT data.
Copyright © 2021 Texas Instruments Incorporated
8
Submit Document Feedback
Product Folder Links: PCM1820 PCM1821
PCM1820, PCM1821
SBASA61A – DECEMBER 2020 – REVISED JUNE 2021
www.ti.com
7.8 Typical Characteristics
at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, fIN = 1-kHz sinusoidal signal, fS = 48 kHz, 32-bit audio data, BCLK = 256 ×
fS, TDM slave mode, PLL on, DRE_LVL = –36 dB, channel gain = 0 dB, and linear phase decimation filter (unless otherwise
noted); all performance measurements are done with a 20-kHz, low-pass filter, and an A-weighted filter
-60
-60
Channel-1
Channel-2
Channel-1
Channel-2
-70
-70
-80
-80
-90
-90
-100
-110
-120
-130
-100
-110
-120
-130
-130
-115
-100
-85
-70
-55
-40
-25
-10
0
-130
-115
-100
-85
-70
-55
-40
-25
-10
0
Input Amplitude (dB)
Input Amplitude (dB)
TDH0D0+1
TDH0D0+2
Figure 7-1. PCM1820: THD+N vs Input Amplitude
With DRE Enabled
Figure 7-2. PCM1820: THD+N vs Input Amplitude
With DRE Disabled
-60
-60
Channel-1 : DRE enabled
Channel-2 : DRE enabled
Channel-1 : DRE enabled
Channel-2 : DRE enabled
-70
-80
-70
-80
-90
-90
-100
-110
-120
-130
-100
-110
-120
-130
20 30 4050 70 100
200 300 500
1000 2000
5000 10000 20000
20 30 4050 70 100
200 300 500
1000 2000
5000 10000 20000
Frequency (Hz)
Frequency (Hz)
DF0re0q3
D004
Figure 7-4. PCM1820: THD+N vs Input Frequency
With a –60-dBr Input
Figure 7-3. PCM1820: THD+N vs Input Frequency
With a –60-dBr Input
-60
20
Channel-1
Channel-2
Channel-1
Channel-2
10
-70
-80
0
-10
-20
-30
-90
-40
-50
-100
-110
-120
-130
-60
-70
-80
-90
-100
-110
-120
20 30 4050 70 100
200 300 500
1000 2000
5000 10000 20000
D005
20 30 50 70100 200300 500 1000 2000
5000 1000020000
100000
DF0re0q6
Frequency (Hz)
Frequency (Hz)
Figure 7-5. PCM1820: THD+N vs Input Frequency
With a –1-dBr Input
Figure 7-6. PCM1820: Frequency Response
With a –12-dBr Input
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
9
Product Folder Links: PCM1820 PCM1821
PCM1820, PCM1821
SBASA61A – DECEMBER 2020 – REVISED JUNE 2021
www.ti.com
7.8 Typical Characteristics (continued)
at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, fIN = 1-kHz sinusoidal signal, fS = 48 kHz, 32-bit audio data, BCLK = 256 ×
fS, TDM slave mode, PLL on, DRE_LVL = –36 dB, channel gain = 0 dB, and linear phase decimation filter (unless otherwise
noted); all performance measurements are done with a 20-kHz, low-pass filter, and an A-weighted filter
-60
0
-20
Channel-1
Channel-2
Channel-1 : DRE enabled
Channel-2 : DRE enabled
-70
-40
-80
-60
-80
-90
-100
-120
-140
-160
-180
-200
-100
-110
-120
-130
20 30 4050 70 100
200 300 500
1000 2000
5000 10000 20000
D007
20 30 4050 70 100
200 300 500
1000 2000
5000 10000 20000
D008
Frequency (Hz)
Frequency (Hz)
Figure 7-7. PCM1820: Power-Supply Rejection Ratio vs
Ripple Frequency With a 100-mVPP Amplitude
Figure 7-8. PCM1820: FFT With Idle Input and DRE Enabled
0
0
Channel-1 : DRE disabled
Channel-1 : DRE enabled
Channel-2 : DRE disabled
-20
Channel-2 : DRE enabled
-20
-40
-60
-40
-60
-80
-80
-100
-120
-140
-160
-180
-200
-100
-120
-140
-160
-180
-200
20 30 4050 70 100
200 300 500
1000 2000
5000 10000 20000
D009
20 30 4050 70 100
200 300 500
1000 2000
5000 10000 20000
D010
Frequency (Hz)
Frequency (Hz)
Figure 7-9. PCM1820: FFT With Idle Input and DRE Disabled
Figure 7-10. PCM1820: FFT With a –60-dBr Input and DRE
Enabled
0
0
Channel-1 : DRE disabled
Channel-1
Channel-2 : DRE disabled
-20
Channel-2
-20
-40
-60
-40
-60
-80
-80
-100
-120
-140
-160
-180
-200
-100
-120
-140
-160
-180
-200
20 30 4050 70 100
200 300 500
1000 2000
5000 10000 20000
D011
20 30 4050 70 100
200 300 500
1000 2000
5000 10000 20000
D012
Frequency (Hz)
Frequency (Hz)
Figure 7-11. PCM1820: FFT With a –60-dBr Input and DRE
Disabled
Figure 7-12. PCM1820: FFT With a –1-dBr Input
Copyright © 2021 Texas Instruments Incorporated
10
Submit Document Feedback
Product Folder Links: PCM1820 PCM1821
PCM1820, PCM1821
SBASA61A – DECEMBER 2020 – REVISED JUNE 2021
www.ti.com
7.8 Typical Characteristics (continued)
at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, fIN = 1-kHz sinusoidal signal, fS = 48 kHz, 32-bit audio data, BCLK = 256 ×
fS, TDM slave mode, PLL on, DRE_LVL = –36 dB, channel gain = 0 dB, and linear phase decimation filter (unless otherwise
noted); all performance measurements are done with a 20-kHz, low-pass filter, and an A-weighted filter
-60
-60
Channel-1
Channel-2
Channel-1
Channel-2
-70
-70
-80
-80
-90
-90
-100
-110
-120
-130
-100
-110
-120
-130
-130
-115
-100
-85
-70
-55
-40
-25
-10
0
20 30 4050 70 100
200 300 500
1000 2000
5000 10000 20000
D002
Input Amplitude (dB)
Frequency (Hz)
TDH0D0+1
Figure 7-13. PCM1821: THD+N vs Input Amplitude
Figure 7-14. PCM1821: THD+N vs Input Frequency
With a –60-dBr Input
-60
20
Channel-1
Channel-2
Channel-1
Channel-2
10
-70
-80
0
-10
-20
-30
-90
-40
-50
-100
-110
-120
-130
-60
-70
-80
-90
-100
-110
-120
20 30 4050 70 100
200 300 500
1000 2000
5000 10000 20000
20 30 50 70100 200300 500 1000 2000
5000 1000020000
100000
DF0re0q4
Frequency (Hz)
Frequency (Hz)
D003
Figure 7-15. PCM1821: THD+N vs Input Frequency
With a –1-dBr Input
Figure 7-16. PCM1821: Frequency Response
With a –12-dBr Input
-60
0
Channel-1
Channel-2
Channel-1
Channel-2
-20
-70
-80
-40
-60
-80
-90
-100
-120
-140
-160
-180
-200
-100
-110
-120
-130
20 30 4050 70 100
200 300 500
1000 2000
5000 10000 20000
D005
20 30 4050 70 100
200 300 500
1000 2000
5000 10000 20000
D006
Frequency (Hz)
Frequency (Hz)
Figure 7-17. PCM1821: Power-Supply Rejection Ratio vs
Ripple Frequency With a 100-mVPP Amplitude
Figure 7-18. PCM1821: FFT With Idle Input
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
11
Product Folder Links: PCM1820 PCM1821
PCM1820, PCM1821
SBASA61A – DECEMBER 2020 – REVISED JUNE 2021
www.ti.com
7.8 Typical Characteristics (continued)
at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, fIN = 1-kHz sinusoidal signal, fS = 48 kHz, 32-bit audio data, BCLK = 256 ×
fS, TDM slave mode, PLL on, DRE_LVL = –36 dB, channel gain = 0 dB, and linear phase decimation filter (unless otherwise
noted); all performance measurements are done with a 20-kHz, low-pass filter, and an A-weighted filter
0
-20
0
-20
Channel-1
Channel-2
Channel-1
Channel-2
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-180
-200
-100
-120
-140
-160
-180
-200
20 30 4050 70 100
200 300 500
1000 2000
5000 10000 20000
D007
20 30 4050 70 100
200 300 500
1000 2000
5000 10000 20000
D008
Frequency (Hz)
Frequency (Hz)
Figure 7-19. PCM1821: FFT With a –60-dBr Input
Figure 7-20. PCM1821: FFT With a –1-dBr Input
Copyright © 2021 Texas Instruments Incorporated
12
Submit Document Feedback
Product Folder Links: PCM1820 PCM1821
PCM1820, PCM1821
SBASA61A – DECEMBER 2020 – REVISED JUNE 2021
www.ti.com
8 Detailed Description
8.1 Overview
The PCM182x is a high-performance, low-power, stereo-channel, audio analog-to-digital converter (ADC) with
flexible audio interface control options. This device is intended for applications in voice-activated systems,
AV receivers, tv and blu-ray players, professional microphones, audio conferencing, portable computing,
communication, and entertainment applications. The high dynamic range of the device enables far-field audio
recording with high fidelity. This device integrates a host of features that reduces cost, board space, and power
consumption in space-constrained, battery-powered, consumer, home, and industrial applications. The device
features are controlled through hardware by pulling pins high or low with resistors or a controller general-purpose
inut/output (GPIO). The PCM182x also supports a power-down and reset function by means of halting the
system clock.
The PCM182x consists of the following blocks and features:
•
•
•
•
•
•
•
•
•
•
•
•
•
Stereo-channel, multibit, high-performance delta-sigma (ΔΣ) ADC
Differential audio inputs with a 2-VRMS full-scale signal
Hardware pin control operation to select the device features
Audio bus serial interface master or slave select option
Audio bus serial interface format select option
Slave mode supports the audio bus serial interface up to 192 kHz sampling
Slave mode supports a dynamic range enhancer (DRE) with 123-dB dynamic range for the PCM1820
Slave mode supports decimation filters with linear-phase or low-latency filter selection
Master mode operation supported using a system clock of 256 × fS or 512 × fS
Power-down function by means of halting the audio clocks
Integrated high-pass filter (HPF) that removes the DC component of the input signal
Integrated low-jitter phase-locked loop (PLL) supporting a wide range of system clocks
Integrated digital and analog voltage regulators to support single-supply, 3.3-V operation
8.2 Functional Block Diagram
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
13
Product Folder Links: PCM1820 PCM1821
PCM1820, PCM1821
SBASA61A – DECEMBER 2020 – REVISED JUNE 2021
www.ti.com
8.3 Feature Description
8.3.1 Hardware Control
The device supports simple hardware-pin-controlled options to select a specific mode of operation and audio
interface for a given system. The MSZ, MD0, MD1, and FMT0 pins allow the device to be controlled by either
pullup or pulldown resistors.
8.3.2 Audio Serial Interfaces
Digital audio data flows between the host processor and the PCM182x on the digital audio serial interface (ASI),
or audio bus. This highly flexible ASI bus includes a TDM mode for multichannel operation, support for the I2S,
and the pin-selectable master-slave configurability for bus clock lines.
The device supports an audio bus master or slave mode of operation using the hardware pin MSZ. In slave
mode, FSYNC and BCLK work as input pins whereas in master mode, FSYNC and BCLK work as output pins
generated by the device. Table 8-1 shows the master and slave mode selection using the MSZ pin.
Table 8-1. Master and Slave Mode Selection
MSZ
Low
High
MASTER AND SLAVE SELECTION
Slave mode of operation
Master ode of operation
The bus protocol TDM or I2S format can be selected by using the FMT0 pin. As shown in Table 8-2, these
modes are all most significant byte (MSB)-first, pulse code modulation (PCM) data format, with an output
channel data word-length of 32 bits.
Table 8-2. Audio Serial Interface Format
FMT0
Low
AUDIO SERIAL INTERFACE FORMAT
2-channel output with inter IC sound (I2S) mode
2-channel output with time division multiplexing (TDM) mode
High
8.3.2.1 Time Division Multiplexed Audio (TDM) Interface
In TDM mode, also known as DSP mode, the rising edge of FSYNC starts the data transfer with the slot 0 data
first. Immediately after the slot 0 data transmission, the remaining slot data are transmitted in order. FSYNC and
each data bit (except the MSB of slot 0 when TX_OFFSET equals 0) is transmitted on the rising edge of BCLK.
Figure 8-1 and Figure 8-2 show the protocol timing for TDM operation with various configurations.
FSYNC
BCLK
SDOUT
N-1 N-2
2
1
0
N-1 N-2 N-3
2
1
0
N-1 N-2
2
1
0
Ch2
(Word Length : 32)
Ch1
(Word Length : 32)
Ch1
(Word Length : 32)
(n+1)th Sample
nth Sample
Figure 8-1. TDM Mode Protocol Timing (FMT0 = HIGH) In Slave Mode
FSYNC
BCLK
SDOUT
0
N-1 N-2 N-3
2
1
0
N-1 N-2 N-3
N-1 N-2 N-3
2
1
0
N-1 N-2 N-3
1
0
1
0
N-1
Ch2
(Word Length : 32)
Ch1
(Word Length : 32)
Ch2
(Word Length : 32)
(n+1)th Sample (64 BCLK Cycles)
Ch1
(Word Length : 32)
nth Sample (64 BCLK Cycles)
Figure 8-2. TDM Mode Protocol Timing (FMT0 = HIGH) In Master Mode
Copyright © 2021 Texas Instruments Incorporated
14
Submit Document Feedback
Product Folder Links: PCM1820 PCM1821
PCM1820, PCM1821
SBASA61A – DECEMBER 2020 – REVISED JUNE 2021
www.ti.com
For proper operation of the audio bus in TDM mode, the number of bit clocks per frame must be greater than
or equal to the number of active output channels times the 32-bits word length of the output channel data. The
device transmits a zero data value on SDOUT for the extra unused bit clock cycles. The device supports FSYNC
as a pulse with a 1-cycle-wide bit clock, but also supports multiples as well.
8.3.2.2 Inter IC Sound (I2S) Interface
The standard I2S protocol is defined for only two channels: left and right. In I2S mode, the MSB of the left slot 0
is transmitted on the falling edge of BCLK in the second cycle after the falling edge of FSYNC. The MSB of the
right slot 0 is transmitted on the falling edge of BCLK in the second cycle after the rising edge of FSYNC. Each
subsequent data bit is transmitted on the falling edge of BCLK. In master mode, FSYNC is transmitted on the
rising edge of BCLK. Figure 8-3 and Figure 8-4 show the protocol timing for I2S operation in slave and master
mode of operation.
FSYNC
BCLK
SDOUT
N-1 N-2
1
0
1
0
N-1 N-2
1
0
N-1 N-2
Left (Ch1)
Slot-0
(Word Length : 32)
(n+1)th Sample
Left (Ch1)
Slot-0
(Word Length : 32)
nth Sample
Right (Ch2)
Slot-0
(Word Length : 32)
Figure 8-3. I2S Mode Protocol Timing (FMT0 = LOW) in Slave Mode
FSYNC
BCLK
SDOUT
1
0
N-1 N-2
1
0
N-1 N-2
1
0
N-1 N-2
1
0
N-1 N-2
1
0
Right (Ch2)
Slot-0
(Word Length : 32)
Right (Ch2)
Slot-0
(Word Length : 32)
Left (Ch1)
Slot-0
(Word Length : 32)
Left (Ch1)
Slot-0
(Word Length : 32)
nth Sample (64 BCLK Cycles)
(n+1)th Sample (64 BCLK Cycles)
Figure 8-4. I2S Protocol Timing (FMT0 = LOW) In Master Mode
For proper operation of the audio bus in I2S mode, the number of bit clocks per frame must be greater than or
equal to the number of active output channels (including left and right slots) times the 32-bits word length of the
output channel data. The device FSYNC low pulse must be a number of BCLK cycles wide that is greater than
or equal to the number of active left slots times the 32-bits data word length. Similarly, the FSYNC high pulse
must be a number of BCLK cycles wide that is greater than or equal to the number of active right slots times the
32-bits data word length. The device transmit zero data value on SDOUT for the extra unused bit clock cycles.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
15
Product Folder Links: PCM1820 PCM1821
PCM1820, PCM1821
SBASA61A – DECEMBER 2020 – REVISED JUNE 2021
www.ti.com
8.3.3 Phase-Locked Loop (PLL) and Clock Generation
The device uses an integrated, low-jitter, phase-locked loop (PLL) to generate internal clocks required for the
ADC modulator and digital filter engine, as well as other control blocks.
In slave mode of operation, the device supports the various output data sample rates (of the FSYNC signal
frequency) and the BCLK to FSYNC ratio to configure all clock dividers, including the PLL configuration,
internally without host programming. Table 8-3 and Table 8-4 list the supported FSYNC and BCLK frequencies.
Table 8-3. Supported FSYNC (Multiples or Submultiples of 48 kHz) and BCLK Frequencies
BCLK (MHz)
BCLK TO
FSYNC RATIO
FSYNC
(8 kHz)
FSYNC
(16 kHz)
FSYNC
(24 kHz)
FSYNC
(32 kHz)
FSYNC
(48 kHz)
FSYNC
(96 kHz)
FSYNC
(192 kHz)
16
24
Reserved
Reserved
0.256
0.256
0.384
0.512
0.768
1.024
1.536
2.048
3.072
4.096
6.144
8.192
0.384
0.576
0.768
1.152
1.536
2.304
3.072
4.608
6.144
9.216
12.288
0.512
0.768
1.024
1.536
2.048
3.072
4.096
6.144
8.192
12.288
16.384
0.768
1.152
1.536
2.304
3.072
4.608
6.144
9.216
12.288
18.432
24.576
1.536
2.304
3.072
4.608
32
3.072
6.144
48
0.384
4.608
9.216
64
0.512
6.144
12.288
96
0.768
9.216
18.432
128
192
256
384
512
1.024
12.288
18.432
24.576
Reserved
Reserved
24.576
1.536
Reserved
Reserved
Reserved
Reserved
2.048
3.072
4.096
Table 8-4. Supported FSYNC (Multiples or Submultiples of 44.1 kHz) and BCLK Frequencies
BCLK (MHz)
BCLK TO
FSYNC
FSYNC
FSYNC
FSYNC
FSYNC
FSYNC
FSYNC
FSYNC RATIO
(7.35 kHz)
(14.7 kHz)
(22.05 kHz)
(29.4 kHz)
(44.1 kHz)
(88.2 kHz)
(176.4 kHz)
16
24
Reserved
Reserved
Reserved
0.3528
Reserved
0.3528
0.4704
0.7056
0.9408
1.4112
1.8816
2.8224
3.7632
5.6448
7.5264
0.3528
0.5292
0.7056
1.0584
1.4112
2.1168
2.8224
4.2336
5.6448
8.4672
11.2896
0.4704
0.7056
0.9408
1.4112
1.8816
2.8224
3.7632
5.6448
7.5264
11.2896
15.0528
0.7056
1.0584
1.4112
2.1168
2.8224
4.2336
5.6448
8.4672
11.2896
16.9344
22.5792
1.4112
2.1168
2.8224
4.2336
32
2.8224
5.6448
48
4.2336
8.4672
64
0.4704
5.6448
11.2896
16.9344
22.5792
Reserved
Reserved
Reserved
Reserved
96
0.7056
8.4672
128
192
256
384
512
0.9408
11.2896
16.9344
22.5792
Reserved
Reserved
1.4112
1.8816
2.8224
3.7632
In the master mode of operation, the device uses the MD1 pin (as the system clock, MCLK) as the reference
input clock source with a supported system clock frequency option of either 256 × fS or 512 × fS as configured
using the MD0 pin. Master mode supports fS rates of 44.1 kHz and 48 kHz. Table 8-5 shows the system clock
selection for the master mode using the MD0 pin.
Table 8-5. System Clock Selection for the Master Mode
MD0
LOW
HIGH
SYSTEM CLOCK SELECTION (Valid for Master Mode Only)
System clock with frequency 256 × fS connected to the MD1 pin as MCLK
System clock with frequency 512 × fS connected to the MD1 pin as MCLK
See Table 8-7 and Table 8-20 for the MD0 and MD1 pin function in the slave mode of operation.
Copyright © 2021 Texas Instruments Incorporated
16
Submit Document Feedback
Product Folder Links: PCM1820 PCM1821
PCM1820, PCM1821
SBASA61A – DECEMBER 2020 – REVISED JUNE 2021
www.ti.com
8.3.4 Input Channel Configurations
The device consists of two pairs of analog input pins (INxP and INxM) as differential inputs for the recording
channel. The device supports simultaneous recording of up to two channels using the high-performance stereo
ADC. The input source for the analog pins can be from electret condenser analog microphones, micro electrical-
mechanical system (MEMS) analog microphones, or line-in (auxiliary) inputs from the system board.
The voice or audio signal inputs must be capacitively coupled (AC-coupled) to the device and, for best distortion
performance, use the low-voltage coefficient capacitors for AC coupling. The typical input impedance for the
PCM1820 is 2.5 kΩ for the INxP or INxM pins and 10 kΩ for the PCM1821. The value of the coupling capacitor
in AC-coupled mode must be chosen so that the high-pass filter formed by the coupling capacitor and the input
impedance do not affect the signal content. Before proper recording can begin, this coupling capacitor must be
charged up to the common-mode voltage at power-up. To enable quick charging, the device has a quick charge
scheme to speed up the charging of the coupling capacitor at power-up. The default value of the quick-charge
timing is set for a coupling capacitor up to 1 µF.
8.3.5 Reference Voltage
All audio data converters require a DC reference voltage. The PCM182x achieves low-noise performance by
internally generating a low-noise reference voltage. This reference voltage is generated using a band-gap
circuit with high PSRR performance. This audio converter reference voltage must be filtered externally using a
minimum 1-µF capacitor connected from the VREF pin to analog ground (AVSS). The value of this reference
voltage, VREF, is set to 2.75 V, which in turn supports a 2-VRMS differential full-scale input to the device. The
required minimum AVDD voltage for this VREF voltage is 3 V. Do not connect any external load to a VREF pin.
8.3.6 Signal-Chain Processing
The PCM182x signal chain is comprised of very-low-noise, high-performance, and low-power analog blocks and
highly flexible and programmable digital processing blocks. The high performance and flexibility combined with a
compact package makes the PCM182x optimized for a variety of end-equipments and applications that require
multichannel audio capture. Figure 8-5 shows a conceptual block diagram for the PCM1820 that highlights the
various building blocks used in the signal chain, and how the blocks interact in the signal chain. The PCM1821
does not support DRE.
Output
Channel
Data to
INP
INM
Configurable
Decimation
Filters
DRE
Amplifier
HPF
DRE
ADC
Audio Bus
Figure 8-5. Signal-Chain Processing Flowchart
The front-end dynamic range enhancer (DRE) gain amplifier in the PCM1820 is very low noise, with a 123-dB
dynamic range performance. Along with a low-noise and low-distortion, multibit, delta-sigma ADC, the front-end
DRE gain amplifier enables the PCM1820 to record a far-field audio signal with very high fidelity, both in quiet
and loud environments. Moreover, the ADC architecture has inherent antialias filtering with a high rejection of
out-of-band frequency noise around multiple modulator frequency components. Therefore, the device prevents
noise from aliasing into the audio band during ADC sampling. Further on in the signal chain, an integrated,
high-performance multistage digital decimation filter sharply cuts off any out-of-band frequency noise with high
stop-band attenuation.
The device supports an input signal bandwidth up to 80 kHz, which allows the high-frequency non-audio signal
to be recorded by using a 176.4-kHz (or higher) sample rate.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
17
Product Folder Links: PCM1820 PCM1821
PCM1820, PCM1821
SBASA61A – DECEMBER 2020 – REVISED JUNE 2021
www.ti.com
8.3.6.1 Digital High-Pass Filter
To remove the DC offset component and attenuate the undesired low-frequency noise content in the record data,
the device supports a fixed high-pass filter (HPF) with –3-dB cut-off frequency of 0.00025 × fS. The HPF is not a
channel-independent filter but is globally applicable for all the ADC channels. This HPF is constructed using the
first-order infinite impulse response (IIR) filter, and is efficient enough to filter out possible DC components of the
signal. Table 8-6 shows the fixed –3-dB cutoff frequency value. Figure 8-6 shows a frequency response plot for
the HPF filter.
Table 8-6. HPF Cutoff Frequency Value
-3-dB CUTTOFF FREQUENCY AT 16 kHz
SAMPLE RATE
-3-dB CUTTOFF FREQUENCY AT 48 kHz
SAMPLE RATE
–3-dB CUTOFF FREQUENCY VALUE
0.00025 × fS
4 Hz
12 Hz
3
0
-3
-6
-9
-12
-15
-18
-21
-24
HPF -3 dB Cutoff = 0.00025 ì fS
5E-5
0.0001
0.0005
0.001
Normalized Frequency (1/fS)
0.005
0.01
0.05
DPlo
Figure 8-6. HPF Filter Frequency Response Plot
Copyright © 2021 Texas Instruments Incorporated
18
Submit Document Feedback
Product Folder Links: PCM1820 PCM1821
PCM1820, PCM1821
SBASA61A – DECEMBER 2020 – REVISED JUNE 2021
www.ti.com
8.3.6.2 Configurable Digital Decimation Filters
The device record channel includes a high dynamic range, built-in digital decimation filter to process the
oversampled data from the multibit delta-sigma (ΔΣ) modulator to generate digital data at the same Nyquist
sampling rate as the FSYNC rate. The decimation filter can be chosen from two different types only in slave
mode, depending on the required frequency response, group delay, and phase linearity requirements for the
target application. The selection of the decimation filter option can be done by the MD0 pin. Table 8-7 shows the
decimation filter mode selection for the record channel.
Table 8-7. Decimation Filter Mode Selection for the Record Channel
MD0
DECIMATION FILTER MODE SELECTION (Supported Only in Slave Mode)
LOW
Linear phase filters are used for the decimation in slave mode. For master mode, the device
always use linear phase filters for the decimation.
HIGH
Low latency filters are used for the decimation in slave mode. For master mode, the device
always use linear phase filters for the decimation.
8.3.6.2.1 Linear Phase Filters
The linear phase decimation filters are the default filters set by the device and can be used for all applications
that require a perfect linear phase with zero-phase deviation within the pass-band specification of the filter.
The filter performance specifications and various plots for all supported output sampling rates are listed in this
section.
8.3.6.2.1.1 Sampling Rate: 8 kHz or 7.35 kHz
Figure 8-7 and Figure 8-8 respectively show the magnitude response and the pass-band ripple for a decimation
filter with a sampling rate of 8 kHz or 7.35 kHz. Table 8-8 lists the specifications for a decimation filter with an
8-kHz or 7.35-kHz sampling rate.
10
0
0.5
0.4
0.3
0.2
0.1
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
D001
D001
Figure 8-7. Linear Phase Decimation Filter
Magnitude Response
Figure 8-8. Linear Phase Decimation Filter Pass-
Band Ripple
Table 8-8. Linear Phase Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Pass-band ripple
Frequency range is 0 to 0.454 × fS
–0.05
0.05
dB
Frequency range is 0.58 × fS to 4 × fS
Frequency range is 4 × fS onwards
Frequency range is 0 to 0.454 × fS
72.7
81.2
Stop-band attenuation
Group delay or latency
dB
17.1
1/fS
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
19
Product Folder Links: PCM1820 PCM1821
PCM1820, PCM1821
SBASA61A – DECEMBER 2020 – REVISED JUNE 2021
www.ti.com
8.3.6.2.1.2 Sampling Rate: 16 kHz or 14.7 kHz
Figure 8-9 and Figure 8-10 respectively show the magnitude response and the pass-band ripple for a decimation
filter with a sampling rate of 16 kHz or 14.7 kHz. Table 8-9 lists the specifications for a decimation filter with an
16-kHz or 14.7-kHz sampling rate.
10
0
0.5
0.4
0.3
0.2
0.1
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
D001
D001
Figure 8-9. Linear Phase Decimation Filter
Magnitude Response
Figure 8-10. Linear Phase Decimation Filter Pass-
Band Ripple
Table 8-9. Linear Phase Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Pass-band ripple
Frequency range is 0 to 0.454 × fS
–0.05
0.05
dB
Frequency range is 0.58 × fS to 4 × fS
Frequency range is 4 × fS onwards
Frequency range is 0 to 0.454 × fS
73.3
95.0
Stop-band attenuation
Group delay or latency
dB
15.7
1/fS
8.3.6.2.1.3 Sampling Rate: 24 kHz or 22.05 kHz
Figure 8-11 and Figure 8-12 respectively show the magnitude response and the pass-band ripple for a
decimation filter with a sampling rate of 24 kHz or 22.05 kHz. Table 8-10 lists the specifications for a decimation
filter with an 24-kHz or 22.05-kHz sampling rate.
10
0
0.5
0.4
0.3
0.2
0.1
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
D001
D001
Figure 8-11. Linear Phase Decimation Filter
Magnitude Response
Figure 8-12. Linear Phase Decimation Filter Pass-
Band Ripple
Table 8-10. Linear Phase Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Pass-band ripple
Frequency range is 0 to 0.454 × fS
–0.05
0.05
dB
Frequency range is 0.58 × fS to 4 × fS
Frequency range is 4 × fS onwards
Frequency range is 0 to 0.454 × fS
73.0
96.4
Stop-band attenuation
Group delay or latency
dB
16.6
1/fS
Copyright © 2021 Texas Instruments Incorporated
20
Submit Document Feedback
Product Folder Links: PCM1820 PCM1821
PCM1820, PCM1821
SBASA61A – DECEMBER 2020 – REVISED JUNE 2021
www.ti.com
8.3.6.2.1.4 Sampling Rate: 32 kHz or 29.4 kHz
Figure 8-13 and Figure 8-14 respectively show the magnitude response and the pass-band ripple for a
decimation filter with a sampling rate of 32 kHz or 29.4 kHz. Table 8-11 lists the specifications for a decimation
filter with an 32-kHz or 29.4-kHz sampling rate.
10
0
0.5
0.4
0.3
0.2
0.1
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
D001
D001
Figure 8-13. Linear Phase Decimation Filter
Magnitude Response
Figure 8-14. Linear Phase Decimation Filter Pass-
Band Ripple
Table 8-11. Linear Phase Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Pass-band ripple
Frequency range is 0 to 0.454 × fS
–0.05
0.05
dB
Frequency range is 0.58 × fS to 4 × fS
Frequency range is 4 × fS onwards
Frequency range is 0 to 0.454 × fS
73.7
Stop-band attenuation
Group delay or latency
dB
107.2
16.9
1/fS
8.3.6.2.1.5 Sampling Rate: 48 kHz or 44.1 kHz
Figure 8-15 and Figure 8-16 respectively show the magnitude response and the pass-band ripple for a
decimation filter with a sampling rate of 48 kHz or 44.1 kHz. Table 8-12 lists the specifications for a decimation
filter with an 48-kHz or 44.1-kHz sampling rate.
10
0
0.5
0.4
0.3
0.2
0.1
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
D001
D001
Figure 8-15. Linear Phase Decimation Filter
Magnitude Response
Figure 8-16. Linear Phase Decimation Filter Pass-
Band Ripple
Table 8-12. Linear Phase Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Pass-band ripple
Frequency range is 0 to 0.454 × fS
–0.05
0.05
dB
Frequency range is 0.58 × fS to 4 × fS
Frequency range is 4 × fS onwards
Frequency range is 0 to 0.454 × fS
73.8
98.1
Stop-band attenuation
Group delay or latency
dB
17.1
1/fS
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
21
Product Folder Links: PCM1820 PCM1821
PCM1820, PCM1821
SBASA61A – DECEMBER 2020 – REVISED JUNE 2021
www.ti.com
8.3.6.2.1.6 Sampling Rate: 96 kHz or 88.2 kHz
Figure 8-17 and Figure 8-18 respectively show the magnitude response and the pass-band ripple for a
decimation filter with a sampling rate of 96 kHz or 88.2 kHz. Table 8-13 lists the specifications for a decimation
filter with an 96-kHz or 88.2-kHz sampling rate.
10
0
0.5
0.4
0.3
0.2
0.1
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
D001
D001
Figure 8-17. Linear Phase Decimation Filter
Magnitude Response
Figure 8-18. Linear Phase Decimation Filter Pass-
Band Ripple
Table 8-13. Linear Phase Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Pass-band ripple
Frequency range is 0 to 0.454 × fS
–0.05
0.05
dB
Frequency range is 0.58 × fS to 4 × fS
Frequency range is 4 × fS onwards
Frequency range is 0 to 0.454 × fS
73.6
97.9
Stop-band attenuation
Group delay or latency
dB
17.1
1/fS
8.3.6.2.1.7 Sampling Rate: 192 kHz or 176.4 kHz
Figure 8-19 and Figure 8-20 respectively show the magnitude response and the pass-band ripple for a
decimation filter with a sampling rate of 192 kHz or 176.4 kHz. Table 8-14 lists the specifications for a decimation
filter with an 192-kHz or 176.4-kHz sampling rate.
10
0
0.5
0.4
0.3
0.2
0.1
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
0
0.05
0.1
0.15
0.2
0.25
Normalized Frequency (1/fS)
0.3
0.35
0.4
D001
D001
Figure 8-19. Linear Phase Decimation Filter
Magnitude Response
Figure 8-20. Linear Phase Decimation Filter Pass-
Band Ripple
Table 8-14. Linear Phase Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Pass-band ripple
Frequency range is 0 to 0.3 × fS
–0.05
0.05
dB
Frequency range is 0.473 × fS to 4 × fS
Frequency range is 4 × fS onwards
Frequency range is 0 to 0.3 × fS
70.0
Stop-band attenuation
Group delay or latency
dB
111.0
11.9
1/fS
Copyright © 2021 Texas Instruments Incorporated
22
Submit Document Feedback
Product Folder Links: PCM1820 PCM1821
PCM1820, PCM1821
SBASA61A – DECEMBER 2020 – REVISED JUNE 2021
www.ti.com
8.3.6.2.2 Low-Latency Filters
For applications where low latency with minimal phase deviation (within the audio band) is critical, the low-
latency decimation filters on the PCM182x can be used. The device supports these filters with a group delay of
approximately seven samples with an almost linear phase response within the 0.365 × fS frequency band. This
section provides the filter performance specifications and various plots for all supported output sampling rates for
the low-latency filters.
8.3.6.2.2.1 Sampling Rate: 16 kHz or 14.7 kHz
Figure 8-21 shows the magnitude response and Figure 8-22 shows the pass-band ripple and phase deviation for
a decimation filter with a sampling rate of 16 kHz or 14.7 kHz. Table 8-15 lists the specifications for a decimation
filter with a 16-kHz or 14.7-kHz sampling rate.
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
0.3
0.2
0.1
0
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
Pass-Band Ripple
Phase Deviation
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
D002
D002
Figure 8-22. Low-Latency Decimation Filter Pass-
Band Ripple and Phase Deviation
Figure 8-21. Low-Latency Decimation Filter
Magnitude Response
Table 8-15. Low-Latency Decimation Filter Specifications
PARAMETER
Pass-band ripple
TEST CONDITIONS
MIN
TYP
MAX
UNIT
dB
Frequency range is 0 to 0.451 × fS
–0.05
0.05
Stop-band attenuation
Group delay or latency
Group delay deviation
Phase deviation
Frequency range is 0.61 × fS onwards
Frequency range is 0 to 0.363 × fS
Frequency range is 0 to 0.363 × fS
Frequency range is 0 to 0.363 × fS
87.3
dB
7.6
1/fS
–0.022
–0.21
0.022
0.25
1/fS
Degrees
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
23
Product Folder Links: PCM1820 PCM1821
PCM1820, PCM1821
SBASA61A – DECEMBER 2020 – REVISED JUNE 2021
www.ti.com
8.3.6.2.2.2 Sampling Rate: 24 kHz or 22.05 kHz
Figure 8-23 shows the magnitude response and Figure 8-24 shows the pass-band ripple and phase deviation
for a decimation filter with a sampling rate of 24 kHz or 22.05 kHz. Table 8-16 lists the specifications for a
decimation filter with a 24-kHz or 22.05-kHz sampling rate.
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
0.3
0.2
0.1
0
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
Pass-Band Ripple
Phase Deviation
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
D002
D002
Figure 8-24. Low-Latency Decimation Filter Pass-
Band Ripple and Phase Deviation
Figure 8-23. Low-Latency Decimation Filter
Magnitude Response
Table 8-16. Low-Latency Decimation Filter Specifications
PARAMETER
Pass-band ripple
TEST CONDITIONS
MIN
TYP
MAX
UNIT
dB
Frequency range is 0 to 0.459 × fS
–0.01
0.01
Stop-band attenuation
Group delay or latency
Group delay deviation
Phase deviation
Frequency range is 0.6 × fS onwards
Frequency range is 0 to 0.365 × fS
Frequency range is 0 to 0.365 × fS
Frequency range is 0 to 0.365 × fS
87.2
dB
7.5
1/fS
–0.026
–0.26
0.026
0.30
1/fS
Degrees
8.3.6.2.2.3 Sampling Rate: 32 kHz or 29.4 kHz
Figure 8-25 shows the magnitude response and Figure 8-26 shows the pass-band ripple and phase deviation for
a decimation filter with a sampling rate of 32 kHz or 29.4 kHz. Table 8-17 lists the specifications for a decimation
filter with a 32-kHz or 29.4-kHz sampling rate.
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
0.3
0.2
0.1
0
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
Pass-Band Ripple
Phase Deviation
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
D002
D002
Figure 8-26. Low-Latency Decimation Filter Pass-
Band Ripple and Phase Deviation
Figure 8-25. Low-Latency Decimation Filter
Magnitude Response
Copyright © 2021 Texas Instruments Incorporated
24
Submit Document Feedback
Product Folder Links: PCM1820 PCM1821
PCM1820, PCM1821
SBASA61A – DECEMBER 2020 – REVISED JUNE 2021
www.ti.com
Table 8-17. Low-Latency Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
MIN
–0.04
88.3
TYP
MAX
UNIT
dB
Pass-band ripple
Frequency range is 0 to 0.457 × fS
Frequency range is 0.6 × fS onwards
Frequency range is 0 to 0.368 × fS
Frequency range is 0 to 0.368 × fS
Frequency range is 0 to 0.368 × fS
0.04
Stop-band attenuation
Group delay or latency
Group delay deviation
Phase deviation
dB
8.7
1/fS
–0.026
–0.26
0.026
0.31
1/fS
Degrees
8.3.6.2.2.4 Sampling Rate: 48 kHz or 44.1 kHz
Figure 8-27 shows the magnitude response and Figure 8-28 shows the pass-band ripple and phase deviation for
a decimation filter with a sampling rate of 48 kHz or 44.1 kHz. Table 8-18 lists the specifications for a decimation
filter with a 48-kHz or 44.1-kHz sampling rate.
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
0.3
0.2
0.1
0
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
Pass-Band Ripple
Phase Deviation
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
D002
D002
Figure 8-28. Low-Latency Decimation Filter Pass-
Band Ripple and Phase Deviation
Figure 8-27. Low-Latency Decimation Filter
Magnitude Response
Table 8-18. Low-Latency Decimation Filter Specifications
PARAMETER
Pass-band ripple
TEST CONDITIONS
MIN
TYP
MAX
UNIT
dB
Frequency range is 0 to 0.452 × fS
–0.015
0.015
Stop-band attenuation
Group delay or latency
Group delay deviation
Phase deviation
Frequency range is 0.6 × fS onwards
Frequency range is 0 to 0.365 × fS
Frequency range is 0 to 0.365 × fS
Frequency range is 0 to 0.365 × fS
86.4
dB
7.7
1/fS
–0.027
–0.25
0.027
0.30
1/fS
Degrees
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
25
Product Folder Links: PCM1820 PCM1821
PCM1820, PCM1821
SBASA61A – DECEMBER 2020 – REVISED JUNE 2021
www.ti.com
8.3.6.2.2.5 Sampling Rate: 96 kHz or 88.2 kHz
Figure 8-29 shows the magnitude response and Figure 8-30 shows the pass-band ripple and phase deviation for
a decimation filter with a sampling rate of 96 kHz or 88.2 kHz. Table 8-19 lists the specifications for a decimation
filter with a 96-kHz or 88.2-kHz sampling rate.
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
0.3
0.2
0.1
0
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
Pass-Band Ripple
Phase Deviation
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
D002
D002
Figure 8-30. Low-Latency Decimation Filter Pass-
Band Ripple and Phase Deviation
Figure 8-29. Low-Latency Decimation Filter
Magnitude Response
Table 8-19. Low-Latency Decimation Filter Specifications
PARAMETER
Pass-band ripple
TEST CONDITIONS
MIN
TYP
MAX
UNIT
dB
Frequency range is 0 to 0.466 × fS
–0.04
0.04
Stop-band attenuation
Group delay or latency
Group delay deviation
Phase deviation
Frequency range is 0.6 × fS onwards
Frequency range is 0 to 0.365 × fS
Frequency range is 0 to 0.365 × fS
Frequency range is 0 to 0.365 × fS
86.3
dB
7.7
1/fS
–0.027
–0.26
0.027
0.30
1/fS
Degrees
Copyright © 2021 Texas Instruments Incorporated
26
Submit Document Feedback
Product Folder Links: PCM1820 PCM1821
PCM1820, PCM1821
SBASA61A – DECEMBER 2020 – REVISED JUNE 2021
www.ti.com
8.3.7 Dynamic Range Enhancer (DRE)
The device integrates an ultra-low noise front-end DRE gain amplifier with 123-dB dynamic range performance
with a low-noise, low-distortion, multibit delta-sigma (ΔΣ) ADC with a 113-dB dynamic range. The dynamic range
enhancer (DRE) is a digitally assisted algorithm to boost the overall channel performance. The DRE monitors
the incoming signal amplitude and accordingly adjusts the internal DRE amplifier gain automatically. The DRE
achieves a complete-channel dynamic range as high as 123 dB. At a system level, the DRE scheme enables
far-field, high-fidelity recording of audio signals in very quiet environments and low-distortion recording in loud
environments.
The DRE can be enabled only in slave mode by driving the MD1 pin high. Table 8-20 shows the DRE selection
for the record channel. Additionally, this feature is only supported in the PCM1820 and not in the PCM1821.
Table 8-20. DRE Selection for the Record Channel
MD1
Low
High
DRE SELECTION (Supported Only in Slave Mode)
The DRE is disabled in slave mode. For master mode, the DRE is always disabled.
The DRE is enabled with DRE_LVL = –36 dB and DRE_MAXGAIN = 24 dB in slave mode.
For master mode, the DRE is always disabled.
This algorithm is implemented with very low latency and all signal chain blocks are designed to minimize
any audible artifacts that may occur resulting from dynamic gain modulation. The target signal threshold level
(DRE_LVL), at which the DRE is triggered, is fixed to the –36-dB input signal level. The DRE gain range can be
dynamically modulated by using DRE_MAXGAIN, which is fixed to 24 dB to maximize the benefit of the DRE in
real-world applications and to minimize any audible artifacts.
Enabling the DRE for processing increases the power consumption of the device because of increased
signal processing. Therefore, disable the DRE for low-power critical applications. Furthermore, the DRE is not
supported for output sample rates greater than 96 kHz.
8.4 Device Functional Modes
8.4.1 Active Mode
The device wakes up in active mode when AVDD and IOVDD are available. Configure all hardware control pins
(MSZ, MD0, MD1, and FMT0) for the device desired mode of operation before enabling clocks for the device.
In active mode, when the audio clocks are available, the device automatically powers up all ADC channels and
starts transmitting data over the audio serial interface. If the clocks are stopped, then the device auto powers
down the ADC channels.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
27
Product Folder Links: PCM1820 PCM1821
PCM1820, PCM1821
SBASA61A – DECEMBER 2020 – REVISED JUNE 2021
www.ti.com
9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The PCM182x is a multichannel, high-performance audio analog-to-digital converter (ADC) that supports output
sample rates of up to 192 kHz. The device supports up to two analog microphones for simultaneous recording
applications.
The PCM182x configuration is supported using various hardware pin control options. The device supports a
highly flexible, audio serial interface (TDM and I2S) to transmit audio data seamlessly in the system across
devices.
9.2 Typical Application
Figure 9-1 shows a typical configuration of the PCM182x for an application using stereo analog microelectrical-
mechanical system (MEMS) microphones for simultaneous recording operation with a time-division multiplexing
(TDM) audio data slave interface. For best distortion performance, use input AC-coupling capacitors with a
low-voltage coefficient.
3.3 V
(3.0 V to
3.6 V)
1 ꢀF
10 ꢀF
GND
GND
GND
10 ꢀF
VDD
OUTP
IN1P
IN1M
DREG
AMIC1
OUTM
VSS
0.1 ꢀF
GND
GND
VDD
OUTP
IN2P
IN2M
PCM1820, PCM1821
AMIC2
OUTM
VSS
3.3 V (3.0 V to
OR
1.8 V (1.65 V to
10 ꢀF
0.1 ꢀF
IOVDD
GND
GND
Thermal Pad
(VSS)
GND
LOW or HIGH Pin
Selector
Host
Processor
Figure 9-1. Two-Channel Analog Microphone Recording Diagram for 3.3-V AVDD Operation
Copyright © 2021 Texas Instruments Incorporated
28
Submit Document Feedback
Product Folder Links: PCM1820 PCM1821
PCM1820, PCM1821
SBASA61A – DECEMBER 2020 – REVISED JUNE 2021
www.ti.com
9.2.1 Design Requirements
Table 9-1 lists the design parameters for this application.
Table 9-1. Design Parameters
KEY PARAMETER
SPECIFICATION (3.3-V AVDD Operation)
AVDD
3.3 V
AVDD supply current consumption
IOVDD
12.9 mA (two-channel recording, fS = 48 kHz)
1.8 V or 3.3 V
9.2.2 Detailed Design Procedure
This section describes the necessary steps to configure the PCM182x for this specific application. The following
steps provide a sequence of steps that must be executed in the time between powering the device up and
reading data from the device or transitioning from one mode to another mode of operation.
1. Apply power to the device:
a. Power-up the IOVDD and AVDD power supplies
b. The device now goes into low-power mode
2. Configure the pins for correct configuration:
a. Connect the MSZ, FMT0, MD0, and MD1 pin voltages for the desired configuration
b. Apply FSYNC and BCLK with the desired output sample rates and the BCLK to FSYNC ratio
See the Phase-Locked Loop (PLL) and Clock Generation section for supported sample rates and the
BCLK to FSYNC ratio
c. The device recording data are now sent to the host processor via the audio serial data bus
3. Stop the clocks to stop recording of data at any time
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
29
Product Folder Links: PCM1820 PCM1821
PCM1820, PCM1821
SBASA61A – DECEMBER 2020 – REVISED JUNE 2021
www.ti.com
9.2.3 Application Curves
Measurements are done on the EVM by feeding the device analog input signal using audio precision and with a
3.3-V AVDD supply.
0
-20
-60
Channel-1 : DRE enabled
Channel-2 : DRE enabled
Channel-1: DRE Enabled
Channel-2: DRE Enabled
-70
-40
-80
-60
-80
-90
-100
-120
-140
-160
-180
-200
-100
-110
-120
-130
20 30 4050 70 100
200 300 500
1000 2000
5000 10000 20000
ADC6
-130
-115
-100
-85
-70
-55
-40
-25
-10
0
Frequency (Hz)
Input Amplitude (dB)
ATHDDC+6
Figure 9-2. PCM1820: FFT With a –60-dBr Input
With DRE Enabled
Figure 9-3. PCM1820: THD+N vs Input Amplitude
With DRE Enabled
0
-60
Channel-1 : DRE disabled
Channel-1: DRE Disabled
Channel-2: DRE Disabled
Channel-2 : DRE disabled
-20
-70
-80
-40
-60
-80
-90
-100
-120
-140
-160
-180
-200
-100
-110
-120
-130
20 30 4050 70 100
200 300 500
1000 2000
5000 10000 20000
ADC6
-130
-115
-100
-85
-70
-55
-40
-25
-10
0
Frequency (Hz)
Input Amplitude (dB)
ATHDDC+6
Figure 9-4. PCM1820: FFT With a –60-dBr Input
With DRE Disabled
Figure 9-5. PCM1820: THD+N vs Input Amplitude
With DRE Disabled
0
-60
Channel-1
Channel-1
Channel-2
Channel-2
-20
-70
-80
-40
-60
-80
-90
-100
-120
-140
-160
-180
-200
-100
-110
-120
-130
20 30 4050 70 100
200 300 500
1000 2000
5000 10000 20000
PCM1
-130
-115
-100
-85
-70
-55
-40
-25
-10
0
Frequency (Hz)
Input Amplitude (dB)
PTCHMD+1
Figure 9-6. PCM1821: FFT With a –60-dBr Input
Figure 9-7. PCM1821: THD+N vs Input Amplitude
Copyright © 2021 Texas Instruments Incorporated
30
Submit Document Feedback
Product Folder Links: PCM1820 PCM1821
PCM1820, PCM1821
SBASA61A – DECEMBER 2020 – REVISED JUNE 2021
www.ti.com
10 Power Supply Recommendations
The power-supply sequence between the IOVDD and AVDD rails can be applied in any order. However, do not
provide any clocks until the IOVDD and AVDD supply voltage settles to a stable and supported operating voltage
range. Provide the clocks (FSYNC and BCLK) only when all hardware control pins (MSZ, MD0, MD1, and FMT0)
are driven to the voltage level for the device desired mode of operation.
For the supply power-up requirement, t1 and t2 must be at least 100 µs. For the supply power-down requirement,
t3 and t4 must be at least 10 ms. This timing (as shown in Figure 10-1) allows the device to ramp down
the volume on the record data, power down the analog and digital blocks, and put the device into hardware
shutdown mode.
AVDD
t1
t3
IOVDD
ASI Clocks
t2
t4
Figure 10-1. Power-Supply Sequencing Requirement Timing Diagram
Make sure that the supply ramp rate is slower than 1 V/µs and that the wait time between a power-down and a
power-up event is at least 100 ms. All digital input pins must be held at valid input levels and not toggling during
supply sequencing.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
31
Product Folder Links: PCM1820 PCM1821
PCM1820, PCM1821
SBASA61A – DECEMBER 2020 – REVISED JUNE 2021
www.ti.com
11 Layout
11.1 Layout Guidelines
Each system design and printed circuit board (PCB) layout is unique. The layout must be carefully reviewed in
the context of a specific PCB design. However, the following guidelines can optimize the device performance:
•
Connect the thermal pad to ground. Use a via pattern to connect the device thermal pad, which is the area
directly under the device, to the ground planes. This connection helps dissipate heat from the device.
The decoupling capacitors for the power supplies must be placed close to the device pins.
Route the analog differential audio signals differentially on the PCB for better noise immunity. Avoid crossing
digital and analog signals to prevent undesirable crosstalk.
•
•
•
•
•
The device internal voltage references must be filtered using external capacitors. Place the filter capacitors
near the VREF pin for optimal performance.
Directly short the VREF external capacitor ground terminal to the AVSS pin without using any vias for this
connection trace.
Use ground planes to provide the lowest impedance for power and signal current between the device and the
decoupling capacitors. Treat the area directly under the device as a central ground area for the device, and
all device grounds must be connected directly to that area.
11.2 Layout Example
15: VSS
16: AVDD
17: AREG
9: IOVDD
8: FSYNC
18: VREF
19: FMT0
7: BCLK
6: SDOUT
5: VSS
Figure 11-1. Example Layout
Copyright © 2021 Texas Instruments Incorporated
32
Submit Document Feedback
Product Folder Links: PCM1820 PCM1821
PCM1820, PCM1821
SBASA61A – DECEMBER 2020 – REVISED JUNE 2021
www.ti.com
12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
Burr-Brown™ and TI E2E™ are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
33
Product Folder Links: PCM1820 PCM1821
PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PCM1820IRTER
PCM1821IRTER
XCM1820IRTER
XCM1821IRTER
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WQFN
WQFN
WQFN
WQFN
RTE
RTE
RTE
RTE
20
20
20
20
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Call TI
-40 to 125
-40 to 125
-40 to 125
-40 to 125
PC1820
PC1821
NIPDAU
Call TI
3000
3000
TBD
TBD
Call TI
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2021
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Jul-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
PCM1820IRTER
PCM1821IRTER
WQFN
WQFN
RTE
RTE
20
20
3000
3000
330.0
330.0
12.4
12.4
3.3
3.3
3.3
3.3
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Jul-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
PCM1820IRTER
PCM1821IRTER
WQFN
WQFN
RTE
RTE
20
20
3000
3000
367.0
367.0
367.0
367.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
A
RTE0020A
3.1
2.9
B
PIN 1 INDEX AREA
3.1
2.9
C
0.8 MAX
SEATING PLANE
0.08 C
0.05
0.00
1.5
SQ
1.4±0.1
4X (SQ 0.2)
TYP
(0.1)
6
10
5
9
8X 0.4625
0.225
0.125
0.1
8X
4
11
C
A B
0.05
C
SYMM
21
1.5
14
1
12X 0.5
0.3
0.2
0.1
16X
0.5
C A B
PIN1 ID
(OPTIONAL)
15
20
19
16
0.05
C
16X
SYMM
0.3
4225900/A 06/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
WQFN - 0.8 mm max height
RTE0020A
PLASTIC QUAD FLATPACK- NO LEAD
(2.825)
(2.8)
(SQ 1.4)
4X (0.575)
4X (0.175)
16X (0.6)
4X (0.575)
15
19
16
20
8X (0.4625)
4X (0.175)
14
1
16X (0.25)
12X (0.5)
(2.825)
(2.8)
SYMM
21
2X (0.45)
11
4
(R 0.05) TYP
(Ø 0.2) VIA
TYP
5
10
2X (0.45)
9
6
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.07 MAX
0.07 MIN
ALL AROUND
ALL AROUND
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4225900/A 06/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271)
.
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
WQFN - 0.8 mm max height
RTE0020A
PLASTIC QUAD FLATPACK- NO LEAD
(2.825)
(2.8)
4X (0.575)
4X (0.175)
(SQ 1.3)
16X (0.6)
4X (0.575)
19
16
15
20
8X (0.4625)
4X (0.175)
21
1
14
16X (0.25)
12X (0.5)
(2.825)
SYMM
(2.8)
11
4
(R 0.05) TYP
METAL TYP
5
10
9
6
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
86% PRINTED COVERAGE BY AREA
SCALE: 20X
4225900/A 06/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明