PCM1840 [TI]
四通道、32 位、192kHz 音频模数转换器 (ADC);
| 型号： | PCM1840 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 四通道、32 位、192kHz 音频模数转换器 (ADC) 转换器 模数转换器 |
| 文件： | 总39页 (文件大小：2484K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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PCM1840
ZHCSL25 –APRIL 2019
PCM1840 四通道、32 位、192kHz Burr-BrownTM 音频 ADC
1 特性
3 说明
1
•
多通道高性能 ADC：
PCM1840 是一款高性能 Burr-Brown™音频模数转换
器 (ADC)，可支持高达四个模拟通道的同步采样。此
器件支持差分线路和麦克风输入，具有 2VRMS 满量程
信号，集成了麦克风偏置电压、锁相环 (PLL)、直流去
除高通滤波器 (HPF) 等特性，并支持高达 192kHz 的
采样率。该器件支持时分多路复用 (TDM)、I2S 或左平
衡 (LJ) 音频格式，且硬件引脚电平可选。此
–
4 通道模拟麦克风输入或线路输入
•
ADC 线路和麦克风差分输入性能：
–
动态范围：
–
–
123dB，启用动态范围增强器
113dB，禁用动态范围增强器
–
THD+N：–98dB
外，PCM1840 还支持主从模式选择，从而实现音频总
线接口操作。这些集成的高性能 特性，以及采用 3.3V
单电源供电的功能，使该器件非常适用于远场麦克风录
音 应用中成本敏感的空间受限型音频系统。
•
•
•
•
•
ADC 差分 2VRMS 满量程输入
ADC 采样率 (fS) = 8kHz 至 192kHz
硬件引脚控制配置
线性相位或低延迟滤波器可选
灵活的音频串行数据接口：
PCM1840 的额定工作温度范围为 –40°C 至 +125°C，
并且采用 24 引脚 WQFN 封装。
–
–
–
–
–
主或从接口可选
32 位、4 通道 TDM
32 位、2 通道 TDM
32 位、2 通道 I2S
器件信息(1)
器件型号
PCM1840
封装
封装尺寸（标称值）
4.00mm × 4.00mm，间距
为 0.5mm
WQFN (24)
32 位、2 通道左平衡 (LJ)
•
•
•
•
•
•
音频时钟丢失时自动断电
集成高性能音频 PLL
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
低噪声麦克风偏置 2.75V 输出
单电源运行：3.3V
简化方框图
I/O 电源运行：3.3V 或 1.8V
3.3V AVDD 电源电压下的功耗：
IN1P
PLL and Clock Generation
IN1M
FSYNC
Audio Serial
Interface
BCLK
–
–
16kHz 采样率下为 17.0mW/通道
48kHz 采样率下为 18.4mW/通道
IN2P
(TDM, I2S, LJ)
SDOUT
SHDNZ
IN2M
Quad Channel
ADC with
Front-End DRE
Amplifier
Configurable
Digital Filters,
and DRE
IN3P
IN3M
2 应用
MSZ
FMT0
IN4P
IN4M
•
•
•
•
•
智能扬声器
Hardware Pin
Control
Interface
FMT1
MD0
DVD 录像机和播放器
AV 接收机
MICBIAS, Regulators and Voltage
Reference
MICBIAS
VREF
MD1
视频会议系统
IP 网络摄像头
Thermal Pad
(VSS)
AVDD
DREG
AVSS
IOVDD
AREG
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBAS989
PCM1840
ZHCSL25 –APRIL 2019
www.ti.com.cn
目录
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 26
Application and Implementation ........................ 27
8.1 Application Information............................................ 27
8.2 Typical Application .................................................. 27
Power Supply Recommendations...................... 30
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Timing Requirements: TDM, I2S or LJ Interface....... 7
6.7 Switching Characteristics: TDM, I2S or LJ Interface. 7
6.8 Typical Characteristics.............................................. 8
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
8
9
10 Layout................................................................... 31
10.1 Layout Guidelines ................................................. 31
10.2 Layout Example .................................................... 31
11 器件和文档支持 ..................................................... 32
11.1 接收文档更新通知 ................................................. 32
11.2 社区资源................................................................ 32
11.3 商标....................................................................... 32
11.4 静电放电警告......................................................... 32
11.5 Glossary................................................................ 32
12 机械、封装和可订购信息....................................... 32
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
日期
修订版本
说明
2020 年 4 月
*
初始发行版。
2
Copyright © 2019, Texas Instruments Incorporated
PCM1840
www.ti.com.cn
ZHCSL25 –APRIL 2019
5 Pin Configuration and Functions
RTW Package
24-Pin WQFN With Exposed Thermal Pad
Top View
AVDD
AREG
VREF
1
2
3
4
5
6
18
17
16
15
14
13
MD0
MSZ
FMT0
FMT1
SHDNZ
IN4M
Thermal Pad (VSS)
AVSS
MICBIAS
IN1P
Not to scale
Pin Functions
PIN
NAME
TYPE
DESCRIPTION
NO.
1
AVDD
AREG
VREF
AVSS
MICBIAS
IN1P
Analog supply
Analog Supply
Analog
Analog power (3.3 V, nominal)
2
Analog on-chip regulator output voltage for analog supply (1.8 V, nominal)
Analog reference voltage filter output
Analog ground. Short this pin directly to the board ground plane.
MICBIAS output
3
4
Analog supply
Analog
5
6
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Digital input
Digital input
Digital input
Digital input
Digital input
Digital supply
Digital input
Digital output
Digital I/O
Analog input 1P pin
7
IN1M
Analog input 1M pin
8
IN2P
Analog input 2P pin
9
IN2M
Analog input 2M pin
10
11
12
13
14
15
16
17
18
19
20
21
22
23
IN3P
Analog input 3P pin
IN3M
Analog input 3M pin
IN4P
Analog input 4P pin
IN4M
Analog input 4M pin
SHDNZ
FMT1
FMT0
MSZ
Device hardware shutdown and reset (active low)
Audio interface format select 1 pin
Audio interface format select 0 pin
Audio interface bus master or slave select pin
Device configuration mode select 0 pin
Digital I/O power supply (1.8 V or 3.3 V, nominal)
Device configuration mode select 1 pin
Audio serial data interface bus output
Audio serial data interface bus bit clock
Audio serial data interface bus frame synchronization signal
MD0
IOVDD
MD1
SDOUT
BCLK
FSYNC
Digital I/O
Copyright © 2019, Texas Instruments Incorporated
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PCM1840
ZHCSL25 –APRIL 2019
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Pin Functions (continued)
PIN
TYPE
DESCRIPTION
NO.
NAME
24
DREG
Digital supply
Ground supply
Digital regulator output voltage for digital core supply (1.5 V, nominal)
Thermal pad shorted to internal device ground. Short thermal pad directly to board
ground plane.
Thermal Pad (VSS)
6 Specifications
6.1 Absolute Maximum Ratings
over the operating ambient temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–40
MAX
UNIT
AVDD to AVSS
3.9
Supply voltage
AREG to AVSS
2.0
3.9
V
IOVDD to VSS (thermal pad)
AVSS to VSS (thermal pad)
Analog input pins voltage to AVSS
Digital input pins voltage to VSS (thermal pad)
Operating ambient, TA
Ground voltage differences
Analog input voltage
Digital input voltage
0.3
V
V
V
AVDD + 0.3
IOVDD + 0.3
125
Temperature
Junction, TJ
–40
150
°C
Storage, Tstg
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
NOM
MAX
UNIT
POWER
AVDD,
Analog supply voltage AVDD to AVSS (AREG is generated using onchip regulator) -
AVDD 3.3-V operation
3.0
3.3
3.6
V
V
AREG(1)
IO supply voltage to VSS (thermal pad) - IOVDD 3.3-V operation
IO supply voltage to VSS (thermal pad) - IOVDD 1.8-V operation
3.0
3.3
1.8
3.6
IOVDD
1.65
1.95
INPUTS
Analog input pins voltage to AVSS
0
0
AVDD
V
V
Digital input pins voltage to VSS (thermal pad)
IOVDD
TEMPERATURE
TA
Operating ambient temperature
–40
125
°C
OTHERS
Digital input pin used as MCLK input clock frequency
Digital output load capacitance
36.864
50
MHz
pF
CL
20
(1) AVSS and VSS (thermal pad): all ground pins must be tied together and must not differ in voltage by more than 0.2 V.
4
Copyright © 2019, Texas Instruments Incorporated
PCM1840
www.ti.com.cn
ZHCSL25 –APRIL 2019
6.4 Thermal Information
PCM1840
RTW (WQFN)
24 PINS
32.6
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
25.0
11.9
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
ψJB
11.9
RθJC(bot)
2.9
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, fIN = 1-kHz sinusoidal signal, fS = 48 kHz, 32-bit audio data, BCLK = 256 × fS,
TDM slave mode (unless otherwise noted)
PARAMETER
ADC CONFIGURATION
AC input impedance
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Input pins INxP or INxM
2.5
kΩ
ADC PERFORMANCE FOR LINE/MICROPHONE INPUT RECORDING : AVDD 3.3-V OPERATION
Differential input full-scale
AC-coupled input
2
122
112
123
113
–98
–98
VRMS
AC signal voltage
IN1 differential input selected and AC signal shorted to
ground, DRE enabled (DRE_LVL = –36 dB,
DRE_MAXGAIN = 24 dB)
115
106
Signal-to-noise ratio, A-
weighted(1)(2)
SNR
DR
dB
IN1 differential input selected and AC signal shorted to
ground, DRE disabled
IN1 differential input selected and –60-dB full-scale AC
signal input, DRE enabled (DRE_LVL = –36 dB,
DRE_MAXGAIN = 24 dB)
Dynamic range, A-
weighted(2)
dB
dB
IN1 differential input selected and –60-dB full-scale AC
signal input, DRE disabled
IN1 differential input selected and –1-dB full-scale AC
signal input, DRE enabled (DRE_LVL = –36 dB,
DRE_MAXGAIN = 24 dB)
–80
Total harmonic
distortion(2)(3)
THD+N
IN1 differential input selected and –1-dB full-scale AC
signal input, DRE disabled
ADC OTHER PARAMETERS
Output data sample rate
7.35
192
32
kHz
Bits
Output data sample word
length
–1-dB full-scale AC-signal input to non measurement
channel
Interchannel isolation
–124
dB
Interchannel gain
mismatch
–6-dB full-scale AC-signal input
across temperature range 15°C to 35°C
1-kHz sinusoidal signal
0.1
–4.4
0.02
dB
Gain drift
ppm/°C
Degrees
Interchannel phase
mismatch
1-kHz sinusoidal signal, across temperature range 15°C
to 35°C
Phase drift
0.0005
102
Degrees/°C
Power-supply rejection
ratio
100-mVPP, 1-kHz sinusoidal signal on AVDD, differential
input selected, 0-dB channel gain
PSRR
CMRR
dB
dB
Common-mode rejection
ratio
Differential microphone input selected, 100-mVPP, 1-kHz
signal on both pins and measure level at output
60
(1) Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with the AC signal input shorted to ground, measured A-
weighted over a 20-Hz to 20-kHz bandwidth using an audio analyzer.
(2) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values.
(3) For best distortion performance, use input AC-coupling capacitors with low-voltage-coefficient.
Copyright © 2019, Texas Instruments Incorporated
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PCM1840
ZHCSL25 –APRIL 2019
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Electrical Characteristics (continued)
at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, fIN = 1-kHz sinusoidal signal, fS = 48 kHz, 32-bit audio data, BCLK = 256 × fS,
TDM slave mode (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MICROPHONE BIAS
BW = 20 Hz to 20 kHz, A-weighted, 1-μF capacitor
between MICBIAS and AVSS
MICBIAS noise
1.6
µVRMS
MICBIAS voltage
VREF
V
mA
%
MICBIAS current drive
MICBIAS load regulation
20
Measured up to max load
0.1
30
0.6
1.8
MICBIAS over current
protection threshold
mA
DIGITAL I/O
0.30 ×
IOVDD
All digital pins, IOVDD 1.8-V operation
All digital pins, IOVDD 3.3-V operation
All digital pins, IOVDD 1.8-V operation
–0.3
–0.3
Low-level digital input logic
voltage threshold
VIL
V
V
0.8
0.7 ×
IOVDD
IOVDD +
0.3
High-level digital input logic
voltage threshold
VIH
IOVDD +
0.3
All digital pins, IOVDD 3.3-V operation
2.1
All digital pins, IOL = –2 mA, IOVDD 1.8-V operation
All digital pins, IOL = –2 mA, IOVDD 3.3-V operation
0.45
0.4
Low-level digital output
voltage
VOL
V
V
IOVDD –
0.45
All digital pins, IOH = 2 mA, IOVDD 1.8-V operation
All digital pins, IOH = 2 mA, IOVDD 3.3-V operation
All digital pins, input = IOVDD
High-level digital output
voltage
VOH
2.4
–5
Input logic-high leakage for
digital inputs
IIH
0.1
0.1
5
5
5
µA
µA
pF
Input logic-low leakage for
digital inputs
IIL
All digital pins, input = 0 V
All digital pins
–5
Input capacitance for
digital inputs
CIN
Pulldown resistance for
digital I/O pins when
asserted on
RPD
20
kΩ
TYPICAL SUPPLY CURRENT CONSUMPTION
IAVDD
IIOVDD
IIOVDD
IAVDD
IIOVDD
IIOVDD
IAVDD
IIOVDD
IIOVDD
IAVDD
IIOVDD
IIOVDD
SHDNZ = 0, AVDD = 3.3 V, internal AREG
0.5
0.1
Current consumption in
hardware shutdown mode
SHDNZ = 0, all external clocks stopped, IOVDD = 3.3 V
SHDNZ = 0, all external clocks stopped, IOVDD = 1.8 V
AVDD = 3.3 V, internal AREG
IOVDD = 3.3 V
µA
mA
mA
mA
0.1
20.6
0.05
0.02
22.3
0.1
Current consumption with
ADC 4-channel operating
at fS 16-kHz, BCLK = 256
× fS and DRE disable
IOVDD = 1.8 V
AVDD = 3.3 V, internal AREG
IOVDD = 3.3 V
Current consumption with
ADC 4-channel operating
at fS 48-kHz, BCLK = 256
× fS and DRE disable
IOVDD = 1.8 V
0.05
24.4
0.1
AVDD = 3.3 V, internal AREG
IOVDD = 3.3 V
Current consumption with
ADC 4-channel operating
at fS 48-kHz, BCLK = 256
× fS and DRE enable
IOVDD = 1.8 V
0.05
6
Copyright © 2019, Texas Instruments Incorporated
PCM1840
www.ti.com.cn
ZHCSL25 –APRIL 2019
6.6 Timing Requirements: TDM, I2S or LJ Interface
at TA = 25°C, IOVDD = 3.3 V or 1.8 V and 20-pF load on all outputs (unless otherwise noted); see Figure 3 for timing diagram
MIN
40
18
18
8
NOM
MAX
UNIT
t(BCLK)
BCLK period
ns
(1)
tH(BCLK)
tL(BCLK)
tSU(FSYNC)
tHLD(FSYNC)
tr(BCLK)
BCLK high pulse duration
BCLK low pulse duration
FSYNC setup time
FSYNC hold time
BCLK rise time
ns
(1)
ns
ns
8
ns
10% - 90% rise time
90% - 10% fall time
10
10
ns
tf(BCLK)
BCLK fall time
ns
(1) The BCLK minimum high or low pulse duration must be higher than 25 ns (to meet the timing specifications), if the SDOUT data line is
latched on the opposite BCLK edge polarity than the edge used by the device to transmit SDOUT data.
6.7 Switching Characteristics: TDM, I2S or LJ Interface
at TA = 25°C, IOVDD = 3.3 V or 1.8 V and 20-pF load on all outputs (unless otherwise noted); see Figure 3 for timing diagram
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
td(SDOUT-BCLK)
td(SDOUT-FSYNC)
BCLK to SDOUT delay
50% of BCLK to 50% of SDOUT
18
ns
FSYNC to SDOUT delay in TDM
or LJ mode (for MSB data with
TX_OFFSET = 0)
50% of FSYNC to 50% of
SDOUT
18
ns
BCLK output clock frequency:
master mode
f(BCLK)
24.576
MHz
ns
(1)
BCLK high pulse duration:
master mode
tH(BCLK)
tL(BCLK)
td(FSYNC)
14
14
BCLK low pulse duration: master
mode
ns
BCLK to FSYNC delay: master
mode
50% of BCLK to 50% of FSYNC
18
ns
tr(BCLK)
tf(BCLK)
BCLK rise time: master mode
BCLK fall time: master mode
10% - 90% rise time
90% - 10% fall time
8
8
ns
ns
(1) The BCLK output clock frequency must be lower than 18.5 MHz (to meet the timing specifications), if the SDOUT data line is latched on
the opposite BCLK edge polarity than the edge used by the device to transmit SDOUT data.
FSYNC
tSU(FSYNC)
tHLD(FSYNC)
t(BCLK)
tL(BCLK)
BCLK
tH(BCLK)
tr(BCLK)
tf(BCLK)
td(FSYNC)
td(SDOUT-BCLK)
td(SDOUT-FSYNC)
SDOUT
图 1. TDM, I2S, and LJ Interface Timing Diagram
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PCM1840
ZHCSL25 –APRIL 2019
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6.8 Typical Characteristics
at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, fIN = 1-kHz sinusoidal signal, fS = 48 kHz, 32-bit audio data, BCLK = 256 × fS,
TDM slave mode, PLL on, DRE_LVL = –36 dB, channel gain = 0 dB, and linear phase decimation filter (unless otherwise
noted); all performance measurements are done with a 20-kHz, low-pass filter, and an A-weighted filter
-60
-70
-60
-70
Channel-1 : DRE enabled
Channel-2 : DRE enabled
Channel-3 : DRE enabled
Channel-4 : DRE enabled
Channel-1 : DRE disabled
Channel-2 : DRE disabled
Channel-3 : DRE disabled
Channel-4 : DRE disabled
-80
-80
-90
-90
-100
-110
-120
-130
-100
-110
-120
-130
-130
-115
-100
-85
-70
-55
-40
-25
-10
0
-130
-115
-100
-85
-70
-55
-40
-25
-10
0
Input Amplitude (dB)
Input Amplitude (dB)
TDH1D0+1
TDH1D0+1
Differential input
Differential input
图 2. THD+N vs Input Amplitude With DRE Enabled
图 3. THD+N vs Input Amplitude With DRE Disabled
-60
-60
Channel-1 : DRE enabled
Channel-2 : DRE enabled
Channel-3 : DRE enabled
Channel-4 : DRE enabled
Channel-1
Channel-2
Channel-3
Channel-4
-70
-70
-80
-90
-80
-90
-100
-110
-120
-130
-100
-110
-120
-130
20
50
100
500
1000
5000 10000 20000
D103
20
50
100
500
1000
5000 10000 20000
D410
Frequency (Hz)
Frequency (Hz)
图 4. THD+N vs Input Frequency With a –60-dBr Input
20
图 5. THD+N vs Input Frequency With a –1-dBr Input
-60
Channel-1
Channel-2
Channel-3
10
0
-70
-80
Channel-4
-10
-20
-30
-40
-90
-50
-60
-100
-110
-120
-130
-70
-80
-90
-100
-110
-120
20 30 50 70100 200300 500 1000 2000
5000 1000020000
100000
AFDrCeq6
20
50
100
500
1000
5000 10000 20000
D106
Frequency (Hz)
Frequency (Hz)
图 6. Frequency Response With a –12-dBr Input
图 7. Power-Supply Rejection Ratio vs Ripple Frequency
With 100-mVPP Amplitude
8
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Typical Characteristics (接下页)
at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, fIN = 1-kHz sinusoidal signal, fS = 48 kHz, 32-bit audio data, BCLK = 256 × fS,
TDM slave mode, PLL on, DRE_LVL = –36 dB, channel gain = 0 dB, and linear phase decimation filter (unless otherwise
noted); all performance measurements are done with a 20-kHz, low-pass filter, and an A-weighted filter
0
0
Channel-1 : DRE enabled
Channel-2 : DRE enabled
Channel-3 : DRE enabled
Channel-4 : DRE enabled
Channel-1 : DRE disabled
Channel-2 : DRE disabled
Channel-3 : DRE disabled
Channel-4 : DRE disabled
-20
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-180
-200
-100
-120
-140
-160
-180
-200
20
50
100
500
1000
5000 10000 20000
ADC6
20
50
100
500
1000
5000 10000 20000
ADC6
Frequency (Hz)
Frequency (Hz)
图 8. FFT With Idle Input With DRE Enabled
图 9. FFT With Idle Input With DRE Disabled
0
-20
0
-20
Channel-1 : DRE enabled
Channel-2 : DRE enabled
Channel-3 : DRE enabled
Channel-4 : DRE enabled
Channel-1 : DRE disabled
Channel-2 : DRE disabled
Channel-3 : DRE disabled
Channel-4 : DRE disabled
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-180
-200
-100
-120
-140
-160
-180
-200
20
50
100
500
1000
5000 10000 20000
ADC6
20
50
100
500
1000
5000 10000 20000
ADC6
Frequency (Hz)
Frequency (Hz)
图 10. FFT With a –60-dBr Input With DRE Enabled
图 11. FFT With a –60-dBr Input With DRE Disabled
0
0
Channel-1 : DRE enabled
Channel-2 : DRE enabled
Channel-1 : DRE disabled
Channel-2 : DRE disabled
-20
Channel-3 : DRE disabled
-20
Channel-3 : DRE enabled
Channel-4 : DRE enabled
Channel-4 : DRE disabled
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-180
-200
-100
-120
-140
-160
-180
-200
20
50
100
500
1000
5000 10000 20000
ADC6
20
50
100
500
1000
5000 10000 20000
ADC6
Frequency (Hz)
Frequency (Hz)
图 12. FFT With a –1-dBr Input With DRE Enabled
图 13. FFT With a –1-dBr Input With DRE Disabled
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7 Detailed Description
7.1 Overview
The PCM1840 is a high-performance, low-power, quad-channel, audio analog-to-digital converter (ADC) with
flexible audio interface control options. This device is intended for applications in voice-activated systems, AV
receivers, TV and blu-ray players, professional microphones, audio conferencing, portable computing,
communication, and entertainment applications. The high dynamic range of the device enables far-field audio
recording with high fidelity. This device integrates a host of features that reduces cost, board space, and power
consumption in space-constrained, battery-powered, consumer, home, and industrial applications. The device
features are controlled through hardware by pulling pins high or low with resistors or a controller GPIO. The
PCM1808 also supports a power-down and reset function by means of halting the system clock.
The PCM1840 consists of the following blocks and features:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Quad-channel, multibit, high-performance delta-sigma (ΔΣ) ADC
Differential audio inputs with a 2-VRMS full-scale signal
Low-noise, 1.6-µVRMS, microphone bias output
Hardware pin control operation to select the device features
Audio bus serial interface master or slave select option
Audio bus serial interface format select option
Audio bus serial interface supported up to 192 kHz sampling
Slave mode supports dynamic range enhancer (DRE) with 123-dB dynamic range
Slave mode supports decimation filters with linear-phase or low-latency filter selection
Master mode operation supported using system clock of 256 × fS or 512 × fS
Power-down function by means of halting the audio clocks
Integrated high-pass filter (HPF) that removes the dc component of the input signal
Integrated low-jitter phase-locked loop (PLL) supporting a wide range of system clocks
Integrated digital and analog voltage regulators to support single-supply 3.3-V operation
7.2 Functional Block Diagram
Audio Clock
Generation
PLL
(Input Clock
Source - BCLK,
MD1)
IN1P
IN1M
DRE
Amplifier
ADC
Channel-1
Digital Filters
(Linear-Phase and
Low-Latency LPF)
IN2P
IN2M
DRE
Amplifier
ADC
Channel-2
and
SDOUT
BCLK
DRE
Amplifier
ADC
Channel-3
IN3P
IN3M
Dynamic Range
Enhancer (DRE)
Audio Serial
Interface (TDM,
I2S, LJ)
ADC
Channel-4
DRE
Amplifier
IN4P
IN4M
FSYNC
SHDNZ
Hardware Pin Control
Interface
Regulators, Current Bias and
Voltage Reference
Microphone
Bias
MICBIAS
10
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7.3 Feature Description
7.3.1 Hardware Control
The device supports simple hardware pin controlled options to select specific mode of operation and audio
interface for a given system. The MSZ, MD0, MD1, FMT0, and FMT1 pins allow the device to be controlled by
either pullup or pulldown resistors as well as the GPIO from a digital device.
7.3.2 Audio Serial Interfaces
Digital audio data flows between the host processor and the PCM1840 on the digital audio serial interface (ASI),
or audio bus. This highly flexible ASI bus includes a TDM mode for multichannel operation, support for I2S or left-
justified protocols format, and the pin-selectable master-slave configurability for bus clock lines.
The device supports audio bus master or slave mode of operation using the hardware pin MSZ. In slave mode,
FSYNC and BCLK work as input pins whereas in master mode, FSYNC and BCLK work as output pins
generated by the device.表 1 shows the master and slave mode selection using the MSZ pin.
表 1. Master and Slave Mode Selection
MSZ
LOW
HIGH
MASTER AND SLAVE SELECTION
Slave mode of operation
Master ode of operation
The bus protocol TDM, I2S, or left-justified (LJ) format can be selected by using the FMT0 and FMT1 pins. As
shown in 表 2, these modes are all most significant byte (MSB)-first, pulse code modulation (PCM) data format,
with the output channel data word-length of 32 bits.
表 2. Audio Serial Interface Format
FMT1
LOW
LOW
HIGH
HIGH
FMT0
LOW
HIGH
LOW
HIGH
AUDIO SERIAL INTERFACE FORMAT
4-channel output with time division multiplexing (TDM) mode
2-channel output with time division multiplexing (TDM) mode
2-channel output with left-justified (LJ) mode
2-channel output with inter IC sound (I2S) mode
7.3.2.1 Time Division Multiplexed Audio (TDM) Interface
In TDM mode, also known as DSP mode, the rising edge of FSYNC starts the data transfer with the slot 0 data
first. Immediately after the slot 0 data transmission, the remaining slot data are transmitted in order. FSYNC and
each data bit (except the MSB of slot 0 when TX_OFFSET equals 0) is transmitted on the rising edge of BCLK.
图 14 to 图 17 illustrate the protocol timing for TDM operation with various configurations.
FSYNC
BCLK
SDOUT
N-1 N-2
2
1
0
N-1 N-2 N-3
2
1
0
N-1 N-2 N-3
2
1
0
N-1 N-2
2
1
0
Ch2
(Word Length : 32)
Ch1
(Word Length : 32)
Ch3 to Ch4
(Word Length : 32)
Ch1
(Word Length : 32)
(n+1)th Sample
nth Sample
图 14. TDM Mode Protocol Timing (FMT0 = LOW) In Slave Mode
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FSYNC
BCLK
SDOUT
N-1 N-2
2
1
0
N-1 N-2 N-3
2
1
0
N-1 N-2
2
1
0
Ch2
(Word Length : 32)
Ch1
(Word Length : 32)
Ch1
(Word Length : 32)
(n+1)th Sample
nth Sample
图 15. TDM Mode Protocol Timing (FMT0 = HIGH) In Slave Mode
FSYNC
BCLK
SDOUT
0
N-1 N-2 N-3
2
1
0
N-1 N-2 N-3
1
0
N-1 N-2 N-3
2
1
0
2
1
0
N-1 N-2 N-3
Ch2
(Word Length : 32)
Ch1
(Word Length : 32)
Ch1
(Word Length : 32)
(n+1)th Sample
Ch3 to Ch4
(Word Length : 32)
nth Sample ( 128 BCLK Cycles)
图 16. TDM Mode Protocol Timing (FMT0 = LOW) In Master Mode
FSYNC
BCLK
SDOUT
0
N-1 N-2 N-3
2
1
0
N-1 N-2 N-3
N-1 N-2 N-3
2
1
0
1
0
N-1 N-2 N-3
1
0
N-1
Ch2
(Word Length : 32)
Ch2
(Word Length : 32)
(n+1)th Sample (64 BCLK Cycles)
Ch1
(Word Length : 32)
Ch1
(Word Length : 32)
nth Sample (64 BCLK Cycles)
图 17. TDM Mode Protocol Timing (FMT0 = HIGH) In Master Mode
For proper operation of the audio bus in TDM mode, the number of bit clocks per frame must be greater than or
equal to the number of active output channels times the 32-bits word length of the output channel data. The
device transmits a zero data value on SDOUT for the extra unused bit clock cycles. The device supports FSYNC
as a pulse with a 1-cycle-wide bit clock, but also supports multiples as well.
7.3.2.2 Inter IC Sound (I2S) Interface
The standard I2S protocol is defined for only two channels: left and right. In I2S mode, the MSB of the left slot 0 is
transmitted on the falling edge of BCLK in the second cycle after the falling edge of FSYNC. The MSB of the
right slot 0 is transmitted on the falling edge of BCLK in the second cycle after the rising edge of FSYNC. Each
subsequent data bit is transmitted on the falling edge of BCLK. In master mode, FSYNC is transmitted on the
rising edge of BCLK. 图 18 and 图 19 illustrate the protocol timing for I2S operation in slave and master mode of
operation.
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FSYNC
BCLK
SDOUT
N-1 N-2
1
0
1
0
N-1 N-2
1
0
N-1 N-2
Left (Ch1)
Slot-0
(Word Length : 32)
(n+1)th Sample
Left (Ch1)
Slot-0
(Word Length : 32)
nth Sample
Right (Ch2)
Slot-0
(Word Length : 32)
图 18. I2S Mode Protocol Timing in Slave Mode
FSYNC
BCLK
SDOUT
1
0
N-1 N-2
1
0
N-1 N-2
1
0
N-1 N-2
1
0
N-1 N-2
1
0
Right (Ch2)
Slot-0
(Word Length : 32)
Right (Ch2)
Slot-0
(Word Length : 32)
Left (Ch1)
Slot-0
(Word Length : 32)
Left (Ch1)
Slot-0
(Word Length : 32)
nth Sample (64 BCLK Cycles)
(n+1)th Sample (64 BCLK Cycles)
图 19. I2S Protocol Timing In Master Mode
For proper operation of the audio bus in I2S mode, the number of bit clocks per frame must be greater than or
equal to the number of active output channels (including left and right slots) times the 32-bits word length of the
output channel data. The device FSYNC low pulse must be a number of BCLK cycles wide that is greater than or
equal to the number of active left slots times the 32-bits data word length. Similarly, the FSYNC high pulse must
be a number of BCLK cycles wide that is greater than or equal to the number of active right slots times the 32-
bits data word length. The device transmit zero data value on SDOUT for the extra unused bit clock cycles.
7.3.2.3 Left-Justified (LJ) Interface
The standard LJ protocol is defined for only two channels: left and right. In LJ mode, the MSB of the left slot 0 is
transmitted in the same BCLK cycle after the rising edge of FSYNC. Each subsequent data bit is transmitted on
the falling edge of BCLK. The MSB of the right slot 0 is transmitted in the same BCLK cycle after the falling edge
of FSYNC. Each subsequent data bit is transmitted on the falling edge of BCLK. In master mode, FSYNC is
transmitted on the rising edge of BCLK. 图 20 and 图 21 illustrate the protocol timing for LJ operation in slave
and master mode of operation.
FSYNC
BCLK
SDOUT
N-1 N-2
1
0
1
0
N-1 N-2
1
0
N-1 N-2
Left (Ch1)
Slot-0
(Word Length : 32)
(n+1)th Sample
Left (Ch1)
Slot-0
(Word Length : 32)
Right (Ch2)
Slot-0
(Word Length : 32)
nth Sample
图 20. LJ Mode Protocol Timing In Slave Mode
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FSYNC
BCLK
SDOUT
N-1 N-2
1
0
1
0
N-1 N-2
1
0
N-1 N-2
Left (Ch1)
Slot-0
(Word Length : 32)
(n+1)th Sample
Left (Ch1)
Slot-0
(Word Length : 32)
Right (Ch2)
Slot-0
(Word Length : 32)
nth Sample (128 BCLK Cycles)
图 21. LJ Mode Protocol Timing In Master Mode
For proper operation of the audio bus in LJ mode, the number of bit clocks per frame must be greater than or
equal to the number of active output channels (including left and right slots) times the 32-bits word length of the
output channel data. The device FSYNC high pulse must be a number of BCLK cycles wide that is greater than
or equal to the number of active left slots times the 32-bits data word length. Similarly, the FSYNC low pulse
must be number of BCLK cycles wide that is greater than or equal to the number of active right slots times the
32-bits data word length. The device transmit zero data value on SDOUT for the extra unused bit clock cycles.
14
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7.3.3 Phase-Locked Loop (PLL) and Clock Generation
The device uses an integrated, low-jitter, phase-locked loop (PLL) to generate internal clocks required for the
ADC modulator and digital filter engine, as well as other control blocks.
In slave mode of operation, the device supports the various output data sample rates (of the FSYNC signal
frequency) and the BCLK to FSYNC ratio to configure all clock dividers, including the PLL configuration,
internally without host programming. 表 3 and 表 4 list the supported FSYNC and BCLK frequencies.
表 3. Supported FSYNC (Multiples or Submultiples of 48 kHz) and BCLK Frequencies
BCLK (MHz)
BCLK TO
FSYNC RATIO
FSYNC
(8 kHz)
FSYNC
(16 kHz)
FSYNC
(24 kHz)
FSYNC
(32 kHz)
FSYNC
(48 kHz)
FSYNC
(96 kHz)
FSYNC
(192 kHz)
16
24
Reserved
Reserved
0.256
0.256
0.384
0.512
0.768
1.024
1.536
2.048
3.072
4.096
6.144
8.192
0.384
0.576
0.768
1.152
1.536
2.304
3.072
4.608
6.144
9.216
12.288
0.512
0.768
1.024
1.536
2.048
3.072
4.096
6.144
8.192
12.288
16.384
0.768
1.152
1.536
2.304
3.072
4.608
6.144
9.216
12.288
18.432
24.576
1.536
2.304
3.072
4.608
32
3.072
6.144
48
0.384
4.608
9.216
64
0.512
6.144
12.288
96
0.768
9.216
18.432
128
192
256
384
512
1.024
12.288
18.432
24.576
Reserved
Reserved
24.576
1.536
Reserved
Reserved
Reserved
Reserved
2.048
3.072
4.096
表 4. Supported FSYNC (Multiples or Submultiples of 44.1 kHz) and BCLK Frequencies
BCLK (MHz)
BCLK TO
FSYNC
FSYNC
FSYNC
FSYNC
FSYNC
FSYNC
FSYNC
FSYNC RATIO
(7.35 kHz)
(14.7 kHz)
(22.05 kHz)
(29.4 kHz)
(44.1 kHz)
(88.2 kHz)
(176.4 kHz)
16
24
Reserved
Reserved
Reserved
0.3528
Reserved
0.3528
0.4704
0.7056
0.9408
1.4112
1.8816
2.8224
3.7632
5.6448
7.5264
0.3528
0.5292
0.7056
1.0584
1.4112
2.1168
2.8224
4.2336
5.6448
8.4672
11.2896
0.4704
0.7056
0.9408
1.4112
1.8816
2.8224
3.7632
5.6448
7.5264
11.2896
15.0528
0.7056
1.0584
1.4112
2.1168
2.8224
4.2336
5.6448
8.4672
11.2896
16.9344
22.5792
1.4112
2.1168
2.8224
4.2336
32
2.8224
5.6448
48
4.2336
8.4672
64
0.4704
5.6448
11.2896
16.9344
22.5792
Reserved
Reserved
Reserved
Reserved
96
0.7056
8.4672
128
192
256
384
512
0.9408
11.2896
16.9344
22.5792
Reserved
Reserved
1.4112
1.8816
2.8224
3.7632
In the master mode of operation, the device uses the MD1 pin (as system clock, MCLK) as the reference input
clock source with supported system clock frequency option of either 256 × fS or 512 × fS as configured using the
MD0 pin. 表 5 shows the system clock selection for the master mode using the MD0 pin.
表 5. System Clock Selection for the Master Mode
MD0
LOW
HIGH
SYSTEM CLOCK SELECTION (Valid for Master Mode Only)
System clock with frequency 256 × fS connected to pin MD1 as MCLK
System clock with frequency 512 × fS connected to pin MD1 as MCLK
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See 表 7 and 表 20 for the MD0 and MD1 pin function in the slave mode of operation.
7.3.4 Input Channel Configurations
The device consists of four pairs of analog input pins (INxP and INxM) as differential inputs for the recording
channel. The device supports simultaneous recording of up to four channels using the high-performance
multichannel ADC. The input source for the analog pins can be from electret condenser analog microphones,
micro electrical-mechanical system (MEMS) analog microphones, or line-in (auxiliary) inputs from the system
board.
The voice or audio signal inputs must be capacitively coupled (AC-coupled) to the device and for best distortion
performance, use the low-voltage coefficient capacitors for AC coupling. The device has the typical input
impedance on INxP or INxM as 2.5 kΩ on each pins. The value of the coupling capacitor in AC-coupled mode
must be chosen so that the high-pass filter formed by the coupling capacitor and the input impedance do not
affect the signal content. Before proper recording can begin, this coupling capacitor must be charged up to the
common-mode voltage at power-up. To enable quick charging, the device has quick charge scheme to speed up
the charging of the coupling capacitor at power-up. The default value of the quick-charge timing is set for a
coupling capacitor up to 1 µF.
7.3.5 Reference Voltage
All audio data converters require a DC reference voltage. The PCM1840 achieves low-noise performance by
internally generating a low-noise reference voltage. This reference voltage is generated using a band-gap circuit
with high PSRR performance. This audio converter reference voltage must be filtered externally using a minimum
1-µF capacitor connected from the VREF pin to analog ground (AVSS). The value of this reference voltage,
VREF, is set to 2.75 V, which in turn supports a 2-VRMS differential full-scale input to the device. The required
minimum AVDD voltage for this VREF voltage is 3 V. Do not connect any external load to a VREF pin.
7.3.6 Microphone Bias
The device integrates a built-in, low-noise, 1.6-µVRMS microphone bias pin with an output voltage of 2.75 V that
can be used in the system for biasing electret-condenser microphones or providing the supply to the MEMS
analog or digital microphone. The integrated bias amplifier supports up to 20 mA of load current that can be used
for multiple microphones and is designed to provide a combination of high PSRR, and low noise bias voltages to
bias microphone for high-end audio applications. When using this MICBIAS pin for biasing or supplying to
multiple microphones, avoid any common impedance on the board layout for the MICBIAS connection to
minimize coupling across microphones.
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7.3.7 Signal-Chain Processing
The PCM1840 signal chain is comprised of very-low-noise, high-performance, and low-power analog blocks and
highly flexible and programmable digital processing blocks. The high performance and flexibility combined with a
compact package makes the PCM1840 optimized for a variety of end-equipments and applications that require
multichannel audio capture. 图 22 shows a conceptual block diagram that highlights the various building blocks
used in the signal chain, and how the blocks interact in the signal chain.
Output
Channel
Data to
INP
INM
Configurable
Decimation
Filters
DRE
Amplifier
HPF
DRE
ADC
Audio Bus
图 22. Signal-Chain Processing Flowchart
The front-end dynamic range enhancer (DRE) gain amplifier is very low noise, with a 123-dB dynamic range
performance. Along with a low-noise and low-distortion, multibit, delta-sigma ADC, the front-end DRE gain
amplifier enables the PCM1840 to record a far-field audio signal with very high fidelity, both in quiet and loud
environments. Moreover, the ADC architecture has inherent antialias filtering with a high rejection of out-of-band
frequency noise around multiple modulator frequency components. Therefore, the device prevents noise from
aliasing into the audio band during ADC sampling. Further on in the signal chain, an integrated, high-
performance multistage digital decimation filter sharply cuts off any out-of-band frequency noise with high stop-
band attenuation.
The device supports an input signal bandwidth up to 80 kHz, which allows the high-frequency non-audio signal to
be recorded by using a 176.4-kHz (or higher) sample rate.
7.3.7.1 Digital High-Pass Filter
To remove the DC offset component and attenuate the undesired low-frequency noise content in the record data,
the device supports a fixed high-pass filter (HPF) with –3-dB cut-off frequency of 0.00025 × fS. The HPF is not a
channel-independent filter but is globally applicable for all the ADC channels. This HPF is constructed using the
first-order infinite impulse response (IIR) filter, and is efficient enough to filter out possible DC components of the
signal. 表 6 shows the fixed –3-dB cutoff frequency value. 图 23 shows a frequency response plot for the HPF
filter.
表 6. HPF Cutoff Frequency Value
-3-dB CUTTOFF FREQUENCY AT 16 kHz
SAMPLE RATE
-3-dB CUTTOFF FREQUENCY AT 48 kHz
SAMPLE RATE
-3-dB CUTOFF FREQUENCY VALUE
0.00025 × fS
4 Hz
12 Hz
3
0
-3
-6
-9
-12
-15
-18
-21
-24
HPF -3 dB Cutoff = 0.00025 ì fS
5E-5
0.0001
0.0005
0.001
Normalized Frequency (1/fS)
0.005
0.01
0.05
DPlo
图 23. HPF Filter Frequency Response Plot
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7.3.7.2 Configurable Digital Decimation Filters
The device record channel includes a high dynamic range, built-in digital decimation filter to process the
oversampled data from the multibit delta-sigma (ΔΣ) modulator to generate digital data at the same Nyquist
sampling rate as the FSYNC rate. The decimation filter can be chosen from two different types only in slave
mode, depending on the required frequency response, group delay, and phase linearity requirements for the
target application. The selection of the decimation filter option can be done by the MD0 pin. 表 7 shows the
decimation filter mode selection for the record channel.
表 7. Decimation Filter Mode Selection for the Record Channel
MD0
DECIMATION FILTER MODE SELECTION (Supported Only in Slave Mode)
LOW
Linear phase filters are used for the decimation in slave mode. For master mode, the device
always use linear phase filters for the decimation.
HIGH
Low latency filters are used for the decimation in slave mode. For master mode, the device
always use linear phase filters for the decimation.
7.3.7.2.1 Linear Phase Filters
The linear phase decimation filters are the default filters set by the device and can be used for all applications
that require a perfect linear phase with zero-phase deviation within the pass-band specification of the filter. The
filter performance specifications and various plots for all supported output sampling rates are listed in this
section.
7.3.7.2.1.1 Sampling Rate: 8 kHz or 7.35 kHz
图 24 and 图 25 respectively show the magnitude response and the pass-band ripple for a decimation filter with a
sampling rate of 8 kHz or 7.35 kHz. 表 8 lists the specifications for a decimation filter with an
8-kHz or 7.35-kHz sampling rate.
10
0
0.5
0.4
0.3
0.2
0.1
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
D001
D001
图 24. Linear Phase Decimation Filter Magnitude Response
图 25. Linear Phase Decimation Filter Pass-Band Ripple
表 8. Linear Phase Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Pass-band ripple
Frequency range is 0 to 0.454 × fS
Frequency range is 0.58 × fS to 4 × fS
Frequency range is 4 × fS onwards
Frequency range is 0 to 0.454 × fS
–0.05
72.7
81.2
0.05
dB
Stop-band attenuation
Group delay or latency
dB
17.1
1/fS
18
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PCM1840
www.ti.com.cn
ZHCSL25 –APRIL 2019
7.3.7.2.1.2 Sampling Rate: 16 kHz or 14.7 kHz
图 26 and 图 27 respectively show the magnitude response and the pass-band ripple for a decimation filter with a
sampling rate of 16 kHz or 14.7 kHz. 表 9 lists the specifications for a decimation filter with an 16-kHz or 14.7-
kHz sampling rate.
10
0
0.5
0.4
0.3
0.2
0.1
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
D001
D001
图 26. Linear Phase Decimation Filter Magnitude Response
图 27. Linear Phase Decimation Filter Pass-Band Ripple
表 9. Linear Phase Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Pass-band ripple
Frequency range is 0 to 0.454 × fS
Frequency range is 0.58 × fS to 4 × fS
Frequency range is 4 × fS onwards
Frequency range is 0 to 0.454 × fS
–0.05
73.3
95.0
0.05
dB
Stop-band attenuation
Group delay or latency
dB
15.7
1/fS
7.3.7.2.1.3 Sampling Rate: 24 kHz or 22.05 kHz
图 28 and 图 29 respectively show the magnitude response and the pass-band ripple for a decimation filter with a
sampling rate of 24 kHz or 22.05 kHz. 表 10 lists the specifications for a decimation filter with an 24-kHz or
22.05-kHz sampling rate.
10
0
0.5
0.4
0.3
0.2
0.1
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
D001
D001
图 28. Linear Phase Decimation Filter Magnitude Response
图 29. Linear Phase Decimation Filter Pass-Band Ripple
表 10. Linear Phase Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Pass-band ripple
Frequency range is 0 to 0.454 × fS
Frequency range is 0.58 × fS to 4 × fS
Frequency range is 4 × fS onwards
Frequency range is 0 to 0.454 × fS
–0.05
73.0
96.4
0.05
dB
Stop-band attenuation
Group delay or latency
dB
16.6
1/fS
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7.3.7.2.1.4 Sampling Rate: 32 kHz or 29.4 kHz
图 30 and 图 31 respectively show the magnitude response and the pass-band ripple for a decimation filter with a
sampling rate of 32 kHz or 29.4 kHz. 表 11 lists the specifications for a decimation filter with an 32-kHz or 29.4-
kHz sampling rate.
10
0
0.5
0.4
0.3
0.2
0.1
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
D001
D001
图 30. Linear Phase Decimation Filter Magnitude Response
图 31. Linear Phase Decimation Filter Pass-Band Ripple
表 11. Linear Phase Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Pass-band ripple
Frequency range is 0 to 0.454 × fS
Frequency range is 0.58 × fS to 4 × fS
Frequency range is 4 × fS onwards
Frequency range is 0 to 0.454 × fS
–0.05
73.7
0.05
dB
Stop-band attenuation
Group delay or latency
dB
107.2
16.9
1/fS
7.3.7.2.1.5 Sampling Rate: 48 kHz or 44.1 kHz
图 32 and 图 33 respectively show the magnitude response and the pass-band ripple for a decimation filter with a
sampling rate of 48 kHz or 44.1 kHz. 表 12 lists the specifications for a decimation filter with an 48-kHz or 44.1-
kHz sampling rate.
10
0
0.5
0.4
0.3
0.2
0.1
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
D001
D001
图 32. Linear Phase Decimation Filter Magnitude Response
图 33. Linear Phase Decimation Filter Pass-Band Ripple
表 12. Linear Phase Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Pass-band ripple
Frequency range is 0 to 0.454 × fS
Frequency range is 0.58 × fS to 4 × fS
Frequency range is 4 × fS onwards
Frequency range is 0 to 0.454 × fS
–0.05
73.8
98.1
0.05
dB
Stop-band attenuation
Group delay or latency
dB
17.1
1/fS
20
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PCM1840
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ZHCSL25 –APRIL 2019
7.3.7.2.1.6 Sampling Rate: 96 kHz or 88.2 kHz
图 34 and 图 35 respectively show the magnitude response and the pass-band ripple for a decimation filter with a
sampling rate of 96 kHz or 88.2 kHz. 表 13 lists the specifications for a decimation filter with an 96-kHz or 88.2-
kHz sampling rate.
10
0
0.5
0.4
0.3
0.2
0.1
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
D001
D001
图 34. Linear Phase Decimation Filter Magnitude Response
图 35. Linear Phase Decimation Filter Pass-Band Ripple
表 13. Linear Phase Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Pass-band ripple
Frequency range is 0 to 0.454 × fS
Frequency range is 0.58 × fS to 4 × fS
Frequency range is 4 × fS onwards
Frequency range is 0 to 0.454 × fS
–0.05
73.6
97.9
0.05
dB
Stop-band attenuation
Group delay or latency
dB
17.1
1/fS
7.3.7.2.1.7 Sampling Rate: 192 kHz or 176.4 kHz
图 36 and 图 37 respectively show the magnitude response and the pass-band ripple for a decimation filter with a
sampling rate of 192 kHz or 176.4 kHz. 表 14 lists the specifications for a decimation filter with an 192-kHz or
176.4-kHz sampling rate.
0.5
0.4
0.3
0.2
0.1
0
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
0
0.05
0.1
0.15
0.2
Normalized Frequency (1/fS)
0.25
0.3
0.35
0.4
D001
D001
图 36. Linear Phase Decimation Filter Magnitude Response
图 37. Linear Phase Decimation Filter Pass-Band Ripple
表 14. Linear Phase Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Pass-band ripple
Frequency range is 0 to 0.3 × fS
Frequency range is 0.473 × fS to 4 × fS
Frequency range is 4 × fS onwards
Frequency range is 0 to 0.3 × fS
–0.05
70.0
0.05
dB
Stop-band attenuation
Group delay or latency
dB
111.0
11.9
1/fS
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7.3.7.2.2 Low-Latency Filters
For applications where low latency with minimal phase deviation (within the audio band) is critical, the low-
latency decimation filters on the PCM1840 can be used. The device supports these filters with a group delay of
approximately seven samples with an almost linear phase response within the 0.365 × fS frequency band. This
section provides the filter performance specifications and various plots for all supported output sampling rates for
the low-latency filters.
7.3.7.2.2.1 Sampling Rate: 16 kHz or 14.7 kHz
图 38 shows the magnitude response and 图 39 shows the pass-band ripple and phase deviation for a
decimation filter with a sampling rate of 16 kHz or 14.7 kHz. 表 15 lists the specifications for a decimation filter
with a 16-kHz or 14.7-kHz sampling rate.
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
0.3
0.2
0.1
0
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
Pass-Band Ripple
Phase Deviation
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
D002
图 39. Low-Latency Decimation Filter Pass-Band Ripple
D002
and Phase Deviation
图 38. Low-Latency Decimation Filter Magnitude Response
表 15. Low-Latency Decimation Filter Specifications
PARAMETER
Pass-band ripple
TEST CONDITIONS
Frequency range is 0 to 0.451 × fS
Frequency range is 0.61 × fS onwards
Frequency range is 0 to 0.363 × fS
Frequency range is 0 to 0.363 × fS
Frequency range is 0 to 0.363 × fS
MIN
–0.05
87.3
TYP
MAX
UNIT
dB
0.05
Stop-band attenuation
Group delay or latency
Group delay deviation
Phase deviation
dB
7.6
1/fS
–0.022
–0.21
0.022
0.25
1/fS
Degrees
22
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PCM1840
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ZHCSL25 –APRIL 2019
7.3.7.2.2.2 Sampling Rate: 24 kHz or 22.05 kHz
图 40 shows the magnitude response and 图 41 shows the pass-band ripple and phase deviation for a
decimation filter with a sampling rate of 24 kHz or 22.05 kHz. 表 16 lists the specifications for a decimation filter
with a 24-kHz or 22.05-kHz sampling rate.
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
0.3
0.2
0.1
0
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
Pass-Band Ripple
Phase Deviation
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
D002
图 41. Low-Latency Decimation Filter Pass-Band Ripple
D002
and Phase Deviation
图 40. Low-Latency Decimation Filter Magnitude Response
表 16. Low-Latency Decimation Filter Specifications
PARAMETER
Pass-band ripple
TEST CONDITIONS
MIN
–0.01
87.2
TYP
MAX
UNIT
dB
Frequency range is 0 to 0.459 × fS
Frequency range is 0.6 × fS onwards
Frequency range is 0 to 0.365 × fS
Frequency range is 0 to 0.365 × fS
Frequency range is 0 to 0.365 × fS
0.01
Stop-band attenuation
Group delay or latency
Group delay deviation
Phase deviation
dB
7.5
1/fS
–0.026
–0.26
0.026
0.30
1/fS
Degrees
7.3.7.2.2.3 Sampling Rate: 32 kHz or 29.4 kHz
图 42 shows the magnitude response and 图 43 shows the pass-band ripple and phase deviation for a
decimation filter with a sampling rate of 32 kHz or 29.4 kHz. 表 17 lists the specifications for a decimation filter
with a 32-kHz or 29.4-kHz sampling rate.
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
0.3
0.2
0.1
0
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
Pass-Band Ripple
Phase Deviation
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
D002
图 43. Low-Latency Decimation Filter Pass-Band Ripple
D002
and Phase Deviation
图 42. Low-Latency Decimation Filter Magnitude Response
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www.ti.com.cn
表 17. Low-Latency Decimation Filter Specifications
PARAMETER
Pass-band ripple
TEST CONDITIONS
MIN
–0.04
88.3
TYP
MAX
UNIT
dB
Frequency range is 0 to 0.457 × fS
Frequency range is 0.6 × fS onwards
Frequency range is 0 to 0.368 × fS
Frequency range is 0 to 0.368 × fS
Frequency range is 0 to 0.368 × fS
0.04
Stop-band attenuation
Group delay or latency
Group delay deviation
Phase deviation
dB
8.7
1/fS
–0.026
–0.26
0.026
0.31
1/fS
Degrees
7.3.7.2.2.4 Sampling Rate: 48 kHz or 44.1 kHz
图 44 shows the magnitude response and 图 45 shows the pass-band ripple and phase deviation for a
decimation filter with a sampling rate of 48 kHz or 44.1 kHz. 表 18 lists the specifications for a decimation filter
with a 48-kHz or 44.1-kHz sampling rate.
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
0.3
0.2
0.1
0
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
Pass-Band Ripple
Phase Deviation
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
D002
图 45. Low-Latency Decimation Filter Pass-Band Ripple
D002
and Phase Deviation
图 44. Low-Latency Decimation Filter Magnitude Response
表 18. Low-Latency Decimation Filter Specifications
PARAMETER
Pass-band ripple
TEST CONDITIONS
Frequency range is 0 to 0.452 × fS
Frequency range is 0.6 × fS onwards
Frequency range is 0 to 0.365 × fS
Frequency range is 0 to 0.365 × fS
Frequency range is 0 to 0.365 × fS
MIN
–0.015
86.4
TYP
MAX
UNIT
dB
0.015
Stop-band attenuation
Group delay or latency
Group delay deviation
Phase deviation
dB
7.7
1/fS
–0.027
–0.25
0.027
0.30
1/fS
Degrees
24
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PCM1840
www.ti.com.cn
ZHCSL25 –APRIL 2019
7.3.7.2.2.5 Sampling Rate: 96 kHz or 88.2 kHz
图 46 shows the magnitude response and 图 47 shows the pass-band ripple and phase deviation for a
decimation filter with a sampling rate of 96 kHz or 88.2 kHz. 表 19 lists the specifications for a decimation filter
with a 96-kHz or 88.2-kHz sampling rate.
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
0.3
0.2
0.1
0
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
Pass-Band Ripple
Phase Deviation
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
D002
图 47. Low-Latency Decimation Filter Pass-Band Ripple
D002
and Phase Deviation
图 46. Low-Latency Decimation Filter Magnitude Response
表 19. Low-Latency Decimation Filter Specifications
PARAMETER
Pass-band ripple
TEST CONDITIONS
Frequency range is 0 to 0.466 × fS
Frequency range is 0.6 × fS onwards
Frequency range is 0 to 0.365 × fS
Frequency range is 0 to 0.365 × fS
Frequency range is 0 to 0.365 × fS
MIN
–0.04
86.3
TYP
MAX
UNIT
dB
0.04
Stop-band attenuation
Group delay or latency
Group delay deviation
Phase deviation
dB
7.7
1/fS
–0.027
–0.26
0.027
0.30
1/fS
Degrees
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7.3.8 Dynamic Range Enhancer (DRE)
The device integrates an ultra-low noise front-end DRE gain amplifier with 123-dB dynamic range performance
with a low-noise, low-distortion, multibit delta-sigma (ΔΣ) ADC with a 108-dB dynamic range. The dynamic range
enhancer (DRE) is a digitally assisted algorithm to boost the overall channel performance. The DRE monitors the
incoming signal amplitude and accordingly adjusts the internal DRE amplifier gain automatically. The DRE
achieves a complete-channel dynamic range as high as 123 dB. At a system level, the DRE scheme enables far-
field, high-fidelity recording of audio signals in very quiet environments and low-distortion recording in loud
environments.
The DRE can be enable only in slave mode by driving high to the MD1 pin. 表 20 shows the DRE selection for
the record channel.
表 20. DRE Selection for the Record Channel
MD1
LOW
HIGH
DRE SELECTION (Supported Only in Slave Mode)
DRE is disabled in slave mode. For master mode, DRE is always disabled.
DRE is enabled with DRE_LVL = –36 dB and DRE_MAXGAIN = 24 dB in slave mode. For
master mode, DRE is always disabled.
This algorithm is implemented with very low latency and all signal chain blocks are designed to minimize any
audible artifacts that may occur resulting from dynamic gain modulation. The target signal threshold level,
DRE_LVL, at which DRE is triggered is fixed to the –36-dB input signal level. The DRE gain range can be
dynamically modulated by using DRE_MAXGAIN, which is fixed to 24 dB to maximize the benefit of the DRE in
real-world applications and to minimize any audible artifacts.
Enabling the DRE for processing increases the power consumption of the device because of increased signal
processing. Therefore, disable the DRE for low-power critical applications. Furthermore, the DRE is not
supported for output sample rates greater than 48 kHz.
7.4 Device Functional Modes
7.4.1 Hardware Shutdown
The device enters hardware shutdown mode when the SHDNZ pin is asserted low or the AVDD supply voltage is
not applied to the device. In hardware shutdown mode, the device consumes the minimum quiescent current
from the AVDD supply. If the SHDNZ pin is asserted low when the device is in active mode, the device ramps
down volume on the record data, powers down the analog and digital blocks, and puts the device into hardware
shutdown mode in 25 ms (typical).
7.4.2 Active Mode
In the hardware shutdown state, when the SHDNZ pin goes high, the device starts the internal boot-up sequence
and then enters into active mode in less than 20 ms (typical). Assert the SHDNZ pin high only when the IOVDD
supply settles to a steady voltage level and all hardware control pins (MSZ, MD0, MD1, FMT0, and FMT1) are
driven to the voltage level for the device desired mode of operation.
In active mode, when the audio clocks are available, the device powers up all the ADC channels and starts
transmitting the data over the audio serial interface. If the clocks are stopped then the device auto powers down
the ADC channels.
26
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PCM1840
www.ti.com.cn
ZHCSL25 –APRIL 2019
8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The PCM1840 is a multichannel, high-performance audio analog-to-digital converter (ADC) that supports output
sample rates of up to 192 kHz. The device supports up to four analog microphones for simultaneous recording
applications.
The PCM1840 configuration is supported using various hardware pin control options. The device supports a
highly flexible, audio serial interface (TDM, I2S, and LJ) to transmit audio data seamlessly in the system across
devices.
8.2 Typical Application
图 48 shows a typical configuration of the PCM1840 for an application using four analog microelectrical-
mechanical system (MEMS) microphones for simultaneous recording operation with a time-division multiplexing
(TDM) audio data slave interface. For best distortion performance, use input AC-coupling capacitors with a low-
voltage coefficient.
1 ꢀF
10 ꢀF
3.3 V
(3.0 V to
3.6 V)
1 ꢀF
GND GND
1 ꢀF
0.1 ꢀF
GND
0.1 ꢀF
GND
10 ꢀF
1 ꢀF
VDD
OUTP
IN1P
IN1M
DREG
AMIC1
OUTM
VSS
0.1 ꢀF
0.1 ꢀF
1 ꢀF
1 ꢀF
GND
GND
VDD
OUTP
IN2P
IN2M
3.3 V
(3.0 V to 3.6 V)
OR
1.8 V
(1.65 V to 1.95 V)
AMIC2
OUTM
VSS
10 ꢀF
0.1 ꢀF
IOVDD
1 ꢀF
1 ꢀF
PCM1840
GND
VDD
OUTP
IN3P
IN3M
0.1 ꢀF
AMIC3
OUTM
VSS
GND
0.1 ꢀF
Thermal Pad
(VSS)
1 ꢀF
1 ꢀF
GND
GND
VDD
OUTP
IN4P
IN4M
AMIC4
OUTM
VSS
0.1 ꢀF
1 ꢀF
GND
Host
Processor
LOW/HIGH Pin Selector
图 48. Four-Channel Analog Microphone Recording Diagram for 3.3-V AVDD Operation
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Typical Application (接下页)
8.2.1 Design Requirements
表 21 lists the design parameters for this application.
表 21. Design Parameters
KEY PARAMETER
SPECIFICATION: 3.3-V AVDD OPERATION
AVDD
3.3 V
AVDD supply current consumption
IOVDD
> 23 mA (PLL on, four-channel recording, fS = 48 kHz)
1.8 V or 3.3 V
Maximum MICBIAS current
10 mA (MICBIAS voltage is the same as VREF)
8.2.2 Detailed Design Procedure
This section describes the necessary steps to configure the PCM1840 for this specific application. The following
steps provide a sequence of items that must be executed in the time between powering the device up and
reading data from the device or transitioning from one mode to another mode of operation.
1. Apply power to the device:
a. Power-up the IOVDD and AVDD power supplies, keeping the SHDNZ pin voltage low
b. The device now goes into hardware shutdown mode (ultra-low-power mode < 1 µA)
2. Transition from hardware shutdown mode to active mode whenever required for the recording operation:
a. Connect the MSZ, FMT0, and FMT1 pins voltage low to configure the device in 4-channel TDM slave
mode
b. Release SHDNZ only when the IOVDD and AVDD power supplies settle to the steady-state operating
voltage
c. Apply FSYNC and BCLK with the desired output sample rates and the BCLK to FSYNC ratio
This specific step can be done at any point in the sequence after step a
See the Phase-Locked Loop (PLL) and Clock Generation section for supported sample rates and the
BCLK to FSYNC ratio
d. The device recording data are now sent to the host processor via the TDM audio serial data bus
3. Assert the SHDNZ pin low to enter hardware shutdown mode (again) at any time
4. Follow step 2 onwards to exit hardware shutdown mode (again)
28
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PCM1840
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8.2.3 Application Curves
Measurements are done on the EVM by feeding the device analog input signal using audio precision and with a
3.3-V AVDD supply.
0
-20
-60
-70
Channel-1 : DRE enabled
Channel-2 : DRE enabled
Channel-3 : DRE enabled
Channel-4 : DRE enabled
Channel-1 : DRE enabled
Channel-2 : DRE enabled
Channel-3 : DRE enabled
Channel-4 : DRE enabled
-40
-80
-60
-80
-90
-100
-120
-140
-160
-180
-200
-100
-110
-120
-130
-130
-115
-100
-85
-70
-55
-40
-25
-10
0
20
50
100
500
1000
5000 10000 20000
D212
Input Amplitude (dB)
Frequency (Hz)
TDH2D0+2
图 50. THD+N vs Input Amplitude With DRE Enabled
图 49. FFT With a –60-dBr Input With DRE Enabled
0
-60
Channel-1 : DRE disabled
Channel-2 : DRE disabled
Channel-3 : DRE disabled
Channel-4 : DRE disabled
Channel-1 : DRE disabled
Channel-2 : DRE disabled
Channel-3 : DRE disabled
Channel-4 : DRE disabled
-20
-40
-70
-80
-60
-80
-90
-100
-120
-140
-160
-180
-200
-100
-110
-120
-130
-130
-115
-100
-85
-70
-55
-40
-25
-10
0
20
50
100
500
1000
5000 10000 20000
D212
Input Amplitude (dB)
Frequency (Hz)
TDH2D0+2
图 52. THD+N vs Input Amplitude With DRE Disabled
图 51. FFT With a –60-dBr Input With DRE Disabled
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9 Power Supply Recommendations
The power-supply sequence between the IOVDD and AVDD rails can be applied in any order. However, keep
the SHDNZ pin low until the IOVDD supply voltage settles to a stable and supported operating voltage range.
After all supplies are stable, set the SHDNZ pin high to initialize the device. Assert the SHDNZ pin high only
when all hardware control pins (MSZ, MD0, MD1, FMT0, and FMT1) are driven to the voltage level for the device
desired mode of operation.
For the supply power-up requirement, t1 and t2 must be at least 100 µs. For the supply power-down requirement,
t3 and t4 must be at least 10 ms. This timing (as shown in 图 53) allows the device to ramp down the volume on
the record data, power down the analog and digital blocks, and put the device into hardware shutdown mode.
AVDD
t1
t3
IOVDD
SHDNZ
t4
t2
图 53. Power-Supply Sequencing Requirement Timing Diagram
Make sure that the supply ramp rate is slower than 1 V/µs and that the wait time between a power-down and a
power-up event is at least 100 ms.
The PCM1840 supports a single AVDD supply operation by integrating an on-chip digital regulator, DREG, and
an analog regulator, AREG. However, if the AVDD voltage is less than 1.98 V in the system, then short the
AREG and AVDD pins onboard.
30
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PCM1840
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ZHCSL25 –APRIL 2019
10 Layout
10.1 Layout Guidelines
Each system design and printed circuit board (PCB) layout is unique. The layout must be carefully reviewed in
the context of a specific PCB design. However, the following guidelines can optimize the device performance:
•
Connect the thermal pad to ground. Use a via pattern to connect the device thermal pad, which is the area
directly under the device, to the ground planes. This connection helps dissipate heat from the device.
•
•
The decoupling capacitors for the power supplies must be placed close to the device pins.
Route the analog differential audio signals differentially on the PCB for better noise immunity. Avoid crossing
digital and analog signals to prevent undesirable crosstalk.
•
•
•
•
•
The device internal voltage references must be filtered using external capacitors. Place the filter capacitors
near the VREF pin for optimal performance.
Directly tap the MICBIAS pin to avoid common impedance when routing the biasing or supply traces for
multiple microphones to avoid coupling across microphones.
Directly short the VREF and MICBIAS external capacitors ground terminal to the AVSS pin without using any
vias for this connection trace.
Place the MICBIAS capacitor (with low equivalent series resistance) close to the device with minimal trace
impedance.
Use ground planes to provide the lowest impedance for power and signal current between the device and the
decoupling capacitors. Treat the area directly under the device as a central ground area for the device, and
all device grounds must be connected directly to that area.
10.2 Layout Example
Audio output interface connections
1 : AVDD
18 : MD0
17 : MSZ
2 : AREG
3 : VREF
4 : AVSS
16 : FMT0
15 : FMT1
14 : SHDNZ
13 : IN4M
5 : MICBIAS
6 : IN1P
Audio input signal connections
图 54. Example Layout
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11 器件和文档支持
11.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.2 社区资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.3 商标
Burr-Brown, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
32
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PACKAGE OPTION ADDENDUM
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19-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PCM1840IRTWR
PCM1840IRTWT
ACTIVE
ACTIVE
WQFN
WQFN
RTW
RTW
24
24
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
PCM1840
PCM1840
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
19-Aug-2021
Addendum-Page 2
GENERIC PACKAGE VIEW
RTW 24
4 x 4, 0.5 mm pitch
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224801/A
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