PCM2707C_15 [TI]
PCM270xC Stereo Audio DAC With USB Interface, Single-Ended Headphone Output and S/PDIF Output;
| 型号： | PCM2707C_15 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | PCM270xC Stereo Audio DAC With USB Interface, Single-Ended Headphone Output and S/PDIF Output PC 光电二极管 |
| 文件： | 总47页 (文件大小：1138K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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PCM2704C, PCM2705C, PCM2706C, PCM2707C
Burr-Brown Audio
SBFS036B –MAY 2015–REVISED AUGUST 2015
PCM270xC Stereo Audio DAC With USB Interface, Single-Ended Headphone Output and
S/PDIF Output
1 Features
2 Applications
1
•
On-Chip USB Interface:
•
•
•
•
•
USB Headphones
USB Audio Speaker
–
–
–
No Dedicated Device Driver Needed
Full-Speed Transceivers
USB CRT/LCD Monitor
USB Audio Interface Box
USB-Featured Consumer Audio Product
Fully Compliant With USB 2.0 Specification
–
USB 1.1 Descriptors With USB Audio Class
Support
3 Description
–
–
–
–
Certified by USB-IF
The PCM270xC are TI's single-chip USB stereo
audio digital-to-analog converters (DACs) with USB
2.0 compliant full-speed protocol controller and
S/PDIF. The USB-protocol controller works with no
software code, but USB descriptors can be modified
in some areas (for example, vendor ID/product ID)
through the use of an external ROM (PCM2704C and
PCM2706C) or serial peripheral interface (SPI)
(PCM2705C and PCM2707C). The PCM270xC also
employ SpAct™ architecture, TI's unique system that
recovers the audio clock from USB packet data. On-
chip analog phase-locked loops (PLLs) with SpAct
enable playback with low clock jitter.
Partially Programmable Descriptors
Adaptive Isochronous Transfer for Playback
Bus-Powered or Self-Powered Operation
•
•
Sampling Rates: 32 kHz, 44.1 kHz, and 48 kHz
On-Chip Clock Generator With Single 12-MHz
Clock Source
•
Single Power Supply:
–
–
Bus-Powered: 5 V, Typical (VBUS
)
Self-Powered: 3.3 V, Typical
•
16-Bit Delta-Sigma Stereo DAC
–
Analog Performance at 5 V (Bus-Powered),
3.3 V (Self-Powered):
Device Information(1)
PART NUMBER
PCM2704C
PACKAGE
BODY SIZE (NOM)
–
THD + N: 0.006% RL > 10 kΩ, Self-
Powered
SSOP (28)
5.30 mm × 10.20 mm
PCM2705C
–
–
–
–
THD + N: 0.025% RL = 32 Ω
SNR = 98 dB
PCM2706C
TQFP (32)
7.00 mm × 7.00 mm
PCM2707C
Dynamic Range: 98 dB
PO = 12 mW, RL = 32 Ω
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
–
Oversampling Digital Filter
Block Diagram
–
–
Passband Ripple = ±0.04 dB
Stop-Band Attenuation = –50 dB
USB
–
–
Single-Ended Voltage Output
Analog LPF Included
Line Out
S/PDIF
I2S
HID Controls
External ROM
SPI
PCM2704C/5C/6C/7C
•
Multiple Functions:
–
Up to Eight Human Interface Device (HID)
Interfaces (Model and Setting Dependent)
PGND
AGNDR
VCCL
VCCR
VCCP
–
–
–
–
–
Suspend Flag
VDD
AGNDL
ZGND
DGND
S/PDIF Out With SCMS
External ROM Interface (PCM2704C/6C)
Serial Programming Interface (PCM2705C/7C)
I2S Interface (Selectable on PCM2706C/7C)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
PCM2704C, PCM2705C, PCM2706C, PCM2707C
SBFS036B –MAY 2015–REVISED AUGUST 2015
www.ti.com
Table of Contents
9.1 Overview ................................................................. 18
9.2 Functional Block Diagrams ..................................... 18
9.3 Feature Description................................................. 20
9.4 Device Functional Modes........................................ 25
9.5 Programming........................................................... 26
9.6 Register Maps......................................................... 29
10 Application and Implementation........................ 30
10.1 Application Information.......................................... 30
10.2 Typical Application ............................................... 30
11 Power Supply Recommendations ..................... 37
12 Layout................................................................... 37
12.1 Layout Guidelines ................................................. 37
12.2 Layout Example .................................................... 37
13 Device and Documentation Support ................. 40
13.1 Documentation Support ........................................ 40
13.2 Related Links ........................................................ 40
13.3 Community Resources.......................................... 40
13.4 Trademarks........................................................... 40
13.5 Electrostatic Discharge Caution............................ 40
13.6 Glossary................................................................ 40
1
2
3
4
5
6
7
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 4
Specifications......................................................... 7
7.1 Absolute Maximum Ratings ...................................... 7
7.2 ESD Ratings.............................................................. 7
7.3 Recommended Operating Conditions ...................... 8
7.4 Thermal Information: PCM2704C, PCM2705C......... 8
7.5 Thermal Information: PCM2706C, PCM2707C......... 8
7.6 Electrical Characteristics: PCM2704CDB,
PCM2705CDB, PCM2706CPJT, PCM2707CPJT ..... 9
7.7 Audio Interface Timing Characteristics ................... 11
7.8 Audio Clock Timing Characteristics ........................ 11
7.9 External ROM Read Interface Timing
Characteristics ......................................................... 11
7.10 SPI Timing Characteristics.................................... 12
7.11 Typical Characteristics.......................................... 14
Parameter Measurement Information ................ 17
Detailed Description ............................................ 18
8
9
14 Mechanical, Packaging, and Orderable
Information ........................................................... 40
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (July 2012) to Revision B
Page
•
Added Handling Ratings table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section ............................................................... 1
Changes from Original (August 2011) to Revision A
Page
•
•
•
Changed product status from Mixed Status to Production Data ............................................................................................ 1
Changed Features section to show full compliance with USB2.0 Specification (but still using USB1.1 descriptors)............ 1
Changed Description section to show USB2.0 compliance (USB1.1 was absorbed into 2.0 specification) .......................... 1
2
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PCM2704C, PCM2705C, PCM2706C, PCM2707C
www.ti.com
SBFS036B –MAY 2015–REVISED AUGUST 2015
5 Device Comparison Table
FEATURE
PCM2704C
3.3, 5
PCM2705C
3.3, 5
PCM2706C
3.3, 5
PCM2707C
3.3, 5
Supply Voltage (V)
Control Interface
HID
HID, SPI
HID, SPI
HID, SPI
S/PDIF Output
HP Output
Ext. ROM I/F
S/PDIF Output
HP Output
Ext. ROM I/F
S/PDIF Output
HP Output
S/PDIF Output
HP Output
Additional Features
Package Group
SSOP
SSOP
TQFP
TQFP
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PCM2704C, PCM2705C, PCM2706C, PCM2707C
SBFS036B –MAY 2015–REVISED AUGUST 2015
www.ti.com
6 Pin Configuration and Functions
PCM2704C, PCM2705C DB Package
28-Pin SSOP
Top View
XTO
CK
1
2
3
4
5
6
7
8
9
28 XTI
27 SSPND
26 TEST0
25 TEST1
DT
PSEL
DOUT
DGND
VDD
24
HID2/MD
23 HID1/MC
22 HID0/MS
21 HOST
20 VCCP
D-
D+
VBUS 10
ZGND 11
AGNDL 12
VCCL 13
19 PGND
18 VCOM
17 AGNDR
16 VCCR
VOUTL
14
15 VOUT
R
Pin Functions: DB Package (PCM2704C/PCM2705C)
PIN
NAME
AGNDL
DESCRIPTION
NO.
12
17
2
I/O
—
—
O
Analog ground for headphone amplifier of L-channel
AGNDR
CK
Analog ground for headphone amplifier of R-channel
Clock output for external ROM (PCM2704C). Must be left open (PCM2705C).
D+
9
I/O USB differential input/output plus(1)
I/O USB differential input/output minus(1)
D–
8
DGND
DOUT
DT
6
—
O
Digital ground
S/PDIF output
5
3
I/O Data input/output for external ROM (PCM2704C). Must be left open with pullup resistor (PCM2705C).(1)
HID0/MS
HID1/MC
HID2/MD
22
23
24
I
I
I
HID key state input (mute), active high (PCM2704C). MS input (PCM2705C)(2)
HID key state input (volume up), active high (PCM2704C). MC input (PCM2705C)(2)
HID key state input (volume down), active high (PCM2704C). MD input (PCM2705C)(2)
Host detection during self-powered operation (connect to VBUS). Max power select during bus-powered
operation (low: 100 mA, high: 500 mA).(3)
HOST
21
I
PGND
PSEL
SSPND
TEST0
TEST1
VBUS
19
4
—
I
Analog ground for DAC, OSC, and PLL
Power source select (low: self-power, high: bus-power)(1)
Suspend flag, active low (low: suspend, high: operational)
Test pin. Must be set high(1)
27
26
25
10
13
O
I
I
Test pin. Must be set high(1)
—
—
Connect to USB power (VBUS) for bus-powered operation. Connect to VDD for self-powered operation.
Analog power supply for headphone amplifier of L-channel(4)
VCCL
(1) LV-TTL level.
(2) LV-TTL level with internal pulldown
(3) LV-TTL level, 5-V tolerant
(4) Connect decoupling capacitor to GND. Supply 3.3 V for self-powered applications.
4
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SBFS036B –MAY 2015–REVISED AUGUST 2015
Pin Functions: DB Package (PCM2704C/PCM2705C) (continued)
PIN
NAME
VCCP
DESCRIPTION
Analog power supply for DAC, OSC, and PLL(4)
Analog power supply for headphone amplifier of R-channel(4)
Common voltage for DAC (VCCP/2). Connect decoupling capacitor to PGND.
Digital power supply(4)
NO.
20
16
18
7
I/O
—
—
—
—
O
VCCR
VCOM
VDD
VOUT
VOUT
XTI
L
14
15
28
1
DAC analog output for L-channel
R
O
DAC analog output for R-channel
Crystal oscillator input(1)
I
XTO
O
Crystal oscillator output
ZGND
11
—
Ground for internal regulator
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PCM2704C, PCM2705C, PCM2706C, PCM2707C
SBFS036B –MAY 2015–REVISED AUGUST 2015
www.ti.com
PCM2706C, PCM2707C PJT Package
32-Pin TQFP
Top View
32 31 30 29 28 27 26 25
PGND
VCCP
VBUS
23 D+
1
2
3
4
5
6
7
8
24
HOST
22
21
20
D-
FUNC3
VDD
FUNC0
HID0/MS
HID1/MC
HID2/MD
DGND
19 FUNC1
18
17 DOUT
FUNC2
9
10 11 12 13 14 15 16
Pin Functions: PJT Package (PCM2706C/PCM2707C)
PIN
NAME
AGNDL
DESCRIPTION
NO.
26
31
14
23
22
20
17
15
9
I/O
—
—
O
Analog ground for headphone amplifier of L-channel
AGNDR
CK
Analog ground for headphone amplifier of R-channel
Clock output for external ROM (PCM2706C). Must be left open (PCM2707C).
D+
I/O USB differential input/output plus(1)
I/O USB differential input/output minus(1)
D–
DGND
DOUT
DT
—
O
Digital ground
S/PDIF output/I2S data output
I/O Data input/output for external ROM (PCM2706C). Must be left open with pullup resistor (PCM2707C).(1)
Function select (low: I2S data output, high: S/PDIF output)(2)
FSEL
I
FUNC0
FUNC1
FUNC2
FUNC3
HID0/MS
HID1/MC
HID2/MD
5
I/O HID key state input (next track), active high (FSEL = 1). I2S LR clock output (FSEL = 0).(3)
I/O HID key state input (previous track), active high (FSEL = 1). I2S bit clock output (FSEL = 0).(3)
I/O HID key state input (stop), active high (FSEL = 1). I2S system clock output (FSEL = 0).(3)
19
18
4
I
I
I
I
HID key state input (play/pause), active high (FSEL = 1). I2S data input (FSEL = 0).(3)
HID key state input (mute), active high (PCM2706C). MS input (PCM2707C).(3)
HID key state input (volume up), active high (PCM2706C). MC input (PCM2707C).(3)
HID key state input (volume down), active high (PCM2706C). MD input (PCM2707C).(3)
6
7
8
Host detection during self-powered operation (connect to VBUS). Max power select during bus-powered
operation. (low: 100 mA, high: 500 mA).(4)
HOST
3
I
PGND
PSEL
1
—
I
Analog ground for DAC, OSC, and PLL
16
11
10
Power source select (low: self-power, high: bus-power)(1)
Suspend flag, active low (low: suspend, high: operational)
Test pin. Must be set high(1)
SSPND
TEST
O
I
(1) LV-TTL level
(2) LV-TTL level.
(3) LV-TTL level with internal pulldown
(4) LV-TTL level, 5-V tolerant
6
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SBFS036B –MAY 2015–REVISED AUGUST 2015
Pin Functions: PJT Package (PCM2706C/PCM2707C) (continued)
PIN
NAME
VBUS
DESCRIPTION
NO.
24
27
2
I/O
—
—
—
—
—
—
O
Connect to USB power (VBUS) for bus-powered operation. Connect to VDD for self-powered operation.
Analog power supply for headphone amplifier of L-channel(5)
Analog power supply for DAC, OSC, and PLL(5)
Analog power supply for headphone amplifier of R-channel(5)
Common voltage for DAC (VCCP/2). Connect decoupling capacitor to PGND.
Digital power supply(5)
VCCL
VCCP
VCCR
VCOM
VDD
30
32
21
28
29
12
13
25
VOUT
VOUT
XTI
L
DAC analog output for L-channel
R
O
DAC analog output for R-channel
Crystal oscillator input(1)
I
XTO
O
Crystal oscillator output
ZGND
—
Ground for internal regulator
(5) Connect decoupling capacitor to GND. Supply 3.3 V for self-powered applications.
7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range unless otherwise noted.
(1)
MIN
–0.3
–0.3
MAX
6.5
4
UNIT
V
VBUS
Supply voltage
VCCP, VCCL, VCCR, VDD
V
Supply voltage
VCCP, VCCL, VCCR, VDD
differences
±0.1
V
Ground voltage
PGND, AGNDL, AGNDR, DGND, ZGND
differences
±0.1
6.5
V
V
HOST
–0.3
–0.3
D+, D–, HID0/MS, HID1/MC, HID2/MD, XTI, XTO, DOUT,
Digital input voltage
SSPND, CK, DT, PSEL, FSEL, TEST, TEST0, TEST1, FUNC0,
FUNC1, FUNC2, FUNC3
(VDD + 0.3) < 4
V
VCOM
–0.3
–0.3
–0.3
±10
(VCCP + 0.3) < 4
(VCCR + 0.3) < 4
(VCCL + 0.3) < 4
V
V
Analog input voltage
VOUT
R
L
VOUT
V
Input current (any pins except supplies)
Ambient temperature under bias
Junction temperature
mA
°C
°C
°C
°C
–40
125
150
260
150
Package temperature (IR reflow, peak)
Storage temperature, Tstg
–55
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
MAX
±3000
±1500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2)
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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SBFS036B –MAY 2015–REVISED AUGUST 2015
www.ti.com
7.3 Recommended Operating Conditions
Over operating free-air temperature range.
MIN
4.35
3
NOM
MAX
5.25
3.6
UNIT
VBUS
Supply voltage
5
V
VCCP, VCCL, VCCR, VDD
3.3
Digital input logic level
TTL-compatible
Digital input clock frequency
Analog output load resistance
Analog output load capacitance
Digital output load capacitance
Operating free-air temperature, TA
11.994
16
12
32
12.006
MHz
Ω
100
20
pF
pF
°C
–25
85
7.4 Thermal Information: PCM2704C, PCM2705C
PCM2704C, PCM2705C
THERMAL METRIC(1)
DB (SSOP)
28 PINS
68.2
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
27.2
29.5
Junction-to-top characterization parameter
Junction-to-board characterization parameter
2.7
ψJB
29.1
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5 Thermal Information: PCM2706C, PCM2707C
PCM2706C, PCM2707C
THERMAL METRIC(1)
PJT (TQFP)
32 PINS
68.2
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
27.2
29.5
Junction-to-top characterization parameter
Junction-to-board characterization parameter
2.7
ψJB
29.1
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
8
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SBFS036B –MAY 2015–REVISED AUGUST 2015
7.6 Electrical Characteristics: PCM2704CDB, PCM2705CDB, PCM2706CPJT, PCM2707CPJT
All specifications at TA = 25°C, VBUS = 5 V, ƒS = 44.1 kHz, ƒIN = 1 kHz, and 16-bit data (unless otherwise noted). For the Host
interface, apply USB revision 1.1, full-speed. For audio data format, use USB isochronous data format.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT LOGIC
Input logic high level
2
2
3.3
5.5
VIH
VIL
IIH
VDC
VDC
μA
Input logic high level(1)
Input logic low level
–0.3
–0.3
0.8
Input logic low level(1)
Input logic high current(2)
Input logic high current
Input logic low current(2)
Input logic low current
0.8
VIN = 3.3 V
±10
100
±10
±10
VIN = 3.3 V
VIN = 0 V
VIN = 0 V
65
IIL
μA
OUTPUT LOGIC
Output logic high level(3)
IOH = –2 mA
IOH = –2 mA
IOL = 2 mA
IOL = 2 mA
2.8
2.4
VOH
VDC
Output logic high level
Output logic low level(3)
Output logic low level
0.3
0.4
VOL
VDC
CLOCK FREQUENCY
Input clock frequency, XTI
11.994
12
12.006
MHz
kHz
32
44.1
48
ƒS
Sampling frequency
DAC CHARACTERISTICS
Resolution
16
bits
Audio data channel
DC ACCURACY
1, 2
channel
Gain mismatch, channel-to-channel
±2
±2
±3
±8 % of FSR
±8 % of FSR
±6 % of FSR
Gain error
Bipolar zero error
(4)
DYNAMIC PERFORMANCE
RL > 10 kΩ, self-powered,
VOUT = 0 dB
0.006%
0.012%
0.025%
2%
0.01%
0.02%
(5)
Line
THD + Total harmonic
RL > 10 kΩ, bus-powered,
VOUT = 0 dB
N
distortion + noise
RL = 32 Ω, self- or bus-
powered, VOUT = 0 dB
Headphone
THD +
N
Total harmonic distortion + noise
VOUT = –60 dB
Dynamic range
EIAJ, A-weighted
EIAJ, A-weighted
90
90
60
98
98
70
dB
dB
dB
SNR
Signal-to-noise ratio
Channel separation
(1) HOST pin.
(2) D+, D–, HOST, TEST, TEST0, TEST1, DT, PSEL, FSEL, XTI pins.
(3) FUNC0, FUNC1, and FUNC2 pins.
(4) ƒIN = 1 kHz, using the System Two Cascade™ audio measurement system by Audio Precision® in RMS mode with a 20-kHz low-pass
filter (LPF) and 400-Hz high-pass filter (HPF).
(5) THD + N performance varies slightly, depending on the effective output load, including dummy load R7 and R8 in Figure 35.
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SBFS036B –MAY 2015–REVISED AUGUST 2015
www.ti.com
Electrical Characteristics: PCM2704CDB, PCM2705CDB, PCM2706CPJT,
PCM2707CPJT (continued)
All specifications at TA = 25°C, VBUS = 5 V, ƒS = 44.1 kHz, ƒIN = 1 kHz, and 16-bit data (unless otherwise noted). For the Host
interface, apply USB revision 1.1, full-speed. For audio data format, use USB isochronous data format.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG OUTPUT
0.55 VCCL
0.55 VCCR
Output voltage
VPP
Center voltage
0.5 VCCP
V
kΩ
Ω
Line
AC-coupling
10
16
Load impedance
Headphone
AC-coupling
–3 dB
32
140
kHz
dB
LPF frequency response
ƒ = 20 kHz
–0.1
DIGITAL FILTER PERFORMANCE
Passband
0.454 ƒS
±0.04
Hz
Hz
dB
dB
s
Stop band
0.546 ƒS
–50
Passband ripple
Stop band attenuation
Delay time
20 / ƒS
POWER SUPPLY REQUIREMENTS
VBUS
Bus-powered
4.35
3
5
3.3
23
5.25
3.6
Voltage range
VDC
VCCP, VCCL, VCCR, VDD Self-powered
Line
DAC operation
30
mA
μA
Supply current
Headphone
Line/headphone
Line
DAC operation (RL = 32 Ω)
35
46
(6)
Suspend mode
150
76
190
108
166
684
158
242
998
DAC operation
mW
μW
mW
Power dissipation
(self-powered)
Headphone
Line/headphone
Line
DAC operation (RL = 32 Ω)
116
495
115
175
750
(6)
Suspend mode
DAC operation
Power dissipation
(bus-powered)
Headphone
Line/headphone
DAC operation (RL = 32 Ω)
(6)
Suspend mode
μW
Internal power-
supply voltage
VCCP, VCCL, VCCR, VDD Bus-powered
3.2
3.35
3.5
VDC
(7)
TEMPERATURE RANGE
Operating temperature
–25
85
°C
(6) In USB suspended state
(7) VDD, VCCP, VCCL, VCCR pins. These pins work as output pins of internal power supply for bus-powered operation.
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7.7 Audio Interface Timing Characteristics
Load capacitance of LRCK, BCK, and DOUT is 20 pF. For timing diagrams, see Figure 1 and Figure 2.
MIN
MAX
UNIT
ns
t(BCY)
t(BCH)
t(BCL)
t(BL)
BCK pulse cycle time
300
100
100
–20
–20
–20
20
BCK pulse duration, high
BCK pulse duration, low
ns
ns
LRCK delay time from BCK falling edge
DOUT delay time from BCK falling edge
DOUT delay time from LRCK edge
DIN setup time
40
40
40
ns
t(BD)
t(LD)
t(DS)
t(DH)
ns
ns
ns
DIN hold time
20
ns
7.8 Audio Clock Timing Characteristics
Load capacitance is 20 pF. For timing diagrams, see Figure 3.
MIN
–5
MAX
10
UNIT
ns
t(SLL), t(SLH)
t(SBL), t(SBH)
LRCK delay time from SYSCK rising edge
BCK delay time from SYSCK rising edge
–5
10
ns
7.9 External ROM Read Interface Timing Characteristics
For timing diagrams, see Figure 4.
MIN
MAX
UNIT
kHz
μs
ƒ(CK)
t(BUF)
t(LOW)
t(HI)
CK clock frequency
100
Bus free time between a STOP and a START condition
Low period of the CK clock
4.7
4.7
4
μs
High period of the CK clock
μs
t(RS-SU)
Setup time for START/repeated START condition
4.7
μs
t(S-HD)
t(RS-HD)
Hold time for START/repeated START condition
4
μs
t(D-SU)
t(D-HD)
t(CK-R)
t(CK-F)
t(DT-R)
t(DT-F)
t(P-SU)
CB
Data setup time
250
0
ns
ns
ns
ns
ns
ns
μs
pF
V
Data hold time
900
1000
1000
1000
1000
Rise time of CK signal
20 + 0.1 CB
20 + 0.1 CB
20 + 0.1 CB
20 + 0.1 CB
4
Fall time of CK signal
Rise time of DT signal
Fall time of DT signal
Setup time for STOP condition
Capacitive load for DT and CK lines
Noise margin at high level for each connected device (including hysteresis)
400
VNH
0.2 VDD
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7.10 SPI Timing Characteristics
For timing diagrams, see Figure 5.
MIN
100
50
MAX
UNIT
ns
t(MCY)
t(MCL)
t(MCH)
t(MHH)
t(MLS)
t(MLH)
t(MDH)
t(MDS)
MC pulse cycle time
MC low-level time
MC high-level time
MS high-level time
MS falling edge to MC rising edge
MS hold time
ns
50
ns
100
20
ns
ns
20
ns
MD hold time
15
ns
MD setup time
20
ns
SYSCK
(256 fS)
1/fS
LRCK
L-Channel
R-Channel
BCK
(64 fS)
DOUT
DIN
1
1
2
3
3
14 15 16
LSB
1
1
2
3
3
14 15 16
LSB
1
2
MSB
2
MSB
2
MSB
2
14 15 16
14 15 16
1
Figure 1. Audio Data Interface Format
50% of VDD
LRCK (Output)
BCK (Output)
DOUT (Output)
t(BCH)
t(BCL)
t(BL)
50% of VDD
t(BCY)
t(BD)
t(LD)
50% of VDD
t(DS)
t(DH)
50% of VDD
DIN (Input)
Figure 2. Audio Interface Timing
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SYSCK
(Output)
t(SLL)
t(SLH)
LRCK
(Output)
t(SBL)
t(SBH)
BCK
(Output)
Figure 3. Audio Clock Timing
Repeated
Start
Start
Stop
t(D-HD)
t(DT-F)
t(P-SU)
t(D-SU)
t(BUF)
t(DT-R)
DT
t(CK-R)
t(RS-HD)
t(LOW)
CK
t(S-HD)
t(HI)
t(RS-SU)
t(CK-F)
Figure 4. External ROM Read Interface Timing Requirements
t(MHH)
50% of VDD
MS
t(MCL)
t(MLS)
t(MCH)
t(MLH)
50% of VDD
MC
MD
t(MCY)
LSB
50% of VDD
t(MDS)
t(MDH)
Figure 5. SPI Timing Diagram
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7.11 Typical Characteristics
7.11.1 Internal Filter: DAC Digital Interpolation Filter Frequency Response
All specifications at TA = 25°C, VBUS = 5 V, ƒS = 44.1 kHz, ƒIN = 1 kHz, 16-bit data (unless otherwise noted).
0.05
0.04
0.03
0.02
0.01
0
0
-20
-40
-60
-80
-0.01
-0.02
-0.03
-0.04
-0.05
-100
-120
-140
0
0.1
0.2
0.3
0.4
0.5
0
1
2
3
4
Frequency (× fS)
Frequency (× fS)
G002
G001
Figure 7. Passband Ripple
Figure 6. Frequency Response
7.11.2 Internal Filter: DAC Analog Low-Pass Filter Frequency Response
All specifications at TA = 25°C, VBUS = 5 V, ƒS = 44.1 kHz, ƒIN = 1 kHz, 16-bit data (unless otherwise noted).
0
-0.5
-1
0
-20
-40
-60
-80
-1.5
-2
0.01
0.1
1
10
100
1
10
100
1k
10k
Frequency (kHz)
Frequency (kHz)
G003
G004
Figure 8. Passband Characteristics
Figure 9. Stop Band Characteristics
7.11.3 General Characteristics
All specifications at TA = 25°C, VBUS = 5 V, ƒS = 44.1 kHz, ƒIN = 1 kHz, 16-bit data (unless otherwise noted).
0.05
0.04
0.03
0.02
0.01
0
0.05
0.04
0.03
0.02
0.01
0
32 Ω
32 Ω
10 kΩ
10 kΩ
–50
–25
0
25
50
75
100
–50
–25
0
25
50
75
100
Free-Air Temperature (°C)
Free-Air Temperature (°C)
G005
G006
Figure 10. Total Harmonic Distortion + Noise vs Free-Air
Temperature
Figure 11. Total Harmonic Distortion + Noise vs Free-Air
Temperature
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General Characteristics (continued)
All specifications at TA = 25°C, VBUS = 5 V, ƒS = 44.1 kHz, ƒIN = 1 kHz, 16-bit data (unless otherwise noted).
0.05
0.04
0.03
0.02
0.01
0
0.05
0.04
0.03
0.02
0.01
0
32 Ω
32 Ω
10 kΩ
10 kΩ
4
4.5
Supply Voltage (V)
5
5.5
3
3.2
3.3
3.4
3.6
3.1
3.5
Supply Voltage (V)
G007
G008
Figure 12. Total Harmonic Distortion + Noise vs Supply
Voltage
Figure 13. Total Harmonic Distortion + Noise vs Supply
Voltage
0.05
0.05
0.04
0.03
0.02
0.01
0
0.04
0.03
0.02
0.01
0
32 Ω
32 Ω
10 kΩ
10 kΩ
30
35
40
Sampling Frequency (kHz)
45
50
30
35
40
45
50
Sampling Frequency (kHz)
G009
G010
Figure 14. Total Harmonic Distortion + Noise vs Sampling
Frequency
Figure 15. Total Harmonic Distortion + Noise vs Sampling
Frequency
105
103
101
105
103
101
99
99
Dynamic Range
Dynamic Range
97
97
SNR
SNR
–25
95
95
–50
–25
0
25
50
75
100
–50
0
25
50
75
100
Free-Air Temperature (°C)
Free-Air Temperature (°C)
G011
G012
Figure 16. Dynamic Range and SNR vs Free-Air
Temperature
Figure 17. Dynamic Range and SNR vs Free-Air
Temperature
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General Characteristics (continued)
All specifications at TA = 25°C, VBUS = 5 V, ƒS = 44.1 kHz, ƒIN = 1 kHz, 16-bit data (unless otherwise noted).
105
103
101
99
105
103
101
99
Dynamic Range
Dynamic Range
SNR
97
97
SNR
4.5
95
95
4
5
5.5
3
3.2
3.3
3.4
3.6
3.1
3.5
Supply Voltage (V)
Supply Voltage (V)
G013
G014
Figure 18. Dynamic Range and SNR vs Supply Voltage
Figure 19. Dynamic Range and SNR vs Supply Voltage
105
105
103
101
99
103
101
99
Dynamic Range
Dynamic Range
97
97
SNR
SNR
35
95
95
30
40
Sampling Frequency (kHz)
45
50
30
35
40
Sampling Frequency (kHz)
45
50
G015
G016
Figure 20. Dynamic Range and SNR vs Sampling
Frequency
Figure 21. Dynamic Range and SNR vs Sampling
Frequency
200
150
100
50
200
150
100
50
0
0
-40
-20
0
20
40
60
80
100
4
4.5
Supply Voltage (V)
5
5.5
Free-Air Temperature (°C)
G018
G017
Figure 23. Suspend Current vs Free-Air Temperature
Figure 22. Suspend Current vs Supply Voltage
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General Characteristics (continued)
All specifications at TA = 25°C, VBUS = 5 V, ƒS = 44.1 kHz, ƒIN = 1 kHz, 16-bit data (unless otherwise noted).
0
0
-20
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-100
-120
-140
0
20
40
60
80
100
120
0
5
10
15
20
Frequency (kHz)
Frequency (kHz)
G020
G019
Figure 25. Output Spectrum (–60 dB, N = 8192)
Figure 24. Output Spectrum (–60 dB, N = 8192)
8 Parameter Measurement Information
All parameters are measured according to the conditions described in Specifications.
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9 Detailed Description
9.1 Overview
The PCM2704C/5C/6C/7C is a stereo audio digital-to-analog converter (DAC) with USB connection capability
and a S/PDIF digital interface.
The PCM2704C/5C/6C/7C can be used in self-powered and bus-powered modes. These devices meet the
requirements of USB2.0 standard connection. The PCM2704C/5C/6C/7C has digital input from the USB port.
The PCM2704C/5C provides two different paths for the audio data, one of which goes to the digital S/PDIF
output, and the other to the analog output through the DAC. The PCM2706C/7C provides three different paths
for the audio data; to the digital S/PDIF output, to the analog output through the DAC, and leading the audio data
to the I2S digital output (the I2S path is selectable trough FSEL pin 9).
The PCM2704C has 3 external interrupts (HID) which control the Mute, Volume Up, and Volume Down; these
control inputs are active High. The PCM2706C has 7 external interrupts (I2S/HID control is selectable trough
FSEL pin 9) which control the Mute, Volume Up, Volume Down, Next track, Previous track, Play/Pause, and
Stop; these control inputs are active High. The PCM2704C/5C/6C/7C requires a 12-MHz clock, which can be
provided by an external clock or generated by a built-in crystal resonator.
9.2 Functional Block Diagrams
VCCP
VCCL
VCCR
VDD
PGND
AGNDL
AGNDR
DGND
ZGND
Power
Manager
SSPND
VBUS
5-V to 3.3-V
Voltage Regulator
VCOM
USB
Protocol
Controller
Analog
PLL
VOUTL
DAC
D+
Control
Endpoint
VOUTR
D-
S/PDIF Encoder
DOUT
EEPROM
Interface(1)
CK
ISO-Out
Endpoint
DT
FIFO
Buffer
HOST
HID0/MS
HID1/MC
HID2/MD
Serial Peripheral
Interface(2)
HID
Endpoint
PSEL
TEST0
TEST1
96 MHz
Tracker
(SpAct)
PLL (x 8)
12 MHz
XTO
XTI
(1) Applies to PCM2704CDB
(2) Applies to PCM2705CDB
Figure 26. PCM2704C/PCM2705C
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Functional Block Diagrams (continued)
VCCP
VCCL
VCCR
VDD
PGND
AGNDL
AGNDR
DGND
ZGND
Power
Manager
SSPND
VBUS
5-V to 3.3-V
Voltage Regulator
VCOM
USB
Protocol
Controller
Analog
PLL
VOUTL
DAC
D+
Control
Endpoint
VOUTR
D-
S/PDIF
Encoder
DOUT
DOUT
LRCK
FSEL
FUNC0
FUNC1
FUNC2
FUNC3
I2S
Interface
BCK
SYSCK
DIN
EEPROM
Interface(1)
CK
ISO-Out
Endpoint
DT
FIFO
Buffer
HOST
HID3: Next Track(1)
HID4: Previous Track(1)
HID5: Stop(1)
HID0/MS
HID1/MC
HID2/MD
Serial Peripheral
Interface(2)
HID
Endpoint
HID6: Play/Pause(1)
PSEL
TEST
96 MHz
Tracker
(SpAct)
PLL (x 8)
12 MHz
XTO
XTI
(1) Applies to PCM2706CPJT
(2) Applies to PCM2707CPJT
Figure 27. PCM2706C/PCM2707C
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9.3 Feature Description
9.3.1 Clock and Reset
For both USB and audio functions, the PCM2704C/5C/6C/7C require a 12-MHz (±500 ppm) clock that can be
generated by the onboard oscillator using a 12-MHz crystal resonator. The 12-MHz crystal resonator must be
connected to the XTI pin (pin 28 for the PCM2704C/5C, pin 12 for the PCM2706C/7C) and the XTO pin (pin 1 for
the PCM2704C/5C, pin 13 for the PCM2706C/7C) with one large (1-MΩ) resistor and two small capacitors; the
capacitance of these components depends on the specified load capacitance of the crystal resonator. An
external clock can be supplied from XTI (pin 28 for the PCM2704C/5C, pin 12 for the PCM2706C/7C). If an
external clock is supplied, XTO (pin 1 for the PCM2704C/5C, pin 13 for the PCM2706C/7C) must be left open.
No clock disabling pin is provided; therefore, TI does not recommend to use the external clock supply. SSPND
(pin 27 for the PCM2704C/5C, pin 11 for the PCM2706C/7C) cannot use clock disabling.
The PCM2704C/5C/6C/7C have an internal power-on reset circuit, which works automatically when VDD (pin 7 for
the PCM2704C/5C, pin 21 for the PCM2706C/7C) exceeds 2-V typical (1.6 to 2.4 V), which is equivalent to VBUS
(pin 10 for the PCM2704C/5C, pin 24 for the PCM2706C/7C) exceeding 3-V typical for bus-powered applications.
Approximately 700 μs is required until an internal reset release occurs.
9.3.2 Operation Mode Selection
The PCM2704C/5C/6C/7C have the following mode-select pins.
9.3.2.1 Power Configuration Select/Host Detection
PSEL (pin 4 for the PCM2704C/5C, pin 16 for the PCM2706C/7C) is dedicated to selecting the power source.
This selection affects the configuration descriptor. While in bus-powered operation, the maximum power
consumption from VBUS is determined by the HOST pin (pin 21 for the PCM2704C/5C, pin 3 for the
PCM2706C/7C). For self-powered operation, the HOST pin must be connected to VBUS of the USB bus with a
pulldown resistor to detect attach and detach. (To avoid excessive suspend current, the pulldown should be a
high-value resistor.) Table 1 summarizes the power configuration select options.
Table 1. Power Configuration Select
PSEL
DESCRIPTION
Self-powered
0
1
Bus-powered
HOST
DESCRIPTION
0
1
Detached from USB (self-powered)/100 mA (bus-powered)
Attached to USB (self-powered)/500 mA (bus-powered)
9.3.2.2 Function Select (PCM2706C/7C Only)
FSEL (pin 9) determines the function of the FUNC0 through FUNC3 pins (pins 4, 5, 18, and 19) and DOUT (pin
17). When the I2S interface is required, FSEL must be low. Otherwise, FSEL must be high. Table 2 lists the
functionality of the FUNC0 through FUNC3 pins, based on the FSEL pin.
Table 2. Function Select
FSEL
DOUT
Data out (I2S)
S/PDIF data
FUNC0
LRCK (I2S)
Next track (HID)
FUNC1
BCK (I2S)
Previous track (HID)
FUNC2
SYSCK (I2S)
FUNC3
Data in (I2S)
Play/pause (HID)
0
1
(1)
(1)
(1)
(1)
Stop (HID)
(1) Valid on the PCM2706C only; no function assigned on the PCM2707C.
9.3.3 DAC
The PCM2704C/5C/6C/7C have a DAC that uses an oversampling technique with 128-ƒS, second-order, multi-bit
noise shaping. This technique provides extremely-low quantization noise in the audio band, and the built-in
analog low-pass filter removes the high-frequency components of the noise-shaping signal. The DAC analog
outputs, VOUTL and VOUTR , are sent through the headphone amplifier and can provide 12 mW at 32 Ω as well as
1.8 VPP into a 10-kΩ load.
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9.3.4 Digital Audio Interface: S/PDIF Output
The PCM2704C/5C/6C/7C employ S/PDIF output. Isochronous-out data from the host are encoded to S/PDIF
output DOUT, as well as to DAC analog outputs VOUTL and VOUTR. The interface format and timing follow the
IEC-60958 standard. Monaural data are converted to the stereo format at the same data rate. S/PDIF output is
not supported in the I2S I/F enable mode. The implementation of this feature is optional.
NOTE
It is the responsibility of the user to determine whether or not to implement this feature in
the end application.
9.3.4.1 Channel Status Information
Channel status information is fixed, and includes consumer application, PCM mode, copyright, and digital/digital
converter data. All other bits are fixed as 0s, except for the sample frequency, which is set automatically
according to the data received through the USB.
9.3.4.2 Copyright Management
Digital audio data output is always encoded as original with SCMS control. Only one generation of digital
duplication is allowed.
9.3.5 Digital Audio Interface: I2S Interface Output (PCM2706C/7C)
The PCM2706C and PCM2707C can support the I2S interface, which is enabled by the FSEL pin (pin 9). In the
I2S interface-enabled mode, pins 4, 18, 19, 5, and 17 are assigned as DIN, SYSCK, BCK, LRCK, and DOUT,
respectively. These pins provide digital output/input data in the 16-bit I2S format, which is also accepted by the
internal DAC. Figure 1, Figure 2, and Figure 3 show the I2S interface format and timing. Audio Interface Timing
Characteristics and Audio Clock Timing Characteristics list the audio interface timing and audio clock timing
characteristics, respectively.
9.3.6 Descriptor Data Modification
The descriptor data can be modified through the I2C port by external ROM (PCM2704C/6C) or through the SPI
port by an SPI host such as an MCU (PCM2705C/7C) under a particular configuration of the PSEL and HOST
pins. Setting both the PSEL and the HOST pins high is necessary to modify the descriptor data; the D+ pin
pullup resistor must not be activated before programming the descriptor data through the external ROM or SPI
port is completed. The descriptor data must be sent from an external ROM to the PCM2704C/6C or from the SPI
host to the PCM2705C/7C in LSB first format, with a specified byte order. Additionally, the power attribute and
max power contents must be consistent with the PSEL setting and the power usage from the USB VBUS of the
end application. Therefore, the device does not support descriptor data modification in self-powered configuration
(PSEL = low).
9.3.7 External ROM Descriptor (PCM2704C/6C)
The PCM2704C/6C support an external ROM interface to override internal descriptors. Pin 3 (for the
PCM2704C) or pin 15 (for the PCM2706C) is assigned as DT (serial data), and pin 2 (for the PCM2704C) or pin
14 (for the PCM2706C) is assigned as CK (serial clock) of the I2C interface when using the external ROM
descriptor. Descriptor data are transferred from the external ROM to the PCM2704C/6C through the I2C interface
the first time when the device is activated after a power-on reset. Before completing a read of the external ROM,
the PCM2704C/6C reply with NACK for any USB command request from the host to the device itself. The
descriptor data, which can be in the external ROM, must meet these parameters:
•
•
•
String descriptors must be described in ANSI ASCII code (1 byte for each character).
String descriptors are converted automatically to unicode strings for transmission to the host.
The device address of the external ROM is fixed as 0xA0.
The data bits must be sent from LSB to MSB on the I2C bus. This condition means that each byte of data must
be stored with its bits in reverse order. A read operation is performed at a frequency of XTI/384 (approximately
30 kHz). The power attribute and max power contents must be consistent with the end application circuit
configuration (the PSEL setting and the actual power usage from VBUS of the USB connector); otherwise, it may
cause improper or unexpected PCM2704C/6C operation.
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The data must be stored from address 0x00 and must consist of 57 bytes, according to these listed parameters:
•
•
•
•
•
•
•
Vendor ID (2 bytes)
Product ID (2 bytes)
Product string (16 bytes in ANSI ASCII code)
Vendor string (32 bytes in ANSI ASCII code)
Power attribute (1 byte)
Max power (1 byte)
Auxiliary HID usage ID in report descriptor (3 bytes)
Figure 28 shows the timing for an external ROM read operation. Table 3 summarizes the timing characteristics.
DT
CK
1 - 7
8
9
1 - 8
9
1 - 8
9
9
S
P
Device Address
ACK
DATA
ACK
DATA
ACK
NACK
R/W
R/W: Read operation if ‘1’; otherwise, Write operation
ACK: Acknowledgement of a byte if ‘0’
DATA: 8 bits (1 byte)
Start
Condition
Stop
Condition
NACK: No acknowledgement if ‘1’
Figure 28. External ROM Read Operation
Table 3. External ROM Read Operation Characteristics
M
M
M
S
S
M
S
M
S
M
M
S
Device address
R/W
ACK
DATA
ACK
DATA
ACK
. . .
NACK
P
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9.3.8 External ROM Example
External ROM data (sample set)
0xBB, 0x08, 0x04, 0x27,
0x50, 0x72, 0x6F, 0x64, 0x75, 0x63, 0x74, 0x20, 0x73, 0x74, 0x72, 0x69, 0x6E, 0x67, 0x73, 0x2E,
0x56, 0x65, 0x6E, 0x64, 0x6F, 0x72, 0x20, 0x73, 0x74, 0x72, 0x69, 0x6E, 0x67, 0x73, 0x20, 0x61,
0x72, 0x65, 0x20, 0x70, 0x6C, 0x61, 0x63, 0x65, 0x64, 0x20, 0x68, 0x65, 0x72, 0x65, 0x2E, 0x20,
0x80,
0x7D,
0x0A, 0x93, 0x01
Explanation
Data are stored beginning at address 0x00
Vendor ID: 0x08BB
Product ID: 0x2704
Product string: Product strings (16 bytes)
Vendor string: Vendor strings are placed here (32 bytes, 31 visible characters are followed by 1 space).
Power attribute (bmAttribute): 0x80 (bus-powered)
Max power (maxPower): 0x7D (250 mA)
Auxiliary HID usage ID: 0x0A, 0x93, 0x01 (AL A/V capture)
Note that the data bits must be sent from LSB to MSB on the I2C bus. Therefore, each data byte must be stored
with its bits in reverse order.
9.3.9 Serial Programming Interface (PCM2705C/7C)
The PCM2705C/7C supports a SPI to program the descriptor and to set the HID state. External ROM Descriptor
(PCM2704C/6C) describes descriptor data. Figure 5 shows the SPI timing; SPI Timing Characteristics lists the
respective timing characteristics.
Figure 29 shows the SPI write timing sequence.
(1) Single Write Operation
16 Bits
MS
MC
MD
MSB
LSB
MSB
(2) Continuous Write Operation
16 Bits ? N Frames
MS
MC
MD
MSB
LSB
MSB
LSB
MSB
LSB
N Frames
Figure 29. SPI Write Operation
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9.3.10 USB Host Interface Sequence
9.3.10.1 Power-On, Attach, and Playback Sequence
The PCM2704C/5C/6C/7C are ready for setup when the reset sequence has finished and the USB bus is
attached. After a connection has been established (through the setup process), the PCM2704C/5C/6C/7C are
ready to accept USB audio data. While waiting for the audio data (that is, the device is in an idle state), the
analog output is set to bipolar zero (BPZ).
Upon receiving the audio data, the PCM2704C/5C/6C/7C stores the first audio packet in the internal storage
buffer. The packet contains 1 ms of audio data. The PCM2704C/5C/6C/7C start playing the audio data after
detecting the next subsequent start-of-frame (SOF) packet. Figure 30 shows the initial operation sequence for
the device.
3.3 V (typ)
VDD
0 V
2.0 V (typ)
Bus Reset
Set Configuration
First Audio Data
Second Audio Data
Bus Idle
D+ / D-
SOF
SOF
SOF
SSPND
BPZ
VOUTL
VOUTR
Device Setup
1 ms
700 ms
Internal Reset
Ready for Setup
Ready for Playback
Figure 30. Initial Sequence
9.3.10.2 Play, Stop, and Detach Sequence
When the host finishes or aborts playback, the PCM2704C/5C/6C/7C stop playing after the last audio data output
is complete. Figure 31 shows the play, stop, and detach sequence.
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VBUS
Audio Data
Audio Data
Last Audio Data
D+ / D-
SOF
SOF
SOF
SOF
SOF
VOUTL
VOUTR
1 ms
Detach
Figure 31. Play, Stop, and Detach Sequence
9.3.10.3 Suspend and Resume Sequence
The PCM2704C/5C/6C/7C enter a suspended state after the USB bus has been in a constant idle state for
approximately 5 ms. While the PCM2704C/5C/6C/7C are in this suspended state, the SSPND flag (pin 27 for the
PCM2704C/5C, pin 11 for the PCM2706C/7C) is asserted. The PCM2704C/5C/6C/7C wake up immediately
when detecting a non-idle state on the USB bus. Figure 32 shows the operating sequence for the suspend and
resume process.
Idle
D+ / D-
SSPND
5 ms
Suspend
VOUTL
VOUTR
Active
Active
2.5 ms
Figure 32. Suspend and Resume
9.3.11 Operating Environment
For current information on the PCM2704C/2705C/2706C/2707C operating environments, see the Updated
Operating Environments for PCM270X, PCM290X Applications application report, SLAA374, available through
the TI website at www.ti.com.
9.4 Device Functional Modes
The PCM2903C is a USB-controlled device. The PCM2903C is a digital-to-analog converter (DAC), with digital
input (that goes to a D/A converter) and analog output, alongside the digital path to USB and S/PDIF and I2S
(only in PCM2706C/7C). A wider explanation of these operational modes is shown in Feature Description.
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9.5 Programming
9.5.1 USB Interface
Control data and audio data are transferred to the PCM2704C/5C/6C/7C through the D+ pin (pin 9 for the
PCM2704C/5C, pin 23 for the PCM2706C/7C) and D– pin (pin 8 for the PCM2704C/5C, pin 22 for the
PCM2706C/7C). D+ should be pulled up with a 1.5-kΩ (±5%) resistor. To avoid back voltage in self-powered
operation, the device must not provide power to the pullup resistor on D+ while VBUS of the USB port is inactive.
All data to/from the PCM2704C/5C/6C/7C are transferred at full speed. Table 4 shows the information that is
provided in the device descriptor. Some parts of the device descriptor can be modified through external ROM
(PCM2704C/6C) or SPI (PCM2705C/7C).
Table 4. Device Descriptor
DEVICE DESCRIPTOR
USB revision
DESCRIPTION
1.1 compliant
Device class
0x00 (device defined interface level)
0x00 (not specified)
Device subclass
Device protocol
Max packet size for endpoint 0
Vendor ID
0x00 (not specified)
8 bytes
0x08BB (default value, can be modified)
0x27C4/0x27C5/0x27C6/0x27C7 (These values correspond to the model number, and the value can
be modified.)
Product ID
Device release number
Number of configurations
Vendor strings
1.0 (0x0100)
1
BurrBrown from Texas Instruments (default value, can be modified)
USB AUDIO DAC (default value, can be modified)
Not supported
Product strings
Serial number
Table 5 shows the information contained in the configuration descriptor. Some parts of the configuration
descriptor can be modified through external ROM (PCM2704C/6C) or SPI (PCM2705C/7C).
Table 5. Configuration Descriptor
CONFIGURATION DESCRIPTOR
DESCRIPTION
Interface
Three interfaces
0x80 or 0xC0 (bus-powered or self-powered, depending on PSEL; no remote wake up. This value can
be modified.)
Power attribute
Max power
0x0A, 0x32, or 0xFA (20 mA for self-powered, 100 mA or 500 mA for bus-powered, depending on
PSEL and HOST. This value can be modified.)
Table 6 shows the information contained in the string descriptor. Some parts of the string descriptor can be
modified through external ROM (PCM2704C/6C) or SPI (PCM2705C/7C).
Table 6. String Descriptor
STRING DESCRIPTOR
DESCRIPTION
0
1
2
0x0409
BurrBrown from Texas Instruments (default value, can be modified)
USB AUDIO DAC (default value, can be modified)
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9.5.1.1 Device Configuration
Figure 33 shows the USB audio function topology. The PCM2704C/5C/6C/7C have three interfaces. Each
interface is enabled by different alternative settings.
Endpoint #0
Default
Endpoint
FU
Endpoint #2
(I/F #1)
IT
TID1
OT
TID2
Analog Out
Audio Streaming
Interface
UID3
Standard Audio Control Interface (I/F #0)
Endpoint #5
(I/F #2)
HID Interface
PCM2704C/5C/6C/7C
Figure 33. USB Audio Function Topology
9.5.1.2 Interface Number 0 (Default/Control Interface)
Interface number 0 is the control interface. Setting number 0 is the only possible setting for interface number 0.
Setting number 0 describes the standard audio control interface. The audio control interface consists of a
terminal. The PCM2704C/5C/6C/7C have three terminals:
•
•
•
Input terminal (IT number 1) for isochronous-out stream
Output terminal (OT number 2) for audio analog output
Feature unit (FU number 3) for DAC digital attenuator
Input terminal number 1 is defined as a USB stream (terminal type 0x0101). Input terminal number 1 can accept
two-channel audio streams consisting of left and right channels. Output terminal number 2 is defined as a
speaker (terminal type 0x0301). Feature unit number 3 supports these sound control features:
•
•
Volume control
Mute control
The built-in digital volume controller can be manipulated by an audio-class-specific request from 0 to –64 dB in
steps of 1 dB. Changes are made by incrementing or decrementing one step (that is, 1 dB) for every 1 / ƒS time
interval, until the volume level reaches the requested value. Each channel can be set to a separate value. The
master volume control is not supported. A request to the master volume is stalled and ignored. The built-in digital
mute controller can be manipulated by an audio-class-specific request. A master mute control request is
acceptable. A mute control request to an individual channel is stalled and ignored. The digital volume control
does not affect either the S/PDIF or I2S outputs (PCM2706C/7C only).
9.5.1.3 Interface Number 1 (Isochronous-Out Interface)
Interface number 1 is for the audio-streaming data-out interface. Interface number 1 has the alternative settings
described in Table 7. Alternative setting number 0 is the zero-bandwidth setting. All other alternative settings are
operational settings.
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Table 7. Interface Number 1 Parameters
ALTERNATIVE
SETTING
TRANSFER
MODE
SAMPLING RATE
DATA FORMAT
(kHz)
00
01
02
Zero bandwidth
16-bit
16-bit
Stereo
Mono
2's complement (PCM)
2's complement (PCM)
Adaptive
Adaptive
32, 44.1, 48
32, 44.1, 48
9.5.1.4 Interface Number 2 (HID Interface)
Interface number 2 is the interrupt-data-in interface. The HID consumer control device consists of interface
number 2. Alternative setting number 0 is the only possible setting for interface number 2.
On the HID device descriptor, eight HID items are reported for any model, in any configuration.
9.5.1.4.1 HID Items Reported
9.5.1.4.1.1 Basic HID Operation
Interface number 2 can report these three key statuses for any model. These statuses can be set by the HID0
through HID2 pins (PCM2704C/6C) or the SPI port (PCM2705C/7C).
•
•
•
Mute (0xE2)
Volume up (0xE9)
Volume down (0xEA)
9.5.1.4.1.2 Extended HID Operation (PCM2705/6/7)
By using the FUNC0 through FUNC3 pins (PCM2706C) or the SPI port (PCM2705C/7C), these additional
conditions can be reported to the host.
•
•
•
•
Play/Pause (0xCD)
Stop (0xB7)
Previous (0xB6)
Next (0xB5)
9.5.1.4.1.3 Auxiliary HID Status Report (PCM2705C/7C)
One additional HID status can be reported to the host though the SPI port. This status flag is defined by SPI
command or external ROM. This definition must be described as on the report descriptor with a three-byte usage
ID. AL A/V Capture (0x0193) is assigned as the default value for this status flag.
9.5.1.5 Endpoints
The PCM2704C/5C/6C/7C has three endpoints:
•
•
•
Control endpoint (EP number 0)
Isochronous-out audio data-stream endpoint (EP number 2)
HID endpoint (EP number 5)
The control endpoint is
a
default endpoint. The control endpoint controls all functions of the
PCM2704C/5C/6C/7C by standard USB request and USB audio-class-specific request from the host. The
isochronous-out audio data-stream endpoint is an audio sink endpoint that receives the PCM audio data. The
isochronous-out audio data-stream endpoint accepts the adaptive transfer mode. The HID endpoint is an
interrupt-in endpoint. The HID endpoint reports HID status every 10 ms.
The HID endpoint is defined as a consumer-control device. The HID function is designed as an independent
endpoint from the isochronous-out endpoint. This configuration means that the effect of HID operation depends
on the host software. Typically, the HID function controls the primary audio-out device.
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9.6 Register Maps
9.6.1 SPI Register (PCM2705C/7C)
NOTE
Contents of the power attribute and max power must be consistent with the actual
application circuit configuration (the PSEL setting and the actual power usage from VBUS
of the USB connector); otherwise, it may cause improper or unexpected PCM2705C/7C
operation.
Figure 34. SPI Register Description
15
0
14
0
13
0
12
0
11
10
0
9
8
0
7
6
5
4
3
2
1
0
ST
ADDR
D0
D1
D2
D3
D4
D5
D6
D7
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8. SPI Register Field Descriptions(1)
Bit
Field
Type
Reset
Description
Determines the function of the lower 8-bit data. Table 9 summarizes the
functionality of ST and ADDR bit combinations.
0: HID status write
11
ST
1: Descriptor ROM data write
Starts write operation for internal descriptor reprogramming (active high)
This bit resets the descriptor ROM address counter and indicates that subsequent
words should be ROM data (described in External ROM Example). 456 bits of ROM
data must be continuously followed after this bit has been asserted. The data bits
must be sent from LSB (D0) to MSB (D7).
9
ADDR
To set ADDR high, ST must be set low. Note that the lower 8 bits are still active as an
HID status write when ST is set low.
ST = 0 (HID status write); Reports extended command status to the host (active high)
ST = 1 (ROM data write); Internal descriptor ROM data, D0:LSB
7
6
5
4
3
2
1
0
D0
D1
D2
D3
D4
D5
D6
D7
ST = 0 (HID status write); Reports play/pause HID status to the host (active high)
ST = 1 (ROM data write); Internal descriptor ROM data
ST = 0 (HID status write); Reports stop HID status to the host (active high)
ST = 1 (ROM data write); Internal descriptor ROM data
ST = 0 (HID status write); Reports previous-track HID status to the host (active high)
ST = 1 (ROM data write); Internal descriptor ROM data
ST = 0 (HID status write); Reports next-track HID status to the host (active high)
ST = 1 (ROM data write); Internal descriptor ROM data
ST = 0 (HID status write); Reports volume-down HID status to the host (active high)
ST = 1 (ROM data write); Internal descriptor ROM data
ST = 0 (HID status write); Reports volume-up HID status to the host (active high)
ST = 1 (ROM data write); Internal descriptor ROM data
ST = 0 (HID status write); Reports MUTE HID status to the host (active high)
ST = 1 (ROM data write); Internal descriptor ROM data, D7:MSB
(1) D[7:0] – Function of the lower 8 bits depends on the value of the ST (B11) bit.
Table 9. Functionality of ST and ADDR Bit Combinations
ST
0
ADDR
FUNCTION
0
1
0
1
HIS status write
0
HIS status write and descriptor ROM address reset
Descriptor ROM data write
Reserved
1
1
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The PSEL allows the device to configure for bus-powered mode (High) or self-powered mode (Low). The HOST
pin configures the maximum current consumption of the device during bus-powered mode (low: 100 mA, high:
500 mA), or can be used as host detector during self-powered mode. The SSPND flag notifies when the USB
input is idle for at least 5 ms; this flag can be used to control or notify subsequent circuits. The device descriptor
can be modified by using an external ROM (PCM2704C/6C) or through the SPI port (PCM2705C/7C); this
descriptor programming function is only available when PSEL and HOST are high. More functional details can be
found in USB Interface.
10.2 Typical Application
10.2.1 Typical Circuit Connection 1: USB Speaker
Figure 35 shows a typical circuit connection for an internal-descriptor, bus-powered, 500-mA application.
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Typical Application (continued)
X1
C1
C2
R1
PCM2704CDB
External ROM(3)
(Optional)
1
2
XTO
CK
XTI
28
27
26
SUSPEND
SCL
SSPND
TEST0
SDA
3
DT
PSEL(2)
DOUT
DGND
VDD
R9
4
TEST1 25
HID2/MD
S/PDIF OUT
5
24
23
22
21
20
19
18
17
16
15
VOLUME-
VOLUME+
MUTE
6
HID1/MC
HID0/MS
HOST(2)
R2
USB ‘B’
Connector
C7
7
R3
R4
D-
D+
8
D-
C4
(3)
9
D+
VCCP
VBUS
10
11
12
13
14
VBUS
PGND
VCOM
C3
C8
+
GND
ZGND
AGNDL
VCCL
AGNDR
VCCR
C6
C5
C9
C13
+
+
+
VOUTL(1)
VOUTR(1)
+
C11
C12
C10
C14
TPA200x
Power Amp
R5
R6 R7
R8
NOTE: X1: 12-MHz crystal resonator. C1, C2: 10- to 33-pF capacitors (depending on load capacitance of crystal resonator). C3to C7: 1-μF
ceramic capacitors. C8: 10-μF electrolytic capacitor. C9, C10: 100-μF electrolytic capacitors (depending on tradeoff between required
frequency response and discharge time for resume). C11, C12: 0.022-μF ceramic capacitors. C13, C14: 1-μF electrolytic capacitors. R1: 1-MΩ
resistor. R2, R9: 1.5-kΩ resistors. R3, R4: 22-Ω resistors. R5, R6: 16-Ω resistors. R7, R8: 330-Ω resistors (depending on tradeoff between
required THD performance and pop-noise level for suspend).
(1) Output impedance of VOUTL and VOUTR during suspended mode or lack of power supply is 26 kΩ ±20%, which is the discharge path for
C9 and C10
.
(2) Descriptor programming through external ROM is only available when PSEL and HOST are high.
(3) External ROM power can be supplied from VCCP, but any other active component must not use VCCP, VCCL, VCCR, or VDD as a power
source.
Figure 35. Bus-Powered Application
NOTE
The circuit shown in Figure 35 is for information only. The entire board design should be
considered to meet the USB specification as a USB-compliant product.
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Typical Application (continued)
10.2.1.1 Design Requirements
For this design example, use the parameters listed in Table 10.
Table 10. Design Parameters
DESIGN PARAMETER
Input voltage range
Current
EXAMPLE VALUE
4.35 V to 5.25 V (USB power)
500 mA (Bus-Powered Max power)
11.994 MHz to 12.006 MHz
Input clock frequency
10.2.1.2 Detailed Design Procedure
The PCM2704C/5C/6C/7C is a simple design device that can connect directly to a USB port. Only a 3.3-V
external regulator is needed (in self-powered mode), and an external ROM for the descriptor programming
function (PCM2704C/6C). The switches connected to the HID ports must be normally open. TI recommends
placing an output filter such as the one shown in Figure 35. The PCM2704C/5C/6C/7C requires decoupling
capacitors on the voltage source pins.
10.2.1.3 Application Curves
For the application curves, see the graphs listed in Table 11.
Table 11. Table of Graphs
FIGURE
Frequency Response
Passband Ripple
Figure 6
Figure 7
Figure 8
Figure 9
DAC Digital Interpolation Filter
Frequency Response
Passband Characteristics
Stop Band Characteristics
DAC Analog Low-Pass Filter
Frequency Response
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10.2.2 Typical Circuit Connection 2: Remote Headphone
Figure 36 shows a typical circuit connection for a bus-powered, 100-mA headphone with seven HIDs.
C9
+
Headphone
+
C11
C12
C10
R5
R6
R7
R8
R9
R10
C3
C4
C6
+
USB ‘B’
Connector
32 31 30 29 28 27 26 25
R2
C5
VBUS
D+
PGND
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
VBUS
D+
(3)
R3
VCCP
HOST(2)
FUNC3
D-
D-
VDD
R4
GND
PLAY/PAUSE
NEXT TRACK
MUTE
C8
PCM2706CPJT
FUNC0
HID0/MS
HID1/MC
HID2/MD
DGND
FUNC1
FUNC2
DOUT
C7
PREVIOUS TRACK
STOP
VOLUME+
VOLUME-
External ROM(3)
(Optional)
9
10 11 12 13 14 15 16
SCL
SDA
SUSPEND
R11
R1
X1
C1
C2
NOTE: X1: 12-MHz crystal resonator. C1, C2: 10- to 33-pF capacitors (depending on load capacitance of crystal resonator). C3 to C5, C7, C8:
1-μF ceramic capacitors. C6: 10-μF electrolytic capacitor. C9, C10: 100-μF electrolytic capacitors (depending on required frequency response).
C11, C12: 0.022-μF ceramic capacitors. R1: 1-MΩ resistor. R2, R11: 1.5-kΩ resistors. R3, R4: 22-Ω resistors. R5, R6: 16-Ω resistors. R7 to R10
:
3.3-kΩ resistors.
(1) Output impedance of VOUTL and VOUTR during suspend mode or lack of power supply is 26 kΩ ±20%, which is the discharge path for C9
and C10
.
(2) Descriptor programming through external ROM is only available when PSEL and HOST are high.
(3) External ROM power can be supplied from VCCP, but any other active component must not use VCCP, VCCL, VCCR, or VDD as a power
source.
Figure 36. Bus-Powered Application
NOTE
The circuit shown in Figure 36 is for information only. The entire board design should be
considered to meet the USB specification as a USB-compliant product.
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10.2.2.1 Design Requirements
For this design example, use the parameters listed in Table 12.
Table 12. Design Parameters
DESIGN PARAMETER
Input voltage range
Current
EXAMPLE VALUE
4.35 V to 5.25 V (USB power)
100 mA (Bus-Powered Max power)
11.994 MHz to 12.006 MHz
Input clock frequency
10.2.2.2 Detailed Design Procedure
A general detailed design procedure is explained in Detailed Design Procedure.
10.2.2.3 Application Curves
For the application curves, see the graphs listed in Table 11.
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SBFS036B –MAY 2015–REVISED AUGUST 2015
10.2.3 Typical Circuit Connection 3: DSP Surround Processing Amplifier
Figure 37 shows a typical circuit connection for an I2S- and SPI-enabled self-powered application.
C8
+
Headphone
+
C10
C11
C9
R9
R6
R7
R8
R10
R11
C3
C4
C6
+
USB ‘B’
Connector
(3)
32 31 30 29 28 27 26 25
R2
C5
VBUS
D+
PGND
(3)
TAS300x(4)
I2S I/F
Audio Device
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
VBUS
(3)
R3
VCCP
D+
HOST(2)
FUNC3
D-
D-
VDD
DIN
R4
(3)
GND
R12
PCM2707CPJT
C7
LRCK
MS
FUNC0
HID0/MS
HID1/MC
HID2/MD
DGND
FUNC1
FUNC2
DOUT
BCK
MC
MD
SYSTEM CLOCK
DOUT
9
10 11 12 13 14 15 16
SUSPEND
R5
R1
X1
Power
3.3 V
C1
C2
GND
NOTE: X1: 12-MHz crystal resonator. C1, C2: 10- to 33-pF capacitors (depending on load capacitance of crystal resonator). C3, C4: 1-μF
ceramic capacitors. C5, C7: 0.1-μF ceramic capacitor and 10-μF electrolytic capacitor. C6: 10-μF electrolytic capacitors. C8, C9: 100-μF
electrolytic capacitors (depending on required frequency response). C10, C11: 0.022-μF ceramic capacitors. R1, R12: 1-MΩ resistors. R2, R5:
1.5-kΩ resistors. R3, R4: 22-Ω resistors. R6, R7: 16-Ω resistors. R8to R11: 3.3-kΩ resistors.
(1) Output impedance of VOUTL and VOUTR during suspend mode or lack of power supply is 26 kΩ ±20%, which is the discharge path for C8
and C9.
(2) Descriptor programming through SPI is only available when PSEL and HOST are high.
(3) D+ pullup must not be activated (high: 3.3 V) while the device is detached from USB or power supply is not applied on VDD and VCCx
.
VBUS of USB (5 V) can be used to detect USB power status.
(4) MS must be high until the PCM2707C power supply is ready and the SPI host (the DSP) is ready to send data. Also, the SPI host must
handle the D+ pullup if the descriptor is programmed through the SPI. D+ pullup must not be activated (high = 3.3 V) before programming of
the PCM2707C through the SPI is complete.
Figure 37. Self-Powered Application
NOTE
The circuit shown in Figure 37 is for information only. The entire board design should be
considered to meet the USB specification as a USB-compliant product.
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10.2.3.1 Design Requirements
For this design example, use the parameters listed in Table 13.
Table 13. Design Parameters
DESIGN PARAMETER
Input voltage range
Current
EXAMPLE VALUE
3 V to 3.6 V
100 mA
Input clock frequency
11.994 MHz to 12.006 MHz
10.2.3.2 Detailed Design Procedure
A general detailed design procedure is explained in Detailed Design Procedure.
10.2.3.3 Application Curves
For the application curves, see the graphs listed in Table 11.
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SBFS036B –MAY 2015–REVISED AUGUST 2015
11 Power Supply Recommendations
The voltage source required to power the PCM2704C/5C/6C/7C must be between 3 V and 3.6 V for proper
operation (self-powered mode). TI recommends placing a decoupling capacitor in every voltage source pin. This
helps filter lower frequency power supply noise. Place these decoupling capacitors as close as possible to the
PCM2704C/5C/6C/7C.
12 Layout
12.1 Layout Guidelines
The decoupling capacitors must be as close as possible to the PCM2704C/5C/6C/7C pins. TI recommends
placing an output filter such as the one shown in Detailed Design Procedure. The PCM2704C/5C/6C/7C is a low
power device, so there is no need for a special heat sink PCB design.
12.2 Layout Example
SUSPEND
HID controls
Clock hardware for
built-in resonator
1uF
1uF
1uF
10uF
100uF
0.022uF
V
OUT
L
10pF-33pF
1MΩ
Decoupling capacitors as
close as possible to de IC
12MHz
PCM2704C/5C
10pF-33pF
100uF
1uF
V
OUT
R
0.022uF
1uF
1uF
1uF
USB port
Connection to ground plane
Top layer traces
Connection to power VBUS
Top layer ground plane
Figure 38. Layout Example 1
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www.ti.com
Layout Example (continued)
0.022uF
100uF
V
OUT
R
L
V
OUT
0.022uF
100uF
Decoupling capacitors as
close as possible to de IC
10uF
1uF
1uF
USB port
1uF
VBUS
HID controls
22Ω
D+
D-
1uF
22Ω
1uF
PLAY/PAUSE
NEXT TRACK
MUTE
GND
PCM2706C
VOLUME+
VOLUME-
S/PDIF OUT
PREVIOUS TRACK
STOP
SUSPEND
SCL
SDA
1MΩ
Clock hardware for
built-in resonator
12MHz
External ROM
(Optional)
10pF-33pF
10pF-33pF
Connection to ground
Bottom layer
Top layer
Top layer ground plane
Figure 39. Layout Example 2
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PCM2704C, PCM2705C, PCM2706C, PCM2707C
www.ti.com
SBFS036B –MAY 2015–REVISED AUGUST 2015
Layout Example (continued)
0.022uF
100uF
V
OUT
R
L
V
OUT
0.022uF
100uF
Decoupling capacitors as
close as possible to de IC
1uF
1uF
10uF
I2S I/F Audio
Device
V
BUS
22Ω
22Ω
D+
D-
10uF
DIN
LRCK
MS
GND
PCM2707C
0.1uF
MC
USB port
MD
DOUT
BCK
System Clock
SUSPEND
1MΩ
Clock hardware for
built-in resonator
12MHz
10pF-33pF
10pF-33pF
Connection to power 3.3 V
Top layer ground plane
Connection to ground
Bottom layer
Top layer
Figure 40. Layout Example 3
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SBFS036B –MAY 2015–REVISED AUGUST 2015
www.ti.com
13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
For related documentation, see the Updated Operating Environments for PCM270x, PCM290x Applications,
SLAA374.
13.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 14. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
SAMPLE & BUY
PCM2704C
PCM2705C
PCM2706C
PCM2707C
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
13.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.4 Trademarks
SpAct, E2E are trademarks of Texas Instruments.
System Two Cascade is a trademark of Audio Precision, Inc.
Audio Precision is a registered trademark of Audio Precision, Inc.
All other trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
3-Oct-2014
PACKAGING INFORMATION
Orderable Device
PCM2704CDB
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-25 to 85
-25 to 85
-25 to 85
-25 to 85
-25 to 85
-25 to 85
-25 to 85
-25 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
SSOP
SSOP
SSOP
SSOP
TQFP
TQFP
TQFP
TQFP
DB
28
28
28
28
32
32
32
32
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
PCM2704C
PCM2704CDBR
PCM2705CDB
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DB
DB
2000
50
Green (RoHS
& no Sb/Br)
PCM2704C
PCM2705C
PCM2705C
PCM2706C
PCM2706C
PCM2707C
PCM2707C
Green (RoHS
& no Sb/Br)
PCM2705CDBR
PCM2706CPJT
PCM2706CPJTR
PCM2707CPJT
PCM2707CPJTR
DB
2000
250
Green (RoHS
& no Sb/Br)
PJT
PJT
PJT
PJT
Green (RoHS
& no Sb/Br)
1000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
1000
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
3-Oct-2014
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Oct-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
PCM2705CDBR
PCM2706CPJTR
PCM2707CPJTR
SSOP
TQFP
TQFP
DB
PJT
PJT
28
32
32
2000
1000
1000
330.0
330.0
330.0
16.4
16.8
16.8
8.2
9.6
9.6
10.5
9.6
2.5
1.5
1.5
12.0
12.0
12.0
16.0
16.0
16.0
Q1
Q2
Q2
9.6
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Oct-2014
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
PCM2705CDBR
PCM2706CPJTR
PCM2707CPJTR
SSOP
TQFP
TQFP
DB
PJT
PJT
28
32
32
2000
1000
1000
367.0
367.0
367.0
367.0
367.0
367.0
38.0
38.0
38.0
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPQF112 – NOVEMBER 2001
PJT (S-PQFP–N32)
PLASTIC QUAD FLATPACK
0,45
0,30
0,80
M
0,20
0,20
0,09
Gage Plane
32
0,15
0,05
0,25
1
0°– 7°
7,00
9,00
SQ
SQ
0,75
0,45
1,05
0,95
Seating Plane
0,10
1,20
1,00
4203540/A 11/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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