PCM3120-Q1 [TI]
汽车类、立体声、106dB SNR、768kHz、低功耗、软件控制的音频 ADC;
| 型号： | PCM3120-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类、立体声、106dB SNR、768kHz、低功耗、软件控制的音频 ADC |
| 文件： | 总122页 (文件大小：5665K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PCM3120-Q1
ZHCSPD4A –APRIL 2022 –REVISED SEPTEMBER 2022
PCM3120-Q1 2 通道、768 kHz、Burr-BrownTM 音频ADC
1 特性
3 说明
• 多通道高性能ADC：
PCM3120-Q1 是一款高性能 Burr-Brown™ 音频模数转
换器 (ADC)，最多可支持对脉冲密度调制 (PDM) 麦克
风输入的两个模拟通道或四个数字通道进行同步采样。
该器件支持线路和麦克风输入，并能够实现单端和差分
输入配置。该器件集成了可编程通道增益、数字音量控
制、可编程麦克风偏置电压、锁相环 (PLL)、可编程高
通滤波器 (HPF)、双二阶滤波器、低延迟滤波器模式，
并可实现高达 768kHz 的采样率。该器件支持时分多路
复用 (TDM)、I2S 或左对齐 (LJ) 音频格式，并可通过
I2C 接口进行控制。这些集成的高性能特性，以及采用
3.3V 或 1.8 V 单电源供电的功能，使该器件非常适用
于远场麦克风录音应用中空间受限的音频系统。
– 2 通道模拟麦克风输入或线路输入
– 4 通道数字PDM 麦克风
– 多达2 个模拟和多达2 个数字麦克风通道
• ADC 线路和麦克风差分输入性能：
– 动态范围(DR)：106 dB
– THD+N：-95 dB
• ADC 通道相加模式，DR 性能：
– 109 dB，2 通道相加
• ADC 输入电压：
– 差分2VRMS 满量程输入
– 单端1VRMS 满量程输入
• ADC 采样率(fS) = 8 kHz 至768 kHz
• 可编程通道设置：
PCM3120-Q1 的额定工作温度范围为 –40°C 至
+125°C，并且采用20 引脚WQFN 封装。
– 通道增益：0 dB 至42 dB，步长0.5 dB
– 数字音量控制：–100 dB 至27 dB
– 增益校准分辨率为0.1 dB
– 相位校准分辨率为163 ns
• 可编程麦克风偏置或电源电压生成
• 低延迟信号处理滤波器选择
• 可编程HPF 和双二阶数字滤波器
• 自动增益控制器(AGC)
器件信息
器件型号(1)
PCM3120-Q1
封装尺寸（标称值）
封装
3.00mm × 3.00mm，间距
为0.5mm
WQFN (20)
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
Digital PDM Microphones
Interface 4-channel
PLL and Clock
Generation
IN1P
IN1M
GPIO1
• 话音激活检测(VAD)
• I2C 控制接口
• 集成高性能音频PLL
• 自动时钟分频器设置配置
• 音频串行数据接口：
FSYNC
BCLK
Stereo ADC
with Front-End
PGA
Programmable
Digital Filters,
Biquads, AGC
Audio Serial
Interface
IN2P_GPI1
(TDM, I2S, LJ)
SDOUT
IN2M_GPO1
– 格式：TDM、I2S 或左对齐(LJ)
– 字长：16 位、20 位、24 位或32 位
– 主/从接口
SDA
SCL
MICBIAS_GPI2
VREF
MICBIAS, Regulators and
Voltage Reference
I2C Control Interface
• 单电源运行：3.3V 或1.8V
• I/O 电源运行：3.3V 或1.8V
• 1.8V AVDD 电源电压下的功耗：
Thermal Pad
(VSS)
AVDD
DREG
IOVDD
AREG
简化版方框图
– 48 kHz 采样率下为9.5 mW/通道
2 应用
• 汽车主动噪声消除
• 汽车音响主机
• 后座娱乐系统
• 数字驾驶舱处理单元
• 远程信息处理控制单元
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBASAH0
PCM3120-Q1
ZHCSPD4A –APRIL 2022 –REVISED SEPTEMBER 2022
www.ti.com.cn
Table of Contents
8.1 Overview...................................................................17
8.2 Functional Block Diagram.........................................18
8.3 Feature Description...................................................18
8.4 Device Functional Modes..........................................56
8.5 Programming............................................................ 57
8.6 Register Maps...........................................................60
9 Application and Implementation..................................98
9.1 Application Information............................................. 98
9.2 Typical Applications.................................................. 98
9.3 What to Do and What Not to Do............................. 105
10 Power Supply Recommendations............................105
11 Layout.........................................................................108
11.1 Layout Guidelines................................................. 108
11.2 Layout Example.................................................... 108
12 Device and Documentation Support........................109
12.1 Documentation Support........................................ 109
12.2 接收文档更新通知................................................. 109
12.3 支持资源................................................................109
12.4 Trademarks...........................................................109
12.5 Electrostatic Discharge Caution............................109
12.6 术语表................................................................... 109
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions.........................6
Thermal Information..........................................................6
7.4 Electrical Characteristics.............................................7
7.5 Timing Requirements: I2C Interface..........................10
7.6 Switching Characteristics: I2C Interface....................11
7.7 Timing Requirements: TDM, I2S or LJ Interface....... 11
7.8 Switching Characteristics: TDM, I2S or LJ
Interface.......................................................................11
Timing Requirements: PDM Digital Microphone
Interface.......................................................................11
7.9 Switching Characteristics: PDM Digial
Microphone Interface...................................................12
7.10 Timing Diagrams.....................................................12
7.11 Typical Characteristics............................................ 14
8 Detailed Description......................................................17
Information.................................................................. 110
13.1 Tape and Reel Information....................................114
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (April 2022) to Revision A (September 2022)
Page
• 将文档状态从预告信息更改为量产数据...............................................................................................................1
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5 Device Comparison Table
FEATURE
Control interface
PCM1821-Q1
PCM1820-Q1
Pin control
PCM1822-Q1
PCM3120-Q1
PCM5120-Q1
I2C
PCM6120-Q1
Digital audio serial interface
Audio analog channel
TDM or I2S
TDM or I2S or left-justified (LJ)
2
Digital microphone channel
Not available
N/A
4
Programmable MICBIAS
voltage
Yes
Dynamic range (DRE
disabled)
106 dB
113 dB
111 dB
106 dB
108 dB
113 dB
Dynamic range (DRE enabled)
ADC SNR with DRE
Input Voltage
Not available
N/A
123 dB
123 dB
117 dB
117 dB
1 Vrms
Not available
N/A
120 dB
120 dB
2 Vrms
123 dB
123 dB
2 Vrms
Input Type
Differential/Single-
Ended
Differential
Differential/Single-Ended
Input impedance
Compatibility
10 kΩ
2.5 kΩ
2.5 kΩ, 10 kΩ, 20 kΩ
Pin-to-pin, package, drop-in replacements of each other
Pin-to-pin, package, and control registers compatible; drop-in
replacements of each other
Package
WQFN (RTE), 20-pin, 3.00 mm × 3.00 mm (0.5-mm pitch)
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6 Pin Configuration and Functions
20
VSS
VSS
15
IN1P
IN1M
1
14
13
12
11
DREG
SCL
2
3
4
Thermal Pad (VSS)
IN2P_GPI1
IN2M_GPO1
SDA
GPIO1
5
VSS
VSS
10
Not to scale
图6-1. RTE Package, 20-Pin WQFN With Exposed Thermal Pad, Top View
表6-1. Pin Functions
PIN
TYPE
DESCRIPTION
NO.
1
NAME
IN1P
Analog input
Analog input
Analog input 1P pin.
Analog input 1M pin.
2
IN1M
Analog input 2P pin or general-purpose digital input 1 (multipurpose functions
such as digital microphones data, PLL input clock source, and so forth).
3
4
IN2P_GPI1
Analog input/digital input
Analog input 2M pin or general-purpose digital output 1 (multipurpose functions
such as digital microphone clock, interrupt, and so forth).
IN2M_GPO1 Analog input/digital output
Device ground internally shorted to thermal pad. Short this package corner pin
directly to the board ground plane. See the package drawings at the end of this
document for corner pin dimensions.
5
VSS
Ground supply
6
7
8
9
SDOUT
BCLK
Digital output
Digital I/O
Audio serial data interface bus output.
Audio serial data interface bus bit clock.
FSYNC
IOVDD
Digital I/O
Audio serial data interface bus frame synchronization signal.
Digital I/O power supply (1.8 V or 3.3 V, nominal).
Digital supply
Device ground internally shorted to thermal pad. Short this package corner pin
directly to the board ground plane. See the package drawings at the end of this
document for corner pin dimensions.
10
11
VSS
Ground supply
Digital I/O
General-purpose digital input/output 1 (multipurpose functions such as digital
microphones clock or data, PLL input clock source, interrupt, and so forth).
GPIO1
12
13
SDA
SCL
Digital I/O
Data pin for I2C control bus.
Clock pin for I2C control bus.
Digital input
Digital regulator output voltage for digital core supply (1.5 V, nominal). Connect
a 10-µF and 0.1-µF low ESR capacitor in parallel to device ground (VSS).
14
DREG
Digital supply
Device ground internally shorted to thermal pad. Short this package corner pin
directly to the board ground plane. See the package drawings at the end of this
document for corner pin dimensions.
15
16
VSS
Ground supply
Analog supply
AVDD
Analog power (1.8 V or 3.3 V, nominal).
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表6-1. Pin Functions (continued)
PIN
TYPE
DESCRIPTION
NO.
NAME
Analog on-chip regulator output voltage for analog supply (1.8 V, nominal) or
external analog power (1.8 V, nominal). Connect a 10-µF and 0.1-µF low ESR
capacitor in parallel to analog ground (AVSS).
17
AREG
Analog supply
Analog
Analog reference voltage filter output. Connect a 1-µF capacitor to analog
ground (AVSS).
18
19
VREF
MICBIAS output or general-purpose digital input 2 (multipurpose functions such
MICBIAS_GPI2 Analog output/digital input as digital microphones data, PLL input clock source, and so forth). If used as
MICBIAS output, then connect a 1-µF capacitor to analog ground (AVSS).
Device ground internally shorted to thermal pad. Short this package corner pin
20
VSS
Ground supply
Ground supply
directly to the board ground plane. See the package drawings at the end of this
document for corner pin dimensions.
Thermal Pad
(VSS)
Thermal pad shorted to internal device ground. Short the thermal pad directly to
the board ground plane.
Thermal Pad
7 Specifications
7.1 Absolute Maximum Ratings
over the operating ambient temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
MAX
UNIT
AVDD to AVSS
3.9
2.0
Supply voltage
AREG to AVSS
V
IOVDD to VSS (thermal pad)
AVSS to VSS (thermal pad)
Analog input pins voltage to AVSS
3.9
Ground voltage differences
Analog input voltage
0.3
V
V
AVDD + 0.3
Digital input except IN2P_GPI1 and MICBIAS_GPI2 pins
voltage to VSS (thermal pad)
IOVDD + 0.3
AVDD + 0.3
–0.3
–0.3
Digital input voltage
Temperature
V
Digital input IN2P_GPI1 and MICBIAS_GPI2 pins
voltage to VSS (thermal pad)
Operating ambient, TA
Junction, TJ
125
150
150
–40
–40
–65
°C
Storage, Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
7.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions
MIN
NOM
MAX
UNIT
POWER
Analog supply voltage AVDD to AVSS (AREG is generated using onchip regulator):
AVDD 3.3-V operation
3.0
1.7
3.3
1.8
3.6
1.9
AVDD,
V
V
AREG(1)
Analog supply voltage AVDD and AREG to AVSS (AREG internal regulator is
shutdown): AVDD 1.8-V operation
IO supply voltage to VSS (thermal pad): IOVDD 3.3-V operation
IOVDD
3.0
3.3
1.8
3.6
IO supply voltage to VSS (thermal pad): IOVDD 1.8-V operation
1.65
1.95
INPUTS
Analog input pins voltage to AVSS
0
0
0
AVDD
IOVDD
AVDD
V
V
V
Digital input except IN2P_GPI1 and MICBIAS_GPI2 pins voltage to VSS (thermal pad)
Digital input IN2P_GPI1 and MICBIAS_GPI2 pins voltage to VSS (thermal pad)
TEMPERATURE
TA
Operating ambient temperature
125
°C
–40
OTHERS
GPIOx or GPIx (used as MCLK input) clock frequency
36.864
400
MHz
pF
SCL and SDA bus capacitance for I2C interface supports standard-mode and fast-
mode
Cb
CL
SCL and SDA bus capacitance for I2C interface supports fast-mode plus
Digital output load capacitance
550
50
20
pF
(1) AVSS and VSS (thermal pad): all ground pins must be tied together and must not differ in voltage by more than 0.2 V.
Thermal Information
PCM3120-Q1
THERMAL METRIC(1)
RTE (WQFN)
20 PINS
55.9
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
33.1
23.4
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.6
ψJT
23.3
ψJB
RθJC(bot)
16.7
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.4 Electrical Characteristics
at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, fIN = 1-kHz sinusoidal signal, fS = 48 kHz, 32-bit audio data, BCLK = 256 × fS,
TDM slave mode, and PLL on (unless otherwise noted)
PARAMETER
ADC CONFIGURATION
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Input pins INxP or INxM, 2.5-kΩ input impedance
2.5
10
20
selection
Input pins INxP or INxM, 10-kΩ input impedance
selection
AC input impedance
Channel gain range
kΩ
Input pins INxP or INxM, 20-kΩ input impednace
selection
Programmable range with 0.5-dB steps
0
42
dB
ADC PERFORMANCE FOR LINE/MICROPHONE INPUT RECORDING : AVDD 3.3-V OPERATION
Differential input full-scale
AC-coupled input
2
1
VRMS
VRMS
AC signal voltage
Single-ended input full-
AC-coupled input
scale AC signal voltage
IN1 differential input selected and AC signal shorted to
100
106
100
107
100
ground, 10-kΩ input impedance selection, 0-dB channel
gain
Signal-to-noise ratio, A-
SNR
dB
dB
dB
weighted(1) (2)
IN1 differential input selected and AC signal shorted to
ground, 10-kΩ input impedance selection, 12-dB channel
gain
IN1 differential input selected and –60-dB full-scale AC
signal input, 10-kΩ input impedance selection, 0-dB
channel gain
Dynamic range, A-
DR
weighted(2)
IN1 differential input selected and –72-dB full-scale AC
signal input, 10-kΩ input impedance selection, 12-dB
channel gain
IN1 differential input selected and –1-dB full-scale AC
signal input, 10-kΩ input impedance selection, 0-dB
–95
–93
–80
Total harmonic distortion(2)
channel gain
THD+N
(3)
IN1 differential input selected and –13-dB full-scale AC
signal input, 10-kΩ input impedance selection, 12-dB
channel gain
ADC PERFORMANCE FOR LINE/MICROPHONE INPUT RECORDING : AVDD 1.8-V OPERATION
Differential input full-scale
AC-coupled Input
1
VRMS
VRMS
AC signal voltage
Single-ended input full-
AC-coupled Input
0.5
scale AC signal voltage
IN1 differential input selected and AC signal shorted to
Signal-to-noise ratio, A-
SNR
DR
100
101
dB
dB
dB
ground, 10-kΩ input impedance selection, 0-dB channel
weighted(1) (2)
gain
IN1 differential input selected and –60-dB full-scale AC
signal input, 10-kΩ input impedance selection, 0-dB
channel gain
Dynamic range, A-
weighted(2)
IN1 differential input selected and –2-dB full-scale AC
signal Input, 10-kΩ input impedance selection, 0 dB
channel gain
Total harmonic distortion(2)
THD+N
–90
(3)
ADC OTHER PARAMETERS
Digital volume control
Programmable 0.5-dB steps
Programmable
27
768
32
dB
–100
7.35
16
range
Output data sample rate
kHz
Bits
Output data sample word
length
Programmable
First-order IIR filter with programmable coefficients,
–3-dB point (default setting)
Digital high-pass filter cutoff
frequency
12
Hz
–1-dB full-scale AC-signal input to non measurement
channel
Interchannel isolation
dB
dB
–124
Interchannel gain mismatch
0.1
–6-dB full-scale AC-signal input and 0-dB channel gain
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at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, fIN = 1-kHz sinusoidal signal, fS = 48 kHz, 32-bit audio data, BCLK = 256 × fS,
TDM slave mode, and PLL on (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0-dB channel gain, across temperature range –40°C to
125°C
Gain drift(4)
36.8
ppm/°C
Interchannel phase
mismatch
1-kHz sinusoidal signal
0.02
0.0005
102
Degrees
Degrees/°C
dB
1-kHz sinusoidal signal, across temperature range –
40°C to 125°C
Phase drift(5)
Power-supply rejection
ratio
100-mVPP, 1-kHz sinusoidal signal on AVDD, differential
input selected, 0-dB channel gain
PSRR
CMRR
Differential microphone input selected, 0-dB channel
gain, 100-mVPP, 1-kHz signal on both pins and measure
level at output
Common-mode rejection
ratio
60
dB
µVRMS
V
MICROPHONE BIAS
MICBIAS noise
BW = 20 Hz to 20 kHz, A-weighted, 1-μF capacitor
between MICBIAS and AVSS
2.1
MICBIAS programmed to VREF and VREF programmed
to either 2.75 V, 2.5 V, or 1.375 V
VREF
MICBIAS programmed to VREF × 1.096 and VREF
programmed to either 2.75 V, 2.5 V, or 1.375 V
VREF ×
1.096
MICBIAS voltage
Bypass to AVDD with 5-mA load
AVDD –0.2
MICBIAS current drive
5
1
mA
%
MICBIAS programmed to either VREF or VREF ×
1.096, measured up to max load
MICBIAS load regulation
0
0.6
MICBIAS over current
protection threshold
6.1
mA
DIGITAL I/O
All digital pins except IN2P_GPI1 and MICBIAS_GPI2,
SDA and SCL, IOVDD 1.8-V operation
0.35 ×
IOVDD
–0.3
–0.3
Low-level digital input logic
voltage threshold
VIL
V
V
V
All digital pins except IN2P_GPI1 and MICBIAS_GPI2,
SDA and SCL, IOVDD 3.3-V operation
0.8
IOVDD + 0.3
IOVDD + 0.3
0.45
All digital pins except IN2P_GPI1 and MICBIAS_GPI2,
SDA and SCL, IOVDD 1.8-V operation
0.65 ×
IOVDD
High-level digital input logic
voltage threshold
VIH
All digital pins except IN2P_GPI1 and MICBIAS_GPI2,
SDA and SCL, IOVDD 3.3-V operation
2
All digital pins except IN2M_GPO1, SDA and SCL, IOL
–2 mA, IOVDD 1.8-V operation
=
=
=
=
Low-level digital output
voltage
VOL
All digital pins except IN2M_GPO1, SDA and SCL, IOL
–2 mA, IOVDD 3.3-V operation
0.4
All digital pins except IN2M_GPO1, SDA and SCL, IOH
2 mA, IOVDD 1.8-V operation
IOVDD –
0.45
High-level digital output
voltage
VOH
V
All digital pins except IN2M_GPO1, SDA and SCL, IOH
2 mA, IOVDD 3.3-V operation
2.4
–0.5
Low-level digital input logic
voltage threshold
VIL(I2C)
SDA and SCL
0.3 x IOVDD
IOVDD + 0.5
0.4
V
V
V
V
High-level digital input logic
voltage threshold
VIH(I2C)
VOL1(I2C)
VOL2(I2C)
SDA and SCL
0.7 x IOVDD
Low-level digital output
voltage
SDA, IOL(I2C) = –3 mA, IOVDD > 2 V
SDA, IOL(I2C) = –2 mA, IOVDD ≤2 V
Low-level digital output
voltage
0.2 x IOVDD
SDA, VOL(I2C) = 0.4 V, standard-mode or fast-mode
SDA, VOL(I2C) = 0.4 V, fast-mode plus
3
Low-level digital output
current
IOL(I2C)
mA
20
Input logic-high leakage for All digital pins except IN2P_GPI1 and MICBIAS_GPI2
digital inputs pins, input = IOVDD
IIH
IIL
0.1
0.1
5
5
µA
µA
–5
–5
Input logic-low leakage for All digital pins except IN2P_GPI1 and MICBIAS_GPI2
digital inputs pins, input = 0 V
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at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, fIN = 1-kHz sinusoidal signal, fS = 48 kHz, 32-bit audio data, BCLK = 256 × fS,
TDM slave mode, and PLL on (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IN2P_GPI1 and MICBIAS_GPI2 digital pins, AVDD 1.8-V
operation
0.35 × AVDD
–0.3
Low-level digital input logic
voltage threshold
VIL(GPIx)
VIH(GPIx)
VOL(GPOx)
V
IN2P_GPI1 and MICBIAS_GPI2 digital pins, AVDD 3.3-V
operation
0.8
AVDD + 0.3
AVDD + 0.3
0.45
–0.3
0.65 × AVDD
2
IN2P_GPI1 and MICBIAS_GPI2 digital pins, AVDD 1.8-V
operation
High-level digital input logic
voltage threshold
V
V
V
IN2P_GPI1 and MICBIAS_GPI2 digital pins, AVDD 3.3-V
operation
IN2M_GPO2 digital pin, IOL = –2 mA, AVDD 1.8-V
operation
Low-level digital output
voltage
IN2M_GPO2 digital pin, IOL = –2 mA, AVDD 3.3-V
operation
0.4
IN2M_GPO2 digital pin, IOH = 2 mA, AVDD 1.8-V
operation
AVDD –
0.45
High-level digital output
voltage
VOH(GPOx)
IN2M_GPO2 digital pin, IOH = 2 mA, AVDD 3.3-V
operation
2.4
–5
–5
Input logic-high leakage for IN2P_GPI1 and MICBIAS_GPI2 digital pins, input =
IIH(GPIx)
IIL(GPIx)
CIN
0.1
0.1
5
5
5
µA
µA
pF
digital inputs
AVDD
Input logic-high leakage for
digital inputs
IN2P_GPI1 and MICBIAS_GPI2 digital pins, input = 0 V
Input capacitance for digital
inputs
All digital pins
Pulldown resistance for
digital I/O pins when
asserted on
RPD
20
kΩ
TYPICAL SUPPLY CURRENT CONSUMPTION
All external clocks stopped, AVDD = 3.3 V, internal
IAVDD
5
AREG
Current consumption in
sleep mode (software
shutdown mode)
All external clocks stopped, AVDD = 1.8 V, external
AREG supply (AREG shorted to AVDD)
IAVDD
29
µA
IIOVDD
IIOVDD
IAVDD
All external clocks stopped, IOVDD = 3.3 V
All external clocks stopped, IOVDD = 1.8 V
AVDD = 3.3 V, internal AREG
0.5
0.5
11.1
Current consumption with
ADC 2-channel operating
at fS 48-kHz, PLL off
AVDD = 1.8 V, external AREG supply (AREG shorted to
AVDD)
IAVDD
10.5
mA
mA
mA
IIOVDD
IIOVDD
IAVDD
IOVDD = 3.3 V
0.1
0.05
11.3
and BCLK = 512 × fS
IOVDD = 1.8 V
AVDD = 3.3 V, internal AREG
Current consumption with
ADC 2-channel operating
at fS 16-kHz, PLL on and
BCLK = 256 × fS
AVDD = 1.8 V, external AREG supply (AREG shorted to
AVDD)
IAVDD
10.6
IIOVDD
IIOVDD
IAVDD
IOVDD = 3.3 V
0.05
0.02
12.2
IOVDD = 1.8 V
AVDD = 3.3 V, internal AREG
Current consumption with
ADC 2-channel operating
at fS 48-kHz, PLL on
AVDD = 1.8 V, external AREG supply (AREG shorted to
AVDD)
IAVDD
11.6
IIOVDD
IIOVDD
IOVDD = 3.3 V
IOVDD = 1.8 V
0.1
and BCLK = 256 × fS
0.05
(1) Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with the AC signal input shorted to ground, measured A-
weighted over a 20-Hz to 20-kHz bandwidth using an audio analyzer.
(2) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values.
(3) For best distortion performance, use input AC-coupling capacitors with low-voltage coefficient.
(4) Gain drift = gain variation (in temperature range) / typical gain value (gain at room temperature) / temperature range × 106 measured
with gain in linear scale.
(5) Phase drift = phase deviation (in temperature range) / (temperature range).
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7.5 Timing Requirements: I2C Interface
at TA = 25°C, IOVDD = 3.3 V or 1.8 V (unless otherwise noted); see Figure 7-1 for timing diagram
MIN
NOM
MAX
UNIT
STANDARD-MODE
fSCL
SCL clock frequency
0
4
100
kHz
Hold time (repeated) START condition.
After this period, the first clock pulse is generated.
tHD;STA
μs
tLOW
Low period of the SCL clock
High period of the SCL clock
Setup time for a repeated START condition
Data hold time
4.7
4
μs
μs
μs
μs
ns
tHIGH
tSU;STA
tHD;DAT
tSU;DAT
tr
4.7
0
3.45
Data setup time
250
SDA and SCL rise time
1000
300
ns
tf
SDA and SCL fall time
ns
tSU;STO
tBUF
Setup time for STOP condition
Bus free time between a STOP and START condition
4
μs
μs
4.7
FAST-MODE
fSCL
SCL clock frequency
0
400
kHz
Hold time (repeated) START condition.
After this period, the first clock pulse is generated.
tHD;STA
0.6
μs
tLOW
Low period of the SCL clock
High period of the SCL clock
Setup time for a repeated START condition
Data hold time
1.3
0.6
0.6
0
μs
μs
μs
μs
ns
tHIGH
tSU;STA
tHD;DAT
tSU;DAT
tr
0.9
Data setup time
100
20
SDA and SCL rise time
300
300
ns
20 × (IOVDD / 5.5
V)
tf
SDA and SCL fall time
ns
tSU;STO
Setup time for STOP condition
0.6
1.3
μs
μs
tBUF
Bus free time between a STOP and START condition
FAST-MODE PLUS
fSCL
SCL clock frequency
0
1000
kHz
Hold time (repeated) START condition.
After this period, the first clock pulse is generated.
tHD;STA
0.26
μs
tLOW
Low period of the SCL clock
High period of the SCL clock
Setup time for a repeated START condition
Data hold time
0.5
0.26
0.26
0
μs
μs
μs
μs
ns
tHIGH
tSU;STA
tHD;DAT
tSU;DAT
tr
Data setup time
50
SDA and SCL rise time
120
120
ns
20 × (IOVDD / 5.5
V)
tf
SDA and SCL fall time
ns
tSU;STO
tBUF
Setup time for STOP condition
0.26
0.5
μs
μs
Bus free time between a STOP and START condition
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7.6 Switching Characteristics: I2C Interface
at TA = 25°C, IOVDD = 3.3 V or 1.8 V (unless otherwise noted); see Figure 7-1 for timing diagram
PARAMETER
TEST CONDITIONS
MIN
250
250
TYP
MAX
1250
850
UNIT
Standard-mode
td(SDA)
SCL to SDA delay
Fast-mode
ns
Fast-mode plus
400
7.7 Timing Requirements: TDM, I2S or LJ Interface
at TA = 25°C, IOVDD = 3.3 V or 1.8 V and 20-pF load on all outputs (unless otherwise noted); see 图7-2 for timing diagram
MIN
40
25
25
8
NOM
MAX
UNIT
t(BCLK)
BCLK period
ns
tH(BCLK)
tL(BCLK)
tSU(FSYNC)
tHLD(FSYNC)
tr(BCLK)
BCLK high pulse duration (1)
BCLK low pulse duration (1)
FSYNC setup time
FSYNC hold time
BCLK rise time
ns
ns
ns
8
ns
10% - 90% rise time(2)
90% - 10% fall time(2)
10
10
ns
tf(BCLK)
BCLK fall time
ns
(1) The BCLK minimum high or low pulse duration can be relaxed to 14 ns (to meet the timing specifications), if the SDOUT data line is
latched on the same BCLK edge polarity as the edge used by the device to transmit SDOUT data.
(2) The BCLK maximum rise and fall time can be relaxed to 13 ns if the BCLK frequency used in the system is below 20 MHz. Relaxing
the BCLK rise and fall time can cause noise to increase because of higher clock jitter.
7.8 Switching Characteristics: TDM, I2S or LJ Interface
at TA = 25°C, IOVDD = 3.3 V or 1.8 V and 20-pF load on all outputs (unless otherwise noted); see 图7-2 for timing diagram
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
td(SDOUT-BCLK)
td(SDOUT-FSYNC)
BCLK to SDOUT delay
50% of BCLK to 50% of SDOUT
3
18
ns
FSYNC to SDOUT delay in TDM
or LJ mode (for MSB data with
TX_OFFSET = 0)
50% of FSYNC to 50% of
SDOUT
18
ns
BCLK output clock frequency:
master mode (1)
f(BCLK)
24.576
MHz
ns
BCLK high pulse duration: master
mode
tH(BCLK)
tL(BCLK)
td(FSYNC)
14
14
3
BCLK low pulse duration: master
mode
ns
BCLK to FSYNC delay: master
mode
50% of BCLK to 50% of FSYNC
18
ns
tr(BCLK)
tf(BCLK)
BCLK rise time: master mode
BCLK fall time: master mode
10% - 90% rise time
90% - 10% fall time
8
8
ns
ns
(1) The BCLK output clock frequency must be lower than 18.5 MHz (to meet the timing specifications), if the SDOUT data line is latched
on the opposite BCLK edge polarity than the edge used by the device to transmit SDOUT data.
Timing Requirements: PDM Digital Microphone Interface
at TA = 25°C, IOVDD = 3.3 V or 1.8 V and 20-pF load on all outputs (unless otherwise noted); see Figure 7-3 for timing
diagram
MIN
30
0
NOM
MAX
UNIT
ns
tSU(PDMDINx)
tHLD(PDMDINx)
PDMDINx setup time
PDMDINx hold time
ns
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7.9 Switching Characteristics: PDM Digial Microphone Interface
at TA = 25°C, IOVDD = 3.3 V or 1.8 V and 20-pF load on all outputs (unless otherwise noted); see Figure 7-3 for timing
diagram
PARAMETER
TEST CONDITIONS
MIN
0.768
72
TYP
MAX
UNIT
MHz
ns
f(PDMCLK)
tH(PDMCLK)
tL(PDMCLK)
tr(PDMCLK)
tf(PDMCLK)
PDMCLK clock frequency
PDMCLK high pulse duration
PDMCLK low pulse duration
PDMCLK rise time
6.144
72
ns
10% - 90% rise time
18
18
ns
PDMCLK fall time
90% - 10% fall time
ns
7.10 Timing Diagrams
SDA
tBUF
tHD;STA
tLOW
tr
td(SDA)
SCL
tHD;STA
tHD;DAT
tHIGH
tSU;DAT
tSU;STA
tSU;STO
STO
STA
tf
STA
STO
图7-1. I2C Interface Timing Diagram
FSYNC
tSU(FSYNC)
tHLD(FSYNC)
t(BCLK)
tL(BCLK)
BCLK
tH(BCLK)
tr(BCLK)
tf(BCLK)
td(FSYNC)
td(SDOUT-BCLK)
td(SDOUT-FSYNC)
SDOUT
图7-2. TDM (With BCLK_POL = 1), I2S, and LJ Interface Timing Diagram
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tSU(PDMDINx)
tHLD(PDMDINx) tSU(PDMDINx)
tHLD(PDMDINx)
tH(PDMCLK)
tL(PDMCLK)
PDMCLK
PDMDINx
t(PDMCLK)
tf(PDMCLK)
tr(PDMCLK)
Falling Edge Captured
Rising Edge Captured
图7-3. PDM Digital Microphone Interface Timing Diagram
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7.11 Typical Characteristics
at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, fIN = 1-kHz sinusoidal signal, fS = 48 kHz, 32-bit audio data, BCLK = 256 × fS,
TDM slave mode, PLL on, differential input, channel gain = 0 dB, and linear phase decimation filter (unless otherwise noted);
all performance measurements are done with a 20-kHz, low-pass filter, and an A-weighted filter
-60
-60
Channel-1
Channel-2
Channel-1
Channel-2
-70
-70
-80
-80
-90
-90
-100
-110
-120
-130
-100
-110
-120
-130
-130
-115
-100
-85
-70
-55
-40
-25
-10
0
-130
-115
-100
-85
-70
-55
-40
-25
-10
0
Input Amplitude (dB)
Input Amplitude (dB)
TDH0D0+1
TDH0D0+2
Differential input
Single-ended input
图7-4. THD+N vs Input Amplitude
图7-5. THD+N vs Input Amplitude
-60
-70
-60
-70
Channel-1
Channel-2
Channel-1
Channel-2
-80
-80
-90
-90
-100
-110
-120
-130
-100
-110
-120
-130
-130
-115
-100
-85
-70
-55
-40
-25
-10
0
20 30 4050 70 100
200 300 500
1000 2000
5000 10000 20000
D004
Input Amplitude (dB)
Frequency (Hz)
TDH0D0+3
Differential input with AVDD = 1.8 V and VREF = 1.375 V
图7-6. THD+N vs Input Amplitude
图7-7. THD+N vs Input Frequency With a –60-dBr Input
-60
14
Channel-1
Channel-1
Channel-2
13
12
11
10
9
Channel-2
-70
-80
-90
8
7
-100
-110
-120
-130
6
5
4
3
2
1
20 30 4050 70 100
200 300 500
1000 2000
5000 10000 20000
D005
0
4
8
12
16
20
24
28
32
36
40
44
Frequency (Hz)
Channel Gain (dB)
TDH0D0+6
Differential input
图7-8. THD+N vs Input Frequency With a –1-dBr Input
图7-9. Input-Referred Noise vs Channel Gain
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7.11 Typical Characteristics (continued)
at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, fIN = 1-kHz sinusoidal signal, fS = 48 kHz, 32-bit audio data, BCLK = 256 × fS,
TDM slave mode, PLL on, differential input, channel gain = 0 dB, and linear phase decimation filter (unless otherwise noted);
all performance measurements are done with a 20-kHz, low-pass filter, and an A-weighted filter
14
13
12
11
10
9
20
10
Channel-1
Channel-2
Channel-1
Channel-2
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
8
7
6
5
4
3
2
1
0
4
8
12
16
20
24
28
32
36
40
44
20 30 50 70100 200300 500 1000 2000
5000 1000020000
100000
DF0re0q8
Channel Gain (dB)
Frequency (Hz)
TDH0D0+7
Single-ended input
图7-10. Input-Referred Noise vs Channel Gain
图7-11. Frequency Response With a –12-dBr Input
-60
0
Channel-1
Channel-2
Channel-1
Channel-2
-20
-70
-40
-60
-80
-90
-80
-100
-120
-140
-160
-180
-200
-100
-110
-120
-130
20 30 4050 70 100
200 300 500
1000 2000
5000 10000 20000
20 30 4050 70 100
200 300 500
1000 2000
5000 10000 20000
D010
Frequency (Hz)
Frequency (Hz)
D009
图7-12. Power-Supply Rejection Ratio vs Ripple Frequency
图7-13. Differential FFT With Idle Input
With 100-mVPP Amplitude
0
0
-20
Channel-1
Channel-1
Channel-2
Channel-2
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-180
-200
-100
-120
-140
-160
-180
-200
20 30 4050 70 100
200 300 500
1000 2000
5000 10000 20000
20 30 4050 70 100
200 300 500
1000 2000
5000 10000 20000
D011
Frequency (Hz)
Frequency (Hz)
图7-15. Single Ended FFT With Idle Input
图7-14. Differential FFT With a –60-dBr Input
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7.11 Typical Characteristics (continued)
at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, fIN = 1-kHz sinusoidal signal, fS = 48 kHz, 32-bit audio data, BCLK = 256 × fS,
TDM slave mode, PLL on, differential input, channel gain = 0 dB, and linear phase decimation filter (unless otherwise noted);
all performance measurements are done with a 20-kHz, low-pass filter, and an A-weighted filter
0
-20
0
-20
Channel-1
Channel-2
Channel-1
Channel-2
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-180
-200
-100
-120
-140
-160
-180
-200
20 30 4050 70 100
200 300 500
1000 2000
5000 10000 20000
20 30 4050 70 100
200 300 500
1000 2000
5000 10000 20000
D012
Frequency (Hz)
Frequency (Hz)
图7-16. Single Ended FFT With a –60-dBr Input
图7-17. Differential FFT With a –1-dBr Input
-60
-60
Channel-1
Channel-2
Channel-3
Channel-4
Channel-1
Channel-2
Channel-3
Channel-4
-70
-80
-70
-80
-90
-90
-100
-110
-120
-130
-100
-110
-120
-130
-130
-115
-100
-85
-70
-55
-40
-25
-10 -1
20 30 4050 70 100
200 300 500
1000 2000
5000 10000 20000
TDH0D2+2
Input Amplitude (dB)
Frequency (Hz)
TDH0D1+3
图7-18. PDM Input THD+N vs Input Amplitude
图7-19. PDM Input THD+N vs Input Frequency With a
–20-dBr Input
0
20
10
Channel-1
Channel-2
-20
-40
Channel-3
Channel-4
0
-10
-20
-30
-40
-50
-60
-70
-80
-60
-80
-100
-120
-140
-160
-180
-200
-90
Channel-1
Channel-2
Channel-3
-100
-110
Channel-4
-120
20 30 50 70100 200300 500 1000 2000
20 30 4050 70 100
200 300 500
1000 2000
5000 10000 20000
5000 1000020000
100000
Frequency (Hz)
Frequency (Hz)
Freq
D015
D016
图7-20. PDM Input FFT With a –60-dBr Input
图7-21. PDM Input Frequency Response With a
–20-dBr Input
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8 Detailed Description
8.1 Overview
The PCM3120-Q1 is a high-performance, low-power, flexible, 2-channel, audio analog-to-digital converter (ADC)
with extensive feature integration. This device is intended for applications in voice-activated systems,
professional microphones, audio conferencing, portable computing, communication, and entertainment
applications. The high dynamic range of the device enables far-field audio recording with high fidelity. This
device integrates a host of features that reduces cost, board space, and power consumption in space-
constrained, battery-powered, consumer, home, and industrial applications.
The PCM3120-Q1 consists of the following blocks:
• 2-channel, multibit, high-performance delta-sigma (ΔΣ) ADC
• Configurable single-ended or differential audio inputs
• Low-noise, programmable microphone bias output
• Automatic gain controller (AGC)
• Programmable decimation filters with a linear-phase filter or a low-latency filter
• Programmable channel gain, volume control, biquad filters for each channel
• Programmable phase and gain calibration with fine resolution for each channel
• Programmable high-pass filter (HPF), and digital channel mixer
• Pulse density modulation (PDM) microphone 4-channel interface with a high-performance decimation filter
• Integrated low-jitter phase-locked loop (PLL) supporting a wide range of system clocks
• Integrated digital and analog voltage regulators to support single-supply operation
Communication to the PCM3120-Q1 for configuring the control registers is supported using an I2C interface. The
device supports a highly flexible audio serial interface [time-division multiplexing (TDM), I2S, or left-justified (LJ)]
to transmit audio data seamlessly in the system across devices.
The PCM3120-Q1 can support multiple devices by sharing the common TDM bus across devices. Moreover, the
device includes a daisy-chain feature as well. These features relax the shared TDM bus timing requirements and
board design complexities when operating multiple devices for applications requiring high audio data bandwidth.
表8-1 lists the reference abbreviations used throughout this document to registers that control the device.
表8-1. Abbreviations for Register References
REFERENCE
ABBREVIATION
DESCRIPTION
EXAMPLE
Single data bit. The value of a
single bit in a register.
Page y, register z, bit k
Py_Rz_Dk
Page 4, register 36, bit 0 = P4_R36_D0
Range of data bits. A range of
data bits (inclusive).
Page y, register z, bits k-m
Page y, register z
Py_Rz_D[k:m]
Py_Rz
Page 4, register 36, bits 3-0 = P4_R36_D[3:0]
Page 4, register 36 = P4_R36
One entire register. All eight
bits in the register as a unit.
Range of registers. A range of
registers in the same page.
Page y, registers z-n
Py_Rz-Rn
Page 4, registers 36, 37, 38 = P4_R36-R38
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8.2 Functional Block Diagram
Audio Clock Generation
PLL
Multifunction Pins
(Digital Microphones
4-Channel Digital Microphone Filters
(Input Clock Source -
BCLK, GPIOx, GPIx)
GPIO1
Interface, Interrupt, PLL
Input Clock)
SDOUT
BCLK
IN1P
IN1M
ADC
Channel-1
PGA
PGA
Audio Serial
Interface (TDM,
I2S, LJ)
Digital Filters
IN2P_GPI1
ADC
Channel-2
(Low Latency LPF,
Programmable
Biquads, AGC)
FSYNC
IN2M_GPO1
Regulators, Current Bias
and Voltage Reference
Programmable
MICBIAS_GPI2
SDA
SCL
I2C Control
Interface
Microphone Bias
8.3 Feature Description
8.3.1 Serial Interfaces
This device has two serial interfaces: control and audio data. The control serial interface is used for device
configuration. The audio data serial interface is used for transmitting audio data to the host device.
8.3.1.1 Control Serial Interfaces
The device contains configuration registers and programmable coefficients that can be set to the desired values
for a specific system and application use. All registers can be accessed using I2C communication to the device.
For more information, see 节8.5 for further details.
8.3.1.2 Audio Serial Interfaces
Digital audio data flows between the host processor and the PCM3120-Q1 on the digital audio serial interface
(ASI), or audio bus. This highly flexible ASI bus includes a TDM mode for multichannel operation, support for I2S
or left-justified protocols format, programmable data length options, very flexible master-slave configurability for
bus clock lines, and the ability to communicate with multiple devices within a system directly.
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The bus protocol TDM, I2S, or left-justified (LJ) format can be selected by using the ASI_FORMAT[1:0]
(P0_R7_D[7:6]) register bits. As shown in 表 8-2 and 表 8-3, these modes are all most significant bit (MSB)-first,
pulse code modulation (PCM) data format, with the output channel data word-length programmable as 16, 20,
24, or 32 bits by configuring the ASI_WLEN[1:0] (P0_R7_D[5:4]) register bits.
表8-2. Audio Serial Interface Format
P0_R7_D[7:6] : ASI_FORMAT[1:0]
AUDIO SERIAL INTERFACE FORMAT
00 (default)
Time division multiplexing (TDM) mode
01
10
11
Inter IC sound (I2S) mode
Left-justified (LJ) mode
Reserved (do not use this setting)
表8-3. Audio Output Channel Data Word-Length
P0_R7_D[5:4] : ASI_WLEN[1:0]
AUDIO OUTPUT CHANNEL DATA WORD-LENGTH
00
01
Output channel data word-length set to 16 bits
Output channel data word-length set to 20 bits
Output channel data word-length set to 24 bits
Output channel data word-length set to 32 bits
10
11 (default)
The frame sync pin, FSYNC, is used to define the beginning of a frame and has the same frequency as the
output data sample rates. The bit clock pin, BCLK, is used to clock out the digital audio data across the serial
bus. The number of bit-clock cycles in a frame must accommodate all active output channels with the
programmed data word length.
A frame consists of multiple time-division channel slots (up to 64) on the audio bus. This allows for either a single
device or multiple PCM3120-Q1 devices sharing the same bus. The device supports up to four output channels
that can be configured to place their audio data on bus slot 0 to slot 63. 表 8-4 lists the output channel slot
configuration settings. In I2S and LJ mode, the slots are divided into two sets, left-channel slots and right-
channel slots, as described in 节8.3.1.2.2 and 节8.3.1.2.3 .
表8-4. Output Channel Slot Assignment Settings
P0_R11_D[5:0] : CH1_SLOT[5:0]
00 0000 = 0d (default)
00 0001 = 1d
OUTPUT CHANNEL 1 SLOT ASSIGNMENT
Slot 0 for TDM or left slot 0 for I2S, LJ.
Slot 1 for TDM or left slot 1 for I2S, LJ.
…
…
01 1111 = 31d
10 0000 = 32d
Slot 31 for TDM or left slot 31 for I2S, LJ.
Slot 32 for TDM or right slot 0 for I2S, LJ.
…
…
11 1110 = 62d
11 1111 = 63d
Slot 62 for TDM or right slot 30 for I2S, LJ.
Slot 63 for TDM or right slot 31 for I2S, LJ.
Similarly, the slot assignment setting for output channel 2 to channel 8 can be done using the CH2_SLOT
(P0_R12) to CH8_SLOT (P0_R18) registers, respectively.
The slot word length is the same as the output channel data word length set for the device. The output channel
data word length must be set to the same value for all PCM3120-Q1 devices if all devices share the same ASI
bus in a system. The maximum number of slots possible for the ASI bus in a system is limited by the available
bus bandwidth, which depends upon the BCLK frequency, output data sample rate used, and the channel data
word length configured.
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The device also includes a feature that offsets the start of the slot data transfer with respect to the frame sync by
up to 31 cycles of the bit clock. 表8-5 lists the programmable offset configuration settings.
表8-5. Programmable Offset Settings for the ASI Slot Start
P0_R8_D[4:0] : TX_OFFSET[4:0]
PROGRAMMABLE OFFSET SETTING FOR SLOT DATA TRANSMISSION START
0 0000 = 0d (default)
The device follows the standard protocol timing without any offset.
Slot start is offset by one BCLK cycle, as compared to standard protocol timing.
For I2S or LJ, the left and right slot start is offset by one BCLK cycle, as compared to
standard protocol timing.
0 0001 = 1d
......
......
Slot start is offset by 30 BCLK cycles, as compared to standard protocol timing.
For I2S or LJ, the left and right slot start is offset by 30 BCLK cycles, as compared to
standard protocol timing.
1 1110 = 30d
Slot start is offset by 31 BCLK cycles, as compared to standard protocol timing.
For I2S or LJ, the left and right slot start is offset by 31 BCLK cycles, as compared to
standard protocol timing.
1 1111 = 31d
The device also features the ability to invert the polarity of the frame sync pin, FSYNC, used to transfer the audio
data as compared to the default FSYNC polarity used in standard protocol timing. This feature can be set using
the FSYNC_POL (P0_R7_D3) register bit. Similarly, the device can invert the polarity of the bit clock pin, BCLK,
which can be set using the BCLK_POL (P0_R7_D2) register bit.
8.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
In TDM mode, also known as DSP mode, the rising edge of FSYNC starts the data transfer with the slot 0 data
first. Immediately after the slot 0 data transmission, the remaining slot data are transmitted in order. FSYNC and
each data bit (except the MSB of slot 0 when TX_OFFSET equals 0) is transmitted on the rising edge of BCLK.
图8-1 to 图8-4 illustrate the protocol timing for TDM operation with various configurations.
FSYNC
BCLK
SDOUT
N-1 N-2 N-3
2
1
0
N-1 N-2 N-3
2
1
0
N-1 N-2 N-3
2
1
0
N-1 N-2 N-3
2
1
0
Slot-1
(Word Length : N)
Slot-0
(Word Length : N)
Slot-2 to Slot-7
(Word Length : N)
Slot-0
(Word Length : N)
(n+1)th Sample
nth Sample
图8-1. TDM Mode Standard Protocol Timing (TX_OFFSET = 0)
FSYNC
BCLK
SDOUT
N-1
2
1
0
N-1 N-2 N-3
2
1
0
N-1 N-2 N-3
2
1
0
N-1
2
1
0
Slot-1
(Word Length : N)
Slot-0
(Word Length : N)
nth Sample
Slot-0
(Word Length : N)
(n+1)th Sample
Slot-2 to Slot-7
(Word Length : N)
TX_OFFSET = 2
TX_OFFSET = 2
图8-2. TDM Mode Protocol Timing (TX_OFFSET = 2)
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FSYNC
BCLK
1
0
N-1
2
1
0
N-1 N-2 N-3
2
1
0
2
1
0
N-1 N-2 N-3
0
N-1 N-2
3
2
1
0
N-1
SDOUT
Slot-1
(Word Length : N)
Slot-0
(Word Length : N)
Slot-0
(Word Length : N)
(n+1)th Sample
Slot-2 to Slot-7
(Word Length : N)
TX_OFFSET = 2
nth Sample
图8-3. TDM Mode Protocol Timing (No Idle BCLK Cycles, TX_OFFSET = 2)
FSYNC
BCLK
SDOUT
N-1 N-2 N-3
2
1
0
N-1 N-2 N-3
2
1
0
N-1 N-2 N-3
2
1
0
N-1 N-2 N-3
2
1
0
Slot-1
(Word Length : N)
Slot-0
(Word Length : N)
Slot-2 to Slot-7
(Word Length : N)
Slot-0
(Word Length : N)
(n+1)th Sample
nth Sample
图8-4. TDM Mode Protocol Timing (TX_OFFSET = 0 and BCLK_POL = 1)
For proper operation of the audio bus in TDM mode, the number of bit clocks per frame must be greater than or
equal to the number of active output channels times the programmed word length of the output channel data.
The device supports FSYNC as a pulse with a 1-cycle-wide bit clock, but also supports multiples as well. For a
higher BCLK frequency operation, using TDM mode with a TX_OFFSET value higher than 0 is recommended.
8.3.1.2.2 Inter IC Sound (I2S) Interface
The standard I2S protocol is defined for only two channels: left and right. The device extends the same protocol
timing for multichannel operation. In I2S mode, the MSB of the left slot 0 is transmitted on the falling edge of
BCLK in the second cycle after the falling edge of FSYNC. Immediately after the left slot 0 data transmission, the
remaining left slot data are transmitted in order. The MSB of the right slot 0 is transmitted on the falling edge of
BCLK in the second cycle after the rising edge of FSYNC. Immediately after the right slot 0 data transmission,
the remaining right slot data are transmitted in order. FSYNC and each data bit is transmitted on the falling edge
of BCLK. 图8-5 to 图8-8 illustrate the protocol timing for I2S operation with various configurations.
FSYNC
BCLK
SDOUT
N-1 N-2
1
0
N-1 N-2
1
0
N-1
1
0
N-1 N-2
N-1 N-2
1
0
1
0
Left
Slot-0
(Word Length : N)
Left
Slot-2 to Slot-3
(Word Length : N)
Right
Slot-0
Right
Slot-2 to Slot-3
(Word Length : N) (Word Length : N)
Left
Slot-0
(Word Length : N)
(n+1)th Sample
nth Sample
图8-5. I2S Mode Standard Protocol Timing (TX_OFFSET = 0)
FSYNC
BCLK
SDOUT
N-1
1
0
N-1 N-2
1
0
N-1
1
0
N-1
N-1
1
0
1
0
Left
Slot-0
(Word Length : N) (Word Length : N)
Left
Slot-2 to Slot-3
Right
Slot-0
Right
Slot-2 to Slot-3
(Word Length : N) (Word Length : N)
Left
Slot-0
(Word Length : N)
(n+1)th Sample
TX_OFFSET = 1
TX_OFFSET = 1
TX_OFFSET = 1
nth Sample
图8-6. I2S Protocol Timing (TX_OFFSET = 1)
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FSYNC
BCLK
N-1 N-2
1
0
N-1 N-2
0
0
N-1
1
0
N-1
1
0
N-1 N-2
0
N-1
1
0
1
0
N-1 N-2
SDOUT
Left
Slot-0
(Word Length : N)
(n+1)th Sample
Left
Slot-1 to Slot-3
(Word Length : N)
Right
Slot-1 to Slot-3
(Word Length : N)
nth Sample
图8-7. I2S Protocol Timing (No Idle BCLK Cycles, TX_OFFSET = 0)
FSYNC
BCLK
SDOUT
N-1 N-2
1
0
N-1 N-2
1
0
N-1
1
0
N-1 N-2
N-1 N-2
1
0
1
0
Left
Slot-0
(Word Length : N)
Left
Slot-2 to Slot-3
(Word Length : N)
Right
Slot-0
Right
Slot-2 to Slot-3
(Word Length : N) (Word Length : N)
Left
Slot-0
(Word Length : N)
(n+1)th Sample
nth Sample
图8-8. I2S Protocol Timing (TX_OFFSET = 0 and BCLK_POL = 1)
For proper operation of the audio bus in I2S mode, the number of bit clocks per frame must be greater than or
equal to the number of active output channels (including left and right slots) times the programmed word length
of the output channel data. The device FSYNC low pulse must be a number of BCLK cycles wide that is greater
than or equal to the number of active left slots times the data word length configured. Similarly, the FSYNC high
pulse must be a number of BCLK cycles wide that is greater than or equal to the number of active right slots
times the data word length configured.
8.3.1.2.3 Left-Justified (LJ) Interface
The standard LJ protocol is defined for only two channels: left and right. The device extends the same protocol
timing for multichannel operation. In LJ mode, the MSB of the left slot 0 is transmitted in the same BCLK cycle
after the rising edge of FSYNC. Each subsequent data bit is transmitted on the falling edge of BCLK.
Immediately after the left slot 0 data transmission, the remaining left slot data are transmitted in order. The MSB
of the right slot 0 is transmitted in the same BCLK cycle after the falling edge of FSYNC. Each subsequent data
bit is transmitted on the falling edge of BCLK. Immediately after the right slot 0 data transmission, the remaining
right slot data are transmitted in order. FSYNC is transmitted on the falling edge of BCLK. 图 8-9 to 图 8-12
illustrate the protocol timing for LJ operation with various configurations.
FSYNC
BCLK
SDOUT
N-1 N-2
1
0
N-1 N-2
1
0
N-1
1
0
N-1 N-2
N-1 N-2
1
0
1
0
Left
Slot-0
(Word Length : N)
Left
Slot-2 to Slot-3
(Word Length : N)
Right
Slot-0
Right
Slot-2 to Slot-3
(Word Length : N) (Word Length : N)
Left
Slot-0
(Word Length : N)
(n+1)th Sample
nth Sample
图8-9. LJ Mode Standard Protocol Timing (TX_OFFSET = 0)
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FSYNC
BCLK
SDOUT
N-1
1
0
N-1 N-2
1
0
N-1
1
0
N-1
N-1
1
0
1
0
Left
Slot-0
(Word Length : N) (Word Length : N)
Left
Slot-2 to Slot-3
Right
Slot-0
Right
Slot-2 to Slot-3
(Word Length : N) (Word Length : N)
Left
Slot-0
(Word Length : N)
(n+1)th Sample
TX_OFFSET = 2
TX_OFFSET = 2
TX_OFFSET = 2
nth Sample
图8-10. LJ Protocol Timing (TX_OFFSET = 2)
FSYNC
BCLK
N-1 N-2
1
0
N-1 N-2
0
0
N-1
1
0
N-1
1
0
N-1 N-2
0
N-1
1
0
N-1 N-2
1
0
SDOUT
Left
Slot-0
(Word Length : N)
(n+1)th Sample
Left
Slot-1 to Slot-3
(Word Length : N)
Right
Slot-1 to Slot-3
(Word Length : N)
nth Sample
图8-11. LJ Protocol Timing (No Idle BCLK Cycles, TX_OFFSET = 0)
FSYNC
BCLK
SDOUT
N-1 N-2
1
0
N-1 N-2
1
0
N-1
1
0
N-1 N-2
N-1 N-2
1
0
1
0
Left
Slot-0
(Word Length : N)
Left
Slot-2 to Slot-3
(Word Length : N)
Right
Slot-0
Right
Slot-2 to Slot-3
(Word Length : N) (Word Length : N)
Left
Slot-0
(Word Length : N)
(n+1)th Sample
TX_OFFSET = 1
TX_OFFSET = 1
TX_OFFSET = 1
nth Sample
图8-12. LJ Protocol Timing (TX_OFFSET = 1 and BCLK_POL = 1)
For proper operation of the audio bus in LJ mode, the number of bit clocks per frame must be greater than or
equal to the number of active output channels (including left and right slots) times the programmed word length
of the output channel data. The device FSYNC high pulse must be a number of BCLK cycles wide that is greater
than or equal to the number of active left slots times the data word length configured. Similarly, the FSYNC low
pulse must be number of BCLK cycles wide that is greater than or equal to the number of active right slots times
the data word length configured. For a higher BCLK frequency operation, using LJ mode with a TX_OFFSET
value higher than 0 is recommended.
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8.3.1.3 Using Multiple Devices With Shared Buses
The device has many supported features and flexible options that can be used in the system to seamlessly
connect the PCM3120-Q1 and any other audio device by sharing a single common I2C control bus and an audio
serial interface bus. This architecture enables multiple applications to be applied to a system that require a
microphone array for beam-forming operations, audio conferencing, noise cancellation, and so forth. 图 8-13
shows a diagram of the PCM3120-Q1 and PCMx140-Q1 devices in a configuration where the control and audio
data buses are shared.
Control Bus – I2C Interface
PCMx120-Q1
U1
PCMx140-Q1
U2
Host Processor
Audio Data Bus – TDM, I2S, LJ Interface
图8-13. Multiple Devices With Shared Control and Audio Data Buses
The PCM3120-Q1 consists of the following features to enable seamless connection and interaction of multiple
devices using a shared bus:
• I2C broadcast simultaneously writes to (or triggers) all PCM3120-Q1 and PCMx140-Q1 devices
• Supports up to 64 configuration output channel slots for the audio serial interface
• Tri-state feature (with enable and disable) for the unused audio data slots of the device
• Supports a bus-holder feature (with enable and disable) to keep the last driven value on the audio bus
• The GPIO1 or GPOx pin can be configured as a secondary output data lane for the audio serial interface
• The GPIO1 or GPIx pin can be used in a daisy-chain configuration of multiple devices
• Supports one BCLK cycle data latching timing to relax the timing requirement for the high-speed interface
• Programmable master and slave options for the audio serial interface
• Ability to synchronize the multiple devices for the simultaneous sampling requirement across devices
See the Multiple TLV320ADCx140 Devices With Shared TDM and I2C Bus application report for further details.
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8.3.2 Phase-Locked Loop (PLL) and Clock Generation
The device has a smart auto-configuration block to generate all necessary internal clocks required for the ADC
modulator and the digital filter engine used for signal processing. This configuration is done by monitoring the
frequency of the FSYNC and BCLK signal on the audio bus.
The device supports the various output data sample rates (of the FSYNC signal frequency) and the BCLK to
FSYNC ratio to configure all clock dividers, including the PLL configuration, internally without host programming.
表8-6 and 表8-7 list the supported FSYNC and BCLK frequencies.
表8-6. Supported FSYNC (Multiples or Submultiples of 48 kHz) and BCLK Frequencies
BCLK (MHz)
BCLK TO
FSYNC
RATIO
FSYNC
(8 kHz)
FSYNC
(16 kHz)
FSYNC
(24 kHz)
FSYNC
(32 kHz)
FSYNC
(48 kHz)
FSYNC
(96 kHz)
FSYNC (192 FSYNC (384 FSYNC (768
kHz)
kHz)
kHz)
16
24
Reserved
Reserved
0.256
0.256
0.384
0.384
0.576
0.512
0.768
0.768
1.152
1.536
2.304
3.072
6.144
12.288
4.608
9.216
18.432
32
0.512
0.768
1.024
1.536
3.072
6.144
12.288
24.576
48
0.384
0.768
1.152
1.536
2.304
4.608
9.216
18.432
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
64
0.512
1.024
1.536
2.048
3.072
6.144
12.288
24.576
96
0.768
1.536
2.304
3.072
4.608
9.216
18.432
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
128
192
256
384
512
1024
2048
1.024
2.048
3.072
4.096
6.144
12.288
18.432
24.576
Reserved
Reserved
Reserved
Reserved
24.576
1.536
3.072
4.608
6.144
9.216
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
2.048
4.096
6.144
8.192
12.288
18.432
24.576
Reserved
Reserved
3.072
6.144
9.216
12.288
16.384
Reserved
Reserved
4.096
8.192
12.288
24.576
Reserved
8.192
16.384
Reserved
16.384
表8-7. Supported FSYNC (Multiples or Submultiples of 44.1 kHz) and BCLK Frequencies
BCLK (MHz)
BCLK TO
FSYNC
RATIO
FSYNC
(7.35 kHz)
FSYNC
FSYNC
FSYNC
FSYNC
(44.1 kHz)
FSYNC
FSYNC
FSYNC
FSYNC
(14.7 kHz) (22.05 kHz) (29.4 kHz)
(88.2 kHz) (176.4 kHz) (352.8 kHz) (705.6 kHz)
16
24
Reserved
Reserved
Reserved
0.3528
Reserved
0.3528
0.4704
0.7056
0.9408
1.4112
0.3528
0.5292
0.7056
1.0584
1.4112
0.4704
0.7056
0.7056
1.0584
1.4112
2.1168
2.8224
4.2336
5.6448
8.4672
11.2896
16.9344
32
0.9408
1.4112
2.8224
5.6448
11.2896
22.5792
48
1.4112
2.1168
4.2336
8.4672
16.9344
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
64
0.4704
1.8816
2.8224
5.6448
11.2896
22.5792
96
0.7056
2.1168
2.8224
4.2336
8.4672
16.9344
22.5792
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
128
192
256
384
512
1024
2048
0.9408
1.8816
2.8224
3.7632
5.6448
7.5264
15.0528
Reserved
2.8224
4.2336
5.6448
8.4672
11.2896
22.5792
Reserved
3.7632
5.6448
11.2896
16.9344
22.5792
Reserved
Reserved
Reserved
Reserved
1.4112
5.6448
8.4672
1.8816
7.5264
11.2896
16.9344
22.5792
Reserved
Reserved
2.8224
11.2896
15.0528
Reserved
Reserved
3.7632
7.5264
15.0528
The status register ASI_STS (P0_R21), captures the device auto detect result for the FSYNC frequency and the
BCLK to FSYNC ratio. If the device finds any unsupported combinations of FSYNC frequency and BCLK to
FSYNC ratios, the device generates an ASI clock-error interrupt and mutes the record channels accordingly.
The device uses an integrated, low-jitter, phase-locked loop (PLL) to generate internal clocks required for the
ADC modulator and digital filter engine, as well as other control blocks. The device also supports an option to
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use BCLK, GPIO1, or the GPIx pin (as MCLK) as the audio clock source without using the PLL to reduce power
consumption. However, the ADC performance may degrade based on jitter from the external clock source, and
some processing features may not be supported if the external audio clock source frequency is not high enough.
Therefore, TI recommends using the PLL for high-performance applications. More details and information on
how to configure and use the device in low-power mode without using the PLL are discussed in the
TLV320ADCx120 Power Consumption Matrix Across Various Usage Scenarios application report.
The device also supports an audio bus master mode operation using the GPIO1 or GPIx pin (as MCLK) as the
reference input clock source and supports various flexible options and a wide variety of system clocks. More
details and information on master mode configuration and operation are discussed in the Configuring and
Operating TLV320ADCx120 as an Audio Bus Master application report.
The audio bus clock error detection and auto-detect feature automatically generates all internal clocks, but can
be disabled using the ASI_ERR (P0_R9_D5) and AUTO_CLK_CFG (P0_R19_D6) register bits, respectively. In
the system, this disable feature can be used to support custom clock frequencies that are not covered by the
auto detect scheme. For such application use cases, care must be taken to ensure that the multiple clock
dividers are all configured appropriately. Therefore, TI recommends using the PPC3 GUI for device configuration
settings; for more details see the ADCx120EVM-PDK Evaluation module user's guide and the PurePath™
console graphical development suite.
8.3.3 Input Channel Configurations
The device consists of two pairs of analog input pins (INxP and INxM) that can be configured as differential
inputs or single-ended inputs for the recording channel. The device supports simultaneous recording of up to two
channels using the high-performance multichannel ADC. The input source for the analog pins can be from
electret condenser analog microphones, micro-electro-mechanical system (MEMS) analog microphones, or line-
in (auxiliary) inputs from the system board. Additionally, if the application uses digital PDM microphones for the
recording, then the IN2P_GPI1, IN2M_GPO1, GPIO1, and MICBIAS_GPI2 pins can be reconfigured in the
device to support up to four channels for the digital microphone recording. The device can also support
simultaneous recording on two analog and two digital microphone channels. 表 8-8 shows the input source
selection for the record channel.
表8-8. Input Source Selection for the Record Channel
P0_R60_D[6:5] : CH1_INSRC[1:0]
INPUT CHANNEL 1 RECORD SOURCE SELECTION
Analog differential input for channel 1 (this setting is valid only when the GPI1 and GPO1 pin
functions are disabled)
00 (default)
Analog single-ended input for channel 1 (this setting is valid only when the GPI1 and GPO1
pin functions are disabled)
01
Digital PDM input for channel 1 (configure the GPIx and GPOx pin accordingly for PDMDIN1
and PDMCLK)
10
11
Reserved (do not use this setting)
Similarly, the input source selection setting for input channel 2, channel 3, and channel 4 can be configured
using the CH2_INSRC[1:0] (P0_R65_D[6:5]), CH3_INSRC[1:0] (P0_R70_D[6:5]), and CH4_INSRC[1:0]
(P0_R75_D[6:5]) register bits, respectively.
Typically, voice or audio signal inputs are capacitively coupled (AC coupled) to the device; however, the device
also supports an option for DC-coupled inputs to save board space. This configuration can be done
independently for each channel by setting the CH1_DC (P0_R60_D4), CH2_DC (P0_R65_D4), CH3_DC
(P0_R70_D4), and CH4_DC (P0_R75_D4) register bits. The INxM pin can be directly grounded in DC-coupled
mode (see 图 8-14), but the INxM pin must be grounded after the AC-coupling capacitor in AC-coupled mode
(see 图 8-15) for the single-ended input configuration. For the best dynamic range performance, the differential
AC-coupled input must be used .
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Line or
Line or
Microphone
Single-ended
Input
Microphone
Single-ended
Input
INxP
INxM
INxP
INxM
GND
PCMx120-Q1
PCMx120-Q1
GND
图8-14. Single-Ended, DC-Coupled Input
图8-15. Single-Ended, AC-Coupled Input
Connection
Connection
The device allows for flexibility in choosing the typical input impedance on INxP or INxM from 2.5 kΩ (default),
10 kΩ, and 20 kΩ based on the input source impedance. The higher input impedance results in slightly higher
noise or lower dynamic range. 表 8-9 lists the configuration register settings for the input impedance for the
record channel.
表8-9. Input Impedance Selection for the Record Channel
P0_R60_D[3:2] : CH1_IMP[1:0]
CHANNEL 1 INPUT IMPEDANCE SELECTION
Channel 1 input impedance typical value is 2.5 kΩ on INxP or INxM
Channel 1 input impedance typical value is 10 kΩ on INxP or INxM
Channel 1 input impedance typical value is 20 kΩ on INxP or INxM
Reserved (do not use this setting)
00 (default)
01
10
11
Similarly, the input impedance selection setting for input channel 2 can be configured using the CH2_IMP[1:0]
(P0_R65_D[3:2]) register bits.
The value of the coupling capacitor in AC-coupled mode must be chosen so that the high-pass filter formed by
the coupling capacitor and the input impedance do not affect the signal content. Before proper recording can
begin, this coupling capacitor must be charged up to the common-mode voltage at power up. To enable quick
charging, the device has modes to speed up the charging of the coupling capacitor. The default value of the
quick-charge timing is set for a coupling capacitor up to 1 µF. However, if a higher-value capacitor is used in the
system, then the quick-charging timing can be increased by using the INCAP_QCHG (P0_R5_D[5:4]) register
bits. For best distortion performance, use the low-voltage coefficient capacitors for AC coupling.
The PCM3120-Q1 can also support a higher input common-mode tolerance at the expense of noise
performance by a few decibels. The device supports three different modes with different common-mode
tolerances, which can be configured using the CH1_INP_CM_TOL_CFG[1:0] (P0_R58_D[7:6]) register bits. 表
8-10 lists the configuration register settings for the input impedance for the record channel.
表8-10. Common-Mode Tolerance Mode Selection for Record Channel
P0_R58_D[7:6] :
CHANNEL 1 INPUT COMMON-MODE TOLERANCE
CH1_INP_CM_TOL_CFG[1:0]
Channel 1 input common-mode tolerance of: AC-coupled input = 100 mVPP, DC-coupled
00 (default)
01
input = 2.82 VPP
.
Channel 1 input common-mode tolerance of: AC/DC-coupled input = 1 VPP
.
Channel 1 input common-mode tolerance of: AC/DC-coupled input = 0-AVDD (supported
only with an input impedance of 10 kΩ and 20 kΩ). For input impedance of 2.5 kΩ, the input
common-mode tolerance is 0.4 V to 2.6 V.
10 (high CMRR mode)
11
Reserved (do not use this setting)
Similarly, the common-mode tolerance setting for input channel 2 can be configured using the
CH2_INP_CM_TOL_CFG[1:0] (P0_R58_D[5:4]) register bits. See the Input Common Mode Tolerance and High
CMRR modes for TLV320ADCx120 Devices application report for further details.
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8.3.4 Reference Voltage
All audio data converters require a DC reference voltage. The PCM3120-Q1 achieves low-noise performance by
internally generating a low-noise reference voltage. This reference voltage is generated using a band-gap circuit
with high PSRR performance. This audio converter reference voltage must be filtered externally using a
minimum 1-µF capacitor connected from the VREF pin to analog ground (AVSS).
The value of this reference voltage can be configured using the P0_R59_D[1:0] register bits and must be set to
an appropriate value based on the desired full-scale input for the device and the AVDD supply voltage available
in the system. The default VREF value is set to 2.75 V, which in turn supports a 2-VRMS differential full-scale
input to the device. The required minimum AVDD voltage for this mode is 3 V. 表 8-11 lists the various VREF
settings supported along with required AVDD range and the supported full-scale input signal for that
configuration.
表8-11. VREF Programmable Settings
VREF OUTPUT
VOLTAGE (Same as
Internal ADC VREF)
DIFFERENTIAL FULL-
SCALE INPUT
SINGLE-ENDED FULL-
SCALE INPUT
P0_R59_D[1:0] :
ADC_FSCALE[1:0]
AVDD RANGE
REQUIREMENT
SUPPORTED
SUPPORTED
00 (default)
2.75 V
2.5 V
2 VRMS
1.818 VRMS
1 VRMS
1 VRMS
0.909 VRMS
0.5 VRMS
Reserved
3 V to 3.6 V
2.8 V to 3.6 V
1.7 V to 1.9 V
Reserved
01
10
11
1.375 V
Reserved
Reserved
To achieve low-power consumption, this audio reference block is powered down as described in the 节 8.4.1
section. When exiting sleep mode, the audio reference block is powered up using the internal fast-charge
scheme and the VREF pin settles to its steady-state voltage after the settling time (a function of the decoupling
capacitor on the VREF pin). This time is approximately equal to 3.5 ms when using a 1-μF decoupling capacitor.
If a higher-value decoupling capacitor is used on the VREF pin, the fast-charge setting must be reconfigured
using the VREF_QCHG (P0_R2_D[4:3]) register bits, which support options of 3.5 ms (default), 10 ms, 50 ms, or
100 ms.
8.3.5 Programmable Microphone Bias
The device integrates a built-in, low-noise microphone bias pin that can be used in the system for biasing
electret-condenser microphones or providing the supply to the MEMS analog or digital microphone. The
integrated bias amplifier supports up to 5 mA of load current that can be used for multiple microphones and is
designed to provide a combination of high PSRR, low noise, and programmable bias voltages to allow the
biasing to be fine tuned for specific microphone combinations.
When using this MICBIAS pin for biasing or supplying to multiple microphones, avoid any common impedance
on the board layout for the MICBIAS connection to minimize coupling across microphones. 表 8-12 shows the
available microphone bias programmable options.
表8-12. MICBIAS Programmable Settings
P0_R59_D[6:4] : MBIAS_VAL[2:0]
P0_R59_D[1:0] : ADC_FSCALE[1:0]
MICBIAS OUTPUT VOLTAGE
2.75 V (same as the VREF output)
2.5 V (same as the VREF output)
1.375 V (same as the VREF output)
3.014 V (1.096 times the VREF output)
2.740 V (1.096 times the VREF output)
1.507 V (1.096 times the VREF output)
Reserved (do not use these settings)
Same as AVDD
00 (default)
000 (default)
01
10
00 (default)
001
01
10
010 to 101
110
XX
XX
XX
111
Reserved (do not use this setting)
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The microphone bias output can be powered on or powered off (default) by configuring the MICBIAS_PDZ
(P0_R117_D7) register bit. Additionally, the device provides an option to configure the GPIO1 or GPIx pin to
directly control the microphone bias output powering on or off. This feature is useful to control the microphone
directly without engaging the host for I2C communication. The MICBIAS_PDZ (P0_R117_D7) register bit value is
ignored if the GPIO1 or GPIx pin is configured to set the microphone bias on or off.
8.3.6 Signal-Chain Processing
The PCM3120-Q1 signal chain is comprised of very-low-noise, high-performance, and low-power analog blocks
and highly flexible and programmable digital processing blocks. The high performance and flexibility combined
with a compact package makes the PCM3120-Q1 optimized for a variety of end-equipments and applications
that require multichannel audio capture. 图 8-16 shows a conceptual block diagram that highlights the various
building blocks used in the signal chain, and how the blocks interact in the signal chain.
PDMCLK
PDM
Interface
PDMIN
Digital Microphone
M
U
X
Phase
Calibration
Decimation
Filters
INP
INM
PGA
ADC
Output
Channel
Data to ASI
Gain
Calibration
Digital
Summer/Mixer
Biquad
Filters
Digital Volume
Control (DVC)
HPF
Other Input Channels Processed Data
after Gain Calibration
图8-16. Signal-Chain Processing Flowchart
The front-end PGA is very low noise, with a -dB dynamic range performance. Along with a low-noise and low-
distortion, multibit, delta-sigma ADC, the front-end PGA enables the PCM3120-Q1 to record a far-field audio
signal with very high fidelity, both in quiet and loud environments. Moreover, the ADC architecture has inherent
antialias filtering with a high rejection of out-of-band frequency noise around multiple modulator frequency
components. Therefore, the device prevents noise from aliasing into the audio band during ADC sampling.
Further on in the signal chain, an integrated, high-performance multistage digital decimation filter sharply cuts off
any out-of-band frequency noise with high stop-band attenuation.
The device also has an integrated programmable biquad filters that allows for custom low-pass, high-pass, or
any other desired frequency shaping. Thus, the overall signal chain architecture removes the requirement to add
external components for antialiasing low-pass filtering, and thus saves drastically on the external system
component cost and board space. See the TLV320ADCx140 Integrated Analog Anti-Aliasing Filter and Flexible
Digital Filter application report for further details.
The signal chain also consists of various highly programmable digital processing blocks such as phase
calibration, gain calibration, high-pass filter, digital summer or mixer, biquad filters, and volume control. The
details on these processing blocks are discussed further in this section. The device also supports up to four
digital PDM microphone recording channels when the analog record channels are not used. Channels 1 to 2 in
the signal chain block diagram of 图 8-16 are as described in this section, however, channels 3 to 4 only support
the digital microphone recording option and do not support the digital summer or mixer option.
The desired input channels for recording can be enabled or disabled by using the IN_CH_EN (P0_R115)
register, and the output channels for the audio serial interface can be enabled or disabled by using the
ASI_OUT_EN (P0_R116) register. In general, the device supports simultaneous power-up and power-down of all
active channels for simultaneous recording. However, based on the application needs, if some channels must be
powered-up or powered-down dynamically when the other channel recording is on, then that use case is
supported by setting the DYN_CH_PUPD_EN (P0_R117_D4) register bit to 1'b1.
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The device supports an input signal bandwidth up to 80 kHz, which allows the high-frequency non-audio signal
to be recorded by using a 176.4-kHz (or higher) sample rate.
For output sample rates of 48 kHz or lower, the device supports all features for 4-channel recording and various
programmable processing blocks. However, for output sample rates higher than 48 kHz, there are limitations in
the number of simultaneous channel recordings supported and the number of biquad filters and such. See the
TLV320ADCx140 Sampling Rates and Programmable Processing Blocks Supported application report for further
details.
8.3.6.1 Programmable Channel Gain and Digital Volume Control
The device has an independent programmable channel gain setting for each input channel that can be set to the
appropriate value based on the maximum input signal expected in the system and the ADC VREF setting used
(see the 节8.3.4 section), which determines the ADC full-scale signal level.
Configure the desired channel gain setting before powering up the ADC channel and do not change this setting
when the ADC is powered on. The programmable range supported for each channel gain is from 0 dB to 42 dB
in steps of 0.5 dB. To achieve low-noise performance, the device internal logic first maximizes the gain for the
front-end, low-noise analog PGA, which supports a dynamic range of 120 dB, and then applies any residual
programmed channel gain in the digital processing block.
表8-13 shows the programmable options available for the channel gain.
表8-13. Channel Gain Programmable Settings
P0_R61_D[7:1] : CH1_GAIN[6:0]
000 0000 = 0d (default)
000 0001 = 1d
CHANNEL GAIN SETTING FOR INPUT CHANNEL 1
Input channel 1 gain is set to 0 dB
Input channel 1 gain is set to 0.5 dB
Input channel 1 gain is set to 1 dB
000 0010 = 2d
…
…
101 0011 = 83d
Input channel 1 gain is set to 41.5 dB
Input channel 1 gain is set to 42 dB
Reserved (do not use these settings)
101 0100 = 84d
101 0101 to 111 1111 = 85d to 127d
Similarly, the channel gain setting for input channel 2 can be configured using the CH2_GAIN (P0_R66_D[7:1])
register bits. The channel gain feature is not available for the digital microphone record path.
The device also supports gain change when the ADC is enabled. The device supports multiple configurations to
limit the audible artifacts during dynamic gain change. This feature can be configured by using the
OTF_GAIN_CHANGE_CFG (P0_R113_D[7:6]) register bits.
The device also has a programmable digital volume control with a range from –100 dB to +27 dB in steps of
0.5 dB with the option to mute the channel recording. The digital volume control value can be changed
dynamically when the ADC channel is powered up and recording. During volume control changes, the soft ramp-
up or ramp-down volume feature is used internally to avoid any audible artifacts. Soft-stepping can be entirely
disabled using the DISABLE_SOFT_STEP (P0_R108_D4) register bit.
The digital volume control setting is independently available for each output channel, including the digital
microphone record channel. However, the device also supports an option to gang-up the volume control setting
for all channels together using the channel 1 digital volume control setting, regardless if channel 1 is powered up
or powered down. This gang-up can be enabled using the DVOL_GANG (P0_R108_D7) register bit.
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表8-14 shows the programmable options available for the digital volume control.
表8-14. Digital Volume Control (DVC) Programmable Settings
P0_R62_D[7:0] : CH1_DVOL[7:0]
DVC SETTING FOR OUTPUT CHANNEL 1
0000 0000 = 0d
Output channel 1 DVC is set to mute
0000 0001 = 1d
Output channel 1 DVC is set to –100 dB
Output channel 1 DVC is set to –99.5 dB
Output channel 1 DVC is set to –99 dB
…
0000 0010 = 2d
0000 0011 = 3d
…
1100 1000 = 200d
1100 1001 = 201d (default)
1100 1010 = 202d
Output channel 1 DVC is set to –0.5 dB
Output channel 1 DVC is set to 0 dB
Output channel 1 DVC is set to 0.5 dB
…
…
1111 1101 = 253d
1111 1110 = 254d
1111 1111 = 255d
Output channel 1 DVC is set to 26 dB
Output channel 1 DVC is set to 26.5 dB
Output channel 1 DVC is set to 27 dB
Similarly, the digital volume control setting for output channel 2 to channel 4 can be configured using the
CH2_DVOL (P0_R67) to CH4_DVOL (P0_R77) register bits, respectively.
The internal digital processing engine soft ramps up the volume from a muted level to the programmed volume
level when the channel is powered up, and the internal digital processing engine soft ramps down the volume
from a programmed volume to mute when the channel is powered down. This soft-stepping of volume is done to
prevent abruptly powering up and powering down the record channel. This feature can also be entirely disabled
using the DISABLE_SOFT_STEP (P0_R108_D4) register bit.
8.3.6.2 Programmable Channel Gain Calibration
Along with the programmable channel gain and digital volume, this device also provides programmable channel
gain calibration. The gain of each channel can be finely calibrated or adjusted in steps of 0.1 dB for a range of –
0.8-dB to 0.7-dB gain error. This adjustment is useful when trying to match the gain across channels resulting
from external components and microphone sensitivity. This feature, in combination with the regular digital
volume control, allows the gains across all channels to be matched for a wide gain error range with a resolution
of 0.1 dB. 表8-15 shows the programmable options available for the channel gain calibration.
表8-15. Channel Gain Calibration Programmable Settings
P0_R63_D[7:4] : CH1_GCAL[3:0]
CHANNEL GAIN CALIBRATION SETTING FOR INPUT CHANNEL 1
0000 = 0d
Input channel 1 gain calibration is set to –0.8 dB
0001 = 1d
Input channel 1 gain calibration is set to –0.7 dB
…
…
1000 = 8d (default)
Input channel 1 gain calibration is set to 0 dB
…
…
1110 = 14d
1111 = 15d
Input channel 1 gain calibration is set to 0.6 dB
Input channel 1 gain calibration is set to 0.7 dB
Similarly, the channel gain calibration setting for input channel 2 to channel 4 can be configured using the
CH2_GCAL (P0_R68) to CH4_GCAL (P0_R78) register bits, respectively.
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8.3.6.3 Programmable Channel Phase Calibration
In addition to the gain calibration, the phase delay in each channel can be finely calibrated or adjusted in steps
of one modulator clock cycle for a cycle range of 0 to 255 for the phase error of the analog microphone. The
modulator clock, which is the same clock used for ADC_MOD_CLK, is 6.144 MHz (the output data sample rate
is multiples or submultiples of 48 kHz) or 5.6448 MHz (the output data sample rate is multiples or submultiples of
44.1 kHz). For the digital microphone interface, the phase calibration clock is dependent on the PDM clock used.
For a PDM_CLK of 6.144 MHz (the output data sample rate is multiples or submultiples of 48 kHz) or 5.6448
MHz (the output data sample rate is multiples or submultiples of 44.1 kHz), the phase calibration clock is the
same as PDM_CLK. For a PDM_CLK equal to or lower than 3.072 MHz (the output data sample rate is multiples
or submultiples of 48 kHz), the phase calibration clock used is 3.072 MHz. Similarly, for a PDM_CLK of 2.8224
MHz, 1.4112 MHz, or 705.6 kHz (the output data sample rate is multiples or submultiples of 44.1 kHz), and the
phase calibration clock used is 2.8224 MHz. This feature is very useful for applications that must match the
phase with fine resolution between each channel, including any phase mismatch across channels resulting from
external components or microphones. 表 8-16 shows the available programmable options for channel phase
calibration for the analog or digital microphone with a PDM_CLK of 6.144 MHz or 5.6448 MHz.
表8-16. Channel Phase Calibration Programmable Settings
P0_R64_D[7:0] : CH1_PCAL[7:0]
0000 0000 = 0d (default)
0000 0001 = 1d
CHANNEL PHASE CALIBRATION SETTING FOR INPUT CHANNEL 1
Input channel 1 phase calibration with no delay
Input channel 1 phase calibration delay is set to one cycle of the modulator clock
Input channel 1 phase calibration delay is set to two cycles of the modulator clock
0000 0010 = 2d
…
…
1111 1110 = 254d
1111 1111 = 255d
Input channel 1 phase calibration delay is set to 254 cycles of the modulator clock
Input channel 1 phase calibration delay is set to 255 cycles of the modulator clock
For a digital microphone interface with a PDM_CLK frequency below 3.072 MHz, the phase calibration range is
from 0 to 127 of the phase calibration clock (3.072 MHz for the output data sample rate is multiples or
submultiples of 48 kHz and 2.8224 MHz for the output data sample rate is multiples or submultiples of 44.1 kHz).
This range can be configured using CH1_PCAL[7:1] for channel 1.
Similarly, the channel phase calibration setting for input channel 2 to channel 4 can be configured using the
CH2_PCAL (P0_R69) to CH4_PCAL (P0_R79) register bits, respectively.
The phase calibration feature must not be used when the analog input and PDM input are used together for
simultaneous conversion.
8.3.6.4 Programmable Digital High-Pass Filter
To remove the DC offset component and attenuate the undesired low-frequency noise content in the record data,
the device supports a programmable high-pass filter (HPF). The HPF is not a channel-independent filter setting
but is globally applicable for all ADC channels. This HPF is constructed using the first-order infinite impulse
response (IIR) filter, and is efficient enough to filter out possible DC components of the signal. 表8-17 shows the
predefined –3-dB cutoff frequencies available that can be set by using the HPF_SEL[1:0] register bits of
P0_R107. Additionally, to achieve a custom –3-dB cutoff frequency for a specific application, the device also
allows the first-order IIR filter coefficients to be programmed when the HPF_SEL[1:0] register bits are set to
2'b00. 图8-17 shows a frequency response plot for the HPF filter.
表8-17. HPF Programmable Settings
P0_R107_D[1:0] :
HPF_SEL[1:0]
-3-dB CUTOFF FREQUENCY
SETTING
-3-dB CUTOFF FREQUENCY AT
16-kHz SAMPLE RATE
-3-dB CUTOFF FREQUENCY AT
48-kHz SAMPLE RATE
00
01 (default)
10
Programmable 1st-order IIR filter
0.00025 × fS
Programmable 1st-order IIR filter
Programmable 1st-order IIR filter
4 Hz
32 Hz
128 Hz
12 Hz
96 Hz
0.002 × fS
11
0.008 × fS
384 Hz
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3
0
-3
-6
-9
-12
-15
-18
-21
-24
-27
-30
-33
-36
-39
-42
-45
HPF -3 dB Cutoff = 0.00025 ì fS
HPF -3 dB Cutoff = 0.002 ì fS
HPF -3 dB Cutoff = 0.008 ì fS
5E-50.0001
0.001 0.002 0.005 0.01 0.02
0.05
Normalized Frequency (1/fS)
HPF_
图8-17. HPF Filter Frequency Response Plot
方程式1 gives the transfer function for the first-order programmable IIR filter:
00 + 01VF1
231 F &1VF1
: ;
* V =
(1)
The frequency response for this first-order programmable IIR filter with default coefficients is flat at a gain of 0 dB
(all-pass filter). The host device can override the frequency response by programming the IIR coefficients in 表
8-18 to achieve the desired frequency response for high-pass filtering or any other desired filtering. If
HPF_SEL[1:0] are set to 2'b00, the host device must write these coefficients values for the desired frequency
response before powering-up any ADC channel for recording. 表 8-18 shows the filter coefficients for the first-
order IIR filter.
表8-18. 1st-Order IIR Filter Coefficients
FILTER
COEFFICIENT
COEFFICIENT REGISTER
MAPPING
FILTER
DEFAULT COEFFICIENT VALUE
0x7FFFFFFF
N0
N1
D1
P4_R72-R75
P4_R76-R79
P4_R80-R83
Programmable 1st-order IIR filter (can be
allocated to HPF or any other desired filter)
0x00000000
0x00000000
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8.3.6.5 Programmable Digital Biquad Filters
The device supports up to 12 programmable digital biquad filters. These highly efficient filters achieve the
desired frequency response. In digital signal processing, a digital biquad filter is a second-order, recursive linear
filter with two poles and two zeros. 方程式2 gives the transfer function of each biquad filter:
00 + 201VF1 + 02VF2
231 F 2&1VF1 F &2VF2
: ;
* V =
(2)
The frequency response for the biquad filter section with default coefficients is flat at a gain of 0 dB (all-pass
filter). The host device can override the frequency response by programming the biquad coefficients to achieve
the desired frequency response for a low-pass, high-pass, or any other desired frequency shaping. The
programmable coefficients for the mixer operation are located in 节 8.6.4.1 and 节 8.6.4.2 . If biquad filtering is
required, then the host device must write these coefficients values before powering up any ADC channels for
recording. As described in 表 8-19, these biquad filters can be allocated for each output channel based on the
BIQUAD_CFG[1:0] register setting of P0_R108. By setting BIQUAD_CFG[1:0] to 2'b00, the biquad filtering for all
record channels is disabled and the host device can choose this setting if no additional filtering is required for the
system application. See the TLV320ADCx140 Programmable Biquad Filter Configuration and Applications
application report for further details.
表8-19. Biquad Filter Allocation to the Record Output Channel
RECORD OUTPUT CHANNEL ALLOCATION USING P0_R108_D[6:5] REGISTER SETTING
PROGRAMMABLE
BIQUAD FILTER
BIQUAD_CFG[1:0] = 2'b01
(1 Biquad per Channel)
BIQUAD_CFG[1:0] = 2'b10 (Default)
(2 Biquads per Channel)
BIQUAD_CFG[1:0] = 2'b11
(3 Biquads per Channel)
Biquad filter 1
Biquad filter 2
Biquad filter 3
Biquad filter 4
Biquad filter 5
Biquad filter 6
Biquad filter 7
Biquad filter 8
Biquad filter 9
Biquad filter 10
Biquad filter 11
Biquad filter 12
Allocated to output channel 1
Allocated to output channel 2
Allocated to output channel 3
Allocated to output channel 4
Not used
Allocated to output channel 1
Allocated to output channel 2
Allocated to output channel 3
Allocated to output channel 4
Allocated to output channel 1
Allocated to output channel 2
Allocated to output channel 3
Allocated to output channel 4
Not used
Allocated to output channel 1
Allocated to output channel 2
Allocated to output channel 3
Allocated to output channel 4
Allocated to output channel 1
Allocated to output channel 2
Allocated to output channel 3
Allocated to output channel 4
Allocated to output channel 1
Allocated to output channel 2
Allocated to output channel 3
Allocated to output channel 4
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
表8-20 shows the biquad filter coefficients mapping to the register space.
表8-20. Biquad Filter Coefficients Register Mapping
PROGRAMMABLE BIQUAD BIQUAD FILTER COEFFICIENTS PROGRAMMABLE BIQUAD BIQUAD FILTER COEFFICIENTS
FILTER
REGISTER MAPPING
FILTER
REGISTER MAPPING
Biquad filter 1
Biquad filter 2
Biquad filter 3
Biquad filter 4
Biquad filter 5
Biquad filter 6
P2_R8-R27
Biquad filter 7
Biquad filter 8
Biquad filter 9
Biquad filter 10
Biquad filter 11
Biquad filter 12
P3_R8-R27
P2_R28-R47
P3_R28-R47
P2_R48-R67
P3_R48-R67
P2_R68-R87
P3_R68-R87
P2_R88-R107
P2_R108-R127
P3_R88-R107
P3_R108-R127
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8.3.6.6 Programmable Channel Summer and Digital Mixer
For applications that require an even higher SNR than that supported for each channel, the device digital
summing mode can be used. In this mode, the digital record data are summed up across the channel with an
equal weightage factor, which helps in reducing the effective record noise. 表8-21 lists the configuration settings
available for channel summing mode.
表8-21. Channel Summing Mode Programmable Settings
SNR AND DYNAMIC RANGE
P0_R107_D[3:2] : CH_SUM[1:0]
CHANNEL SUMMING MODE FOR INPUT CHANNELS
Channel summing mode is disabled
BOOST
00 (default)
Not applicable
Output channel 1 = (input channel 1 + input channel 2) / 2
Output channel 2 = (input channel 1 + input channel 2) / 2
Reserved (do not use this setting)
Around 3-dB boost in SNR and
dynamic range
01
10
11
Not applicable
Not applicable
Reserved (do not use this setting)
The device additionally supports a fully programmable mixer feature that can mix the various input channels with
their custom programmable scale factor to generate the final output channels. The programmable mixer feature
is available only if CH_SUM[1:0] is set to 2'b00. The mixer function is supported for all input channels. 图 8-18
shows a block diagram that describes the mixer 1 operation to generate output channel 1. The programmable
coefficients for the mixer operation are located in the 节8.6.4.3 section.
Attenuated by
Input Channel-1
MIX1_CH1
Processed Data
factor
Output Channel-1
Routed to Bi-Quad
Filter
+
Attenuated by
Input Channel-2
MIX1_CH2
Processed Data
factor
图8-18. Programmable Digital Mixer Block Diagram
A similar mixer operation is performed by mixer 2 to generate output channel 2.
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8.3.6.7 Configurable Digital Decimation Filters
The device record channel includes a high dynamic range, built-in digital decimation filter to process the
oversampled data from the multibit delta-sigma (ΔΣ) modulator to generate digital data at the same Nyquist
sampling rate as the FSYNC rate. As illustrated in 图 8-16, this decimation filter can also be used for processing
the oversampled PDM stream from the digital microphone. The decimation filter can be chosen from three
different types, depending on the required frequency response, group delay, and phase linearity requirements for
the target application. The selection of the decimation filter option can be done by configuring the DECI_FILT
(P0_R107_D[5:4]) register bits. 表 8-22 shows the configuration register setting for the decimation filter mode
selection for the record channel.
表8-22. Decimation Filter Mode Selection for the Record Channel
P0_R107_D[5:4] : DECI_FILT[1:0]
DECIMATION FILTER MODE SELECTION
00 (default)
Linear phase filters are used for the decimation
01
10
11
Low latency filters are used for the decimation
Ultra-low latency filters are used for the decimation
Reserved (do not use this setting)
8.3.6.7.1 Linear Phase Filters
The linear phase decimation filters are the default filters set by the device and can be used for all applications
that require a perfect linear phase with zero-phase deviation within the pass-band specification of the filter. The
filter performance specifications and various plots for all supported output sampling rates are listed in this
section.
8.3.6.7.1.1 Sampling Rate: 7.35 kHz to 8 kHz
图 8-19 and 图 8-20 respectively show the magnitude response and the pass-band ripple for a decimation filter
with a sampling rate of 7.35 kHz to 8 kHz. 表8-23 lists the specifications for a decimation filter with a 7.35-kHz to
8-kHz sampling rate.
10
0
0.5
0.4
0.3
0.2
0.1
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
D001
D001
图8-19. Linear Phase Decimation Filter Magnitude 图8-20. Linear Phase Decimation Filter Pass-Band
Response Ripple
表8-23. Linear Phase Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
MIN
–0.05
72.7
TYP
MAX
UNIT
Pass-band ripple
Frequency range is 0 to 0.454 × fS
Frequency range is 0.58 × fS to 4 × fS
Frequency range is 4 × fS onwards
Frequency range is 0 to 0.454 × fS
0.05
dB
Stop-band attenuation
Group delay or latency
dB
81.2
17.1
1/fS
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8.3.6.7.1.2 Sampling Rate: 14.7 kHz to 16 kHz
图 8-21 and 图 8-22 respectively show the magnitude response and the pass-band ripple for a decimation filter
with a sampling rate of 14.7 kHz to16 kHz. 表 8-24 lists the specifications for a decimation filter with a 14.7 kHz
to 16-kHz sampling rate.
10
0
0.5
0.4
0.3
0.2
0.1
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
D001
D001
图8-21. Linear Phase Decimation Filter Magnitude 图8-22. Linear Phase Decimation Filter Pass-Band
Response Ripple
表8-24. Linear Phase Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
MIN
–0.05
73.3
TYP
MAX
UNIT
Pass-band ripple
Frequency range is 0 to 0.454 × fS
Frequency range is 0.58 × fS to 4 × fS
Frequency range is 4 × fS onwards
Frequency range is 0 to 0.454 × fS
0.05
dB
Stop-band attenuation
Group delay or latency
dB
95.0
15.7
1/fS
8.3.6.7.1.3 Sampling Rate: 22.05 kHz to 24 kHz
图 8-23 and 图 8-24 respectively show the magnitude response and the pass-band ripple for a decimation filter
with a sampling rate of 22.05 kHz to 24 kHz. 表 8-25 lists the specifications for a decimation filter with a 22.05-
kHz to 24-kHz sampling rate.
10
0
0.5
0.4
0.3
0.2
0.1
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
D001
D001
图8-23. Linear Phase Decimation Filter Magnitude 图8-24. Linear Phase Decimation Filter Pass-Band
Response Ripple
表8-25. Linear Phase Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
MIN
–0.05
73.0
TYP
MAX
UNIT
Pass-band ripple
Frequency range is 0 to 0.454 × fS
Frequency range is 0.58 × fS to 4 × fS
Frequency range is 4 × fS onwards
0.05
dB
Stop-band attenuation
dB
96.4
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表8-25. Linear Phase Decimation Filter Specifications (continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Group delay or latency
Frequency range is 0 to 0.454 × fS
16.6
1/fS
8.3.6.7.1.4 Sampling Rate: 29.4 kHz to 32 kHz
图 8-25 and 图 8-26 respectively show the magnitude response and the pass-band ripple for a decimation filter
with a sampling rate of 29.4 kHz to 32 kHz. 表 8-26 lists the specifications for a decimation filter with a 29.4-kHz
to 32-kHz sampling rate.
10
0
0.5
0.4
0.3
0.2
0.1
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
D001
D001
图8-25. Linear Phase Decimation Filter Magnitude 图8-26. Linear Phase Decimation Filter Pass-Band
Response Ripple
表8-26. Linear Phase Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
MIN
–0.05
73.7
TYP
MAX
UNIT
Pass-band ripple
Frequency range is 0 to 0.454 × fS
Frequency range is 0.58 × fS to 4 × fS
Frequency range is 4 × fS onwards
Frequency range is 0 to 0.454 × fS
0.05
dB
Stop-band attenuation
Group delay or latency
dB
107.2
16.9
1/fS
8.3.6.7.1.5 Sampling Rate: 44.1 kHz to 48 kHz
图 8-27 and 图 8-28 respectively show the magnitude response and the pass-band ripple for a decimation filter
with a sampling rate of 44.1 kHz to 48 kHz. 表 8-27 lists the specifications for a decimation filter with a 44.1-kHz
to 48-kHz sampling rate.
10
0
0.5
0.4
0.3
0.2
0.1
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
D001
D001
图8-27. Linear Phase Decimation Filter Magnitude 图8-28. Linear Phase Decimation Filter Pass-Band
Response
Ripple
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表8-27. Linear Phase Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
MIN
–0.05
73.8
TYP
MAX
UNIT
Pass-band ripple
Frequency range is 0 to 0.454 × fS
Frequency range is 0.58 × fS to 4 × fS
Frequency range is 4 × fS onwards
Frequency range is 0 to 0.454 × fS
0.05
dB
Stop-band attenuation
Group delay or latency
dB
98.1
17.1
1/fS
8.3.6.7.1.6 Sampling Rate: 88.2 kHz to 96 kHz
图 8-29 and 图 8-30 respectively show the magnitude response and the pass-band ripple for a decimation filter
with a sampling rate of 88.2 kHz to 96 kHz. 表8-28 lists the specifications for a decimation filter with an 88.2-kHz
to 96-kHz sampling rate.
10
0
0.5
0.4
0.3
0.2
0.1
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
D001
D001
图8-29. Linear Phase Decimation Filter Magnitude 图8-30. Linear Phase Decimation Filter Pass-Band
Response Ripple
表8-28. Linear Phase Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
MIN
–0.05
73.6
TYP
MAX
UNIT
Pass-band ripple
Frequency range is 0 to 0.454 × fS
Frequency range is 0.58 × fS to 4 × fS
Frequency range is 4 × fS onwards
Frequency range is 0 to 0.454 × fS
0.05
dB
Stop-band attenuation
Group delay or latency
dB
97.9
17.1
1/fS
8.3.6.7.1.7 Sampling Rate: 176.4 kHz to 192 kHz
图 8-31 and 图 8-32 respectively show the magnitude response and the pass-band ripple for a decimation filter
with a sampling rate of 176.4 kHz to 192 kHz. 表 8-29 lists the specifications for a decimation filter with a 176.4-
kHz to 192-kHz sampling rate.
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10
0
0.5
0.4
0.3
0.2
0.1
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
0
0.05
0.1
0.15
0.2
0.25
Normalized Frequency (1/fS)
0.3
0.35
0.4
D001
D001
图8-31. Linear Phase Decimation Filter Magnitude
图8-32. Linear Phase Decimation Filter Pass-Band
Response
Ripple
表8-29. Linear Phase Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Pass-band ripple
Frequency range is 0 to 0.3 × fS
Frequency range is 0.473 × fS to 4 × fS
Frequency range is 4 × fS onwards
Frequency range is 0 to 0.3 × fS
0.05
dB
–0.05
70.0
Stop-band attenuation
Group delay or latency
dB
111.0
11.9
1/fS
8.3.6.7.1.8 Sampling Rate: 352.8 kHz to 384 kHz
图 8-33 and 图 8-34 respectively show the magnitude response and the pass-band ripple for a decimation filter
with a sampling rate of 352.8 kHz to 384 kHz. 表 8-30 lists the specifications for a decimation filter with a 352.8-
kHz to 384-kHz sampling rate.
10
0
0.5
0.4
0.3
0.2
0.1
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
0
0.05
0.1
0.15
Normalized Frequency (1/fS)
0.2
0.25
0.3
D001
D001
图8-33. Linear Phase Decimation Filter Magnitude 图8-34. Linear Phase Decimation Filter Pass-Band
Response Ripple
表8-30. Linear Phase Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
MIN
–0.05
70.0
TYP
MAX
UNIT
Pass-band ripple
Frequency range is 0 to 0.212 × fS
Frequency range is 0.58 × fS to 4 × fS
Frequency range is 4 × fS onwards
Frequency range is 0 to 0.212 × fS
0.05
dB
Stop-band attenuation
Group delay or latency
dB
108.8
7.2
1/fS
8.3.6.7.1.9 Sampling Rate: 705.6 kHz to 768 kHz
图 8-35 and 图 8-36 respectively show the magnitude response and the pass-band ripple for a decimation filter
with a sampling rate of 705.6 kHz to 768 kHz. 表 8-31 lists the specifications for a decimation filter with a 705.6-
kHz to 768-kHz sampling rate.
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10
0
0.5
0.4
0.3
0.2
0.1
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
0
0.05
0.1
Normalized Frequency (1/fS)
0.15
0.2
D001
D001
图8-35. Linear Phase Decimation Filter Magnitude 图8-36. Linear Phase Decimation Filter Pass-Band
Response Ripple
表8-31. Linear Phase Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
MIN
–0.05
75.0
TYP
MAX
UNIT
Pass-band ripple
Frequency range is 0 to 0.113 × fS
Frequency range is 0.58 × fS to 2 × fS
Frequency range is 2 × fS onwards
Frequency range is 0 to 0.113 × fS
0.05
dB
Stop-band attenuation
Group delay or latency
dB
88.0
5.9
1/fS
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8.3.6.7.2 Low-Latency Filters
For applications where low latency with minimal phase deviation (within the audio band) is critical, the low-
latency decimation filters on the PCM3120-Q1 can be used. The device supports these filters with a group delay
of approximately seven samples with an almost linear phase response within the 0.365 × fS frequency band.
This section provides the filter performance specifications and various plots for all supported output sampling
rates for the low-latency filters.
8.3.6.7.2.1 Sampling Rate: 14.7 kHz to 16 kHz
图 8-37 shows the magnitude response and 图 8-38 shows the pass-band ripple and phase deviation for a
decimation filter with a sampling rate of 14.7 kHz to 16 kHz. 表 8-32 lists the specifications for a decimation filter
with a 14.7-kHz to 16-kHz sampling rate.
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
0.3
0.2
0.1
0
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
Pass-Band Ripple
Phase Deviation
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
D002
D002
图8-38. Low-Latency Decimation Filter Pass-Band
图8-37. Low-Latency Decimation Filter Magnitude
Ripple and Phase Deviation
Response
表8-32. Low-Latency Decimation Filter Specifications
PARAMETER
Pass-band ripple
TEST CONDITIONS
MIN
TYP
MAX
UNIT
dB
Frequency range is 0 to 0.451 × fS
Frequency range is 0.61 × fS onwards
Frequency range is 0 to 0.363 × fS
Frequency range is 0 to 0.363 × fS
Frequency range is 0 to 0.363 × fS
0.05
–0.05
Stop-band attenuation
Group delay or latency
Group delay deviation
Phase deviation
87.3
dB
7.6
1/fS
0.022
0.25
1/fS
–0.022
–0.21
Degrees
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8.3.6.7.2.2 Sampling Rate: 22.05 kHz to 24 kHz
图 8-39 shows the magnitude response and 图 8-40 shows the pass-band ripple and phase deviation for a
decimation filter with a sampling rate of 22.05 kHz to 24 kHz. 表 8-33 lists the specifications for a decimation
filter with a 22.05-kHz to 24-kHz sampling rate.
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
0.3
0.2
0.1
0
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
Pass-Band Ripple
Phase Deviation
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
D002
D002
图8-40. Low-Latency Decimation Filter Pass-Band
图8-39. Low-Latency Decimation Filter Magnitude
Ripple and Phase Deviation
Response
表8-33. Low-Latency Decimation Filter Specifications
PARAMETER
Pass-band ripple
TEST CONDITIONS
MIN
TYP
MAX
UNIT
dB
Frequency range is 0 to 0.459 × fS
Frequency range is 0.6 × fS onwards
Frequency range is 0 to 0.365 × fS
Frequency range is 0 to 0.365 × fS
Frequency range is 0 to 0.365 × fS
0.01
–0.01
Stop-band attenuation
Group delay or latency
Group delay deviation
Phase deviation
87.2
dB
7.5
1/fS
0.026
0.30
1/fS
–0.026
–0.26
Degrees
8.3.6.7.2.3 Sampling Rate: 29.4 kHz to 32 kHz
图 8-41 shows the magnitude response and 图 8-42 shows the pass-band ripple and phase deviation for a
decimation filter with a sampling rate of 29.4 kHz to 32 kHz. 表 8-34 lists the specifications for a decimation filter
with a 29.4-kHz to 32-kHz sampling rate.
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
0.3
0.2
0.1
0
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
Pass-Band Ripple
Phase Deviation
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
D002
D002
图8-42. Low-Latency Decimation Filter Pass-Band
图8-41. Low-Latency Decimation Filter Magnitude
Ripple and Phase Deviation
Response
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表8-34. Low-Latency Decimation Filter Specifications
PARAMETER
Pass-band ripple
TEST CONDITIONS
MIN
–0.04
88.3
TYP
MAX
UNIT
dB
Frequency range is 0 to 0.457 × fS
Frequency range is 0.6 × fS onwards
Frequency range is 0 to 0.368 × fS
Frequency range is 0 to 0.368 × fS
Frequency range is 0 to 0.368 × fS
0.04
Stop-band attenuation
Group delay or latency
Group delay deviation
Phase deviation
dB
8.7
1/fS
0.026
0.31
1/fS
–0.026
–0.26
Degrees
8.3.6.7.2.4 Sampling Rate: 44.1 kHz to 48 kHz
图 8-43 shows the magnitude response and 图 8-44 shows the pass-band ripple and phase deviation for a
decimation filter with a sampling rate of 44.1 kHz to 48 kHz. 表 8-35 lists the specifications for a decimation filter
with a 44.1-kHz to 48-kHz sampling rate.
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
0.3
0.2
0.1
0
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
Pass-Band Ripple
Phase Deviation
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
D002
D002
图8-44. Low-Latency Decimation Filter Pass-Band
图8-43. Low-Latency Decimation Filter Magnitude
Ripple and Phase Deviation
Response
表8-35. Low-Latency Decimation Filter Specifications
PARAMETER
Pass-band ripple
TEST CONDITIONS
MIN
TYP
MAX
UNIT
dB
Frequency range is 0 to 0.452 × fS
Frequency range is 0.6 × fS onwards
Frequency range is 0 to 0.365 × fS
Frequency range is 0 to 0.365 × fS
Frequency range is 0 to 0.365 × fS
0.015
–0.015
Stop-band attenuation
Group delay or latency
Group delay deviation
Phase deviation
86.4
dB
7.7
1/fS
0.027
0.30
1/fS
–0.027
–0.25
Degrees
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8.3.6.7.2.5 Sampling Rate: 88.2 kHz to 96 kHz
图 8-45 shows the magnitude response and 图 8-46 shows the pass-band ripple and phase deviation for a
decimation filter with a sampling rate of 88.2 kHz to 96 kHz. 表 8-36 lists the specifications for a decimation filter
with an 88.2-kHz to 96-kHz sampling rate.
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
0.3
0.2
0.1
0
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
Pass-Band Ripple
Phase Deviation
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
D002
D002
图8-46. Low-Latency Decimation Filter Pass-Band
图8-45. Low-Latency Decimation Filter Magnitude
Ripple and Phase Deviation
Response
表8-36. Low-Latency Decimation Filter Specifications
PARAMETER
Pass-band ripple
TEST CONDITIONS
MIN
TYP
MAX
UNIT
dB
Frequency range is 0 to 0.466 × fS
Frequency range is 0.6 × fS onwards
Frequency range is 0 to 0.365 × fS
Frequency range is 0 to 0.365 × fS
Frequency range is 0 to 0.365 × fS
0.04
–0.04
Stop-band attenuation
Group delay or latency
Group delay deviation
Phase deviation
86.3
dB
7.7
1/fS
0.027
0.30
1/fS
–0.027
–0.26
Degrees
8.3.6.7.2.6 Sampling Rate: 176.4 kHz to 192 kHz
图 8-47 shows the magnitude response and 图 8-48 shows the pass-band ripple and phase deviation for a
decimation filter with a sampling rate of 176.4 kHz to 192 kHz. 表 8-37 lists the specifications for a decimation
filter with a 176.4-kHz to 192-kHz sampling rate.
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
0.3
0.2
0.1
0
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
Pass-Band Ripple
Phase Deviation
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
D002
D002
图8-48. Low-Latency Decimation Filter Pass-Band
图8-47. Low-Latency Decimation Filter Magnitude
Ripple and Phase Deviation
Response
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表8-37. Low-Latency Decimation Filter Specifications
PARAMETER
Pass-band ripple
TEST CONDITIONS
Frequency range is 0 to 463 × fS
Frequency range is 0.6 × fS onwards
Frequency range is 0 to 0.365 × fS
Frequency range is 0 to 0.365 × fS
Frequency range is 0 to 0.365 × fS
MIN
–0.03
85.6
TYP
MAX
UNIT
dB
0.03
Stop-band attenuation
Group delay or latency
Group delay deviation
Phase deviation
dB
7.7
1/fS
0.027
0.30
1/fS
–0.027
–0.26
Degrees
8.3.6.7.3 Ultra-Low Latency Filters
For applications where ultra-low latency (within the audio band) is critical, the ultra-low latency decimation filters
on the PCM3120-Q1 can be used. The device supports these filters with a group delay of approximately four
samples with an almost linear phase response within the 0.325 × fS frequency band. This section provides the
filter performance specifications and various plots for all supported output sampling rates for the ultra-low latency
filters.
8.3.6.7.3.1 Sampling Rate: 14.7 kHz to 16 kHz
图 8-49 shows the magnitude response and 图 8-50 shows the pass-band ripple and phase deviation for a
decimation filter with a sampling rate of 14.7 kHz to 16 kHz. 表 8-38 lists the specifications for a decimation filter
with a 14.7-kHz to 16-kHz sampling rate.
0.5
0.4
0.3
0.2
0.1
0
25
20
15
10
5
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
0
-0.1
-0.2
-0.3
-0.4
-0.5
-5
-10
-15
-20
-25
Pass-Band Ripple
Phase Deviation
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
D003
D003
图8-50. Ultra-Low-Latency Decimation Filter Pass-
图8-49. Ultra-Low-Latency Decimation Filter
Band Ripple and Phase Deviation
Magnitude Response
表8-38. Ultra-Low-Latency Decimation Filter Specifications
PARAMETER
Pass-band ripple
TEST CONDITIONS
MIN
TYP
MAX
UNIT
dB
Frequency range is 0 to 0.45 × fS
Frequency range is 0.6 × fS onwards
Frequency range is 0 to 0.325 × fS
Frequency range is 0 to 0.325 × fS
Frequency range is 0 to 0.325 × fS
0.05
–0.05
Stop-band attenuation
Group delay or latency
Group delay deviation
Phase deviation
87.2
dB
4.3
1/fS
0.512
14.2
1/fS
–0.512
–10.0
Degrees
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8.3.6.7.3.2 Sampling Rate: 22.05 kHz to 24 kHz
图 8-51 shows the magnitude response and 图 8-52 shows the pass-band ripple and phase deviation for a
decimation filter with a sampling rate of 22.05 kHz to 24 kHz. 表 8-39 lists the specifications for a decimation
filter with a 22.05-kHz to 24-kHz sampling rate.
0.5
0.4
0.3
0.2
0.1
0
25
20
15
10
5
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
0
-0.1
-0.2
-0.3
-0.4
-0.5
-5
-10
-15
-20
-25
Pass-Band Ripple
Phase Deviation
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
D003
D003
图8-52. Ultra-Low-Latency Decimation Filter Pass-
图8-51. Ultra-Low-Latency Decimation Filter
Band Ripple and Phase Deviation
Magnitude Response
表8-39. Ultra-Low-Latency Decimation Filter Specifications
PARAMETER
Pass-band ripple
TEST CONDITIONS
MIN
TYP
MAX
UNIT
dB
Frequency range is 0 to 0.46 × fS
Frequency range is 0.6 × fS onwards
Frequency range is 0 to 0.325 × fS
Frequency range is 0 to 0.325 × fS
Frequency range is 0 to 0.325 × fS
0.01
–0.01
Stop-band attenuation
Group delay or latency
Group delay deviation
Phase deviation
87.1
dB
4.1
1/fS
0.514
14.3
1/fS
–0.514
–10.0
Degrees
8.3.6.7.3.3 Sampling Rate: 29.4 kHz to 32 kHz
图 8-53 shows the magnitude response and 图 8-54 shows the pass-band ripple and phase deviation for a
decimation filter with a sampling rate of 29.4 kHz to 32 kHz. 表 8-40 lists the specifications for a decimation filter
with a 29.4-kHz to 32-kHz sampling rate.
0.5
0.4
0.3
0.2
0.1
0
25
20
15
10
5
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
0
-0.1
-0.2
-0.3
-0.4
-0.5
-5
-10
-15
-20
-25
Pass-Band Ripple
Phase Deviation
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
D003
D003
图8-54. Ultra-Low-Latency Decimation Filter Pass-
图8-53. Ultra-Low-Latency Decimation Filter
Band Ripple and Phase Deviation
Magnitude Response
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表8-40. Ultra-Low-Latency Decimation Filter Specifications
PARAMETER
Pass-band ripple
TEST CONDITIONS
MIN
–0.04
88.3
TYP
MAX
UNIT
dB
Frequency range is 0 to 0.457 × fS
Frequency range is 0.6 × fS onwards
Frequency range is 0 to 0.325 × fS
Frequency range is 0 to 0.325 × fS
Frequency range is 0 to 0.325 × fS
0.04
Stop-band attenuation
Group delay or latency
Group delay deviation
Phase deviation
dB
5.2
1/fS
0.492
13.5
1/fS
–0.492
–9.5
Degrees
8.3.6.7.3.4 Sampling Rate: 44.1 kHz to 48 kHz
图 8-55 shows the magnitude response and 图 8-56 shows the pass-band ripple and phase deviation for a
decimation filter with a sampling rate of 44.1 kHz to 48 kHz. 表 8-41 lists the specifications for a decimation filter
with a 44.1-kHz to 48-kHz sampling rate.
0.5
0.4
0.3
0.2
0.1
0
25
20
15
10
5
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
0
-0.1
-0.2
-0.3
-0.4
-0.5
-5
-10
-15
-20
-25
Pass-Band Ripple
Phase Deviation
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
D003
D003
图8-56. Ultra-Low-Latency Decimation Filter Pass-
图8-55. Ultra-Low-Latency Decimation Filter
Band Ripple and Phase Deviation
Magnitude Response
表8-41. Ultra-Low-Latency Decimation Filter Specifications
PARAMETER
Pass-band ripple
TEST CONDITIONS
MIN
TYP
MAX
UNIT
dB
Frequency range is 0 to 0.452 × fS
Frequency range is 0.6 × fS onwards
Frequency range is 0 to 0.325 × fS
Frequency range is 0 to 0.325 × fS
Frequency range is 0 to 0.325 × fS
0.015
–0.015
Stop-band attenuation
Group delay or latency
Group delay deviation
Phase deviation
86.4
dB
4.1
1/fS
0.525
14.5
1/fS
–0.525
–10.3
Degrees
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8.3.6.7.3.5 Sampling Rate: 88.2 kHz to 96 kHz
图 8-57 shows the magnitude response and 图 8-58 shows the pass-band ripple and phase deviation for a
decimation filter with a sampling rate of 88.2 kHz to 96 kHz. 表 8-42 lists the specifications for a decimation filter
with an 88.2-kHz to 96-kHz sampling rate.
0.5
0.4
0.3
0.2
0.1
0
5
10
0
4
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
3
2
1
0
-0.1
-0.2
-0.3
-0.4
-0.5
-1
-2
-3
-4
-5
Pass-Band Ripple
Phase Deviation
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
D003
D003
图8-58. Ultra-Low-Latency Decimation Filter Pass-
图8-57. Ultra-Low-Latency Decimation Filter
Band Ripple and Phase Deviation
Magnitude Response
表8-42. Ultra-Low-Latency Decimation Filter Specifications
PARAMETER
Pass-band ripple
TEST CONDITIONS
MIN
TYP
MAX
UNIT
dB
Frequency range is 0 to 0.466 × fS
Frequency range is 0.6 × fS onwards
Frequency range is 0 to 0.1625 × fS
Frequency range is 0 to 0.1625 × fS
Frequency range is 0 to 0.1625 × fS
0.04
–0.04
Stop-band attenuation
Group delay or latency
Group delay deviation
Phase deviation
86.3
dB
3.7
1/fS
0.091
1.30
1/fS
–0.091
–0.86
Degrees
8.3.6.7.3.6 Sampling Rate: 176.4 kHz to 192 kHz
图 8-59 shows the magnitude response and 图 8-60 shows the pass-band ripple and phase deviation for a
decimation filter with a sampling rate of 176.4 kHz to 192 kHz. 表 8-43 lists the specifications for a decimation
filter with a 176.4-kHz to 192-kHz sampling rate.
0.5
0.4
0.3
0.2
0.1
0
5
10
0
4
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
3
2
1
0
-0.1
-0.2
-0.3
-0.4
-0.5
-1
-2
-3
-4
-5
Pass-Band Ripple
Phase Deviation
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Frequency (1/fS)
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
D003
D003
图8-60. Ultra-Low-Latency Decimation Filter Pass-
图8-59. Ultra-Low-Latency Decimation Filter
Band Ripple and Phase Deviation
Magnitude Response
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表8-43. Ultra-Low-Latency Decimation Filter Specifications
PARAMETER
Pass-band ripple
TEST CONDITIONS
Frequency range is 0 to 0.463 × fS
Frequency range is 0.6 × fS onwards
Frequency range is 0 to 0.085 × fS
Frequency range is 0 to 0.085 × fS
Frequency range is 0 to 0.085 × fS
MIN
–0.03
85.6
TYP
MAX
UNIT
dB
0.03
Stop-band attenuation
Group delay or latency
Group delay deviation
Phase deviation
dB
3.7
1/fS
0.024
0.18
1/fS
–0.024
–0.12
Degrees
8.3.6.7.3.7 Sampling Rate: 352.8 kHz to 384 kHz
图 8-61 shows the magnitude response and 图 8-62 shows the pass-band ripple and phase deviation for a
decimation filter with a sampling rate of 352.8 kHz to 384 kHz. 表 8-44 lists the specifications for a decimation
filter with a 352.8-kHz to 384-kHz sampling rate.
0.5
0.4
0.3
0.2
0.1
0
2
10
0
1.6
1.2
0.8
0.4
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-0.1
-0.2
-0.3
-0.4
-0.5
-0.4
-0.8
-1.2
-1.6
-2
Pass-Band Ripple
Phase Deviation
0
0.05
0.1 0.15
Normalized Frequency (1/fS)
0.2
0.25
0
0.4 0.8 1.2 1.6
2
Normalized Frequency (1/fS)
2.4 2.8 3.2 3.6
4
D002
D002
图8-62. Ultra-Low-Latency Decimation Filter Pass-
图8-61. Ultra-Low-Latency Decimation Filter
Band Ripple and Phase Deviation
Magnitude Response
表8-44. Ultra-Low-Latency Decimation Filter Specifications
PARAMETER
Pass-band ripple
TEST CONDITIONS
MIN
TYP
MAX
UNIT
dB
Frequency range is 0 to 0.1 × fS
Frequency range is 0.56 × fS onwards
Frequency range is 0 to 0.157 × fS
Frequency range is 0 to 0.157 × fS
Frequency range is 0 to 0.157 × fS
0.01
–0.04
Stop-band attenuation
Group delay or latency
Group delay deviation
Phase deviation
70.1
dB
4.1
1/fS
0.18
2.07
1/fS
–0.18
–0.85
Degrees
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8.3.7 Automatic Gain Controller (AGC)
The device includes an automatic gain controller (AGC) for ADC recording. As shown in 图 8-63, the AGC can
be used to maintain a nominally constant output level when recording speech. Instead of manually setting the
channel gain in AGC mode, the circuitry automatically adjusts the channel gain when the input signal becomes
overly loud or very weak, such as when a person speaking into a microphone moves closer to or farther from the
microphone. The AGC algorithm has several programmable parameters, including target level, maximum gain
allowed, attack and release (or decay) time constants, and noise thresholds that allow the algorithm to be fine-
tuned for any particular application.
Input
Signal
Output
Signal
Target
Level
AGC
Gain
Decay Time
Attack
Time
图8-63. AGC Characteristics
The target level (AGC_LVL) represents the nominal approximate output level at which the AGC attempts to hold
the ADC output signal level. The PCM3120-Q1 allows programming of different target levels, which can be
programmed from –6 dB to –36 dB relative to a full-scale signal, and the AGC_LVL default value is set to –
34 dB. The target level is recommended to be set with enough margin to prevent clipping when loud sounds
occur. 表8-45 lists the AGC target level configuration settings.
表8-45. AGC Target Level Programmable Settings
P0_R112_D[7:4] : AGC_LVL[3:0]
AGC TARGET LEVEL FOR OUTPUT
0000
0001
0010
The AGC target level is the –6-dB output signal level
The AGC target level is the –8-dB output signal level
The AGC target level is the –10-dB output signal level
…
…
1110 (default)
The AGC target level is the –34-dB output signal level
The AGC target level is the –36-dB output signal level
1111
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The maximum gain allowed (AGC_MAXGAIN) gives flexibility to the designer to restrict the maximum gain
applied by the AGC. This feature limits the channel gain in situations where environmental noise is greater than
the programmed noise threshold. The AGC_MAXGAIN can be programmed from 3 dB to 42 dB with steps of
3 dB and the default value is set to 24 dB. 表8-46 lists the AGC_MAXGAIN configuration settings.
表8-46. AGC Maximum Gain Programmable Settings
P0_R112_D[3:0] :
AGC MAXIMUM GAIN ALLOWED
AGC_MAXGAIN[3:0]
0000
0001
0010
The AGC maximum gain allowed is 3 dB
The AGC maximum gain allowed is 6 dB
The AGC maximum gain allowed is 9 dB
…
…
0111 (default)
The AGC maximum gain allowed is 24 dB
…
…
1110
1111
The AGC maximum gain allowed is 39 dB
The AGC maximum gain allowed is 42 dB
For further details on the AGC various configurable parameter and application use, see the Using the Automatic
Gain Controller (AGC) in TLV320ADCx120 Family application report.
8.3.8 Voice Activity Detection (VAD)
The PCM3120-Q1 supports voice activity detection (VAD) mode. In this mode, the PCM3120-Q1 continuously
monitors one of the input channels for voice detection. The device consumes low quiescent current from the
AVDD supply in this mode. This feature can be enabled by setting VAD_EN (P0_R117_D0) to 1'b1. On detecting
voice activity, the PCM3120-Q1 can alert the host through an interrupt or auto wake up and start recording
based on the I2C programmed configuration. This alert can be configured through the VAD_MODE
(P1_R30_D[7:6]) register bits.
This feature is supported on both the analog and digital microphone interfaces. For lowest power VAD, the digital
microphone interface is recommended. The input channel for the VAD can be selected by setting the
VAD_CH_SEL (P1_R30_D[5:4]) register bits to an appropriate value. See the Using the Voice Activity Detector
(VAD) in the TLV320ADC5120 and TLV320ADC6120 application report for further details.
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8.3.9 Digital PDM Microphone Record Channel
In addition to supporting analog microphones, the device also interfaces to digital pulse-density-modulation
(PDM) microphones and uses high-order and high-performance decimation filters to generate pulse code
modulation (PCM) output data that can be transmitted on the audio serial interface to the host. The device
supports up to four digital microphone recording channels. If the second channel analog microphone is not used
in the system, then the analog input pins (IN2P and IN2M) can be repurposed as the GPI1 and GPO1 pins,
respectively, and can be configured for the PDMDIN1 and PDMCLK clocks for digital PDM microphone
recording. GPIO1 or GPI2 (multiplexed with MICBIAS) can be used as PDMDIN2 to enable four-channel PDM
microphone recording. If two-channel analog input recording is needed, MICBIAS (configured as GPI2) and
GPIO1 can be used as PDMDIN and PDMCLK, respectively, to enable two-channel DMIC recording along with
two-channel AIN recording. The device can support a total of four channels at the input (analog and digital).
The device internally generates PDMCLK with a programmable frequency of either 6.144 MHz, 3.072 MHz,
1.536 MHz, or 768 kHz (for output data sample rates in multiples or submultiples of 48 kHz) or 5.6448 MHz,
2.8224 MHz, 1.4112 MHz, or 705.6 kHz (for output data sample rates in multiples or submultiples of 44.1 kHz)
using the PDMCLK_DIV[1:0] (P0_R31_D[1:0]) register bits. PDMCLK can be routed on the GPO1 and GPIO1
pins. This clock can be connected to the external digital microphone device. 图 8-64 shows a connection
diagram of the digital PDM microphones.
VDD
VDD
VDD
IOVDD
DATA
Digital
PDM
SEL
Microphone
U1
CLK
GND
GND
PCMx120-Q1
VDD
VDD
SEL
GPIx (PDMDINx)
GPOx (PDMCLK)
DATA
CLK
Digital
PDM
Microphone
U2
GND
GND
图8-64. Digital PDM Microphones Connection Diagram for the PCM3120-Q1
The single-bit output of the external digital microphone device can be connected to the GPIx pin. This single
data line can be shared by two digital microphones to place their data on the opposite edge of PDMCLK.
Internally, the device latches the steady value of the data on either the rising or falling edge of PDMCLK based
on the configuration register bits set in P0_R32_D[7:4]. 图 8-65 shows the digital PDM microphone interface
timing diagram.
PDMCLK
PDMDINx
D1[n]
D2[n]
D1[n+1]
D2[n+1]
D1[n+2]
Mic-1
Data
Mic-2
Data
Mic-1
Data
Mic-2
Data
Mic-1
Data
(n+1)th Sample
(n+2)th Sample
nth Sample
图8-65. Digital PDM Microphone Protocol Timing Diagram
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When the digital microphone is used for recording, the analog blocks of the respective ADC channel are
powered down and bypassed for power efficiency. Use the CH1_INSRC[1:0] (P0_R60_D[6:5]) and
CH2_INSRC[1:0] (P0_R65_D[6:5]) register bits to select the analog microphone or digital microphone for
channel 1 to channel 2. Channel 3 and channel 4 support only the digital microphone interface.
8.3.10 Interrupts, Status, and Digital I/O Pin Multiplexing
Certain events in the device may require host processor intervention and can be used to trigger interrupts to the
host processor. One such event is an audio serial interface (ASI) bus error. The device powers down the record
channels if any faults are detected with the ASI bus error clocks, such as:
• Invalid FSYNC frequency
• Invalid SBCLK to FSYNC ratio
• Long pauses of the SBCLK or FSYNC clocks
When an ASI bus clock error is detected, the device shuts down the record channel as quickly as possible. After
all ASI bus clock errors are resolved, the device volume ramps back to its previous state to recover the record
channel. During an ASI bus clock error, the internal interrupt request (IRQ) interrupt signal asserts low if the
clock error interrupt mask register bit INT_MASK0[7] (P0_R51_D7) is set low. The clock fault is also available for
readback in the latched fault status register bit INT_LTCH0 (P0_R54), which is a read-only register. Reading the
latched fault status register, INT_LTCH0, clears all latched fault status. The device can be additionally configured
to route the internal IRQ interrupt signal on the GPIO1 or GPOx pins and also can be configured as open-drain
outputs so that these pins can be wire-ANDed to the open-drain interrupt outputs of other devices.
The IRQ interrupt signal can either be configured as active low or active high polarity by setting the INT_POL
(P0_R50_D7) register bit. This signal can also be configured as a single pulse or a series of pulses by
programming the INT_EVENT[1:0] (P0_R50_D[6:5]) register bits. If the interrupts are configured as a series of
pulses, the events trigger the start of pulses that stop when the latched fault status register is read to determine
the cause of the interrupt.
The device also supports read-only live-status registers to determine if the channels are powered up or down
and if the device is in sleep mode or not. These status registers are located in the DEV_STS0 (P0_R118) and
DEV_STS1 (P0_R119) register bits.
The device has a multifunctional GPIO1 pin that can be configured for a desired specific function. Additionally, if
the channel is not used for analog input recording, then the analog input pins for that channel (INxP and INxM)
can be repurposed as multifunction pins (GPIx and GPOx) by configuring the CHx_INSRC[1:0] register bits
located in the CHx_CFG0 register. The maximum number of GPO pins supported by the device is four and the
maximum number of GPI pins are four. 表 8-47 lists all possible allocations of these multifunctional pins for the
various features.
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表8-47. Multifunction Pin Assignments
ROW
PIN FUNCTION(3)
GPIO1
GPO1
GPI1
GPI2
GPIO1_CFG
GPO1_CFG
GPI1_CFG
GPI2_CFG
—
—
A
B
C
D
E
F
—
P0_R33[7:4]
P0_R34[7:4]
P0_R43[6:4]
P0_R43[2:0]
—
Pin disabled
S(1)
S (default)
S (default)
S (default)
General-purpose output (GPO)
Interrupt output (IRQ)
S
S
NS(2)
NS
S
NS
NS
S
S (default)
S
Power down for all ADC channels
PDM clock output (PDMCLK)
MiCBIAS on/off input (BIASEN)
General-purpose input (GPI)
Master clock input (MCLK)
ASI daisy-chain input (SDIN)
PDM data input 1 (PDMDIN1)
PDM data input 2 (PDMDIN2)
S
S
S
S
S
S
S
S
NS
S
NS
NS
S
NS
NS
S
NS
NS
NS
NS
NS
NS
G
H
I
S
S
S
S
J
S
S
K
S
S
(1) S means the feature mentioned in this row is supported for the respective GPIO1, GPOx, or GPIx pin mentioned in this column.
(2) NS means the feature mentioned in this row is not supported for the respective GPIO1, GPOx, or GPIx pin mentioned in this column.
(3) Only the GPIO1 pin is with reference to the IOVDD supply, the other GPOx and GPIx pins are with reference to the AVDD supply and
their primary pin functions are for the PDMCLK or PDMDIN function.
Each GPOx or GPIOx pin can be independently set for the desired drive configurations setting using the
GPOx_DRV[3:0] or GPIO1_DRV[3:0] register bits. 表8-48 lists the drive configuration settings.
表8-48. GPIO or GPOx Pins Drive Configuration Settings
P0_R33_D[3:0] : GPIO1_DRV[3:0]
GPIO OUTPUT DRIVE CONFIGURATION SETTINGS FOR GPIO1
000
001
The GPIO1 pin is set to high impedance (floated)
The GPIO1 pin is set to be driven active low or active high
The GPIO1 pin is set to be driven active low or weak high (on-chip pullup)
The GPIO1 pin is set to be driven active low or Hi-Z (floated)
The GPIO1 pin is set to be driven weak low (on-chip pulldown) or active high
The GPIO1 pin is set to be driven Hi-Z (floated) or active high
Reserved (do not use these settings)
010 (default)
011
100
101
110 and 111
Similarly, the GPO1 pin can be configured using the GPO1_DRV(P0_R34) register bits.
When configured as a general-purpose output (GPO), the GPIO1 or GPOx pin values can be driven by writing
the GPIO_VAL or GPOx_VAL (P0_R41) registers. The GPIO_MON (P0_R42) register can be used to readback
the status of the GPIO1 pin when configured as a general-purpose input (GPI). Similarly, the GPI_MON
(P0_R47) register can be used to readback the status of the GPIx pins when configured as a general-purpose
input (GPI).
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8.4 Device Functional Modes
8.4.1 Sleep Mode or Software Shutdown
In sleep mode or software shutdown mode, the device consumes very low quiescent current from the AVDD
supply and, at the same time, allows the I2C communication to wake the device for active operation.
The device enters sleep mode when the host device sets the SLEEP_ENZ (P0_R2_D0) bit to 1'b0. If the
SLEEP_ENZ bit is asserted low when the device is in active mode, the device ramps down the volume on the
record data, powers down the analog and digital blocks, and enters sleep mode. However, the device still
continues to retain the last programmed value of the device configuration registers and programmable
coefficients.
In sleep mode, do not perform any I2C transactions, except for exiting sleep mode in order to enter active mode.
After entering sleep mode, wait at least 10 ms before starting I2C transactions to exit sleep mode.
When exiting sleep mode, the host device must configure the PCM3120-Q1 to use either an external 1.8-V
AREG supply (default setting) or an on-chip-regulator-generated AREG supply. To configure the AREG supply,
write to AREG_SELECT, bit D7 in the same P0_R2 register.
8.4.2 Active Mode
If the host device exits sleep mode by setting the SLEEP_ENZ bit to 1'b1, the device enters active mode. In
active mode, I2C transactions can be done to configure and power-up the device for active operation. After
entering active mode, wait at least 1 ms before starting any I2C transactions in order to allow the device to
complete the internal wake-up sequence.
Read and write operations to the programmable coefficient registers in page 2, page 3, and page 4, and to the
channel configuration registers (CHx_CFG[1:4]), and AGC_CFG0 in page 0 must be done 10 ms after exiting
sleep mode.
After configuring all other registers for the target application and system settings, configure the input and output
channel enable registers, IN_CH_EN (P0_R115) and ASI_OUT_CH_EN (P0_R116), respectively. Lastly,
configure the device power-up register, PWR_CFG (P0_R117). All programmable coefficient values must be
written before powering up the respective channel.
In active mode, the power-up and power-down status of various blocks is monitored by reading the read-only
device status bits located in the DEV_STS0 (P0_R117) and DEV_STS1 (P0_R118) registers.
8.4.3 Software Reset
A software reset can be done any time by asserting the SW_RESET (P0_R1_D0) register bit, which is a self-
clearing bit. This software reset immediately shuts down the device, and restores all device configuration
registers and programmable coefficients to their default values.
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8.5 Programming
The device contains configuration registers and programmable coefficients that can be set to the desired values
for a specific system and application use. These registers are called device control registers and are each eight
bits in width, mapped using a page scheme.
Each page contains 128 configuration registers. All device configuration registers are stored in page 0, which is
the default page setting at power up and after a software reset. All programmable coefficient registers are
located in page 2, page 3, and page 4. The current page of the device can be switched to a new desired page by
using the PAGE[7:0] bits located in register 0 of every page.
8.5.1 Control Serial Interfaces
The device control registers can be accessed using I2C communication to the device. The device operates with
a fixed I2C address and can be configured using this address.
8.5.1.1 I2C Control Interface
The device supports the I2C control protocol as a target device, and is capable of operating in standard mode,
fast mode, and fast mode plus. The I2C control protocol requires a 7-bit target address. The 7-bit target address
is fixed at 1001110 and cannot be changed. If the I2C_BRDCAST_EN (P0_R2_D2) bit is set to 1'b1, then the I2C
target address is fixed to 1001100 in order to allow simultaneous I2C broadcast communication to multiple
devices in the system, including the PCMx140-Q1, PCMD3140-Q1, and PCMD3180-Q1 devices. 表 8-49 lists
the possible device addresses resulting from this configuration.
表8-49. I2C Target Address Settings
I2C_BRDCAST_EN (P0_R2_D2)
I2C TARGET ADDRESS
0 (default)
1
1001 110
1001 100
8.5.1.1.1 General I2C Operation
The I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a
system using serial data transmission. The address and data 8-bit bytes are transferred MSB first. In addition,
each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each
transfer operation begins with the controller device driving a start condition on the bus and ends with the
controller device driving a stop condition on the bus. The bus uses transitions on the data pin (SDA) while the
clock is at logic high to indicate start and stop conditions. A high-to-low transition on SDA indicates a start, and a
low-to-high transition indicates a stop. Normal data-bit transitions must occur within the low time of the clock
period.
The controller device drives a start condition followed by the 7-bit target address and the read/write (R/W) bit to
open communication with another device and then waits for an acknowledgment condition. The target device
holds SDA low during the acknowledge clock period to indicate acknowledgment. When this occurs, the
controller device transmits the next byte of the sequence. Each target device is addressed by a unique 7-bit
target address plus the R/W bit (1 byte). All compatible devices share the same signals via a bidirectional bus
using a wired-AND connection.
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There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last
word transfers, the controller device generates a stop condition to release the bus. 图8-66 shows a generic data
transfer sequence.
8- Bit Data for
Register (N)
8- Bit Data for
Register (N+1)
图8-66. Typical I2C Sequence
In the system, use external pullup resistors for the SDA and SCL signals to set the logic high level for the bus.
The SDA and SCL voltages must not exceed the device supply voltage, IOVDD.
8.5.1.1.1.1 I2C Single-Byte and Multiple-Byte Transfers
The device I2C interface supports both single-byte and multiple-byte read/write operations for all registers.
During multiple-byte read operations, the device responds with data, a byte at a time, starting at the register
assigned, as long as the controller device continues to respond with acknowledges.
The device supports sequential I2C addressing. For write transactions, if a register is issued followed by data for
that register and all the remaining registers that follow, a sequential I2C write transaction takes place. For I2C
sequential write transactions, the register issued then serves as the starting point, and the amount of data
subsequently transmitted, before a stop or start is transmitted, determines how many registers are written.
8.5.1.1.1.1.1 I2C Single-Byte Write
As shown in 图 8-67, a single-byte data write transfer begins with the controller device transmitting a start
condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of
the data transfer. For a write-data transfer, the read/write bit must be set to 0. After receiving the correct I2C
target address and the read/write bit, the device responds with an acknowledge bit (ACK). Next, the controller
device transmits the register byte corresponding to the device internal register address being accessed. After
receiving the register byte, the device again responds with an acknowledge bit (ACK). Then, the controller
transmits the byte of data to be written to the specified register. When finished, the target device responds with
an acknowledge bit (ACK). Finally, the controller device transmits a stop condition to complete the single-byte
data write transfer.
Start
Condition
Acknowledge
Acknowledge
Acknowledge
R/W
ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
A6 A5 A4
A3 A2 A1 A0
Stop
2
I C Device Address and
Read/Write Bit
Register
Data Byte
Condition
图8-67. I2C Single-Byte Write Transfer
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8.5.1.1.1.1.2 I2C Multiple-Byte Write
As shown in 图8-68, a multiple-byte data write transfer is identical to a single-byte data write transfer except that
multiple data bytes are transmitted by the controller device to the target device. After receiving each data byte,
the device responds with an acknowledge bit (ACK). Finally, the controller device transmits a stop condition after
the last data-byte write transfer.
Register
图8-68. I2C Multiple-Byte Write Transfer
8.5.1.1.1.1.3 I2C Single-Byte Read
As shown in 图 8-69, a single-byte data read transfer begins with the controller device transmitting a start
condition followed by the I2C target address and the read/write bit. For the data read transfer, both a write
followed by a read are done. Initially, a write is done to transfer the address byte of the internal register address
to be read. As a result, the read/write bit is set to 0.
After receiving the target address and the read/write bit, the device responds with an acknowledge bit (ACK).
The controller device then sends the internal register address byte, after which the device issues an
acknowledge bit (ACK). The controller device transmits another start condition followed by the target address
and the read/write bit again. This time, the read/write bit is set to 1, indicating a read transfer. Next, the device
transmits the data byte from the register address being read. After receiving the data byte, the controller device
transmits a not-acknowledge (NACK) followed by a stop condition to complete the single-byte data read transfer.
Repeat Start
Condition
Not
Start
Acknowledge
Condition
Acknowledge
Acknowledge
A0 ACK
Acknowledge
A6 A5
A1 A0 R/W ACK A7 A6 A5 A4
A6 A5
A1 A0 R/W ACK D7 D6
D1 D0 ACK
2
2
Stop
Condition
I C Device Address and
Read/Write Bit
Register
I C Device Address and
Read/Write Bit
Data Byte
图8-69. I2C Single-Byte Read Transfer
8.5.1.1.1.1.4 I2C Multiple-Byte Read
As shown in 图 8-70, a multiple-byte data read transfer is identical to a single-byte data read transfer except that
multiple data bytes are transmitted by the device to the controller device. With the exception of the last data byte,
the controller device responds with an acknowledge bit after receiving each data byte. After receiving the last
data byte, the controller device transmits a not-acknowledge (NACK) followed by a stop condition to complete
the data read transfer.
Repeat Start
Condition
Not
Start
Acknowledge
Condition
Acknowledge
Acknowledge
A0 ACK
Acknowledge
Acknowledge
Acknowledge
D0 ACK D7
A6
A0 R/W ACK A7 A6 A5
A6
A0 R/W ACK D7
D0 ACK D7
D0 ACK
2
2
Register
Stop
Condition
I C Device Address and
Read/Write Bit
I C Device Address and
Read/Write Bit
First Data Byte
Other Data Bytes
Last Data Byte
图8-70. I2C Multiple-Byte Read Transfer
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8.6 Register Maps
This section describes the control registers for the device in detail. All registers are eight bits in width and are
allocated to device configuration and programmable coefficients settings. These registers are mapped internally
using a page scheme that can be controlled using I2C communication to the device. Each page contains 128
bytes of registers. All device configuration registers are stored in page 0, which is the default page setting at
power up (and after a software reset). All programmable coefficient registers are located in page 2, page 3, and
page 4. The device current page can be switch to a new desired page by using the PAGE[7:0] bits located in
register 0 of every page.
Do not read from or write to reserved pages or reserved registers. Write only default values for the reserved bits
in the valid registers.
The procedure for register access across pages is:
• Select page N (write data N to register 0 regardless of the current page number)
• Read or write data from or to valid registers in page N
• Select the new page M (write data M to register 0 regardless of the current page number)
• Read or write data from or to valid registers in page M
• Repeat as needed
8.6.1 Device Configuration Registers
This section describes the device configuration registers for page 0 and page 1.
8.6.1.1 PCM3120-Q1 Access Codes
节8.6.1.1 lists the access codes used for the PCM3120-Q1 registers.
表8-50. PCMx120-Q1 Access Type Codes
ACCESS TYPE
CODE
DESCRIPTION
Read Type
R
R
Read
R-W
R/W
Read or write
Write Type
W
W
Write
Reset or Default Value
-n
Value after reset or the default value
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8.6.2 Page 0 Registers
表 8-51 lists the memory-mapped registers for the Page 0 registers. All register offset addresses not listed in 表
8-51 should be considered as reserved locations and the register contents should not be modified.
表8-51. PAGE 0 Registers
Address
0x0
Acronym
Register Name
Reset Value
0x00
0x00
0x00
0x05
0x30
0x00
0x00
0x00
0x00
0x01
0x02
0x03
0x02
0x48
0xFF
0x10
0x40
0x00
0x22
0x00
0x00
0x00
0x00
0x00
0x00
0xFF
0x00
0x00
0x00
0x00
0x00
0xC9
0x80
0x00
0x00
0x00
0xC9
0x80
0x00
Section
PAGE_CFG
SW_RESET
SLEEP_CFG
SHDN_CFG
ASI_CFG0
ASI_CFG1
ASI_CFG2
ASI_MIX_CFG
ASI_CH1
Device page register
节8.6.2.1
节8.6.2.2
节8.6.2.3
节8.6.2.4
节8.6.2.5
节8.6.2.6
节8.6.2.7
节8.6.2.8
节8.6.2.9
节8.6.2.10
节8.6.2.11
节8.6.2.12
节8.6.2.13
节8.6.2.14
节8.6.2.15
节8.6.2.16
节8.6.2.17
节8.6.2.18
节8.6.2.19
节8.6.2.20
节8.6.2.21
节8.6.2.22
节8.6.2.23
节8.6.2.24
节8.6.2.25
节8.6.2.26
节8.6.2.27
节8.6.2.28
节8.6.2.29
节8.6.2.30
节8.6.2.31
节8.6.2.32
节8.6.2.33
节8.6.2.34
节8.6.2.35
节8.6.2.36
节8.6.2.37
节8.6.2.38
节8.6.2.39
0x1
Software reset register
0x2
Sleep mode register
0x5
Shutdown configuration register
ASI configuration register 0
0x7
0x8
ASI configuration register 1
0x9
ASI configuration register 2
0xA
ASI input mixing configuration register
Channel 1 ASI slot configuration register
Channel 2 ASI slot configuration register
Channel 3 ASI slot configuration register
Channel 4 ASI slot configuration register
ASI master mode configuration register 0
ASI master mode configuration register 1
ASI bus clock monitor status register
Clock source configuration register 0
PDM clock generation configuration register
PDM DINx sampling edge register
GPIO configuration register 0
0xB
0xC
ASI_CH2
0xD
ASI_CH3
0xE
ASI_CH4
0x13
0x14
0x15
0x16
0x1F
0x20
0x21
0x22
0x29
0x2A
0x2B
0x2F
0x32
0x33
0x36
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x42
0x43
0x44
0x45
MST_CFG0
MST_CFG1
ASI_STS
CLK_SRC
PDMCLK_CFG
PDMIN_CFG
GPIO_CFG0
GPO_CFG0
GPO_VAL
GPO configuration register 0
GPIO, GPO output value register
GPIO monitor value register
GPIO_MON
GPI_CFG0
GPI_MON
GPI configuration register 0
GPI monitor value register
INT_CFG
Interrupt configuration register
Interrupt mask register 0
INT_MASK0
INT_LTCH0
CM_TOL_CFG
BIAS_CFG
CH1_CFG0
CH1_CFG1
CH1_CFG2
CH1_CFG3
CH1_CFG4
CH2_CFG0
CH2_CFG1
CH2_CFG2
CH2_CFG3
CH2_CFG4
Latched interrupt readback register 0
ADC common mode configuration register
Bias and ADC configuration register
Channel 1 configuration register 0
Channel 1 configuration register 1
Channel 1 configuration register 2
Channel 1 configuration register 3
Channel 1 configuration register 4
Channel 2 configuration register 0
Channel 2 configuration register 1
Channel 2 configuration register 2
Channel 2 configuration register 3
Channel 2 configuration register 4
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表8-51. PAGE 0 Registers (continued)
Address
0x48
0x49
0x4A
0x4D
0x4E
0x4F
0x6B
0x6C
0x70
0x71
0x73
0x74
0x75
0x76
0x77
0x7E
Acronym
Register Name
Reset Value
0xC9
0x80
Section
CH3_CFG2
CH3_CFG3
CH3_CFG4
CH4_CFG2
CH4_CFG3
CH4_CFG4
DSP_CFG0
DSP_CFG1
AGC_CFG0
GAIN_CFG
IN_CH_EN
ASI_OUT_CH_EN
PWR_CFG
DEV_STS0
DEV_STS1
I2C_CKSUM
Channel 3 configuration register 2
Channel 3 configuration register 3
Channel 3 configuration register 4
Channel 4 configuration register 2
Channel 4 configuration register 3
Channel 4 configuration register 4
DSP configuration register 0
节8.6.2.40
节8.6.2.41
节8.6.2.42
节8.6.2.43
节8.6.2.44
节8.6.2.45
节8.6.2.46
节8.6.2.47
节8.6.2.48
节8.6.2.49
节8.6.2.50
节8.6.2.51
节8.6.2.52
节8.6.2.53
节8.6.2.54
节8.6.2.55
0x00
0xC9
0x80
0x00
0x01
DSP configuration register 1
0x40
AGC configuration register 0
0xE7
0x00
Gain change Configuration
Input channel enable configuration register
ASI output channel enable configuration register
Power up configuration register
Device status value register 0
Device status value register 1
I2C checksum register
0xC0
0x00
0x00
0x00
0x80
0x00
8.6.2.1 PAGE_CFG Register (Address = 0x0) [Reset = 0x00]
PAGE_CFG is shown in 表8-52.
Return to the 表8-51.
The device memory map is divided into pages. This register sets the page.
表8-52. PAGE_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
PAGE[7:0]
R/W
00000000b These bits set the device page.
0d = Page 0
1d = Page 1
2d to 254d = Page 2 to page 254 respectively
255d = Page 255
8.6.2.2 SW_RESET Register (Address = 0x1) [Reset = 0x00]
SW_RESET is shown in 表8-53.
Return to the 表8-51.
This register is the software reset register. Asserting a software reset places all register values in their default
power-on-reset (POR) state.
表8-53. SW_RESET Register Field Descriptions
Bit
7-1
0
Field
Type
Reset
0000000b
0b
Description
RESERVED
SW_RESET
R
Reserved bits; Write only reset value
R/W
Software reset. This bit is self clearing.
0d = Do not reset
1d = Reset all registers to their reset values
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8.6.2.3 SLEEP_CFG Register (Address = 0x2) [Reset = 0x00]
SLEEP_CFG is shown in 表8-54.
Return to the 表8-51.
This register configures the regulator, VREF quick charge, I2C broadcast and sleep mode.
表8-54. SLEEP_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7
AREG_SELECT
R/W
0b
The analog supply selection from either the internal regulator supply
or the external AREG supply.
0d = External 1.8-V AREG supply (use this setting when AVDD is 1.8
V and short AREG with AVDD)
1d = Internally generated 1.8-V AREG supply using an on-chip
regulator (use this setting when AVDD is 3.3 V)
6-5
4-3
RESERVED
R/W
R/W
00b
00b
Reserved bits; Write only reset values
VREF_QCHG[1:0]
The duration of the quick-charge for the VREF external capacitor is
set using an internal series impedance of 200 Ω.
0d = VREF quick-charge duration of 3.5 ms (typical)
1d = VREF quick-charge duration of 10 ms (typical)
2d = VREF quick-charge duration of 50 ms (typical)
3d = VREF quick-charge duration of 100 ms (typical)
2
I2C_BRDCAST_EN
R/W
0b
I2C broadcast addressing setting.
0d = I2C broadcast mode disabled
1d = I2C broadcast mode enabled; the I2C target address is fixed at
1001 100
1
0
RESERVED
SLEEP_ENZ
R
0b
0b
Reserved bit; Write only reset value
R/W
Sleep mode setting.
0d = Device is in sleep mode
1d = Device is not in sleep mode
8.6.2.4 SHDN_CFG Register (Address = 0x5) [Reset = 0x05]
SHDN_CFG is shown in 表8-55.
Return to the 表8-51.
This register configures the device shutdown
表8-55. SHDN_CFG Register Field Descriptions
Bit
7-6
5-4
Field
Type
Reset
Description
RESERVED
INCAP_QCHG[1:0]
R
00b
Reserved bits; Write only reset value
R/W
00b
The duration of the quick-charge for the external AC-coupling
capacitor is set using an internal series impedance of 800 Ω.
0d = INxP, INxM quick-charge duration of 2.5 ms (typical)
1d = INxP, INxM quick-charge duration of 12.5 ms (typical)
2d = INxP, INxM quick-charge duration of 25 ms (typical)
3d = INxP, INxM quick-charge duration of 50 ms (typical)
3-2
1-0
RESERVED
RESERVED
R/W
R/W
01b
01b
Reserved bits; Write only reset values
Reserved bits; Write only reset values
8.6.2.5 ASI_CFG0 Register (Address = 0x7) [Reset = 0x30]
ASI_CFG0 is shown in 表8-56.
Return to the 表8-51.
This register is the ASI configuration register 0.
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表8-56. ASI_CFG0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
ASI_FORMAT[1:0]
R/W
00b
ASI protocol format.
0d = TDM mode
1d = I2S mode
2d = LJ (left-justified) mode
3d = Reserved; Don't use
5-4
ASI_WLEN[1:0]
R/W
11b
ASI word or slot length.
0d = 16 bits (Recommended this setting to be used with 10-kΩor
20-kΩinput impedance configuration)
1d = 20 bits
2d = 24 bits
3d = 32 bits
3
2
1
FSYNC_POL
BCLK_POL
TX_EDGE
R/W
R/W
R/W
0b
0b
0b
ASI FSYNC polarity.
0d = Default polarity as per standard protocol
1d = Inverted polarity with respect to standard protocol
ASI BCLK polarity.
0d = Default polarity as per standard protocol
1d = Inverted polarity with respect to standard protocol
ASI data output (on the primary and secondary data pin) transmit
edge.
0d = Default edge as per the protocol configuration setting in bit 2
(BCLK_POL)
1d = Inverted following edge (half cycle delay) with respect to the
default edge setting
0
TX_FILL
R/W
0b
ASI data output (on the primary and secondary data pin) for any
unused cycles
0d = Always transmit 0 for unused cycles
1d = Always use Hi-Z for unused cycles
8.6.2.6 ASI_CFG1 Register (Address = 0x8) [Reset = 0x00]
ASI_CFG1 is shown in 表8-57.
Return to the 表8-51.
This register is the ASI configuration register 1.
表8-57. ASI_CFG1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
TX_LSB
R/W
0b
ASI data output (on the primary and secondary data pin) for LSB
transmissions.
0d = Transmit the LSB for a full cycle
1d = Transmit the LSB for the first half cycle and Hi-Z for the second
half cycle
6-5
TX_KEEPER[1:0]
R/W
00b
ASI data output (on the primary and secondary data pin) bus keeper.
0d = Bus keeper is always disabled
1d = Bus keeper is always enabled
2d = Bus keeper is enabled during LSB transmissions only for one
cycle
3d = Bus keeper is enabled during LSB transmissions only for one
and half cycles
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表8-57. ASI_CFG1 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
4-0
TX_OFFSET[4:0]
R/W
00000b
ASI data MSB slot 0 offset (on the primary and secondary data pin).
0d = ASI data MSB location has no offset and is as per standard
protocol
1d = ASI data MSB location (TDM mode is slot 0 or I2S, LJ mode is
the left and right slot 0) offset of one BCLK cycle with respect to
standard protocol
2d = ASI data MSB location (TDM mode is slot 0 or I2S, LJ mode is
the left and right slot 0) offset of two BCLK cycles with respect to
standard protocol
3d to 30d = ASI data MSB location (TDM mode is slot 0 or I2S, LJ
mode is the left and right slot 0) offset assigned as per configuration
31d = ASI data MSB location (TDM mode is slot 0 or I2S, LJ mode is
the left and right slot 0) offset of 31 BCLK cycles with respect to
standard protocol
8.6.2.7 ASI_CFG2 Register (Address = 0x9) [Reset = 0x00]
ASI_CFG2 is shown in 表8-58.
Return to the 表8-51.
This register is the ASI configuration register 2.
表8-58. ASI_CFG2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
ASI_DAISY
R/W
0b
ASI daisy chain connection.
0d = All devices are connected in the common ASI bus
1d = All devices are daisy-chained for the ASI bus. This is supported
only if ASI input mixing is disabled, refer register 10 for details on
ASI input mixing feature.
6
5
RESERVED
ASI_ERR
R
0b
0b
Reserved bit; Write only reset value
R/W
ASI bus error detection.
0d = Enable bus error detection
1d = Disable bus error detection
4
ASI_ERR_RCOV
R/W
0b
ASI bus error auto resume.
0d = Enable auto resume after bus error recovery
1d = Disable auto resume after bus error recovery and remain
powered down until the host configures the device
3
RESERVED
RESERVED
R/W
R
0b
Reserved bit; Write only reset value
Reserved bits; Write only reset value
2-0
000b
8.6.2.8 ASI_MIX_CFG Register (Address = 0xA) [Reset = 0x00]
ASI_MIX_CFG is shown in 表8-59.
Return to the 表8-51.
This register is the ASI input mixing configuration register.
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表8-59. ASI_MIX_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
ASI_MIX_SEL[1:0]
R/W
00b
ASI input (from GPIx or GPIO) mixing selection with channel data.
0d = No mixing
1d = Channel 1 and channel 2 output data mixed with ASI input data
on channel 1 (slot 0)
2d = Channel 1 and channel 2 output data mixed with ASI input data
on channel 2 (slot 1)
3d = Mixed both channel data with ASI input data independently.
Mixed asi_in_ch_1 with channel 1 output data and similarly mix
asi_in_ch_2 with channel 2 output data
5-4
3
ASI_GAIN_SEL[1:0]
ASI_IN_INVERSE
R/W
R/W
00b
0b
ASI input data gain selection before mixing to channel data.
0d = No gain
1d = Gain asi input data by -6dB
2d = Gain asi input data by -12dB
3d = Gain asi input data by -18dB
Invert ASI input data before mixing to channel data.
0d = No inversion done for ASI input data
1d = ASI input data inverted before mixing with channel data
2
1
0
RESERVED
RESERVED
RESERVED
R
R
R
0b
0b
0b
Reserved bit; Write only reset value
Reserved bit; Write only reset value
Reserved bit; Write only reset value
8.6.2.9 ASI_CH1 Register (Address = 0xB) [Reset = 0x00]
ASI_CH1 is shown in 表8-60.
Return to the 表8-51.
This register is the ASI slot configuration register for channel 1.
表8-60. ASI_CH1 Register Field Descriptions
Bit
7-6
5-0
Field
Type
Reset
Description
RESERVED
CH1_SLOT[5:0]
R
00b
Reserved bits; Write only reset value
R/W
000000b
Channel 1 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0
1d = TDM is slot 1 or I2S, LJ is left slot 1
2d to 30d = Slot assigned as per configuration
31d = TDM is slot 31 or I2S, LJ is left slot 31
32d = TDM is slot 32 or I2S, LJ is right slot 0
33d = TDM is slot 33 or I2S, LJ is right slot 1
34d to 62d = Slot assigned as per configuration
63d = TDM is slot 63 or I2S, LJ is right slot 31
8.6.2.10 ASI_CH2 Register (Address = 0xC) [Reset = 0x01]
ASI_CH2 is shown in 表8-61.
Return to the 表8-51.
This register is the ASI slot configuration register for channel 2.
表8-61. ASI_CH2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
RESERVED
R
00b
Reserved bits; Write only reset value
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表8-61. ASI_CH2 Register Field Descriptions (continued)
Bit
Field
CH2_SLOT[5:0]
Type
Reset
Description
5-0
R/W
000001b
Channel 2 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0
1d = TDM is slot 1 or I2S, LJ is left slot 1
2d to 30d = Slot assigned as per configuration
31d = TDM is slot 31 or I2S, LJ is left slot 31
32d = TDM is slot 32 or I2S, LJ is right slot 0
33d = TDM is slot 33 or I2S, LJ is right slot 1
34d to 62d = Slot assigned as per configuration
63d = TDM is slot 63 or I2S, LJ is right slot 31
8.6.2.11 ASI_CH3 Register (Address = 0xD) [Reset = 0x02]
ASI_CH3 is shown in 表8-62.
Return to the 表8-51.
This register is the ASI slot configuration register for channel 3.
表8-62. ASI_CH3 Register Field Descriptions
Bit
7-6
5-0
Field
Type
Reset
Description
RESERVED
CH3_SLOT[5:0]
R
00b
Reserved bits; Write only reset value
R/W
000010b
Channel 3 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0
1d = TDM is slot 1 or I2S, LJ is left slot 1
2d to 30d = Slot assigned as per configuration
31d = TDM is slot 31 or I2S, LJ is left slot 31
32d = TDM is slot 32 or I2S, LJ is right slot 0
33d = TDM is slot 33 or I2S, LJ is right slot 1
34d to 62d = Slot assigned as per configuration
63d = TDM is slot 63 or I2S, LJ is right slot 31
8.6.2.12 ASI_CH4 Register (Address = 0xE) [Reset = 0x03]
ASI_CH4 is shown in 表8-63.
Return to the 表8-51.
This register is the ASI slot configuration register for channel 4.
表8-63. ASI_CH4 Register Field Descriptions
Bit
7-6
5-0
Field
Type
Reset
Description
RESERVED
CH4_SLOT[5:0]
R
00b
Reserved bits; Write only reset value
R/W
000011b
Channel 4 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0
1d = TDM is slot 1 or I2S, LJ is left slot 1
2d to 30d = Slot assigned as per configuration
31d = TDM is slot 31 or I2S, LJ is left slot 31
32d = TDM is slot 32 or I2S, LJ is right slot 0
33d = TDM is slot 33 or I2S, LJ is right slot 1
34d to 62d = Slot assigned as per configuration
63d = TDM is slot 63 or I2S, LJ is right slot 31
8.6.2.13 MST_CFG0 Register (Address = 0x13) [Reset = 0x02]
MST_CFG0 is shown in 表8-64.
Return to the 表8-51.
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This register is the ASI master mode configuration register 0.
表8-64. MST_CFG0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
MST_SLV_CFG
R/W
0b
ASI master or slave configuration register setting.
0d = Device is in slave mode (both BCLK and FSYNC are inputs to
the device)
1d = Device is in master mode (both BCLK and FSYNC are
generated from the device)
6
AUTO_CLK_CFG
R/W
0b
Automatic clock configuration setting.
0d = Auto clock configuration is enabled (all internal clock divider and
PLL configurations are auto derived)
1d = Auto clock configuration is disabled (custom mode and device
GUI must be used for the device configuration settings)
5
4
AUTO_MODE_PLL_DIS
BCLK_FSYNC_GATE
R/W
R/W
0b
0b
Automatic mode PLL setting.
0d = PLL is enabled in auto clock configuration
1d = PLL is disabled in auto clock configuration
BCLK and FSYNC clock gate (valid when the device is in master
mode).
0d = Do not gate BCLK and FSYNC
1d = Force gate BCLK and FSYNC when being transmitted from the
device in master mode
3
FS_MODE
R/W
R/W
0b
Sample rate setting (valid when the device is in master mode).
0d = fS is a multiple (or submultiple) of 48 kHz
1d = fS is a multiple (or submultiple) of 44.1 kHz
2-0
MCLK_FREQ_SEL[2:0]
010b
These bits select the MCLK (GPIO or GPIx) frequency for the PLL
source clock input (valid when the device is in master mode and
MCLK_FREQ_SEL_MODE = 0).
0d = 12 MHz
1d = 12.288 MHz
2d = 13 MHz
3d = 16 MHz
4d = 19.2 MHz
5d = 19.68 MHz
6d = 24 MHz
7d = 24.576 MHz
8.6.2.14 MST_CFG1 Register (Address = 0x14) [Reset = 0x48]
MST_CFG1 is shown in 表8-65.
Return to the 表8-51.
This register is the ASI master mode configuration register 1.
表8-65. MST_CFG1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
FS_RATE[3:0]
R/W
0100b
Programmed sample rate of the ASI bus (not used when the device
is configured in slave mode auto clock configuration).
0d = 7.35 kHz or 8 kHz
1d = 14.7 kHz or 16 kHz
2d = 22.05 kHz or 24 kHz
3d = 29.4 kHz or 32 kHz
4d = 44.1 kHz or 48 kHz
5d = 88.2 kHz or 96 kHz
6d = 176.4 kHz or 192 kHz
7d = 352.8 kHz or 384 kHz
8d = 705.6 kHz or 768 kHz
9d to 15d = Reserved; Don't use
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表8-65. MST_CFG1 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3-0
FS_BCLK_RATIO[3:0]
R/W
1000b
Programmed BCLK to FSYNC frequency ratio of the ASI bus (not
used when the device is configured in slave mode auto clock
configuration).
0d = Ratio of 16
1d = Ratio of 24
2d = Ratio of 32
3d = Ratio of 48
4d = Ratio of 64
5d = Ratio of 96
6d = Ratio of 128
7d = Ratio of 192
8d = Ratio of 256
9d = Ratio of 384
10d = Ratio of 512
11d = Ratio of 1024
12d = Ratio of 2048
13d to 15d = Reserved; Don't use
8.6.2.15 ASI_STS Register (Address = 0x15) [Reset = 0xFF]
ASI_STS is shown in 表8-66.
Return to the 表8-51.
This register s the ASI bus clock monitor status register
表8-66. ASI_STS Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
FS_RATE_STS[3:0]
R
1111b
Detected sample rate of the ASI bus.
0d = 7.35 kHz or 8 kHz
1d = 14.7 kHz or 16 kHz
2d = 22.05 kHz or 24 kHz
3d = 29.4 kHz or 32 kHz
4d = 44.1 kHz or 48 kHz
5d = 88.2 kHz or 96 kHz
6d = 176.4 kHz or 192 kHz
7d = 352.8 kHz or 384 kHz
8d = 705.6 kHz or 768 kHz
9d to 14d = Reserved status
15d = Invalid sample rate
3-0
FS_RATIO_STS[3:0]
R
1111b
Detected BCLK to FSYNC frequency ratio of the ASI bus.
0d = Ratio of 16
1d = Ratio of 24
2d = Ratio of 32
3d = Ratio of 48
4d = Ratio of 64
5d = Ratio of 96
6d = Ratio of 128
7d = Ratio of 192
8d = Ratio of 256
9d = Ratio of 384
10d = Ratio of 512
11d = Ratio of 1024
12d = Ratio of 2048
13d to 14d = Reserved status
15d = Invalid ratio
8.6.2.16 CLK_SRC Register (Address = 0x16) [Reset = 0x10]
CLK_SRC is shown in 表8-67.
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Return to the 表8-51.
This register is the clock source configuration register.
表8-67. CLK_SRC Register Field Descriptions
Bit
Field
Type
Reset
Description
7
DIS_PLL_SLV_CLK_SRC R/W
0b
Audio root clock source setting when the device is configured with
the PLL disabled in the auto clock configuration for slave mode
(AUTO_MODE_PLL_DIS = 1).
0d = BCLK is used as the audio root clock source
1d = MCLK (GPIO or GPIx) is used as the audio root clock source
(the MCLK to FSYNC ratio is as per MCLK_RATIO_SEL setting)
6
MCLK_FREQ_SEL_MOD R/W
E
0b
Master mode MCLK (GPIO or GPIx) frequency selection mode (valid
when the device is in auto clock configuration).
0d = MCLK frequency is based on the MCLK_FREQ_SEL (P0_R19)
configuration
1d = MCLK frequency is specified as a multiple of FSYNC in the
MCLK_RATIO_SEL (P0_R22) configuration
5-3
MCLK_RATIO_SEL[2:0]
R/W
010b
These bits select the MCLK (GPIO or GPIx) to FSYNC ratio for
master mode or when MCLK is used as the audio root clock source
in slave mode.
0d = Ratio of 64
1d = Ratio of 256
2d = Ratio of 384
3d = Ratio of 512
4d = Ratio of 768
5d = Ratio of 1024
6d = Ratio of 1536
7d = Ratio of 2304
2
1
RESERVED
R/W
0b
0b
Reserved bit; Write only reset value
INV_BCLK_FOR_FSYNC R/W
Invert BCLK polarity only for FSYNC generation in master mode
configuration.
0d = Do not invert BCLK polarity for FSYNC generation
1d = Invert BCLK polarity for FSYNC generation
0
RESERVED
R/W
0b
Reserved bit; Write only reset value
8.6.2.17 PDMCLK_CFG Register (Address = 0x1F) [Reset = 0x40]
PDMCLK_CFG is shown in 表8-68.
Return to the 表8-51.
This register is the PDM clock generation configuration register.
表8-68. PDMCLK_CFG Register Field Descriptions
Bit
7
Field
Type
Reset
Description
RESERVED
RESERVED
PDMCLK_DIV[1:0]
R/W
0b
Reserved bit; Write only reset value
6-2
1-0
R/W
R/W
10000b
00b
Reserved bits; Write only reset values
PDMCLK divider value.
0d = PDMCLK is 2.8224 MHz or 3.072 MHz
1d = PDMCLK is 1.4112 MHz or 1.536 MHz
2d = PDMCLK is 705.6 kHz or 768 kHz
3d = PDMCLK is 5.6448 MHz or 6.144 MHz (applicable only for PDM
channel 1 and 2)
8.6.2.18 PDMIN_CFG Register (Address = 0x20) [Reset = 0x00]
PDMIN_CFG is shown in 表8-69.
Return to the 表8-51.
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This register is the PDM DINx sampling edge configuration register.
表8-69. PDMIN_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7
PDMDIN1_EDGE
R/W
0b
PDMCLK latching edge used for channel 1 and channel 2 data.
0d = Channel 1 data are latched on the negative edge, channel 2
data are latched on the positive edge
1d = Channel 1 data are latched on the positive edge, channel 2 data
are latched on the negative edge
6
RESERVED
RESERVED
R/W
R
0b
Reserved bit; Write only reset value
Reserved bits; Write only reset value
5-0
000000b
8.6.2.19 GPIO_CFG0 Register (Address = 0x21) [Reset = 0x22]
GPIO_CFG0 is shown in 表8-70.
Return to the 表8-51.
This register is the GPIO configuration register 0.
表8-70. GPIO_CFG0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
GPIO1_CFG[3:0]
R/W
0010b
GPIO1 configuration.
0d = GPIO1 is disabled
1d = GPIO1 is configured as a general-purpose output (GPO)
2d = GPIO1 is configured as a device interrupt output (IRQ)
3d = Reserved; Don't use
4d = GPIO1 is configured as a PDM clock output (PDMCLK)
5d = Reserved; Don't use
6d = Reserved; Don't use
7d = PD all ADC channels
8d = GPIO1 is configured as an input to control when MICBIAS turns
on or off (MICBIAS_EN)
9d = GPIO1 is configured as a general-purpose input (GPI)
10d = GPIO1 is configured as a master clock input (MCLK)
11d = GPIO1 is configured as an ASI input for daisy-chain or ASI
input for mixing (SDIN)
12d = GPIO1 is configured as a PDM data input for channel 1 and
channel 2 (PDMDIN1)
13d = GPIO1 is configured as a PDM data input for channel 3 and
channel 4 (PDMDIN2)
14d to 15d = Reserved; Don't use
3
RESERVED
R
0b
Reserved bit; Write only reset value
2-0
GPIO1_DRV[2:0]
R/W
010b
GPIO1 output drive configuration.
0d = Hi-Z output
1d = Drive active low and active high
2d = Drive active low and weak high
3d = Drive active low and Hi-Z
4d = Drive weak low and active high
5d = Drive Hi-Z and active high
6d to 7d = Reserved; Don't use
8.6.2.20 GPO_CFG0 Register (Address = 0x22) [Reset = 0x00]
GPO_CFG0 is shown in 表8-71.
Return to the 表8-51.
This registeris the GPO configuration register 0.
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表8-71. GPO_CFG0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
GPO1_CFG[3:0]
R/W
0000b
IN2M_GPO1 (GPO1) configuration.
0d = GPO1 is disabled
1d = GPO1 is configured as a general-purpose output (GPO)
2d = GPO1 is configured as a device interrupt output (IRQ)
3d = Reserved; Don't use
4d = GPO1 is configured as a PDM clock output (PDMCLK)
5d to 15d = Reserved; Don't use
3
RESERVED
R
0b
Reserved bit; Write only reset value
2-0
GPO1_DRV[2:0]
R/W
000b
IN2M_GPO1 (GPO1) output drive configuration.
0d = Hi-Z output
1d = Drive active low and active high
2d = Reserved; Don't use
3d = Drive active low and Hi-Z
4d = Reserved; Don't use
5d = Drive Hi-Z and active high
6d to 7d = Reserved; Don't use
8.6.2.21 GPO_VAL Register (Address = 0x29) [Reset = 0x00]
GPO_VAL is shown in 表8-72.
Return to the 表8-51.
This register is the GPIO and GPO output value register.
表8-72. GPO_VAL Register Field Descriptions
Bit
Field
Type
Reset
Description
7
GPIO1_VAL
R/W
0b
GPIO1 output value when configured as a GPO.
0d = Drive the output with a value of 0
1d = Drive the output with a value of 1
6
GPO1_VAL
RESERVED
R/W
R
0b
GPO1 output value when configured as a GPO.
0d = Drive the output with a value of 0
1d = Drive the output with a value of 1
5-0
000000b
Reserved bits; Write only reset value
8.6.2.22 GPIO_MON Register (Address = 0x2A) [Reset = 0x00]
GPIO_MON is shown in 表8-73.
Return to the 表8-51.
This register is the GPIO monitor value register.
表8-73. GPIO_MON Register Field Descriptions
Bit
Field
Type
Reset
Description
7
GPIO1_MON
R
0b
GPIO1 monitor value when configured as a GPI.
0d = Input monitor value 0
1d = Input monitor value 1
6-0
RESERVED
R
0000000b
Reserved bits; Write only reset value
8.6.2.23 GPI_CFG0 Register (Address = 0x2B) [Reset = 0x00]
GPI_CFG0 is shown in 表8-74.
Return to the 表8-51.
This register is the GPI configuration register 0.
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表8-74. GPI_CFG0 Register Field Descriptions
Bit
7
Field
Type
Reset
Description
RESERVED
R
0b
Reserved bit; Write only reset value
6-4
GPI1_CFG[2:0]
R/W
000b
IN2P_GPI1 (GPI1) configuration.
0d = GPI1 is disabled
1d = GPI1 is configured as a general-purpose input (GPI)
2d = GPI1 is configured as a master clock input (MCLK)
3d = GPI1 is configured as an ASI input for daisy-chain or ASI input
for mixing (SDIN)
4d = GPI1 is configured as a PDM data input for channel 1 and
channel 2 (PDMDIN1)
5d = GPI1 is configured as a PDM data input for channel 3 and
channel 4 (PDMDIN2)
6d = Reserved; Don't use
7d = PD all ADC channels
3
RESERVED
R
0b
Reserved bit; Write only reset value
2-0
GPI2_CFG[2:0]
R/W
000b
MICBIAS as GPI2 configuration.
0d = GPI2 is disabled
1d = GPI2 is configured as a general-purpose input (GPI)
2d = GPI2 is configured as a master clock input (MCLK)
3d = GPI2 is configured as an ASI input for daisy-chain or ASI input
for mixing (SDIN)
4d = GPI2 is configured as a PDM data input for channel 1 and
channel 2 (PDMDIN1)
5d = GPI2 is configured as a PDM data input for channel 3 and
channel 4 (PDMDIN2)
6d = Reserved; Don't use
7d = PD all ADC channels
8.6.2.24 GPI_MON Register (Address = 0x2F) [Reset = 0x00]
GPI_MON is shown in 表8-75.
Return to the 表8-51.
This regiser is the GPI monitor value register.
表8-75. GPI_MON Register Field Descriptions
Bit
Field
Type
Reset
Description
7
GPI1_MON
R
0b
GPI1 monitor value when configured as a GPI.
0d = Input monitor value 0
1d = Input monitor value 1
6
GPI2_MON
RESERVED
R
R
0b
GPI2 monitor value when MICBIAS is configured as a GPI.
0d = Input monitor value 0
1d = Input monitor value 1
5-0
000000b
Reserved bits; Write only reset value
8.6.2.25 INT_CFG Register (Address = 0x32) [Reset = 0x00]
INT_CFG is shown in 表8-76.
Return to the 表8-51.
This regiser is the interrupt configuration register.
表8-76. INT_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7
INT_POL
R/W
0b
Interrupt polarity.
0d = Active low (IRQZ)
1d = Active high (IRQ)
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表8-76. INT_CFG Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
6-5
INT_EVENT[1:0]
R/W
00b
Interrupt event configuration.
0d = INT asserts on any unmasked latched interrupts event
Dont use
2d = INT asserts for 2 ms (typical) for every 4-ms (typical) duration
on any unmasked latched interrupts event
3d = INT asserts for 2 ms (typical) one time on each pulse for any
unmasked interrupts event
4-3
2
RESERVED
R
00b
0b
Reserved bits; Write only reset value
LTCH_READ_CFG
R/W
Interrupt latch registers readback configuration.
0d = All interrupts can be read through the LTCH registers
1d = Only unmasked interrupts can be read through the LTCH
registers
1-0
RESERVED
R
00b
Reserved bits; Write only reset value
8.6.2.26 INT_MASK0 Register (Address = 0x33) [Reset = 0xFF]
INT_MASK0 is shown in 表8-77.
Return to the 表8-51.
This register is the interrupt masks register 0.
表8-77. INT_MASK0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
INT_MASK0
R/W
1b
ASI clock error mask.
0d = Do not mask
1d = Mask
6
5
4
3
INT_MASK0
INT_MASK0
INT_MASK0
INT_MASK0
R/W
R/W
R/W
R/W
1b
1b
1b
1b
PLL Lock interrupt mask.
0d = Do not mask
1d = Mask
ASI input mixing saturation alert mask.
0d = Do not mask
1d = Mask
VAD Power up detect interrupt mask.
0d = Do not mask
1d = Mask
VAD Power down detect interrupt mask.
0d = Do not mask
1d = Mask
2
1
0
RESERVED
RESERVED
RESERVED
R/W
R/W
R/W
1b
1b
1b
Reserved bit; Write only reset value
Reserved bit; Write only reset value
Reserved bit; Write only reset value
8.6.2.27 INT_LTCH0 Register (Address = 0x36) [Reset = 0x00]
INT_LTCH0 is shown in 表8-78.
Return to the 表8-51.
This register is the latched Interrupt readback register 0.
表8-78. INT_LTCH0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
INT_LTCH0
R
0b
Interrupt caused by an ASI bus clock error (self-clearing bit).
0d = No interrupt
1d = Interrupt
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表8-78. INT_LTCH0 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
6
INT_LTCH0
R
0b
Interrupt caused by PLL LOCK (self-clearing bit).
0d = No interrupt
1d = Interrupt
5
INT_LTCH0
R
0b
Interrupt caused by ASI input mixing channel saturation alert (self
clearing bit).
0d = No interrupt
1d = Interrupt
4
3
INT_LTCH0
INT_LTCH0
R
R
0b
0b
Interrupt caused by VAD power up detect (self clearing bit).
0d = No interrupt
1d = Interrupt
Interrupt caused by VAD power down detect (self clearing bit).
0d = No interrupt
1d = Interrupt
2
1
0
RESERVED
RESERVED
RESERVED
R
R
R
0b
0b
0b
Reserved bit; Write only reset value
Reserved bit; Write only reset value
Reserved bit; Write only reset value
8.6.2.28 CM_TOL_CFG Register (Address = 0x3A) [Reset = 0x00]
CM_TOL_CFG is shown in 表8-79.
Return to the 表8-51.
This register is the ADC common mode configuration register
表8-79. CM_TOL_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
CH1_INP_CM_TOL_CFG[ R/W
1:0]
00b
Channel 1 input common mode variance tolerance configuration.
0d = Common mode variance tolerance for AC coupled = 100 mVpp
and DC coupled = 2.82 Vpp
1d = Common Mode Tolerance of: AC/DC Coupled Input=1V peak to
peak
2d = Common Mode Tolerance of: AC/DC Coupled Input=0-
AVDD(Supported only with Input Impendance of 10 kΩ/20 kΩ). For
input impedance of 2.5 kΩ, input common mode tolerance= 0.4V to
2.6V.
3d = Reserved; Don't use
5-4
CH2_INP_CM_TOL_CFG[ R/W
1:0]
00b
Channel 2 input common mode variance tolerance configuration.
0d = Common mode variance tolerance for AC coupled = 100 mVpp
and DC coupled = 2.82 Vpp
1d = Common Mode Tolerance of: AC/DC Coupled Input=1V peak to
peak
2d = Common Mode Tolerance of: AC/DC Coupled Input=0-
AVDD(Supported only with Input Impendance of 10 kΩ/20 kΩ). For
input impedance of 2.5 kΩ, input common mode tolerance= 0.4V to
2.6V.
3d = Reserved; Don't use
3-0
RESERVED
R
0000b
Reserved bits; Write only reset value
8.6.2.29 BIAS_CFG Register (Address = 0x3B) [Reset = 0x00]
BIAS_CFG is shown in 表8-80.
Return to the 表8-51.
This register is the bias and ADC configuration register
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表8-80. BIAS_CFG Register Field Descriptions
Bit
7
Field
Type
Reset
Description
RESERVED
MBIAS_VAL[2:0]
R
0b
Reserved bit; Write only reset value
MICBIAS value.
6-4
R/W
000b
0d = Microphone bias is set to VREF (2.750 V, 2.500 V, or 1.375 V)
1d = Microphone bias is set to VREF x 1.096 (3.014 V, 2.740 V, or
1.507 V)
2d = Microphone bias is set to VCM = IN1M, for ADC single-ended
configuration
3d = Microphone bias is set to VCM = IN2M, for ADC single-ended
configuration
4d = Microphone bias is set to VCM = average of IN1M and IN2M,
for ADC single-ended configuration
5d = Microphone bias is set to VCM = internal crude common mode
6d = Microphone bias is set to AVDD
7d = MICBIAS configured as GPI2
3-2
1-0
RESERVED
R
00b
00b
Reserved bits; Write only reset value
ADC_FSCALE[1:0]
R/W
ADC full-scale setting (configure this setting based on the AVDD
supply minimum voltage used).
0d = VREF is set to 2.75 V to support 2 VRMS for the differential input
or 1 VRMS for the single-ended input
1d = VREF is set to 2.5 V to support 1.818 VRMS for the differential
input or 0.909 VRMS for the single-ended input
2d = VREF is set to 1.375 V to support 1 VRMS for the differential
input or 0.5 VRMS for the single-ended input
3d = Reserved; Don't use
8.6.2.30 CH1_CFG0 Register (Address = 0x3C) [Reset = 0x00]
CH1_CFG0 is shown in 表8-81.
Return to the 表8-51.
This register is configuration register 0 for channel 1.
表8-81. CH1_CFG0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
CH1_INTYP
R/W
0b
Channel 1 input type.
0d = Microphone input
1d = Line input
6-5
CH1_INSRC[1:0]
R/W
00b
Channel 1 input configuration.
0d = Analog differential input
1d = Analog single-ended input
2d = Digital microphone PDM input (configure the GPO and GPI pins
accordingly for PDMDIN1 and PDMCLK)
3d = Reserved; Don't use
4
CH1_DC
R/W
R/W
0b
Channel 1 input coupling (applicable for the analog input).
0d = AC-coupled input
1d = DC-coupled input
3-2
CH1_IMP[1:0]
00b
Channel 1 input impedance (applicable for the analog input).
0d = Typical 2.5-kΩinput impedance
1d = Typical 10-kΩinput impedance
2d = Typical 20-kΩinput impedance
3d = Reserved; Don't use
1
0
RESERVED
R
0b
0b
Reserved bit; Write only reset value
CH1_AGCEN
R/W
Channel 1 automatic gain controller (AGC) setting.
0d = AGC disabled
1d = AGC enabled based on the configuration of bit 3 in register 108
(P0_R108)
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8.6.2.31 CH1_CFG1 Register (Address = 0x3D) [Reset = 0x00]
CH1_CFG1 is shown in 表8-82.
Return to the 表8-51.
This register is configuration register 1 for channel 1.
表8-82. CH1_CFG1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-1
CH1_GAIN[6:0]
R/W
0000000b
Channel 1 gain.
0d = Channel gain is set to 0 dB
1d = Channel gain is set to 0.5 dB
2d = Channel gain is set to 1 dB
3d to 83d = Channel gain is set as per configuration
84d = Channel gain is set to 42 dB
85d to 127d = Reserved; Don't use
0
CH1_GAIN_SIGN_BIT
R/W
0b
Channel-1 gain sign configuration.
0d = Positive channel gain
1d = Negative channel gain (minimum channel gain supported till -11
dB; supported only for channel input impedance of 10-kΩand 20-
kΩ)
8.6.2.32 CH1_CFG2 Register (Address = 0x3E) [Reset = 0xC9]
CH1_CFG2 is shown in 表8-83.
Return to the 表8-51.
This register is configuration register 2 for channel 1.
表8-83. CH1_CFG2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
CH1_DVOL[7:0]
R/W
11001001b Channel 1 digital volume control.
0d = Digital volume is muted
1d = Digital volume control is set to -100 dB
2d = Digital volume control is set to -99.5 dB
3d to 200d = Digital volume control is set as per configuration
201d = Digital volume control is set to 0 dB
202d = Digital volume control is set to 0.5 dB
203d to 253d = Digital volume control is set as per configuration
254d = Digital volume control is set to 26.5 dB
255d = Digital volume control is set to 27 dB
8.6.2.33 CH1_CFG3 Register (Address = 0x3F) [Reset = 0x80]
CH1_CFG3 is shown in 表8-84.
Return to the 表8-51.
This register is configuration register 3 for channel 1.
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表8-84. CH1_CFG3 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
CH1_GCAL[3:0]
R/W
1000b
Channel 1 gain calibration.
0d = Gain calibration is set to -0.8 dB
1d = Gain calibration is set to -0.7 dB
2d = Gain calibration is set to -0.6 dB
3d to 7d = Gain calibration is set as per configuration
8d = Gain calibration is set to 0 dB
9d = Gain calibration is set to 0.1 dB
10d to 13d = Gain calibration is set as per configuration
14d = Gain calibration is set to 0.6 dB
15d = Gain calibration is set to 0.7 dB
3-0
RESERVED
R
0000b
Reserved bits; Write only reset value
8.6.2.34 CH1_CFG4 Register (Address = 0x40) [Reset = 0x00]
CH1_CFG4 is shown in 表8-85.
Return to the 表8-51.
This register is configuration register 4 for channel 1.
表8-85. CH1_CFG4 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
CH1_PCAL[7:0]
R/W
00000000b Channel 1 phase calibration with modulator clock resolution.
0d = No phase calibration
1d = Phase calibration delay is set to one cycle of the modulator
clock
2d = Phase calibration delay is set to two cycles of the modulator
clock
3d to 254d = Phase calibration delay as per configuration
255d = Phase calibration delay is set to 255 cycles of the modulator
clock
8.6.2.35 CH2_CFG0 Register (Address = 0x41) [Reset = 0x00]
CH2_CFG0 is shown in 表8-86.
Return to the 表8-51.
This register is configuration register 0 for channel 2.
表8-86. CH2_CFG0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
CH2_INTYP
R/W
0b
Channel 2 input type.
0d = Microphone input
1d = Line input
6-5
CH2_INSRC[1:0]
R/W
00b
Channel 2 input configuration.
0d = Analog differential input (the GPI1 and GPO1 pin functions must
be disabled)
1d = Analog single-ended input (the GPI1 and GPO1 pin functions
must be disabled)
2d = Digital microphone PDM input (configure the GPO and GPI pins
accordingly for PDMDIN1 and PDMCLK)
3d = Reserved; Don't use
4
CH2_DC
R/W
0b
Channel 2 input coupling (applicable for the analog input).
0d = AC-coupled input
1d = DC-coupled input
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表8-86. CH2_CFG0 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3-2
CH2_IMP[1:0]
R/W
00b
Channel 2 input impedance (applicable for the analog input).
0d = Typical 2.5-kΩinput impedance
1d = Typical 10-kΩinput impedance
2d = Typical 20-kΩinput impedance
3d = Reserved; Don't use
1
0
RESERVED
R
0b
0b
Reserved bit; Write only reset value
CH2_AGCEN
R/W
Channel 2 automatic gain controller (AGC) setting.
0d = AGC disabled
1d = AGC enabled based on the configuration of bit 3 in register 108
(P0_R108)
8.6.2.36 CH2_CFG1 Register (Address = 0x42) [Reset = 0x00]
CH2_CFG1 is shown in 表8-87.
Return to the 表8-51.
This register is configuration register 1 for channel 2.
表8-87. CH2_CFG1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-1
CH2_GAIN[6:0]
R/W
0000000b
Channel 2 gain.
0d = Channel gain is set to 0 dB
1d = Channel gain is set to 0.5 dB
2d = Channel gain is set to 1 dB
3d to 83d = Channel gain is set as per configuration
84d = Channel gain is set to 42 dB
85d to 127d = Reserved; Don't use
0
CH2_GAIN_SIGN_BIT
R/W
0b
Channel-2 gain sign configuration.
0d = Positive channel gain
1d = Negative channel gain (minimum channel gain supported till -11
dB; supported only for channel input impedance of 10-kΩand 20-
kΩ)
8.6.2.37 CH2_CFG2 Register (Address = 0x43) [Reset = 0xC9]
CH2_CFG2 is shown in 表8-88.
Return to the 表8-51.
This register is configuration register 2 for channel 2.
表8-88. CH2_CFG2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
CH2_DVOL[7:0]
R/W
11001001b Channel 2 digital volume control.
0d = Digital volume is muted
1d = Digital volume control is set to -100 dB
2d = Digital volume control is set to -99.5 dB
3d to 200d = Digital volume control is set as per configuration
201d = Digital volume control is set to 0 dB
202d = Digital volume control is set to 0.5 dB
203d to 253d = Digital volume control is set as per configuration
254d = Digital volume control is set to 26.5 dB
255d = Digital volume control is set to 27 dB
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8.6.2.38 CH2_CFG3 Register (Address = 0x44) [Reset = 0x80]
CH2_CFG3 is shown in 表8-89.
Return to the 表8-51.
This register is configuration register 3 for channel 2.
表8-89. CH2_CFG3 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
CH2_GCAL[3:0]
R/W
1000b
Channel 2 gain calibration.
0d = Gain calibration is set to -0.8 dB
1d = Gain calibration is set to -0.7 dB
2d = Gain calibration is set to -0.6 dB
3d to 7d = Gain calibration is set as per configuration
8d = Gain calibration is set to 0 dB
9d = Gain calibration is set to 0.1 dB
10d to 13d = Gain calibration is set as per configuration
14d = Gain calibration is set to 0.6 dB
15d = Gain calibration is set to 0.7 dB
3-0
RESERVED
R
0000b
Reserved bits; Write only reset value
8.6.2.39 CH2_CFG4 Register (Address = 0x45) [Reset = 0x00]
CH2_CFG4 is shown in 表8-90.
Return to the 表8-51.
This register is configuration register 4 for channel 2.
表8-90. CH2_CFG4 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
CH2_PCAL[7:0]
R/W
00000000b Channel 2 phase calibration with modulator clock resolution.
0d = No phase calibration
1d = Phase calibration delay is set to one cycle of the modulator
clock
2d = Phase calibration delay is set to two cycles of the modulator
clock
3d to 254d = Phase calibration delay as per configuration
255d = Phase calibration delay is set to 255 cycles of the modulator
clock
8.6.2.40 CH3_CFG2 Register (Address = 0x48) [Reset = 0xC9]
CH3_CFG2 is shown in 表8-91.
Return to the 表8-51.
This register is configuration register 2 for channel 3.
表8-91. CH3_CFG2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
CH3_DVOL[7:0]
R/W
11001001b Channel 3 digital volume control.
0d = Digital volume is muted
1d = Digital volume control is set to -100 dB
2d = Digital volume control is set to -99.5 dB
3d to 200d = Digital volume control is set as per configuration
201d = Digital volume control is set to 0 dB
202d = Digital volume control is set to 0.5 dB
203d to 253d = Digital volume control is set as per configuration
254d = Digital volume control is set to 26.5 dB
255d = Digital volume control is set to 27 dB
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8.6.2.41 CH3_CFG3 Register (Address = 0x49) [Reset = 0x80]
CH3_CFG3 is shown in 表8-92.
Return to the 表8-51.
This register is configuration register 3 for channel 3.
表8-92. CH3_CFG3 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
CH3_GCAL[3:0]
R/W
1000b
Channel 3 gain calibration.
0d = Gain calibration is set to -0.8 dB
1d = Gain calibration is set to -0.7 dB
2d = Gain calibration is set to -0.6 dB
3d to 7d = Gain calibration is set as per configuration
8d = Gain calibration is set to 0 dB
9d = Gain calibration is set to 0.1 dB
10d to 13d = Gain calibration is set as per configuration
14d = Gain calibration is set to 0.6 dB
15d = Gain calibration is set to 0.7 dB
3-0
RESERVED
R
0000b
Reserved bits; Write only reset value
8.6.2.42 CH3_CFG4 Register (Address = 0x4A) [Reset = 0x00]
CH3_CFG4 is shown in 表8-93.
Return to the 表8-51.
This register is configuration register 4 for channel 3.
表8-93. CH3_CFG4 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
CH3_PCAL[7:0]
R/W
00000000b Channel 3 phase calibration with modulator clock resolution.
0d = No phase calibration
1d = Phase calibration delay is set to one cycle of the modulator
clock
2d = Phase calibration delay is set to two cycles of the modulator
clock
3d to 254d = Phase calibration delay as per configuration
255d = Phase calibration delay is set to 255 cycles of the modulator
clock
8.6.2.43 CH4_CFG2 Register (Address = 0x4D) [Reset = 0xC9]
CH4_CFG2 is shown in 表8-94.
Return to the 表8-51.
This register is configuration register 2 for channel 4.
表8-94. CH4_CFG2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
CH4_DVOL[7:0]
R/W
11001001b Channel 4 digital volume control.
0d = Digital volume is muted
1d = Digital volume control is set to -100 dB
2d = Digital volume control is set to -99.5 dB
3d to 200d = Digital volume control is set as per configuration
201d = Digital volume control is set to 0 dB
202d = Digital volume control is set to 0.5 dB
203d to 253d = Digital volume control is set as per configuration
254d = Digital volume control is set to 26.5 dB
255d = Digital volume control is set to 27 dB
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8.6.2.44 CH4_CFG3 Register (Address = 0x4E) [Reset = 0x80]
CH4_CFG3 is shown in 表8-95.
Return to the 表8-51.
This register is configuration register 3 for channel 4.
表8-95. CH4_CFG3 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
CH4_GCAL[3:0]
R/W
1000b
Channel 4 gain calibration.
0d = Gain calibration is set to -0.8 dB
1d = Gain calibration is set to -0.7 dB
2d = Gain calibration is set to -0.6 dB
3d to 7d = Gain calibration is set as per configuration
8d = Gain calibration is set to 0 dB
9d = Gain calibration is set to 0.1 dB
10d to 13d = Gain calibration is set as per configuration
14d = Gain calibration is set to 0.6 dB
15d = Gain calibration is set to 0.7 dB
3-0
RESERVED
R
0000b
Reserved bits; Write only reset value
8.6.2.45 CH4_CFG4 Register (Address = 0x4F) [Reset = 0x00]
CH4_CFG4 is shown in 表8-96.
Return to the 表8-51.
This register is configuration register 4 for channel 4.
表8-96. CH4_CFG4 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
CH4_PCAL[7:0]
R/W
00000000b Channel 4 phase calibration with modulator clock resolution.
0d = No phase calibration
1d = Phase calibration delay is set to one cycle of the modulator
clock
2d = Phase calibration delay is set to two cycles of the modulator
clock
3d to 254d = Phase calibration delay as per configuration
255d = Phase calibration delay is set to 255 cycles of the modulator
clock
8.6.2.46 DSP_CFG0 Register (Address = 0x6B) [Reset = 0x01]
DSP_CFG0 is shown in 表8-97.
Return to the 表8-51.
This register is the digital signal processor (DSP) configuration register 0.
表8-97. DSP_CFG0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
DIS_DVOL_OTF_CHG
R/W
0b
Disable run-time changes to DVOL settings.
0d = Digital volume control changes supported while ADC is
powered-on
1d = Digital volume control changes not supported while ADC is
powered-on. This is useful for 384 kHz and higher sample rate if
more than one channel processing is required.
6
RESERVED
R/W
0b
Reserved bit; Write only reset value
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表8-97. DSP_CFG0 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
5-4
DECI_FILT[1:0]
R/W
00b
Decimation filter response.
0d = Linear phase
1d = Low latency
2d = Ultra-low latency
3d = Reserved; Don't use
3-2
1-0
CH_SUM[1:0]
R/W
R/W
00b
01b
Channel summation mode for higher SNR
0d = Channel summation mode is disabled
1d = 2-channel summation mode is enabled to generate a (CH1 +
CH2) / 2 output
2d = Reserved; Don't use
3d = Reserved; Don't use
HPF_SEL[1:0]
High-pass filter (HPF) selection.
0d = Programmable first-order IIR filter for a custom HPF with default
coefficient values in P4_R72 to P4_R83 set as the all-pass filter
1d = HPF with a cutoff of 0.00025 x fS (12 Hz at fS = 48 kHz) is
selected
2d = HPF with a cutoff of 0.002 x fS (96 Hz at fS = 48 kHz) is selected
3d = HPF with a cutoff of 0.008 x fS (384 Hz at fS = 48 kHz) is
selected
8.6.2.47 DSP_CFG1 Register (Address = 0x6C) [Reset = 0x40]
DSP_CFG1 is shown in 表8-98.
Return to the 表8-51.
This register is the digital signal processor (DSP) configuration register 1.
表8-98. DSP_CFG1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
DVOL_GANG
R/W
0b
DVOL control ganged across channels.
0d = Each channel has its own DVOL CTRL settings as programmed
in the CHx_DVOL bits
1d = All active channels must use the channel 1 DVOL setting
(CH1_DVOL) irrespective of whether channel 1 is turned on or not
6-5
BIQUAD_CFG[1:0]
R/W
10b
Number of biquads per channel configuration.
0d = No biquads per channel; biquads are all disabled
1d = 1 biquad per channel
2d = 2 biquads per channel
3d = 3 biquads per channel
4
3
DISABLE_SOFT_STEP
AGC_SEL
R/W
R/W
0b
0b
Soft-stepping disable during DVOL change, mute, and unmute.
0d = Soft-stepping enabled
1d = Soft-stepping disabled
AGC Selection when is enabled for any channel
0d = AGC is not selected
1d = AGC is selected
2
1
0
RESERVED
R/W
R/W
R/W
0b
0b
0b
Reserved bit; Write only reset value
Reserved bit; Write only reset value
RESERVED
EN_AVOID_CLIP
Anti clippler when channel gain > 0 dB and AGC mode enabled.
0d = Channel gain is maintained as per user programmed value
1d = Signal level is compressed to avoid clipping when channel gain
> 0 dB amd signal level crosses programmed threshold setting set in
page-4.
8.6.2.48 AGC_CFG0 Register (Address = 0x70) [Reset = 0xE7]
AGC_CFG0 is shown in 表8-99.
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Return to the 表8-51.
This register is the automatic gain controller (AGC) configuration register 0.
表8-99. AGC_CFG0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
AGC_LVL[3:0]
R/W
1110b
AGC output signal target level.
0d = Output signal target level is -6 dB
1d = Output signal target level is -8 dB
2d = Output signal target level is -10 dB
3d to 13d = Output signal target level is as per configuration
14d = Output signal target level is -34 dB
15d = Output signal target level is -36 dB
3-0
AGC_MAXGAIN[3:0]
R/W
0111b
AGC maximum gain allowed.
0d = Maximum gain allowed is 3 dB
1d = Maximum gain allowed is 6 dB
2d = Maximum gain allowed is 9 dB
3d to 11d = Maximum gain allowed is as per configuration
12d = Maximum gain allowed is 39 dB
13d = Maximum gain allowed is 42 dB
14d to 15d = Reserved; Don't use
8.6.2.49 GAIN_CFG Register (Address = 0x71) [Reset = 0x00]
GAIN_CFG is shown in 表8-100.
Return to the 表8-51.
This register is the channel gain change configuration register.
表8-100. GAIN_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
OTF_GAIN_CHANGE_CF R/W
G[1:0]
00b
On the fly channel gain change configuration
0d = On-the-fly gain change with some artifacts due to applying gain
change immediately
1d = On-the-fly gain change enabled with reduced artifacts but
without soft-stepping
2d = On-the-fly gain change enabled with soft-stepping of 0.5 dB per
~20 µs, supported channel gain up to 30 dB for 10-kΩinput
impedance mode and 24 dB for 20-kΩinput impedance mode
3d = On-the-fly gain change enabled with soft-stepping of 0.5 dB per
~40 µs, supported channel gain up to 30 dB for 10-kΩinput
impedance mode and 24 dB for 20-kΩinput impedance mode
5
RESERVED
RESERVED
R/W
R
0b
Reserved bit; Write only reset value
Reserved bits; Write only reset value
4-0
00000b
8.6.2.50 IN_CH_EN Register (Address = 0x73) [Reset = 0xC0]
IN_CH_EN is shown in 表8-101.
Return to the 表8-51.
This register is the input channel enable configuration register.
表8-101. IN_CH_EN Register Field Descriptions
Bit
Field
Type
Reset
Description
7
IN_CH1_EN
R/W
1b
Input channel 1 enable setting.
0d = Channel 1 is disabled
1d = Channel 1 is enabled
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表8-101. IN_CH_EN Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
6
IN_CH2_EN
IN_CH3_EN
IN_CH4_EN
RESERVED
R/W
1b
Input channel 2 enable setting.
0d = Channel 2 is disabled
1d = Channel 2 is enabled
5
4
R/W
R/W
R
0b
Input channel 3 (PDM only) enable setting.
0d = Channel 3 is disabled
1d = Channel 3 is enabled
0b
Input channel 4 (PDM only) enable setting.
0d = Channel 4 is disabled
1d = Channel 4 is enabled
3-0
0000b
Reserved bits; Write only reset value
8.6.2.51 ASI_OUT_CH_EN Register (Address = 0x74) [Reset = 0x00]
ASI_OUT_CH_EN is shown in 表8-102.
Return to the 表8-51.
This register is the ASI output channel enable configuration register.
表8-102. ASI_OUT_CH_EN Register Field Descriptions
Bit
Field
Type
Reset
Description
7
ASI_OUT_CH1_EN
R/W
0b
ASI output channel 1 enable setting.
0d = Channel 1 output slot is in a tri-state condition
1d = Channel 1 output slot is enabled
6
5
ASI_OUT_CH2_EN
ASI_OUT_CH3_EN
ASI_OUT_CH4_EN
RESERVED
R/W
R/W
R/W
R
0b
ASI output channel 2 enable setting.
0d = Channel 2 output slot is in a tri-state condition
1d = Channel 2 output slot is enabled
0b
ASI output channel 3 enable setting.
0d = Channel 3 output slot is in a tri-state condition
1d = Channel 3 output slot is enabled
4
0b
ASI output channel 4 enable setting.
0d = Channel 4 output slot is in a tri-state condition
1d = Channel 4 output slot is enabled
3-0
0000b
Reserved bits; Write only reset value
8.6.2.52 PWR_CFG Register (Address = 0x75) [Reset = 0x00]
PWR_CFG is shown in 表8-103.
Return to the 表8-51.
This register is the power-up configuration register.
表8-103. PWR_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7
MICBIAS_PDZ
R/W
0b
Power control for MICBIAS.
0d = Power down MICBIAS
1d = Power up MICBIAS
6
5
ADC_PDZ
PLL_PDZ
R/W
R/W
0b
0b
Power control for ADC and PDM channels.
0d = Power down all ADC and PDM channels
1d = Power up all enabled ADC and PDM channels
Power control for the PLL.
0d = Power down the PLL
1d = Power up the PLL
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表8-103. PWR_CFG Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
4
DYN_CH_PUPD_EN
R/W
0b
Dynamic channel power-up, power-down enable.
0d = Channel power-up, power-down is not supported if any channel
recording is on
1d = Channel can be powered up or down individually, even if
channel recording is on
3-2
DYN_MAXCH_SEL[1:0]
R/W
00b
Dynamic mode maximum channel select configuration.
0d = Channel 1 and channel 2 are used with dynamic channel
power-up, power-down feature enabled
1d = Channel 1 to channel 4 are used with dynamic channel power-
up, power-down feature enabled
2d = Reserved; Don't use
3d = Reserved; Don't use
1
0
RESERVED
VAD_EN
R/W
R/W
0b
0b
Reserved bit; Write only reset value
Enable voice activity detection (VAD) algorithm.
0d = VAD is disabled
1d = VAD is enabled
8.6.2.53 DEV_STS0 Register (Address = 0x76) [Reset = 0x00]
DEV_STS0 is shown in 表8-104.
Return to the 表8-51.
This register is the device status value register 0.
表8-104. DEV_STS0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
CH1_STATUS
R
0b
ADC or PDM channel 1 power status.
0d = ADC or PDM channel is powered down
1d = ADC or PDM channel is powered up
6
CH2_STATUS
RESERVED
R
R
0b
ADC or PDM channel 2 power status.
0d = ADC or PDM channel is powered down
1d = ADC or PDM channel is powered up
5-0
000000b
Reserved bits; Write only reset value
8.6.2.54 DEV_STS1 Register (Address = 0x77) [Reset = 0x80]
DEV_STS1 is shown in 表8-105.
Return to the 表8-51.
This register is the device status value register 1.
表8-105. DEV_STS1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-5
MODE_STS[2:0]
R
100b
Device mode status.
4d = Device is in sleep mode or software shutdown mode
6d = Device is in active mode with all ADC or PDM channels turned
off
7d = Device is in active mode with at least one ADC or PDM channel
turned on
4-0
RESERVED
R
00000b
Reserved bits; Write only reset value
8.6.2.55 I2C_CKSUM Register (Address = 0x7E) [Reset = 0x00]
I2C_CKSUM is shown in 表8-106.
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Return to the 表8-51.
This register returns the I2C transactions checksum value.
表8-106. I2C_CKSUM Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
I2C_CKSUM[7:0]
R/W
00000000b These bits return the I2C transactions checksum value. Writing to this
register resets the checksum to the written value. This register is
updated on writes to other registers on all pages.
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8.6.3 Page 1 Registers
表8-107 lists the memory-mapped registers for the Page 1 registers. All register offset addresses not listed in 表
8-107 should be considered as reserved locations and the register contents should not be modified.
表8-107. PAGE 1 Registers
Address
0x0
Acronym
Register Name
Reset Value
0x00
Section
节8.6.3.1
节8.6.3.2
节8.6.3.3
PAGE_CFG
VAD_CFG1
VAD_CFG2
Device page register
0x1E
Voice activity detection configuration register 1
Voice activity detection configuration register 2
0x20
0x1F
0x08
8.6.3.1 PAGE_CFG Register (Address = 0x0) [Reset = 0x00]
PAGE_CFG is shown in 表8-108.
Return to the 表8-107.
The device memory map is divided into pages. This register sets the page.
表8-108. PAGE_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
PAGE[7:0]
R/W
00000000b These bits set the device page.
0d = Page 0
1d = Page 1
2d to 254d = Page 2 to page 254 respectively
255d = Page 255
8.6.3.2 VAD_CFG1 Register (Address = 0x1E) [Reset = 0x20]
VAD_CFG1 is shown in 表8-109.
Return to the 表8-107.
This register is configuration register 1 for voice activity detection.
表8-109. VAD_CFG1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
VAD_MODE[1:0]
R/W
00b
Auto ADC power up / power down configuration selection.
0d = User initiated ADC power-up and ADC power-down
1d = VAD interrupt based ADC power up and ADC power down
2d = VAD interrupt based ADC power up but user initiated ADC
power down
3d = User initiated ADC power-up but VAD interrupt based ADC
power down
5-4
3-2
VAD_CH_SEL[1:0]
VAD_CLK_CFG[1:0]
R/W
R/W
10b
00b
VAD channel select.
0d = Channel 1 is monitored for VAD activity
1d = Channel 2 is monitored for VAD activity
2d = Channel 3 is monitored for VAD activity
3d = Channel 4 is monitored for VAD activity
Clock select for VAD
0d = VAD processing using internal oscillator clock
1d = VAD processing using external clock on BCLK input
2d = VAD processing using external clock on MCLK input
3d = Custom clock configuration based on MST_CFG, CLK_SRC
and CLKGEN_CFG registers in page 0
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表8-109. VAD_CFG1 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
1-0
VAD_EXT_CLK_CFG[1:0] R/W
00b
Clock configuration using external clock for VAD.
0d = External clock is 3.072 MHz
1d = External clock is 6.144 MHz
2d = External clock is 12.288 MHz
3d = External clock is 18.432 MHz
8.6.3.3 VAD_CFG2 Register (Address = 0x1F) [Reset = 0x08]
VAD_CFG2 is shown in 表8-110.
Return to the 表8-107.
This register is configuration register 2 for voice activity detection.
表8-110. VAD_CFG2 Register Field Descriptions
Bit
7
Field
Type
Reset
Description
RESERVED
SDOUT_INT_CFG
R/W
0b
Reserved bit; Write only reset value
6
R/W
0b
SDOUT interrupt configuration.
0d = SDOUT pin is not enabled for interrupt function
1d = SDOUT pin is enabled to support interrupt output when channel
data in not being recorded
5
4
3
RESERVED
R
0b
0b
1b
Reserved bit; Write only reset value
Reserved bit; Write only reset value
RESERVED
R/W
R/W
VAD_PD_DET_EN
Enable ASI output data during VAD activity.
0d = VAD processing is not enabled during ADC recording
1d = VAD processing is enabled during ADC recording and VAD
interrupts are generated as configured
2-0
RESERVED
R
000b
Reserved bits; Write only reset values
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8.6.4 Programmable Coefficient Registers
8.6.4.1 Programmable Coefficient Registers: Page 2
This register page (shown in 表 8-111) consists of the programmable coefficients for the biquad 1 to biquad 6
filters. To optimize the coefficients register transaction time for page 2, page 3, and page 4, the device also
supports (by default) auto-incremented pages for the I2C writes and reads. After a transaction of register address
0x7F, the device auto increments to the next page at register 0x08 to transact the next coefficient value.
表8-111. Page 2 Programmable Coefficient Registers
ADDRESS
0x00
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
ACRONYM
REGISTER NAME
RESET VALUE
0x00
0x7F
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x7F
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x7F
0xFF
PAGE[7:0]
Device page register
BQ1_N0_BYT1[7:0]
BQ1_N0_BYT2[7:0]
BQ1_N0_BYT3[7:0]
BQ1_N0_BYT4[7:0]
BQ1_N1_BYT1[7:0]
BQ1_N1_BYT2[7:0]
BQ1_N1_BYT3[7:0]
BQ1_N1_BYT4[7:0]
BQ1_N2_BYT1[7:0]
BQ1_N2_BYT2[7:0]
BQ1_N2_BYT3[7:0]
BQ1_N2_BYT4[7:0]
BQ1_D1_BYT1[7:0]
BQ1_D1_BYT2[7:0]
BQ1_D1_BYT3[7:0]
BQ1_D1_BYT4[7:0]
BQ1_D2_BYT1[7:0]
BQ1_D2_BYT2[7:0]
BQ1_D2_BYT3[7:0]
BQ1_D2_BYT4[7:0]
BQ2_N0_BYT1[7:0]
BQ2_N0_BYT2[7:0]
BQ2_N0_BYT3[7:0]
BQ2_N0_BYT4[7:0]
BQ2_N1_BYT1[7:0]
BQ2_N1_BYT2[7:0]
BQ2_N1_BYT3[7:0]
BQ2_N1_BYT4[7:0]
BQ2_N2_BYT1[7:0]
BQ2_N2_BYT2[7:0]
BQ2_N2_BYT3[7:0]
BQ2_N2_BYT4[7:0]
BQ2_D1_BYT1[7:0]
BQ2_D1_BYT2[7:0]
BQ2_D1_BYT3[7:0]
BQ2_D1_BYT4[7:0]
BQ2_D2_BYT1[7:0]
BQ2_D2_BYT2[7:0]
BQ2_D2_BYT3[7:0]
BQ2_D2_BYT4[7:0]
BQ3_N0_BYT1[7:0]
BQ3_N0_BYT2[7:0]
Programmable biquad 1, N0 coefficient byte[31:24]
Programmable biquad 1, N0 coefficient byte[23:16]
Programmable biquad 1, N0 coefficient byte[15:8]
Programmable biquad 1, N0 coefficient byte[7:0]
Programmable biquad 1, N1 coefficient byte[31:24]
Programmable biquad 1, N1 coefficient byte[23:16]
Programmable biquad 1, N1 coefficient byte[15:8]
Programmable biquad 1, N1 coefficient byte[7:0]
Programmable biquad 1, N2 coefficient byte[31:24]
Programmable biquad 1, N2 coefficient byte[23:16]
Programmable biquad 1, N2 coefficient byte[15:8]
Programmable biquad 1, N2 coefficient byte[7:0]
Programmable biquad 1, D1 coefficient byte[31:24]
Programmable biquad 1, D1 coefficient byte[23:16]
Programmable biquad 1, D1 coefficient byte[15:8]
Programmable biquad 1, D1 coefficient byte[7:0]
Programmable biquad 1, D2 coefficient byte[31:24]
Programmable biquad 1, D2 coefficient byte[23:16]
Programmable biquad 1, D2 coefficient byte[15:8]
Programmable biquad 1, D2 coefficient byte[7:0]
Programmable biquad 2, N0 coefficient byte[31:24]
Programmable biquad 2, N0 coefficient byte[23:16]
Programmable biquad 2, N0 coefficient byte[15:8]
Programmable biquad 2, N0 coefficient byte[7:0]
Programmable biquad 2, N1 coefficient byte[31:24]
Programmable biquad 2, N1 coefficient byte[23:16]
Programmable biquad 2, N1 coefficient byte[15:8]
Programmable biquad 2, N1 coefficient byte[7:0]
Programmable biquad 2, N2 coefficient byte[31:24]
Programmable biquad 2, N2 coefficient byte[23:16]
Programmable biquad 2, N2 coefficient byte[15:8]
Programmable biquad 2, N2 coefficient byte[7:0]
Programmable biquad 2, D1 coefficient byte[31:24]
Programmable biquad 2, D1 coefficient byte[23:16]
Programmable biquad 2, D1 coefficient byte[15:8]
Programmable biquad 2, D1 coefficient byte[7:0]
Programmable biquad 2, D2 coefficient byte[31:24]
Programmable biquad 2, D2 coefficient byte[23:16]
Programmable biquad 2, D2 coefficient byte[15:8]
Programmable biquad 2, D2 coefficient byte[7:0]
Programmable biquad 3, N0 coefficient byte[31:24]
Programmable biquad 3, N0 coefficient byte[23:16]
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表8-111. Page 2 Programmable Coefficient Registers (continued)
ADDRESS
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B
0x5C
0x5D
0x5E
0x5F
0x60
0x61
0x62
0x63
ACRONYM
REGISTER NAME
RESET VALUE
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x7F
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x7F
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
BQ3_N0_BYT3[7:0]
Programmable biquad 3, N0 coefficient byte[15:8]
Programmable biquad 3, N0 coefficient byte[7:0]
Programmable biquad 3, N1 coefficient byte[31:24]
Programmable biquad 3, N1 coefficient byte[23:16]
Programmable biquad 3, N1 coefficient byte[15:8]
Programmable biquad 3, N1 coefficient byte[7:0]
Programmable biquad 3, N2 coefficient byte[31:24]
Programmable biquad 3, N2 coefficient byte[23:16]
Programmable biquad 3, N2 coefficient byte[15:8]
Programmable biquad 3, N2 coefficient byte[7:0]
Programmable biquad 3, D1 coefficient byte[31:24]
Programmable biquad 3, D1 coefficient byte[23:16]
Programmable biquad 3, D1 coefficient byte[15:8]
Programmable biquad 3, D1 coefficient byte[7:0]
Programmable biquad 3, D2 coefficient byte[31:24]
Programmable biquad 3, D2 coefficient byte[23:16]
Programmable biquad 3, D2 coefficient byte[15:8]
Programmable biquad 3, D2 coefficient byte[7:0]
Programmable biquad 4, N0 coefficient byte[31:24]
Programmable biquad 4, N0 coefficient byte[23:16]
Programmable biquad 4, N0 coefficient byte[15:8]
Programmable biquad 4, N0 coefficient byte[7:0]
Programmable biquad 4, N1 coefficient byte[31:24]
Programmable biquad 4, N1 coefficient byte[23:16]
Programmable biquad 4, N1 coefficient byte[15:8]
Programmable biquad 4, N1 coefficient byte[7:0]
Programmable biquad 4, N2 coefficient byte[31:24]
Programmable biquad 4, N2 coefficient byte[23:16]
Programmable biquad 4, N2 coefficient byte[15:8]
Programmable biquad 4, N2 coefficient byte[7:0]
Programmable biquad 4, D1 coefficient byte[31:24]
Programmable biquad 4, D1 coefficient byte[23:16]
Programmable biquad 4, D1 coefficient byte[15:8]
Programmable biquad 4, D1 coefficient byte[7:0]
Programmable biquad 4, D2 coefficient byte[31:24]
Programmable biquad 4, D2 coefficient byte[23:16]
Programmable biquad 4, D2 coefficient byte[15:8]
Programmable biquad 4, D2 coefficient byte[7:0]
Programmable biquad 5, N0 coefficient byte[31:24]
Programmable biquad 5, N0 coefficient byte[23:16]
Programmable biquad 5, N0 coefficient byte[15:8]
Programmable biquad 5, N0 coefficient byte[7:0]
Programmable biquad 5, N1 coefficient byte[31:24]
Programmable biquad 5, N1 coefficient byte[23:16]
Programmable biquad 5, N1 coefficient byte[15:8]
Programmable biquad 5, N1 coefficient byte[7:0]
Programmable biquad 5, N2 coefficient byte[31:24]
Programmable biquad 5, N2 coefficient byte[23:16]
Programmable biquad 5, N2 coefficient byte[15:8]
Programmable biquad 5, N2 coefficient byte[7:0]
BQ3_N0_BYT4[7:0]
BQ3_N1_BYT1[7:0]
BQ3_N1_BYT2[7:0]
BQ3_N1_BYT3[7:0]
BQ3_N1_BYT4[7:0]
BQ3_N2_BYT1[7:0]
BQ3_N2_BYT2[7:0]
BQ3_N2_BYT3[7:0]
BQ3_N2_BYT4[7:0]
BQ3_D1_BYT1[7:0]
BQ3_D1_BYT2[7:0]
BQ3_D1_BYT3[7:0]
BQ3_D1_BYT4[7:0]
BQ3_D2_BYT1[7:0]
BQ3_D2_BYT2[7:0]
BQ3_D2_BYT3[7:0]
BQ3_D2_BYT4[7:0]
BQ4_N0_BYT1[7:0]
BQ4_N0_BYT2[7:0]
BQ4_N0_BYT3[7:0]
BQ4_N0_BYT4[7:0]
BQ4_N1_BYT1[7:0]
BQ4_N1_BYT2[7:0]
BQ4_N1_BYT3[7:0]
BQ4_N1_BYT4[7:0]
BQ4_N2_BYT1[7:0]
BQ4_N2_BYT2[7:0]
BQ4_N2_BYT3[7:0]
BQ4_N2_BYT4[7:0]
BQ4_D1_BYT1[7:0]
BQ4_D1_BYT2[7:0]
BQ4_D1_BYT3[7:0]
BQ4_D1_BYT4[7:0]
BQ4_D2_BYT1[7:0]
BQ4_D2_BYT2[7:0]
BQ4_D2_BYT3[7:0]
BQ4_D2_BYT4[7:0]
BQ5_N0_BYT1[7:0]
BQ5_N0_BYT2[7:0]
BQ5_N0_BYT3[7:0]
BQ5_N0_BYT4[7:0]
BQ5_N1_BYT1[7:0]
BQ5_N1_BYT2[7:0]
BQ5_N1_BYT3[7:0]
BQ5_N1_BYT4[7:0]
BQ5_N2_BYT1[7:0]
BQ5_N2_BYT2[7:0]
BQ5_N2_BYT3[7:0]
BQ5_N2_BYT4[7:0]
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表8-111. Page 2 Programmable Coefficient Registers (continued)
ADDRESS
0x64
0x65
0x66
0x67
0x68
0x69
0x6A
0x6B
0x6C
0x6D
0x6E
0x6F
0x70
0x71
0x72
0x73
0x74
0x75
0x76
0x77
0x78
0x79
0x7A
0x7B
0x7C
0x7D
0x7E
0x7F
ACRONYM
REGISTER NAME
RESET VALUE
BQ5_D1_BYT1[7:0]
Programmable biquad 5, D1 coefficient byte[31:24]
Programmable biquad 5, D1 coefficient byte[23:16]
Programmable biquad 5, D1 coefficient byte[15:8]
Programmable biquad 5, D1 coefficient byte[7:0]
Programmable biquad 5, D2 coefficient byte[31:24]
Programmable biquad 5, D2 coefficient byte[23:16]
Programmable biquad 5, D2 coefficient byte[15:8]
Programmable biquad 5, D2 coefficient byte[7:0]
Programmable biquad 6, N0 coefficient byte[31:24]
Programmable biquad 6, N0 coefficient byte[23:16]
Programmable biquad 6, N0 coefficient byte[15:8]
Programmable biquad 6, N0 coefficient byte[7:0]
Programmable biquad 6, N1 coefficient byte[31:24]
Programmable biquad 6, N1 coefficient byte[23:16]
Programmable biquad 6, N1 coefficient byte[15:8]
Programmable biquad 6, N1 coefficient byte[7:0]
Programmable biquad 6, N2 coefficient byte[31:24]
Programmable biquad 6, N2 coefficient byte[23:16]
Programmable biquad 6, N2 coefficient byte[15:8]
Programmable biquad 6, N2 coefficient byte[7:0]
Programmable biquad 6, D1 coefficient byte[31:24]
Programmable biquad 6, D1 coefficient byte[23:16]
Programmable biquad 6, D1 coefficient byte[15:8]
Programmable biquad 6, D1 coefficient byte[7:0]
Programmable biquad 6, D2 coefficient byte[31:24]
Programmable biquad 6, D2 coefficient byte[23:16]
Programmable biquad 6, D2 coefficient byte[15:8]
Programmable biquad 6, D2 coefficient byte[7:0]
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x7F
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
BQ5_D1_BYT2[7:0]
BQ5_D1_BYT3[7:0]
BQ5_D1_BYT4[7:0]
BQ5_D2_BYT1[7:0]
BQ5_D2_BYT2[7:0]
BQ5_D2_BYT3[7:0]
BQ5_D2_BYT4[7:0]
BQ6_N0_BYT1[7:0]
BQ6_N0_BYT2[7:0]
BQ6_N0_BYT3[7:0]
BQ6_N0_BYT4[7:0]
BQ6_N1_BYT1[7:0]
BQ6_N1_BYT2[7:0]
BQ6_N1_BYT3[7:0]
BQ6_N1_BYT4[7:0]
BQ6_N2_BYT1[7:0]
BQ6_N2_BYT2[7:0]
BQ6_N2_BYT3[7:0]
BQ6_N2_BYT4[7:0]
BQ6_D1_BYT1[7:0]
BQ6_D1_BYT2[7:0]
BQ6_D1_BYT3[7:0]
BQ6_D1_BYT4[7:0]
BQ6_D2_BYT1[7:0]
BQ6_D2_BYT2[7:0]
BQ6_D2_BYT3[7:0]
BQ6_D2_BYT4[7:0]
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8.6.4.2 Programmable Coefficient Registers: Page 3
This register page (shown in 表 8-112) consists of the programmable coefficients for the biquad 7 to biquad 12
filters. To optimize the coefficients register transaction time for page 2, page 3, and page 4, the device also
supports (by default) auto-incremented pages for the I2C writes and reads. After a transaction of register address
0x7F, the device auto increments to the next page at register 0x08 to transact the next coefficient value.
表8-112. Page 3 Programmable Coefficient Registers
ADDRESS
0x00
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
ACRONYM
REGISTER NAME
RESET VALUE
0x00
0x7F
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x7F
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x7F
0xFF
0xFF
PAGE[7:0]
Device page register
BQ7_N0_BYT1[7:0]
BQ7_N0_BYT2[7:0]
BQ7_N0_BYT3[7:0]
BQ7_N0_BYT4[7:0]
BQ7_N1_BYT1[7:0]
BQ7_N1_BYT2[7:0]
BQ7_N1_BYT3[7:0]
BQ7_N1_BYT4[7:0]
BQ7_N2_BYT1[7:0]
BQ7_N2_BYT2[7:0]
BQ7_N2_BYT3[7:0]
BQ7_N2_BYT4[7:0]
BQ7_D1_BYT1[7:0]
BQ7_D1_BYT2[7:0]
BQ7_D1_BYT3[7:0]
BQ7_D1_BYT4[7:0]
BQ7_D2_BYT1[7:0]
BQ7_D2_BYT2[7:0]
BQ7_D2_BYT3[7:0]
BQ7_D2_BYT4[7:0]
BQ8_N0_BYT1[7:0]
BQ8_N0_BYT2[7:0]
BQ8_N0_BYT3[7:0]
BQ8_N0_BYT4[7:0]
BQ8_N1_BYT1[7:0]
BQ8_N1_BYT2[7:0]
BQ8_N1_BYT3[7:0]
BQ8_N1_BYT4[7:0]
BQ8_N2_BYT1[7:0]
BQ8_N2_BYT2[7:0]
BQ8_N2_BYT3[7:0]
BQ8_N2_BYT4[7:0]
BQ8_D1_BYT1[7:0]
BQ8_D1_BYT2[7:0]
BQ8_D1_BYT3[7:0]
BQ8_D1_BYT4[7:0]
BQ8_D2_BYT1[7:0]
BQ8_D2_BYT2[7:0]
BQ8_D2_BYT3[7:0]
BQ8_D2_BYT4[7:0]
BQ9_N0_BYT1[7:0]
BQ9_N0_BYT2[7:0]
BQ9_N0_BYT3[7:0]
Programmable biquad 7, N0 coefficient byte[31:24]
Programmable biquad 7, N0 coefficient byte[23:16]
Programmable biquad 7, N0 coefficient byte[15:8]
Programmable biquad 7, N0 coefficient byte[7:0]
Programmable biquad 7, N1 coefficient byte[31:24]
Programmable biquad 7, N1 coefficient byte[23:16]
Programmable biquad 7, N1 coefficient byte[15:8]
Programmable biquad 7, N1 coefficient byte[7:0]
Programmable biquad 7, N2 coefficient byte[31:24]
Programmable biquad 7, N2 coefficient byte[23:16]
Programmable biquad 7, N2 coefficient byte[15:8]
Programmable biquad 7, N2 coefficient byte[7:0]
Programmable biquad 7, D1 coefficient byte[31:24]
Programmable biquad 7, D1 coefficient byte[23:16]
Programmable biquad 7, D1 coefficient byte[15:8]
Programmable biquad 7, D1 coefficient byte[7:0]
Programmable biquad 7, D2 coefficient byte[31:24]
Programmable biquad 7, D2 coefficient byte[23:16]
Programmable biquad 7, D2 coefficient byte[15:8]
Programmable biquad 7, D2 coefficient byte[7:0]
Programmable biquad 8, N0 coefficient byte[31:24]
Programmable biquad 8, N0 coefficient byte[23:16]
Programmable biquad 8, N0 coefficient byte[15:8]
Programmable biquad 8, N0 coefficient byte[7:0]
Programmable biquad 8, N1 coefficient byte[31:24]
Programmable biquad 8, N1 coefficient byte[23:16]
Programmable biquad 8, N1 coefficient byte[15:8]
Programmable biquad 8, N1 coefficient byte[7:0]
Programmable biquad 8, N2 coefficient byte[31:24]
Programmable biquad 8, N2 coefficient byte[23:16]
Programmable biquad 8, N2 coefficient byte[15:8]
Programmable biquad 8, N2 coefficient byte[7:0]
Programmable biquad 8, D1 coefficient byte[31:24]
Programmable biquad 8, D1 coefficient byte[23:16]
Programmable biquad 8, D1 coefficient byte[15:8]
Programmable biquad 8, D1 coefficient byte[7:0]
Programmable biquad 8, D2 coefficient byte[31:24]
Programmable biquad 8, D2 coefficient byte[23:16]
Programmable biquad 8, D2 coefficient byte[15:8]
Programmable biquad 8, D2 coefficient byte[7:0]
Programmable biquad 9, N0 coefficient byte[31:24]
Programmable biquad 9, N0 coefficient byte[23:16]
Programmable biquad 9, N0 coefficient byte[15:8]
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表8-112. Page 3 Programmable Coefficient Registers (continued)
ADDRESS
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B
0x5C
0x5D
0x5E
0x5F
0x60
0x61
0x62
0x63
0x64
ACRONYM
REGISTER NAME
RESET VALUE
BQ9_N0_BYT4[7:0]
Programmable biquad 9, N0 coefficient byte[7:0]
Programmable biquad 9, N1 coefficient byte[31:24]
Programmable biquad 9, N1 coefficient byte[23:16]
Programmable biquad 9, N1 coefficient byte[15:8]
Programmable biquad 9, N1 coefficient byte[7:0]
Programmable biquad 9, N2 coefficient byte[31:24]
Programmable biquad 9, N2 coefficient byte[23:16]
Programmable biquad 9, N2 coefficient byte[15:8]
Programmable biquad 9, N2 coefficient byte[7:0]
Programmable biquad 9, D1 coefficient byte[31:24]
Programmable biquad 9, D1 coefficient byte[23:16]
Programmable biquad 9, D1 coefficient byte[15:8]
Programmable biquad 9, D1 coefficient byte[7:0]
Programmable biquad 9, D2 coefficient byte[31:24]
Programmable biquad 9, D2 coefficient byte[23:16]
Programmable biquad 9, D2 coefficient byte[15:8]
Programmable biquad 9, D2 coefficient byte[7:0]
Programmable biquad 10, N0 coefficient byte[31:24]
Programmable biquad 10, N0 coefficient byte[23:16]
Programmable biquad 10, N0 coefficient byte[15:8]
Programmable biquad 10, N0 coefficient byte[7:0]
Programmable biquad 10, N1 coefficient byte[31:24]
Programmable biquad 10, N1 coefficient byte[23:16]
Programmable biquad 10, N1 coefficient byte[15:8]
Programmable biquad 10, N1 coefficient byte[7:0]
Programmable biquad 10, N2 coefficient byte[31:24]
Programmable biquad 10, N2 coefficient byte[23:16]
Programmable biquad 10, N2 coefficient byte[15:8]
Programmable biquad 10, N2 coefficient byte[7:0]
Programmable biquad 10, D1 coefficient byte[31:24]
Programmable biquad 10, D1 coefficient byte[23:16]
Programmable biquad 10, D1 coefficient byte[15:8]
Programmable biquad 10, D1 coefficient byte[7:0]
Programmable biquad 10, D2 coefficient byte[31:24]
Programmable biquad 10, D2 coefficient byte[23:16]
Programmable biquad 10, D2 coefficient byte[15:8]
Programmable biquad 10, D2 coefficient byte[7:0]
Programmable biquad 11, N0 coefficient byte[31:24]
Programmable biquad 11, N0 coefficient byte[23:16]
Programmable biquad 11, N0 coefficient byte[15:8]
Programmable biquad 11, N0 coefficient byte[7:0]
Programmable biquad 11, N1 coefficient byte[31:24]
Programmable biquad 11, N1 coefficient byte[23:16]
Programmable biquad 11, N1 coefficient byte[15:8]
Programmable biquad 11, N1 coefficient byte[7:0]
Programmable biquad 11, N2 coefficient byte[31:24]
Programmable biquad 11, N2 coefficient byte[23:16]
Programmable biquad 11, N2 coefficient byte[15:8]
Programmable biquad 11, N2 coefficient byte[7:0]
Programmable biquad 11, D1 coefficient byte[31:24]
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x7F
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x7F
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
BQ9_N1_BYT1[7:0]
BQ9_N1_BYT2[7:0]
BQ9_N1_BYT3[7:0]
BQ9_N1_BYT4[7:0]
BQ9_N2_BYT1[7:0]
BQ9_N2_BYT2[7:0]
BQ9_N2_BYT3[7:0]
BQ9_N2_BYT4[7:0]
BQ9_D1_BYT1[7:0]
BQ9_D1_BYT2[7:0]
BQ9_D1_BYT3[7:0]
BQ9_D1_BYT4[7:0]
BQ9_D2_BYT1[7:0]
BQ9_D2_BYT2[7:0]
BQ9_D2_BYT3[7:0]
BQ9_D2_BYT4[7:0]
BQ10_N0_BYT1[7:0]
BQ10_N0_BYT2[7:0]
BQ10_N0_BYT3[7:0]
BQ10_N0_BYT4[7:0]
BQ10_N1_BYT1[7:0]
BQ10_N1_BYT2[7:0]
BQ10_N1_BYT3[7:0]
BQ10_N1_BYT4[7:0]
BQ10_N2_BYT1[7:0]
BQ10_N2_BYT2[7:0]
BQ10_N2_BYT3[7:0]
BQ10_N2_BYT4[7:0]
BQ10_D1_BYT1[7:0]
BQ10_D1_BYT2[7:0]
BQ10_D1_BYT3[7:0]
BQ10_D1_BYT4[7:0]
BQ10_D2_BYT1[7:0]
BQ10_D2_BYT2[7:0]
BQ10_D2_BYT3[7:0]
BQ10_D2_BYT4[7:0]
BQ11_N0_BYT1[7:0]
BQ11_N0_BYT2[7:0]
BQ11_N0_BYT3[7:0]
BQ11_N0_BYT4[7:0]
BQ11_N1_BYT1[7:0]
BQ11_N1_BYT2[7:0]
BQ11_N1_BYT3[7:0]
BQ11_N1_BYT4[7:0]
BQ11_N2_BYT1[7:0]
BQ11_N2_BYT2[7:0]
BQ11_N2_BYT3[7:0]
BQ11_N2_BYT4[7:0]
BQ11_D1_BYT1[7:0]
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表8-112. Page 3 Programmable Coefficient Registers (continued)
ADDRESS
0x65
0x66
0x67
0x68
0x69
0x6A
0x6B
0x6C
0x6D
0x6E
0x6F
0x70
0x71
0x72
0x73
0x74
0x75
0x76
0x77
0x78
0x79
0x7A
0x7B
0x7C
0x7D
0x7E
0x7F
ACRONYM
REGISTER NAME
RESET VALUE
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x7F
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
BQ11_D1_BYT2[7:0]
Programmable biquad 11, D1 coefficient byte[23:16]
Programmable biquad 11, D1 coefficient byte[15:8]
Programmable biquad 11, D1 coefficient byte[7:0]
Programmable biquad 11, D2 coefficient byte[31:24]
Programmable biquad 11, D2 coefficient byte[23:16]
Programmable biquad 11, D2 coefficient byte[15:8]
Programmable biquad 11, D2 coefficient byte[7:0]
Programmable biquad 12, N0 coefficient byte[31:24]
Programmable biquad 12, N0 coefficient byte[23:16]
Programmable biquad 12, N0 coefficient byte[15:8]
Programmable biquad 12, N0 coefficient byte[7:0]
Programmable biquad 12, N1 coefficient byte[31:24]
Programmable biquad 12, N1 coefficient byte[23:16]
Programmable biquad 12, N1 coefficient byte[15:8]
Programmable biquad 12, N1 coefficient byte[7:0]
Programmable biquad 12, N2 coefficient byte[31:24]
Programmable biquad 12, N2 coefficient byte[23:16]
Programmable biquad 12, N2 coefficient byte[15:8]
Programmable biquad 12, N2 coefficient byte[7:0]
Programmable biquad 12, D1 coefficient byte[31:24]
Programmable biquad 12, D1 coefficient byte[23:16]
Programmable biquad 12, D1 coefficient byte[15:8]
Programmable biquad 12, D1 coefficient byte[7:0]
Programmable biquad 12, D2 coefficient byte[31:24]
Programmable biquad 12, D2 coefficient byte[23:16]
Programmable biquad 12, D2 coefficient byte[15:8]
Programmable biquad 12, D2 coefficient byte[7:0]
BQ11_D1_BYT3[7:0]
BQ11_D1_BYT4[7:0]
BQ11_D2_BYT1[7:0]
BQ11_D2_BYT2[7:0]
BQ11_D2_BYT3[7:0]
BQ11_D2_BYT4[7:0]
BQ12_N0_BYT1[7:0]
BQ12_N0_BYT2[7:0]
BQ12_N0_BYT3[7:0]
BQ12_N0_BYT4[7:0]
BQ12_N1_BYT1[7:0]
BQ12_N1_BYT2[7:0]
BQ12_N1_BYT3[7:0]
BQ12_N1_BYT4[7:0]
BQ12_N2_BYT1[7:0]
BQ12_N2_BYT2[7:0]
BQ12_N2_BYT3[7:0]
BQ12_N2_BYT4[7:0]
BQ12_D1_BYT1[7:0]
BQ12_D1_BYT2[7:0]
BQ12_D1_BYT3[7:0]
BQ12_D1_BYT4[7:0]
BQ12_D2_BYT1[7:0]
BQ12_D2_BYT2[7:0]
BQ12_D2_BYT3[7:0]
BQ12_D2_BYT4[7:0]
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8.6.4.3 Programmable Coefficient Registers: Page 4
This register page (shown in 表 8-113) consists of the programmable coefficients for mixer 1 to mixer 4 and the
first-order IIR filter.
表8-113. Page 4 Programmable Coefficient Registers
ADDRESS
0x00
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
ACRONYM
REGISTER NAME
RESET VALUE
0x00
0x7F
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x7F
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x7F
0xFF
0xFF
0xFF
0x00
PAGE[7:0]
Device page register
MIX1_CH1_BYT1[7:0]
MIX1_CH1_BYT2[7:0]
MIX1_CH1_BYT3[7:0]
MIX1_CH1_BYT4[7:0]
MIX1_CH2_BYT1[7:0]
MIX1_CH2_BYT2[7:0]
MIX1_CH2_BYT3[7:0]
MIX1_CH2_BYT4[7:0]
MIX1_CH3_BYT1[7:0]
MIX1_CH3_BYT2[7:0]
MIX1_CH3_BYT3[7:0]
MIX1_CH3_BYT4[7:0]
MIX1_CH4_BYT1[7:0]
MIX1_CH4_BYT2[7:0]
MIX1_CH4_BYT3[7:0]
MIX1_CH4_BYT4[7:0]
MIX2_CH1_BYT1[7:0]
MIX2_CH1_BYT2[7:0]
MIX2_CH1_BYT3[7:0]
MIX2_CH1_BYT4[7:0]
MIX2_CH2_BYT1[7:0]
MIX2_CH2_BYT2[7:0]
MIX2_CH2_BYT3[7:0]
MIX2_CH2_BYT4[7:0]
MIX2_CH3_BYT1[7:0]
MIX2_CH3_BYT2[7:0]
MIX2_CH3_BYT3[7:0]
MIX2_CH3_BYT4[7:0]
MIX2_CH4_BYT1[7:0]
MIX2_CH4_BYT2[7:0]
MIX2_CH4_BYT3[7:0]
MIX2_CH4_BYT4[7:0]
MIX3_CH1_BYT1[7:0]
MIX3_CH1_BYT2[7:0]
MIX3_CH1_BYT3[7:0]
MIX3_CH1_BYT4[7:0]
MIX3_CH2_BYT1[7:0]
MIX3_CH2_BYT2[7:0]
MIX3_CH2_BYT3[7:0]
MIX3_CH2_BYT4[7:0]
MIX3_CH3_BYT1[7:0]
MIX3_CH3_BYT2[7:0]
MIX3_CH3_BYT3[7:0]
MIX3_CH3_BYT4[7:0]
MIX3_CH4_BYT1[7:0]
Digital mixer 1, channel 1 coefficient byte[31:24]
Digital mixer 1, channel 1 coefficient byte[23:16]
Digital mixer 1, channel 1 coefficient byte[15:8]
Digital mixer 1, channel 1 coefficient byte[7:0]
Digital mixer 1, channel 2 coefficient byte[31:24]
Digital mixer 1, channel 2 coefficient byte[23:16]
Digital mixer 1, channel 2 coefficient byte[15:8]
Digital mixer 1, channel 2 coefficient byte[7:0]
Digital mixer 1, channel 3 coefficient byte[31:24]
Digital mixer 1, channel 3 coefficient byte[23:16]
Digital mixer 1, channel 3 coefficient byte[15:8]
Digital mixer 1, channel 3 coefficient byte[7:0]
Digital mixer 1, channel 4 coefficient byte[31:24]
Digital mixer 1, channel 4 coefficient byte[23:16]
Digital mixer 1, channel 4 coefficient byte[15:8]
Digital mixer 1, channel 4 coefficient byte[7:0]
Digital mixer 2, channel 1 coefficient byte[31:24]
Digital mixer 2, channel 1 coefficient byte[23:16]
Digital mixer 2, channel 1 coefficient byte[15:8]
Digital mixer 2, channel 1 coefficient byte[7:0]
Digital mixer 2, channel 2 coefficient byte[31:24]
Digital mixer 2, channel 2 coefficient byte[23:16]
Digital mixer 2, channel 2 coefficient byte[15:8]
Digital mixer 2, channel 2 coefficient byte[7:0]
Digital mixer 2, channel 3 coefficient byte[31:24]
Digital mixer 2, channel 3 coefficient byte[23:16]
Digital mixer 2, channel 3 coefficient byte[15:8]
Digital mixer 2, channel 3 coefficient byte[7:0]
Digital mixer 2, channel 4 coefficient byte[31:24]
Digital mixer 2, channel 4 coefficient byte[23:16]
Digital mixer 2, channel 4 coefficient byte[15:8]
Digital mixer 2, channel 4 coefficient byte[7:0]
Digital mixer 3, channel 1 coefficient byte[31:24]
Digital mixer 3, channel 1 coefficient byte[23:16]
Digital mixer 3, channel 1 coefficient byte[15:8]
Digital mixer 3, channel 1 coefficient byte[7:0]
Digital mixer 3, channel 2 coefficient byte[31:24]
Digital mixer 3, channel 2 coefficient byte[23:16]
Digital mixer 3, channel 2 coefficient byte[15:8]
Digital mixer 3, channel 2 coefficient byte[7:0]
Digital mixer 3, channel 3 coefficient byte[31:24]
Digital mixer 3, channel 3 coefficient byte[23:16]
Digital mixer 3, channel 3 coefficient byte[15:8]
Digital mixer 3, channel 3 coefficient byte[7:0]
Digital mixer 3, channel 4 coefficient byte[31:24]
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表8-113. Page 4 Programmable Coefficient Registers (continued)
ADDRESS
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
ACRONYM
MIX3_CH4_BYT2[7:0]
MIX3_CH4_BYT3[7:0]
MIX3_CH4_BYT4[7:0]
MIX4_CH1_BYT1[7:0]
MIX4_CH1_BYT2[7:0]
MIX4_CH1_BYT3[7:0]
MIX4_CH1_BYT4[7:0]
MIX4_CH2_BYT1[7:0]
MIX4_CH2_BYT2[7:0]
MIX4_CH2_BYT3[7:0]
MIX4_CH2_BYT4[7:0]
MIX4_CH3_BYT1[7:0]
MIX4_CH3_BYT2[7:0]
MIX4_CH3_BYT3[7:0]
MIX4_CH3_BYT4[7:0]
MIX4_CH4_BYT1[7:0]
MIX4_CH4_BYT2[7:0]
MIX4_CH4_BYT3[7:0]
MIX4_CH4_BYT4[7:0]
IIR_N0_BYT1[7:0]
REGISTER NAME
RESET VALUE
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x7F
0xFF
0xFF
0xFF
0x7F
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Digital mixer 3, channel 4 coefficient byte[23:16]
Digital mixer 3, channel 4 coefficient byte[15:8]
Digital mixer 3, channel 4 coefficient byte[7:0]
Digital mixer 4, channel 1 coefficient byte[31:24]
Digital mixer 4, channel 1 coefficient byte[23:16]
Digital mixer 4, channel 1 coefficient byte[15:8]
Digital mixer 4, channel 1 coefficient byte[7:0]
Digital mixer 4, channel 2 coefficient byte[31:24]
Digital mixer 4, channel 2 coefficient byte[23:16]
Digital mixer 4, channel 2 coefficient byte[15:8]
Digital mixer 4, channel 2 coefficient byte[7:0]
Digital mixer 4, channel 3 coefficient byte[31:24]
Digital mixer 4, channel 3 coefficient byte[23:16]
Digital mixer 4, channel 3 coefficient byte[15:8]
Digital mixer 4, channel 3 coefficient byte[7:0]
Digital mixer 4, channel 4 coefficient byte[31:24]
Digital mixer 4, channel 4 coefficient byte[23:16]
Digital mixer 4, channel 4 coefficient byte[15:8]
Digital mixer 4, channel 4 coefficient byte[7:0]
Programmable first-order IIR, N0 coefficient byte[31:24]
Programmable first-order IIR, N0 coefficient byte[23:16]
Programmable first-order IIR, N0 coefficient byte[15:8]
Programmable first-order IIR, N0 coefficient byte[7:0]
Programmable first-order IIR, N1 coefficient byte[31:24]
Programmable first-order IIR, N1 coefficient byte[23:16]
Programmable first-order IIR, N1 coefficient byte[15:8]
Programmable first-order IIR, N1 coefficient byte[7:0]
Programmable first-order IIR, D1 coefficient byte[31:24]
Programmable first-order IIR, D1 coefficient byte[23:16]
Programmable first-order IIR, D1 coefficient byte[15:8]
Programmable first-order IIR, D1 coefficient byte[7:0]
IIR_N0_BYT2[7:0]
IIR_N0_BYT3[7:0]
IIR_N0_BYT4[7:0]
IIR_N1_BYT1[7:0]
IIR_N1_BYT2[7:0]
IIR_N1_BYT3[7:0]
IIR_N1_BYT4[7:0]
IIR_D1_BYT1[7:0]
IIR_D1_BYT2[7:0]
IIR_D1_BYT3[7:0]
IIR_D1_BYT4[7:0]
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
The PCM3120-Q1 is a multichannel, high-performance audio analog-to-digital converter (ADC) that supports
output sample rates of up to 768 kHz. The device supports either up to two analog microphones or up to four
digital pulse density modulation (PDM) microphones for simultaneous recording applications.
Communication to the PCM3120-Q1 for configuration of the control registers is supported using an I2C interface.
The device supports a highly flexible, audio serial interface (TDM, I2S, and LJ) to transmit audio data seamlessly
in the system across devices.
9.2 Typical Applications
9.2.1 Two-Channel Analog Microphone Recording
图 9-1 shows a typical configuration of the PCM3120-Q1 for an application using two analog microelectrical-
mechanical system (MEMS) microphones for simultaneous recording operation with an I2C control interface and
a time-division multiplexing (TDM) audio data slave interface. For best distortion performance, use input AC-
coupling capacitors with a low-voltage coefficient.
10 μF
1 μF
3.3 V
(3.0 V to 3.6 V)
1 μF
1 μF
0.1 μF
0.1 μF
10 μF
1 μF
1 μF
DREG
VDD
OUTP
INP1
0.1 μF
AMIC1
OUTM
VSS
INM1
3.3 V
(3.0 V to 3.6 V)
OR
1.8 V
(1.65 V to 1.95 V)
10 μF
VDD
OUTP
INP2_GPI1 (INP2)
AMIC2
OUTM
VSS
INM2_GPO1 (INM2)
0.1 μF
IOVDD
1 μF
PCMx120-Q1
0.1 μF
Thermal Pad
(VSS)
R Ω
R Ω
Host Processor
图9-1. Two-Channel Analog Microphone Recording Diagram
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9.2.1.1 Design Requirements
表9-1 lists the design parameters for this application.
表9-1. Design Parameters
KEY PARAMETER
SPECIFICATION
AVDD
3.3 V
AVDD supply current consumption
IOVDD
>14 mA (PLL on, two-channel recording, fS = 48 kHz)
1.8 V or 3.3 V
Maximum MICBIAS current
5 mA (MICBIAS voltage is the same as AVDD)
9.2.1.2 Detailed Design Procedure
This section describes the necessary steps to configure the PCM3120-Q1 for this specific application. The
following steps provide a sequence of items that must be executed in the time between powering the device up
and reading data from the device or transitioning from one mode to another mode of operation.
1. Apply power to the device:
a. Power-up the IOVDD and AVDD power supplies
b. Wait for at least 1 ms to allow the device to initialize the internal registers initialization
c. The device now goes into sleep mode (low-power mode < 10 µA)
2. Transition from sleep mode to active mode whenever required for the recording operation:
a. Wake up the device by writing to P0_R2 to disable sleep mode
b. Wait for at least 1 ms to allow the device to complete the internal wake-up sequence
c. Override default configuration registers or programmable coefficients value as required (this step is
optional)
d. Enable all desired input channels by writing to P0_R115
e. Enable all desired audio serial interface output channels by writing to P0_R116
f. Power-up the ADC, MICBIAS, and PLL by writing to P0_R117
g. Apply FSYNC and BCLK with the desired output sample rates and the BCLK to FSYNC ratio
This specific step can be done at any point in the sequence after step a.
See the 节8.3.2 section for supported sample rates and the BCLK to FSYNC ratio.
h. The device recording data are now sent to the host processor via the TDM audio serial data bus
3. Transition from active mode to sleep mode (again) as required in the system for low-power operation:
a. Enter sleep mode by writing to P0_R2 to enable sleep mode
b. Wait at least 6 ms (when FSYNC = 48 kHz) for the volume to ramp down and for all blocks to power
down
c. Read P0_R119 to check the device shutdown and sleep mode status
d. If the device P0_R119_D7 status bit is 1'b1 then stop FSYNC and BCLK in the system
e. The device now goes into sleep mode (low-power mode < 10 µA) and retains all register values
4. Transition from sleep mode to active mode (again) as required for the recording operation:
a. Wake up the device by writing to P0_R2 to disable sleep mode
b. Wait for at least 1 ms to allow the device to complete the internal wake-up sequence
c. Apply FSYNC and BCLK with the desired output sample rates and the BCLK to FSYNC ratio
d. The device recording data are now sent to the host processor via the TDM audio serial data bus
5. Repeat step 2 to step 4 as required for configuration changes or step 3 to step 4 for mode transitions
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9.2.1.2.1 Example Device Register Configuration Script for EVM Setup
This section provides a typical EVM I2C register control script that shows how to set up the PCM3120-Q1 in a
two-channel analog microphone recording mode with differential inputs.
# Key: w 9C XX YY ==> write to I2C address 0x9C, to register 0xXX, data 0xYY
#
#
# ==> comment delimiter
# The following list gives an example sequence of items that must be executed in the time
# between powering the device up and reading data from the device. There are
# other valid sequences depending on which features are used.
#
# See the PCM3120-Q1EVM user guide for jumper settings and audio connections.
#
# Differential 2-channel : INP1/INM1 - Ch1, INP2/INM2 - Ch2
# FSYNC = 44.1 kHz (output data sample rate), BCLK = 11.2896 MHz (BCLK/FSYNC = 256)
################################################################
#
#
# Power-up the IOVDD and AVDD power supplies
# Wait for the IOVDD and AVDD power supplies to settle to a steady-state operating voltage range.
# Wait for 1 ms.
#
# Wake-up the device with an I2C write into P0_R2 using an internal AREG
w 9C 0281
#
# Enable input Ch-1 and Ch-2 by an I2C write into P0_R115
w 9C 73 C0
#
# Enable ASI output Ch-1 and Ch-2 slots by an I2C write into P0_R116
w 9C 74 C0
#
# Power-up the ADC, MICBIAS, and PLL by an I2C write into P0_R117
w 9C 75 E0
#
# Apply FSYNC = 44.1 kHz and BCLK = 11.2896 MHz and
# Start recording data via the host on the ASI bus with a TDM protocol 32-bits channel wordlength
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9.2.1.3 Application Curves
Measurements are done on the EVM by feeding the device analog input signal using audio precision.
0
-20
-60
Channel-1
Channel-2
Channel-1
Channel-2
-70
-40
-80
-60
-80
-90
-100
-120
-140
-160
-180
-200
-100
-110
-120
-130
20 30 4050 70 100
200 300 500
1000 2000
5000 10000 20000
ADC3
-130
-115
-100
-85
-70
-55
-40
-25
-10
0
Frequency (Hz)
Input Amplitude (dB)
ATHDDC+3
图9-2. FFT With a –60-dBr Input
图9-3. THD+N vs Input Amplitude
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9.2.2 Four-Channel Digital PDM Microphone Recording
图 9-4 shows a typical configuration of the PCM3120-Q1 for an application using four digital PDM MEMS
microphones with simultaneous recording operation using an I2C control interface and the TDM audio data slave
interface. If the MICBIAS output is not used in the system then the 1 µF capacitor for the MICBIAS pin is not
must.
10 μF
1 μF
VDD
(3.0 V to 3.6 V)
0.1 μF
0.1 μF
1 μF
10 μF
VDD
SEL
VSS
CLK
VDD
0.1 μF
DREG
DMIC1
Rterm
0.1 μF
MICBIAS_GPI2
DOUT
VDD
SEL
CLK
VDD
0.1 μF
3.3 V
(3.0 V to 3.6 V)
OR
1.8 V
(1.65 V to 1.95 V)
DMIC2
VSS
DOUT
Rterm
Rterm
10 μF
VDD
SEL
CLK
VDD
0.1 μF
DMIC3
PCMx120-Q1
IN2P_GPI1
DOUT
IOVDD
VSS
0.1 μF
VDD
SEL
CLK
IN2M_GPO1
VDD
0.1 μF
Rterm
DMIC4
Thermal Pad
(VSS)
DOUT
VSS
Rterm
IN1P
IN1M
R Ω
R Ω
Host
Processor
图9-4. Four-Channel Digital PDM Microphone Recording Diagram
9.2.2.1 Design Requirements
表9-2 lists the design parameters for this application.
表9-2. Design Parameters
KEY PARAMETER
SPECIFICATION
AVDD
3.3 V
AVDD supply current consumption
IOVDD
>8 mA (PLL on, four-channel recording, fS = 48 kHz)
1.8 V or 3.3 V
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9.2.2.2 Detailed Design Procedure
This section describes the necessary steps to configure the PCM3120-Q1 for this specific application. The
following steps provide a sequence of items that must be executed in the time between powering the device up
and reading data from the device or transitioning from one mode to another mode of operation.
1. Apply power to the device:
a. Power up the IOVDD and AVDD power supplies
b. Wait for at least 1 ms to allow the device to initialize the internal registers initialization
c. The device now goes into sleep mode (low-power mode < 10 µA)
2. Transition from sleep mode to active mode whenever required for the recording operation:
a. Wake up the device by writing to P0_R2 to disable sleep mode
b. Wait for at least 1 ms to allow the device to complete the internal wake-up sequence
c. Override the default configuration registers or programmable coefficients value as required (this step is
optional)
d. Configure channel 1 to channel 2 (CHx_INSRC) for the digital microphone as the input source for
recording
e. Configure GPO1 (GPO1_CFG) and GPIO1 (GPIO1_CFG) as the PDMCLK output
f. Configure GPIx (GPI1x_CFG) as PDMDINx
g. Enable all desired input channels by writing to P0_R115
h. Enable all desired audio serial interface output channels by writing to P0_R116
i. Power-up the ADC and PLL by writing to P0_R117
j. Apply FSYNC and BCLK with the desired output sample rates and the BCLK to FSYNC ratio
This specific step can be done at any point in the sequence after step a.
See the 节8.3.2 section for supported sample rates and the BCLK to FSYNC ratio.
k. The device recording data is now sent to the host processor using the TDM audio serial data bus
3. Transition from active mode to sleep mode (again) as required in the system for low-power operation:
a. Enter sleep mode by writing to P0_R2 to enable sleep mode
b. Wait at least 6 ms (when FSYNC = 48 kHz) for the volume to ramp down and for all blocks to power
down
c. Read P0_R119 to check the device shutdown and sleep mode status
d. If the device P0_R119_D7 status bit is 1'b1 then stop FSYNC and BCLK in the system
e. The device now goes into sleep mode (low-power mode < 10 µA) and retains all register values
4. Transition from sleep mode to active mode (again) as required for the recording operation:
a. Wake up the device by writing to P0_R2 to disable sleep mode
b. Wait at least 1 ms to allow the device to complete the internal wake-up sequence
c. Apply FSYNC and BCLK with the desired output sample rates and the BCLK to FSYNC ratio
d. The device recording data are now sent to the host processor using the TDM audio serial data bus
5. Repeat step 3 and step 4 as required for mode transitions and step 2 to step 4 for configuration changes
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9.2.2.2.1 Example Device Register Configuration Script for EVM Setup
This section provides a typical EVM I2C register control script that shows how to set up the PCM3120-Q1 in a
four-channel digital PDM microphone recording mode.
# Key: w 9C XX YY ==> write to I2C address 0x9C, to register 0xXX, data 0xYY
#
#
# ==> comment delimiter
# The following list gives an example sequence of items that must be executed in the time
# between powering the device up and reading data from the device. There are
# other valid sequences depending on which features are used.
#
# See the PCM3120-Q1EVM user guide for jumper settings and audio connections.
#
# PDM 4-channel : PDMDIN1 - Ch1 and Ch2, PDMDIN2 - Ch3 and Ch4
#
# FSYNC = 44.1 kHz (output data sample rate), BCLK = 11.2896 MHz (BCLK/FSYNC = 256)
################################################################
#
#
# Power-up the IOVDD and AVDD power supplies
# Wait for the IOVDD and AVDD power supplies to settle to a steady state operating voltage range.
# Wait for 1 ms.
#
# Wake-up the device by an I2C write into P0_R2 using an internal AREG
w 9C 02 81
#
# Configure CH2_INSRC as a digital PDM input by an I2C write into P0_R65
w 9C 41 40
#
# Configure MICBIAS_GPI2 as a digital PDM input by an I2C write into P0_R59
w 9C 3B 70
#
# Configure GPO1 as PDMCLK by an I2C write into P0_R34
w 9C 22 41
#
# Configure GPI1 and GPI2 as PDMDIN1 and PDMDIN2 by an I2C write into P0_R43
w 9C 2B 45
#
# Enable input Ch-1 to Ch-4 by an I2C write into P0_R115
w 9C 73 F0
#
# Enable ASI output Ch-1 to Ch-4 slots by an I2C write into P0_R116
w 9C 74 F0
#
# Power-up the ADC and PLL by an I2C write into P0_R117
w 9C 75 60
#
# Apply FSYNC = 44.1 kHz and BCLK = 11.2896 MHz and
# Start recording data via the host on the ASI bus with a TDM protocol 32-bits channel wordlength
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9.3 What to Do and What Not to Do
In the VAD mode of operation, there are some limitations on interrupt generation when auto wake up is enabled.
For details about these limitations, see the Using the Voice Activity Detector (VAD) in the TLV320ADC5120 and
TLV320ADC6120 application report.
The automatic gain controller (AGC) feature has some limitation when using sampling rates lower than 44.1 kHz.
For further details about this limitation, see the Using the Automatic Gain Controller (AGC) in TLV320ADCx120
Family application report.
10 Power Supply Recommendations
The power-supply sequence between the IOVDD and AVDD rails can be applied in any order. However, after all
supplies are stable, then only initiate the I2C transactions to initialize the device.
For the supply power-up requirement, t1 and t2 must be at least 2 ms to allow the device to initialize the internal
registers. See the 节 8.4 section for details on how the device operates in various modes after the device power
supplies are settled to the recommended operating voltage levels. For the supply power-down requirement, t3
and t4 must be at least 10 ms. This timing (as shown in 图 10-1) allows the device to ramp down the volume on
the record data, power down the analog and digital blocks, and put the device into shutdown mode. The device
can also be immediately put into shutdown mode by ramping down power supplies, but doing so causes an
abrupt shutdown.
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AVDD
t1
t3
IOVDD
I2C bus transaction for PCMx120-Q1
t4
t2
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Make sure that the supply ramp rate is slower than 1 V/µs and that the wait time between a power-down and a
power-up event is at least 100 ms. For supply ramp rate slower than 0.1 V/ms, host device must apply a
software reset as first transaction before doing any device configuration. Make sure all digital input pins are at
valid input levels and not toggling during supply sequencing.
The PCM3120-Q1 supports a single AVDD supply operation by integrating an on-chip digital regulator, DREG,
and an analog regulator, AREG. However, if the AVDD voltage is less than 1.98 V in the system, then short the
AREG and AVDD pins onboard and do not enable the internal AREG by keeping the AREG_SELECT bit to 1b'0
(default value) of P0_R2. If the AVDD supply used in the system is higher than 2.7 V, then the host device can
set AREG_SELECT to 1'b1 while exiting sleep mode to allow the device internal regulator to generate the AREG
supply.
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11 Layout
11.1 Layout Guidelines
Each system design and printed circuit board (PCB) layout is unique. The layout must be carefully reviewed in
the context of a specific PCB design. However, the following guidelines can optimize the device performance:
• Connect the thermal pad to ground. Use a via pattern to connect the device thermal pad, which is the area
directly under the device, to the ground planes. This connection helps dissipate heat from the device.
• The decoupling capacitors for the power supplies must be placed close to the device pins.
• The supply decoupling capacitors must be used ceramic type with low ESR.
• Route the analog differential audio signals differentially on the PCB for better noise immunity. Avoid crossing
digital and analog signals to prevent undesirable crosstalk.
• The device internal voltage references must be filtered using external capacitors. Place the filter capacitors
near the VREF pin for optimal performance.
• Directly tap the MICBIAS pin to avoid common impedance when routing the biasing or supply traces for
multiple microphones to avoid coupling across microphones.
• Directly short the VREF and MICBIAS external capacitors ground terminal to the AVSS pin without using any
vias for this connection trace.
• Place the MICBIAS capacitor (with low equivalent series resistance) close to the device with minimal trace
impedance.
• Use ground planes to provide the lowest impedance for power and signal current between the device and the
decoupling capacitors. Treat the area directly under the device as a central ground area for the device, and
all device grounds must be connected directly to that area.
11.2 Layout Example
10:VSS
16:AVDD
9:IOVDD
8:FSYNC
7:BCLK
21:VSS
17:AREG
18:VREF
19:MICBIAS_GPI2
20:VSS
6:SDOUT
图11-1. Layout Example
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Multiple TLV320ADCx140 & TLV320ADCx120 Multiple TLV320ADCx140 Devices With
Shared TDM and I2C Bus application report
• Texas Instruments, Configuring and Operating TLV320ADCx120 as an Audio Bus Master application report
• Texas Instruments, TLV320ADCx120 Sampling Rates and Programmable Processing Blocks Supported
application report
• Texas Instruments, TLV320ADCx140 & TLV320ADCx120 Programmable Biquad Filter Configuration and
Applications application report
• Texas Instruments, TLV320ADCx120 Power Consumption Matrix Across Various Usage Scenarios
application report
• Texas Instruments, TLV320ADCx140 & TLV320ADCx120 Integrated Analog Anti-Aliasing Filter and Flexible
Digital Filter application report
• Texas Instruments, Using the Automatic Gain Controller (AGC) in TLV320ADCx120 Family application report
• Texas Instruments, Using the Voice Activity Detector (VAD) in the TLV320ADCx120 and PCMD3140 devices
application report
• Texas Instruments, Input Common Mode Tolerance and High CMRR modes for TLV320ADCx120 devices
application report
• Texas Instruments, ADCx120EVM-PDK Evaluation module user's guide
• Texas Instruments, PurePath™ Console Graphical Development Suite for Audio System Design and
Development
12.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.4 Trademarks
Burr-Brown™, PurePath™, and TI E2E™ are trademarks of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
A
RTE0020A
3.1
2.9
B
PIN 1 INDEX AREA
3.1
2.9
C
0.8 MAX
SEATING PLANE
0.08
C
0.05
0.00
1.5
SQ
1.4 0.1
4X (SQ 0.2)
TYP
(0.1)
6
10
5
9
8X 0.4625
0.225
8X
4
0.125
0.1
11
C A B
0.05
C
SYMM
21
1.5
14
1
12X 0.5
0.3
16X
0.2
0.1
C A B
PIN1 ID
(OPTIONAL)
15
20
19
16
0.05
C
0.5
0.3
16X
SYMM
4225900/A 06/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
WQFN - 0.8 mm max height
RTE0020A
PLASTIC QUAD FLATPACK- NO LEAD
(2.825)
(2.8)
(SQ 1.4)
4X (0.575)
4X (0.175)
16X (0.6)
4X (0.575)
19
16
15
20
8X (0.4625)
1
4X (0.175)
14
16X (0.25)
(2.825)
SYMM
21
(2.8)
12X (0.5)
4
2X (0.45)
11
(R 0.05) TYP
(Ø 0.2) VIA
TYP
5
10
2X (0.45)
9
6
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4225900/A 06/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271)
.
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
WQFN - 0.8 mm max height
RTE0020A
PLASTIC QUAD FLATPACK- NO LEAD
(2.825)
(2.8)
4X (0.575)
4X (0.175)
(SQ 1.3)
16X (0.6)
4X (0.575)
19
16
15
20
8X (0.4625)
4X (0.175)
21
1
14
16X (0.25)
12X (0.5)
(2.825)
(2.8)
SYMM
11
4
(R 0.05) TYP
METAL TYP
5
10
9
6
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
86% PRINTED COVERAGE BY AREA
SCALE: 20X
4225900/A 06/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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13.1 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
Reel
Diameter
(mm)
Reel
Width W1
(mm)
Package
Type
Package
Drawing
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
Device
Pins
SPQ
XCM3120QRTERQ1
WQFN
RTE
20
3000
330
12.4
3.3
3.3
1.1
8
12
Q2
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TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
Device
XCM3120QRTERQ1
Package Type
Package Drawing Pins
RTE 20
SPQ
Length (mm) Width (mm)
367 367
Height (mm)
WQFN
3000
35
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Product Folder Links: PCM3120-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Dec-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PCM3120QRTERQ1
ACTIVE
WQFN
RTE
20
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
3120Q
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
PCM3120QRTERQ1
WQFN
RTE
20
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
WQFN RTE 20
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
PCM3120QRTERQ1
3000
Pack Materials-Page 2
PACKAGE OUTLINE
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
A
RTE0020A
3.1
2.9
B
PIN 1 INDEX AREA
3.1
2.9
C
0.8 MAX
SEATING PLANE
0.08 C
0.05
0.00
1.5
SQ
1.4±0.1
4X (SQ 0.2)
TYP
(0.1)
6
10
5
9
8X 0.4625
0.225
0.125
0.1
8X
4
11
C
A B
0.05
C
SYMM
21
1.5
14
1
12X 0.5
0.3
0.2
0.1
16X
0.5
C A B
PIN1 ID
(OPTIONAL)
15
20
19
16
0.05
C
16X
SYMM
0.3
4225900/A 06/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
WQFN - 0.8 mm max height
RTE0020A
PLASTIC QUAD FLATPACK- NO LEAD
(2.825)
(2.8)
(SQ 1.4)
4X (0.575)
4X (0.175)
16X (0.6)
4X (0.575)
15
19
16
20
8X (0.4625)
4X (0.175)
14
1
16X (0.25)
12X (0.5)
(2.825)
(2.8)
SYMM
21
2X (0.45)
11
4
(R 0.05) TYP
(Ø 0.2) VIA
TYP
5
10
2X (0.45)
9
6
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.07 MAX
0.07 MIN
ALL AROUND
ALL AROUND
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4225900/A 06/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271)
.
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
WQFN - 0.8 mm max height
RTE0020A
PLASTIC QUAD FLATPACK- NO LEAD
(2.825)
(2.8)
4X (0.575)
4X (0.175)
(SQ 1.3)
16X (0.6)
4X (0.575)
19
16
15
20
8X (0.4625)
4X (0.175)
21
1
14
16X (0.25)
12X (0.5)
(2.825)
SYMM
(2.8)
11
4
(R 0.05) TYP
METAL TYP
5
10
9
6
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
86% PRINTED COVERAGE BY AREA
SCALE: 20X
4225900/A 06/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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