PCM4104_技术文档

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SBAS291C − AUGUST 2003 − REVISED DECEMBER 2004

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FEATURES

APPLICATIONS

D

Digital Mixing Consoles

Digital Audio Workstations

Digital Audio Effects Processors

Broadcast Studio Equipment

Surround-Sound Processors

High-End A/V Receivers

D

Four High-Performance, Multi-Level,

Delta-Sigma Digital-to-Analog Converters

Differential Voltage Outputs

− Full-Scale Output (Differential): 6.15V

PP

D

Supports Sampling Frequencies up to 216kHz

D

Typical Dynamic Performance (24-Bit Data)

− Dynamic Range (A-Weighted): 118dB

− THD+N: −100dB

DESCRIPTION

D

Linear Phase, 8x Oversampling Digital

Interpolation Filter

The PCM4104 is a high-performance, four-channel

digital-to-analog (D/A) converter designed for use in

professional audio applications. The PCM4104 supports

16- to 24-bit linear PCM input data, with sampling

frequencies up to 216kHz. The PCM4104 features lower

power consumption than most comparable stereo audio

D/A converters, making it ideal for use in high channel

count applications by lowering the overall power budget

required for the D/A conversion sub-system.

Digital De-Emphasis Filters for 32kHz,

44.1kHz, and 48kHz Sampling Rates

Soft Mute Function

− All-Channel Mute via the MUTE Input Pin

− Per-Channel Mute Available in Software

Mode

D

Digital Attenuation (Software Mode Only)

− Attenuation Range: 0dB to −119.5dB

− 256 Steps with 0.5dB per Step

The PCM4104 features delta-sigma architecture,

employing a high-performance multi-level modulator

combined with a switched capacitor output filter. This

architecture yields lower out-of-band noise and a high

tolerance to system clock phase jitter. Differential voltage

outputs are provided for each channel and are well-suited

to high-performance audio applications. The differential

outputs are easily converted to a single-ended output

using an external op amp IC.

D

Output Phase Inversion (Software Mode Only)

Zero Data Mute (Software Mode Only)

Audio Serial Port

− Supports Left-Justified, Right-Justified,

2

I SE, and TDM Data Formats

− Accepts 16-, 18-, 20, and 24-Bit Two’s

Complement PCM Audio Data

The PCM4104 includes a flexible audio serial port

interface, which supports standard and time division

multiplexed (TDM) formats. Support for TDM formats

simplifies interfacing to DSP serial ports, while supporting

a cascade connection for two PCM4104 devices. In

addition, the PCM4104 offers two configuration modes:

Standalone and Software-Controlled. The Standalone

mode provides dedicated control pins for configuring a

subset of the available PCM4104 functions, while

Software mode utilizes a serial peripheral interface (SPI)

port for accessing the complete feature set via internal

control registers.

D

Standalone or Software-Controlled

Configuration Modes

Four-Wire Serial Peripheral Interface (SPIE)

Port Provides Control Register Access in

Software Mode

D

Power Supplies: +5V Analog, +3.3V Digital

Power Dissipation

− 203mW typical with f = 48kHz

S

− 220mW typical with f = 96kHz

S

− 236mW typical with f = 192kHz

S

The PCM4104 operates from a +5V analog power supply

and a +3.3V digital power supply. The digital I/O is

compatible with +3.3V logic families. The PCM4104 is

available in a TQFP-48 package.

D

Power-Down Modes

Small 48-Lead TQFP Package

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

ꢅꢤ ꢥ ꢟꢦ ꢜ ꢧꢨ ꢥꢩ ꢟ ꢝꢧꢝ ꢁꢌ ꢈꢉ ꢇ ꢊꢋ ꢒꢁꢉꢌ ꢁꢪ ꢍꢛ ꢇ ꢇ ꢆꢌꢒ ꢋꢪ ꢉꢈ ꢘꢛꢫ ꢙꢁꢍ ꢋꢒꢁ ꢉꢌ ꢞꢋ ꢒꢆꢬ ꢅꢇ ꢉꢞꢛ ꢍꢒꢪ

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Copyright  2003−2004, Texas Instruments Incorporated

www.ti.com

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www.ti.com

SBAS291C − AUGUST 2003 − REVISED DECEMBER 2004

(1)

ORDERING INFORMATION

SPECIFIED

TEMPERATURE

RANGE

PACKAGE

DESIGNATOR

PACKAGE

MARKING

ORDERING

NUMBER

TRANSPORT

MEDIA, QUANTITY

PRODUCT

PACKAGE−LEAD

PCM4104PFBT

PCM4104PFBR

Tape and Reel, 250

Tape and Reel, 2000

PCM4104

TQFP-48

PFB

−10°C to +70°C

PCM4104PFB

(1)

For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or refer to

our web site at www.ti.com.

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate

precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to

damage because very small parametric changes could cause the device not to meet its published specifications.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted

(1)

PCM4104

+6.0

UNIT

V

CC

Supply voltage

+3.6

DD

Ground voltage difference

Any AGND-to-AGND and AGND-to-DGND

0.1

FS0, FS1, FMT0, FMT1, FMT2, CDOUT,

CDIN, CCLK, CS, DATA0, DATA1, BCK,

LRCK, SCKI, SUB, DEM0, DEM1, MUTE,

RST, MODE

Digital input voltage

−0.3 to (V

+ 0.3)

V

DD

Input current (any pin except supplies)

Operating temperature range

10

mA

°C

−10 to +70

−65 to +150

Storage temperature range, T

STG

°C

(1)

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum

conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or

any other conditions beyond those specified is not implied.

2

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SBAS291C − AUGUST 2003 − REVISED DECEMBER 2004

ELECTRICAL CHARACTERISTICS

All parameters are specified at T = +25°C with V

= +5V, V

= +3.3V, and a measurement bandwidth from 10Hz to 20kHz, unless otherwise

A

CC DD

noted. System clock frequency is equal to 256f for Single and Dual Rate sampling modes, and 128f for Quad Rate sampling mode.

S

PCM4104

TYP

PARAMETER

CONDITIONS

MIN

MAX

UNITS

RESOLUTION

DATA FORMAT

24

Bits

2

Audio data formats

Left or Right Justified, I S, and TDM

16 24

Two’s Complement Binary, MSB First

Audio data word length

Binary data format

Bits

CLOCK RATES AND TIMING

Single rate sampling mode

Dual rate sampling mode

Quad rate sampling mode

Single rate sampling mode

Dual rate sampling mode

Quad rate sampling mode

6.144

13.824

24

36.864

54

MHz

kHz

MHz

ns

System clock frequency

Sampling frequency

f

SCKI

54

108

f

S

108

216

SPI port data clock

f

24

CCLK

SPI port data clock high time

SPI port data clock low time

DIGITAL INPUT/OUTPUT

t

15

CCLKH

t

ns

CCLKL

V

2.0

V

IH

Input logic level

Input logic current

Output logic level

0.8

10

IL

I

V

= V

DD

1

µA

V

IH

IN

= 0V

−10

IL

IN

V

I

= −2mA

= +2mA

2.4

OH

OL

OH

V

I

0.4

V

ANALOG OUTPUTS

Full-scale output voltage, differential

Bipolar zero voltage

R

= 600Ω

6.15

2.5

5

V

L

PP

V

Output impedance

Ohms

dB

Switched capacitor filter frequency response

Gain error

f = 20kHz, all sampling modes

−0.2

0.5

0.6

1

% FSR

mV

Gain mismatch, channel-to-channel

Bipolar zero error

V

1 and V

2 output voltage

2 output current

V = +5V

CC

2.5

V

COM

200

µA

COM

3

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www.ti.com

SBAS291C − AUGUST 2003 − REVISED DECEMBER 2004

ELECTRICAL CHARACTERISTICS (continued)

All parameters are specified at T = +25°C with V

= +5V, V = +3.3V, and a measurement bandwidth from 10Hz to 20kHz, unless otherwise

DD

A

CC

noted. System clock frequency is equal to 256f for Single and Dual Rate sampling modes, and 128f for Quad Rate sampling mode.

S

PCM4104

TYP

PARAMETER

CONDITIONS

MIN

MAX

UNITS

(1)

DYNAMIC PERFORMANCE WITH 24-BIT DATA

f

= 48kHz

S

f = 1kHz at 0dBFS

−100

−56

118

119

116

110

−94

dB

Total harmonic distortion + noise

THD+N

f = 1kHz at −60dBFS

All zero input data

Dynamic range, A-weighted

Idle channel SNR, A-weighted

Idle channel SNR, unweighted

Channel separation

112

100

All zero input data

f = 1kHz at 0dBFS for active channel

f

= 96kHz

S

f = 1kHz at 0dBFS, BW = 10Hz to 40kHz

f = 1kHz at −60dBFS, BW = 10Hz to 40kHz

f = 1kHz at −60dBFS

−100

−53

118

119

113

110

dB

Total harmonic distortion + noise

Dynamic range, A-weighted

Idle channel SNR, A-weighted

Idle channel SNR, unweighted

Channel separation

All zero input data

All zero input data, BW = 10Hz to 40kHz

f = 1kHz at 0dBFS for active channel

fs = 192kHz

f = 1kHz at 0dBFS, BW = 10Hz to 40kHz

f = 1kHz at −60dBFS, BW = 10Hz to 40kHz

f = 1kHz at −60dBFS

−97

−53

118

113

110

dB

Total harmonic distortion + noise

Dynamic range, A-weighted

Idle channel SNR, A-weighted

Idle channel SNR, unweighted

Channel separation

All zero input data

All zero input data, BW = 10Hz to 40kHz

f = 1kHz at 0dBFS for active channel

DYNAMIC PERFORMANCE WITH 16-BIT DATA

fs = 44.1kHz

f = 1kHz at 0dBFS

f = 1kHz at −60dBFS

All zero input data

−92

−33

96

dB

Total harmonic distortion + noise

Dynamic Range, A-weighted

THD+N

(2)

Idle channel SNR, A-weighted

Idle channel SNR, unweighted

118

115

(2)

(1)

Dynamic performance parameters are measured using an Audio Precision System Two Cascade or Cascade Plus test system. Input data word

length is 24 bits with triangular PDF dither added for dynamic range and THD+N tests. Idle channel SNR is measured with both the soft and

zero data mute functions disabled and 0% full-scale input data with no dither applied. The measurement bandwidth is limited by using the Audio

Precision 10Hz high-pass filter in combination with either the AES17 20kHz low-pass filter or AES17 40kHz low-pass filter. All A-weighted

measurements are performed using the Audio Precision A-weighting filter in combination with either the 22kHz or 80kHz low-pass filter.

Measurementmode is set to RMS for all parameters. The AVERAGE measurement mode will yield better typical performance numbers.

Idle Channel SNR is not limited by word length.

(2)

4

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SBAS291C − AUGUST 2003 − REVISED DECEMBER 2004

ELECTRICAL CHARACTERISTICS (continued)

All parameters are specified at T = +25°C with V

= +5V, V = +3.3V, and a measurement bandwidth from 10Hz to 20kHz, unless otherwise

DD

A

CC

noted. System clock frequency is equal to 256f for Single and Dual Rate sampling modes, and 128f for Quad Rate sampling mode.

S

PCM4104

TYP

PARAMETER

CONDITIONS

MIN

MAX

UNITS

DIGITAL FILTERS

0.002dB

−3dB

0.454f

Hz

dB

sec

dB

S

Passband

0.487f

S

Stop Band

0.546fs

Passband ripple

0.002

0.546fs

0.567fs

−75

−82

Stopband attenuation

Group delay

29/f

S

De-emphasis filter error

POWER SUPPLY

Supply Range

0.1

Analog supply, V

+4.75

+3.0

+5.0

+3.3

+5.25

+3.6

V

CC

Digital supply, V

DD

Power down current

Power-down supply current, I

Quiescent current

V

= +5V, VDD = +3.3V

CC

+ I

CC DD

RST = low, system and audio clocks off

1

mA

System and audio clocks applied, all 0s data

V

= +5V, f =48kHz

S

32

13

18

23

40

17

mA

CC

DD

CC

= +5V, f =96kHz

S

Analog supply, I

CC

= +5V, f =192kHz

S

= +3.3V, f =48kHz

S

= +3.3V, f =96kHz

S

Digital supply, I

DD

= +3.3V, f =192kHz

S

= +5V, V

DD

= +3.3V

f

= 48kHz

203

220

236

256

mW

S

Total power dissipation

= 96kHz

= 192kHz

5

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SBAS291C − AUGUST 2003 − REVISED DECEMBER 2004

PIN ASSIGNMENTS

TQFP PACKAGE

(TOP VIEW)

48 47 46 45 44 43 42 41 40 39 38 37

1

2

V_OUT1+

36

35

V_OUT4+

−

V_OUT4

V

_OUT1

AGND1

3

34 AGND2

−

4

−

V

_REF1

33

32

31

V

_REF4

5

V

_REF1+

V

_REF4+

NC

6

NC

PCM4104

NC

7

30 NC

MODE

RST

8

29

28

27

FS1

9

FS0

10

11

MUTE

DEM1

FMT2

26 FMT1

25 FMT0

DEM0 12

13 14 15 16 17 18 19 20 21 22 23 24

Terminal Functions

TERMINAL

NAME

NO.

1

I/O

DESCRIPTION

Channel 1 Analog Output, Noninverted

Channel 1 Analog Output, Inverted

Analog Ground

V

1+

1−

Output

Ground

OUT

2

OUT

AGND1

3

V

1−

1+

4

5

Input

Channel 1 Low Reference Voltage; Connect to AGND

REF

Channel 1 High Reference Voltage; Connect to V

No Internal Connection

REF

CC

NC

6

7

No Internal Connection

MODE

RST

8

Input

Operating Mode (0 = Standalone, 1= Software Controlled)

Reset/Power Down (Active Low)

9

MUTE

DEM1

DEM0

SUB

10

11

12

13

14

All−Channel Soft Mute (Active High)

Digital De-Emphasis Filter Configuration

Sub-Frame Assignment (TDM Formats Only)

System Clock

SCKI

6

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TERMINAL

SBAS291C − AUGUST 2003 − REVISED DECEMBER 2004

Terminal Functions (continued)

NAME

NO.

I/O

DESCRIPTION

BCK

15

Input

Audio Bit (or Data) Clock

LRCK

DATA0

16

17

Input

Audio Left/Right (or Word) Clock

2

Audio Data for Channels 1 and 2 (I S, Left/Right Justified formats)

or Audio Data for Channels 1 Through 4 for TDM Formats

2

DATA1

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

Input

Power

Ground

Input

Audio Data for Channels 3 and 4 (I S, Left/Right Justified formats)

V

DD

Digital Power Supply, +3.3V

DGND

CS

Digital Ground

Serial Peripheral Interface (SPI) Chip Select (Active Low)

Serial Peripheral Interface (SPI) Data Clock

Serial Peripheral Interface (SPI) Data Input

Serial Peripheral Interface (SPI) Data Output

Audio Data Format Configuration

Sampling Mode Configuration

CCLK

CDIN

CDOUT

FMT0

FMT1

FMT2

FS0

Input

Output

Input

FS1

Input

Sampling Mode Configuration

NC

No Internal Connection

NC

No Internal Connection

V

4+

4−

Input

Channel 4 High Reference Voltage; Connect to V

CC

REF

Channel 4 Low Reference Voltage; Connect to AGND

Analog Ground

REF

AGND2

Ground

Output

Power

Input

V

4−

4+

Channel 4 Analog Output, Inverted

OUT

COM

Channel 4 Analog Output, Noninverted

DC Common-Mode Voltage for Channels 3 and 4, +2.5V nominal

Channel 3 Analog Output, Noninverted

Channel 3 Analog Output, Inverted

2

3+

OUT

3−

2

CC

Analog Power Supply, +5V

3+

3−

2−

2+

Channel 3 High Reference Voltage; Connect to V

CC

REF

Input

Channel 3 Low Reference Voltage,; Connect to AGND

Channel 2 Low Reference Voltage; Connect to AGND

Input

Channel 2 High Reference Voltage; Connect to V

CC

1

CC

Power

Output

Analog Power Supply, +5V

2−

2+

Channel 2 Analog Output, Inverted

Channel 2 Analog Output, Noninverted

OUT

COM

1

DC Common-Mode Voltage for Channels 1 and 2, +2.5V nominal

7

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SBAS291C − AUGUST 2003 − REVISED DECEMBER 2004

TYPICAL CHARACTERISTICS

All parameters are specified at T = +25°C with V

CC

= +5V, V = +3.3V, and a measurement bandwidth from 10Hz to 20kHz, unless otherwise

DD

A

noted. System clock frequency is equal to 256f for Single and Dual Rate sampling modes, and 128f for Quad Rate sampling mode.

S

FFT PLOT

0

10

20

30

40

50

60

70

80

90

100

110

120

130

140

150

160

0

10

f_S= 48kHz

f_IN= 1kHz

0dBFS Amplitude

24−Bit Data

f_S= 48kHz

−

20 f_IN= 1kHz

30

40

50

60

70

80

90

100

110

120

130

140

150

160

−

20dBFS Amplitude

24−Bit Data

20

100

1k

10k 20k

40k

20

100

1k

10k 20k

Frequency (Hz)

FFT PLOT

0

10

f_S= 48kHz

Idle Channel Input

24−Bit Data

f_S= 48kHz

−

10

20

30

40

50

60

70

80

90

100

110

120

130

140

150

160

−

20 f_IN= 1kHz

30

−

60dBFS Amplitude

24−Bit Data

40

50

60

70

80

90

100

110

120

130

140

150

160

−

20

100

1k

10k 20k

20

100

1k

Frequency (Hz)

FFT PLOT

0

10

0

10

f_S= 96kHz

−

20 f_IN= 1kHz

30

20 f_IN= 1kHz

30

40

50

60

70

80

90

100

110

120

130

140

150

160

−

0dBFS Amplitude

24−Bit Data

20dBFS Amplitude

24−Bit Data

40

50

60

70

80

90

100

110

120

130

140

150

160

20

100

1k

10k

20

100

1k

10k

40k

Frequency (Hz)

8

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SBAS291C − AUGUST 2003 − REVISED DECEMBER 2004

TYPICAL CHARACTERISTICS (continued)

All parameters are specified at T = +25°C with V

CC

= +5V, V

DD

= +3.3V, and a measurement bandwidth from 10Hz to 20kHz, unless otherwise

A

noted. System clock frequency is equal to 256f for Single and Dual Rate sampling modes, and 128f for Quad Rate sampling mode.

S

FFT PLOT

0

10

0

10

f_S= 96kHz

−

20 f_IN= 1kHz

20 Idle Channel Input

30

40

50

60

70

80

90

−

60dBFS Amplitude

24−Bit Data

40

50

60

70

80

90

24−Bit Data

−

100

110

120

130

140

150

160

100

110

120

130

140

150

160

20

100

1k

10k

40k

20

100

1k

10k

40k

Frequency (Hz)

FFT PLOT

0

10

0

f_S= 192kHz

−

10

−

20 f_IN= 1kHz

30

−

30

40

50

60

70

80

90

−

0dBFS Amplitude

24−Bit Data

20dBFS Amplitude

40

50

60

70

80

90

24−Bit Data

−

100

110

120

130

140

150

160

100

110

120

130

140

150

160

20

100

1k

20

100

1k

Frequency (Hz)

FFT PLOT

0

f_S= 192kHz

−

f_S= 192kHz

10

20 f_IN= 1kHz

−

10

20 Idle Channel Input

30

40

50

60

70

80

90

−

60dBFS Amplitude

30

40

50

60

70

80

90

24−Bit Data

−

100

110

120

130

140

150

160

−

100

110

120

130

140

150

160

20

100

1k

20

100

1k

Frequency (Hz)

9

ꢅ ꢜꢢ ꢐ ꢓ ꢣ ꢐ

www.ti.com

SBAS291C − AUGUST 2003 − REVISED DECEMBER 2004

TYPICAL CHARACTERISTICS (continued)

All parameters are specified at T = +25°C with V

CC

= +5V, V = +3.3V, and a measurement bandwidth from 10Hz to 20kHz, unless otherwise

DD

A

noted. System clock frequency is equal to 256f for Single and Dual Rate sampling modes, and 128f for Quad Rate sampling mode.

S

FFT PLOT

0

10

0

10

f_S= 44.1kHz

−

20 f_IN= 1kHz

30

20 f_IN= 1kHz

30

40

50

60

70

80

90

−

0dBFS Amplitude

16−Bit Data

20dBFS Amplitude

40

50

60

70

80

90

16−Bit Data

−

100

110

120

130

140

150

160

100

110

120

130

140

150

160

20

100

1k

10k 20k

20

100

1k

10k 20k

Frequency (Hz)

FFT PLOT

0

10

f_S= 44.1kHz

−

10

20 f_IN= 1kHz

20 Idle Channel Input

30

40

50

60

70

80

90

−

60dBFS Amplitude

16−Bit Data

40

50

60

70

80

90

16−Bit Data

−

100

110

120

130

140

150

160

100

110

120

130

140

150

160

20

100

1k

10k 20k

20

100

1k

10k 20k

Frequency (Hz)

THD+N vs AMPLITUDE

−

80

f_S= 48kHz

f_S= 96kHz

85 f_IN= 1kHz

24−Bit Data

85 f_IN= 1kHz

24−Bit Data

90

95

−

100

105

110

115

120

100

105

110

115

120

Amplitude (dBFS)

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TYPICAL CHARACTERISTICS (continued)

All parameters are specified at T = +25°C with V

CC

= +5V, V

DD

= +3.3V, and a measurement bandwidth from 10Hz to 20kHz, unless otherwise

A

noted. System clock frequency is equal to 256f for Single and Dual Rate sampling modes, and 128f for Quad Rate sampling mode.

S

THD+N vs AMPLITUDE

−

80

f_S= 192kHz

f_S= 44.1kHz

85 f_IN= 1kHz

24−Bit Data

90

85 f_IN= 1kHz

16−Bit Data

90

95

−

100

105

110

115

120

100

105

110

115

120

Amplitude (dBFS)

FREQUENCY RESPONSE

PASSBAND RIPPLE

0

0.003

0.002

0.001

0

−

20

40

60

80

−

100

120

−

0.001

0.002

0.003

−

140

160

0

1

2

3

4

0

0.1

0.2

0.3

0.4

0.5

Frequency (x f_S)

DE−EMPHASIS FILTER RESPONSE (f_S= 32kHz)

DE−EMPHASIS ERROR (f_S= 32kHz)

0.0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

9.0

0.5

0.4

0.3

0.2

0.1

0.0

−

0.1

0.2

0.3

0.4

0.5

−

10.0

0

2

4

6

8

10

12

14

0

2

4

6

8

10

12

14

Frequency (kHz)

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TYPICAL CHARACTERISTICS (continued)

All parameters are specified at T = +25°C with V

CC

= +5V, V = +3.3V, and a measurement bandwidth from 10Hz to 20kHz, unless otherwise

DD

A

noted. System clock frequency is equal to 256f for Single and Dual Rate sampling modes, and 128f for Quad Rate sampling mode.

S

DE−EMPHASIS FILTER RESPONSE (f_S= 44.1kHz)

DE−EMPHASIS ERROR (f_S= 44.1kHz)

0.0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

9.0

0.5

0.4

0.3

0.2

0.1

0.0

0.1

0.2

0.3

0.4

0.5

−

10.0

0

2

4

6

8

10

12

14

16

18

20

0

2

4

6

8

10

12

14

16

18

20

Frequency (kHz)

DE− EMPHASIS FILTER RESPONSE (f_S= 48kHz)

DE− EMPHASIS ERROR (f_S= 48kHz)

0.0

0.5

0.4

0.3

0.2

0.1

0.0

0.1

0.2

0.3

0.4

0.5

−

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

9.0

−

10.0

0

2

4

6

8

10

12

14

16

18

22

0

2

4

6

8

10

12

14

16

18

22

Frequency (kHz)

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SBAS291C − AUGUST 2003 − REVISED DECEMBER 2004

PRODUCT OVERVIEW

The PCM4104 is a high-performance, four-channel D/A

converter designed for professional audio systems. The

PCM4104 supports 16- to 24-bit linear PCM input data and

sampling frequencies up to 216kHz. The PCM4104

utilizes an 8x oversampling digital interpolation filter,

followed by a multi-level delta-sigma modulator with a

single pole switched capacitor output filter. This

architecture provides excellent dynamic and sonic

performance, as well as high tolerance to clock phase

jitter. Functional block diagrams, showing both

Standalone and Software modes, are shown in Figure 1

and Figure 2.

Philips I²S) and TDM data formats. The TDM formats are

especially useful for interfacing to the synchronous serial

ports of digital signal processors. The TDM formats

support daisy-chaining of two PCM4104 devices on a

single three-wire serial interface (for sampling frequencies

up to 108kHz), forming a high-performance eight-channel

D/A conversion system.

The PCM4104 offers two modes for configuration control:

Software and Standalone. Software mode makes use of a

four-wire SPI port to access internal control registers,

allowing configuration of the full PCM4104 feature set.

Standalone mode offers a more limited subset of the

functions available in Software mode, while allowing for a

simplified pin-programmed configuration mode.

The PCM4104 incorporates a flexible audio serial port,

which accepts 16- to 24-bit PCM audio data in both

standard audio formats (Left Justified, Right Justified, and

V_REF1+

V_OUT1+

D/A Converter

and

−

1

V_OUT

Output Filter

LRCK

BCK

Audio

Serial

Port

−

_REF1

V

DATA0

DATA1

_COM1

_REF2+

V_OUT2+

D/A Converter

and

RST

MUTE

DEM0

DEM1

SUB

−

2

V_OUT

Output Filter

−

_REF2

V

Digital

Filtering

and

V_REF3+

V_OUT3+

Control

FMT0

FMT1

FMT2

FS0

Functions

D/A Converter

and

Output Filter

−

_OUT3

V

FS1

MODE

−

_REF3

V

_COM2

_REF4+

System Clock

and

V_OUT4+

D/A Converter

and

Output Filter

SCKI

Timing

−

V_OUT4

−

V_REF4

V_CC

AGND1

V_CC2

AGND2

1

V_DD

Digital

Power

Analog

Power

DGND

1

Figure 1. Functional Block Diagram for Standalone Mode

13

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SBAS291C − AUGUST 2003 − REVISED DECEMBER 2004

V_REF1+

V_OUT1+

D/A Converter

and

−

V_OUT1

Output Filter

LRCK

Audio

BCK

DATA0

DATA1

Serial

Port

−

_REF1

V

_COM1

_REF2+

D/A Converter

and

V_OUT2+

Output Filter

−

_OUT2

V

RST

MUTE

SUB

−

_REF2

Digital

Filtering

and

Control

and

SPI Port

V_REF3+

V_OUT3+

CS

Functions

CCLK

CDIN

CDOUT

MODE

D/A Converter

and

−

_OUT3

V

Output Filter

−

3

V_REF

V_DD

V_COM

2

V_REF4+

System Clock

and

V

_OUT4+

D/A Converter

and

Output Filter

SCKI

Timing

−

V_OUT4

−

_REF4

V

V_CC

AGND1

_CC21

AGND2

1

V_DD

Digital

Power

Analog

Power

DGND

V

Figure 2. PCM4104 Functional Block Diagram for Software Mode

recommended to further reduce the out-of-band noise

energy and to band limit the output spectrum to

frequencies suitable for audio reproduction. Refer to the

Applications Information section of this data sheet for

recommended output filter circuits.

ANALOG OUTPUTS

The PCM4104 provides four differential voltage outputs,

corresponding to audio channels 1 through 4. V_OUT1+ (pin

1) and V_OUT1− (pin 2) correspond to Channel 1. V_OUT2+

(pin 47) and V_OUT2− (pin 46) correspond to Channel 2.

V

_OUT3+ (pin 38) and V_OUT3− (pin 39) correspond to

Channel 3. V_OUT4+ (pin 36) and V_OUT4− (pin 35)

correspond to Channel 4.

VOLTAGE REFERENCES

The PCM4104 includes high and low reference pins for

each output channel. V_REF1+ (pin 5) and V_REF1− (pin 4)

correspond to Channel 1. V_REF2+ (pin 44) and V_REF2− (pin

43) correspond to Channel 2. V_REF3+ (pin 41) and V_REF3−

(pin 42) correspond to Channel 3. V_REF4+ (pin 32) and

Each differential output is typically capable of providing

6.15V full-scale (differential) into a 600Ω output load. The

output pins are internally biased to the common-mode (or

bipolar zero) voltage, which is nominally V_CC/2. The output

section of each D/A converter channel includes a

single-pole, switched capacitor low-pass filter circuit. The

switched capacitor filter response tracks with the sampling

frequency of the D/A converter and provides attenuation of

the out-of-band noise produced by the delta-sigma

modulator. An external two-pole continuous time filter is

V

_REF4− (pin 33) correspond to Channel 4.

The high reference (+) pin may be connected to the

corresponding V_CCsupply or an external +5.0V reference,

while the low reference (−) pin is connected to analog

ground. A 0.01µF bypass capacitor should be placed

14

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SBAS291C − AUGUST 2003 − REVISED DECEMBER 2004

between the corresponding high and low reference pins.

An X7R ceramic chip capacitor is recommended for this

purpose. In some cases, a larger capacitor may need to be

placed in parallel with the 0.01µF capacitor, with the value

of the larger capacitor being dependent upon the

low-frequency power-supply noise present in the system.

Typical values may range from 1µF to 10µF. Low ESR

tantalum or multilayer ceramic chip capacitors are

recommended. Figure 3 illustrates the recommended

connections for the reference pins.

SAMPLING MODES

The PCM4104 can operate in one of three sampling

modes: Single Rate, Dual Rate, or Quad Rate. Sampling

modes are selected by using the FS[1:0] bits in Control

Register 6 in Software mode, or by using the FS0 (pin 28)

and FS1 (pin 29) inputs in Standalone mode.

The Single Rate mode allows sampling frequencies up to

and including 54kHz. The D/A converter performs 128x

oversampling of the input data in Single Rate mode.

The Dual Rate mode allows sampling frequencies greater

than 54kHz, up to and including 108kHz. The D/A

converter performs 64x oversampling of the input data in

Dual Rate mode.

V_CC

(1)

V_REF

+

µ

µ µ

0.1 F to 10 F

0.01 F

(1)

−

V_REF

The Quad Rate mode allows sampling frequencies greater

than 108kHz, up to and including 216kHz. The D/A

converter performs 32x oversampling of the input data in

Quad Rate mode.

V_COM

1

Refer to Table 1 for examples of system clock

requirements for common sampling frequencies.

V_COM

2

µ

0.1 F

µ

0.1 F

SYSTEM CLOCK REQUIREMENTS

(1) Capacitor(s) required for each of the four reference pairs.

The PCM4104 requires a system clock, applied at the

SCKI (pin 14) input. The system clock operates at an

integer multiple of the input sampling frequency, or f_S. The

multiples supported include 128f_S, 192f_S, 256f_S, 384f_S,

512f_S, or 768f_S. The system clock frequency is dependent

upon the sampling mode. Table 1 shows the required

system clock frequencies for common audio sampling

frequencies. Figure 4 shows the system clock timing

requirements.

Figure 3. Recommended Connections for Voltage

Reference and Common-Mode Output Pins

In addition to the reference pins, there are two

common-mode voltage output pins, V_COM1 (pin 48) and

_COM2 (pin 37). These pins are nominally set to a value

equal to V_CC/2 by internal voltage dividers. The V_COM1 pin

is common to both Channels 1 and 2, while the V_COM2 pin

is common to Channels 3 and 4. A 0.1µF X7R ceramic chip

capacitor should be connected between the

common-mode output pin and analog ground. The

common-mode outputs are used primarily to bias external

output circuitry.

V

Although the architecture of the PCM4104 is tolerant to

phase jitter on the system clock, it is recommended that

the user provide a low jitter clock (100 picoseconds or less)

for optimal performance.

Table 1. Sampling Modes and System Clock Frequencies for Common Audio Sampling Rates

SAMPLING MODE

SAMPLING FREQUENCY, f

(kHz)

SYSTEM CLOCK FREQUENCY (MHz)

192f 256f 384f 512f

S

128f

768f

S

Single Rate

Dual Rate

Quad Rate

32

44.1

48

n/a

8.192

11.2896

12.288

22.5792

24.576

n/a

12.288

16.9344

18.432

33.8688

36.864

n/a

16.384

22.5792

24.576

n/a

24.576

33.8688

36.864

n/a

88.2

96

n/a

176.4

192

22.5792

24.576

33.8688

36.864

n/a

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SBAS291C − AUGUST 2003 − REVISED DECEMBER 2004

t

SCKIH

SCKI

t

SCKI

SCKIL

DESCRIPTION

PARAMETER

t_SCKI

MIN

26

MAX

UNITS

ns

System Clock Period

t_SCKIH

System Clock High Pulse Time

System Clock Low Pulse Time

12

ns

t_SCKIL

12

ns

Figure 4. System Clock Timing Requirements

Standalone and Software modes, the analog outputs for all

four channels are muted during the reset and initialization

sequence. While in mute state, the analog output pins are

driven to the bipolar zero voltage, or V_CC/2.

RESET OPERATION

The PCM4104 includes three reset functions: power-on,

external, and software-controlled. This section describes

each of the three reset functions.

The user may force a reset initialization sequence at any

time while the system clock input is active by utilizing the

RST input (pin 9). The RST input is active low, and requires

a minimum low pulse width of 40 nanoseconds. The

low-to-high transition of the applied reset signal will force

an initialization sequence to begin. As in the case of the

power-on reset, the initialization sequence requires 1024

system clock periods for completion. Figure 6 illustrates

the reset sequence initiated when using the RST input.

On power up, the internal reset signal is forced low, forcing

the PCM4104 into a reset state. The power-on reset circuit

monitors the V_DD, V_CC1, and V_CC2 power supplies. When

V

_DDexceeds +2.0V (margin of error is 400mV) and V_CC1

and V_CC2 exceed +4.0V (margin of error is 400mV), the

internal reset signal is forced high. The PCM4104 then

waits for the system clock input (SCKI) to become active.

Once the system clock has been detected, the initialization

sequence begins. The initialization sequence requires

1024 system clock periods for completion. When the

initialization sequence is completed, the PCM4104 is

ready to accept audio data at the audio serial port. Figure 5

shows the power-on reset sequence timing.

A reset initialization sequence is available in Software

mode, using the RST bit in Control Register 6_.The RST bit

is active high. When RST is set to 1, a reset sequence is

initiated in the same fashion as an external reset applied

at the RST input.

If the PCM4104 is configured for Software mode control

via the SPI port, all control registers will be reset to their

default state during the initialization sequence. In both

Figure 7 shows the state of the analog outputs for the

PCM4104 before, during and after the reset operations.

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SBAS291C − AUGUST 2003 − REVISED DECEMBER 2004

~ 4.0V

0V

V_CC

1

V_CC2

~ 2.0V

0V

V_DD

Internal

Reset

1024 System Clock Periods

Required for Initialization

0V

SCKI

System Clock

Indeterminate

or Inactive

Figure 5. Power-Up Reset Timing

t

_RSTL> 40ns

RST

0V

1024 System Clock Periods

Required for Initialization

Internal

Reset

SCKI

0V

Figure 6. External Reset Timing

HI

Internal

Reset

LO

Analog

Outputs

Outputs are Muted

for 1024 SCKI Periods

Outputs are On

Outputs are Muted

Outputs are On

Initialization

Period

Figure 7. Analog Output State for Reset Operations

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This allows the user to conserve power when a channel

pair is not in use. The power-down function is the same as

described in the previous paragraph for the corresponding

channel pair. Unlike the power-down function

implemented using the RST input, setting a power-down

bit will immediately power down the corresponding

channel pair.

POWER-DOWN OPERATION

The PCM4104 can be forced to a power-down state by

applying a low level to the RST input for a minimum of

65,536 system clock cycles. In power-down mode, all

internal clocks are stopped, and analog outputs are set to

a high-impedance state. The system clock can then be

removed to conserve additional power. In the case of

system clock restart when exiting the power-down state,

the clock should be restarted prior to a low-to-high

transition of the reset signal at the RST input. The

low-to-high transition of the reset signal initiates a reset

sequence, as described in the Reset Operation section of

this data sheet.

When exiting power-down mode, either by forcing the RST

input high or by setting the PDN12 or PDN34 bits low, the

analog outputs will transition from the high-impedance

state to the mute state, with the output level set to the

bipolar zero voltage. There may be a small transient

created by this transition, since internal capacitor charge

can initially force the output to a voltage above or below

bipolar zero, or external circuitry can pull the outputs to

some other voltage level. Figure 8 illustrates the state of

the analog outputs before, during, and after a power-down

event.

In Software mode, two additional power-down controls are

provided. The PDN12 and PDN34 bits are located in

Control Register 6 and may be used to power-down

channel pairs, with PDN12 corresponding to channels 1

and 2, and PDN34 corresponding to channels 3 and 4.

V_DD

RST

0V

Outputs Transition

from High Impedance

to Muted State

Outputs are

High Impedance

Analog

Outputs

Outputs are

Muted

Outputs are On

1024

65,536

SCKI Periods

Required for

Initialization

SCKI Periods

HI

PDN12

PDN34

LO

Outputs Transition

from High Impedance

to Muted State

Outputs are

High Impedance

Analog

Outputs

Outputs are On

Transitioning

to Driven State

1024

SCKI Periods

Required for

Initialization

Figure 8. Analog Output State for Power-Down Operations

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The DATA0 and DATA1 pins are the audio data inputs.

When using Left Justified, Right Justified, or I²S data

formats, the DATA0 pin carries the audio data for channels

1 and 2, while the DATA1 pin carries the audio data for

channels 3 and 4. When using TDM data formats, DATA0

carries the audio data for all four channels, while the

DATA1 input is ignored.

AUDIO SERIAL PORT

The audio serial port provides a common interface to

digital signal processors, digital interface receivers (AES3,

S/PDIF), and other digital audio devices. The port

operates as a slave to the processor, receiver, or other

clock generation circuitry. Figure 9 illustrates a typical

audio serial port connection to a processor or receiver. The

audio serial port is comprised of four signal pins: BCK (pin

15), LRCK (pin 16), DATA0 (pin 17), and DATA1 (pin 18).

The audio serial port data formats are shown in Figure 10,

Figure 13, and Figure 14. Data formats are selected by

using the FMT[2:0] bits in Control Register 7 in Software

mode, or by using the FMT0 (pin 25), FMT1 (pin 26), and

FMT2 (pin 27) inputs in Standalone mode. In Software

mode, the user may also select the phase (normal or

inverted) for the LRCK input, as well as the data sampling

edge for the BCK input (either rising or falling edge). The

reset default conditions for the Software mode are normal

phase for LRCK and rising edge data sampling for BCK.

DSP

FSX

PCM4104

LRCK

CLKX

DX0

BCK

DATA0

DATA1

DX1

SCKI

The Left Justified, Right Justified, and I²S data formats are

similar to one another, with differences in data justification

and word length. The PCM audio data must be two’s

complement binary, MSB first. Figure 10 provides

illustrations for these data formats.

System Clock

The TDM formats carry the information for four or eight

channels on a single data line. The DATA0 input (pin 17)

is used as the data input for the TDM formats. The data is

carried in a time division multiplexed fashion; hence, the

TDM acronym used to describe this format. Figure 12

shows the TDM connection of two PCM4104 devices. The

data for each channel is assigned one of the time slots in

the TDM frame, as shown in Figure 13 and Figure 14. The

sub−frame assignment for each PCM4104 is determined

by the state of the SUB input (pin 13). When SUB is forced

low, the device is assigned to sub-frame 0. When SUB is

forced high, the device is assigned to sub-frame 1.

Figure 9. Audio Serial Port Connections for Left

2

Justified, Right Justified, and I S Formats.

The LRCK pin functions as either the left/right word clock

or the frame synchronization clock, depending upon the

data format selected. The LRCK frequency is equal to the

input sampling frequency (44.1kHz, 48kHz, 96kHz, etc.).

The BCK pin functions as the serial data clock input. This

input is referred to as the bit clock. The bit clock runs at an

integer multiple of the input sampling frequency. Typical

multiples include 32, 48, 64, 96, 128, 192, and 256,

depending upon the data format, word length, and system

clock frequency selected.

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SBAS291C − AUGUST 2003 − REVISED DECEMBER 2004

Ch. 1 (DATA0) or Ch. 3 (DATA1)

Ch. 2 (DATA0) or Ch. 4 (DATA1)

LRCK

BCK

MSB

LSB

MSB

LSB

DATA0

DATA1

(a) Left−Justified Data Format

LRCK

BCK

DATA0

DATA1

MSB

LSB

MSB

LSB

(b) Right−Justified Data Format

LRCK

BCK

M S B

LSB

MSB

LSB

DATA0

DATA1

(c) I²S Data Format

1/f_S

2

Figure 10. Left Justified, Right Justified, and I S Data Formats

LRCK

t_LRBKD

t_BKLRD

BCK

(BCKE = 0)

t_BCKP

t_BCKHL

BCK

(BCKE = 1)

DATA0

DATA1

t_DS

t_DH

DESCRIPTION

M IN

MAX

UNITS

PARAM ETER

t_BCKP

t_BCKHL

t_LRBKD

t_BKLRD

t_DS

BCK Cycle Time

70

30

10

ns

BCK High/Low Time

LRCK Edge to BCK Sampling Edge Delay

BCK Sampling Edge to LRCK Edge Delay

Data Setup Time

Data Hold Time

LRCK Duty Cycle

10

50

ns

%

t_DH

−

2

Figure 11. Audio Serial Port Timing for Left Justified, Right Justified, and I S Data Formats.

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Device #1

(Sub−Frame 0)

DSP

FSX

PCM4104

LRCK

CLKX

DX

BCK

DATA0

SCKI

SUB

Device #2

(Sub−Frame 1)

PCM4104

LRCK

BCK

DATA0

SUB

SCKI

V_CC

System Clock

Figure 12. TDM Connection

−

TDM Data Formats Long Frame

Supported for Single and Dual Rate Sampling Modes Only

LRCK

Normal, Zero BCK Delay

LRCK

Normal, One BCK Delay

LRCK

Inverted, Zero BCK Delay

LRCK

Inverted, One BCK Delay

DATA0

Supports 8 Channels, or

two PCM4104 devices.

Slot 1

Ch. 1

Slot 2

Ch. 2

Slot 3

Ch. 3

Slot 4

Ch. 4

Slot 5

Ch. 1

Slot 6

Ch. 2

Slot 7

Ch. 3

Slot 8

Ch. 4

Sub−Frame 0

(SUB = 0)

Sub−Frame 1

(SUB = 1)

One Frame

BCK = 192f_Sor 256f_S

In the case of BCK = 192f_S, each time slot is 24 bits long and contains the 24−bit audio data for the corresponding channel.

In the case of BCK = 256f_S, each time slot is 32 bits long and contains the 24−bit audio data for the corresponding channel.

The audio data is left justified in the time slot, with the the least significant 8 bits of each time slot being don’t care bits.

Audio data is always presented in two’s complement, MSB−first format.

Figure 13. TDM Data Formats: Long Frame

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−

TDM Data Formats Short Frame

All Sampling Modes Supported

LRCK

Normal, Zero BCK Delay

LRCK

Normal, One BCK Delay

LRCK

Inverted, Zero BCK Delay

LRCK

Inverted, One BCK Delay

DATA0

Supports 4 Channels, or

one PCM4104 device.

Slot 1

Ch. 1

Slot 2

Ch. 2

Slot 3

Ch. 3

Slot 4

Ch. 4

One Frame

BCK = 96f_Sor 128f_S

(the SUB pin is ignored when using a Short Frame)

In the case of BCK = 96f_S, each time slot is 24 bits long and contains the 24−bit audio data for the corresponding channel.

In the case of BCK = 128f_S, each time slot is 32 bits long and contains the 24−bit audio data for the corresponding channel.

The audio data is left justified in the time slot, with the the least significant 8 bits of each time slot being don’t care bits.

Audio data is always presented in two’s complement, MSB−first format.

Figure 14. TDM Data Formats: Short Frame

One Frame

t_LRCKP

t_BNF

LRCK

t_BKBF

t_LRBKD

BCK

(BCKE = 0)

BCK

(BCKE = 1)

DATA0

t_DS

t_DH

DESCRIPTION

MIN

1/f_BCK

12

MAX

UNITS

PARAMETER

t_LRCKP

t_LRBKD

t_DS

ns

LRCK pulse width

LRCK active edge to BCK sampling edge delay

Data setup time

10

t_DH

10

Data hold time

1/f_BCK

t_BNF

LRCK transition before new frame

BCK sampling edge to new frame delay

t_BKBF

12

Figure 15. TDM Timing

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SBAS291C − AUGUST 2003 − REVISED DECEMBER 2004

STANDALONE MODE CONFIGURATION

Soft Mute Function

The MUTE input (pin 10) may be used in either the

Standalone or Software modes to simultaneously mute the

four output channels. The soft mute function slowly ramps

the digital output attenuation from its current setting to the

mute level, minimizing or eliminating audible artifacts.

Table 4 summarizes MUTE function operation.

Standalone mode is selected by forcing the MODE input

(pin 8) low. Standalone mode operation provides a subset

of the functions available in Software mode, while

providing an option for a simplified control model.

Standalone configuration is accomplished by either

hardwiring or driving a small set of input pins with external

logic or switches. Standalone mode functions include

sampling mode and audio data format selection, an

all-channel soft mute function, and digital de-emphasis

filtering. The following paragraphs provide a brief

description of each function available when using

Standalone mode.

Table 4. Mute Function Configuration

MUTE

ANALOG OUTPUTS

On (mute disabled)

Muted

0

1

Sampling Mode

Digital De-Emphasis

The sampling mode is selected using the FS0 (pin 28) and

FS1 (pin 29) inputs. A more detailed discussion of the

sampling modes was provided in an earlier section of this

data sheet. Table 2 summarizes the sampling mode

configuration for Standalone mode.

This is a global digital function (common to all four

channels) and provides de-emphasis of the higher

frequency content within the 20kHz audio band.

De-emphasis is required when the input audio data has

been pre-emphasized. Pre-emphasis entails increasing

the amplitude of the higher frequency components in the

20kHz audio band using a standardized filter function in

order to enhance the high-frequency response. The

PCM4104 de-emphasis filters implement the standard

50/15µs de-emphasis transfer function commonly used in

digital audio applications.

Table 2. Sampling Mode Configuration

FS1

0

FS0

0

SAMPLING MODE

Single Rate

0

1

Dual Rate

1

0

Quad Rate

De-emphasis filtering is available for three input sampling

frequencies in Single Rate sampling mode: 32kHz,

44.1kHz, and 48kHz. De-emphasis is not available when

operating in Dual or Quad Rate sampling modes. The

de-emphasis filter is selected using the DEM0 (pin 12) and

DEM1 (pin 11) inputs. Table 5 illustrates the de-emphasis

filter configuration for Standalone mode.

1

− Not Used −

Audio Data Format

The audio data format is selected using the FMT0 (pin 25),

FMT1 (pin 26), and FMT2 (pin 27) inputs. A detailed

discussion of the audio serial port operation and the

corresponding data formats was provided in the Audio

Serial Port section on page 19. For Standalone mode, the

LRCK polarity is always normal, while the serial audio data

is always sampled on the rising edge of the BCK clock.

Table 3 shows the audio data format configuration for

Standalone mode.

Table 5. Digital De-Emphasis Configuration

DEM1

DEM0

DIGITAL DE-EMPHASIS MODE

0

1

0

1

0

1

Off (de-emphasis disabled)

48kHz

44.1kHz

32kHz

Table 3. Audio Data Format Configuration

FMT2

FMT1

FMT0

AUDIO DATA FORMAT

0

1

0

1

0

1

0

1

0

1

0

1

0

1

24-bit left justified

2

24-bit I S

TDM with zero BCK delay

TDM with one BCK delay

24-bit right justified

20-bit right justified

18-bit right justified

16-bit right justified

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SOFTWARE MODE CONFIGURATION

Output Phase Reversal

The PCM4104 includes an output phase reversal function,

which provides the ability to invert the output phase for all

four channels, either for testing or for matching various

output circuit configurations. This function is controlled

using the PHASE bit, located within Control Register 5.

The output phase is set to noninverted by default on power

up or reset.

Software mode is selected by forcing the MODE input

(pin 8) high. Software mode operation provides full access

to the features of the PCM4104 by allowing the writing and

reading of on-chip control registers. This is accomplished

using the four-wire SPI port. The following paragraphs

provide a brief description of each function available when

using Software mode.

Sampling Mode

Digital Attenuation

Sampling mode configuration was discussed earlier in this

data sheet, with Table 1 providing a reference for common

sampling and system clock frequencies. The FS0 and FS1

bits located in Control Register 6 are used to set the

sampling mode. The sampling mode defaults to Single

Rate on power up or reset.

The audio signal for each channel can be attenuated in the

digital domain using this function. Attenuation settings

from 0dB (unity gain) to −119.5dB are provided in 0.5dB

steps. In addition, the attenuation level may be set to the

mute state. The rate of change for the digital attenuation

function is one 0.5dB step for every eight LRCK periods.

Each channel has its own independent attenuation control,

accessed using control registers 1 through 4. The reset

default setting for all channels is 0dB, or unity gain (no

attenuation applied).

Power-Down Modes

The power-down control bits are located in Control

Register 6. These bits are used to power down pairs of D/A

converters within the PCM4104. The PDN12 bit is used to

power down channels 1 and 2, while the PDN34 bit is used

to power down channels 3 and 4. When a channel pair is

powered down, it ignores the audio data inputs and sets its

outputs to a high-impedance state. By default, the

power-down bits are disabled on power up or reset.

Digital De-Emphasis

The de-emphasis function is accessed through Control

Register 5 using the DEM[1:0] bits. The reset default

setting is that the de-emphasis is disabled for all four

channels. De-emphasis filter operation is described in the

Standalone Mode Configuration section of this data sheet.

Software Reset

Soft Mute

This reset function allows a reset sequence to be initiated

under software control. All control registers are reset to

their default state. The reset bit, RST, is located in Control

Register 6. Setting this bit to 1 initiates a one-time reset

sequence. The RST bit is cleared by the initialization

sequence.

Each of the four D/A converter channels has its own

independent soft mute control, located in Control Register

5.

The reset default is normal output for all four channels with

the soft mute function disabled. The MUTE input (pin 10)

also functions in Software mode, with a high input forcing

soft mute on all four channels.

Audio Data Formats, LRCK Polarity, and BCK

Sampling Edge

Control Register 7 is used to configure the PCM4104 audio

serial port. Audio serial port operation was discussed

previously in this data sheet; refer to that section for more

details regarding the functions controlled by this register.

The control register definitions provide additional

information regarding the register functions and their

default settings.

Zero Data Mute

The PCM4104 includes a zero data detection and mute

function in Software mode. This function automatically

mutes a given channel when 1024 consecutive LRCK

periods of all zero data are detected for that channel. The

zero data mute function is enabled and disabled using the

ZDM bit in Control Register 5. The zero data mute function

is disabled by default on power up or reset.

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automatically incremented by 1, so the next write or read

operation is performed without issuing another control

byte, as shown in Figure 17.

SERIAL PERIPHERAL INTERFACE (SPI) PORT

OPERATION

The SPI port is a four-wire synchronous serial interface

that is used to access the on-chip control registers when

the PCM4104 is configured for Software mode operation.

The CDIN input (pin 23) is the serial data input for the port,

while CDOUT (pin 24) is used for reading back control

register contents in a serial fashion. The CS input (pin 21)

functions as the chip select input, and must be forced low

for register write or read access. The CCLK input (pin 22)

functions as the serial data clock, used to clock data in and

out of the port. Data is clocked into the port on the rising

edge of CCLK, while data is clocked out of the port on the

falling edge of CCLK.

Control Byte (or Byte 0)

The control byte, or byte 0, is the first byte written to the

PCM4104 SPI port when performing a write or read

operation. The control byte includes bits that define the

operation to be performed (read or write), the

auto-increment mode status, and the control register

address.

The Read/Write bit, R/W, is set to 0 to indicate a register

write operation, or set to 1 for a register read operation.

The Increment bit, INC, enables or disables the

Auto-Increment mode of operation. When this bit is set to

a 0, auto-increment operation is disabled, and the

operation performed is either Single Register or

There are three modes of operation supported for the SPI

port: Single Register, Continuous, and Auto-Increment.

The Single Register and Continuous modes are similar to

one another. In Continuous mode, instead of bringing the

CS input high after writing or reading a single register, the

CS input is held low and a new control byte is issued with

a new address for the next write or read operation.

Continuous mode allows multiple, sequential or

nonsequential register addresses to be read or written in

succession, as shown in Figure 16.

Continuous. Setting the INC bit to

Auto-Increment operation.

1

enables

A two-bit key code, 10_B, follows the INC bit and must be

present in order for any operation to take place on the

control port. Any other combination for these bits will result

in the port ignoring the write or read request.

The four-bit address field, A[3:0], is used to specify the

control register address for the read or write operation, or

the starting address for an Auto-Increment write or read

operation.

Auto-Increment mode is designed for writing or reading

multiple sequential register addresses. After the first

register is written or read, the register address is

Set CS = 1 here for Single Register Operations

CS

Keep CS = 0 for writing or reading multiple registers in Continuous mode

Control Byte

byte 0

Register Data

byte 1

Control Byte

byte 0

Register Data

byte 1

byte N

CDIN

Register Data

byte 1

Register Data

byte 2

High Impedance

CDOUT

CCLK

Control Byte Definition (Byte 0)

MSB

LSB

R/W INC

1

0

A3 A2 A1 A0

Register Address

Auto −Increment Control: Set to 0 for Single Register or Continuous Operation

Read/WriteControl: 0 = Write

1 = Read

Figure 16. Single Register and Continuous Write or Read Operation

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Keep CS = 0 for Auto−Increment Operation

CS

Control Byte

byte 0

Register Data

byte 1

Register Data

byte 1

byte N

byte 2

byte 3

CDIN

High Impedance

CDOUT

CCLK

Control Byte Definition (Byte 0)

MSB

LSB

R/W INC

1

0

A3 A2 A1 A0

Register Address

Auto−Increment Control: Set to 1 for Auto−Increment Operation

Read/WriteControl: 0 = Write

1 = Read

Figure 17. Auto-Increment Write or Read Operation

t_DS

t_DH

t_CH

CS

CCLK

CDIN

MSB

CDOUT

LSB

High Impedance (Hi Z)

MSB

Hi Z

t_DO

t_CSZ

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

5

t_DS

CDIN Data Setup Time

ns

2

t_DH

t_CH

t_DO

t_CSZ

CDIN Data Hold Time

ns

Hold Time

CS

CDOUT Data Delay Time

High to CDOUT Hi Z

5

CS

Figure 18. SPI Port Timing

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CONTROL REGISTER DEFINITIONS (SOFTWARE MODE ONLY)

The PCM4104 includes a small set of control registers, which are utilized to configure the full set of on-chip functions in

Software mode. The register map is shown in Table 6. Register 0 is reserved for factory use and should not be written to

for normal operation. Register 0 defaults to all zero data on power up or reset.

Table 6. Control Register Map

CONTROL REGISTER ADDRESS

(HEX)

MSB

BIT 7

LSB

BIT 0

BIT 6

0

BIT 5

0

BIT 4

0

BIT 3

0

BIT 2

0

BIT 1

0

1

2

3

4

5

6

7

0

AT17

AT27

AT37

AT47

MUT4

RST

0

AT16

AT26

AT36

AT46

MUT3

0

AT15

AT25

AT35

AT45

MUT2

0

AT14

AT24

AT34

AT44

MUT1

0

AT13

AT23

AT33

AT43

ZDM

PDN34

0

AT12

AT22

AT32

AT42

PHASE

PDN12

FMT2

AT11

AT21

AT31

AT41

DEM1

FS1

AT10

AT20

AT30

AT40

DEM0

FS0

0

BCKE

LRCKP

FMT1

FMT0

Register 1: Attenuation Control Register − Channel 1

BIT 7 (MSB)

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0 (LSB)

AT17

AT16

AT15

AT14

AT13

AT12

AT11

AT10

This register controls the digital output attenuation for Channel 1.

Default: AT1[7:0] = 255, or 0dB

Let N = AT1[7:0].

For N = 16 to 255, Attenuation (dB) = 0.5 x (255 – N)

For N = 0 to 15, Attenuation (dB) = Infinite (Muted)

Register 2: Attenuation Control Register – Channel 2

BIT 7 (MSB)

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0 (LSB)

AT27

AT26

AT25

AT24

AT23

AT22

AT21

AT20

This register controls the digital output attenuation for Channel 2.

Default: AT2[7:0] = 255, or 0dB

Let N = AT2[7:0].

For N = 16 to 255, Attenuation (dB) = 0.5 x (255 – N)

For N = 0 to 15, Attenuation (dB) = Infinite (Muted)

Register 3: Attenuation Control Register – Channel 3

BIT 7 (MSB)

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0 (LSB)

AT37

AT36

AT35

AT34

AT33

AT32

AT31

AT30

This register controls the digital output attenuation for Channel 3.

Default: AT3[7:0] = 255, or 0dB

Let N = AT3[7:0].

For N = 16 to 255, Attenuation (dB) = 0.5 x (255 – N)

For N = 0 to 15, Attenuation (dB) = Infinite (Muted)

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Register 4: Attenuation Control Register – Channel 4

BIT 7 (MSB)

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0 (LSB)

AT47

AT46

AT45

AT44

AT43

AT42

AT41

AT40

This register controls the digital output attenuation for Channel 4.

Default: AT4[7:0] = 255, or 0dB

Let N = AT4[7:0].

For N = 16 to 255, Attenuation (dB) = 0.5 x (255 – N)

For N = 0 to 15, Attenuation (dB) = Infinite (Muted)

Register 5: Function Control Register

BIT 7 (MSB)

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0 (LSB)

MUT4

MUT3

MUT2

MUT1

ZDM

PHASE

DEM1

DEM0

This register controls various D/A converter functions, including de-emphasis filtering, output phase reversal, zero data

mute, and per-channel soft muting.

DEM[1:0]

Digital De-Emphasis

De-emphasis is available for Single Rate mode only.

De-emphasis is disabled for Dual and Quad Rate modes.

DEM1

DEM0 De-Emphasis Selection

0

1

0

1

0

1

De-emphasis disabled (default)

De-emphasis for f_S= 48kHz

De-emphasis for f_S= 44.1kHz

De-emphasis for f_S= 32kHz

PHASE

ZDM

Output Phase

PHASE

Output Phase

0

1

Noninverted (default)

Inverted

Zero Data Mute

ZDM

Zero Mute

0

1

Disabled (default)

Enabled

MUT[4:1]

Soft Mute

MUTx

D/A Converter Output

On (default)

0

1

Muted

NOTE: x = channel number.

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Register 6: System Control Register

BIT 7 (MSB)

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0 (LSB)

RST

0

PDN34

PDN12

FS1

FS0

This register controls various system level functions of the PCM4104, including sampling mode, power down, and soft

reset.

FS[1:0]

Sampling Mode

FS1

0

FS0

0

Sampling Mode

Single Rate (default)

Dual Rate

0

1

0

Quad Rate

1

− Not Used −

PDN12

PDN34

RST

Power-Down for Channels 1 and 2

PDN12

Power Down for Channels 1 and 2

0

1

Disabled (default)

Enabled

Power Down for Channels 3 and 4

PDN34

Power Down for Channels 3 and 4

0

1

Disabled (default)

Enabled

Software Reset (value defaults to 0)

Setting this bit to 1 will initiate a logic reset of the PCM4104. This bit functions the same as an external reset

applied at the RST input (pin 9).

Register 7: Audio Serial Port Control Register

BIT 7 (MSB)

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0 (LSB)

0

BCKE

LRCKP

0

FMT2

FMT1

FMT0

This register is used to control the data format and clock polarity for the PCM4104 audio serial port.

FMT[2:0]

Audio Data Format

FMT2 FMT1 DEM0 Data Format

0

1

0

1

0

1

0

1

0

1

0

1

0

1

24-bit left justified (default)

24-bit I²S

TDM with zero BCK delay

TDM with one BCK delay

24-bit right justified

20-bit right justified

18-bit right justified

16-bit right justified

LRCKP

BCKE

LRCK Polarity (0 = Normal, 1 = Inverted). Defaults to 0.

BCK Sampling Edge (0 = Rising Edge, 1 = Falling Edge), Defaults to 0.

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APPLICATIONS INFORMATION

This section provides practical information for system and

hardware engineers that are designing in the PCM4104.

The configuration of the output filter circuit is dependent

upon whether a single-ended or differential output is

required. Single-ended outputs are commonly used in

consumer playback systems, while differential or balanced

outputs are used in many professional audio applications,

such as recording or broadcast studios and live sound

systems.

BASIC CIRCUIT CONFIGURATIONS

Figure 19 and Figure 20 show typical circuit configurations

for the PCM4104 operated in Standalone and Software

modes. Power supply bypass and reference decoupling

capacitors should be placed as close to the corresponding

PCM4104 pins as possible. A common ground is shown in

both figures, with the analog and digital ground pins

connected to a common plane. Separate power supplies

are utilized for the analog and digital sections, with +5V

required for the PCM4104 analog supplies and +3.3V

required for the digital supply.

Figure 21 illustrates an active filter circuit that uses a single

op amp to provide both 2nd-order low-pass filtering and

differential to single-ended signal conversion. This circuit

is used on the PCM4104EVM evaluation circuit and meets

the published typical Electrical Characteristics for dynamic

performance. The single-ended output is convenient for

connecting to both headphone and power amplifiers when

used for listening tests.

The +5V analog supply may be derived from a higher

valued, positive analog power supply using a linear

voltage regulator, such as the REG103 available from

Texas Instruments. The +3.3V digital supply can be

derived from a primary +5V digital supply using a linear

voltage regulator, such as the REG1117, also from TI. The

PCM4104EVM evaluation module provides an example of

how the common ground with separate supply approach

can be successfully implemented. The PCM4104EVM

User’s Guide includes schematics and PCB layout plots

for reference. The evaluation module is available through

Texas Instruments’ distributors and sales representatives,

or may be ordered online through the TI eStore, which can

be accessed through the TI home page at

http://www.ti.com.

The quality of the op amp used is this circuit is important,

as many devices will degrade the dynamic range and/or

total harmonic distortion plus noise (THD+N)

specifications for the PCM4104. An NE5534A is shown in

Figure 21 and provides both low noise and distortion.

Bipolar input op amps with equivalent specifications

should produce similar measurement results. Devices that

exhibit higher equivalent input noise voltage, such as the

Texas Instruments OPA134 or OPA604 families, will

produce

lower

dynamic

range

measurements

(approximately 1dB to 2dB lower than the typical

PCM4104 specification), while having little or no impact on

the THD+N specification when measuring a full-scale

output level.

Figure 22 illustrates a fully-differential output filter circuit

suitable for use with the PCM4104. The OPA1632 from

Texas Instruments provides the fully differential signal path

in this circuit. The OPA1632 features very low noise and

distortion, making it suitable for high-end audio

applications.

The master clock generator supplies the system clock for

the PCM4104, as well as the audio data source, such as

a digital signal processor. The LRCK and BCK audio

clocks should be derived from the system clock, in order

to ensure synchronous operation.

Texas Instruments provides a free software tool,

FilterProt, used to assist in the design of active filter

circuits. The software supports design of multiple

feedback (MFB), Sallen-Key, and fully differential filter

circuits. FilterPro is available from the TI web site.

Additionally, TI document number SBAF001A, also

available from the TI web site, provides pertinent

application information regarding the proper usage of the

FilterPro program.

ANALOG OUTPUT FILTER CIRCUITS

An external output filter is recommended for each

differential output pair. The external output filter further

reduces the out-of-band noise energy produced by the

delta-sigma modulator, while providing band limiting

suitable for audio reproduction. A 2nd-order Butterworth

low-pass filter circuit with a −3dB corner frequency from

50kHz to 180kHz is recommended.

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To Analog Output Filters⁽¹⁾

(2)

48 47 46 45 44 43 42 41 40 39 38 37

V_OUT1+

V_OUT4+

1

2

36

35

34

33

32

31

30

29

28

27

26

25

−

_OUT1

−

V_OUT4

V

AGND1

AGND2

3

−

V_REF1

−

V

_REF4

4

(2)

V_REF1+

_REF4+

5

NC

6

PCM4104

NC

7

MODE

RST

FS1

8

FS0

9

From

Logic,

MUTE

DEM1

DEM0

FMT2

FMT1

FMT0

10

11

12

µ

P,

or DSP

From

Logic,

µ

P,

or DSP

13 14 15 16 17 18 19 20 21 22 23 24

+5.0V

+3.3V

Pin 40

Pin 45

Pin 19

Master

Clock

+

µ

10 F

0.1 F

10 F

0.1 F

µ

10 F

Audio Data Source

0.1 F

Generator

(1) Refer to Figure 21 and Figure 22 in this document.

(2) Refer to Figure 3 in this document for external connection requirements.

Figure 19. Typical Standalone Mode Configuration

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To Analog Output Filters⁽¹⁾

(2)

48 47 46 45 44 43 42 41 40 39 38 37

V_OUT1+

V_OUT4+

1

2

36

35

34

33

32

31

30

29

28

27

26

25

−

V_OUT1

−

V_OUT4

AGND1

AGND2

3

−

V_REF4

V

_REF1

_REF1+

NC

4

(2)

V

V_REF4+

5

NC

6

PCM4104

NC

7

MODE

RST

FS1

8

FS0

9

MUTE

DEM1

DEM0

FMT2

FMT1

FMT0

+3.3V

10

11

12

From

Logic or

Host Control

13 14 15 16 17 18 19 20 21 22 23 24

Master

Clock

Generator

Audio Data Source

Host Control

Pin 40

+5.0V

+3.3V

Pin 45

Pin 19

+

µ

10 F

0.1 F

10 F

0.1 F

µ

10 F

0.1 F

(1) Refer to Figure 21 and Figure 22 in this document.

(2) Refer to in this document for external connection requirements.

Figure 3

Figure 20. Typical Software Mode Configuration

32

ꢅ ꢜꢢ ꢐ ꢓꢣ ꢐ

www.ti.com

SBAS291C − AUGUST 2003 − REVISED DECEMBER 2004

Ω

1k

560pF

+12V

µ

10 F

+

µ

0.1 F

PCM4104

µ

100 F

Ω

604

499

2

3

7

+

−

VOUTn

Ω

100

NE5534A

22pF

2200pF

µ

100 F

Filtered

Output

Ω

604

499

6

+

VOUTn+

4

µ

0.1 F

RCA or 1/4−inch

Phone Jack

Ω

1k

560pF

µ

10 F

n = 1, 2, 3, or 4

+

−

12V

Figure 21. Single-Ended Output Filter Circuit

Ω

1k

560pF

−

15V

µ

10 F

+

µ

0.1 F

Filtered

Output

PCM4104

6

7

µ

100 F

Ω

604

499

Ω

100

8

3

5

4

+

VOUTn+

EN

1

OPA1632

22pF

2200pF

100

µ

100 F

Ω

604

499

1

+

V_OCM

−

VOUTn

2

3

Male XLR

Connector

µ

10 F

n = 1, 2, 3, or 4

µ

0.1 F

+

+15V

560pF

Ω

1k

Figure 22. Differential Output Filter Circuit

33

PACKAGE MATERIALS INFORMATION

www.ti.com

24-Jul-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

PCM4104PFBR

PCM4104PFBT

TQFP

PFB

48

2000

250

330.0

177.8

16.8

16.4

9.6

1.5

12.0

16.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

24-Jul-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

PCM4104PFBR

PCM4104PFBT

TQFP

PFB

48

2000

250

367.0

210.0

367.0

185.0

38.0

35.0

Pack Materials-Page 2

MECHANICAL DATA

MTQF019A – JANUARY 1995 – REVISED JANUARY 1998

PFB (S-PQFP-G48)

PLASTIC QUAD FLATPACK

0,27

0,17

0,50

M

0,08

36

25

37

24

48

13

0,13 NOM

1

12

5,50 TYP

7,20

SQ

Gage Plane

6,80

9,20

SQ

8,80

0,25

0,05 MIN

0°–7°

1,05

0,95

0,75

0,45

Seating Plane

0,08

1,20 MAX

4073176/B 10/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

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型号：	PCM4104
厂家：	TEXAS INSTRUMENTS
描述：	SNR 为 118dB 的 4 通道音频 DAC 转换器数模转换器
文件：	总40页 (文件大小：1122K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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