PCM4204 [TI]
118dB SNR 4 通道音频 ADC;
| 型号： | PCM4204 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 118dB SNR 4 通道音频 ADC |
| 文件： | 总39页 (文件大小：1193K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SBAS327A − JUNE 2004 − REVISED SEPTEMBER 2004
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FEATURES
APPLICATIONS
D
Four High-Performance Delta-Sigma
Analog-to-Digital Converters
− 24-Bit Linear PCM or 1-Bit Direct Stream
Digital (DSD) Output Data
− Supports PCM Output Sampling Rates up
to 216kHz
D
D
D
D
D
Digital Recorders and Mixing Desks
Digital Audio Effects Processors
Broadcast Studio Equipment
Surround Sound Encoders
High-End A/V Receivers
− Supports 64f and 128f DSD Output Data
S
S
DESCRIPTION
Rates
D
D
D
Dynamic Performance: PCM Output
− Dynamic Range: 118dB
− THD+N: −105dB
Dynamic Performance: DSD Output
− Dynamic Range: 115dB
− THD+N: −103dB
The PCM4204 is a high-performance, four-channel
analog-to-digital (A/D) converter designed for professional
and broadcast audio applications. The PCM4204
architecture utilizes a 1-bit delta-sigma modulator per
channel incorporating a novel density modulated dither
scheme for improved dynamic performance.
Audio Serial Port
The PCM4204 supports 24-bit linear PCM output data,
with sampling frequencies up to 216kHz. The PCM4204
can also be configured to output either 64x or 128x
oversampled, 1-bit direct stream digital (DSD) data for
each channel. In addition, the PCM4204 supports a DSD
input mode, allowing 1-bit DSD to 24-bit PCM data format
conversion utilizing the on-chip digital decimation filter.
These features make the PCM4204 suitable for a variety
of digital audio recording and processing applications.
− 24-Bit Linear PCM Output Data
− Master or Slave Mode Operation
− Supports Left-Justified, Right-Justified,
2
I S, and TDM Data Formats
D
D
DSD Data Port
− Supports DSD Output or Input for All Four
Channels Simultaneously
− Input Mode Provides 1-Bit DSD to 24-Bit
PCM Data Format Conversion
Additional PCM Output Features
− Linear-Phase Digital Decimation Filter
− Digital High-Pass Filter for DC Removal
− Clipping Flag Output for Each Channel
Power Supplies: +5V Analog and +3.3V Digital
Power Dissipation:
The PCM4204 includes a flexible audio serial port inter-
face, which supports standard PCM audio data formats, as
well as time division multiplexed (TDM) PCM data formats.
Multiple format support allows the system designer to
choose the interface format that best suits the end applica-
tion. Audio data format selection, sampling mode configu-
ration, and high-pass filter functions are all programmed
using dedicated control pins.
D
D
− f = 48kHz: 600mW typical
S
The PCM4204 operates from a +5V analog power
supply and a +3.3V digital power supply. The digital I/O
pins are compatible with +3.3V logic families. The
PCM4204 is available in a thermally-enhanced HTQFP-64
PowerPAD package.
− f = 96kHz: 640mW typical
S
− f = 192kHz: 615mW typical
S
Power-Down Mode
Available in a Thermally-Enhanced HTQFP-64
Package
D
D
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners.
ꢅꢤ ꢥ ꢟꢦ ꢜ ꢧꢨ ꢥꢩ ꢟ ꢝꢧꢝ ꢁꢌ ꢈꢉ ꢇ ꢊꢋ ꢑꢁꢉꢌ ꢁꢪ ꢍꢛ ꢇ ꢇ ꢆꢌꢑ ꢋꢪ ꢉꢈ ꢘꢛꢫ ꢙꢁꢍ ꢋꢑꢁ ꢉꢌ ꢞꢋ ꢑꢆꢬ ꢅꢇ ꢉꢞꢛ ꢍꢑꢪ
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ꢅꢇ ꢉ ꢞꢛꢍ ꢑ ꢁꢉ ꢌ ꢘꢇ ꢉ ꢍ ꢆ ꢪ ꢪ ꢁꢌ ꢂ ꢞꢉ ꢆ ꢪ ꢌꢉꢑ ꢌꢆ ꢍꢆ ꢪꢪ ꢋꢇ ꢁꢙ ꢯ ꢁꢌꢍ ꢙꢛꢞ ꢆ ꢑꢆ ꢪꢑꢁ ꢌꢂ ꢉꢈ ꢋꢙ ꢙ ꢘꢋ ꢇ ꢋꢊ ꢆꢑꢆ ꢇ ꢪꢬ
Copyright 2004, Texas Instruments Incorporated
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SBAS327A − JUNE 2004 − REVISED SEPTEMBER 2004
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to
damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
PCM4204
+6.0
UNIT
V
V
1, V
2
V
V
V
CC
CC
Supply voltage
1, V 2, V
DD
3
+3.6
DD DD
Ground voltage differences
(any AGND to DGND or BGND)
0.1
FMT0, FMT1, FMT2, S/M, FS0, FS1, FS2,
SCKI, RST, HPFD, SUB, BCK, LRCK,
DSDCLK, DSD1, DSD2, DSD3, DSD4, TEST
Digital input voltage
−0.3 to (V
+ 0.3)
V
DD
Analog input voltage
V 1−4+, V 1−4−
IN IN
−0.3 to (V
+ 0.3)
V
V
CC
Input current (any pin except supplies)
Operating temperature range
10mA
−10 to +70
°C
°C
Storage temperature range, T
STG
−65 to +150
(1)
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or
any other conditions beyond those specified is not implied.
PACKAGE/ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum located at the end of this
datasheet.
2
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SBAS327A − JUNE 2004 − REVISED SEPTEMBER 2004
ELECTRICAL CHARACTERISTICS
Unless otherwise noted, all characteristics specified with T = +25°C, V
= +5V, V = +3.3V, system clock (SCKI) is 512f for Single Rate
DD S
A
CC
Sampling, 256f for Dual Rate Sampling, or 128f for Quad Rate Sampling. The device is operated in Master mode for all dynamic performance
S
S
measurements.
PCM4204
TYP
PARAMETER
RESOLUTION
TEST CONDITIONS
MIN
MAX
UNIT
24
Bits
DATA FORMAT
2
Audio Data Formats (PCM)
Audio Data Word Length (PCM)
Binary Data Format (PCM)
DSD Output Format and Word Length
DIGITAL INPUT/OUTPUT
Input Logic Level
Left and Right Justified, I S, TDM
24
Bits
Bits
Two’s Complement Binary, MSB First
1-Bit Data
V
V
0.7 x V
0
V
IH
IL
DD
DD
0.3 x V
V
V
DD
Output Logic Level
V
V
I
I
= −2mA
= +2mA
0.8 x V
0
V
OH
OL
OH
OH
DD
DD
DD
0.2 x V
Input Leakage
(1)
Current
I
V
= V
+1
−1
+10
−10
µA
µA
IH
IN
DD
I
V
= 0V
IL
IN
Input Leakage
(2)
I
V
= V
+35
−35
+100
−100
µA
µA
IH
IN
DD
Current
I
V
= 0V
IL
IN
CLOCK FREQUENCIES
System Clock Frequency, f
Single Rate Sampling Mode
Dual Rate Sampling Mode
6.144
12.8
38.4
38.4
MHz
MHz
SCKI
Quad Rate Sampling Mode
12.8
38.4
MHz
Sampling Frequency, f
Single Rate Sampling Mode
Dual Rate Sampling Mode
Quad Rate Sampling Mode
24
54
108
54
108
216
kHz
kHz
kHz
S
ANALOG INPUTS
Full Scale Input Voltage
Average Input Impedance
Common-mode Rejection
Differential Input
6.0
3
85
V
PP
kΩ
dB
DC SPECIFICATIONS
V
COM
V
COM
12, V
12, V
34 Output Voltage
COM
34 Output Current
COM
+2.5
200
V
µA
(1)
(2)
(3)
Applies to the FMT0, FMT1, FMT2, S/M, FS0, FS1, FS2, HPFD, BCK, LRCK, SUB, DSDCLK, DSD1, DSD2, DSD3, DSD4, and SCKI pins.
Applies to the TEST and RST pins.
Typical performance is measured using an Audio Precision System Two Cascade or Cascade Plus test system. The measurement bandwidth
is limited using the Audio Precision 22Hz high-pass filter in combination with either a 20kHz low-pass filter for f = 48kHz or a 40kHz low-pass
S
filter for f = 96kHz and 192kHz. All A-weighted measurements are performed using the A-weighting filter in combination with the band limiting
S
filters already mentioned. The measurements are made with the RMS detector selected.
(4)
(5)
A 256f system clock is used at final production test for f = 48kHz measurements.
S
S
Typical DSD performance is measured using an Audio Precision System Two Cascade or Cascade Plus test system. The measurement
bandwidthis limited using the Audio Precision 22Hz high-pass filter in combination with a 20kHz low-pass filter. All A-weighted measurements
are performed using the A-weighting filter in combination with the band limiting filter already mentioned. The measurements are made with the
RMS detector selected. The 1-bit DSD data is converted to 24-bit linear PCM data for measurement using a PCM4204 configured for DSD input
mode.
3
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SBAS327A − JUNE 2004 − REVISED SEPTEMBER 2004
ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise noted, all characteristics specified with T = +25°C, V
= +5V, V = +3.3V, system clock (SCKI) is 512f for Single Rate
DD S
A
CC
Sampling, 256f for Dual Rate Sampling, or 128f for Quad Rate Sampling. The device is operated in Master mode for all dynamic performance
S
S
measurements.
PCM4204
TYP
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
(3)
DYNAMIC PERFORMANCE (PCM Output)
(4)
= 48kHz
THD+N
f
f
f
S
V
V
= −0.5dBFS, f = 1kHz
IN
−105
−56
118
−96
dB
dB
dB
dB
IN
IN
= −60dBFS, f = 1kHz
IN
Dynamic Range
Channel Separation
V
IN
= −60dBFS, f = 1kHz, A-weighted
IN
112
105
120
= 96kHz
THD+N
S
V
V
= −0.5dBFS, f = 1kHz, BW = 20Hz to 40kHz
IN
−103
−52
118
dB
dB
dB
dB
IN
IN
= −60dBFS, f = 1kHz, BW = 20Hz to 40kHz
IN
Dynamic Range
Channel Separation
V
IN
= −60dBFS, f = 1kHz, A-weighted
IN
120
= 192kHz
S
THD+N
Dynamic Range
V
= −0.5dBFS, f = 1kHz, BW = 20Hz to 40kHz
IN
−103
108
117
dB
dB
dB
dB
IN
V
= 0V, Unweighted, BW = 20Hz to 40kHz
IN
V
IN
= 0V, A-weighted
Channel Separation
120
(5)
DYNAMIC PERFORMANCE (DSD Output)
64f Output Rate
S
THD+N
DSDBCK = 2.8224MHz, BW = 20Hz to 20kHz
= −0.5dBFS, f = 1kHz
V
IN
−103
−52
115
dB
dB
dB
IN
V
IN
= −60dBFS, f = 1kHz
IN
Dynamic Range
V
IN
= −60dBFS, f = 1kHz, A-weighted
IN
DSDBCK = 5.6448MHz, BW = 20Hz to 20kHz
= −0.5dBFS, f = 1kHz
128f Output Rate
S
THD+N
V
IN
−105
−56
118
dB
dB
dB
IN
= −60dBFS, f = 1kHz
V
IN
IN
Dynamic Range
V
IN
= −60dBFS, f = 1kHz, A-weighted
IN
DIGITAL DECIMATION FILTER
Single and Dual Rate Sampling Modes
Passband Edge
Passband Ripple
Stop Band Edge
Stop Band Attenuation
Group Delay
−0.005dB
0.453f
0.005
Hz
dB
Hz
dB
sec
S
0.547f
S
−100
37/f
S
(1)
(2)
(3)
Applies to the FMT0, FMT1, FMT2, S/M, FS0, FS1, FS2, HPFD, BCK, LRCK, SUB, DSDCLK, DSD1, DSD2, DSD3, DSD4, and SCKI pins.
Applies to the TEST and RST pins.
Typical performance is measured using an Audio Precision System Two Cascade or Cascade Plus test system. The measurement bandwidth
is limited using the Audio Precision 22Hz high-pass filter in combination with either a 20kHz low-pass filter for f = 48kHz or a 40kHz low-pass
S
filter for f = 96kHz and 192kHz. All A-weighted measurements are performed using the A-weighting filter in combination with the band limiting
S
filters already mentioned. The measurements are made with the RMS detector selected.
(4)
(5)
A 256f system clock is used at final production test for f = 48kHz measurements.
S
S
Typical DSD performance is measured using an Audio Precision System Two Cascade or Cascade Plus test system. The measurement
bandwidthis limited using the Audio Precision 22Hz high-pass filter in combination with a 20kHz low-pass filter. All A-weighted measurements
are performed using the A-weighting filter in combination with the band limiting filter already mentioned. The measurements are made with the
RMS detector selected. The 1-bit DSD data is converted to 24-bit linear PCM data for measurement using a PCM4204 configured for DSD input
mode.
4
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SBAS327A − JUNE 2004 − REVISED SEPTEMBER 2004
ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise noted, all characteristics specified with T = +25°C, V
= +5V, V = +3.3V, system clock (SCKI) is 512f for Single Rate
DD S
A
CC
Sampling, 256f for Dual Rate Sampling, or 128f for Quad Rate Sampling. The device is operated in Master mode for all dynamic performance
S
S
measurements.
PCM4204
TYP
PARAMETER
DIGITAL DECIMATION FILTER (continued)
Quad Rate Sampling Mode
Passband Edge
TEST CONDITIONS
MIN
MAX
UNIT
−0.005dB
−3dB
0.375f
Hz
Hz
dB
Hz
dB
sec
S
0.490f
S
Passband Ripple
Stop Band Edge
Stop Band Attenuation
Group Delay
0.005
0.770f
−135
S
9.5/f
S
DIGITAL HIGH PASS FILTER
Frequency Response (−3dB)
POWER SUPPLY
f /48000
S
Hz
Voltage Range
V
1, V
2
3
+4.75
+3.0
+5.0
+3.3
+5.25
+3.6
VDC
VDC
CC
CC
DD
V
1, V 2, V
DD DD
Power Down Supply Current
V
CC
= +5V, V
= +3.3V, RST = Low
DD
I
1 + I
2
3
10
2
mA
mA
CC
CC
DD
I
1 + I 2 + I
DD
DD
Quiescent Current
I 1 + I 2
CC CC
V
= +5.0V
(4)
CC
= 48kHz
f
S
108
108
108
130
130
130
mA
mA
mA
f
= 96kHz
= 192kHz
S
f
S
I 1 + I 2 + I 3
DD DD DD
V
= +3.3V
DD
= 48kHz
(4)
f
S
18
30
23
23
44
26
mA
mA
mA
f
= 96kHz
= 192kHz
S
f
S
Total Power Dissipation
V
CC
= +5V, V
= +3.3V
(4)
DD
f
S
= 48kHz
600
640
615
726
795
736
mW
mW
mW
f
= 96kHz
= 192kHz
S
f
S
(1)
(2)
(3)
Applies to the FMT0, FMT1, FMT2, S/M, FS0, FS1, FS2, HPFD, BCK, LRCK, SUB, DSDCLK, DSD1, DSD2, DSD3, DSD4, and SCKI pins.
Applies to the TEST and RST pins.
Typical performance is measured using an Audio Precision System Two Cascade or Cascade Plus test system. The measurement bandwidth
is limited using the Audio Precision 22Hz high-pass filter in combination with either a 20kHz low-pass filter for f = 48kHz or a 40kHz low-pass
S
filter for f = 96kHz and 192kHz. All A-weighted measurements are performed using the A-weighting filter in combination with the band limiting
S
filters already mentioned. The measurements are made with the RMS detector selected.
(4)
(5)
A 256f system clock is used at final production test for f = 48kHz measurements.
S
S
Typical DSD performance is measured using an Audio Precision System Two Cascade or Cascade Plus test system. The measurement
bandwidthis limited using the Audio Precision 22Hz high-pass filter in combination with a 20kHz low-pass filter. All A-weighted measurements
are performed using the A-weighting filter in combination with the band limiting filter already mentioned. The measurements are made with the
RMS detector selected. The 1-bit DSD data is converted to 24-bit linear PCM data for measurement using a PCM4204 configured for DSD input
mode.
5
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SBAS327A − JUNE 2004 − REVISED SEPTEMBER 2004
PIN ASSIGNMENT
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
−
1
2
48
47
46
VIN
1
VIN4+
−
IN4
V
IN1+
NC
NC
V
3
NC
4
45 NC
44 VCC2
VCC
1
5
AGND1
BGND1
DGND1
6
43 AGND2
7
42
41
40
39
38
37
BGND4
DGND3
8
PCM4204
V
DD1
9
VDD3
10
11
12
RST
TEST
FS0
SUB
HPFD
CLIP4
FS1 13
FS2 14
SCKI 15
36 CLIP3
35 CLIP2
34 CLIP1
16
33
BGND3
BGND2
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
6
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SBAS327A − JUNE 2004 − REVISED SEPTEMBER 2004
Terminal Functions
TERMINAL
NAME
PIN NO.
I/O
Input
Input
—
DESCRIPTION
1
2
3
V
1−
1+
Channel 1 Analog Input, Inverting
IN
V
IN
Channel 1 Analog Input, Non-inverting
No Internal Connection
No Internal Connection
Analog Supply, +5V Nominal
Analog Ground
NC
NC
4
—
5
V 1
CC
Power
Ground
Ground
Ground
Power
Input
Input
Input
Input
Input
Input
Ground
Input
Input
Input
Input
—
6
AGND1
BGND1
DGND1
7
Substrate Ground
8
Digital Ground
9
V 1
DD
Digital Supply, +3.3V Nominal
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
RST
TEST
FS0
Reset/Power Down (Active Low with internal pull-up to V 1)
DD
Test Pin (Active High with internal pull-down to DGND)
Sampling Mode
FS1
Sampling Mode
FS2
Sampling Mode
SCKI
BGND2
S/M
System Clock
Substrate Ground
Audio Serial Port Slave/Master Mode (0 = Master, 1 = Slave)
Audio Data Format
FMT0
FMT1
FMT2
NC
Audio Data Format
Audio Data Format
No Internal Connection
Digital Ground
DGND2
Ground
Power
I/O
V 2
DD
Digital Supply, +3.3V Nominal
DSD Data Clock
DSDCLK
DSD1
DSD2
DSD3
DSD4
BCK
I/O
Channel 1 DSD Data
I/O
Channel 2 DSD Data
I/O
Channel 3 DSD Data
I/O
Channel 4 DSD Data
I/O
Audio Serial Port Bit Clock
Audio Serial Port Left/Right (or Word) Clock
LRCK
SDOUT1
SDOUT2
BGND3
CLIP1
CLIP2
CLIP3
CLIP4
HPFD
SUB
I/O
(1)
Output
Output
Ground
Output
Output
Output
Output
Input
Input
Power
PCM Data for Channels 1 and 2
PCM Data for Channels 3 and 4
Substrate Ground
(1)
Channel 1 Clipping Flag (Active High)
Channel 2 Clipping Flag (Active High)
Channel 3 Clipping Flag (Active High)
Channel 4 Clipping Flag (Active High)
High-Pass Filter Disable (Active High)
TDM Sub-Frame Assignment (0 = SF 0, 1 = SF 1)
Digital Supply, +3.3V Nominal
V 3
DD
(1)
For TDM formats, SDOUT1 carries data for all four channels, while SDOUT2 is driven low.
7
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SBAS327A − JUNE 2004 − REVISED SEPTEMBER 2004
Terminal Functions (continued)
TERMINAL
NAME
PIN NO.
I/O
DESCRIPTION
41
DGND3
BGND4
AGND2
Ground
Digital Ground
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Ground
Ground
Power
—
Substrate Ground
Analog Ground
V 2
CC
Analog Supply, +5V Nominal
No Internal Connection
No Internal Connection
Channel 4 Analog Input, Inverting
NC
NC
—
V
4−
4+
Input
Input
Output
Output
Output
Output
—
IN
V
IN
Channel 4 Analog Input, Non-inverting
Voltage Reference De-Coupling for Channels 3 and 4
Reference Ground for Channels 3 and 4, connect to AGND
Analog Ground
V
V
34+
34−
REF
REF
AGND3
V 34
COM
Common-mode Voltage for Channels 3 and 4, +2.5V Nominal
No Internal Connection
NC
V
3−
3+
Input
Input
—
Channel 3 Analog Input, Inverting
IN
V
IN
Channel 3 Analog Input, Non-inverting
No Internal Connection
NC
NC
—
No Internal Connection
V
2−
2+
Input
Input
—
Channel 2 Analog Input, Inverting
IN
V
IN
Channel 2 analog Input, Non-inverting
No Internal Connection
NC
V 12
COM
Output
Ground
Output
Output
Common-mode Voltage for Channels 1 and 2, +2.5V Nominal
Analog Ground
AGND4
V 12−
REF
Reference Ground for Channels 1 and 2, connect to AGND
Voltage Reference De-Coupling for Channels 1 and 2
V 12+
REF
(1)
For TDM formats, SDOUT1 carries data for all four channels, while SDOUT2 is driven low.
8
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TYPICAL CHARACTERISTICS
At T = +25°C with V
= +5V, VDD = +3.3V, and a measurement bandwidth from 20Hz to 20kHz, unless otherwise noted.
A
CC
OVERALL CHARACTERISTICS
SINGLE RATE FILTER
STOP BAND ATTENUATION CHARACTERISTICS
SINGLE RATE FILTER
50
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
fS = 48 kHz
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
fS = 48 kHz
0
−
50
−
−
−
100
150
200
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0.5
Normalized Frequency (fS)
0
1
0.75
0.25
Normalized Frequency (fS)
TRANSIENT BAND CHARACTERISTICS
SINGLE RATE FILTER
PASSBAND RIPPLE CHARACTERISTICS
SINGLE RATE FILTER
0
0.02
fS = 48kHz
fS = 48kHz
−
1
2
3
4
5
6
7
8
9
0
0.02
0.04
0.06
0.08
−
−
−
−
−
−
−
−
−
−
−
−
−
10
−
0.1
0.45
0.47
0.49
0.51
0.53
0.55
0
0.2
0.4
0.6
0.1
0.3
0.5
Normalized Frequency (fS)
Normalized Frequency (fS)
OVERALL CHARACTERISTICS
DUAL RATE FILTER
STOP BAND ATTENUATION CHARACTERISTICS
DUAL RATE FILTER
50
0
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
fS = 96kHz
−
−
−
−
−
−
−
−
−
fS = 96kHz
−
50
−
100
150
200
−
−
−
−
−
−
−
−
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Normalized Frequency (fS)
0.5
Normalized Frequency (fS)
0
1
0.75
0.25
9
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SBAS327A − JUNE 2004 − REVISED SEPTEMBER 2004
TYPICAL CHARACTERISTICS (continued)
At T = +25°C with V
= +5V, VDD = +3.3V, and a measurement bandwidth from 20Hz to 20kHz, unless otherwise noted.
A
CC
TRANSIENT BAND CHARACTERISTICS
DUAL RATE FILTER
PASSBAND RIPPLE CHARACTERISTICS
DUAL RATE FILTER
0
1
2
3
4
5
6
7
8
9
0.02
0
fS = 96kHz
fS = 96kHz
−
−
−
−
−
−
−
−
−
−
−
−
−
0.02
0.04
0.06
0.08
−
10
−
0.1
0.45
0.47
0.49
0.51
0.53
0.55
0
0.2
0.4
0.6
0.1
0.3
0.5
Normalized Frequency (fS)
Normalized Frequency (fS)
OVERALL CHARACTERISTICS
QUAD RATE FILTER
STOP BAND ATTENUATION CHARACTERISTICS
QUAD RATE FILTER
50
0
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
fS = 192kHz
−
−
−
−
−
−
−
−
−
fS = 192kHz
−
50
−
−
−
100
150
200
−
−
−
−
−
−
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Normalized Frequency (fS)
1
0.5
Normalized Frequency (fS)
0
1
0.75
0.25
TRANSIENT BAND CHARACTERISTICS
QUAD RATE FILTER
PASSBAND RIPPLE CHARACTERISTICS
QUAD RATE FILTER
0
0.02
0
fS = 192kHz
fS = 192kHz
−
1
2
3
4
5
6
7
8
9
−
−
3.90dB at 0.5fS
−
−
−
−
−
−
−
−
0.02
0.04
0.06
0.08
−
−
−
−
10
−
0.1
0
0.2
0.4
0.6
0.45
0.47
0.49
0.51
0.53
0.55
0.1
0.3
0.5
Normalized Frequency (fS)
Normalized Frequency (fS)
10
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TYPICAL CHARACTERISTICS (continued)
At T = +25°C with V
= +5V, VDD = +3.3V, and a measurement bandwidth from 20Hz to 20kHz, unless otherwise noted.
A
CC
HIGH PASS FILTER
HIGH PASS FILTER
PASSBAND CHARACTERISTICS
STOP BAND CHARACTERISTICS
5
0.02
0
−
−
−
−
20
40
60
80
−
0.02
0.04
0.06
0.08
−
−
−
−
−
0.1
100
0
20
20
0.1
0.2
0.3
0.4
10k 20k
10k 20k
0
0.5
1
1.5
2
2.5
3
3.5
4
Normalized Frequency (fS/1000)
Normalized Frequency (fS/1000)
FFT PLOT
FFT PLOT
−
(fS = 48kHz, fIN = 997Hz at 60dB)
−
(fS = 48kHz, fIN = 997Hz at 20dB)
0
0
−
20
40
60
80
−
20
−
−
−
−
40
60
80
−
−
−
−
−
−
−
−
−
−
−
−
100
120
140
160
180
100
120
140
160
180
100
1k
20
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
FFT PLOT
FFT PLOT
−
(fS = 96kHz, fIN = 997Hz at 20dB)
(fS = 48kHz, No Input [Idle])
0
0
−
−
−
−
−
−
−
−
20
40
60
80
20
40
60
80
−
−
−
−
−
100
120
140
160
180
−
−
−
−
−
100
120
140
160
180
20
100
1k
10k
40k
100
1k
Frequency (Hz)
Frequency (Hz)
11
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TYPICAL CHARACTERISTICS (continued)
At T = +25°C with V
= +5V, VDD = +3.3V, and a measurement bandwidth from 20Hz to 20kHz, unless otherwise noted.
A
CC
FFT PLOT
(fS = 96kHz, fIN = 997Hz at 60dB)
FFT PLOT
(fS = 96kHz, No Input [Idle])
−
0
0
20
40
60
80
−
−
−
−
−
−
−
−
20
40
60
80
−
−
−
−
−
−
−
−
−
−
100
120
140
160
180
100
120
140
160
180
20
20
20
100
1k
10k
40k
100k
100k
20
100
1k
10k
40k
Frequency (Hz)
Frequency (Hz)
FFT PLOT
FFT PLOT
−
−
(fS = 192kHz, fIN = 997Hz at 60dB)
(fS = 192kHz, fIN = 997Hz at 20dB)
0
0
−
−
20
40
60
80
20
40
60
80
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
100
120
140
160
180
100
120
140
160
180
100
1k
10k
20
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
FFT PLOT
(fS = 192kHz, No Input [Idle])
THD+N vs AMPLITUDE
(fS = 48kHz, fIN = 1kHz, BW = 20Hz to 20kHz)
0
−
−
−
−
−
90
92
94
96
98
−
−
−
−
20
40
60
80
−
100
102
104
106
108
110
112
114
116
118
120
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
100
120
140
160
180
100
1k
10k
−
−
−
−
−
−
−
20
140
120
100
80
60
40
0
Frequency (Hz)
Input Amplitude (dB)
12
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SBAS327A − JUNE 2004 − REVISED SEPTEMBER 2004
TYPICAL CHARACTERISTICS (continued)
At T = +25°C with V
CC
= +5V, VDD = +3.3V, and a measurement bandwidth from 20Hz to 20kHz, unless otherwise noted.
A
THD+N vs FREQUENCY
THD+N vs AMPLITUDE
−
(fS = 48kHz, Input Amplitude = 1dB,
(fS = 96kHz, fIN = 1kHz, BW = 20Hz to 40kHz)
BW = 20Hz to 20kHz)
−
−
−
−
−
90
92
94
96
98
−
−
−
−
−
100
102
104
106
108
110
112
114
116
118
120
90
92
94
96
98
−
−
−
−
−
−
−
−
−
−
−
100
102
104
106
108
110
112
114
116
118
120
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
20
140
120
100
80
60
40
0
20
100
1k
10k 20k
Input Amplitude (dB)
Input Frequency (Hz)
THD+N vs FREQUENCY
−
(fS = 96kHz, Input Amplitude = 1dB,
BW = 20Hz to 40kHz)
THD+N vs AMPLITUDE
(fS = 192kHz, fIN = 1kHz, BW = 20Hz to 40kHz)
−
−
−
−
−
−
70
75
80
85
90
95
−
−
−
−
−
90
92
94
96
98
−
−
−
−
−
−
−
−
−
−
−
100
102
104
106
108
110
112
114
116
118
120
−
−
−
−
−
100
105
110
115
120
20
100
1k
10k
40k
−
−
−
−
−
−
−
20
140
120
100
80
60
40
0
Input Frequency (Hz)
Input Amplitude (dB)
THD+N vs FREQUENCY
−
(fS = 192kHz, Input Amplitude = 1dB,
BW = 20Hz to 40kHz)
−
−
−
−
−
−
70
75
80
85
90
95
−
−
−
−
−
100
105
110
115
120
20
100
1k
10k
80k
Input Frequency (Hz)
13
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SBAS327A − JUNE 2004 − REVISED SEPTEMBER 2004
On-chip voltage references are provided for the
modulators, in addition to generating DC common-mode
bias voltage outputs for use with external input circuitry.
Linear phase digital decimation filtering is provided for the
24-bit PCM output, with a minimum stop band attenuation
of −100dB for all sampling modes.
PRODUCT OVERVIEW
The PCM4204 is a high-performance, four-channel audio
analog-to-digital (A/D) converter designed for use in
professional and broadcast audio applications. The
PCM4204 features 24-bit linear PCM data outputs, as well
as 1-bit Direct Stream Digital (DSD) data output and input
capability for all four channels. Sampling rates up to
216kHz are supported for PCM output formats, while 64x
or 128x oversampled 1-bit data is supported for DSD
modes. Native support for both PCM and DSD data
formats makes the PCM4204 ideal for use in a wide variety
of audio recording and processing applications.
The PCM output mode features clipping flag outputs for
each of the four channels, as well as a digital high-pass
filter for DC removal. The PCM4204 may be configured
using dedicated input pins for sampling mode and audio
data format selection, high-pass filter enable/disable, and
reset/power-down operation.
A +5V power supply is required for the analog section of
the device, while a +3.3V power supply is required for the
digital circuitry. Figure 1 shows the functional block
diagram for the PCM4204.
The PCM4204 features 1-bit delta sigma modulators
employing density modulated dither for improved dynamic
performance. Differential voltage inputs are utilized for the
modulators, providing excellent common-mode rejection.
VIN1+
LRCK
BCK
Delta−Sigma
Modulator
Digital
Audio
Serial
Port
Decimation and High Pass
Filters
−
VIN1
SDOUT1
SDOUT2
V
REF12+
DSD1
DSD2
DSD3
−
V
REF12
DSD
Data
Port
Reference
AGND4
VCOM12
DSD4
DSDCLK
FS0
FS1
FS2
S/M
VIN2+
Delta−Sigma
Modulator
−
VIN2
FMT0
FMT1
FMT2
HPFD
SUB
Control
and
Status
To /From
VIN3+
Other Blocks
Delta−Sigma
Modulator
−
VIN3
RST
CLIP1
CLIP2
CLIP3
CLIP4
V
REF34+
−
VREF34
Reference
AGND3
VCOM34
System Clock
and
To Other
Blocks
SCKI
Timing
V
IN4+
Delta−Sigma
Modulator
−
VIN4
Power and Ground
Figure 1. PCM4204 Functional Block Diagram
14
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SBAS327A − JUNE 2004 − REVISED SEPTEMBER 2004
recommended to have at least a 0.1µF X7R ceramic chip
capacitor connected in parallel with a 33µF low ESR
capacitor (tantalum, multilayer ceramic, or aluminum
electrolytic) for de-coupling purposes.
ANALOG INPUTS
The PCM4204 includes four channels of A/D conversion,
each with its own pair of differential voltage input pins. The
VIN1− (pin 1) and VIN1+ (pin 2) analog inputs correspond
to Channel 1. The VIN2− (pin 58) and VIN2+ (pin 59) analog
inputs correspond to Channel 2. The VIN3− (pin 54) and
VIN3+ (pin 55) analog inputs correspond to Channel 3. The
VIN4− (pin 47) and VIN4+ (pin 48) analog inputs
correspond to Channel 4. The average input impedance of
each input pin is 3.0kΩ.
Each analog input pair accepts a full-scale input voltage of
approximately 6.0VPP differential. The analog input should
not swing below analog ground or above the VCC1 (pin 5)
or VCC2 (pin 44) power supplies by more than 300mV.
Schottky diodes may be used to clamp these pins to a safe
input range, or the input buffer circuitry may be designed
in a manner to ensure that the input swing does not exceed
the absolute maximum ratings of the PCM4204. Refer to
theApplications Information section of this datasheet for
an example input buffer circuit.
Refer to the Applications Information section of this
datasheet for the recommended voltage reference pin
connections.
The VREF12+ and VREF34+ outputs should not be utilized
to bias external circuitry, as they are not buffered. Use the
VCOM12 (pin 16) and VCOM34 (pin 52) outputs to bias
external circuitry. Although the VCOML and VCOMR outputs
are internally buffered, the output current is limited to a few
hundred µA. It is recommended to connect these pins to
external nodes with greater than 1MΩ impedance, or to
buffer the outputs with a voltage follower circuit when
driving multiple external nodes.
Refer to the Applications Information section of this
datasheet for an example input buffer circuit that utilizes
the common-mode bias voltage outputs.
SYSTEM CLOCK INPUT
VOLTAGE REFERENCES AND COMMON MODE
BIAS VOLTAGE OUTPUTS
The PCM4204 requires a system clock, from which the
modulator oversampling and digital sub-system clocks are
derived. The system clock is applied at the SCKI input (pin
15). The frequency of the system clock is dependent upon
the desired PCM output sampling frequency or DSD data
rate, along with the sampling mode selection. Table 1
shows the corresponding system clock frequencies for
common output sampling and data rates, along with the
corresponding sampling modes. Timing requirements for
the system clock are shown in Figure 2.
The PCM4204 includes two on-chip voltage references,
one for Channels 1 and 2 and another for Channels 3 and
4. The VREF12− (pin 63) and VREF12+ (pin 64) outputs
correspond to low and high reference outputs for Channels
1 and 2. The VREF34− (pin 50) and VREF34+ (pin 49)
outputs correspond to low and high reference outputs for
Channels 3 and 4. De-coupling capacitors are connected
between the high and low reference pins, and the low
reference pin is then connected to an analog ground. It is
Table 1. System Clock Frequencies for Common Output Sampling and Data Rates
SYSTEM CLOCK FREQUENCY (MHz)
SAMPLING FREQUENCY, f
(kHz)
S
128f
192f
256f
384f
512f
768f
S
SAMPLING MODE
Single Rate
S
S
S
S
S
32
44.1
48
n/a
n/a
n/a
n/a
8.192
11.2896
12.288
22.5792
24.576
n/a
12.288
16.9344
18.432
33.8688
36.864
n/a
16.384
22.5792
24.576
n/a
24.576
33.8688
36.864
n/a
Single Rate
Single Rate
n/a
n/a
Dual Rate
88.2
96
n/a
n/a
Dual Rate
n/a
n/a
n/a
n/a
Quad Rate
176.4
192
22.5792
24.576
n/a
33.8688
36.864
n/a
n/a
n/a
Quad Rate
n/a
n/a
n/a
n/a
DSD Input/Output
DSD Input/Output
128f Data (Single Rate)
11.2896
11.2896
16.9344
16.9344
22.5792
n/a
33.8688
n/a
S
64f Data (Dual Rate)
n/a
n/a
S
15
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SBAS327A − JUNE 2004 − REVISED SEPTEMBER 2004
t
SCKIH
SCKI
t
t
SCKI
SCKIL
DESCRIPTION
System Clock Period
PARAMETER
tSCKI
MIN
26
MAX
UNITS
ns
tSCKIH
System Clock High Pulse Time
System Clock Low Pulse Time
12
ns
tSCKIL
12
ns
Figure 2. System Clock Timing Requirements
of the sampling mode pins is changed any time after
power-up reset initialization, the user should issue an
external forced reset to re-initialize the PCM4204. Table 2,
Table 3, Table 4, and Table 5 indicate the sampling mode
selections for PCM Master and Slave mode operation, as
well as the DSD Output and Input mode operation.
SAMPLING MODES
The PCM4204 may be operated in one of three PCM
sampling modes, or at one of two DSD output data rates.
The PCM sampling modes are referred to as Single Rate,
Dual Rate, and Quad Rate.
Single Rate mode is utilized for sampling rates up to
54kHz. The delta-sigma modulator oversamples the
analog input signal by a rate equal to 128 times the desired
output sampling rate.
Table 2. Sampling Mode Selection for PCM
Master Mode Operation
SAMPLING MODE WITH
SYSTEM CLOCK RATE
FS2
0
FS1
0
FS0
0
Dual Rate mode is utilized for sampling rates higher than
54kHz and up to 108kHz. The delta-sigma modulator
oversamples the analog input signal by a rate equal to 64
times the desired output sampling rate.
Single Rate with f
Single Rate with f
Single Rate with f
Single Rate with f
= 768f
= 512f
= 384f
= 256f
SCKI
SCKI
SCKI
SCKI
SCKI
SCKI
S
S
S
S
0
0
1
0
1
0
Quad Rate mode is utilized for sampling frequencies
higher than 108kHz and up to 216kHz. The delta-sigma
modulator oversamples the analog input signal by a rate
equal to 32 times the desired output sampling rate.
0
1
1
1
0
0
Dual Rate with f
Dual Rate with f
= 384f
= 256f
S
1
0
1
S
1
1
0
Quad Rate with f
= 192f
SCKI
SCKI
S
S
For DSD output data, the user may select either 64fS or
128fS oversampled data rates, where fS is the base
sampling rate, which is 44.1kHz for Super Audio CD
(SACD) applications. The 64fS data rate is analogous to
the Dual Rate PCM sampling mode, where the analog
input signal is oversampled by a rate equal to 64 times the
base sampling rate. The 128fS data rate corresponds to
the Single Rate PCM sampling mode, where the analog
input signal is oversampled by a rate equal to 128 times the
base sampling rate. For DSD input data, the rate of the
data must be known in order to configure the digital
decimation filter for either 1/64 or 1/128 operation.
1
1
1
Quad Rate with f
= 128f
Table 3. Sampling Mode Selection for PCM Slave
Mode Operation
FS2
0
FS1
0
FS0
0
SAMPLING MODE
Single Rate with Clock Auto-Detection
Dual Rate with Clock Auto-Detection
Quad Rate with Clock Auto-Detection
Reserved
0
0
1
0
1
0
0
1
1
1
0
0
Reserved
Table 1 indicates the sampling mode utilized for common
system clock and sampling rate combinations. The FS0
(pin 12), FS1 (pin 13), and FS2 (pin 14) inputs are utilized
to select the sampling mode for the PCM4204. If the state
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
16
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SBAS327A − JUNE 2004 − REVISED SEPTEMBER 2004
In Master mode, the PCM bit and left/right clocks (BCK and
LRCK respectively) are configured as output pins, and are
derived from the system clock input (SCKI). For the DSD
data and clock pins (DSD1, DSD2, DSD3, DSD4, and
DSDCLK), they may be configured as either inputs or
outputs, depending upon the DSD format selection. Table
7 summarizes the corresponding Master mode data format
selections.
Table 4. Sampling Mode Selection for DSD
Output Mode Operation
FS2 FS1 FS0
SAMPLING MODE
128f DSD Output Rate with f
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
= 768f
= 512f
= 384f
= 256f
S
SCKI
SCKI
SCKI
SCKI
SCKI
SCKI
S
S
S
S
128f DSD Output Rate with f
S
128f DSD Output Rate with f
S
128f DSD Output Rate with f
S
64f DSD Output Rate with f
S
= 384f
S
Figure 3, Figure 4, and Figure 5 illustrate the PCM and
DSD data formats supported by the PCM4204.
64f DSD Output Rate with f
S
= 256f
S
Reserved
Reserved
Table 6. Slave Mode Audio Data Format Selection
S/M
1
FMT2 FMT1 FMT0
AUDIO DATA FORMAT
0
0
0
0
0
0
1
1
0
1
0
1
24-bit Left-Justified
Table 5. Sampling Mode Selection for DSD Input
Mode Operation
2
1
24-bit I S
FS2 FS1 FS0
SAMPLING MODE
1
24-bit Right-Justified
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
1
TDM with No BCK Delay for
Start of Frame
128f DSD Output Rate with f
S
= 512f
= 384f
= 256f
SCKI
SCKI
SCKI
SCKI
SCKI
S
S
S
128f DSD Output Rate with f
S
1
1
0
0
TDM with One BCK Delay for
Start of Frame
128f DSD Output Rate with f
S
1
1
1
1
1
1
0
1
1
1
0
1
Reserved
Reserved
Reserved
64f DSD Output Rate with f
= 384f
S
S
64f DSD Output Rate with f
S
= 256f
S
Reserved
Reserved
Table 7. Master Mode Audio Data Format
Selection
AUDIO DATA FORMATS
S/M
0
FMT2 FMT1 FMT0
AUDIO DATA FORMAT
As mentioned previously, the PCM4204 supports 24-bit
linear PCM output data, as well as 1-bit DSD output data.
The available data formats are dependent upon whether
the PCM4204 is configured in Slave or Master mode. The
S/M (pin 17), FMT0 (pin 18), FMT1 (pin 19), and FMT2 (pin
20) inputs are utilized to select either Slave or Master
mode and the corresponding audio data format.
0
0
0
0
0
0
1
1
0
1
0
1
24-bit Left-Justified
2
0
24-bit I S
0
24-bit Right-Justified
0
DSD Output with PCM Output
Disabled
0
1
0
0
DSD Input with 24−Bit Right-
Justified PCM Output
In Slave mode, the PCM bit and left/right word clocks (BCK
and LRCK) are configured as input pins. DSD data formats
are not supported in Slave mode. Slave mode supports
commonly used PCM audio data formats, including Left-
Justified, Right-Justified, and Philips I2S. Time division
multiplexed (TDM) data formats are also supported,
allowing up to two PCM4204 devices to be cascaded on
a single audio serial bus. Table 6 summarizes the
corresponding Slave mode data format selections.
0
0
0
1
1
1
0
1
1
1
0
1
Reserved
Reserved
Reserved
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SBAS327A − JUNE 2004 − REVISED SEPTEMBER 2004
Ch. 1 (SDOUT1) or Ch. 3 (SDOUT2)
Ch. 2 (SDOUT1) or Ch. 4 (SDOUT2)
LRCKI
BCKI
SDOUT1
SDOUT2
MSB
LSB
MSB
LSB
(a) Left−Justified Data Format
LRCKI
BCKI
SDOUT1
SDOUT2
MSB
LSB
MSB
LSB
(b) Right−Justified Data Format
LRCKI
BCKI
SDOUT1
SDOUT2
MSB
LSB
MSB
LSB
(c) I2S Data Format
1/fS
2
Figure 3. PCM Data Formats: Left-Justified, Right-Justified, and Philips I S
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−
TDM Data Format Long Frame (Single and Dual Rate Sampling Modes)
LRCK
No BCK Delay
LRCK
One BCK Delay
Slot 1
Ch. 1
Slot 2
Ch. 2
Slot 3
Ch. 3
Slot 4
Ch. 4
Slot 5
Ch. 1
Slot 6
Ch. 2
Slot 7
Ch. 3
Slot 8
Ch. 4
SDOUT1
Supports 8 Channels, or
two PCM4204 devices.
Sub−Frame 0
(SUB = 0)
Sub−Frame 1
(SUB = 1)
One Frame
BCK = 256fS
−
TDM Data Format Short Frame (All Sampling Modes)
LRCK
No BCK Delay
LRCK
One BCK Delay
Slot 1
Ch. 1
Slot 2
Ch. 2
Slot 3
Ch. 3
Slot 4
Ch. 4
Slot 5
Ch. 1
Slot 6
Ch. 2
Slot 7
Ch. 3
Slot 8
Ch. 4
SDOUT1
Supports 4 Channels, or
two PCM4204 devices.
One Frame
BCK = 128fS
(the SUB pin is ignored when using a Short Frame)
In the case of BCK = 256fS, each time slot is 32 bits long and contains the 24−bit audio data for the corresponding channel.
The audio data is left−justified in the time slot, with the the least significant 8 bits of each time slot being don’t care bits.
Audio data is always presented in two’s complement, MSB−first format.
Figure 4. PCM Data Formats: Time Division Multiplexed (TDM)
audio serial port. The LRCK and BCK clocks must be
DSDCLK
synchronous. The SDOUT1 and SDOUT2 signals are the
serial audio data outputs, with data being clocked out on
the falling edge of the BCK clock. SDOUT1 carries data for
Channels 1 and 2 when using Left-Justified, Right-
Justified, or I2S data formats. SDOUT1 carries data for all
four channels when using TDM data formats. SDOUT2
carries data for Channels 3 and 4 when using Left-
Justified, Right-Justified, or I2S data formats. SDOUT2 is
forced low when using TDM data formats.
DSD1
DSD2
DSD3
DSD4
DN−3 DN−2 DN−1 DN DN+1 DN+2 DN+3 DN+4
Figure 5. DSD Input and Output Data Format
AUDIO SERIAL PORT OPERATION
As mentioned in the Audio Data Format section of this
datasheet, the audio serial port can operate in Master or
Slave mode. In Master mode, the BCK and LRCK clock
signals are outputs, derived from the system clock input,
SCKI. The BCK clock is fixed at 128fS for Single Rate
sampling mode, and at 64fS for Dual or Quad Rate
sampling modes. The LRCK clock operates at fS, the
output sampling rate (that is, 48kHz, 96kHz, etc.).
This section provides additional details regarding the
PCM4204 audio serial port, utilized for 24-bit linear PCM
output data. The serial port is comprised of four signals:
BCK (pin 29), LRCK (pin 30), SDOUT1 (pin 31), and
SDOUT2 (pin 32). The BCK signal functions as the data (or
bit) clock for the serial audio data. The LRCK is the
left/right word or TDM frame synchronization clock for the
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In Slave mode, the BCK and LRCK signals are inputs, with
the clocks being generated by a master timing source,
such as a DSP serial port, PLL clock synthesizer, or a
crystal oscillator/divider circuit. For Left Justified, Right
Justified, and I2S data formats, the BCK rate is typically
128fS in Single Rate sampling mode, and 64fS in Dual or
Quad Rate sampling modes. Although other BCK clock
rates are possible, they are not recommended due to the
potential for clock phase sensitivity issues, which may
degrade the dynamic performance of the PCM4204. The
LRCK clock operates at fS, the output sampling rate.
In Slave mode, the TDM data formats support a BCK clock
rate of 256fS for Long Frame operation, and 128fS for Short
Frame operation. The length and rate of the TDM frame is
auto−detected by the audio serial port. Long Frame
operation is supported for Single and Dual rate sampling
modes only. Short Frame operation is supported for all
sampling modes.
For the TDM data formats, the maximum BCK rate is
27.648MHz for either Long or Short Frame operation. The
LRCK clock operates at fS, the output sampling rate. The
minimum clock high time for the LRCK clock is one BCK
clock period. The start of frame is referenced to the rising
edge of the LRCK signal.
Figure 6 illustrates the typical audio serial port
connections between a PCM4204 and an audio signal
processor when using Left-Justified, Right-Justified, and
I2S data formats in either Slave or Master modes.
Sub-frame selection for Long Frame TDM operation is
accomplished by using the SUB input (pin 39). When SUB
= 0, the PCM4204 is assigned to sub-frame 0. The
SDOUT1 pin will be driven during sub-frame 0 and
tri-stated during sub-frame 1. When SUB = 1, the
PCM4204 is assigned to sub-frame 1. The SDOUT1 pin
will be driven during sub-frame 1 and tri-stated during
sub-frame 0. For Short Frame TDM operation, the SUB pin
is ignored, although driving or hardwiring the SUB pin low
is an acceptable practice. Figure 7 shows two PCM4204
devices and an audio DSP in a typical TDM format
application.
DSP
FSR
PCM4204
LRCK
CLKR
DR0
BCK
SDOUT1
SDOUT2
DR1
SCKI
System Clock
Figure 8 and Figure 9 illustrate the PCM4204 audio serial
port timing for both Master and Slave mode operation.
Figure 6. Typical Audio Serial Port Connections
2
for Left-Justified, Right-Justified, and Philips I S
Data Formats
Device #1
(Sub−Frame 0)
DSP
PCM4204
FSR
CLKR
DR
LRCK
BCK
SDOUT1
SCKI
SUB
Device #2
(Sub−Frame 1)
PCM4204
LRCK
BCK
SDOUT1
SUB
VCC
System Clock
Figure 7. TDM Connections for Two PCM4204 Devices and an Audio DSP
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tLRCKP
tLRCKHL
tLRCKHL
LRCK
BCK
tBCKP
tBCKHL
SDOUT1
SDOUT2
tBCKDO
PARAM ETER
tLRCKP
DESCRIPTION
MIN
MAX
UNITS
µ
µ
LRCK Period
LRCK High/Low Time
BCK Period
5
2.25
78
s
s
tLRCKHL
tBCKP
ns
ns
ns
tBCKHL
BCK High/Low Time
35
tBCKDO
SDOUT Data Output Delay from BCK Falling Edge
10
2
Figure 8. Master and Slave Mode Audio Serial Port Timing: Left-Justified, Right-Justified, and Philips I S
One Frame 1/fS
tLRCKPW
LRCK
BCK
tBCKHL
tBCKP
SDOUT1
tBCKDO
PARAMETER
DESCRIPTION
LRCK Period Width
BCK Period
MIN
tBCKP
39
M AX
UNITS
tLRCKPW
µ
1/fS −tBCKP
s
tBCKP
ns
ns
ns
tBCKHL
tBCKDO
BCK High/Low Time
17.5
SDOUT Data Output Delay from BCK Falling Edge
10
Figure 9. Slave Mode Audio Serial Port Timing: Time Division Multiplexed (TDM) Formats
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DSD DATA PORT OPERATION
HIGH-PASS FILTER
The DSD data port consists of a single DSD data clock
signal, DSDCLK (pin 24), along with four synchronous
DSD data lines, DSD1 (pin 25), DSD2 (pin 26), DSD3 (pin
27), and DSD4 (pin 28). The data lines correspond to
Channels 1 through 4, respectively. The DSD output or
input data rate is determined by the sampling mode
settings for the device, discussed in the Sampling Modes
section of this datasheet.
A digital high-pass filter is available for removing the DC
component of the digitized input signal. The filter is located
at the output of the digital decimation filter, and is available
only when using PCM output data formats. The high-pass
filter can be enabled or disabled for all four channels using
the HPFD input (pin 38). Driving the HPFD input low
enables the high-pass filter. Driving the HPFD input high
disables the high-pass filter.
For DSD output data, the serial port is configured in Master
mode, with the DSDCLK derived from the system clock
input, SCKI. The DSDCLK is equivalent to the
oversampling clock supplied to the delta-sigma
modulators. The DSD data outputs, DSD1 through DSD4,
are synchronous to the DSDCLK. The clock and data lines
are then connected to a data capture device for storage
and processing.
The −3dB corner frequency for the high-pass filter scales
with the output sampling rate, where f−3dB = fS/48000,
where fS is the output sampling rate.
CLIPPING FLAGS
The PCM4204 includes a clipping flag output for each
channel. The outputs are designated CLIP1 (pin 34),
CLIP2 (pin 35), CLIP3 (pin 36), and CLIP4 (pin 37),
corresponding to Channels 1 through 4, respectively.
The DSD input mode, the data port is configured as an
input port, with DSD clock and data lines driven from an
external data source. The Audio Serial Port is configured
in Master mode, with the LRCK and BCK clocks derived
from the system clock input, SCKI. The PCM data format
is set to 24-bit Right-Justified. The input data is processed
by the digital decimation filter and output as PCM data at
the audio serial port.
A clipping flag is forced high as soon as the digital output
of the decimation filter exceeds the full-scale range for the
corresponding channel. The clipping flag output is held
high for a maximum of (256 x N) / fS seconds, where N =
128 for Single Rate sampling mode, 256 for Dual Rate
sampling mode, and 512 for Quad Rate sampling mode.
If the decimation filter output does not exceed the full-scale
range during the initial hold period, the output returns to a
low state upon termination of the hold period.
Figure 10 illustrates the DSD port timing for both the DSD
output and input modes.
DSDCLK
tDCKP
tDCKHL
DSD1
DSD2
DSD3
Input
DSD4
tDS
tDH
DSD1
DSD2
DSD3
DSD4
Output
tDCKDO
DESCRIPTION
MIN
MAX
UNITS
PARAM ETER
tDCKP
ns
ns
ns
DSDCLK Cycle Time
DSDCLK High/Low Time
Data Setup Time
156
70
tDCKHL
tDS
10
10
tDH
10
10
10
ns
ns
Data Hold Time
tDCKDO
DSD Data Output Delay from DSDCLK Falling
Figure 10. DSD Data Port Timing
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SBAS327A − JUNE 2004 − REVISED SEPTEMBER 2004
forced low. Once the initialization sequence is completed,
the PCM4204 output is enabled. Figure 11 shows the
power-on reset sequence timing.
RESET OPERATION
The PCM4204 includes two reset functions: power-on and
externally controlled. This section describes the operation
of each of these functions.
The user may force a reset initialization sequence at any
time while the system clock input is active by utilizing the
RST input (pin 10). The RST input is active low, and
requires a minimum low pulse width of 40ns. The
low-to-high transition of the applied reset signal forces an
initialization sequence to begin. As in the case of the
power-on reset, the initialization sequence requires 1024
system clock periods for completion. Figure 12 illustrates
the reset sequence initiated when using the RST input.
On power-up, the internal reset signal is forced low, forcing
the PCM4204 into a reset state. The power-on reset circuit
monitors the VDD1, VDD2, VDD3, VCC1, and VCC2 power
supply. When the VDD supply exceeds +2.0V ( 400mV)
and VDD1 and VDD2 supply exceeds +4.0V ( 400mV), the
internal reset signal is forced high. The PCM4204 then
waits for the system clock input (SCKI) to become active.
Once the system clock has been detected, the initialization
sequence begins. The initialization sequence requires
1024 system clock periods for completion. During the
initialization sequence, the ADC output data pins are
Figure 13 shows the state of the audio data outputs for the
PCM4204 before, during and after the reset operations.
~ 4.0V
VCC1
VCC2
0V
~ 2.0V
0V
V
VDD
VDD
DD1
2
3
Internal
Reset
1024 System Clock Periods
Required for Initialization
0V
0V
SCKI
System Clock
Indeterminate
or Inactive
Figure 11. Power-On Reset Sequence
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t
> 40ns
RSTL
RST
0V
0V
1024 System Clock Periods
Required for Initialization
Internal
Reset
SCKI
0V
Figure 12. External Reset Sequence
HI
Internal
Reset
LO
Output
Data Pins
Outputs are Forced Low
Outputs are Forced Low
Valid Output Data
Valid Output Data
for 1024 SCKI Periods
Initialization
Period
Figure 13. ADC Digital Output State for Reset Operations
24
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SBAS327A − JUNE 2004 − REVISED SEPTEMBER 2004
A single ground plane is utilized for the analog and digital
ground connections. This approach ensures a low
impedance connection between the analog, digital, and
substrate ground pins. The +5V analog and +3.3V digital
power connections are provided from separate supplies.
POWER-DOWN OPERATION
The PCM4204 can be forced to a power-down state by
applying a low level to the RST input (pin 10) for a minimum
of 65,536 system clock cycles. In power-down mode, all
internal clocks are stopped, and output data pins are
forced low. The system clock may then be removed to
conserve additional power. Before exiting power-down
mode, the system and audio clocks should be restarted.
Once the clocks are active, the RST input may be driven
high, which initiates a reset initialization sequence.
Figure 14 illustrates the state of the output data pins
before, during, and upon exiting the power-down state.
Figure 16 illustrates an example input buffer circuit,
designed for balanced differential input signals. This circuit
is utilized on the PCM4204EVM evaluation board. The
2.7nF and 100pF capacitors shown at the output of the
buffer should be located as close as possible to the analog
input pins of the PCM4204. The buffer shown in Figure 16
can be easily made to function as a single ended to
differential converter by simply grounding the (−) input
terminal of the buffer circuit.
APPLICATIONS INFORMATION
The input impedance for the VCOMIN pin of the OPA1632
is relatively low and will load down the VCOM12 or VCOM34
outputs from the PCM4204. A voltage follower circuit is
required to buffer these outputs, with a typical circuit
configuration shown in Figure 17. An OPA227 is utilized as
the buffer for the PCM4204EVM evaluation board.
However, alternative op amps with comparable
performance may be substituted.
A typical connection diagram for the PCM4204 is shown
in Figure 15. Capacitors for power supply and reference
bypassing are shown with recommended values. Bypass
capacitors should be located as close as possible to the
power supply and reference pins of the PCM4204. Due to
its small size, the 0.1µF capacitor can be located on the
component (top) side of the board, while the larger 33µF
capacitor can be located on the solder (bottom) side of the
board.
HI
RST
LO
Outputs are
Forced Low
Outputs are
Forced Low
Output
Data Pins
Outputs are
Forced Low
Valid Output Data
Valid Output Data
1024
65,536
SCKI Periods
Required for
Initialization
SCKI Periods
Enter
Power Down
State
Figure 14. ADC Digital Output State for Power-Down Operations
25
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SBAS327A − JUNE 2004 − REVISED SEPTEMBER 2004
100Ω
24
DSDCLK
DSD1
25
DSD Data
26
Storage or
DSD2
Processing
27
28
1
2
DSD3
VIN1−
A1
DSD4
VIN1+
100Ω
33µF
15
29
30
31
32
64
63
62
61
+
SCKI
V
REF12+
0.1µF
VREF12−
BCK
0.1µF
AGND4
VCOM12
LRCK
PCM Audio
to
DSP, DIT, etc.
Master
Clock
SDOUT1
SDOUT2
59
58
VIN2+
A2
10
11
12
13
14
17
18
19
20
34
35
36
37
38
39
Analog
Inputs
RST
VIN2−
TEST
FS0
55
54
VIN3+
A3
FS1
VIN3−
FS2
52
51
S/M
V
COM34
FMT0
FMT1
FMT2
CLIP1
CLIP2
CLIP3
CLIP4
HPFD
SUB
AGND3
CONTROL
via
0.1µF
33µF
0.1µF
50
49
48
47
VREF34−
PCM4204
Logic, µP, etc.
+
VREF34+
VIN4+
A4
VIN4−
33µF
5
6
+
VCC1
0.1µF
0.1µF
AGND1
+3.3VD
µ
33 F
33µF
9
8
VDD1
44
43
+
+
VCC2
0.1µF
DGND1
AGND2
33µF
23
22
VDD2
+5VA
+
0.1µF
3
DGND2
NC
NC
NC
NC
NC
NC
NC
NC
NC
4
A1 through A4 are analog input buffers.
Refer to Figure 16 for an example circuit.
21
45
46
53
56
57
60
33µF
40
41
VDD3
All capacitor values are in microfarads (µF).
The 0.1µF caps are X7R ceramic chip type.
+
0.1µF
DGND3
µ
The 33 F caps are Low ESR tantalum or
X7R multi−layer ceramic chip type.
7
16
33
42
BGND1
BGND2
BGND3
BGND4
Figure 15. Typical Connection Diagram
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SBAS327A − JUNE 2004 − REVISED SEPTEMBER 2004
Ω
270
1nF
−
15V
µ
10 F
+
µ
0.1 F
6
7
100pF
Ω
Ω
1k
1k
Ω
Ω
40.2
40.2
8
1
5
4
(+)
EN
−
+
To VIN
Differential
Analog Input
OPA1632
2.7nF
−
( )
VOCM
To VIN
100pF
2
3
Ω
1k
From
Buffered VCOM
in Figure 17.
µ
0.01 F
µ
0.1 F
µ
10 F
+
+15V
1nF
Ω
270
Figure 16. Example Input Buffer Circuit
OPA227
or equivalent
PCM4204
VCOM12
or
To
µ
0.1 F
Buffered VCOM
in Figure 16.
VCOM34
Figure 17. Example Buffer Circuit for V
12 and V
34
COM
COM
27
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SBAS327A − JUNE 2004 − REVISED SEPTEMBER 2004
using standard flow soldering techniques. This allows
efficient attachment to the PCB and permits the board
structure to be utilized as a heat sink for the package.
Using a thermal pad identical in size to the die pad and vias
connected to the PCB ground plane, the board designer
can now implement power packaging without additional
thermal hardware (for example, external heat sinks) or the
need for specialized assembly instructions.
PowerPAD THERMALLY ENHANCED PACKAGING
The PowerPAD concept is implemented in standard epoxy
resin package material. The integrated circuit is attached
to the leadframe die pad using thermally conductive epoxy.
The package is molded so that the leadframe die pad is
exposed at a surface of the package. This provides an
extremely low thermal resistance to the path between the
IC junction and the exterior case. The external surface of
the leadframe die pad is located on the PCB side of the
package, allowing the die pad to be attached to the PCB
Figure 18 illustrates a cross-section view of a PowerPAD
package.
Mold Compount
(Epoxy)
IC Die
Wire Bond
Wire Bond
Leadframe Die Pad
Exposed at Base of Package
Die Attach Epoxy
(thermally conductive)
Leadframe
Figure 18. Cross-Section View of a PowerPAD Thermally-Enhanced Package
28
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SBAS327A − JUNE 2004 − REVISED SEPTEMBER 2004
The via connections to the thermal pad and internal ground
plane should be plated completely around the hole, as
opposed to the typical web or spoke thermal relief
connection. Plating entirely around the thermal via
provides the most efficient thermal connection to the
ground plane.
PowerPAD PCB LAYOUT CONSIDERATIONS FOR
THE PCM4204
Figure 19 shows the recommended layer structure for
thermal management when using a PowerPad package
on a 4-layer printed circuit board design. Note that the
thermal pad is placed on both the top and bottom sides of
the board. The ground plane is utilized as the heat sink,
while the power plane is thermally isolated from the
thermal vias.
ADDITIONAL PowerPAD PACKAGE
INFORMATION
Figure 20 shows the required thermal pad etch pattern for
the 64-lead HTQFP package used for the PCM4204. Nine
13 mil (0.33 mm) thermal vias plated with 1 oz. copper are
placed within the thermal pad area for the purpose of
connecting the pad to the ground plane layer. The ground
plane is utilized as a heatsink in this application. It is very
important that the thermal via diameter be no larger than
13mils in order to avoid solder wicking during the reflow
process. Solder wicking results in thermal voids that
reduce heat dissipation efficiency and hampers heat flow
away from the IC die.
Texas Instruments publishes the PowerPAD Thermally
Enhanced Package Application Report (TI literature
number SLMA002), available for download at www.ti.com,
which provides a more detailed discussion of PowerPAD
design and layout considerations. Before attempting a
board layout with the PCM4204, it is recommended that
the hardware engineer and/or layout designer be familiar
with the information contained in this document.
9/20/2004
Package
Thermal Pad
Component
Traces
13mils (0.33mm)
Component (top) Side
Ground Plane
Thermal Via
Power Plane
Thermal Isolation
(power plane only)
Solder (bottom) Side
Package
Thermal Pad
(bottom trace)
Figure 19. Recommended PCB Structure for a 4−Layer Board
29
ꢅ ꢜꢢ ꢏ ꢎ ꢣ ꢏ
www.ti.com
SBAS327A − JUNE 2004 − REVISED SEPTEMBER 2004
Package Outline
Thermal Pad
40mils (1mm)
40mils (1mm)
118mils (3mm)
316mils (8mm)
Thermal Via
13mils (0.33mm)
316mils (8mm)
Figure 20. Thermal Pad Etch and Via Pattern for the 64-Lead HTQFP Package
30
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PCM4204PAPR
PCM4204PAPT
ACTIVE
ACTIVE
HTQFP
HTQFP
PAP
PAP
64
64
1500 RoHS & Green
250 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-10 to 70
-10 to 70
PCM4204
PCM4204
Samples
Samples
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
PCM4204PAPR
HTQFP
PAP
64
1500
330.0
24.4
13.0
13.0
1.5
16.0
24.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HTQFP PAP 64
SPQ
Length (mm) Width (mm) Height (mm)
350.0 350.0 43.0
PCM4204PAPR
1500
Pack Materials-Page 2
GENERIC PACKAGE VIEW
PAP 64
10 x 10, 0.5 mm pitch
HTQFP - 1.2 mm max height
QUAD FLATPACK
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4226442/A
www.ti.com
PACKAGE OUTLINE
TM
PAP0064F
PowerPAD TQFP - 1.2 mm max height
PLASTIC QUAD FLATPACK
10.2
9.8
B
NOTE 3
64
49
PIN 1 ID
1
48
10.2
9.8
12.2
TYP
11.8
NOTE 3
16
33
17
32
A
0.27
64X
60X 0.5
0.17
0.08
C A B
4X 7.5
C
SEATING PLANE
1.2 MAX
(0.127)
TYP
SEE DETAIL A
17
32
0.25
GAGE PLANE
(1)
8X (R0.091)
NOTE 4
33
16
0.15
0.05
0.08 C
0 -7
0.75
0.45
6.5
5.3
DETAIL A
65
A
17
TYPICAL
20X (R0.137)
NOTE 4
1
48
49
64
4226412/A 11/2020
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs.
4. Strap features may not be present.
5. Reference JEDEC registration MS-026.
www.ti.com
EXAMPLE BOARD LAYOUT
TM
PAP0064F
PowerPAD TQFP - 1.2 mm max height
PLASTIC QUAD FLATPACK
(8)
NOTE 8
(6.5)
SYMM
SOLDER MASK
49
64
DEFINED PAD
64X (1.5)
(R0.05)
TYP
1
48
64X (0.3)
65
(11.4)
SYMM
(1.1 TYP)
60X (0.5)
33
16
(
0.2) TYP
VIA
METAL COVERED
32
17
SEE DETAILS
BY SOLDER MASK
(1.1 TYP)
(11.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:6X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4226412/A 11/2020
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. See technical brief, Powerpad thermally enhanced package,
Texas Instruments Literature No. SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled,
plugged or tented.
10. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
TM
PAP0064F
PowerPAD TQFP - 1.2 mm max height
PLASTIC QUAD FLATPACK
(6.5)
BASED ON
0.125 THICK STENCIL
SYMM
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
64
49
64X (1.5)
1
48
64X (0.3)
(R0.05) TYP
SYMM
65
(11.4)
60X (0.5)
33
16
METAL COVERED
BY SOLDER MASK
17
32
(11.4)
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:6X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
7.27 X 7.27
6.5 X 6.5 (SHOWN)
5.93 X 5.93
0.125
0.15
0.175
5.49 X 5.49
4226412/A 11/2020
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
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TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023, Texas Instruments Incorporated
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