PCM5101A-Q1 [TI]
具有 32 位、384kHz PCM 接口的汽车类 2VRMS DirectPath™、106dB 音频立体声 DAC;
| 型号： | PCM5101A-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 32 位、384kHz PCM 接口的汽车类 2VRMS DirectPath™、106dB 音频立体声 DAC PC |
| 文件： | 总39页 (文件大小：1766K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1
www.ti.com.cn
ZHCSBM3A –SEPTEMBER 2013–REVISED SEPTEMBER 2013
2VRMS DirectPath™，具有 32 位，384kHz 脉冲编码调制 (PCM) 接口的
112，106，100dB 音频立体声数模转换器 (DAC)
查询样品: PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1
1
特性
•
•
当 LRCK 和 BCK 被置为无效时，自动进入省电模
式
23
•
符合汽车应用要求
1.8V 或 3.3V 故障安全低压互补金属氧化物半导体
(LVCMOS) 数字输入
•
具有符合 AEC-Q100 的下列结果：
–
–
–
器件温度 1 级：-40°C 至 125°C 的环境运行温
度范围
•
•
硬件配置
单电源运行：
器件人体模型 (HBM) 静电放电 (ESD) 分类等级
H2
–
3.3V 模拟，1.8V 或 3.3V 数字
•
集成型加电复位
器件充电器件模型 (CDM) ESD 分类等级 C4B
•
•
•
•
•
•
市场领先的低带外噪声
应用范围
可选数字滤波器延迟与性能
无需隔离直流电流的电容器
集成的负电荷泵
•
•
•
•
•
•
汽车应用
车用信息娱乐
音频视频 (A/V) 接收器
数字多用途光盘 (DVD)，蓝光光盘 (BD) 播放器
高清电视 (HDTV) 接收器
需要 2VRMS 音频输出的应用
用于采样率变化或者时钟暂停的内部无爆音控制
智能静噪系统；针对带有无爆音操作的 120dB 静
噪信噪比 (SNR) 的软上升或下降斜坡和模拟静噪
(AMUTE)
•
具有对于内部生成 SCK 的 BCK 基准的集成高性能
音频锁相环路 (PLL)
说明
PCM510xA-Q1 是单片互补金属氧化物半导体 (CMOS)
集成电路系列产品，此产品包括一个立体声数模转换器
和小型薄型小外形尺寸 (TSSOP) 封装内的附加支持电
路。 PCM510xA-Q1 使用 TI 的高级分段数模转换器
(DAC) 架构的最新一代产品来实现出色的动态性能并
提升了对于时钟抖动的耐受度。
•
•
•
•
支持 1.8V 数字输入接口
小型 20 引脚薄型小外形尺寸 (TSSOP) 封装
接受 16，24 和 32 位音频数据
PCM 数据格式：I2S，左对齐
LINE OUT
Current
Segment
DAC
DIN (i2s)
Current
Segment
DAC
Zero
Data
Detector
Advanced Mute Control
Clock Halt
Detection
PCM510xA-Q1
CPVDD (3.3V)
AVDD (3.3V)
DVDD (1.8V or 3.3V)
GND
LRCK
BCK
Power
Supply
PLL Clock
MCK
UVP/Reset
POR
Ch. Pump
图 1. PCM510xA-Q1 功能方框图
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
System Two Cascade, Audio Precision are trademarks of Audio Precision.
DirectPath is a trademark of Texas, Instruments, Inc..
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
English Data Sheet: SLAS979
PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1
ZHCSBM3A –SEPTEMBER 2013–REVISED SEPTEMBER 2013
www.ti.com.cn
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Typical Performance (3.3-V Power Supply)
Parameter
PCM5102A-Q1
PCM5101A-Q1
PCM5100A-Q1
100 dB
SNR
112
106
106
–92
Dynamic Range
112
–93
100 dB
Total Harmonic Distortion + Noise (THD+N) at -1 dBFS
Full Scale Output
–90 dB
2.1 VRMS (GND center)
20 tS
Normal 8 × Oversampling Digital Filter Latency:
Low Latency 8 × Oversampling Digital Filter Latency:
Sampling Frequency:
3.5 tS
8 kHz to 384 kHz
System Clock Multiples (fSCK):
64, 128, 192, 256, 384, 512, 768, 1024, 1152, 1536, 2048, 3072; up to 50 MHz
DESCRIPTION (CONTINUED)
The PCM510xA-Q1 provides 2.1-VRMS ground centered outputs, allowing designers to eliminate DC blocking
capacitors on the output, as well as external muting circuits traditionally associated with single supply line drivers.
The integrated line driver surpasses all other charge-pump based line drivers by supporting loads down to 1 kΩ.
By supporting loads down to 1 kΩ, the PCM510xA-Q1 can essentially drive up to 10 products in parallel. For
instance, liquid crystal display television (LCD TV), DVD-R, A/V Receivers, and so forth.
The integrated PLL on the device removes the requirement for a system clock (commonly known as master
clock), allowing a 3-wire I2S connection and reducing system electromagnetic interference (EMI).
Intelligent clock error and PowerSense undervoltage protection utilizes a two level mute system for pop-free
performance. Upon clock error or system power failure, the device digitally attenuates the data (or last known
good data), then mutes the analog circuit
Compared with existing DAC technology, the PCM510xA-Q1 family offers up to 20-dB lower out-of-band noise,
reducing EMI and aliasing in downstream amplifiers and analog-to-digital converters (ADCs) from traditional 100-
kHz OBN measurements all the way to 3 MHz.
The PCM510xA-Q1 accepts industry-standard audio data formats with 16- to 32-bit data. Sample rates up to 384
kHz are supported.
Table 1. Differences Between PCM510xA-Q1 Devices
TA
Orderable Part Number
PCM5100AQPWRQ1
PCM5101AQPWRQ1
PCM5102AQPWRQ1
Dynamic Range
100 dB
SNR
THD
TOP-SIDE MARKING
P5100AQ1
100 dB
106 dB
112 dB
–90 dB
–92 dB
–93 dB
–40°C to 125°C
106 dB
Preview
112 dB
Preview
2
Copyright © 2013, Texas Instruments Incorporated
PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1
www.ti.com.cn
ZHCSBM3A –SEPTEMBER 2013–REVISED SEPTEMBER 2013
DEVICE INFORMATION
PIN FUNCTIONS, PCM510xA-Q1
PCM510xA-Q1
(Top View)
PIN FUNCTIONS, PCM510xA-Q1
PIN
I/O
DESCRIPTION
NAME
CPVDD
CAPP
CPGND
CAPM
VNEG
OUTL
OUTR
AVDD
AGND
DEMP
FLT
NO.
1
—
O
—
O
O
O
O
-—
—
I
Charge pump power supply, 3.3 V
2
Charge pump flying capacitor terminal for positive rail
Charge pump ground
3
4
Charge pump flying capacitor terminal for negative rail
Negative charge pump rail terminal for decoupling, –3.3 V
Analog output from DAC left channel
Analog output from DAC right channel
Analog power supply, 3.3 V
5
6
7
8
9
Analog ground
10
11
12
13
14
15
16
17
De-emphasis control for 44.1-kHz sampling rate(1): Off (Low), On (High)
Filter select: Normal latency (Low), Low latency (High)
System clock input(1)
Audio data bit clock input(1)
Audio data input(1)
Audio data word clock input(1)
Audio format selection: I2S (Low), Left justified (High)
Soft mute control(1): Soft mute (Low), soft un-mute (High)
I
SCK
I
BCK
I
DIN
I
LRCK
FMT
I
I
XSMT
I
Internal logic supply rail terminal for decoupling, or external 1.8-V supply
terminal
LDOO
18
—
DGND
DVDD
19
20
—
—
Digital ground
Digital power supply, 1.8 V or 3.3 V
(1) Failsafe LVCMOS Schmitt trigger input
Copyright © 2013, Texas Instruments Incorporated
3
PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1
ZHCSBM3A –SEPTEMBER 2013–REVISED SEPTEMBER 2013
www.ti.com.cn
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–25
MAX
UNIT
AVDD, CPVDD, DVDD
Supply Voltage
3.9
2.25
2.25
3.9
LDOO with DVDD at 1.8 V (See Figure 40 and Figure 42)
DVDD at 1.8 V
Digital Input Voltage
V
DVDD at 3.3 V
Analog Input Voltage
3.9
Operating Temperature Range
Storage Temperature Range
125
150
2
°C
–65
Electrostatic Discharge
(ESD) Rating
Human Body Model (HBM) AEC-Q100 Classification Level H2
Charged Device Model (CDM) AEC-Q100 Classification Level C4B
kV
V
750
THERMAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PCM5100A-Q1
THERMAL METRIC(1)
UNIT
(20 PINS)
91.2
1
θJA
Junction-to-ambient thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
ψJT
ψJB
41.5
25.3
42
°C/W
θJC(top)
θJB
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
ELECTRICAL CHARACTERISTICS
All specifications at TA = –40 to 125°C, AVDD = CPVDD = DVDD = 3.3 V, fS = 48 kHz, system clock = 512 fS and 24-bit data
unless otherwise noted.
PARAMETER
Resolution
Data Format (PCM Mode)
Audio data interface format
TEST CONDITIONS
MIN
TYP
MAX
UNIT
16
24
32
Bits
I2S, left justified
16, 24, 32-bit acceptable
MSB First, 2s Complement
8
Audio data bit length
Audio data format
Sampling frequency
(1)
fS
384
kHz
64, 128, 192, 256, 384, 512, 768, 1024, 1152, 1536, 2048,
System clock frequency
or 3072
fSCK, up to 50 MHz
Digital Input/Output
Logic Family: 3.3-V LVCMOS compatible
VIH
VIL
IIH
0.7 × DVDD
Input logic level
Input logic current
Output logic level
V
0.3 × DVDD
VIN = VDD
10
µA
IIL
VIN = 0 V
–10
VOH
VOL
IOH = –4 mA
IOL = 4 mA
0.8 × DVDD
V
0.22 × DVDD
Logic Family 1.8-V LVCMOS compatible
VIH
VIL
0.7 × DVDD
Input logic level
V
0.3 × DVDD
(1) One sample time is defined as the reciprocal of the sampling frequency. 1 tS = 1 / fS
4
Copyright © 2013, Texas Instruments Incorporated
PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1
www.ti.com.cn
ZHCSBM3A –SEPTEMBER 2013–REVISED SEPTEMBER 2013
ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = –40 to 125°C, AVDD = CPVDD = DVDD = 3.3 V, fS = 48 kHz, system clock = 512 fS and 24-bit data
unless otherwise noted.
PARAMETER
TEST CONDITIONS
VIN = VDD
VIN = 0 V
MIN
TYP
MAX
10
UNIT
IIH
IIL
Input logic current
µA
–10
Copyright © 2013, Texas Instruments Incorporated
5
PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1
ZHCSBM3A –SEPTEMBER 2013–REVISED SEPTEMBER 2013
www.ti.com.cn
ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = –40 to 125°C, AVDD = CPVDD = DVDD = 3.3 V, fS = 48 kHz, system clock = 512 fS and 24-bit data
unless otherwise noted.
PARAMETER
TEST CONDITIONS
IOH = –2 mA
MIN
TYP
MAX
UNIT
VOH
VOL
0.8 × DVDD
Output logic level
V
IOL = 2 mA
0.22 × DVDD
Dynamic Performance (PCM Mode)(2)(3)(4)
fS = 48 kHz
fS = 96 kHz
fS = 192 kHz
–93, –92, –90 –83, –82, –80
–93, –92, –90
THD+N at –1 dBFS(3)
–93, –92, –90
EIAJ, A-weighted, fS = 48 kHz 106, 100, 95
EIAJ, A-weighted, fS = 96 kHz
112, 106, 100
112, 106, 100
Dynamic range(3)
EIAJ, A-weighted, fS = 192
kHz
112, 106, 100
EIAJ, A-weighted, fS = 48 kHz
EIAJ, A-weighted, fS = 96 kHz
112, 106, 100
112, 106, 100
112, 106, 100
SNR
Signal-to-noise ratio(3)
dB
EIAJ, A-weighted, fS = 192
kHz
EIAJ, A-weighted, fS = 48 kHz
EIAJ, A-weighted, fS = 96 kHz
113
123
123
123
Signal-to-noise ratio with
AMUTE(3)(5)
EIAJ, A-weighted, fS = 192
kHz
fS = 48 kHz
fS = 96 kHz
fS = 192 kHz
100, 95, 90
109, 103, 97
109, 103, 97
109, 103, 97
Channel separation
Analog Output
Output voltage
2.1
VRMS
Gain error
–7
–7
±2
7
% of
FSR
Gain mismatch,
channel-to-channel
% of
FSR
±2
±1
7
5
Bipolar zero (BPZ) error
Load impedance
At BPZ
–5
1
mV
kΩ
Filter Characteristics–1: Normal
Pass band
0.45 fS
±0.02
Stop band
0.55 fS
–60
Stop band attenuation
Pass-band ripple
dB
s
Delay time
20 tS
Filter Characteristics–2: Low Latency
Pass band
0.47 fS
±0.0001
Stop band
0.55 fS
–52
Stop band attenuation
Pass-band ripple
dB
s
Delay time
3.5 tS
(2) Filter condition: THD+N: 20-Hz HPF, 20-kHz AES17 LPF. Dynamic range: 20-Hz HPF, 20-kHz AES17 LPF. A-weighted SNR: 20-Hz
HPF, 20-kHz AES17 LPF. A-weighted Channel Separation: 20-Hz HPF, 20-kHz AES17 LPF. Analog performance specifications are
measured using the System Two Cascade™ audio measurement system by Audio Precision™ in the record management system
(RMS) mode.
(3) Output load is 10 kΩ, with 470-Ω output resistor and a 2.2-nF shunt capacitor (see recommended output filter).
(4) Values shown for three devices PCM5102A-Q1, PCM5101A-Q1, PCM5100A-Q1, respectively.
(5) Assert XSMT or both left-channel and right-channel PCM data are BPZ.
6
Copyright © 2013, Texas Instruments Incorporated
PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1
www.ti.com.cn
ZHCSBM3A –SEPTEMBER 2013–REVISED SEPTEMBER 2013
ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = –40 to 125°C, AVDD = CPVDD = DVDD = 3.3 V, fS = 48 kHz, system clock = 512 fS and 24-bit data
unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDC
VDC
Power Supply Requirements
DVDD
DVDD
AVDD
Digital supply voltage
Digital supply voltage
Analog supply voltage
Target DVDD = 1.8 V
Target DVDD = 3.3 V
1.65
1.8
3.3
3.3
3.3
7
1.95
3.6
3
3
3
3.6
CPVDD Charge-pump supply voltage
3.6
fS = 48 kHz
fS = 96 kHz
fS = 192 kHz
fS = 48 kHz
fS = 96 kHz
fS = 192 kHz
IDD
DVDD supply current at 1.8 V(6)
8
mA
9
7
IDD
IDD
IDD
DVDD supply current at 1.8 V(7)
DVDD supply current at 1.8 V(8)
DVDD supply current at 3.3 V(6)
8
mA
mA
mA
9
0.3
7
fS = 48 kHz
fS = 96 kHz
fS = 192 kHz
fS = 48 kHz
fS = 96 kHz
fS = 192 kHz
12
13
8
9
8
IDD
IDD
ICC
DVDD supply current at 3.3 V(7)
DVDD supply current at 3.3 V(8)
AVDD / CPVDD Supply Current(6)
9
mA
mA
mA
10
0.5
11
0.8
16
fS = 48 kHz
fS = 96 kHz
fS = 192 kHz
fS = 48 kHz
fS = 96 kHz
fS = 192 kHz
fS = n/a
11
11
22
32
ICC
AVDD / CPVDD Supply Current(7)
AVDD / CPVDD Supply Current(8)
22
mA
mA
mW
22
ICC
0.2
48.9
50.7
52.5
85.2
87
0.4
fS = 48 kHz
185
Power Dissipation, DVDD = 1.8 V(6) fS = 96 kHz
fS = 192 kHz
fS = 48 kHz
Power Dissipation, DVDD = 1.8 V(7) fS = 96 kHz
fS = 192 kHz
187
mW
mW
mW
88.8
1.2
59.4
62.7
66
Power Dissipation, DVDD = 1.8 V(8) fS = n/a (power down mode)
fS = 48 kHz
92.4
148.5
4
Power Dissipation, DVDD = 3.3 V(6) fS = 96 kHz
fS = 192 kHz
fS = 48 kHz
99
Power Dissipation, DVDD = 3.3 V(7) fS = 96 kHz
102.3
105.6
2.3
mW
mW
fS = 192 kHz
Power Dissipation, DVDD = 3.3 V(8) fS = n/a (power down mode)
(6) Input is BPZ data.
(7) Input is 1 kHz - 1 dBFS data
(8) Power down mode
Copyright © 2013, Texas Instruments Incorporated
7
PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1
ZHCSBM3A –SEPTEMBER 2013–REVISED SEPTEMBER 2013
www.ti.com.cn
TYPICAL CHARACTERISTICS
All specifications at TA = 25°C, AVDD = CPVDD = DVDD = 3.3 V, fS = 48 kHz, system clock = 512 fS and 24-bit data unless
otherwise noted.
PCM5100A-Q1 THD+N
PCM5101A-Q1 THD+N
vs
vs
Input Level
Input Level
10
10
-10
-10
-30
-50
-70
-30
-50
-70
-90
-90
-110
-110
-100
-80
-60 -40
Input Level [dBFS]
-20
0
-100
-80
-60 -40
Input Level [dBFS]
-20
0
Figure 2.
Figure 3.
PCM5102A-Q1 THD+N
vs
Input Level
10
-10
-30
-50
-70
-90
-110
-100
-80
-60 -40
Input Level [dBFS]
-20
0
Figure 4.
8
Copyright © 2013, Texas Instruments Incorporated
PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1
www.ti.com.cn
ZHCSBM3A –SEPTEMBER 2013–REVISED SEPTEMBER 2013
TYPICAL CHARACTERISTICS (continued)
All specifications at TA = 25°C, AVDD = CPVDD = DVDD = 3.3 V, fS = 48 kHz, system clock = 512 fS and 24-bit data unless
otherwise noted.
PCM5100A-Q1 Fast Fourier Transform (FFT) Plot at BPZ
with AMUTE
PCM5101A-Q1 FFT Plot at BPZ with AMUTE
-20
-40
-20
-40
-60
-60
-80
-80
-100
-120
-140
-160
-180
-100
-120
-140
-160
-180
0
5
10
Frequency [kHz]
15
20
0
5
10
Frequency [kHz]
15
20
Figure 5.
Figure 6.
PCM5102A-Q1 FFT Plot at BPZ with AMUTE
-20
-40
-60
-80
-100
-120
-140
-160
-180
0
5
10
Frequency [kHz]
15
20
Figure 7.
Copyright © 2013, Texas Instruments Incorporated
9
PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1
ZHCSBM3A –SEPTEMBER 2013–REVISED SEPTEMBER 2013
www.ti.com.cn
TYPICAL CHARACTERISTICS (continued)
All specifications at TA = 25°C, AVDD = CPVDD = DVDD = 3.3 V, fS = 48 kHz, system clock = 512 fS and 24-bit data unless
otherwise noted.
PCM5100A-Q1 FFT Plot at –60 dB to 300 kHz
PCM5101A-Q1 FFT Plot at –60 dB to 300 kHz
0
0
-20
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-100
-120
-140
-160
0
50
100
150
Frequency [kHz]
200
250
300
0
50
100
150
Frequency [kHz]
200
250
300
Figure 8.
Figure 9.
PCM5102A-Q1 FFT Plot at –60 dB to 300 kHz
0
-20
-40
-60
-80
-100
-120
-140
-160
0
50
100
150
Frequency [kHz]
200
250
300
Figure 10.
10
Copyright © 2013, Texas Instruments Incorporated
PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1
www.ti.com.cn
ZHCSBM3A –SEPTEMBER 2013–REVISED SEPTEMBER 2013
APPLICATION INFORMATION
Reset and System Clock Functions
Power-On Reset Function
Power-On Reset, Digital Power Supply Voltage 3.3-V Supply
The PCM510xA-Q1 includes a power-on reset function shown in Figure 11. With supply voltage greater than 2.8
V, the power-on reset function is enabled. After the initialization period, the PCM510xA-Q1 is set to its default
reset state.
3.3V
2.8V
AVDD, DVDD,
CPVDD
Internal Reset
Reset Removal
Internal Reset
4 ms
I2S Clocks
SCK, BCK, LRCK
Figure 11. Power-On Reset Timing, DVDD = 3.3 V
Copyright © 2013, Texas Instruments Incorporated
11
PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1
ZHCSBM3A –SEPTEMBER 2013–REVISED SEPTEMBER 2013
www.ti.com.cn
Power-On Reset, Digital Power Supply Voltage 1.8-V Supply
The PCM510xA-Q1 includes a power-on reset function shown in Figure 12 operating at DVDD = 1.8 V. With
analog power supply voltage greater than approximately 2.8 V, charge-pump power supply voltage greater than
approximately 2.8 V, and digital power supply voltage greater than approximately 1.5 V, the power-on reset
function is enabled. After the initialization period, the PCM510xA-Q1 is set to its default reset state.
3.3V
2.8V
AVDD, CPVDD
1.8V
1.5V
DVDD, LDOO
Internal Reset
Reset Removal
Internal Reset
4 ms
I2S Clocks
SCK, BCK, LRCK
Figure 12. Power-On Reset Timing, DVDD = 1.8 V
12
Copyright © 2013, Texas Instruments Incorporated
PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1
www.ti.com.cn
ZHCSBM3A –SEPTEMBER 2013–REVISED SEPTEMBER 2013
System Clock Input
The PCM510xA-Q1 requires a system clock to operate the digital interpolation filters and advanced segment
DAC modulators. The system clock is applied at the SCK input (pin 12) and supports up to 50 MHz. The
PCM510xA-Q1 system-clock detection circuit automatically senses the system-clock frequency. Common audio
sampling frequencies in the bands of 8 kHz, 16 kHz, (32 kHz – 44.1 kHz – 48 kHz), (88.2 kHz – 96 kHz), (176.4
kHz – 192 kHz), and 384 kHz with ±4% tolerance are supported. Values in the parentheses are grouped when
detected, for example, 88.2 kHz and 96 kHz are detected as double rate, 32 kHz, 44.1 kHz and 48 kHz is
detected as a single rate.
The sampling frequency detector sets the clock for the digital filter, delta sigma modulator (DSM) and the
negative charge pump (NCP) automatically. Table 2 shows examples of system clock frequencies for common
audio sampling rates.
SCK rates that are not common to standard audio clocks, between 1 MHz and 50 MHz, are only supported in
software mode, available only in the PCM512x and PCM514x devices, by configuring various PLL and clock-
divider registers. This programmability allows the device to become a clock master and drive the host serial port
with LRCK and BCK, from a non-audio related clock (for example, using 12 MHz to generate 44.1 kHz (LRCK)
and 2.8224 MHz (BCK)).
Figure 13 shows the timing requirements for the system clock input. For optimal performance, use a clock source
with low phase jitter and noise.
Table 2. System Master Clock Inputs for Audio Related Clocks
System Clock Frequency (fSCK) (MHz)
Sampling
Frequency
64 fS
128 fS
192 fS
256 fS
2.0480
384 fS
3.0720
512 fS
4.0960
768 fS
6.1440
1024 fS
8.1920
1152 fS
9.2160
1536 fS
12.2880
24.5760
49.1520
2048 fS
16.3840
36.8640
3072 fS
24.5760
49.1520
(1)
8 kHz
16 kHz
–
1.0240(2) 1.5360(2)
2.0480(2) 3.0720(2)
4.0960(2) 6.1440(2)
5.6488(2) 8.4672(2)
6.1440(2) 9.2160(2)
11.2896(2) 16.9344
12.2880(2) 18.4320
(1)
–
4.0960
6.1440
8.1920
12.2880
24.5760
33.8688
36.8640
16.3840
32.7680
45.1584
49.1520
18.4320
36.8640
(1)
(1)
(1)
32 kHz
–
8.1920
12.2880
16.9344
18.4320
33.8688
36.8640
16.3840
22.5792
24.5760
45.1584
49.1520
–
–
(1)
(1)
(1)
(1)
(1)
44.1 kHz
48 kHz
–
11.2896
12.2880
22.5792
24.5760
45.1584
49.1520
–
–
–
–
(1)
(1)
(1)
(1)
(1)
–
–
–
–
–
(1)
(1)
(1)
(1)
(1)
(1)
(1)
88.2 kHz
96 kHz
–
–
–
–
–
–
–
(1)
(1)
(1)
(1)
(1)
(1)
(1)
–
–
–
–
–
–
–
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
176.4 kHz
192 kHz
384 kHz
–
22.5792
24.5760
49.1520
33.8688
36.8640
–
–
–
–
–
–
–
–
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
–
–
–
–
–
–
–
–
–
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
24.5760
–
–
–
–
–
–
–
–
–
–
(1) This system clock rate is not supported for the given sampling frequency.
(2) This system clock rate is supported by PLL mode.
tSCKH
"H"
0.7*DVDD
0.3*DVDD
System Clock
(SCK)
"L"
tSCKL
tSCY
Figure 13. Timing Requirements for SCK Input
Table 3. Timing Requirements for SCK Input
Parameters
Min
20
8
Max
Unit
tSCY
System clock pulse cycle time
1000
ns
DVDD = 1.8 V
DVDD = 3.3 V
DVDD = 1.8 V
DVDD = 3.3 V
tSCKH
System clock pulse width, High
ns
ns
9
8
tSCKL
System clock pulse width, Low
9
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System Clock PLL Mode
The system clock PLL mode allows designers to use a simple 3-wire I2S audio source when driving the output.
The 3-wire source reduces the need for a high frequency SCK, making printed circuit board (PCB) layout easier,
and reduces high frequency EMI.
The device starts up requiring an external SCK input, but if BCK and LRCK start correctly while SCK remains at
ground level for 16 successive LRCK periods, then the internal PLL starts, automatically generating an internal
SCK from the BCK reference. The PCM510xA-Q1 disables the internal PLL when an external SCK is supplied;
specific BCK rates are required to generate an appropriate master clock. Table 4 describes the minimum and
maximum BCK per LRCK for the integrated PLL to automatically generate an internal SCK.
Table 4. BCK Rates (MHz) by LRCK Sample Rate for
PCM510xA-Q1 PLL Operation
BCK (fS)
Sample f (kHz)
32
–
64
8
–
16
–
1.024
2.048
2.8224
3.072
6.144
12.288
24.576
32
1.024
1.4112
1.536
3.072
6.144
12.288
44.1
48
96
192
384
Audio Data Interface
Audio Serial Interface
The audio interface port is a 3-wire serial port, including LRCK (pin 15), BCK (pin 13), and DIN (pin 14). BCK is
the serial audio bit clock, used to clock the serial data present on DIN into the serial shift register of the audio
interface. Serial data is clocked into the PCM510xA-Q1 on the rising edge of BCK. LRCK is the serial audio left
and right word clock.
Table 5. PCM510xA-Q1 Audio Data Formats, Bit Depths and Clock Rates
MAX LRCK
CONTROL MODE
FORMAT
DATA BITS
SCK RATE [x fS]
BCK RATE [x fS]
FREQUENCY [fS]
Up to 192 kHz
384 kHz
128 – 3072 (≤ 50
64, 48, 32
64, 48, 32
I2S or LJ
32, 24, 20, 16
MHz)
Hardware Control
64, 128
The PCM510xA-Q1 requires the synchronization of LRCK and system clock, but does not need a specific phase
relation between LRCK and system clock.
If the relationship between LRCK and system clock changes more than ±5 SCK, internal operation is initialized
within one sample period and analog outputs are forced to the BPZ level until resynchronization between LRCK
and system clock is completed.
If the relationship between LRCK and BCK are invalid more than four LRCK periods, internal operation is
initialized within one sample period and analog outputs are forced to the BPZ level until resynchronization
between LRCK and BCK is completed.
14
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PCM Audio Data Formats and Timing
The PCM510xA-Q1 supports industry-standard audio data formats, including standard I2S and left-justified. Data
formats are selected using the FMT (pin 16), Low for I2S, and high for left-justified.
All formats require binary 2s complement, MSB-first audio data. Figure 14 shows a detailed timing diagram for
the serial audio interface.
LRCK
(Input)
0.5 * DVDD
0.5 * DVDD
tBCH
tBCL
tLB
BCK
(Input)
tBCY
tBL
DATA
(Input)
0.5 * DVDD
tDS
tDH
Figure 14. PCM510xA-Q1 Serial Audio Timing - Slave
Table 6. Audio Interface Slave Timing
Parameters
Min
40
16
16
8
Max
Units
ns
tBCY
tBCL
tBCH
tBL
BCK Pulse Cycle Time
BCK Pulse Width LOW
BCK Pulse Width HIGH
BCK Rising Edge to LRCK Edge
LRCK Edge to BCK Rising Edge
DATA Set Up Time
ns
ns
ns
tLB
8
ns
tDS
8
ns
tDH
DATA Hold Time
8
ns
fBCK
fBCK
BCK frequency at DVDD = 3.3 V
BCK frequency at DVDD = 1.8 V
24.576
12.288
MHz
MHz
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1tS
R-channel
L-channel
LRCK
BCK
Audio data word = 16-bit, BCK = 32, 48, 64fS
1
2
15 16
1
1
1
2
15 16
DATA
MSB
LSB
MSB
LSB
Audio data word = 24-bit, BCK = 48, 64fS
-
,
2
1
2
24
2
23 24
DATA
MSB
LSB
MSB
LSB
Audio data word = 32-bit, BCK = 64fS
1
2
31 32
2
31 32
DATA
MSB
LSB
MSB
LSB
Left Justified Data Format; L-channel = HIGH, R-channel = LOW
Figure 15. Left Justified Audio Data Format
1tS
LRCK
BCK
L-channel
R-channel
Audio data word = 16-bit, BCK = 32, 48, 64fS
1
2
15 16
1
2
15 16
DATA
MSB
LSB
MSB
LSB
Audio data word = 24-bit, BCK = 48, 64fS
2
1
2
23 24
1
23 24
DATA
MSB
LSB
MSB
LSB
Audio data word = 32-bit, BCK = 64fS
1
2
31 32
1
2
31 32
DATA
MSB
LSB
MSB
LSB
I2S Data Format; L-channel = LOW, R-channel = HIGH
Figure 16. I2S Audio Data Format
16
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Function Descriptions
Interpolation Filter
The PCM510xA-Q1 provides two types of interpolation filter. Users can select which filter to use by using the FLT
(pin 11)
Table 7. Digital Interpolation Filter Options
FLT Pin Description
0
1
FIR Normal x8 / x4 / x2 / x1 Interpolation Filters
IIR Low Latency x8 / x4 / x2 / x1 Interpolation Filters
The normal x8 / x4 / x2 / x1 (bypass) interpolation filter is programmed in 256 cycles in one sample time (tS) for
sample rates from 8 kHz to 384 kHz.
Table 8. Normal x8 Interpolation Filter
Parameter
Condition
Value (Typ)
Value (Max)
Units
dB
Filter Gain Pass Band
Filter Gain Stop Band
Filter Group Delay
0 ……. 0.45 fS
0.55 fS ….. 7.455 fS
±0.02
–60
dB
22 tS
s
0
−20
1.0
0.8
0.6
−40
0.4
−60
0.2
−80
0.0
−100
−120
−0.2
−0.4
0
0
1
2
3
4
50
100
150
200
Samples
250
300
350
400
Frequency (x fS)
G012
G023
Figure 17. Normal x8 Interpolation Filter Frequency
Response
Figure 18. Normal x8 Interpolation Filter Impulse
Response
0.05
0.04
0.03
0.02
0.01
0.00
−0.01
−0.02
−0.03
−0.04
−0.05
0.0
0.1
0.2
0.3
0.4
0.5
Frequency (x fS)
G034
Figure 19. Normal x8 Interpolation Filter Passband Ripple
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The normal x4 / x2 / x1 (bypass) interpolation filter is programmed in 256 cycles in one tS for sample rates from 8
kHz to 384 kHz.
Table 9. Normal x4 Interpolation Filter
Parameter
Condition
Value (Typ)
Value (Max)
Units
dB
Filter Gain Pass Band
Filter Gain Stop Band
Filter Group Delay
0 ……. 0.45 fS
0.55 fS ….. 7.455 fS
±0.02
–60
dB
22 tS
s
0
−20
1.0
0.8
0.6
−40
0.4
−60
0.2
−80
0.0
−100
−120
−0.2
−0.4
0
0
1
2
3
4
20
40
60
80
Samples
100
120
140
160
Frequency (x fS)
G009
G020
Figure 20. Normal x4 Interpolation Filter Frequency
Response
Figure 21. Normal x4 Interpolation Filter Impulse
Response
0.05
0.04
0.03
0.02
0.01
0.00
−0.01
−0.02
−0.03
−0.04
−0.05
0.0
0.5
Frequency (x fS)
1.0
G031
Figure 22. Normal x4 Interpolation Filter Passband Ripple
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Normal x2 / x1 (bypass) interpolation filter is programmed in 256 cycles in one tS for sample rates from 8 kHz to
384 kHz.
Table 10. Normal x2 Interpolation Filter
Parameter
Condition
Value (Typ)
Value (Max)
Units
dB
Filter Gain Pass Band
Filter Gain Stop Band
Filter Group Delay
0 ……. 0.45 fS
0.55 fS ….. 7.455 fS
±0.02
–60
dB
22 tS
s
0
−20
1.0
0.8
0.6
−40
0.4
−60
0.2
−80
0.0
−100
−120
−0.2
−0.4
0
1
2
3
4
0
10
20
30
40
50
Samples
60
70
80
90 100
Frequency (x fS)
G006
G017
Figure 23. Normal x2 Interpolation Filter Frequency
Response
Figure 24. Normal x2 Interpolation Filter Impulse
Response
0.05
0.04
0.03
0.02
0.01
0.00
−0.01
−0.02
−0.03
−0.04
−0.05
0.0
0.5
1.0
1.5
2.0
Frequency (x fS)
G028
Figure 25. Normal x2 Interpolation Filter Passband Ripple
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The low-latency x8 / x4 / x2 / x1 (bypass) interpolation filter is programmed in 256 cycles one tS for sample rates
from 8 kHz to 384 kHz.
Table 11. Low latency x8 Interpolation Filter
Parameter
Condition
Value (Typ)
±0.0001
–52
Units
dB
Filter Gain Pass Band
Filter Gain Stop Band
Filter Group Delay
0 ……. 0.45 fS
0.55 fS ….. 7.455 fS
dB
3.5 tS
s
0
−20
1.0
0.8
0.6
−40
0.4
−60
0.2
0.0
−80
−0.2
−0.4
−0.6
−100
−120
0
1
2
3
4
0
50
100
150
200
Samples
250
300
350
400
Frequency (x fS)
G011
G022
Figure 26. Low latency x8 Interpolation Filter
Frequency Response
Figure 27. Low latency x8 Interpolation Filter
Impulse Response
0.00010
0.00008
0.00006
0.00004
0.00002
0.00000
−0.00002
−0.00004
−0.00006
−0.00008
−0.00010
0.0
0.1
0.2
0.3
0.4
0.5
Frequency (x fS)
G033
Figure 28. Low latency x8 Interpolation Filter Passband Ripple
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Table 12. Low latency x4 Interpolation Filter
Parameter
Condition
Value (Typ)
±0.0001
–52
Units
dB
Filter Gain Pass Band
Filter Gain Stop Band
Filter Group Delay
0 ……. 0.45 fS
0.55 fS ….. 3.455 fS
dB
3.5 tS
s
0
1.0
0.8
−20
−40
0.6
0.4
−60
0.2
0.0
−80
−0.2
−0.4
−0.6
−100
−120
0
1
2
3
4
0
20
40
60
80
Samples
100 120 140 160 180
Frequency (x fS)
G008
G019
Figure 29. Low latency x4 Interpolation Filter
Frequency Response
Figure 30. Low latency x4 Interpolation Filter
Impulse Response
0.0001
0.00008
0.00006
0.00004
0.00002
0
−0.00002
−0.00004
−0.00006
−0.00008
−0.0001
0.0
0.5
Frequency (x fS)
1.0
G030
Figure 31. Low latency x4 Interpolation Filter Passband Ripple
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Table 13. Low latency x2 Interpolation Filter
Parameter
Condition
Value (Typ)
±0.0001
–52
Units
dB
Filter Gain Pass Band 0 ……. 0.45 fS
Filter Gain Stop Band 0.55 fS ….. 1.455 fS
Filter Group Delay
dB
3.5 tS
s
space
0
−20
1.0
0.8
0.6
−40
0.4
−60
0.2
−80
0.0
−100
−120
−0.2
−0.4
0
1
2
3
4
0
10
20
30
40
50
Samples
60
70
80
90 100
Frequency (x fS)
G005
G016
Figure 32. Low latency x2 Interpolation Filter
Frequency Response
Figure 33. Low latency x2 Interpolation Filter
Impulse Response
0.0001
0.00008
0.00006
0.00004
0.00002
0
−0.00002
−0.00004
−0.00006
−0.00008
−0.0001
0.0
0.5
Frequency (x fS)
1.0
G030
Figure 34. Low latency x2 Interpolation Filter Passband Ripple
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Zero Data Detect
The PCM510xA-Q1 has a zero-data detect function. When the device detects continuous zero data, it enters a
full AMUTE condition.
The PCM510xA-Q1 counts zero data over 1024LRCKs (21 ms at 48 kHz) before setting AMUTE.
Power Save Mode
When any kind of clock error (SCK, BCK, and LRCK) or clock halt is detected, the PCM510xA-Q1 enters stand-
by mode automatically. The current-segment DAC and line driver are also powered down.
When BCK and LRCK halt to a low level for more than one second, the PCM510xA-Q1 enters power-down mode
automatically. Power-down mode includes the negative charge pump and bias or reference circuit power-down in
addition to stand-by.
Whenever expected audio clocks (SCK, BCK, LRCK) are applied to the PCM510xA-Q1, the device starts its
power-up sequence automatically.
XSMT Pin (Soft Mute and Soft Un-Mute)
For external digital control of the PCM510xA-Q1, the XSMT pin must be driven by an external digital host with a
specific minimum rise time (tr) and fall time (tf) for soft mute and soft un-mute. The PCM510xA-Q1 requires rise
and fall times of less than 20 ns. In the majority of applications, this should not be a problem, however, traces
with high capacitance may have issues.
When the XSMT pin is shifted from high to low (3.3 V to 0 V), a soft digital attenuation ramp is started, –1 dB
attenuation is applied every 1 tS from 0 dBFS to –∞. This attenuation takes 104 sample times.
When the XSMT pin is shifted from low to high (0 V to 3.3 V), a soft digital un-mute is started, 1 dB gain steps
are applied every tS from –∞ to 0 dBFS. This ramp-up takes 104 sample times.
0.9 * DVDD
XSMT
0.1 * DVDD
tr
tf
<20ns
<20ns
Figure 35. XSMT Timing for Soft Mute and Soft Un-Mute
Table 14. XSMT Timing Parameters
Parameters
Rise time (tr)
Fall time (tf)
Min
Max
20
Unit
ns
20
ns
External Power Sense Undervoltage Protection Mode (Supported Only When DVDD = 3.3 V)
The XSMT pin can also be used to monitor a system voltage, such as the 24-VDC LCD TV backlight, or 12-VDC
system supply using a potential divider created with two resistors. (See Figure 36 )
•
If the XSMT pin makes a transition from 1 to 0 over 6 ms or more, the device switches into external
undervoltage protection mode. In this mode, two trigger levels are used.
•
•
When XSMT pin level reaches 2 V, soft mute process begins.
When XSMT pin level reaches 1.2 V, AMUTE engages, regardless of digital audio level, and analog shut
down begins. For example, DAC circuitry powers down.
A timing diagram to show this is shown in Figure 37.
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NOTE
The XSMT input pins voltage range is from –0.3 V to DVDD + 0.3 V. The ratio of external
resistors must be considered within this input range. Any increase in power supply (such
as power supply positive noise or ripple) can pull the XSMT pin higher than DVDD + 0.3 V.
For example, if the PCM510xA-Q1 is monitoring a 12-V input, and dividing the voltage by four, then the voltage
at XSMT during ideal power supply conditions is 3 V. If the voltage spikes any higher than 14.4 V, then XSMT
sees a voltage in excess of 3.6 V (DVDD + 0.3), potentially damaging the device.
Providing the divider is set appropriately, any DC voltage can be monitored.
System
VDD
12V
supply
7.25kW
XSMT
2.75kW
Figure 36. XSMT in External UVP Mode
Digital Attenuation Followed by Analog Mute
0.9 * DVDD
2.0 V
1.2 V
Analog Mute
XSMT
0.1 * DVDD
tf
Figure 37. XSMT Timing for Undervoltage Protection
Recommended Powerdown Sequence
With inadequate system design, the PCM510xA-Q1 can exhibit some pop on power down. Pops are caused by
the device not having enough time to detect power loss and start the muting process.
The PCM510xA-Q1 evaluation board avoids audible pop with an electrolytic decoupling capacitor. This capacitor
provides enough time between data loss from universal serial bus (USB) or S/PDIF and power supply loss for the
muting process to take place.
The PCM510xA-Q1 has two auto-mute functions to mute the device upon power loss (intentional or
unintentional).
XSMT = 0
When the XSMT pin is pulled low, the incoming PCM data is attenuated to 0, closely followed by a hard AMUTE.
This process takes 150 ts + 0.2 mS.
24
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ZHCSBM3A –SEPTEMBER 2013–REVISED SEPTEMBER 2013
Because this digital power supply voltage mute time is mainly dominated by the sampling frequency, systems
sampling at 192 kHz mutes much faster than a 48-kHz system.
Clock Error Detect
When clock error is detected on the incoming data clock, the PCM510xA-Q1 family switches to an internal
oscillator, and continues to the drive the output, while attenuating the data from the last known value. Once this
process is complete, the PCM510xA-Q1 outputs are hard muted to ground.
Planned Shutdown
These auto-muting processes can be manipulated by system designs to mute before power loss in the following
ways:
1. Assert XSMT low 150 tS + 0.2 mS before power is removed.
3.3V
VDD
0V
150tS + 0.2ms
High
XSMT
Low
High
2
I S Clocks
SCK, BCK, LRCK
Low
Time
2. Stop I2S clocks (SCK, BCK, LRCK) 3 ms before power down as shown below:
3.3V
VDD
0V
High
XSMT
Low
3msec
High
I2S Clocks
SCK, BCK, LRCK
Low
Time
Copyright © 2013, Texas Instruments Incorporated
25
PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1
ZHCSBM3A –SEPTEMBER 2013–REVISED SEPTEMBER 2013
www.ti.com.cn
Unplanned Shutdown
Many systems use a low-noise regulator to provide an analog power supply voltage 3.3-V supply for the DAC.
The XSMT pin can take advantage of such a feature to measure the pre-regulated output from the system
switched mode power supply (SMPS) to mute the output before the entire SMPS discharges. Figure 38 shows
how to configure such a system to use the XSMT pin. The XSMT pin can also be used in parallel with a GPIO
pin from the system microcontroller or digital signal processor (DSP), or Power Supply.
³PXWH´ꢀVLJQDO
MCU GPIO
GND
XSMT
110V / 220V
Linear
Regulator
PCM51xx-Q1
Audio DAC
6V
3V3
SMPS
10 PF
GND
GND
Figure 38. Using the XSMT Pin
26
Copyright © 2013, Texas Instruments Incorporated
PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1
www.ti.com.cn
ZHCSBM3A –SEPTEMBER 2013–REVISED SEPTEMBER 2013
Typical Application Circuits
Figure 39. PCM510xA-Q1 Standard PCM Audio Operation, 3.3 V
Figure 40. PCM510xA-Q1 Standard PCM Audio Operation, 1.8 V
Copyright © 2013, Texas Instruments Incorporated
27
PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1
ZHCSBM3A –SEPTEMBER 2013–REVISED SEPTEMBER 2013
www.ti.com.cn
Figure 41. PCM510xA-Q1 PLL Operation, 3.3 V
Figure 42. PCM510xA-Q1 PLL Operation, 1.8 V
28
Copyright © 2013, Texas Instruments Incorporated
PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1
www.ti.com.cn
ZHCSBM3A –SEPTEMBER 2013–REVISED SEPTEMBER 2013
Recommended Output Filter for the PCM510xA-Q1
The diagram in Figure 43 shows the recommended output filter for the PCM510xA-Q1. The new PCM510xA-Q1
next generation current segment architecture offers excellent out of band noise, making a traditional 20-kHz low
pass filter unnecessary.
The RC settings below offer a –3-dB filter point at 153 kHz (approximately), giving the DAC the ability to
reproduce virtually all frequencies through to its maximum sampling rate of 384 kHz.
OUTL
470Ω
2.2nF
LINE
OUT
2VRMS
Output voltage is
With a 10kΩ Load
OUTR
470Ω
2.2nF
Figure 43. Recommended Output Lowpass Filter for 10-kΩ Operation
Copyright © 2013, Texas Instruments Incorporated
29
PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1
ZHCSBM3A –SEPTEMBER 2013–REVISED SEPTEMBER 2013
www.ti.com.cn
REVISION HISTORY
Changes from Original (September 2013) to Revision A
Page
•
•
•
•
•
•
•
•
•
Changed 文档状态从产品预览改为生成数据 ........................................................................................................................ 1
Added TA to Differences Between PCM510xA-Q1 Devices table ........................................................................................ 2
Changed generic part number to orderable part number in Differences Between PCM510xA-Q1 Devices table ............... 2
Added top-side marking to Differences Between PCM510xA-Q1 Devices table ................................................................. 2
Changed THERMAL CHARACTERISTICS table to provide more information on Termal Metrics ...................................... 4
Changed TA = 25°C to temperature range in condition statement of ELECTRICAL CHARACTERISTICS table ................ 4
Changed TA = 25°C to temperature range in condition statement of ELECTRICAL CHARACTERISTICS table ................ 5
Changed TA = 25°C to temperature range in condition statement of ELECTRICAL CHARACTERISTICS table ................ 6
Changed min and max values from –6 and +6 to –7 and +7 for the Gain error parameter under Analog Output in the
ELECTRICAL CHARACTERISTICS table ............................................................................................................................ 6
•
•
Changed min and max values from –6 and +6 to –7 and +7 for the Gain mismatch parameter under Analog Output
in the ELECTRICAL CHARACTERISTICS table .................................................................................................................. 6
Changed TA = 25°C to temperature range in condition statement of ELECTRICAL CHARACTERISTICS table ................ 7
30
Copyright © 2013, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PCM5100AQPWRQ1
PCM5101AQPWRQ1
PCM5102AQPWRQ1
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
PW
PW
PW
20
20
20
2000 RoHS & Green
2000 RoHS & Green
2000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
P5100AQ1
NIPDAU
NIPDAU
P5101AQ1
P5102AQ1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
PCM5100AQPWRQ1
PCM5101AQPWRQ1
PCM5102AQPWRQ1
TSSOP
TSSOP
TSSOP
PW
PW
PW
20
20
20
2000
2000
2000
330.0
330.0
330.0
16.4
16.4
16.4
6.95
6.95
6.95
7.1
7.1
7.1
1.6
1.6
1.6
8.0
8.0
8.0
16.0
16.0
16.0
Q1
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
PCM5100AQPWRQ1
PCM5101AQPWRQ1
PCM5102AQPWRQ1
TSSOP
TSSOP
TSSOP
PW
PW
PW
20
20
20
2000
2000
2000
350.0
350.0
350.0
350.0
350.0
350.0
43.0
43.0
43.0
Pack Materials-Page 2
PACKAGE OUTLINE
PW0020A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
18X 0.65
20
1
2X
5.85
6.6
6.4
NOTE 3
10
B
11
0.30
20X
4.5
4.3
NOTE 4
0.19
1.2 MAX
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220206/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0020A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
20X (1.5)
(R0.05) TYP
20
1
20X (0.45)
SYMM
18X (0.65)
11
10
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220206/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0020A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
20X (1.5)
SYMM
(R0.05) TYP
20
1
20X (0.45)
SYMM
18X (0.65)
10
11
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220206/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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