PDR54450QDDARQ1 [TI]
汽车级 5.5V 至 36V 输入、5A、500kHz 降压转换器 | DDA | 8 | -40 to 150;
| 型号： | PDR54450QDDARQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车级 5.5V 至 36V 输入、5A、500kHz 降压转换器 | DDA | 8 | -40 to 150 转换器 |
| 文件： | 总29页 (文件大小：2238K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMR54450-Q1, LMR54430-Q1
ZHCSR84 –NOVEMBER 2022
LMR544x0-Q1 汽车类5A 和3A 宽输入范围降压转换器
1 特性
3 说明
• 符合面向汽车应用的AEC-Q100 标准
LMR54450-Q1 和 LMR54430-Q1 是高输出电流 PWM
转换器，集成了低电阻高侧 N 沟道 MOSFET。集成的
功能包括高性能误差放大器（可在瞬态条件下提供高稳
压精度）、欠压锁定电路（用于防止在输入电压达到
5.5V 前启动）、内部设置的软启动电路（用于限制浪
涌电流）以及电压前馈电路（用于改进瞬态响应）。通
过使用EN 引脚，关断电源电流通常可减少到13μA。
其他特性包括高电平有效使能端、过流限制、过压保护
和热关断。为降低设计复杂性并减少外部组件数量，反
馈环路进行了内部补偿。
– 器件温度等级1：–40°C 至+125°C 环境工作
温度范围
• 功能安全型
– 可提供用于功能安全系统设计的文档
• 5.5V 至36V 的宽输入电压范围
• 高达5A 的持续（峰值为6A）输出电流
• 通过85mΩ 集成MOSFET 开关实现大于90% 的高
效率
• 宽输出电压范围：可调节为低至1.22V，初始精度
为1.5%
• 内部补偿最大限度地减少了外部器件数量
• 适用于小型滤波器尺寸的固定400kHz 低于MW 频
段开关频率
• 13μA 关断电源电流（典型值）
• 通过输入电压前馈改进线路调整和瞬态响应
• 系统受过流限制、过压保护和热关断的保护
• –40°C 至150°C 的工作结温范围
• 采用小型热增强型8 引脚SOIC PowerPAD™ 集成
电路封装
LMR54450-Q1 和 LMR54430-Q1 器件采用热增强型 8
引脚 SOIC PowerPAD 集成电路封装。TI 提供评估模
块和软件工具，有助于实现高性能电源设计，可满足迫
切的器件开发周期要求。
器件信息
封装尺寸（标
封装(1)
器件型号
电流额定值
称值）
LMR54450-Q1
LMR54430-Q1
5A
3A
DDA
（HSOIC，8）
4.89mm ×
3.90mm
2 应用
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 信息娱乐系统与仪表组
• 车身电子装置和照明
• 电池充电器
VOUT = 5 V
IOUT(max) = 5 A or 3 A
L
VIN = 5.5 V 36 V
VIN
SW
CBOOT
COUT
CIN
D1
RFBT
EN
PG
SS
BOOT
FB
RFBT
GND
典型电路原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSGK7
LMR54450-Q1, LMR54430-Q1
ZHCSR84 –NOVEMBER 2022
www.ti.com.cn
Table of Contents
7.4 Device Functional Modes..........................................11
8 Application and Implementation..................................12
8.1 Application Information............................................. 12
8.2 Typical Application.................................................... 12
8.3 Power Supply Recommendations.............................19
8.4 Layout....................................................................... 19
9 Device and Documentation Support............................21
9.1 Device Support......................................................... 21
9.2 接收文档更新通知..................................................... 21
9.3 支持资源....................................................................21
9.4 Trademarks...............................................................21
9.5 Electrostatic Discharge Caution................................21
9.6 术语表....................................................................... 21
10 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information (DDA Package)..........................4
6.5 Electrical Characteristics.............................................5
6.6 System Characteristics............................................... 6
6.7 Typical Characteristics................................................7
7 Detailed Description........................................................9
7.1 Overview.....................................................................9
7.2 Functional Block Diagram...........................................9
7.3 Feature Description...................................................10
Information.................................................................... 21
10.1 Tape and Reel Information......................................22
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
November 2022
*
Initial release
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5 Pin Configuration and Functions
1
8
BOOT
SW
7
6
5
PG
SS
FB
2
3
4
VIN
GND
EN
PowerPad
(Pin 9)
图5-1. 8-Pin SOIC DDA Package (Top View)
表5-1. Pin Functions
PIN
TYPE
DESCRIPTION
(1)
NAME
NO.
Boost capacitor for the high-side FET gate driver. Connect a 10-nF, low-ESR capacitor from BOOT pin to SW
pin.
BOOT
1
P
A
Open-drain power-good monitor output that asserts low if the FB voltage is not within the specified window
thresholds. A 10-kΩto 100-kΩpullup resistor to a suitable voltage is required. If not used, PG can be left
PG
2
open.
Soft-start control pin. Connect to a capacitor to ground for increased soft-start time beyond that provided by
internal soft start. Float this pin to enable fixed internal soft-start time of 8 ms.
SS
FB
3
4
A
A
Feedback input to the converter. Connect a resistor divider to set the output voltage. Never short this terminal
to ground during operation.
On and off control. Below 0.5-V, the device stops switching. Precision enable allows the pin to be used as an
adjustable input voltage UVLO. Connect an external resistor divider between this pin, VIN and GND to create
an external UVLO. Float the pin to enable.
EN
5
A
GND
VIN
SW
6
7
8
9
G
P
P
P
System ground pin. Connect to PowerPAD.
Input supply voltage. Bypass VIN pin to GND pin close to device package with a high-quality, low-ESR
ceramic capacitor.
Source of the high-side power MOSFET. Connected to external inductor and diode.
Electrical ground and heat sink connection. Solder directly to system ground plane. GND pin must be
connected to the exposed pad for proper operation.
PowerPAD
(1) A = analog, P = power, G = ground
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating junction temperature range (unless otherwise noted) (1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.6
–1.2
0
MAX
40
7
UNIT
V
Input voltage
Input voltage
Input voltage
Input voltage
Output voltage
Output voltage
Output voltage
Output voltage
Source current
Source current
Source current
Sink current
TJ
VIN to GND
EN to GND
V
FB to GND
3
V
SS to GND
5.0
6
V
BOOT to SW
V
SW to GND, DC
SW to GND, transient < 10ns
PGOOD to GND
SW
40
V
V
7
V
Internally Limited
A
SW Leakage current
SS
10
20
µA
µA
mA
°C
°C
PGOOD
70
Operating junction temperature
Storage temperature
150
150
–40
–65
Tstg
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per AEC Q100-002 HBM
ESD Classification Level 2(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per AEC Q100-011 CDM
ESD Classification Level C5
±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
Over operating junction temperature range (unless otherwise noted)
MIN
NOM
MAX
36
UNIT
Input voltage
Input voltage
Input voltage
Output voltage
Load current
Input voltage range
EN
5.5
V
V
V
V
A
5.5
6.5
16
PG
0
1.221
0
VOUT range
IOUT range
5
Power Good input current
capability
2
mA
°C
Operating junction temperature
-40
150
6.4 Thermal Information (DDA Package)
LMR544X0 -Q1
DDA (HSOIC)
8 PINs
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance (LMR54450EVM) (2)
Junction-to-ambient thermal resistance (JESD 51-7) (3)
Junction-to-case (top) thermal resistance
41.2
°C/W
°C/W
°C/W
RθJA
45.3
RθJC(top)
46
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6.4 Thermal Information (DDA Package) (continued)
LMR544X0 -Q1
THERMAL METRIC(1)
DDA (HSOIC)
UNIT
8 PINs
22
RθJB
ψJT
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
5.1
21.4
1.9
ψJB
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics
(2) Refer to the EVM User's Guide for board layout and additional information. For thermal design information please see the Maximum
Ambient Temperature section.
(3) The value of RΘJA given in this table is only valid for comparison with other packages and cannot be used for design purposes. These
values were calculated in accordance with JESD 51-7, and simulated on a 4-layer JEDEC board. They do not represent the
performance obtained in an actual application. For example, the EVM RΘJA = TBD ℃/W. For design information please see the
Maximum Ambient Temperature section.
6.5 Electrical Characteristics
TJ = –40°C to +150°C, VIN = 5.5 V to 36 V. Typical values are at TJ = 25°C and VIN = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
IQ(VIN)
VIN quiescent current
Non-switching, VFB = 2V
0.865
12.5
1.15
25
mA
µA
ISD(VIN)
VIN shutdown supply current
Shutdown, VEN = 0 V
5
UVLO
VINUVLO(R)
VINUVLO(H)
VIN UVLO rising threshold
VIN UVLO hysteresis
VVIN rising
5.3
5.5
V
V
0.35
REFERENCE VOLTAGE
VFB
FB voltage
TJ = 25°C
1.202
1.196
1.221
1.221
1.239
1.245
50
V
V
VFB
FB voltage
TJ = –40°C to 150°C
VFB = 1.221 V
IFB(LKG)
FB input leakage current
nA
SWITCHING FREQUENCY
fSW
Switching frequency
320
400
480
1.3
kHz
ENABLE
VEN(R)
EN voltage rising threshold
EN voltage falling threshold
EN voltage hysteresis
V
V
VEN(F)
0.5
1.5
VEN(H)
0.203
2.36
V
IEN(P1)
EN pin pull-up current
4
µA
STARTUP
ISS
Soft-start charge current
VSS = 0 V
10
8
µA
ms
tSS_INT
Internal fixed soft-start time
From VOUT= 0% to VOUT= 100%
6.6
10
BOOT CIRCUIT
VBOOT-SW(UV_R)
BOOT-SW UVLO rising threshold
VBOOT-SW rising
1.857
V
OVERCURRENT PROTECTION
IHS(OC) LMR54450: High-side peak current limit
IHS(OC)
6.0
4.0
13
7.5
5.0
16
9.0
6.0
20
A
A
LMR54430: High-side peak current limit
Hiccup time before re-start
ms
POWER GOOD
VPGTH_UR
Power Good threshold
Power Good threshold
FB rising, PG high to low (OV event)
109.5%
107.5%
112.5%
110.5%
115.5%
113.5%
FB falling, PG low to high (Recovery from
OV event)
VPGTH_UF
FB rising, PG low to high (Vout enters
regulation during startup)
VPGTH_LR
VPGTH_LF
Power Good threshold
Power Good threshold
91%
89%
94%
92%
97%
95%
FB falling, PG high to low (UV event)
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6.5 Electrical Characteristics (continued)
TJ = –40°C to +150°C, VIN = 5.5 V to 36 V. Typical values are at TJ = 25°C and VIN = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
µA
PG pin Leakage current when open drain
output is high
IPG(LKG)
VPG = 5 V
1.5
tPG
PG de-glitch filter
60
170
155
2
µs
RPG
Power Good on-resistance
Minimum input voltage for valid PG function
PG logic low output
VIN = 5.5V, VFB = 1.5V, VEN = 1.5V
75
Ω
V
V
V
VIN-PG
VPG
VIN = 2V, VEN = 0V, IPG = 50uA
VIN = 5.5V, VEN = 0V, IPG = 2mA
0.2
0.4
VPG
PG logic low output
POWER STAGE
RDSON(HS)
RDSON(HS)
tON(min)
tOFF(min)
High-side MOSFET on-resistance
High-side MOSFET on-resistance
Minimum ON pulse width
VIN = 12 V, VBOOT-SW = 4.5 V
VIN = 5.5 V, VBOOT-SW = 4.0 V
83
84
159
164
200
mΩ
mΩ
ns
150
200
Minimum OFF pulse width
ns
THERMAL SHUTDOWN
TJ(SD)
Thermal shutdown threshold
Thermal shutdown hysteresis
Temperature rising
152
163
14
°C
°C
TJ(HYS)
6.6 System Characteristics
The following specifications apply only to the typical applications circuit, with nominal component values. Specifications in the
typical (TYP) column apply to TJ = 25°C only. Specifications in the minimum (MIN) and maximum (MAX) columns apply to the
case of typical components over the temperature range of TJ = –40°C to 150°C. These specifications are not ensured by
production testing.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
ISUPPLY
Input supply current when in regulation
VIN = 12V, VOUT = 5V, IOUT = 0 A
1.4
mA
OUTPUT VOLTAGE
VDROP Dropout voltage (VIN-VOUT
VOUT = 5V, IOUT = 5A, Dropout at -1% of
regulation
)
1300
mV
Load Regulation
Line Regulation
VOUT = 3.3 V, VIN = 12 V, IOUT = 0 A to full load
VOUT = 3.3 V, VIN = 5.5 V to 36 V, IOUT = 1 A
1
1
mV
mV
VOUT = 3.3 V, VIN = 12 V, IOUT = 2.5 A to 5 A @
2.5 A/us.
Load Transient Magnitude
80
mV
EFFICIENCY
Efficiency
VIN = 13.5V, VOUT = 5V, IOUT = 2.5 A
92 %
η5V
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6.7 Typical Characteristics
Unless otherwise specified, VIN = 13.5 V
940
920
900
880
860
840
820
VIN = 13.5 V
VIN = 24 V
-50
-25
0
25
50
75
100
125
150
Junction Temperature (ꢀC)
图6-1. Oscillator Frequency vs Junction Temperature
图6-2. Non-Switching Quiescent Current vs Junction
Temperature
16
15
14
13
12
8.4
8
7.6
7.2
6.8
6.4
6
11
VIN = 13.5 V
VIN = 24 V
10
-50
-25
0
25
50
75
100 125
150
-50
-25
0
25
50
75
100
125
150
Junction Temperature (ꢀC)
Junction Temperature (ꢀC)
图6-3. Shutdown Quiescent Current vs Input Voltage
图6-4. High-side Current Limit vs Junction Temperature
1.25
160
1.24
1.23
1.22
1.21
1.2
140
120
100
80
1.19
60
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Junction Temperature (ꢀC)
Junction Temperature (ꢀC)
图6-5. Voltage Reference vs Junction Temperature
图6-6. On Resistance vs Junction Temperature
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6.7 Typical Characteristics (continued)
Unless otherwise specified, VIN = 13.5 V
10
160
150
140
130
120
110
100
9
8
7
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Junction Temperature (ꢀC)
Junction Temperature (ꢀC)
图6-7. Internal Soft-Start Time vs Junction Temperature
图6-8. Minimum Controllable On Time vs Junction Temperature
180
175
170
165
160
155
150
-50
-25
0
25
50
75
100
125
150
Junction Temperature (ꢀC)
图6-9. Minimum Controllable Off-Time vs Junction Temperature
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7 Detailed Description
7.1 Overview
LMR54450-Q1 and LMR54430-Q1 are 36-V, 5-A and 3-A, step-down (buck) regulators with an integrated high-
side n-channel MOSFET. These devices implement constant-frequency voltage-mode control with voltage feed
forward for improved line regulation and line transient response. Internal compensation reduces design
complexity and external component count.
The integrated 83-mΩhigh-side MOSFET supports high-efficiency power-supply designs capable of delivering 5
A of continuous current to a load when the LMR54450-Q1 is used and 3 A of continuous current when the
LMR54430-Q1 is used. Gate-drive bias voltage for the integrated high-side MOSFET is supplied by a bootstrap
capacitor connected from the BOOT to SW pins. These devices reduce external component count by integrating
the bootstrap recharge diode.
LMR54450-Q1 and LMR54430-Q1 devices have a default input start-up voltage of 5.3 V typical. The EN pin can
be used to disable the LMR54450-Q1 or LMR54430-Q1 reducing the supply current to 13 µA. An internal pullup
current source enables operation when the EN pin is floating. Also included is an internal soft-start circuit that
slows the output rise time during startup to reduce in rush current and output voltage overshoot. Start-up time
can be further reduced using a capacitor between SS and ground.
Minimum output voltage is determined by the device 1.221-V feedback reference. Output overvoltage transients
are minimized by an Overvoltage Protection (OVP) comparator. When the OVP comparator is activated, the
high-side MOSFET is turned off and remains off until the output voltage is less than 112.5% of the desired output
voltage.
Internal cycle-by-cycle overcurrent protection limits the peak current in the integrated high-side MOSFET. For
continuous overcurrent fault conditions, the LMR54450-Q1 or LMR54430-Q1 enter hiccup mode overcurrent
limiting. Thermal protection protects the device from overheating.
7.2 Functional Block Diagram
VIN
SS
5 µA
Shutdown
HICCUP
BOOT
1.221 V Bandgap
Reference
Boot
Regulator
VREF
UVLO
So Start
ENABLE
EN
Shutdown
Shutdown
Shutdown
Thermal
Z1
FB
Protec on
Shutdown
Error
Ampli er
Z2
VIN
Ramp
Generator
Feed Forward
Gain = 25
GND
HICCUP
Shutdown
Oscillator
Shutdown
PWM
Comparator
Overcurrent
Protec on
POWERPAD
PG
POWER GOOD
CONTROL
Shutdown
Gate Drive
Control
Gate
Driver
OVP
FB
112.5% VREF
+
-
Shutdown
SW
BOOT
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7.3 Feature Description
7.3.1 Oscillator Frequency
An internal free running oscillator sets the PWM switching frequency at 400 kHz. The 400-kHz switching
frequency is comfortably below the MW frequency band while still allowing small output inductance and
capacitance.
7.3.2 Voltage Reference
The voltage reference system produces a precision reference signal by scaling the output of a temperature
stable band-gap circuit. The band-gap and scaling circuits are trimmed during production testing to an output of
1.221 V at room temperature.
7.3.3 Enable (EN) and Soft Start
The EN pin provides electrical on and off control of the regulator. After the EN pin voltage exceeds the threshold
voltage, the regulator starts operation and the internal soft start begins to ramp. If the EN pin voltage is pulled
below the threshold voltage, the regulator stops switching and the internal soft start resets. Connecting the pin to
ground or to any voltage less than 0.5 V disables the regulator and activate shutdown mode. The quiescent
current of the LMR54450-Q1 and LMR4430-Q1 in shutdown mode is typically 13 μA.
The EN pin has an internal pullup current source, allowing the user to float the EN pin. If an application requires
controlling the EN pin, use open-drain or open-collector output logic to interface with the pin. To limit the start-up
inrush current, an internal soft-start circuit is used to ramp up the reference voltage from 0 V to its final value,
linearly. The internal slow-start time is 8 ms typically. Soft-start timing can be further slowed by connecting a
capacitor to the SS pin which sources current and monitors voltage creating a ramp. Reference follows the
slower of the internal ramp or external ramp.
7.3.4 Undervoltage Lockout (UVLO)
The LMR54450-Q1 and LMR54430-Q1 incorporate a UVLO circuit to keep these devices disabled when VIN
(input voltage) is below the UVLO start voltage threshold. During power-up, internal circuits are held inactive and
both internal and external soft start are grounded until VIN exceeds UVLO start threshold voltage, VINUVLO(R)
.
After UVLO start threshold voltage is reached, the internal soft start is released and device start-up begins. The
device operates until VIN falls below the UVLO stop threshold voltage. Typical hysteresis in the UVLO
comparator is 330 mV.
7.3.5 Boost Capacitor (BOOT)
Connect a 10-nF, low-ESR ceramic capacitor between the BOOT pin and SW pin. This capacitor provides the
gate-drive voltage for the high-side MOSFET. TI recommends X7R or X5R grade dielectrics due to their stable
values over temperature.
7.3.6 Output Feedback (FB) and Internal Compensation
The output voltage of the regulator is set by feeding back the center point voltage of an external resistor divider
network to the FB pin. In steady-state operation, the FB pin voltage must be equal to the voltage reference 1.221
V.
The LMR54450-Q1 and LMR54430-Q1 implement internal compensation to simplify the regulator design.
Because these parts use voltage mode control, a type 3 compensation network has been designed on chip to
provide a high crossover frequency and a high phase margin for good stability. See Intermal Compensation
Network for more details.
7.3.7 Voltage Feed-Forward
The internal voltage feed-forward provides a constant DC power stage gain despite any variations with the input
voltage. This greatly simplifies stability analysis and improves line transient response. Voltage feed-forward
circuitry varies peak ramp voltage making it proportional to input voltage so that the modulator together with
power stage included is constant.
Typical gain of LMR54450-Q1 and LMR54430-Q1 is 25.
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7.3.8 Pulse-Width-Modulation (PWM) Control
The regulator employs a fixed frequency pulse width modulation (PWM) control method. First, the feedback
voltage (FB pin voltage) is compared to the constant voltage reference by the high-gain error amplifier and
compensation network to produce a error voltage. Then, the error voltage is compared to the ramp voltage by
the PWM comparator. In this way, the error voltage magnitude is converted to a pulse width which is the duty
cycle. Finally, the PWM output is fed into the gate-drive circuit to control the on-time of the high-side MOSFET.
7.3.9 Overcurrent Limiting
Overcurrent limiting is implemented by sensing the drain-to-source voltage across the high-side MOSFET. The
drain to source voltage is then compared to a voltage level representing the overcurrent threshold limit. If the
drain-to-source voltage exceeds the overcurrent threshold limit, the overcurrent indicator is set true. The system
ignores the overcurrent indicator for the leading edge blanking time at the beginning of each cycle to avoid any
turn-on noise glitches.
After overcurrent indicator is set true, overcurrent limiting is triggered. The high-side MOSFET is turned off for
the rest of the cycle after a propagation delay. The overcurrent limiting mode is called cycle-by-cycle current
limiting.
Sometimes under serious overload conditions such as short circuit, the overcurrent runaway can still happen
when using cycle-by-cycle current limiting. A second mode of current limiting is used, that is, hiccup mode
overcurrent limiting. During hiccup mode overcurrent limiting, the voltage reference is grounded and the high-
side MOSFET is turned off for the hiccup time. After the hiccup time duration is complete, the regulator restarts
under control of the soft-start circuit.
7.3.10 Overvoltage Protection
The LMR54450-Q1 and LMR54430-Q1 have an overvoltage protection (OVP) circuit to minimize voltage
overshoot when recovering from output fault conditions. The OVP circuit includes an overvoltage comparator to
compare the FB pin voltage and a threshold of 112.5% × VREF. After the FB pin voltage is higher than the
threshold, the high-side MOSFET is forced off. When the FB pin voltage drops lower than the threshold, the
high-side MOSFET is enabled again.
7.3.11 Thermal Shutdown
Both the LMR54450-Q1 and LMR54430-Q1 protect themselves from overheating with an internal thermal
shutdown circuit. If the junction temperature exceeds their thermal shutdown trip point, TJ(SD), their voltage
reference is grounded and their high-side MOSFET is turned off. The part is restarted under control of the soft-
start circuit automatically when the junction temperature drops 14°C below the thermal shutdown trip point.
7.4 Device Functional Modes
7.4.1 Operation near Minimum Input Voltage
The device is recommended to operate with input voltages above 5.5 V. The typical VIN UVLO threshold is 5.3 V
and the device can operate at input voltages down to the UVLO voltage. At input voltages below the actual
UVLO voltage the device does not switch. If EN is floating or externally pulled up to greater up than 1.3 V, when
V(VIN) passes the UVLO threshold the device becomes active. Switching is enabled and the soft-start sequence
is initiated. The LMR54450-Q1 or LMR54430-Q1 device starts linearly ramping up the internal reference voltage
from 0 V to its final value over the internal soft-start time.
7.4.2 Operation With EN Control
The enable start threshold voltage is 1.3-V maximum. With EN held below the 0.5-V minimum stop threshold
voltage the device is disabled and switching is inhibited even if VIN is above its UVLO threshold. The IC
quiescent current is reduced in this state. If the EN voltage is increased above the threshold while VIN is above
its UVLO threshold, the device becomes active. Switching is enabled and the soft-start sequence is initiated. The
LMR54450-Q1 or LMR54430-Q1 device starts linearly ramping up the internal reference voltage from 0 V to its
final value over the internal soft-start time.
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8 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The LMR54450-Q1 device is a 36-V, 5-A, step-down regulator with an integrated high-side MOSFET. If a 3-A
design is desired, use the LMR54430-Q1. The LMR54450-Q1 is typically used to convert a higher DC voltage to
a lower DC voltage with a maximum available output current of 5 A. Example applications are: High Density
Point-of-Load Regulators, LCD and Plasma Displays, Battery Chargers, and 12-V and 24-V Distributed Power
Systems. Use the following design procedure to select component values for either the LMR54450-Q1 or
LMR54430-Q1 device. This procedure illustrates the design of these high-frequency switching regulators.
8.2 Typical Application
图 8-1 shows the schematic for a typical LMR54450-Q1 application. The LMR54450-Q1 can provide up to 5-A
output current at a nominal output voltage of 5 V. For proper thermal performance, the exposed PowerPAD
integrated circuit package underneath the device must be soldered down to the printed-circuit board.
VOUT = 5 V
IOUT(max) = 5 A or 3 A
L
VIN = 5.5 V 36 V
VIN
SW
CBOOT
COUT
CIN
D1
RFBT
EN
PG
SS
BOOT
FB
RFBT
GND
图8-1. Application Circuit, 12 V to 5.0 V
8.2.1 Design Requirements
To begin the design process a few parameters must be decided upon. These requirements are typically
determined at the system levels. This example is designed to the following known parameters:
表8-1. Design Parameters
DESIGN PARAMETER
Input voltage range
Output voltage
EXAMPLE VALUE
13.5 V (5.5 V to 36 V)
5 V
Output current rating
Operating frequency
5-A continuous
400 kHz
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8.2.2 Detailed Design Procedure
The following design procedure can be used to select component values for the LMR54450-Q1 or LMR54430-
Q1. Alternately, use the WEBENCH® software to generate a complete design. The WEBENCH software uses an
iterative design procedure and accesses a comprehensive database of components when generating a design.
This section presents a simplified discussion of the design process.
8.2.2.1 Switching Frequency
The switching frequency for the LMR54450-Q1 and LMR54430-Q1 are internally set to 400 kHz. Adjusting the
switching frequency is not possible.
8.2.2.2 Output Voltage Setpoint
The output voltage is set by a resistor divider (RFBB and RFBT) from the output to the FB pin. Calculate the RFBB
resistor value for the output voltage of 5 V using 方程式1.
R
V
× 1.221
FBT
R
=
(1)
FBB
− 1.221
OUT
For any design, start with an RFBT value of 10 kΩ.
8.2.2.3 Input Capacitors
The LMR54450-Q1 requires an input decoupling capacitor and, depending on the application, a bulk input
capacitor. The minimum recommended decoupling capacitance is 4.7 μF. A high-quality ceramic type X5R or
X7R is required. For some applications, a smaller value decoupling capacitor can be used, so long as the input
voltage and current ripple ratings are not exceeded. The voltage rating must be greater than the maximum input
voltage, including ripple.
This input ripple voltage can be approximated by 方程式2:
I
× 0.25
× F
SW
OUT MAX
∆ V
=
+
I
× ESR
MAX
(2)
IN
OUT MAX
C
BULK
where
• IOUT(MAX) is the maximum load current
• FSW is the switching frequency
• CBULK is the input capacitor value
• ESRMAX is the maximum series resistance of the input capacitor
For this design, the input capacitance consists of two 4.7-μF capacitors, C1 and C4, in parallel. An additional
high frequency bypass capacitor, C5 is also used.
The maximum RMS ripple current also must be checked. For worst case conditions, this can be approximated by
方程式3:
I
OUT MAX
I
=
(3)
CIN
2
In this case, the input ripple voltage are 281 mV and the RMS ripple current is 2.5 A. The maximum voltage
across the input capacitors are VIN max plus delta VIN/2. The chosen input decoupling capacitor is rated for 50
V and the ripple current capacity is greater than 2.5 A each, providing ample margin. Make sure that the
maximum ratings for voltage and current are not exceeded under any circumstance.
Additionally some bulk capacitance can be needed, especially if the LMR54450-Q1 circuit is not located within
about 2 inches from the input voltage source. The value for this capacitor is not critical but it also must be rated
to handle the maximum input voltage including ripple voltage and must filter the output so that input ripple
voltage is acceptable.
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8.2.2.4 Output Filter Components
Two components must be selected for the output filter, L1 and C2. Because the LMR54450-Q1 is an internally
compensated device, a limited range of filter component types and values can be supported.
8.2.2.5 Inductor Selection
To calculate the minimum value of the output inductor, use 方程式4.
V
×
V
− V
OUT
OUT MAX
× K
IN MAX
× I × F
L
=
(4)
MIN
V
IN MAX
IND OUT SW MIN
KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current.
Three things must be considered when determining the amount of ripple current in the inductor: the peak to peak
ripple current affects the output ripple voltage amplitude, the ripple current affects the peak switch current and
the amount of ripple current determines at what point the circuit becomes discontinuous. For designs using the
LMR54450-Q1, KIND of 0.2 to 0.3 yields good results. Low-output ripple voltages can be obtained when paired
with the proper output capacitor, the peak switch current is well below the current limit set point and relatively
low-load currents can be sourced before discontinuous operation.
For this design example use KIND = 0.2 and the minimum inductor value is calculated to be 10.8 μH. A higher
standard value is 15 μH, which is used in this design.
For the output filter inductor , make sure that the RMS current and saturation current ratings not be exceeded.
The RMS inductor current can be found from 方程式5.
2
V
×
V
− V
OUT
IN MAX
× L × F
OUT
SW MIN
2
1
12
I
=
I
+
×
(5)
L RMS
OUT MAX
V
IN MAX
OUT
The peak inductor current can be determined with 方程式6.
V
×
V
− V
OUT
+
OUT MAX
1.6 × V
IN MAX
× L
OUT
× F
SW MIN
I
= I
(6)
L PK
IN MAX
OUT
For this design, the RMS inductor current is 5.004 A, and the peak inductor current is 5.34 A. The chosen
inductor is a Wurth (7447709150) 15μH. It has a minimum rated current of 6.5 A and saturation current of 8 A.
In general, inductor values for use with the LMR54450-Q1 are in the range of 10 μH to 100 μH.
8.2.2.6 Capacitor Selection
The important design factors for the output capacitor are DC voltage rating, ripple current rating, and equivalent
series resistance (ESR). The DC voltage and ripple current ratings cannot be exceeded. The ESR is important
because along with the inductor ripple current it determines the amount of output ripple voltage. The actual value
of the output capacitor is not critical, but some practical limits do exist. Consider the relationship between the
desired closed-loop crossover frequency of the design and LC corner frequency of the output filter. Due to the
design of the internal compensation, keeping the closed-loop crossover frequency in the range 3 kHz to 30 kHz
is desirable as this frequency range has adequate phase boost to allow for stable operation. For this design
example, assume that the intended closed-loop crossover frequency is between 2590 Hz and 24 kHz and also
below the ESR zero of the output capacitor. Under these conditions, the closed-loop crossover frequency is
related to the LC corner frequency by 方程式7:
2
F
LC
F
=
(7)
CO
85 × V
OUT
And the desired output capacitor value for the output filter to 方程式8:
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1
× F
C
=
(8)
OUT
3357 × L
× V
CO OUT
OUT
For a desired crossover of 12 kHz and a 15-μH inductor, the calculated value for the output capacitor is 330
μF. The capacitor type must be chosen so that the ESR zero is above the loop crossover. The maximum ESR
must follow 方程式9:
1
ESR
=
(9)
MAX
2 × C
× F
CO
OUT
The maximum ESR of the output capacitor also determines the amount of output ripple as specified in the initial
design parameters. The output ripple voltage is the inductor ripple current times the ESR of the output filter.
Check that the maximum specified ESR as listed in the capacitor data sheet results in an acceptable output
ripple voltage detailed in 方程式10:
ESR
× V
×
V
− V
MAX
OUT
IN MAX
× L × F
OUT
SW
V
=
(10)
PP MAX
N
× V
C
IN MAX
OUT
where
• ΔVPP is the desired peak-to-peak output ripple.
• NC is the number of parallel output capacitors.
• FSW is the switching frequency.
For this design example, a single 330-μF output capacitor is chosen for C3. The calculated RMS ripple current
is 143 mA and the maximum ESR required is 40 mΩ. A capacitor that meets these requirements is a Sanyo
Poscap 10TPB330M, rated at 10 V with a maximum ESR of 35 mΩ and a ripple current rating of 3 A. An
additional small 0.1-μF ceramic bypass capacitor, C6 is also used in this design.
The minimum ESR of the output capacitor must also be considered. For good phase margin, the ESR zero when
the ESR is at a minimum must not be too far above the internal compensation poles at 24 kHz and 54 kHz.
The selected output capacitor must also be rated for a voltage greater than the desired output voltage plus one
half the ripple voltage. Any derating amount must also be included. The maximum RMS ripple current in the
output capacitor is given by 方程式11:
V
C
×
V
− V
OUT
× V
IN MAX
× L
OUT
× F
1
12
I
=
×
(11)
COUT RMS
N
IN MAX
OUT
SW
where
• NC is the number of output capacitors in parallel.
• FSW is the switching frequency.
Other capacitor types can be used with the LMR54450-Q1, depending on the needs of the application.
8.2.2.7 Boot Capacitor
Connect a 0.01-μF high-quality MLCC capacitor between the BOOT pin and SW pin. This capacitor provides
the gate-drive voltage for the high-side MOSFET. TI recommends X7R or X5R grade dielectrics due to their
stable values over temperature.
8.2.2.8 Catch Diode
The LMR54450-Q1 is designed to operate using an external catch diode between SW and GND. The selected
diode must meet the absolute maximum ratings for the application: Reverse voltage must be higher than the
maximum voltage at the SW pin, which is VINMAX + 0.5 V. Peak current must be greater than IOUTMAX plus on half
the peak to peak inductor current. Forward voltage drop must be small for higher efficiencies. Note that the catch
diode conduction time is typically longer than the high-side FET on-time, so attention paid to diode parameters
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can make a marked improvement in overall efficiency. Additionally, check that the device chosen is capable of
dissipating the power losses. For this design, a Diodes, Inc. B540A is chosen, with a reverse voltage of 40 V,
forward current of 5 A, and a forward voltage drop of 0.475 V.
8.2.2.9 Output Voltage Limitations
Due to the internal design of the LMR54450-Q1, there are both upper and lower output voltage limits for any
given input voltage. The upper limit of the output voltage set point is constrained by the maximum duty cycle of
92% and is given by 方程式12:
V
= D
×
V
− I
× R
− V
−
I
× R − V
D
(12)
OUT MAX
MAX
IN MIN
OUT MAX
DS1
D
OUT MAX
L
where
• VIN(MIN) = minimum input voltage
• DMAX = maximum duty cycle
• RDS1 = high-side on resistance
• IOUT(MAX) = maximum load current
• VD = catch diode forward voltage.
• RL= output inductor series resistance.
This equation assumes maximum on resistance for the internal high-side FET. The maximum output voltage is
limited to either 16 V or to the calculated value in 方程式12, whichever is lower.
The lower limit is constrained by the minimum controllable on time which can be as high as 200 ns. The
approximate minimum output voltage for a given input voltage and minimum load current is given by 方程式13:
V
= 0.072 ×
V
− I
× R
+ V
−
I
× R − V
D
(13)
OUT MIN
IN MAX
OUT MIN
DS1
D
OUT MIN
L
where
• VIN(MAX) = maximum input voltage
• RDS1 = high-side on resistance
• IOUT(MIN) = minimum load current
• VD = catch diode forward voltage.
• RL= output inductor series resistance.
This equation assumes nominal on resistance for the high-side FET and accounts for worst case variation of
operating frequency set point. Any design operating near the operational limits of the device must be carefully
checked to assure proper functionality.
8.2.2.10 Internal Compensation Network
The design equations given in the example circuit can be used to generate circuits using the LMR54450-Q1.
These designs are based on certain assumptions and tend to always select output capacitors within a limited
range of ESR values. If a different capacitor type is desired, it can be possible to fit one to the internal
compensation of the LMR54450-Q1. 方程式 14 details the nominal frequency response of the internal voltage-
mode type-III compensation network:
s
s
1 +
× 1 +
2 × F
2 × F
Z1
Z2
H s =
(14)
s
s
s
s
×
1 +
×
1 +
× 1 +
2 × F
2 × F
2 × F
2 × F
P0
P1
P2
P3
where
• Zeroes: FZ1 = 2170 Hz, FZ2 = 2590 Hz
• Poles: FP0 = 2165 Hz, FP1 = 24 kHz, FP2 = 54 kHz, FP3 = 440 kHz
• Fp3 represents the non-ideal parasitics effect.
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Using this information along with the desired output voltage, feed-forward gain, and output filter characteristics,
the closed-loop transfer function can be derived.
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8.2.3 Application Curves
Unless otherwise specified, the following conditions apply: Device: LMR54450-Q1, VIN = 13.5 V, VOUT = 5 V, FSW
= 400 kHz, TA = 25 C. The circuit and appropriate BOM are detailed in the EVM User's Guide.
100
95
90
85
80
75
70
5.06
5.04
5.02
5
VIN = 13.5 V
VIN = 24 V
VIN = 36 V
4.98
4.96
4.94
VIN = 13.5 V
VIN = 24 V
VIN = 36 V
0
1
2
3
4
5
0
1
2
3
4
5
Output Current (A)
Output Current (A)
图8-2. Efficiency vs Output Current
图8-4. Output Ripple at 2.5-A Load
图8-6. Start-up Performance
图8-3. Efficiency vs Output Current
图8-5. Short-Circuit Recovery (Hiccup-Mode)
图8-7. Shutdown Performance
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图8-8. Transient Response, IOUT 1.25 A to 3.75 A (TR = TF= 1 us)
8.3 Power Supply Recommendations
The device is designed to operate from an input voltage supply range between 5.5 V and 36 V. This input supply
must be well regulated. If the input supply is located more than a few inches from the LMR54450-Q1 or
LMR54430-Q1 converter additional bulk capacitance can be required in addition to the ceramic bypass
capacitors. An electrolytic capacitor with a value of 100 μF is a typical choice.
8.4 Layout
8.4.1 Layout Guidelines
Connect a low-ESR ceramic bypass capacitor to the VIN pin. Take care to minimize the loop area formed by the
bypass capacitor connections, the VIN pin, and the LMR54450-Q1 or LMR54430-Q1 ground pin. The best way
to do this is to extend the top-side ground area from under the device adjacent to the VIN trace, and place the
bypass capacitor as close as possible to the VIN pin. The minimum recommended bypass capacitance is 4.7-
μF ceramic with a X5R or X7R dielectric.
There must be a ground area on the top layer directly underneath the IC, with an exposed area for connection to
the PowerPAD integrated circuit package. Use vias to connect this ground area to any internal ground planes.
Use additional vias at the ground side of the input and output filter capacitors as well. The GND pin must be tied
to the PCB ground by connecting it to the ground area under the device as shown below.
The SW pin must be routed to the output inductor, catch diode and boot capacitor. Because the SW connection
is the switching node, the inductor must be located very close to the SW pin and the area of the PCB conductor
minimized to prevent excessive capacitive coupling. The catch diode must also be placed close to the device to
minimize the output current loop area. Connect the boot capacitor between the phase node and the BOOT pin
as shown. Keep the boot capacitor close to the IC and minimize the conductor trace lengths. The component
placements and connections shown work well, but other connection routings can also be effective.
Connect the output filter capacitors as shown between the VOUT trace and GND. Keep the loop formed by the
SW pin, Lout, Cout and GND as small as is practical.
Connect the VOUT trace to the FB pin using the resistor divider network to set the output voltage. Do not route
this trace too close to the SW trace. Due to the size of the IC package and the device pin-out, the trace can need
to be routed under the output capacitor. Alternately, the routing can be done on an alternate layer if a trace under
the output capacitor is not desired.
If using the grounding scheme shown in 图8-9, use a via connection to a different layer to route to the EN pin.
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8.4.2 Layout Example
BOOT CAPACITOR
VOUT
OUTPUT
INDUCTOR
BOOT
SW
VIN
PGOOD
VIN
RESISTOR
PG
SS
OUTPUT
FILTER
CAPACITOR
CATCH
DIODE
White
GND
EN
INPUT
FILTER
CAPACITOR
SOFT-START
CAPACITOR
FB
Route VIN trace under the catch diode and
output capacitor or on another layer
RESISTOR DIVIDER
TOP SIDE GROUND AREA
图8-9. Design Layout
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9 Device and Documentation Support
9.1 Device Support
9.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
9.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
9.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
9.4 Trademarks
PowerPAD™ and TI E2E™ are trademarks of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
9.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
9.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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10.1 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
Reel
Diameter
(mm)
Reel
Width W1
(mm)
Package
Type
Package
Drawing
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
Device
Pins
SPQ
PLMR54450QDDARQ1
HSOIC
DDA
8
2500
330.0
12.8
6.4
5.2
2.1
8
12
Q1
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TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
Device
PDR54450QDDARQ1
Package Type
Package Drawing Pins
DDA
SPQ
Length (mm) Width (mm)
366.0 364.0
Height (mm)
HSOIC
8
2500
50.0
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PACKAGE OUTLINE
PowerPADTM SOIC - 1.7 mm max height
DDA0008J
S
C
A
L
E
2
.
4
0
0
PLASTIC SMALL OUTLINE
C
6.2
5.8
TYP
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
6X 1.27
8
1
2X
5.0
4.8
3.81
NOTE 3
4
5
0.51
8X
0.31
4.0
3.8
1.7 MAX
B
0.1
C A
B
NOTE 4
0.25
0.10
TYP
SEE DETAIL A
5
4
EXPOSED
THERMAL PAD
0.25
GAGE PLANE
3.1
2.5
0.15
0.00
0 - 8
1.27
0.40
1
8
DETAIL A
TYPICAL
2.6
2.0
4221637/B 03/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MS-012, variation BA.
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EXAMPLE BOARD LAYOUT
PowerPADTM SOIC - 1.7 mm max height
DDA0008J
PLASTIC SMALL OUTLINE
(2.95)
NOTE 9
SOLDER MASK
DEFINED PAD
(2.6)
SOLDER MASK
OPENING
SEE DETAILS
8X (1.55)
1
8
8X (0.6)
(3.1)
SOLDER MASK
OPENING
SYMM
(1.3)
TYP
(4.9)
NOTE 9
6X (1.27)
5
4
(
0.2) TYP
VIA
METAL COVERED
BY SOLDER MASK
SYMM
(5.4)
(1.3) TYP
LAND PATTERN EXAMPLE
SCALE:10X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221637/B 03/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
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EXAMPLE STENCIL DESIGN
PowerPADTM SOIC - 1.7 mm max height
DDA0008J
PLASTIC SMALL OUTLINE
(2.6)
BASED ON
0.125 THICK
STENCIL
8X (1.55)
1
8
8X (0.6)
(3.1)
SYMM
BASED ON
0.127 THICK
STENCIL
6X (1.27)
5
4
SEE TABLE FOR
METAL COVERED
BY SOLDER MASK
SYMM
(5.4)
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
2.91 X 3.47
2.6 X 3.1 (SHOWN)
2.37 X 2.83
0.125
0.150
0.175
2.20 X 2.62
4221637/B 03/2016
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
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PACKAGE OPTION ADDENDUM
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17-Dec-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PDR54450QDDARQ1
ACTIVE SO PowerPAD
DDA
8
2500
TBD
Call TI
Call TI
-40 to 150
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
GENERIC PACKAGE VIEW
DDA 8
PowerPADTM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4202561/G
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