PGA205 [TI]
50µV 失调电压、G=1、2、4、8 可编程增益仪表放大器;
| 型号： | PGA205 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 50µV 失调电压、G=1、2、4、8 可编程增益仪表放大器 放大器 仪表 仪表放大器 |
| 文件： | 总20页 (文件大小：379K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
PGA204
PGA205
Programmable Gain
INSTRUMENTATION AMPLIFIER
FEATURES
● DIGITALLY PROGRAMMABLE GAIN:
DESCRIPTION
The PGA204 and PGA205 are low cost, general pur-
pose programmable-gain instrumentation amplifiers
offering excellent accuracy. Gains are digitally se-
lected: PGA204—1, 10, 100, 1000, and PGA205—1,
2, 4, 8V/V. The precision and versatility, and low cost
of the PGA204 and PGA205 make them ideal for a
wide range of applications.
PGA204: G=1, 10, 100, 1000V/V
PGA205: G=1, 2, 4, 8V/V
● LOW OFFSET VOLTAGE: 50µV max
● LOW OFFSET VOLTAGE DRIFT: 0.25µV/°C
● LOW INPUT BIAS CURRENT: 2nA max
● LOW QUIESCENT CURRENT: 5.2mA typ
● NO LOGIC SUPPLY REQUIRED
Gain is selected by two TTL or CMOS-compatible
address lines, A0 and A1. Internal input protection can
withstand up to ±40V on the analog inputs without
damage.
● 16-PIN PLASTIC DIP, SOL-16 PACKAGES
The PGA204 and PGA205 are laser trimmed for very
low offset voltage (50µV), drift (0.25µV/°C) and high
common-mode rejection (115dB at G=1000). They op-
erate with power supplies as low as ±4.5V, allowing use
in battery operated systems. Quiescent current is 5mA.
APPLICATIONS
● DATA ACQUISITION SYSTEM
● GENERAL PURPOSE ANALOG BOARDS
● MEDICAL INSTRUMENTATION
The PGA204 and PGA205 are available in 16-pin
plastic DIP, and SOL-16 surface-mount packages, speci-
fied for the –40°C to +85°C temperature range.
VO1 V+
1
13
PGA204
PGA205
–
VIN
4
Over-Voltage
Protection
Feedback
12
A1
25kΩ
25kΩ
16
A1
A0
Digitally Selected
Feedback Network
A3
VO
15
14
11
10
Digital
Ground
A2
Ref
+
VIN
5
Over-Voltage
Protection
25kΩ
25kΩ
6
7
9
8
VOS Adj
VO2
V–
International Airport Industrial Park
•
Mailing Address: PO Box 11400
Cable: BBRCORP
•
Tucson, AZ 85734
•
Street Address: 6730 S. Tucson Blvd.
• Tucson, AZ 85706
Tel: (520) 746-1111
•
Twx: 910-952-1111
•
•
Telex: 066-6491
•
FAX: (520) 889-1510
•
Immediate Product Info: (800) 548-6132
©1991 Burr-Brown Corporation
PDS-1176A
Printed in U.S.A. October, 1993
SBOS022
SPECIFICATIONS
ELECTRICAL
PGA204 G=1, 10, 100, 1000V/V
At TA = +25°C, VS = ±15V, and RL = 2kΩ unless otherwise noted.
PGA204BP, BU
TYP
PGA204AP, AU
TYP
PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
UNITS
INPUT
Offset Voltage, RTI
vs Temperature
TA=+25°C
TA=TMIN to TMAX
VS=±4.5V to ±18V
±10+20/G ±50+100/G
±0.1+0.5/G ±0.25+5/G
±25+30/G ±125+500/G
µV
µV/°C
µV/V
µV/mo
Ω || pF
Ω || pF
V
±0.25+5/G
±1+10/G
vs Power Supply
0.5+2/G
±0.2+0.5/G
1010||6
3+10/G
*
*
*
*
*
*
Long-Term Stability
Impedance, Differential
Common-Mode
Input Common-Mode Range
Safe Input Voltage
Common-Mode Rejection
1010||6
VO=0V (see text)
±10.5
±12.7
*
±40
*
V
V
CM=±10V, ∆RS=1kΩ
G=1
80
96
110
115
99
75
90
106
106
90
dB
dB
dB
dB
G=10
G=100
G=1000
114
123
123
106
110
110
BIAS CURRENT
vs Temperature
Offset Current
±0.5
±8
±0.5
±8
±2
±2
*
*
*
*
±5
nA
pA/°C
nA
*
vs Temperature
pA/°C
NOISE, Voltage, RTI(1): f=10Hz
f=100Hz
G≥100, RS=0Ω
G≥100, RS=0Ω
G≥100, RS=0Ω
G≥100, RS=0Ω
16
13
13
0.4
*
*
*
*
nV/√Hz
nV/√Hz
nV/√Hz
µVp-p
f=1kHz
fB=0.1Hz to 10Hz
Noise Current
f=10Hz
0.4
0.2
18
*
*
*
pA/√Hz
pA/√Hz
pAp-p
f=1kHz
fB=0.1Hz to 10Hz
GAIN, Error
G=1
G=10
G=100
G=1000
G=1 to 1000
G=1
G=10
G=100
G=1000
±0.005
±0.01
±0.01
±0.02
±2.5
±0.0004
±0.0004
±0.0004
±0.0008
±0.024
±0.024
±0.024
±0.05
*
*
*
*
*
*
*
*
*
±0.05
±0.05
±0.05
±0.1
%
%
%
%
Gain vs Temperature
Nonlinearity
±10
*
ppm/°C
% of FSR
% of FSR
% of FSR
% of FSR
±0.001
±0.002
±0.002
±0.01
±0.002
±0.004
±0.004
±0.02
OUTPUT
Voltage, Positive(2)
Negative(2)
Load Capacitance Stability
Short Circuit Current
IO=5mA, TMIN to TMAX
IO=–5mA, TMIN to TMAX
(V+)–1.5
(V–)+1.5
(V+)–1.3
(V–)+1.3
1000
*
*
*
*
*
*
V
V
pF
mA
+23/–17
FREQUENCY RESPONSE
Bandwidth, –3dB
G=1
G=10
G=100
1
80
10
1
0.7
22
*
*
*
*
*
*
*
*
*
*
*
*
*
*
MHz
kHz
kHz
kHz
V/µs
µs
µs
µs
µs
µs
G=1000
VO=±10V, G=10
G=1
Slew Rate
Settling Time(3), 0.1%
0.3
*
G=10
G=100
G=1000
G=1
G=10
23
100
1000
23
0.01%
28
µs
µs
µs
µs
G=100
G=1000
50% Overdrive
140
1300
70
Overload Recovery
DIGITAL LOGIC
Digital Ground Voltage, VDG
Digital Low Voltage
Digital Input Current
Digital High Voltage
V–
V–
(V+)–4
DG+0.8V
*
*
*
*
V
V
µA
V
V
1
*
V
DG +2
V+
*
*
*
POWER SUPPLY, Voltage
±4.5
±15
+5.2/–4.2
±18
±6.5
*
*
*
V
mA
Current
VIN=0V
±7.5
TEMPERATURE RANGE
Specification
Operating
–40
–40
+85
+125
*
*
*
*
°C
°C
θJA
80
*
°C/W
* Specification same as PGA204BP.
NOTES: (1) Input-referred noise voltage varies with gain. See typical curves. (2) Output voltage swing is tested for ±10V min on ±11.4V power supplies. (3) Includes
time to switch to a new gain.
®
PGA204/205
2
SPECIFICATIONS
ELECTRICAL
PGA205 G=1, 2, 4, 8V/V
At TA = +25°C, VS = ±15V, and RL = 2kΩ unless otherwise noted.
PGA205BP, BU
TYP
PGA205AP, AU
TYP
PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
UNITS
INPUT
Offset Voltage, RTI
vs Temperature
vs Power Supply
Long-Term Stability
Impedance, Differential
Common-Mode
Input Common-Mode Range
Safe Input Voltage
TA=+25°C
TA=TMIN to TMAX
VS=±4.5V to ±18V
±10+20/G ±50+100/G
±0.1+0.5/G ±0.25+5/G
±25+30/G ±125+500/G
µV
µV/°C
µV/V
µV/mo
Ω||pF
Ω||pF
V
±0.25+5/G
±1+10/G
0.5+2/G
±0.2+0.5/G
1010||6
3+10/G
*
*
*
*
*
*
1010||6
VO=0V (see text)
±10.5
±12.7
*
±40
*
V
Common-Mode Rejection
V
CM=±10V, ∆RS=1kΩ
G=1
G=2
G=4
G=8
80
85
90
95
94
75
80
85
89
88
94
100
106
dB
dB
dB
dB
100
106
112
BIAS CURRENT
vs Temperature
Offset Current
±0.5
±8
±0.5
±8
±2
±2
*
*
*
*
±5
nA
pA/°C
nA
*
vs Temperature
pA/°C
Noise Voltage, RTI(1): f=10Hz
f=100Hz
G=8, RS=0Ω
G=8, RS=0Ω
G=8, RS=0Ω
G=8, RS=0Ω
19
15
15
0.5
*
*
*
*
nV/√Hz
nV/√Hz
nV/√Hz
µVp-p
f=1kHz
fB=0.1Hz to 10Hz
Noise Current
f=10Hz
0.4
0.2
18
*
*
*
pA/√Hz
pA/√Hz
pAp-p
f=1kHz
fB=0.1Hz to 10Hz
GAIN, Error
G=1
G=2
G=4
G=8
G=1 to 8
G=1
G=2
G=4
G=8
±0.005
±0.01
±0.01
±0.01
±2.5
±0.00024
±0.00024
±0.00024
±0.00024
±0.024
±0.024
±0.024
±0.024
±10
±0.001
±0.002
±0.002
±0.002
*
*
*
*
*
*
*
*
*
±0.05
±0.05
±0.05
±0.05
*
±0.002
±0.004
±0.004
±0.004
%
%
%
%
Gain vs Temperature
Nonlinearity
ppm/°C
% of FSR
% of FSR
% of FSR
% of FSR
OUTPUT
Voltage, Positive(2)
Negative(2)
Load Capacitance Stability
Short Circuit Current
IO=5mA, TMIN to TMAX
IO=–5mA, TMIN to TMAX
(V+)–1.5
(V–)+1.5
(V+)–1.3
(V–)+1.3
1000
*
*
*
*
*
*
V
V
pF
mA
+23/–17
FREQUENCY RESPONSE
Bandwidth, –3dB
G=1
G=2
G=4
1
*
*
*
*
*
*
*
*
*
*
*
*
*
*
MHz
kHz
kHz
kHz
V/µs
µs
µs
µs
µs
µs
400
200
100
0.7
22
22
23
23
23
23
25
28
70
G=8
Slew Rate
Settling Time(3), 0.1%
VO=±10V, G=8
G=1
0.3
*
G=2
G=4
G=8
G=1
G=2
G=4
G=8
0.01%
µs
µs
µs
µs
Overload Recovery
50% overdrive
DIGITAL LOGIC INPUTS
Digital Ground Voltage, VDG
Digital Low Voltage
V–
V–
(V+)–4
DG+0.8V
*
*
*
*
V
V
V
Digital Low Current
Digital High Voltage
1
*
µA
V
V
DG+2
V+
*
*
*
POWER SUPPLY, Voltage
±4.5
±15
+5.2/–4.2
±18
±6.5
*
*
*
V
mA
Current
VIN=0V
±7.5
TEMPERATURE RANGE
Specification
Operating
–40
–40
+85
+125
*
*
*
*
°C
°C
θJA
80
*
°C/W
* Specification same as PGA204BP.
NOTES: (1) Input-referred noise voltage varies with gain. See typical curves. (2) Output voltage swing is tested for ±10V min on ±11.4V power supplies. (3) Includes
time to switch to a new gain.
®
3
PGA204/205
PACKAGE INFORMATION
ABSOLUTE MAXIMUM RATINGS
PACKAGE DRAWING
NUMBER(1)
Supply Voltage .................................................................................. ±18V
Analog Input Voltage Range ............................................................. ±40V
Logic Input Voltage Range .................................................................. ±VS
Output Short-Circuit (to ground) .............................................. Continuous
Operating Temperature ................................................. –40°C to +125°C
Storage Temperature..................................................... –40°C to +125°C
Junction Temperature .................................................................... +150°C
Lead Temperature (soldering –10s) .............................................. +300°C
MODEL
PACKAGE
PGA204AP
PGA204BP
PGA204AU
PGA204BU
16-Pin Plastic DIP
16-Pin Plastic DIP
SOL-16 Surface Mount
SOL-16 Surface Mount
180
180
211
211
PGA205AP
PGA205BP
PGA205AU
PGA205BU
16-Pin Plaseic DIP
16-Pin Plastic DIP
SOL-16 Surface Mount
SOL-16 Surface Mount
180
180
211
211
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix D of Burr-Brown IC Data Book.
ORDERING INFORMATION
MODEL
GAINS
PACKAGE
TEMPERATURE RANGE
PGA204AP
PGA204BP
1, 10, 100, 1000V/V
1, 10, 100, 1000V/V
16-Pin Plastic DIP
16-Pin Plastic DIP
–40 to +85°C
–40 to +85°C
PGA204AU
PGA204BU
1, 10, 100, 1000V/V
1, 10, 100, 1000V/V
SOL-16 Surface-Mount
SOL-16 Surface-Mount
–40 to +85°C
–40 to +85°C
PGA205AP
PGA205BP
1, 2, 4, 8V/V
1, 2, 4, 8V/V
16-Pin Plastic DIP
16-Pin Plastic DIP
–40 to +85°C
–40 to +85°C
PGA205AU
PGA205BU
1, 2, 4, 8V/V
1, 2, 4, 8V/V
SOL-16 Surface-Mount
SOL-16 Surface-Mount
–40 to +85°C
–40 to +85°C
®
PGA204/205
4
DICE INFORMATION
PAD
FUNCTION
PAD
FUNCTION
9
VO2
Ref
1
2
3
4
5
6
7
8
VO1
—
—
10
11
12
13
14
15
16
VO
Feedback
V+
Dig. Ground
A0
V–
V+
IN
IN
VOS Adj
OS Adj
V–
V
A1
Substrate Bias: Internally connected to V– power supply.
MECHANICAL INFORMATION
MILS (0.001")
MILLIMETERS
Die Size
Die Thickness
Min. Pad Size
186 x 130 ±5
20 ±3
4.72 x 3.30 ±0.13
0.51 ±0.08
4 x 4
0.1 x 0.1
Backing
Gold
PGA204/205 DIE TOPOGRAPHY
PIN CONFIGURATION
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with ap-
propriate precautions. Failure to observe proper handling and
installation procedures can cause damage.
Top View
VO1
NC
NC
1
2
3
4
5
6
7
8
16 A1
15 A0
14 Dig. Ground
13 V+
V–
IN
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
V+
12 Feedback
11 VO
IN
VOS Adjust
VOS Adjust
V–
10 Ref
9
VO2
NC: No Internal Connection.
®
5
PGA204/205
TYPICAL PERFORMANCE CURVES
At TA = +25°C, and VS = ±15V, unless otherwise noted.
GAIN vs FREQUENCY
COMMON-MODE REJECTION vs FREQUENCY
140
120
100
80
G = 1k,100
G = 10
G=1k
1k
“B” Grade
G = 1
G=100
100
G = 1k
G=10
10
G = 100
G=1
1
G = 10
G = 1
100k
60
40
10
100
1k
10k
1M
10
100
1k
10k
100k
1M
Frequency (Hz)
Frequency (Hz)
INPUT COMMON-MODE VOLTAGE RANGE
vs OUTPUT VOLTAGE
POSITIVE POWER SUPPLY REJECTION
vs FREQUENCY
15
10
5
140
120
100
80
–
G = 1k
VD/2
VO
+
–
VD/2
G = 100
+
VCM
0
(Any Gain)
60
G = 10
G = 1
A3 + Output
Swing Limit
A3 – Output
Swing Limit
–5
–10
–15
40
20
0
–15
–10
–5
0
5
10
15
10
100
1k
10k
100k
1M
Output Voltage (V)
Frequency (Hz)
NEGATIVE POWER SUPPLY REJECTION
vs FREQUENCY
INPUT- REFERRED NOISE VOLTAGE
vs FREQUENCY
140
1k
100
10
120
100
80
60
40
20
0
G = 1k
G = 100
G = 10
G = 1
G = 10
G = 1
G = 100, 1k
G = 1k
BW Limit
1
10
100
1k
10k
100k
1M
1
10
100
1k
10k
Frequency (Hz)
Frequency (Hz)
®
PGA204/205
6
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, and VS = ±15V, unless otherwise noted.
INPUT-REFERRED
OFFSET VOLTAGE WARM-UP vs TIME
INPUT BIAS AND INPUT OFFSET CURRENT
vs TEMPERATURE
6
4
2
1
>
G
100
2
±IB
0
0
–2
–4
–6
IOS
–1
–2
0
15
30
45
60
75
90
105
120
–75
–50
–25
0
25
50
75
100
125
Time from Power Supply Turn-on (s)
Temperature (°C)
INPUT BIAS CURRENT
INPUT BIAS CURRENT
vs DIFFERENTIAL INPUT VOLTAGE
vs COMMON-MODE INPUT VOLTAGE
3
2
3
2
Both Inputs
One Input
|Ib1| + |Ib2
|
1
1
Over-Voltage
Protection
0
0
Over-Voltage
Protection
Normal
Operation
–1
–2
–3
–1
–2
–3
G = 1
G = 10
One Input
G = 100, 1k
–30
Both Inputs
–30 –15
–45
–15
0
15
30
45
–45
0
15
30
45
Common-Mode Voltage (V)
Differential Overload Voltage (V)
MAXIMUM OUTPUT VOLTAGE vs FREQUENCY
SLEW RATE vs TEMPERATURE
32
1.0
0.8
0.6
0.4
0.2
0
28
24
20
16
12
8
G ≤ 10
G=8 or 10
4
0
10
100
1k
10k
100k
1M
–75
–50
–25
0
25
50
75
100
125
Frequency (Hz)
Temperature (°C)
®
7
PGA204/205
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, and VS = ±15V, unless otherwise noted.
QUIESCENT CURRENT vs TEMPERATURE
OUTPUT CURRENT LIMIT vs TEMPERATURE
6.0
5.5
5.0
4.5
4.0
30
25
20
15
10
+|ICL
|
–|ICL
|
–75
–50
–25
0
25
50
75
100
125
–40
–15
10
35
60
85
Temperature (°C)
Temperature (°C)
QUIESCENT CURRENT
vs POWER SUPPLY VOLTAGE
POSITIVE OUTPUT SWING vs TEMPERATURE
VS = ±15V
5.2
5.0
4.5
4.0
3.5
16
14
12
10
8
V+
VS = 11.4
VS = ±4.5
6
4
V–
2
0
0
±5
±10
±15
±20
–75
–50
–25
0
25
50
75
100
125
Power Supply Voltage (V)
Temperature (°C)
NEGATIVE OUTPUT SWING vs TEMPERATURE
VS = ±15V
–16
–14
–12
–10
–8
VS = 11.4
VS = ±4.5
–6
–4
–2
0
–75
–50
–25
0
25
50
75
100
125
Temperature (°C)
®
PGA204/205
8
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, and VS = ±15V, unless otherwise noted.
SMALL-SIGNAL RESPONSE, G = 1
LARGE-SIGNAL RESPONSE, G = 1
+200mV
–200mV
+10V
–10V
SMALL-SIGNAL RESPONSE, G = 10
LARGE-SIGNAL RESPONSE, G = 10
+200mV
–200mV
+10V
–10V
SMALL-SIGNAL RESPONSE, G = 1000
LARGE-SIGNAL RESPONSE, G = 1000
+10V
–10V
+200mV
–200mV
®
9
PGA204/205
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, and VS = ±15V, unless otherwise noted.
INPUT-REFERRED NOISE,
0.1 TO 10Hz, G = 1000
NOISE, 0.1 TO 10Hz, G = 1
0.5µV/Div
0.2µV/Div
1s/Div
1s/Div
be used to sense the output voltage directly at the load for
best accuracy.
APPLICATION INFORMATION
Figure 1 shows the basic connections required for operation
of the PGA204/205. Applications with noisy or high imped-
ance power supplies may require decoupling capacitors
close to the device pins as shown.
The output is referred to the output reference (Ref) terminal
which is normally grounded. This must be a low-impedance
connection to assure good common-mode rejection. A resis-
tance of 5Ω in series with the Ref pin will cause a typical
device to degrade to approximately 80dB CMR (G=1).
DIGITAL INPUTS
The digital inputs A0 and A1 select the gain according to the
logic table in Figure 1. Logic “1” is defined as a voltage
greater than 2V above digital ground potential (pin 14).
Digital ground can be connected to any potential from the
V– power supply to 4V less than V+. Digital ground is
normally connected to ground. The digital inputs interface
directly CMOS and TTL logic components.
The PGA204/205 has an output feedback connection (pin
12). Pin 12 must be connected to the output terminal (pin 11)
for proper operation. The output Feedback connection can
Approximately 1µA flows out of the digital input pins when
a logic “0” is applied. Logic input current is nearly zero with
a logic “1” input. A constant current of approximately
+15V
1µF
VO1
1
PGA204
PGA205
–
VIN
4
Over-Voltage
Protection
Feedback
A1
12
25kΩ
25kΩ
16
Digitally Selected
Feedback Network
A3
VO
15
14
11
V
O = G (VI+N – VI–N
)
Ref
10
A2
+
VIN
5
Over-Voltage
Protection
25kΩ
25kΩ
6
7
9
8
Sometimes shown in simplified form:
1µF
VOS
Adj
VO2
GAIN
–
VIN
PGA204 PGA205 A1 A0
PGA204
VO
1
1
2
4
8
0
0
1
1
0
1
0
1
+
+15V
VIN
10
100
1000
A1 A0
FIGURE 1. Basic Connections.
®
PGA204/205
10
Some applications select gain of the PGA204/205 with
switches or jumpers. Figure 2 shows pull-up resistors con-
nected to assure a noise-free logic “1” when the switch,
jumper or open-collector logic is open or off. Fixed-gain
applications can connect the logic inputs directly to V+ or
V– (or other valid logic level); no resistor is required.
V+
4
Over-Voltage
Protection
–
A1
VIN
100kΩ
100kΩ
16
Digitally Selected
Feedback Network
15
14
OFFSET VOLTAGE
Voltage offset of the PGA204/205 consists of two compo-
nents—input stage offset and output stage offset. Both
components are specified in the specification table in equa-
tion form:
+
A2
VIN
Over-Voltage
Protection
5
Switches, jumpers
or open-collector
logic output.
6
7
9
Digital ground can
alternatively be connected
to V– power supply.
VOS = VOSI + VOSO / G
where:
(1)
VOS
Adj
VO2
VOS total is the combined offset, referred to the input.
FIGURE 2. Switch or Jumper-Selected Digital Inputs.
VOSI is the offset voltage of the input stage, A1 and A2.
VOSO is the offset voltage of the output difference
amplifier, A3.
1.3mA flows in the digital ground pin. It is good practice to
return digital ground through a separate connection path so
that analog ground is not affected by the digital ground
current.
VOSI and VOSO do not change with gain. The composite
offset voltage VOS changes with gain because of the gain
term in equation 1. Input stage offset dominates in high gain
(G≥100); both sources of offset may contribute at low gain
(G=1 to 10).
The digital inputs, A0 and A1, are not latched; a change in
logic inputs immediately selects a new gain. Switching time
of the logic is approximately 1µs. The time to respond to
gain change is effectively the time it takes the amplifier to
settle to a new output voltage in the newly selected gain (see
settling time specifications).
OFFSET TRIMMING
Both the input and output stages are laser trimmed for very
low offset voltage and drift. Many applications require no
external offset adjustment.
Many applications use an external logic latch to access gain
control data from a high speed data bus (see Figure 7). Using
an external latch isolates the high speed digital bus from
sensitive analog circuitry. Locate the latch circuitry as far as
practical from analog circuitry.
Figure 3 shows an optional input offset voltage trim circuit.
This circuit should be used to adjust only the input stage
offset voltage of the PGA204/205. Do this by programming
VO1 V+
1
13
PGA204
PGA205
–
VIN
4
Over-Voltage
Protection
Feedback
A1
12
25kΩ
25kΩ
Resistors can be substituted
for REF200. Power supply
rejection will be degraded.
16
A1
A0
Digitally Selected
Feedback Network
A3
15
14
11
VO = G (VI+N – VI–N) + VREF
V+
Digital
Ground
100µA
VREF
A2
1/2 REF200
+
VIN
5
Over-Voltage
Protection
10
25kΩ
25kΩ
100Ω
100Ω
OPA177
6
7
9
8
10kΩ
±10mV
Adjustment Range
VO2
V–
Input Offset
200kΩ
to 1MΩ
Output Offset
Adjustment
Adjustment
Trim Range
≈ ±250µV
100µA
1/2 REF200
V+
V–
FIGURE 3. Optional Offset Voltage Trim Circuit.
®
11
PGA204/205
it to its highest gain and trimming the output voltage to zero
with the inputs grounded. Drift performance usually im-
proves slightly when the input offset is nulled with this
procedure.
Microphone,
Hydrophone
etc.
PGA204
Do not use the input offset adjustment to trim system offset
or offset produced by a sensor. Nulling offset that is not
produced by the input amplifiers will increase temperature
drift by approximately 3.3µV/°C per 1mV of offset adjust-
ment.
47kΩ
47kΩ
Many applications that need input stage offset adjustment do
not need output stage offset adjustment. Figure 3 also shows
a circuit for adjusting output offset voltage. First, adjust the
input offset voltage as discussed above. Then program the
device for G=1 and adjust the output to zero. Because of the
interaction of these two adjustments at G=8, the PGA205
may require iterative adjustment.
Thermocouple
PGA204
10kΩ
The output offset adjustment can be used to trim sensor or
system offsets without affecting drift. The voltage applied to
the Ref terminal is summed with the output signal. Low
impedance must be maintained at this node to assure good
common-mode rejection. This is achieved by buffering the
trim voltage with an op amp as shown.
PGA204
VR
Center-tap provides
bias current return.
NOISE PERFORMANCE
The PGA204/205 provides very low noise in most applica-
tions. Low frequency noise is approximately 0.4µVp-p mea-
sured from 0.1 to 10Hz. This is approximately one-tenth the
noise of “low noise” chopper-stabilized amplifiers.
Bridge
PGA204
Bias current return
INPUT BIAS CURRENT RETURN PATH
inherrently provided by source.
The input impedance of the PGA204/205 is extremely high—
approximately 1010Ω. However, a path must be provided for
the input bias current of both inputs. This input bias current
is typically less than ±1nA (it can be either polarity due to
cancellation circuitry). High input impedance means that
this input bias current changes very little with varying input
voltage.
FIGURE 4. Providing an Input Common-Mode Current
Path.
INPUT COMMON-MODE RANGE
The linear common-mode range of the input op amps of the
PGA204/205 is approximately ±12.7V (or 2.3V from the
power supplies). As the output voltage increases, however,
the linear input range will be limited by the output voltage
swing of the input amplifiers, A1 and A2. The common-
mode range is related to the output voltage of the complete
amplifier—see performance curve “Input Common-Mode
Range vs Output Voltage”.
Input circuitry must provide a path for this input bias current
if the PGA204/205 is to operate properly. Figure 4 shows
provisions for an input bias current path. Without a bias
current return path, the inputs will float to a potential which
exceeds the common-mode range of the PGA204/205 and
the input amplifiers will saturate. If the differential source
resistance is low, bias current return path can be connected
to one input (see thermocouple example in Figure 4). With
higher source impedance, using two resistors provides a
balanced input with possible advantages of lower input
offset voltage due bias current and better common-mode
rejection.
A combination of common-mode and differential input
voltage can cause the output of A1 or A2 to saturate. Figure
5 shows the output voltage swing of A1 and A2 expressed in
terms of a common-mode and differential input voltages.
Output swing capability of these internal amplifiers is the
same as the output amplifier, A3. For applications where
input common-mode range must be maximized, limit the
output voltage swing by selecting a lower gain of the
PGA204/205 (see performance curve “Input Common-Mode
Voltage Range vs Output Voltage”). If necessary, add gain
after the PGA204/205 to increase the voltage swing.
Many sources or sensors inherently provide a path for input
bias current (e.g. the bridge sensor shown in Figure 4).
These applications do not require additional resistor(s) for
proper operation.
®
PGA204/205
12
VO1 V+
13
G • VD
2
VCM
–
1
PGA204
PGA205
4
Over-Voltage
Protection
Feedback
12
A1
25kΩ
25kΩ
VD
2
16
A1
A0
Digitally Selected
Feedback Network
A3
VO
15
14
11
10
Digital
Ground
VD
2
A2
Ref
5
Over-Voltage
Protection
VCM
25kΩ
25kΩ
9
8
G • VD
VCM
+
VO2
V–
2
FIGURE 5. Voltage Swing of A1 and A2.
Input-overload often produces an output voltage that appears
normal. For example, consider an input voltage of +20V on
one input and +40V on the other input will obviously exceed
the linear common-mode range of both input amplifiers.
Since both input amplifiers are saturated to the nearly the
same output voltage limit, the difference voltage measured
by the output amplifier will be near zero. The output of the
PGA204/205 will be near 0V even though both inputs are
overloaded.
V+
47kΩ
47kΩ
–
VIN
A1
A0
PGA204
PGA205
+
VIN
INPUT PROTECTION
The inputs of the PGA204/205 are individually protected for
voltages up to ±40V. For example, a condition of –40V on
one input and +40V on the other input will not cause
damage. Internal circuitry on each input provides low series
impedance under normal signal conditions. To provide
equivalent protection, series input resistors would contribute
excessive noise. If the input is overloaded, the protection
circuitry limits the input current to a safe value (approxi-
mately 1.5mA). The typical performance curve “Input Bias
Current vs Common-Mode Input Voltage” shows this input
current limit behavior. The inputs are protected even if no
power supply voltage is present.
B
C
X
A
D
D1, D2: IN4148, IN914, etc.
GAIN
PGA204 PGA205
SWITCH
POSITION
A
B
C
D
1
10
100
1000
1
2
4
8
FIGURE 6. Switch-Selected PGIA.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
13
PGA204/205
+15V
14
VO1 V+
13
2
1
HI-509
4
5
PGA204
PGA205
4
Over-Voltage
Protection
Feedback
12
A1
8
–
VIN
25kΩ
25kΩ
6
7
A1 16
Digitally Selected
Feedback Network
A3
A0
VO
15
14
13
12
11
10
9
+
VIN
A2
Ref
11
10
5
Over-Voltage
Protection
25kΩ
25kΩ
6
7
9
8
A0 A1
1 16
3
15
VOS
Adj
VO2
V–
–15V
Data Out
74HC574
Data In
To Address
Decoding Logic
CK
Data Bus
FIGURE 7. Multiplexed-Input Programmable Gain IA.
A0 A1
VO1
VI–N
VI+N
PGA204
PGA205
VO
Ref
VO2
A1 A0
220Ω
20kΩ
20kΩ
OPA177
FIGURE 8. Shield Drive Circuit.
+
VIN
A1
A1
PGA205
PGA205
AO
VO
–
AO
VO
PGA204
PGA205
–
VIN
VIN
+
Ref
R1
1MΩ
C1
0.1µF
A1 A0
GAIN A3
A2
A1 A0
1
2
4
0
0
1
1
1
1
1
0
1
0
1
1
1
1
0
0
0
0
0
1
1
0
0
0
0
1
0
1
1
f–3dB
=
2πR1C1
OPA602
= 1.59Hz
8
16
32
64
FIGURE 9. Binary Gain Steps, G=1 to G=64.
FIGURE 10. AC-Coupled PGIA.
®
PGA204/205
14
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jun-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PGA204AP
PGA204AU
ACTIVE
ACTIVE
ACTIVE
PDIP
SOIC
SOIC
N
16
16
16
25
40
RoHS & Green
RoHS & Green
Call TI
N / A for Pkg Type
Level-3-260C-168 HR
Level-3-260C-168 HR
PGA204AP
Samples
Samples
Samples
DW
DW
NIPDAU
Call TI
-40 to 85
-40 to 85
PGA204AU
PGA204AU
PGA204AU/1K
1000 RoHS & Green
PGA204AU/1KE4
PGA204AUE4
PGA204BP
LIFEBUY
LIFEBUY
ACTIVE
SOIC
SOIC
PDIP
DW
DW
N
16
16
16
1000 RoHS & Green
Call TI
NIPDAU
Call TI
Level-3-260C-168 HR
Level-3-260C-168 HR
N / A for Pkg Type
-40 to 85
-40 to 85
PGA204AU
PGA204AU
PGA204BP
40
25
RoHS & Green
RoHS & Green
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
PGA204BU
PGA204BU/1K
PGA205AP
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LIFEBUY
SOIC
SOIC
PDIP
SOIC
SOIC
PDIP
SOIC
SOIC
DW
DW
N
16
16
16
16
16
16
16
16
40
RoHS & Green
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Level-3-260C-168 HR
Level-3-260C-168 HR
N / A for Pkg Type
PGA204BU
PGA204BU
PGA205AP
PGA205AU
PGA205AU
PGA205BP
PGA205BU
PGA205BU
1000 RoHS & Green
25
40
RoHS & Green
RoHS & Green
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
PGA205AU
DW
DW
N
Level-3-260C-168 HR
Level-3-260C-168 HR
N / A for Pkg Type
PGA205AU/1K
PGA205BP
1000 RoHS & Green
25
40
40
RoHS & Green
RoHS & Green
RoHS & Green
PGA205BU
DW
DW
Level-3-260C-168 HR
Level-3-260C-168 HR
PGA205BUG4
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jun-2023
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
PGA204AU/1K
PGA204BU/1K
PGA205AU/1K
SOIC
SOIC
SOIC
DW
DW
DW
16
16
16
1000
1000
1000
330.0
330.0
330.0
16.4
16.4
16.4
10.75 10.7
10.75 10.7
10.75 10.7
2.7
2.7
2.7
12.0
12.0
12.0
16.0
16.0
16.0
Q1
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
PGA204AU/1K
PGA204BU/1K
PGA205AU/1K
SOIC
SOIC
SOIC
DW
DW
DW
16
16
16
1000
1000
1000
356.0
356.0
356.0
356.0
356.0
356.0
35.0
35.0
35.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
PGA204AP
PGA204AU
PGA204AUE4
PGA204BP
PGA204BU
PGA205AP
PGA205AU
PGA205BP
PGA205BU
PGA205BUG4
N
PDIP
SOIC
SOIC
PDIP
SOIC
PDIP
SOIC
PDIP
SOIC
SOIC
16
16
16
16
16
16
16
16
16
16
25
40
40
25
40
25
40
25
40
40
506
507
507
506
507
506
507
506
507
507
13.97
12.83
12.83
13.97
12.83
13.97
12.83
13.97
12.83
12.83
11230
5080
5080
11230
5080
11230
5080
11230
5080
5080
4.32
6.6
DW
DW
N
6.6
4.32
6.6
DW
N
4.32
6.6
DW
N
4.32
6.6
DW
DW
6.6
Pack Materials-Page 3
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