PGA2310 [TI]
具有低增益误差 (0.05) 的 +/-15V 立体声音频音量控制;
| 型号： | PGA2310 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有低增益误差 (0.05) 的 +/-15V 立体声音频音量控制 |
| 文件： | 总27页 (文件大小：1128K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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PGA2310
SBOS207C –OCTOBER 2001–REVISED DECEMBER 2015
PGA2310 Stereo Audio Volume Control
1 Features
3 Description
The PGA2310 is a high-performance, stereo audio
volume control designed for professional and high-
end consumer audio systems. The ability to operate
from ±15-V analog power supplies enables the
PGA2310 to process input signals with large voltage
swings, thereby preserving the dynamic range
available in the overall signal path. Using high
performance operational amplifier stages internal to
the PGA2310 yields low noise and distortion, while
providing the capability to drive 600-Ω loads directly
without buffering. The three-wire serial control
interface allows for connection to a wide variety of
host controllers, in addition to support for daisy-
chaining multiple PGA2310 devices.
1
•
Digitally-Controlled Analog Volume Control:
–
–
–
–
Two Independent Audio Channels
Serial Control Interface
Zero Crossing Detection
Mute Function
•
•
Wide Gain and Attenuation Range: 31.5 dB to
−95.5 dB With 0.5-dB Steps
Low Noise and Distortion:
–
–
120-dB Dynamic Range
0.0004% THD+N at 1 kHz
•
•
•
•
•
Low Interchannel Crosstalk: −126 dBFS
Noise-Free Level Transitions
Device Information(1)
Power Supplies: 15-V Analog, 5-V Digital
Available in DIP−16 and SOL−16 Packages
PART NUMBER
PACKAGE
SOIC (16)
PDIP (16)
BODY SIZE (NOM)
7.50 mm × 10.30 mm
6.35 mm × 19.30 mm
PGA2310
Pin and Software Compatible With the PGA2311
and Cirrus Logic CS3310™
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
•
•
•
•
•
•
•
Audio Amplifiers
Mixing Consoles
Multi-Track Recorders
Broadcast Studio Equipment
Musical Instruments
Effects Processors
A/V Receivers
Car Audio Systems
Stereo Audio Volume Control
16
VINL
14
8
VOUT
L
MUTE
MUX
8
1
2
6
3
7
ZCEN
CS
8
15
10
Serial
Control
Port
AGNDL
AGNDR
SCLK
SDI
SDO
8
8
MUX
11
VOUT
R
9
VINR
12
13
4
5
−
VA+VA
VD+ DGND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
PGA2310
SBOS207C –OCTOBER 2001–REVISED DECEMBER 2015
www.ti.com
Table of Contents
7.4 Device Functional Modes........................................ 12
Application and Implementation ........................ 13
8.1 Application Information............................................ 13
8.2 Typical Application ................................................. 13
Power Supply Recommendations...................... 15
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings ............................................................ 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 6
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
7.3 Feature Description................................................... 8
8
9
10 Layout................................................................... 15
10.1 Layout Guidelines ................................................. 15
10.2 Layout Example .................................................... 15
11 Device and Documentation Support ................. 16
11.1 Device Support .................................................... 16
11.2 Documentation Support ....................................... 16
11.3 Community Resources.......................................... 16
11.4 Trademarks........................................................... 16
11.5 Electrostatic Discharge Caution............................ 16
11.6 Glossary................................................................ 16
7
12 Mechanical, Packaging, and Orderable
Information ........................................................... 16
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (June 2004) to Revision C
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1
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SBOS207C –OCTOBER 2001–REVISED DECEMBER 2015
5 Pin Configuration and Functions
D and P Pakcages
16 Pins SOIC and PDIP
Top View
1
2
3
4
5
6
7
8
16
15
ZCEN
CS
VIN
L
AGNDL
SDI
14 VOUT
13 VA−
12 VA+
L
VD+
PGA2310
DGND
SCLK
SDO
MUTE
11
10
9
V
OUTR
AGNDR
VIN
R
Pin Functions
PIN
I/O
DESCRIPTION
NO.
1
NAME
ZCEN
CS
I
I
Zero Crossing Enable Input (Active High)
Chip Select Input (Active Low)
Serial Data Input
2
3
SDI
I
4
VD+
I
Digital Power Supply, 5 V
Digital Ground
5
DGND
SCLK
SDO
MUTE
—
I
6
Serial Clock Input
7
O
I
Serial Data Output
8
Mute Control Input (Active Low)
Analog Input, Right Channel
Analog Ground, Right Channel
Analog Output, Right Channel
Analog Power Supply, 15 V
Analog Power Supply, –15 V
Analog Output, Left Channel
Analog Ground, Left Channel
Analog Input, Left Channel
9
VIN
AGNDR
VOUT
R
I
10
11
12
13
14
15
16
—
O
I
R
VA+
VA–
I
VOUT
L
O
—
I
AGNDL
VINL
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
16
UNIT
VA+
Supply Voltage
VA–
VD+
–16
V
6.5
Analog input voltage
0
VA+,VA–
VD+
125
V
Digital input voltage
–0.3
–55
V
Operating temperature
°C
°C
°C
°C
°C
Junction temperature
150
Lead temperature (soldering, 10 s)
Package temperature (IR, reflow, 10 s)
Storage temperature
300
235
Tstg
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
UNIT
V(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±4000
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
NOM
15
MAX
15.5
–15.5
5.5
UNIT
V
VA+
VA–
VD+
Positive analog power supply
Negative analog power supply
Digital power supply
–4.5
4.5
–15
5
V
V
Operating temperature
–55
25
125
°C
6.4 Thermal Information
PGA2310
THERMAL METRIC(1)
D (SOIC)
16 PINS
83
P (PDIP)
UNIT
16 PINS
39.9
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
44
26.2
40.5
20.1
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
11.5
10.7
ψJB
40.2
19.9
RθJC(bot)
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
At TA = 25°C, VA+ = 15 V, VA− = −15 V, VD+ = 5 V, RL = 100 kΩ, CL = 20 pF, BW measure = 10 Hz to 20 kHz, unless
otherwise noted.
PARAMETER
DC CHARACTERISTICS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Step Size
Gain Error
0.5
±0.05
±0.05
10
dB
dB
dB
kΩ
pF
Gain Setting = 31.5 dB
Gain Matching
Input Resistance
Input Capacitance
AC CHARACTERISTICS
THD+N
7
VIN = 10 VPP, f = 1 kHz
0.0004%
120
0.001%
Dynamic Range
VIN = AGND, Gain = 0 dB
116
dB
V
Voltage Range, Input and Output
(VA−) + 1.5
(VA−) − 1.5
Output Noise
VIN = AGND, Gain = 0 dB
f = 1 kHz
9.5
13.5 μVRMS
Interchannel Crosstalk
–126
dBFS
OUTPUT BUFFER
Offset Voltage
VIN = AGND, Gain = 0 dB
0.5
1000
35
3
mV
pF
Load Capacitance Stability
Short-Circuit Current
mA
MHz
Unity-Gain Bandwidth, Small Signal
1.5
DIGITAL CHARACTERISTICS
High-Level Input Voltage, VIH
Low-Level Input Voltage, VIL
High-Level Output Voltage, VOH
Low-Level Output Voltage, VOL
Input Leakage Current
2
–0.3
VD+
0.8
V
V
IO = 200 μA
(VD+) − 1
V
IO = –3.2 mA
0.4
10
V
1
µA
SWITCHING CHARACTERISTICS
tSCLK
tPL
Serial Clock (SCLK) Frequency
Serial Clock (SCLK) Pulse Width Low
Serial Clock (SCLK) Pulse Width High
MUTE Pulse Width Low
0
80
80
2
6.25
MHz
ns
tPH
ns
tMI
ms
INPUT TIMING
tSDS SDI Setup Time
tSDH SDI Hold Time
20
20
90
35
ns
ns
ns
ns
tCSCR CS Falling to SCLK Rising
tCFCS SCLK Falling to CS Rising
OUTPUT TIMING
tCSO
tCFDO SCLK Falling to SDO Data Valid
tCSZ CS High to SDO High Impedance
POWER SUPPLY
CS Low to SDO Active
35
60
ns
ns
ns
100
VA+
VA–
VD+
IA+
4.5
–4.5
4.5
15
–15
5
15.5
–15.5
5.5
Operating Voltage
V
VA+ = 15 V
VA– = –15 V
VD+ = 5 V
7.5
7.7
0.8
10
Quiescent Current
IA–
10
mA
ID+
1.5
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Electrical Characteristics (continued)
At TA = 25°C, VA+ = 15 V, VA− = −15 V, VD+ = 5 V, RL = 100 kΩ, CL = 20 pF, BW measure = 10 Hz to 20 kHz, unless
otherwise noted.
PARAMETER
TEMPERATURE RANGE
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Specified Range
Operating Range
–40
–55
85
°C
°C
125
6.6 Typical Characteristics
At TA = 25°C, VA+ = 15 V, VA− = −15 V, VD+ = 5 V, RL = 100 kΩ, CL = 20 pF, BW measure = 10 Hz to 20 kHz, unless
otherwise noted.
1
0.8
0.6
0.4
0.2
0
1
0.1
0.01
−
0.2
0.4
0.6
0.8
−
−
−
0.001
0.0001
−
1
10
100
10k
200k
1k
100m
1
9
Frequency (Hz)
Amplitude (VRMS
)
Figure 1. Frequency Response
Figure 2. THD+N vs Amplitude
0.05
0.01
0.05
0.01
0.001
0.001
0.0001
0.0001
20
20k
20
20k
100
1k
10k
100
1k
10k
Frequency (Hz)
Frequency (Hz)
Figure 3. THD+N vs Frequency
Figure 4. THD+N vs Frequency
(VIN = 3 VRMS, Load = 100 kΩ)
(VIN = 3 VRMS, Load = 600 kΩ)
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Typical Characteristics (continued)
At TA = 25°C, VA+ = 15 V, VA− = −15 V, VD+ = 5 V, RL = 100 kΩ, CL = 20 pF, BW measure = 10 Hz to 20 kHz, unless
otherwise noted.
0.05
0.05
0.01
0.01
0.001
0.001
0.0001
0.0001
20
100
1k
10k 20k
20
20k
100
1k
10k
Frequency (Hz)
Frequency (Hz)
Figure 5. THD+N vs Frequency
Figure 6. THD+N vs Frequency
(VIN = 8.5 VRMS, Load = 100 kΩ)
(VIN = 8.5 VRMS, Load = 600 kΩ)
0
0
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
10
20
30
40
50
60
70
80
90
10
20
30
40
50
60
70
80
90
−
−
100
110
120
130
140
150
160
100
110
120
130
140
150
160
−
−
−
−
−
−
−
−
−
−
−
−
20 2k 4k 6k 8k 10k 12k 14k 16k 18k 20k 22k
Frequency (Hz)
0
2k 4k 6k 8k 10k 12k 14k 16k 18k 20k 22k
Frequency (Hz)
Figure 7. Amplitude vs Frequency
(Crosstalk With fIN = 1 kHz)
Figure 8. Amplitude vs Frequency
(Crosstalk with fIN = 10 kHz)
0
−
−
−
−
−
−
−
−
−
10
20
30
40
50
60
70
80
90
−
100
110
120
130
140
150
160
−
−
−
−
−
−
0
22k
2k 4k 6k 8k 10k 12k 14k 16k 18k 20k
Frequency (Hz)
Figure 9. Amplitude vs Frequency
(Crosstalk With fIN = 20 kHz)
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7 Detailed Description
7.1 Overview
The PGA2310 is a stereo audio volume control that can be used in a wide array of professional and consumer
audio equipment. The PGA2310 is fabricated in a mixed-signal BiCMOS process for superior analog
characteristics.
The heart of the PGA2310 is a resistor network, an analog switch array, and a high-performance bipolar op amp
stage. The switches select taps in the resistor network that determine the gain of the amplifier stage. Switch
selections are programmed using a serial control port. The serial port allows connection to a wide variety of host
controllers.
7.2 Functional Block Diagram
16
VINL
14
8
VOUT
L
MUTE
MUX
8
1
2
6
3
7
ZCEN
CS
8
15
10
Serial
Control
Port
AGNDL
AGNDR
SCLK
SDI
SDO
8
8
MUX
11
VOUT
R
9
VINR
12
13
4
5
−
VA+VA
VD+ DGND
7.3 Feature Description
7.3.1 Analog Inputs and Outputs
The PGA2310 includes two independent channels, referred to as the left and right channels. Each channel has a
corresponding input and output pin. The input and output pins are unbalanced, or referenced to analog ground
(either AGNDR or AGNDL). The inputs are VINR (pin 9) and VINL (pin 16), while the outputs are VOUTR (pin 11)
and VOUTL (pin 14).
The input and output pins may swing within 1.5 V of the analog power supplies, VA+ (pin 12) and VA− (pin 13).
Given VA+ = 15 V and VA− = −15 V, the maximum input or output voltage range is 27 VPP
.
Drive the PGA2310 with a low source impedance. If a source impedance of greater than 600 Ω is used, the
distortion performance of the PGA2310 begins to degrade.
7.3.2 Serial Control Port
The serial control port is used to program the gain settings for the PGA2310. The serial control port includes
three input pins and one output pin. The inputs include CS (pin 2), SDI (pin 3), and SCLK (pin 6). The sole output
pin is SDO (pin 7).
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Feature Description (continued)
The CS pin functions as the chip select input. Data may be written to the PGA2310 only when CS is low. SDI is
the serial data input pin. Control data is provided as a 16-bit word at the SDI pin, 8 bits each for the left and right
channel gain settings. Data is formatted as MSB first, in straight binary code. SCLK is the serial clock input. Data
is clocked into SDI on the rising edge of SCLK.
SDO is the serial data output pin, and used when daisy-chaining multiple PGA2310 devices. Daisy-chain
operation is described in Daisy-Chaining Multiple PGA2310 Devices. SDO is a tristate output, and assumes a
high impedance state when CS is high.
The protocol for the serial control port is shown in Figure 10. Figure 11 shows detailed timing specifications of
the serial control port.
CS
SCLK
SDI
R7
R7
R6
R6
R5
R5
R4
R4
R3
R3
R2
R2
R1
R1
R0
R0
L7
L7
L6
L6
L5
L5
L4
L4
L3
L3
L2
L2
L1
L1
L0
L0
SDO
Gain Byte Format is MSB First, Straight Binary
R0 is the Least Significant Bit of the Right Channel Gain Byte
R7 is the Most Significant Bit of the Right Channel Gain Byte
L0 is the Least Significant Bit of the Left Channel Gain Byte
L7 is the Most Significant Bit of the Left Channel Gain Byte
SDI is latched on the rising edge of SCLK.
SDO transitions on the falling edge of SCLK.
Figure 10. Serial Interface Protocol
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Feature Description (continued)
CS
tCSCR
tSDS
tCFCS
SCLK
tSDH
SDI
MSB
SDO
tCFDO
tCSZ
tCSO
Figure 11. Serial Interface Timing Requirements
7.3.3 Gain Settings
The gain for each channel is set by its corresponding 8-bit code, either R[7:0] or L[7:0] (see Figure 10). The gain
code data is straight binary format. If N equals the decimal equivalent of R[7:0] or L[7:0], then the following
relationships exist for the gain settings:
•
•
For N = 0: Mute Condition. The input multiplexer is connected to analog ground (AGNDR or AGNDL).
For N = 1 to 255: Gain (dB) = 31.5 − [0.5 • (255 − N)]
This results in a gain range of 31.5 dB (with N = 255) to −95.5 dB (with N = 1).
Changes in gain setting may be made with or without zero crossing detection. The operation of the zero crossing
detector and time-out circuitry is discussed in Zero Crossing Detection.
7.3.4 Daisy-Chaining Multiple PGA2310 Devices
To reduce the number of control signals required to support multiple PGA2310 devices on a printed-circuit-board,
the serial control port supports daisy-chaining of multiple PGA2310 devices. Figure 12 shows the connection
requirements for daisy-chain operation. This arrangement allows a three-wire serial interface to control many
PGA2310 devices.
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Feature Description (continued)
Controller
SDI
SCLK
CS
VIN
L
Audio
Input
PGA2310
V
INR
#1
VOUT
VOUT
L
SDO
R
Ω
100k
SDI
SCLK
CS
VIN
L
Audio
Input
PGA2310
VINR
#2
VOUT
L
SDO
SDI
VOUTR
Ω
100k
SCLK
CS
VIN
L
Audio
Input
PGA2310
VINR
#3
VOUT
VOUT
L
SDO
R
Figure 12. Daisy-Chaining Multiple PGA2310 Devices
As shown in Figure 12, the SDO pin from device 1 is connected to the SDI input of device 2, and is repeated for
additional devices. This in turn forms a large shift register, in which gain data may be written for all PGA2310s
connected to the serial bus. The length of the shift register is 16 × N bits, where N is equal to the number of
PGA2310 devices included in the chain. The CS input must remain low for 16 × N SCLK periods, where N is the
number of devices connected in the chain, to allow enough SCLK cycles to load all devices.
7.3.5 Zero Crossing Detection
The PGA2310 includes a zero crossing detection function that can provide for noise-free level transitions. The
concept is to change gain settings on a zero crossing of the input signal, thus minimizing audible glitches. This
function is enabled or disabled using the ZCEN input (pin 1). When ZCEN is low, zero crossing detection is
disabled. When ZCEN is high, zero crossing detection is enabled.
The zero crossing detection takes effect with a change in gain setting for a corresponding channel. The new gain
setting is not latched until either two zero crossings are detected, or a time-out period of 16 ms has elapsed
without detecting two zero crossings. In the case of a time-out, the new gain setting takes effect with no attempt
to minimize audible artifacts.
7.3.6 Mute Function
The PGA2310 includes a mute function. This function may be activated by either the MUTE input (pin 8), or by
setting the gain byte value for one or both channels to 00HEX. The MUTE pin may be used to mute both
channels, while the gain setting may be used to selectively mute the left and right channels. Muting is
accomplished by switching the input multiplexer to analog ground (AGNDR or AGNDL) with zero crossing
enabled.
The MUTE pin is active low. When MUTE is low, each channel is muted following the next zero crossing event or
time-out that occurs on that channel. If MUTE becomes active while CS is also active, the mute takes effect once
the CS pin goes high. When the MUTE pin is high, the PGA2310 operates normally, with the mute function
disabled.
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7.4 Device Functional Modes
7.4.1 Power-Up State
On power up, all internal flip-flops are reset. The gain byte value for both the left and right channels are set to
00HEX, or mute condition. The gain remains at this setting until the host controller programs new settings for each
channel using the serial control port.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The PGA2310 is commonly used as a digitally controlled analog volume control. Analog volume is controlled
through a serial interface in 0.5-dB steps, ranging from a gain of 31.5 dB down to an attenuation of −95.5 dB.
8.2 Typical Application
Figure 13 depicts the recommended connections for the PGA2310.
+5V Digital
ZCEN
VIN
L
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CS
SDI
VOUT
L
C3
C5
C4
C6
−15V Analog
+15V Analog
C1
C2
Controller
PGA2310
SCLK
MUTE
VOUT
R
SDO
VINR
µ
C2, C3, C5 = 0.1 F ceramic or metal film.
µ
C1, C4, C6 = 10 F tantalum or aluminum electrolytic.
To
Additional
DGND
AGND
PGA2310s
Figure 13. Recommended Connection Diagram
8.2.1 Design Requirements
•
•
•
Wide dynamic range: 35.5 dB to –95.5 dB
Operate from 5-V digital supply and ±15-V analog supplies
Digitally controlled analog volume
8.2.2 Detailed Design Procedure
The PGA2310 is a complete digitally controlled analog stereo volume controller system on a chip requiring only a
controller to select the gain or attenuation through a serial interface. Figure 13 illustrates the basic connections to
the PGA2310. Power-supply bypass capacitors should be placed as close to the PGA2310 package as
physically possible.
Copyright © 2001–2015, Texas Instruments Incorporated
Submit Documentation Feedback
13
Product Folder Links: PGA2310
PGA2310
SBOS207C –OCTOBER 2001–REVISED DECEMBER 2015
www.ti.com
Typical Application (continued)
8.2.3 Application Curve
3
1.5
0
0 dB
-6 dB
-12 dB
-1.5
-3
0
0.0004
0.0008
0.0012
0.0016
0.002
Time (s)
Figure 14. PGA2310 Operating at 0 dB, –6 dB and –12 dB
14
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Copyright © 2001–2015, Texas Instruments Incorporated
Product Folder Links: PGA2310
PGA2310
www.ti.com
SBOS207C –OCTOBER 2001–REVISED DECEMBER 2015
9 Power Supply Recommendations
The PGA2310 is specified for operation with its analog power supplies ranging from ±4.5 V to ±15.5 V and its
digital power supply ranging from 4.5 V to 5.5 V.
10 Layout
10.1 Layout Guidelines
TI recommends that the ground planes for the digital and analog sections of the printed-circuit-board (PCB) be
separate from one another. The planes should be connected at a single point. Figure 15 shows the
recommended PCB floor plan for the PGA2310.
The PGA2310 is mounted so that it straddles the split between the digital and analog ground planes. Pins 1
through 8 are oriented to the digital side of the board, while pins 9 through 16 are on the analog side of the
board.
10.2 Layout Example
Digital Power
+5V
Analog Power
DGND
AGND
−15V
+15V
Analog
Inputs
and
Host
PGA2310
Outputs
DIGITAL GROUND PLANE
ANALOG GROUND PLANE
Analog
Ground
Digital
Ground
Figure 15. Typical PCB Layout Floor Plan
Copyright © 2001–2015, Texas Instruments Incorporated
Submit Documentation Feedback
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Product Folder Links: PGA2310
PGA2310
SBOS207C –OCTOBER 2001–REVISED DECEMBER 2015
www.ti.com
11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
For immediate development support with the PGA2310, visit Audio Amplifiers Section of the TI E2E Support
Community. Here you may view previously answered questions or submit a new question to the team of
application experts.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
•
•
•
Circuit Board Layout Techniques, SLOA089
Shelf-Life Evaluation of Lead-Free Component Finishes, SZZA046
PGA2310-EVM: Evaluation Module User's Manual, SBOU012
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
CS3310 is a trademark of Cirrus Logic, Inc..
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
16
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Copyright © 2001–2015, Texas Instruments Incorporated
Product Folder Links: PGA2310
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jun-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PGA2310PA
PGA2310UA
ACTIVE
ACTIVE
ACTIVE
LIFEBUY
PDIP
SOIC
SOIC
SOIC
N
16
16
16
16
25
40
RoHS & Green
RoHS & Green
NIPDAU
N / A for Pkg Type
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
PGA2310PA
Samples
Samples
Samples
DW
DW
DW
NIPDAU
NIPDAU
NIPDAU
PGA2310UA
PGA2310UA
PGA2310UA
PGA2310UA/1K
PGA2310UAG4
1000 RoHS & Green
40 RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jun-2023
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
PGA2310UA/1K
SOIC
DW
16
1000
330.0
16.4
10.75 10.7
2.7
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC DW 16
SPQ
Length (mm) Width (mm) Height (mm)
356.0 356.0 35.0
PGA2310UA/1K
1000
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
PGA2310PA
PGA2310UA
N
PDIP
SOIC
SOIC
16
16
16
25
40
40
506
507
507
13.97
12.83
12.83
11230
5080
5080
4.32
6.6
DW
DW
PGA2310UAG4
6.6
Pack Materials-Page 3
GENERIC PACKAGE VIEW
DW 16
7.5 x 10.3, 1.27 mm pitch
SOIC - 2.65 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224780/A
www.ti.com
PACKAGE OUTLINE
DW0016A
SOIC - 2.65 mm max height
S
C
A
L
E
1
.
5
0
0
SOIC
C
10.63
9.97
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
14X 1.27
16
1
2X
10.5
10.1
NOTE 3
8.89
8
9
0.51
0.31
16X
7.6
7.4
B
2.65 MAX
0.25
C A B
NOTE 4
0.33
0.10
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 - 8
1.27
0.40
DETAIL A
TYPICAL
(1.4)
4220721/A 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0016A
SOIC - 2.65 mm max height
SOIC
16X (2)
SEE
DETAILS
SYMM
1
16
16X (0.6)
SYMM
14X (1.27)
R0.05 TYP
9
8
(9.3)
LAND PATTERN EXAMPLE
SCALE:7X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220721/A 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0016A
SOIC - 2.65 mm max height
SOIC
16X (2)
SYMM
1
16
16X (0.6)
SYMM
14X (1.27)
R0.05 TYP
8
9
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:7X
4220721/A 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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