PGA309_14 [TI]
Voltage Output Programmable Sensor Conditioner;
| 型号： | PGA309_14 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Voltage Output Programmable Sensor Conditioner |
| 文件： | 总24页 (文件大小：812K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PGA309
www.ti.com
SBOS292C –DECEMBER 2003–REVISED JANUARY 2011
Voltage Output
Programmable Sensor Conditioner
Check for Samples: PGA309
1
FEATURES
DESCRIPTION
2
•
•
•
•
Complete Bridge Sensor Conditioner
Voltage Output: Ratiometric or Absolute
Digital Cal: No Potentiometers/Sensor Trims
Sensor Error Compensation
The PGA309 is a programmable analog signal
conditioner designed for bridge sensors. The analog
signal path amplifies the sensor signal and provides
digital calibration for zero, span, zero drift, span drift,
and sensor linearization errors with applied stress
(pressure, strain, etc.). The calibration is done via a
–
Span, Offset, and Temperature Drifts
One-Wire digital serial interface or through
Two-Wire industry-standard connection. The
calibration parameters are stored in external
nonvolatile memory (typically SOT23-5) to eliminate
manual trimming and achieve long-term stability.
a
•
•
•
•
Low Error, Time-Stable
Sensor Linearization Circuitry
Temperature Sense: Internal or External
Calibration Lookup Table Logic
–
Uses External EEPROM (SOT23-5)
The all-analog signal path contains a 2x2 input
multiplexer (mux), auto-zero programmable-gain
instrumentation amplifier, linearization circuit, voltage
reference, internal oscillator, control logic, and an
output amplifier. Programmable level shifting
compensates for sensor dc offsets.
•
•
•
•
•
Over/Under-Scale Limiting
Sensor Fault Detection
+2.7V TO +5.5V Operation
–40°C to +125°C Operation
Small TSSOP-16 Package
The core of the PGA309 is the precision, low-drift, no
1/f noise Front-End PGA (Programmable Gain
Amplifier). The overall gain of the Front-End PGA +
Output Amplifier can be adjusted from 2.7V/V to
1152V/V. The polarity of the inputs can be switched
through the input mux to accommodate sensors with
unknown polarity output. The Fault Monitor circuit
detects and signals sensor burnout, overload, and
system fault conditions.
APPLICATIONS
•
•
•
•
Bridge Sensors
Remote 4-20mA Transmitters
Strain, Load, and Weigh Scales
Automotive Sensors
EVALUATION TOOLS
For detailed application information, see the PGA309
User's Guide (SBOU024) available for download at
www.ti.com.
•
Hardware Designer’s Kit (PGA309EVM)
–
–
–
Temperature Eval of PGA309 + Sensor
Full Programming of PGA309
Sensor Compensation Analysis Tool
VS
Ref
Linearization
Circuit
Nonlinear
Bridge
VEXC
PGA309
Transducer
Lin DAC
P
Analog Sensor Linearization
psi
0
50
Over/Under
Scale Limiter
Linear
VOUT
Fault
Monitor
Auto- Zero
PGA
Analog Signal Conditioning
+125°C
-40°C
Digital
Digital Cal
Int Temp
Temperature
Compensation
T
Temp
ADC
EEPROM
(SOT23-5)
Control Register
Interface Circuitry
Ext Temp
Ext Temp
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2011, Texas Instruments Incorporated
PGA309
SBOS292C –DECEMBER 2003–REVISED JANUARY 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION(1)
PACKAGE
DESIGNATOR
PACKAGE
MARKING
PRODUCT
PACKAGE-LEAD
PGA309
TSSOP-16
PW
PGA309
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range, unless otherwise noted.
PARAMETER
PGA309
UNIT
V
Supply Voltage, VSD, VSD
+7.0
(2)
Input Voltage, VIN1, VIN2
Input Current, VFB, VOUT
Input Current
–0.3 to VSA +0.3
V
±150
±10
mA
mA
mA
°C
Output Current Limit
50
Storage Temperature Range
Operating Temperature Range
Junction Temperature
–60 to +150
–55 to +150
+150
°C
°C
ESD Ratings
Human Body Model (HBM)
4
kV
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5V beyond the supply rails should
be current limited to 10mA or less.
2
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Product Folder Link(s): PGA309
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SBOS292C –DECEMBER 2003–REVISED JANUARY 2011
ELECTRICAL CHARACTERISTICS
Boldface limits apply over the specified temperature range, TA = –40°C to +125°C.
At TA = +25°C, VSA= VSD = +5V (VSA = VSUPPLY ANALOG, VSD = VSUPPLY DIGITAL; VSA must equal VSD), GNDD = GNDA = 0, and VREF
= REFIN/REFOUT = +5V, unless otherwise noted.
PGA309
PARAMETER
Front-End PGA + Output Amplifier
VOUT/VIN Differential Signal Gain Range(1)
CONDITIONS
MIN
TYP
MAX
UNIT
Fine gain adjust = 1
Front-End PGA Gains: 4, 8, 16, 23.27, 32, 42.67, 64, 128
Output Amplifier gains: 2, 2.4, 3, 3.6, 4.5, 6, 9
f = 1kHz
8 to 1152
V/V
Input Voltage Noise Density
VOUT Slew Rate
210
0.5
nV/√Hz
V/ms
ms
VOUT Settling Time (0.01%)
VOUT Settling Time (0.01%)
VOUT Nonlinearity
VOUT/VIN Differential gain = 8, RL = 5kΩ || 200pF
VOUT/VIN Differential gain = 191, RL = 5kΩ || 200pF
6
4.1
ms
0.002
1 to 245
%FSR
mV/V
External Sensor Output Sensitivity
Front-End PGA
VSA = VSD = VEXC = +5V
Coarse offset adjust disabled
GF = Front-End PGA gain
Auto-Zero Internal Frequency
Offset Voltage (RTI)(2)
vs Temperature
7
±3
kHz
mV
±50
±0.2
±2
mV/°C
mV/V
mV/V
V
vs Supply Voltage, VSA
vs Common-Mode Voltage
Linear Input Voltage Range(3)
Input Bias Current
1500/GF
6000/GF
0.2
V
SA − 1.5
0.1
30 || 6
50 || 20
4
1.5
nA
Input Impedance: Differential
Input Impedance: Common-Mode
Input Voltage Noise
GΩ || pF
GΩ || pF
mVPP
0.1Hz to 10Hz, GF = 128
PGA Gain
Gain Range Steps
4, 8, 16, 23.27, 32, 42.67, 64, 128
4 to 128
V/V
%
Initial Gain Error
GF = 4 to 42
GF = 64
0.2
±1
0.25
±1.2
±1.6
%
GF = 128
0.3
%
vs Temperature
Output Voltage Range
Bandwidth
10
ppm/°C
V
0.05 to VSA − 0.1
Gain = 4
400
60
kHz
kHz
Gain = 128
Coarse Offset Adjust
(RTI of Front-End PGA)
Range
±(14)(VREF)(0.00085)
±14 steps, 4-bit + sign
±56
±59.5
0.004
4
±64
mV
%/°C
mV
vs Temperature
Drift
Fine Offset Adjust (Zero DAC)
(RTO of the Front-End PGA)(2)
Programming Range
Output Voltage Range
Resolution
0
VREF
V
V
0.1
VSA – 0.1
65,536 steps, 16-bit DAC
73
20
0.5
0.1
10
5
mV
Integral Nonlinearity
Differential Nonlinearity
Gain Error
LSB
LSB
%
Gain Error Drift
Offset
ppm/°C
mV
Offset Drift
10
mV/°C
(1) PGA309 total differential gain from input (VIN1 – VIN2) to output (VOUT). VOUT / (VIN1 – VIN2) = (Front-end PGA gain) × (Output Amplifier
gain) × (Gain DAC).
(2) RTI = Referred-to-input. RTO = referred to output.
(3) Linear input range is the allowed min/max voltage on the VIN1 and VIN2 pins for the input PGA to continue to operate in a linear region.
The allowed common-mode and differential voltage depends on gain and offset settings. Refer to the Gain Scaling section for more
information.
Copyright © 2003–2011, Texas Instruments Incorporated
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ELECTRICAL CHARACTERISTICS (continued)
Boldface limits apply over the specified temperature range, TA = –40°C to +125°C.
At TA = +25°C, VSA= VSD = +5V (VSA = VSUPPLY ANALOG, VSD = VSUPPLY DIGITAL; VSA must equal VSD), GNDD = GNDA = 0, and VREF
= REFIN/REFOUT = +5V, unless otherwise noted.
PGA309
PARAMETER
Output Fine Gain Adjust (Gain DAC)
Range
CONDITIONS
MIN
TYP
MAX
UNIT
0.33 to 1
10
V/V
mV/V
LSB
LSB
Resolution
65,536 steps, 16-bit DAC
Integral Nonlinearity
20
Differential Nonlinearity
Output Amplifier
0.5
Offset Voltage (RTI of Output Amplifier)(4)
3
5
mV
mV/°C
mV/V
V
vs Temperature
vs Supply Voltage, VSA
Common-Mode Input Range
Input Bias Current
30
0
VS – 1.5
100
pA
Amplifier Internal Gain
Gain Range Steps
2, 2.4, 3, 3.6, 4.5, 6, 9
2 to 9
0.25
0.3
0.4
0.6
5
V/V
%
Initial Gain Error
2, 2.4, 3.6
±1
4.5
±1.2
±1.5
±2.0
%
6
%
9
%
vs Temperature
2, 2.4, 3.6
ppm/°C
ppm/°C
ppm/°C
ppm/°C
V
4.5
5
6
9
15
30
Output Voltage Range(5)
Open-Loop Gain
RL = 10kΩ
0.1
4.9
115
2
dB
Gain-Bandwidth Product
Phase Margin
MHz
deg
Gain = 2, CL = 200pF
45
Output Resistance
AC Small-signal, open-loop, f = 1MHz, IO = 0
VREF = 4.096
675
Ω
Over- and Under-Scale Limits
Over-Scale Thresholds
Ratio of VREF, Register 5—bits D5, D4, D3 = ‘000’
Ratio of VREF, Register 5—bits D5, D4, D3 = ‘001’
Ratio of VREF, Register 5—bits D5, D4, D3 = ‘010’
Ratio of VREF, Register 5—bits D5, D4, D3 = ‘011’
Ratio of VREF, Register 5—bits D5, D4, D3 = ‘100’
Ratio of VREF, Register 5—bits D5, D4, D3 = ‘101’
Ratio of VREF, Register 5—bits D5, D4, D3 = ‘110’
0.9708
0.9610
0.9394
0.9160
0.9102
0.7324
0.5528
+60
Over-Scale Comparator Offset
Over-Scale Comparator Offset Drift
Under-Scale Thresholds
+6
+114
mV
+0.37
mV/°C
Ratio of VREF, Register 5—bits D2, D1, D0 = ‘111’
Ratio of VREF, Register 5—bits D2, D1, D0 = ‘110’
Ratio of VREF, Register 5—bits D2, D1, D0 = ‘101’
Ratio of VREF, Register 5—bits D2, D1, D0 = ‘100’
Ratio of VREF, Register 5—bits D2, D1, D0 = ‘011’
Ratio of VREF, Register 5—bits D2, D1, D0 = ‘010
Ratio of VREF, Register 5—bits D2, D1, D0 = ‘001’
Ratio of VREF, Register 5—bits D2, D1, D0 = ‘000’
0.0605
0.0547
0.0507
0.0449
0.0391
0.0352
0.0293
0.0254
−50
Unde-rScale Comparator Offset
−7
+93
mV
Under-Scale Comparator Offset Drift
−0.15
mV/°C
(4) RTI = Referred-to-input. RTO = referred to output.
(5) Unless limited by the over/under-scale setting.
4
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Product Folder Link(s): PGA309
PGA309
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SBOS292C –DECEMBER 2003–REVISED JANUARY 2011
ELECTRICAL CHARACTERISTICS (continued)
Boldface limits apply over the specified temperature range, TA = –40°C to +125°C.
At TA = +25°C, VSA= VSD = +5V (VSA = VSUPPLY ANALOG, VSD = VSUPPLY DIGITAL; VSA must equal VSD), GNDD = GNDA = 0, and VREF
= REFIN/REFOUT = +5V, unless otherwise noted.
PGA309
PARAMETER
Fault Monitor Circuit
CONDITIONS
MIN
TYP
MAX
UNIT
(6)
INP_HI, INN_HI Comparator Threshold
INP_LO, INN_LO Comparator Threshold
A1SAT_HI, A2SAT_HI Comparator Threshold
A1SAT_LO, A2SAT_LO Comparator Threshold
A3_VCM Comparator Threshold
Comparator Hysteresis
See
V
SA− 1.2 or VEXC− 0.1
V
mV
V
40
100
V
SA− 0.12
SA− 0.12
V
V
VSA− 1.2
V
20
mV
Internal Voltage Reference
VREF1
Register 3, bit D9 = 1
Register 3, bit D9 = 0
2.46
4.0
2.5
+10
4.096
+10
100
1
2.53
V
ppm/°C
V
VREF1 Drift vs Temperature
VREF2
IPU
4.14
VREF2 Drift vs Temperature
Input Current REFIN/REFOUT
Output Current REFIN/REFOUT
±7
ppm/°C
mA
Internal VREF disabled
VSA > 2.7V for VREF = 2.5V
VSA > 4.3V for VREF = 4.096V
mA
1
mA
Temperature Sense Circuitry (ADC)
Internal Temperature Measurement
xx Accuracy
Register 6, bit D9 = 1
±2
°C
°C
°C
ms
xx Resolution
12-Bit + sign, twos complement data format
R1, R0 = ‘11’, 12-bit + sign resolution
±0.0625
xx Temperature Measurement Range
xx Conversion Rate
−55
+150
24
Temperature ADC
External Temperature Mode
xx Gain Range Steps
Temp PGA + Temp ADC
GPGA = 1, 2, 4, 8
1 to 8
V/V
V
GND −0.2
VSA +0.2
xx Analog Input Voltage Range
Temperature ADC Internal REF (2.048V)
xx Full-Scale Input Voltage
xx Differential Input Impedance
xx Common-Mode Input Impedance
Register 6, bit D8 = 1
(+Input) − (−Input)
±2.048/GPGA
2.8/GPGA
3.5
V
MΩ
GPGA = 1
GPGA = 2
MΩ
3.5
MΩ
GPGA = 4
1.8
MΩ
GPGA = 8
0.9
MΩ
xx Resolution
R1, R0 = ‘00’, ADC2X = ‘0’, conversion time = 8ms
R1, R0 = ‘01’, ADC2X = ‘0’, conversion time = 32ms
R1, R0 = ‘10’, ADC2X = ‘0’, conversion time = 64ms
R1, R0 = ‘11’, ADC2X = ‘0’, conversion time = 128ms
11
Bits + Sign
Bits + Sign
Bits + Sign
Bits + Sign
%
13
14
15
xx Integral Nonlinearity
xx Offset Error
0.004
1.2
GPGA = 1
GPGA = 2
GPGA = 4
GPGA = 8
GPGA = 1
GPGA = 2
GPGA = 4
GPGA = 8
mV
0.7
mV
0.5
mV
0.4
mV
xx Offset Drift
1.2
mV/°C
mV/°C
mV/°C
mV/°C
0.6
0.3
0.3
(6) When VEXC is enabled, a minimum reference selector circuit becomes the reference for the comparator threshold. This minimum
reference selector circuit uses VEXC − 100mV and VSA − 1.2V and compares the VINX pin to the lower of the two references. This
configuration ensures accurate fault monitoring in conditions where VEXC might be higher or lower than the input CMR of the PGA input
amplifier relative to VSA
.
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ELECTRICAL CHARACTERISTICS (continued)
Boldface limits apply over the specified temperature range, TA = –40°C to +125°C.
At TA = +25°C, VSA= VSD = +5V (VSA = VSUPPLY ANALOG, VSD = VSUPPLY DIGITAL; VSA must equal VSD), GNDD = GNDA = 0, and VREF
= REFIN/REFOUT = +5V, unless otherwise noted.
PGA309
PARAMETER
Temperature ADC. continued
xx Offset vs VSA
CONDITIONS
MIN
TYP
MAX
UNIT
GPGA = 1
GPGA = 2
GPGA = 4
GPGA = 8
800
400
200
150
0.05
5
mV/V
mV/V
mV/V
mV/V
%
xx Gain Error
0.50
50
xx Gain Error Drift
xx Noise
ppm/°C
LSB
ppm/V
dB
All gains
< 1
80
xx Gain vs VSA
xx Common-Mode Rejection
At dc and GPGA = 8
At dc and GPGA = 1
Register 6, bit D8 = 0
(+Input) − (−Input)
105
100
dB
Temp ADC Ext. REF (VREFT = VREF, VEXC, or VSA
xx Full-Scale Input Voltage
)
±VREFT/GPGA
V
MΩ
xx Differential Input Impedance
2.4/GPGA
8
xx Common-Mode Input Impedance
GPGA = 1
GPGA = 2
MΩ
8
MΩ
GPGA = 4
8
MΩ
GPGA = 8
8
MΩ
xx Resolution
R1, R0 = ‘00’, ADC2X = ‘0’, conversion time = 6ms
R1, R0 = ‘01’, ADC2X = ‘0’, conversion time = 24ms
R1, R0 = ‘10’, ADC2X = ‘0’, conversion time = 50ms
R1, R0 = ‘11’, ADC2X = ‘0’, conversion time = 100ms
11
Bits + Sign
Bits + Sign
Bits + Sign
Bits + Sign
%
13
14
15
xx Integral Nonlinearity
xx Offset Error
0.01
2.5
1.25
0.7
0.3
1.5
1.0
0.7
0.6
−0.2
2
GPGA = 1
GPGA = 2
GPGA = 4
GPGA = 8
GPGA = 1
GPGA = 2
GPGA = 4
GPGA = 8
mV
mV
mV
mV
xx Offset Drift
mV/°C
mV/°C
mV/°C
mV/°C
%
xx Gain Error
xx Gain Error Drift
xx Gain vs VSA
ppm/°C
ppm/V
dB
80
xx Common-Mode Rejection
At dc and GPGA = 8
At dc and GPGA = 1
Register 6, bit D11 = 1
100
85
dB
External Temperature Current Excitation ITEMP
xx Current Excitation
5.8
7
5
8
mA
nA/°C
V
xx Temperature Drift
xx Voltage Compliance
VSA −1.2
6
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Product Folder Link(s): PGA309
PGA309
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SBOS292C –DECEMBER 2003–REVISED JANUARY 2011
ELECTRICAL CHARACTERISTICS (continued)
Boldface limits apply over the specified temperature range, TA = –40°C to +125°C.
At TA = +25°C, VSA= VSD = +5V (VSA = VSUPPLY ANALOG, VSD = VSUPPLY DIGITAL; VSA must equal VSD), GNDD = GNDA = 0, and VREF
= REFIN/REFOUT = +5V, unless otherwise noted.
PGA309
PARAMETER
Linearization Adjust and Excitation Voltage (VEXC
Range 0
CONDITIONS
MIN
TYP
MAX
UNIT
)
Register 3, bit D11 = 0
With respect to VFB
xx Linearization DAC Range
xx Linearization DAC Resolution
xx VEXC Gain
−0.166 to +0.166
V/V
mV/V
V/V
±127 steps, 7-bit + sign
With respect to VREF
1.307
0.83
25
xx Gain Error Drift
ppm/°C
Range 1
Register 3, bit D11 = 1
With respect to VFB
xx Linearization DAC Range
xx Linearization DAC Resolution
xx VEXC Gain
−0.124 to +0.124
V/V
mV/V
V/V
±127 steps, 7-bit + sign
With respect to VREF
0.9764
0.52
25
xx Gain Error Drift
ppm/°C
V
VEXC Range Upper Limit
IEXC = 5mA
VSA −0.5
IEXC
Short-circuit VEXC output current
50
mA
SHORT
Digital Interface
Two-Wire Compatible
Bus speed
1
400
kHz
Bits/s
Bits
One-Wire
Serial speed baud rate
4.8K
38.4K
Maximum Lookup Table Size(7)
17 x 3 x 16
65
Two-Wire Data Rate
PGA309 to EEPROM (SCL frequency)
kHz
Logic Levels
Input Levels (SDA, SCL, PRG, TEST)
Input Levels (SDA, SCL, PRG, TEST)
Input Levels (SDA, SCL)
Pull-Up Current Source (SDA, SCL)
Pull-Down Current Source (TEST)
Output LOW Level (SDA, SCL, PRG)
Power Supply
Low
High
0.2 • VSD
V
V
0.7 • VSD
Hysteresis
0.1 • VSD
85
V
55
15
125
40
mA
mA
V
25
Open drain, ISINK = 5mA
0.4
VSA, VSD
2.7
5.5
1.6
V
ISA + ISD, Quiescent Current
Power-On Reset (POR)
Power-Up Threshold
VSA = VSD = +5V, without bridge load
1.2
mA
VS rising
2.2
2.7
V
Power-Down Threshold
Temperature Range
VS falling
1.7
V
Specified Performance Range
Operational-Degraded Performance Range
–40
–55
+125
+150
°C
°C
(7) Lookup table allows multislope compensation over temperature. Lookup table has access to 17 calibration points consisting of three
adjustment values (Tx, Temperature, ZMx, Zero DAC, GMx, Gain DAC) that are stored in 16-bit data format (17x3x16 = Lookup table
size).
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PIN CONFIGURATION
PW PACKAGE
TSSOP-16
(TOP VIEW)
VEXC
1
2
3
4
5
6
7
8
16
REFIN/REFOUT
GNDA
VSA
15 TEMPIN
14 SDA
VIN1
VIN2
VFB
13 SCL
12
PRG
11 GNDD
10 VSD
VOUT
VSJ
9
TEST
PIN DESCRIPTIONS
PIN NO.
NAME
DESCRIPTION
Bridge sensor excitation. Connect to bridge if linearization and/or internal reference for bridge excitation
is to be used.
1
VEXC
2
3
GNDA
VSA
Analog ground. Connect to analog ground return path for VSA. Should be same as GNDD.
Analog voltage supply. Connect to analog voltage supply. To be within 200mV of VSD
.
Signal input voltage 1. Connect to + or – output of sensor bridge. Internal multiplexer can change
connection internally to Front-End PGA.
4
5
VIN1
VIN2
Signal input voltage 2. Connect to + or – output of sensor bridge. Internal multiplexer can change
connection internally to Front-End PGA.
VOUT feedback pin. Voltage feedback sense point for over/under-scale limit circuitry. When internal gain
set resistors for the output amplifier are used, this is also the voltage feedback sense point for the
output amplifier. VFB in combination with VSJ allows for ease of external filter and protection circuits
without degrading the PGA309 VOUT accuracy. VFB must always be connected to either VOUT or the
point of feedback for VOUT, if external protection is used.
6
VFB
7
8
VOUT
VSJ
Analog output voltage of conditioned sensor.
Output amplifier summing junction. Use for output amplifier compensation when driving large capacitive
loads (> 100pF) and/or for using external gain setting resistors for the output amplifier.
9
TEST
VSD
Test/External controller mode pin. Pull to GNDD in normal mode.
10
11
Digital voltage supply. Connect to digital voltage supply. To be within 200mV of VSA.
GNDD
Digital ground. Connect to digital ground return path for VSD. Should be same as GNDA.
Single-wire interface program pin. UART-type interface for digital calibration of the PGA309 over a
single wire. Can be connected to VOUT for a three-lead (VS, GND, VOUT) digitally-programmable sensor
assembly.
12
13
14
PRG
SCL
SDA
Clock input/output for Two-Wire, industry-standard compatible interface for reading and writing digital
calibration and configuration from external EEPROM. Can also communicate directly to the registers in
the PGA309 through the Two-Wire, industry-standard compatible interface.
Data input/output for Two-Wire, industry-standard compatible interface for reading and writing digital
calibration and configuration from external EEPROM. Can also communicate directly to the registers in
the PGA309 through the Two-Wire, industry-standard compatible interface.
External temperature signal input. PGA309 can be configured to read a bridge current sense resistor
as an indicator of bridge temperature, or an external temperature sensing device such as diode
junction, RTD, or thermistor. This input can be internally gained by 1, 2, 4, or 8. In addition, this input
can be read differentially with respect to VGNDA, VEXC, or the internal/external VREF. There is also an
internal, register-selectable, 7mA current source (ITEMP) that can be connected to TEMPIN as an RTD,
thermistor, or diode excitation source.
15
16
TEMPIN
Reference input/output pin. As an output, the internal reference (selectable as 2.5V or 4.096V) is
REFIN/REFOUT available for system use on this pin. As an input, the internal reference may be disabled and an
external reference can then be applied as the reference for the PGA309.
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TYPICAL CHARACTERISTICS
At TA = +25°C, VSA = VSD = +5V (VSA = VSUPPLY ANALOG, VSD = VSUPPLY DIGITAL, VSA must equal VSD), GNDD = GNDA = 0, and
VREF = REFIN/REFOUT = +5V, unless otherwise noted.
VREF vs TEMPERATURE
IB CURRENT vs TEMPERATURE
4.090
4.085
4.080
4.075
4.070
4.065
4.060
1.0
0.5
0
Average, nA
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
Average
-55 -35 -15
5
25
45 65 85 105 125 145
-55 -35 -15
5
25
45 65 85 105 125 145
Temperature (°C)
Temperature (°C)
Figure 1.
Figure 2.
ITEMP CURRENT vs TEMPERATURE
COMMON-MODE REJECTION RATIO vs FREQUENCY
70
9
8
7
6
5
4
3
2
1
0
RTO of Front- End PGA
60
Average
50
40
30
20
10
0
-10
-20
-30
10
100
1k
10k
100k
1M
-55 -35 -15
5
25
45 65 85 105 125 145
Temperature (°C)
Frequency (Hz)
Figure 3.
Figure 4.
POWER-SUPPLY REJECTION RATIO vs FREQUENCY
CLOSED−LOOP GAIN vs FREQUENCY
90
80
70
60
50
40
30
80
60
40
20
0
GOUTAMP = Output Amplifier Gain
GOUTAMP = 9V/V
GFRONT = 128V/V
GOUTAMP = 9V/V
GFRONT = 32V/V
Small-Signal
VREF and VEXT Enabled
20
10
GOUTAMP = 2V/V
GFRONT = 32V/V
GOUTAMP = 2V/V
GFRONT = 8V/V
VREF = 2.5V
0
PSRR at VOUT
-10
10
100
1k
10k
100k
1M
10
100
1k
10k
100k
1M
Frequency (Hz)
Frequency (Hz)
Figure 5.
Figure 6.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VSA = VSD = +5V (VSA = VSUPPLY ANALOG, VSD = VSUPPLY DIGITAL, VSA must equal VSD), GNDD = GNDA = 0, and
VREF = REFIN/REFOUT = +5V, unless otherwise noted.
VOUT SWING TO RAIL vs ILOAD
IQ vs TEMPERATURE
VS
VS - 0.1
VS - 0.2
VS - 0.3
VS - 0.4
VS - 0.5
0.5
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
All Blocks Enabled
VS = 5V
VS = 2.7V
Ref, Exc, and ADC Disabled
0.4
VS = 5V
0.3
VS = 2.7V
0.2
0.1
0
0
5
10
15
20
25
-55 -35 -15
5
25
45 65 85 105 125 145
ILOAD (mA)
Temperature (°C)
Figure 7.
TEMPERATURE ADC ERROR (INTERNAL MODE)
Figure 8.
TEMPERATURE ADC ERROR (EXTERNAL MODES)
0.4
0.4
Reg 6 = 0503h
VREF = 2.048V Internal
Reg 6 = 0433h
VREF = 2.5V Internal
0.3
0.2
0.2
(Temp ADC Internal)
15-Bit + Sign
15-Bit + Sign
0
0.1
-0.2
-0.4
-0.6
-0.8
-1.0
-1.2
0
Reg 6 = 0430h
VREF = 2.5V Internal
11-Bit + Sign
-0.1
-0.2
-0.3
-0.4
Reg 6 = 0403h
VREF = 5V Internal
15-Bit + Sign
-100 -80 -60 -40 -20
0
20
40
60
80 100
-55 -35 -15
5
25
45 65 85 105 125 145
Input Signal (% FS of VREF
)
Actual Die Temperature (°C)
Figure 9.
Figure 10.
VREF NOISE
VOUT NOISE
(0.1Hz TO 10Hz)
(0.1Hz TO 10Hz PEAK-TO-PEAK NOISE)
VIN = +61mV
VREF = 4.096V
G = 1152
Coarse Offset = -59mV
CLK_CFG = 00 (default)
Measured After Bandpass Filter
0.1Hz Second-Order High-Pass
10Hz Fourth-Order Low-Pass
Measured After Bandpass Filter
0.1Hz Second-Order High-Pass
10Hz Fourth-Order Low-Pass
1s/div
1s/div
Figure 11.
Figure 12.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VSA = VSD = +5V (VSA = VSUPPLY ANALOG, VSD = VSUPPLY DIGITAL, VSA must equal VSD), GNDD = GNDA = 0, and
VREF = REFIN/REFOUT = +5V, unless otherwise noted.
INPUT VOLTAGE NOISE DENSITY
INPUT VOLTAGE NOISE DENSITY
1
10
Coarse Offset Adjust = -59mV
VIN = +61mV
Coarse Offset Adjust = 0mV
CLK_CFG = 00 (default)
CLK_CFG = 00 (default)
1
0.1
0.1
0.01
0.01
1
10
100
1k
10k
50k
1
10
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
Figure 13.
Figure 14.
LARGE-SIGNAL STEP RESPONSE
LARGE-SIGNAL STEP RESPONSE
Gain = 1152
Gain = 8
Time (10ms/div)
Time (10ms/div)
Figure 15.
Figure 16.
SMALL-SIGNAL STEP RESPONSE
SMALL-SIGNAL STEP RESPONSE
Gain = 8
Gain = 256
Time (10ms/div)
Time (10ms/div)
Figure 17.
Figure 18.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VSA = VSD = +5V (VSA = VSUPPLY ANALOG, VSD = VSUPPLY DIGITAL, VSA must equal VSD), GNDD = GNDA = 0, and
VREF = REFIN/REFOUT = +5V, unless otherwise noted.
CAPACITIVE LOAD DRIVE
OVERVOLTAGE RECOVERY
25
20
15
10
5
VOUT
GOUTAMP = 2V/V
VIN
GOUTAMP = 3.6V/V
GOUTAMP = 9V/V
0
Time (100ms/div)
0
500
1000
1500
2000
2500
CLOAD (pF)
Figure 19.
Figure 20.
OUTPUT AMPLIFIER
OPEN-LOOP GAIN/PHASE vs FREQUENCY
ZERO DAC TYPICAL ERROR vs CODE
120
100
80
60
40
20
0
45
20
15
CL = 100pF
RL = 4.7kW
0
Unit 2
10
-45
-90
-135
-180
-225
5
0
Unit 1
-5
-10
-15
-20
0
10000 20000 30000 40000 50000 60000 70000
Code (LSB)
0.1
1
10
100
1k
10k 100k
1M
10M
Frequency (Hz)
Figure 21.
Figure 22.
GAIN DAC TYPICAL ERROR vs CODE
20
15
10
5
0
-5
-10
-15
-20
0
10000 20000 30000 40000 50000 60000 70000
Code (LSB)
Figure 23.
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FUNCTIONAL DESCRIPTION
Converter (Temp ADC). In order to compensate for
second-order and higher drift nonlinearity, the span
drift can be fitted to piecewise linear curves during
calibration with the coefficients stored in an external
nonvolatile EEPROM lookup table.
OVERVIEW
The PGA309 is a programmable analog signal
conditioner designed for resistive bridge sensor
applications. It is a complete signal conditioner with
bridge excitation, initial span and offset adjustment,
temperature adjustment of span and offset,
internal/external temperature measurement capability,
output over-scale and under-scale limiting, fault
detection, and digital calibration. The PGA309, in a
calibrated sensor module, can reduce errors to the
level approaching the bridge sensor repeatability. See
Figure 24 for a block diagram of the PGA309.
Following is a brief overview of each major function.
Following the fine gain adjust stage is the Output
Amplifier that provides additional programmable gain.
Two key output amplifier connections, VFB and VSJ,
are brought out on the PGA309 for application
flexibility. These connections allow for an accurate
conditioned signal voltage while also providing a
means for PGA309 output overvoltage and large
capacitive loading for RFI/EMI filtering required in
many end applications.
OFFSET ADJUSTMENT
SENSOR ERROR ADJUSTMENT RANGE
The sensor offset adjustment is performed in two
stages. The input-referred Coarse Offset Adjust DAC
has approximately a ±60mV offset adjustment range
for a selected VREF of 5V. The fine offset and the
offset drift are canceled by the 16-bit Zero DAC that
sums the signal with the output of the front-end
instrumentation amplifier. Similar to the Gain DAC,
the input digital values of the Zero DAC are controlled
by the data in the Temperature Compensation
Lookup Table, stored in external EEPROM, driven by
the Temp ADC. The programming range of the Zero
DAC is 0V to VREF with an output range of 0.1V to
VSA – 0.1V.
The adjustment capability of the PGA309 is
summarized in Table 1.
Table 1. PGA309 Adjustment Capability
FSS (full-scale sensitivity)
Span TC
1mV/V to 245mV/V
Over ±3300ppmFS/°C(1)
≥ 10%
Span TC nonlinearity
Zero offset
±200%FS(2)
Zero offset TC
Over ±3000ppmFS/°C(2)
Zero offset TC nonlinearity
Sensor impedance
≥ 10%
Down to 200Ω(3)
1. Depends on the temperature sensing scheme.
2. Combined coarse and fine offset adjust.
VOLTAGE REFERENCE
The PGA309 contains a precision low-drift voltage
reference (selectable for 2.5V or 4.096V) that can be
used for external circuitry through the REFIN/REFOUT
pin. This same reference is used for the Coarse
Offset Adjust DAC, Zero DAC, Over/Under-Scale
Limits and sensor excitation/linearization through the
VEXC pin. When the internal reference is disabled, the
REFIN/REFOUT pin should be connected to an
external reference or to VSA for ratiometric-scaled
systems.
3. Lower impedance possible by using a dropping
resistor in series with the bridge.
GAIN SCALING
The core of the PGA309 is the precision low-drift and
no 1/f noise Front-End PGA. The overall gain of the
Front-End PGA + Output Amplifier can be adjusted
from 2.7V/V to 1152V/V. The polarity of the inputs
can be switched through the 2x2 input mux to
accommodate sensors with unknown polarity output.
SENSOR EXCITATION AND LINEARIZATION
The Front-End PGA provides initial coarse signal gain
using a no 1/f noise, auto-zero instrumentation
amplifier. The fine gain adjust is accomplished by the
16-bit attenuating Gain Digital-to-Analog Converter
(Gain DAC). This Gain DAC is controlled by the data
in the Temperature Compensation Lookup Table
driven by the Temperature Analog-to-Digital
A dedicated circuit with a 7-bit + sign DAC for sensor
voltage excitation and linearization is provided on the
PGA309. This block scales the reference voltage and
sums it with a portion of the PGA309 output to
compensate the positive or negative bow-shaped
nonlinearity exhibited by many sensors over their
applied pressure range. Sensors not requiring
linearization can be connected directly to the supply
(VSA) or to the VEXC pin with the Linearization DAC
(Lin DAC) set to zero.
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+5V
VSD
VSA
REFIN/REFOUT
PGA309
VREF
Power-On
Reset
KREF
Band-Gap
Voltage
Reference
+5V
VEXC
S
KLIN
VFB
Linearization
DAC
SDA
SCL
Two-Wire
EEPROM
(SOT23-5)
Interface and Control
Circuitry
VOUT
Internal
Temp Sense
VTEMP
Temperature
ADC
TEMPIN
Temp ADC
Signals Mux
Temperature ADC
Input Select
SpanTC and OffsetTC Adjust Lookup
Table with interpolation
Coarse
Offset Adjust
PRG
Fine Offset
Adjust
Zero
DAC
VOS
VOUT
Over-/Under-
Scale Limits
VIN1
Front-End
PGA Out
Front-End PGA
(Gain 4 to 128)
Fault Out
VOUT FILT
VIN2
Bridge
Sensor
RISO
Fine Gain
Adjust
Gain
DAC
VOUT
100W
Output
Amp
CL
10nF
RTEMP
Fault Conditions
Monitoring Circuit
Fault
Out
VFB
Int/Ext
Feedback
RFB
100W
VFB
TEST
Test Logic
Output Coarse
Gain Adjust
(2 to 9)
CF
150pF
VSJ
GNDA
GNDD
Figure 24. Simplified Diagram of the PGA309 in a Typical Configuration
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ADC FOR TEMPERATURE SENSING
algorithm for accurate DAC adjustments between
stored temperature indexes. This approach allows for
a piecewise linear temperature compensation of up to
17 temperature indexes and associated temperature
coefficients.
The temperature sense circuitry drives the
compensation for the sensor span and offset drift.
Either internal or external temperature sensing is
possible. The temperature can be sensed in one of
the following ways:
If either Checksum1, Checksum2, or both are
incorrect, the output of the PGA309 is set to
high-impedance.
•
Bridge impedance change (excitation current
sense, in the positive or negative part of the
bridge), for sensors with large temperature
coefficient of resistance (TCR > 0.1%/°C).
FAULT MONITOR
•
•
On-chip PGA309 temperature, when the chip is
located sufficiently close to the sensor.
External diode, thermistor, or RTD placed on the
sensor membrane. An internal 7mA current source
may be enabled to excite these types of
temperature sensors.
To detect sensor burnout or a short, a set of four
comparators are connected to the inputs of the
Front-End PGA. If any of the inputs are taken to
within 100mV of ground or VEXC, or violate the input
CMR of the Front-End PGA, then the corresponding
comparator sets a sensor fault flag that causes the
PGA309 VOUT to be driven within 100mV of either VSA
or ground, depending upon the alarm configuration
setting (Register 5—PGA Configuration and
Over/Under-Scale Limit). This will be well above the
set Over-Scale Limit level or well below the set
Under-Scale Limit level. The state of the fault
condition can be read in digital form in Register
8—Alarm Status Register. If the Over/Under-Scale
Limit is disabled, the PGA309 output voltage will still
be driven within 100mV of either VSA or ground,
depending upon the alarm configuration setting.
The temperature signal is digitized by the onboard
Temp ADC. The output of the Temp ADC is used by
the control digital circuit to read the data from the
Lookup Table in an external EEPROM, and set the
output of the Gain DAC and the Zero DAC to the
calibrated values as temperature changes.
An additional function provided through the Temp
ADC is the ability to read the VOUT pin back through
the Temp ADC input mux. This provides flexibility for
a digital output through either One-Wire or Two-Wire
interface, as well as the possibility for an external
microcontroller
calibration of the PGA309.
There are five other fault detect comparators that
help detect subtle PGA309 front-end violations that
could otherwise result in linear voltages at VOUT that
would be interpreted as valid states. These are
especially useful during factory calibration and setup,
and are configured through Register 5—PGA
Configuration and Over/Under-Scale Limit. The
respective status of each can also be read back
through Register 8—Alarm Status Register.
to
perform
real-time
custom
EXTERNAL EEPROM AND TEMPERATURE
COEFFICIENTS
The PGA309 uses an industry-standard Two-Wire
external EEPROM (typically, a SOT23-5 package). A
1k-bit (minimum) EEPROM is needed when using all
17 temperature coefficients. Larger EEPROMs may
be used to provide space for a serial number, lot
code, or other data.
OVER-SCALE AND UNDER-SCALE LIMITSE
The over-scale and under-scale limit circuitry
combined with the fault monitor circuitry provides a
The first part of the external EEPROM contains the
configuration data for the PGA309, with settings for:
means
for
system
diagnostics.
A
typical
sensor-conditioned output may be scaled for 10% to
90% of the system ADC range for the sensor normal
operating range. If the conditioned pressure sensor is
below 4%, it is considered under-pressure; if over
96%, it is considered over-pressure.
•
•
Register 3—Reference Control and Linearization
Register 4—PGA Coarse Offset and Gain/Output
Amplifier Gain
•
•
Register
Over/Under-Scale Limit
Register 6—Temp ADC Control
5—PGA
Configuration
and
The PGA309 over/under-scale limit circuit can be
programmed individually for under-scale and
over-scale values that clip or limit the PGA309 output.
From a system diagnostic view, 10% to 90% of ADC
range is normal operation, less than 4% is
under-pressure, and greater than 96% is
over-pressure. If the fault detect circuitry is used, a
detected fault will cause the PGA309 output to be
driven to positive or negative saturation.
This section of the EEPROM contains its own
individual checksum (Checksum1).
The second part of the external EEPROM contains
up to 17 temperature index values and corresponding
temperature coefficients for the Zero DAC and Gain
DAC adjustments with measured temperature, and
also contains its own checksum (Checksum2). The
PGA309 lookup logic contains a linear interpolation
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If this fault flag is programmed for high, then greater
than 97% ADC range will be a fault; if programmed
for low. then less than 3% ADC range will be a fault.
In this configuration, the system software can be
used to distinguish between over- or under-pressure
condition, which indicates an out-of-control process,
or a sensor fault.
DIGITAL INTERFACE
There are two digital interfaces on the PGA309. The
PRG pin uses One-Wire, UART-compatible
a
interface with bit rates from 4.8Kbits/s to 38.4Kbits/s.
The SDA and SCL pins together form an industry
standard Two-Wire interface at clock rates from 1kHz
to 400kHz. The external EEPROM uses the Two-Wire
interface. Communication to the PGA309 internal
registers, as well as to the external EEPROM, for
programming and readback can be conducted
through either digital interface.
POWER-UP AND NORMAL OPERATION
The PGA309 has circuitry to detect when the power
supply is applied to the PGA309, and reset the
internal registers and circuitry to an initial state. This
reset also occurs when the supply is detected to be
invalid, so that the PGA309 is in a known state when
the supply becomes valid again. The rising threshold
for this circuit is typically 2.2V and the falling
threshold is typically 1.7V. After the power supply
becomes valid, the PGA309 waits for approximately
25ms and then attempts to read the configuration
data from the external EEPROM device.
It is also possible to connect the One-Wire
communication pin, PRG, to the VOUT pin in true
three-wire sensor modules and still allow for
programming. In this mode, the PGA309 output
amplifier may be enabled for a set time period and
then disabled again to allow sharing of the PRG pin
with the VOUT connection. This allows for both digital
calibration and analog readback during sensor
calibration in a three-wire sensor module.
If the EEPROM has the proper flag set in address
locations 0 and 1, then the PGA309 continues
reading the first part of the EEPROM; otherwise, the
PGA309 waits for one second before trying again. If
the PGA309 detects no response from the EEPROM,
the PGA309 waits for one second and tries again;
otherwise, the PGA309 tries to free the bus and waits
for 25ms before trying to read the EEPROM again. If
a successful read of the first part of the EEPROM is
accomplished, (including valid Checksum1 data), the
PGA309 triggers the Temp ADC to measure
temperature. For 16-bit resolution results, the
converter takes approximately 125ms to complete a
conversion. Once the conversion is complete, the
PGA309 begins reading the Lookup Table information
from the EEPROM (second part) to calculate the
settings for the Gain DAC and Zero DAC.
The Two-Wire interface has timeout mechanisms to
prevent bus lockup from occurring. The Two-Wire
master controller in the PGA309 has a mode that
attempts to free up a stuck-at-zero SDA line by
issuing SCL pulses, even when the bus is not
indicated as idle after a timeout period has expired.
The timeout will only apply when the master portion
of the PGA309 is attempting to initiate a Two-Wire
communication.
PGA309 TRANSFER FUNCTION
Equation 1 shows the mathematical expression that is
used to compute the output voltage, VOUT. This
equation can also be rearranged algebraically to
solve for different terms. For example, during
calibration, this equation is rearranged to solve for
VIN.
The PGA309 reads the entire Lookup Table so that it
can determine if the checksum for the Lookup Table
(Checksum2) is correct. Each entry in the Lookup
Table requires approximately 500ms to read from the
EEPROM. Once the checksum is determined to be
valid, the calculated values for the Gain and Zero
DACs are updated into their respective registers, and
the output amplifier is enabled. The PGA309 then
begins looping through this entire procedure, starting
with reading the EEPROM configuration registers
from the first part of the EEPROM, then starting a
new conversion on the Temp ADC, which then
triggers reading the Lookup Table data from the
second part of the EEPROM. This loop continues
indefinitely.
VOUT = [ mux_sign ? VIN + VCoarse_Offset ? GI + VZero_DAC ] ? GD ? GO
(
(1)
Where:
mux_sign: This term changes the polarity of the
input signal; value is ±1.
VIN: The input signal for the PGA309; VIN1 = VINP
VIN2 = VINN
,
.
VCoarse_Offset: The coarse offset DAC output
voltage.
GI: Input stage gain.
VZero_DAC: Zero DAC output voltage.
GD: Gain DAC.
GO: Output stage gain.
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REFIN/REFOUT
16
VSA
VSD
10
3
Linearization and VEXC
Gain Adjust
VSA
VSD
PGA309
VFB
x0.166
x0.124
POR
VEXC Enable
7-Bit + Sign
Lin DAC
x0.83
x0.52
VEXC
VREF Internal Set
(2.5V or 4.096V)
VEXC
1
S
VREF
Bandgap
Reference
VSA
ITEMP
VREF
VEXC
7mA
Temp ADC
Internal REF
Temp ADC
Ref Mux
Internal
Temp Sense
ITEMP Enable
VSA VREF Internal Set
(2.5V or 4.096V)
RSET
TEMPIN
15
TEMPIN
VREFT
Temp ADC
REF Select
VREF
VEXC
VOUT
15-Bit + Sign
Temp ADC
Temp ADC
Input Mux
Digital Controls
xG
SDA
14
Control Registers
Alarm Register
Interface and
Control Circuitry
SCL
13
Temp Select
Source
Temp ADC, PGA
(x1, x2, x4, x8)
Temp ADC Input
Mux Select
Offset TC Adjust and Scan TC Adjust
Look-Up Logic with Interpolation Algorithm
Coarse
Offset Adjust
PGA Gain Select (1 of 8)
Range of 4 to 128
Fine
Offset Adjust
Fine Gain Adjust
(16-Bit)
(with PGA Diff Amp Gain = 4)
Input Mux
Control
16-Bit
Zero
DAC
4-Bit +
Sign DAC
VREF
VREF
PRG
12
4R
VINP
VIN2
5
A2
R
Auto
Zero
Over-Scale
Limit
Front-End
PGA Output
RF
PGA
Diff Amp
3-Bit
DAC
VREF
16-Bit
A3
RG
Auto
Zero
RF
VFB VOUT
Front-End PGA
R
Gain
DAC
Output
Amplifier
VOUT
A1
R
Scale
Limiter
Auto
Zero
VINN
7
VIN1
4
Input Mux
INT/EXT FB Select
Alarm Register Inputs
RFO
VFB
Fault Monitor
Circuit
6
Output Gain Select (1 of 7)
Range of 2 to 9
3-Bit
DAC
VREF
RGO
TEST
9
Test Logic
Under-Scale
Limit
VSJ
8
2
11
GNDD
GNDA
Figure 25. Detailed Block Diagram
Copyright © 2003–2011, Texas Instruments Incorporated
Submit Documentation Feedback
17
Product Folder Link(s): PGA309
PGA309
SBOS292C –DECEMBER 2003–REVISED JANUARY 2011
www.ti.com
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (January, 2005) to Revision C
Page
•
•
•
Updated document format to current standards ................................................................................................................... 1
Deleted lead temperature specification from Absolute Maximum Ratings table .................................................................. 2
Added PGA Transfer Function section ............................................................................................................................... 16
18
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Copyright © 2003–2011, Texas Instruments Incorporated
Product Folder Link(s): PGA309
PACKAGE OPTION ADDENDUM
www.ti.com
7-Aug-2010
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
PGA309AIPWR
PGA309AIPWRG4
PGA309AIPWT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
16
16
16
16
2500
2500
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
PGA309AIPWTG4
250
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
PGA309AIPWR
PGA309AIPWT
TSSOP
TSSOP
PW
PW
16
16
2500
250
330.0
180.0
12.4
12.4
6.9
6.9
5.6
5.6
1.6
1.6
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
PGA309AIPWR
PGA309AIPWT
TSSOP
TSSOP
PW
PW
16
16
2500
250
367.0
210.0
367.0
185.0
35.0
35.0
Pack Materials-Page 2
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