PGA4311UAG4 [TI]
4 通道、+/-5V 音频音量控制 | DW | 28;型号: | PGA4311UAG4 |
厂家: | TEXAS INSTRUMENTS |
描述: | 4 通道、+/-5V 音频音量控制 | DW | 28 光电二极管 商用集成电路 |
文件: | 总20页 (文件大小:1194K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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SBOS230A − MARCH 2002 − REVISED JUNE 2002
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FEATURES
APPLICATIONS
D
DIGITALLY-CONTROLLED ANALOG VOLUME
CONTROL:
Four Independent Audio Channels
Serial Control Interface
Zero Crossing Detection
Mute Function
D
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AUDIO AMPLIFIERS
MIXING CONSOLES
MULTI−TRACK RECORDERS
BROADCAST STUDIO EQUIPMENT
MUSICAL INSTRUMENTS
EFFECTS PROCESSORS
A/V RECEIVERS
D
D
WIDE GAIN AND ATTENUATION RANGE:
+31.5dB to −95.5dB with 0.5dB Steps
CAR AUDIO SYSTEMS
LOW NOISE AND DISTORTION:
120dB Dynamic Range
0.0004% THD+N at 1kHz (U−Grade)
0.0002% THD+N at 1kHz (A−Grade)
DESCRIPTION
The PGA4311 is a high−performance, 4-channel audio
volume control designed for professional and high-end
consumer audio systems. Using high performance
operational amplifier stages internal to the PGA4311
yields low noise and distortion, while providing the
capability to drive 600Ω loads directly without buffering.
The 3-wire serial control interface allows for connection
to a wide variety of host controllers, in addition to
support for daisy-chaining of multiple PGA4311
devices.
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NOISE-FREE LEVEL TRANSITIONS
LOW INTERCHANNEL CROSSTALK:
−130dBFS
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POWER SUPPLIES: 5V Analog, +5V Digital
AVAILABLE IN AN SOP-28 PACKAGE
D
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
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ꢞ ꢌꢅ ꢜꢌꢐ ꢎ ꢏꢌ ꢝ ꢟꢆ ꢞ ꢋ ꢜꢋ ꢞ ꢄ ꢏꢋ ꢌꢅꢝ ꢟꢆ ꢐ ꢏꢃꢆ ꢏꢆ ꢐ ꢎꢝ ꢌꢜ ꢙꢆꢢ ꢄ ꢝ ꢚꢅꢝ ꢏꢐ ꢉꢎ ꢆꢅꢏ ꢝ ꢝꢏ ꢄꢅꢊ ꢄꢐ ꢊ ꢣ ꢄꢐ ꢐ ꢄ ꢅꢏꢤꢡ
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Copyright 2002, Texas Instruments Incorporated
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www.ti.com
SBOS230A − MARCH 2002 − REVISED JUNE 2002
(1)
ABSOLUTE MAXIMUM RATINGS
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to ob-
serve proper handling and installation procedures can
cause damage.
Supply Voltage, V + . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.5V
V − . . . . . . . A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −5.5V
A
V
+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.5V
D
V + to V + . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . < 0.3V
A
D
Analog Input Voltage . . . . . . . . . . . . . . . . . . . . . . 0V to V +, V −
A
A
Digital Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . −0.3V to V
+
D
Operating Temperature Range . . . . . . . . . . . . . . . . −40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . . . . −65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . +300°C
Package Temperature (IR reflow, 10s) . . . . . . . . . . . . . . . . . +235°C
ESD damage can range from subtle performance
degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage
because very small parametric changes could cause
the device not to meet its published specifications.
(1)
Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability.
PACKAGE/ORDERING INFORMATION
OPERATING
TEMPERATURE
RANGE
PACKAGE
DESIGNATOR
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
PACKAGE−LEAD
(1)
PGA4311U
PGA4311U
PGA4311UA
PGA4311UA
PGA4311U
PGA4311U/1K
PGA4311UA
Rails
PGA4311 (U−Grade)
PGA4311 (A−Grade)
SOP−28
SOP−28
DW
DW
−40°C to +85°C
−40°C to +85°C
Tape and Reel, 1000
Rails
PGA4311UA/1K
Tape and Reel, 1000
(1)
For the most current specifications and package information, refer to our web site at www. ti.com.
ELECTRICAL CHARACTERISTICS
At T = +25°C, V + = +5V, V − = −5V, V + = +5V, R = 100kΩ, C = 20pF, BW measure = 10Hz to 20kHz, unless otherwise noted.
A
A
A
D
L
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PGA4311U (U−Grade)
PGA4311UA (A−Grade)
PARAMETER
CONDITIONS
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
DC CHARACTERISTICS
Step Size
0.5
0.05
0.05
10
0.5
0.05
0.05
10
dB
dB
dB
kΩ
pF
Gain Error
Gain Setting = 31.5dB
Gain Matching
Input Resistance
Input Capacitance
AC CHARACTERISTICS
THD+N
3
3
V
= 2Vrms, f = 1kHz
0.0004
120
0.001
0.0002
120
0.0004
%
IN
Dynamic Range
V
= AGND, Gain = 0dB
116
116
dB
IN
(V −) +
A
(V +) −
A
(V −) +
A
(V +) −
A
Voltage Range, Output
V
1.25
1.25
1.25
1.25
Voltage Range, Input (without clipping)
Output Noise
2.5
2.5
2.5
2.5
Vrms
µVrms
dBFS
V
V
= AGND, Gain = 0dB
f = 1kHz
4
4
IN
Interchannel Crosstalk
OUTPUT BUFFER
−130
−130
Offset Voltage
= AGND, Gain = 0dB
0.25
100
50
0.5
0.25
100
50
0.5
mV
pF
IN
Load Capacitance Stability
Short−Circuit Current
mA
MHz
Unity−Gain Bandwidth, Small Signal
10
10
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SBOS230A − MARCH 2002 − REVISED JUNE 2002
ELECTRICAL CHARACTERISTICS (Cont.)
At T = +25°C, V + = +5V, V − = −5V, V + = +5V, R = 100kΩ, C = 20pF, BW measure = 10Hz to 20kHz, unless otherwise noted.
A
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PGA4311U (U−Grade)
PGA4311UA (A−Grade)
PARAMETER
CONDITIONS
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
DIGITAL CHARACTERISTICS
High−Level Input Voltage, V
+2.0
−0.3
V
+
+2.0
−0.3
V +
D
0.8
V
V
IH
D
Low−Level Input Voltage, V
IL
0.8
(V +) −
A
(V +) −
D
High−Level Output Voltage, V
I
= 200µA
V
OH
OL
O
1.0
1.0
Low−Level Output Voltage, V
Input Leakage Current
I
= −3.2mA
0.4
10
0.4
10
V
O
1
1
µA
SWITCHING CHARACTERISTICS
Serial Clock (SCLK) Frequency
Serial Clock (SCLK) Pulse Width LOW
Serial Clock (SCLK) Pulse Width HIGH
MUTE Pulse Width LOW
Input Timing
f
0
6.25
0
6.25
MHz
ns
SCLK
t
80
80
2.0
80
80
2.0
PH
t
ns
PL
t
ms
MI
SDI Setup Time
t
20
20
90
35
20
20
90
35
ns
ns
ns
ns
SDS
SDI Hold Time
t
SDH
CS Falling to SCLK Rising
SCLK Falling to CS Rising
Output Timing
t
CSCR
t
CFCS
CS LOW to SDO Active
SCLK Falling to SDO Data Valid
CS HIGH to SDO High Impedance
POWER SUPPLY
t
35
60
35
60
ns
ns
ns
CSO
t
CFDO
t
100
100
CSZ
Operating Voltage
V +
+4.75
−4.75
+4.75
+5
−5
+5
+5.25
−5.25
+5.25
+4.75
−4.75
+4.75
+5
−5
+5
+5.25
−5.25
+5.25
V
V
V
A
V −
A
V
+
D
Quiescent Current
I +
V + = +5V
17
19
22
24
17
19
22
24
mA
mA
mA
dB
A
A
I −
V − = −5V
A
A
I
+
V
+ = +5V
0.5
100
1.0
0.5
100
1.0
D
D
Power−Supply Rejection Ratio PSRR (250Hz)
TEMPERATURE RANGE
Operating Range
−40
−65
+85
−40
−65
+85
°C
°C
Storage Range
+150
+150
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SBOS230A − MARCH 2002 − REVISED JUNE 2002
PIN CONFIGURATION
PIN ASSIGNMENTS
PIN
NAME
MUTE
FUNCTION
Top View
SO
1
Mute Control Input (Active LOW)
Analog Ground, Channel 1
Analog Input, Channel 1
Analog Ground, Channel 1
Analog Output, Channel 1
Analog Power Supply, −5V
Analog Power Supply, +5V
Analog Output, Channel 3
Analog Ground, Channel 3
Analog Input, Channel 3
Analog Ground, Channel 3
Digital Power Supply, +5V
Serial Data Input
2
AGND_1
3
A
_1
IN
4
AGND_1
5
A _1
OUT
6
V −
A
7
V +
A
8
A _3
OUT
9
AGND_3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
A _3
IN
AGND_3
V
+
D
SDI
CS
Chip Select Input
SCLK
SDO
Serial Clock Input
Serial Data Output
DGND
AGND_4
Digital Ground
Analog Ground, Channel 4
Analog Input, Channel 4
Analog Ground, Channel 4
Analog Output, Channel 4
Analog Power Supply, +5V
Analog Power Supply, −5V
Analog Output, Channel 2
Analog Ground, Channel 2
Analog Input, Channel 2
Analog Ground, Channel 2
A
_4
IN
AGND_4
A _4
OUT
V +
A
V −
A
A _2
OUT
AGND_2
_2
A
IN
AGND_2
ZCEN
Zero Crossing Enable (Active HIGH)
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SBOS230A − MARCH 2002 − REVISED JUNE 2002
TYPICAL CHARACTERISTICS
At T = +25°C, V + = +5V, V − = −5V, V + = +5V, R = 100kΩ, C = 20pF, BW measure = 10Hz to 20kHz, unless otherwise noted.
A
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A
D
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(NOTE: All plots taken with PGA4311 A−Grade.)
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SBOS230A − MARCH 2002 − REVISED JUNE 2002
TYPICAL CHARACTERISTICS (Cont.)
At T = +25°C, V + = +5V, V − = −5V, V + = +5V, R = 100kΩ, C = 20pF, BW measure = 10Hz to 20kHz, unless otherwise noted.
A
A
A
D
L
L
(NOTE: All plots taken with PGA4311 A−Grade.)
POWER−UP STATE
GENERAL DESCRIPTION
On power up, “power-up reset” is activated for about
100ms during which the circuit is in hardware MUTE state
and all internal flip-flops are reset. At the end of this period,
the offset calibration is initiated without any external signals.
Once this has been completed, the gain byte value for all
The PGA4311 is a four-channel audio volume control.
It may be used in a wide array of professional and
consumer audio equipment. The PGA4311 is fabricated
in a sub-micron CMOS process.
The heart of the PGA4311 is a resistor network, an analog
switch array, and a high-performance op amp stage. The
switches are used to select taps in the resistor network
that, in turn, determine the gain of the amplifier stage.
Switch selections are programmed using a serial control
port. The serial port allows connection to a wide variety of
host controllers. See Figure 1 for a functional block
diagram of the PGA4311.
channels are set to 00
, or the software MUTE condi-
HEX
tion. The gain will remain at this setting until the host con-
troller programs new settings for for each channel via the
serial control port.
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SBOS230A − MARCH 2002 − REVISED JUNE 2002
Figure 1. PGA4311 Block Diagram.
If during normal operation the power supply voltage
drops below 3.2V, the circuit enters a hardware MUTE
state. A power-up sequence will be initiated if the
power-supply voltage returns to greater than 3.2V.
The input and output pins may swing within 1.25V of the
analog power supplies, V + and V −. Given V + = +5V
A
A
A
and V − = −5V, the maximum input or output voltage
A
range is 7.5Vp-p.
For optimal performance, it is best to drive the PGA4311
with a low source impedance. A source impedance of
600Ω or less is recommended. Source impedances up
to 2kΩ will cause minimal degradation of THD+N. Please
refer to the “THD+N vs Source Impedance” plot in the
Typical Characteristics section of the datasheet.
ANALOG INPUTS AND OUTPUTS
The PGA4311 includes four independent channels.
Each channel has a corresponding input and output pin.
The input and output pins are unbalanced, and refer-
enced to analog ground.
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SBOS230A − MARCH 2002 − REVISED JUNE 2002
Data is formatted as MSB first, straight binary code.
SCLK is the serial clock input. Data is clocked into SDI
on the rising edge of SCLK.
SERIAL CONTROL PORT
The serial control port is utilized to program the gain set-
tings for the PGA4311. The serial control port includes
three input pins and one output pin. The inputs include
CS (pin 14), SDI (pin 13), and SCLK (pin 15). The sole
output pin is SDO (pin 16).
SDO is the serial data output pin, and is used when
daisy-chaining multiple PGA4311 devices. Daisy-chain
operation is described in detail later in this section. SDO
is a tri-state output, and assumes a high impedance state
when CS is HIGH. Data appears at SDO on the falling
edge of SCLK.
The CS pin functions as the chip select input. Data may
be written to the PGA4311 only when CS is LOW. SDI
is the serial data input pin. Control data is provided as
a 32-bit word at the SDI pin, 8 bits each for each chan-
nel gain setting.
The protocol for the serial control port is shown in
Figure 2. See Figure 3 for detailed timing specifi-
cations for the serial control port.
Gain Byte Format is MSB First, Straight Binary
0 is the Least Significant Bit of the Channel Gain Byte
7 is the Most Significant Bit of the Channel Gain Byte
SDI is latched on the rising edge of SCLK.
SDO transitions on the falling edge of SCLK.
Figure 2. Serial Interface Protocol.
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SBOS230A − MARCH 2002 − REVISED JUNE 2002
Figure 3. Serial Interface Timing Requirements.
For N = 1 to 255:
GAIN SETTINGS
The gain for each channel is set by its corresponding
8-bit code, [7:0] (see Figure 2). The gain code data is
straight binary format. If we let N equal the decimal
equivalent of [7:0], then the following relationships ex-
ist for the gain settings:
Gain (dB) = 31.5 − [0.5 w (255 − N)]
This results in a gain range of +31.5dB (with N = 255)
to −95.5dB (with N = 1).
Changes in gain setting may be made with or without
zero crossing detection. The operation of the zero
crossing detector and timeout circuitry is discussed lat-
er in this data sheet.
For N = 0:
Mute Condition. The input multiplexer is connected to
analog ground.
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SBOS230A − MARCH 2002 − REVISED JUNE 2002
DAISY-CHAINING MULTIPLE PGA4311 DEVICES
ZERO CROSSING DETECTION
In order to reduce the number of control signals re-
quired to support multiple PGA4311 devices on a
printed circuit board, the serial control port supports
daisy-chaining of multiple PGA4311 devices. Figure 4
shows the connection requirements for daisy-chain
operation. This arrangement allows a 3-wire serial in-
terface to control many PGA4311 devices.
The PGA4311 includes a zero crossing detection func-
tion that can provide for noise-free level transitions.
The concept is to change gain settings on a zero cross-
ing of the input signal, thus minimizing audible glitches.
This function is enabled or disabled using the ZCEN in-
put. When ZCEN is LOW, zero crossing detection is
disabled. When ZCEN is HIGH, zero crossing detec-
tion will be enabled.
As shown in Figure 4, the SDO pin from device #1 is con-
nected to the SDI input of device #2, and is repeated for
additional devices. This in turn forms a large shift regis-
ter, in which gain data may be written for all PGA4311s
connected to the serial bus. The length of the shift regis-
ter is 32 • N bits, where N is equal to the number of
PGA4311 devices included in the chain. The CS input
must remain LOW for 32 • N SCLK periods, where N is
the number of devices connected in the chain, in order
to allow enough SCLK cycles to load all devices.
The zero crossing detection takes effect with a change
in gain setting for a corresponding channel. The new
gain setting will not be implemented until either positive
slope zero crossing is detected or a time-out period of
16ms has elapsed. In the case of a time-out, the new
gain setting takes effect with no attempt to minimize
audible artifacts.
Figure 4. Daisy-Chaining Multiple PGA4311 Devices.
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SBOS230A − MARCH 2002 − REVISED JUNE 2002
MUTE FUNCTION
APPLICATIONS INFORMATION
This section includes additional information that is per-
tinent to designing the PGA4311 into an end applica-
tion.
Muting can be achieved by either hardware or software
control. Hardware muting is accomplished via the
MUTE input, and software muting by loading all zeroes
into the volume control register.
RECOMMENDED CONNECTION DIAGRAM
Figure 5 depicts the recommended connections for the
PGA4311. Power-supply bypass capacitors should be
placed as close to the PGA4311 package as physically
possible.
MUTE disconnects the internal buffer amplifiers from
the output pins and terminates the outputs with 10kΩ
resistors to ground. The mute is activated with a zero
crossing detection (independent of the zero cross en-
able status) or an 16ms time-out to eliminate any audi-
ble “clicks” or “pops”. MUTE also initiates an internal
offset calibration.
A software mute is implemented by loading all zeroes
into the volume control register. The internal amplifier
is set to unity gain with the amplifier input connected to
AGND.
PRINTED CIRCUIT BOARD (PCB) LAYOUT GUIDE-
LINES
It is recommended that the ground planes for the digital
and analog sections of the PCB be separate from one
another. The planes should be connected at a single
point. See Figure 6 for the recommended PCB floor
plan for the PGA4311.
Figure 5. Recommended Connection Diagram.
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SBOS230A − MARCH 2002 − REVISED JUNE 2002
Figure 6. Typical PCB Layout Floor Plan.
12
PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PGA4311U
ACTIVE
ACTIVE
SOIC
SOIC
DW
DW
28
28
20
RoHS & Green
Call TI
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
PGA4311U
PGA4311U/1K
1000 RoHS & Green
1000 RoHS & Green
Call TI
Call TI
Call TI
Call TI
Call TI
-40 to 85
-40 to 85
PGA4311U
A
PGA4311U/1KG4
PGA4311UA
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
DW
DW
DW
DW
28
28
28
28
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
PGA4311U
A
20
20
20
RoHS & Green
RoHS & Green
RoHS & Green
PGA4311U
A
PGA4311UAG4
PGA4311UG4
PGA4311U
A
PGA4311U
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2021
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
PGA4311U/1K
SOIC
DW
28
1000
330.0
32.4
11.35 18.67
3.1
16.0
32.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC DW 28
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 55.0
PGA4311U/1K
1000
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
PGA4311U
PGA4311UA
DW
DW
DW
DW
SOIC
SOIC
SOIC
SOIC
28
28
28
28
20
20
20
20
507
507
507
507
12.83
12.83
12.83
12.83
5080
5080
5080
5080
6.6
6.6
6.6
6.6
PGA4311UAG4
PGA4311UG4
Pack Materials-Page 3
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