PLL1707 [TI]

3.3-V DUAL PLL MULTICLOCK GENERATOR;


型号：	PLL1707
厂家：	TEXAS INSTRUMENTS
描述：	3.3-V DUAL PLL MULTICLOCK GENERATOR
文件：	总25页 (文件大小：628K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ꢀ ꢁꢁꢂ ꢃꢄ ꢃ

ꢀ ꢁꢁꢂ ꢃꢄ ꢅ

SLES065 – DECEMBER 2002

ꢆ

ꢇ

ꢆ

ꢈ

ꢉ

ꢊ

ꢋ

ꢌ

ꢁ

ꢀ

ꢁ

ꢍ

ꢋ

ꢁ

ꢎ

ꢏ

ꢐ

ꢁ

ꢑ

ꢐ

ꢒ

ꢓ

ꢔ

ꢕ

ꢔ

ꢖ

ꢌ

ꢎ

ꢑ

ꢖ

FEATURES

APPLICATIONS

27-MHz Master Clock Input

HDD + DVD Recorders

DVD Recorders

HDD Recorders

DVD Players

Generated Audio System Clock (PLL1707):

– SCKO0: 768 f (f = 44.1 kHz)

– SCKO1: 768 f , 512 f (f = 48 kHz)

– SCKO2: 256 f (f = 32, 44.1, 48, 64, 88.2,

96 kHz)

– SCKO3: 384 f (f = 32, 44.1, 48, 64, 88.2,

DVD Add-On Cards for Multimedia PCs

Digital HDTV Systems

96 kHz)

Generated Audio System Clock (PLL1708):

– SCKO0: 768 f (f = 44.1 kHz)

Set-Top Boxes

– SCKO1: 768 f , 512 f , 384 f , 256 f

(f = 48 kHz)

– SCKO2: 256 f (f = 16, 22.05, 24, 32, 44.1,

DESCRIPTION

48, 64, 88.2, 96 kHz)

– SCKO3: 384 f (f = 16, 22.05, 24, 32, 44.1,

†

The PLL1707 and PLL1708 are low cost, phase-locked

loop (PLL) multiclock generators. The PLL1707 and

PLL1708 can generate four system clocks from a 27-MHz

reference input frequency. The clock outputs of the

PLL1707 can be controlled by sampling frequency-control

pins and those of the PLL1708 can be controlled through

serial-mode control pins. The device gives customers both

cost and space savings by eliminating external

components and enables customers to achieve the very

low-jitter performance needed for high performance audio

DACs and/or ADCs. The PLL1707 and PLL1708 are ideal

for MPEG-2 applications which use a 27-MHz master

clock such as DVD recorders, HDD recorders, DVD

add-on cards for multimedia PCs, digital HDTV systems,

and set-top boxes.

48, 64, 88.2, 96 kHz)

Zero PPM Error Output Clocks

Low Clock Jitter: 50 ps (Typical)

Multiple Sampling Frequencies (PLL1707):

– f = 32, 44.1, 48, 64, 88.2, 96 kHz

Multiple Sampling Frequencies (PLL1708):

– f = 16, 22.05, 24, 32, 44.1, 48, 64, 88.2,

96 kHz

3.3-V Single Power Supply

PLL1707: Parallel Control

PLL1708: Serial Control

Package: 20-Pin SSOP (150 mil), Lead-Free

Product

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate

precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to

damage because very small parametric changes could cause the device not to meet its published specifications.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

†

The PLL1707 and PLL1708 use the same die and they are electrically identical except for mode control.

ꢀꢖ ꢑ ꢊꢋ ꢐ ꢎꢏ ꢑꢕ ꢊ ꢌꢎꢌ ꢗꢘ ꢙꢚ ꢛ ꢜꢝ ꢞꢗꢚꢘ ꢗꢟ ꢠꢡ ꢛ ꢛ ꢢꢘꢞ ꢝꢟ ꢚꢙ ꢣꢡꢤ ꢥꢗꢠ ꢝꢞꢗ ꢚꢘ ꢦꢝ ꢞꢢꢇ ꢀꢛ ꢚꢦꢡ ꢠꢞꢟ

ꢠ ꢚꢘ ꢙꢚꢛ ꢜ ꢞꢚ ꢟ ꢣꢢ ꢠ ꢗ ꢙꢗ ꢠ ꢝ ꢞꢗ ꢚꢘꢟ ꢣ ꢢꢛ ꢞꢧꢢ ꢞꢢ ꢛ ꢜꢟ ꢚꢙ ꢎꢢꢨ ꢝꢟ ꢏꢘꢟ ꢞꢛ ꢡꢜ ꢢꢘꢞ ꢟ ꢟꢞ ꢝꢘꢦ ꢝꢛ ꢦ ꢩ ꢝꢛ ꢛ ꢝ ꢘꢞꢪꢇ

ꢀꢛ ꢚ ꢦꢡꢠ ꢞ ꢗꢚ ꢘ ꢣꢛ ꢚ ꢠ ꢢ ꢟ ꢟ ꢗꢘ ꢫ ꢦꢚ ꢢ ꢟ ꢘꢚꢞ ꢘꢢ ꢠꢢ ꢟꢟ ꢝꢛ ꢗꢥ ꢪ ꢗꢘꢠ ꢥꢡꢦ ꢢ ꢞꢢ ꢟꢞꢗ ꢘꢫ ꢚꢙ ꢝꢥ ꢥ ꢣꢝ ꢛ ꢝꢜ ꢢꢞꢢ ꢛ ꢟꢇ

ꢀ ꢁ ꢁ ꢂ ꢃ ꢄꢃ

ꢃ

ꢀ

ꢁ

ꢂ

ꢄ

ꢅ

www.ti.com

SLES065 – DECEMBER 2002

FUNCTIONAL BLOCK DIAGRAM

(MS)

(MC) (MD)

FS2

FS1

CSEL

AGND

V 1–3 DGND1–3

Mode Control Interface

Power Supply

Reset

PLL2

XT1

OSC

XT2

PLL1

Divider

SCKO2

Divider

SCKO3

MCKO1 MCKO2

( ): PLL1708

SCKO0

SCKO1

PACKAGE/ORDERING INFORMATION

OPERATION

TEMPERATURE

RANGE

PACKAGE

ORDERING

NUMBER

TRANSPORT

MEDIA

PRODUCT

PACKAGE

PACKAGE CODE

MARKING

PLL1707

PLL1708

PLL1707DBQ

PLL1707DBQR

PLL1708DBQ

PLL1708DBQR

Tube

PLL1707DBQ

PLL1708DBQ

SSOP 20

20DBQ

–25°C to 85°C

Tape and reel

Tube

Tape and reel

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted

(1)

PLL1705 AND PLL1706

Supply voltage: V , V 1–V

4 V

CC DD DD

Supply voltage differences: V , V 1–V

±0.1 V

CC DD DD

Ground voltage differences: AGND, DGND1–DGND3

Digital input voltage: FS1 (MD), FS2 (MC), SR (MS), CSEL

Analog input voltage, XT1, XT2

– 0.3 V to (V

+ 0.3) V

Input current (any pins except supplies)

Ambient temperature under bias

±10 mA

–40°C to 125°C

–55°C to 150°C

150°C

Storage temperature

Junction temperature

Lead temperature (soldering)

260°C, 5 s

260°C

Package temperature (IR reflow, peak)

(1)

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

ꢀ ꢁꢁꢂ ꢃꢄ ꢃ

ꢀ ꢁꢁꢂ ꢃꢄ ꢅ

www.ti.com

SLES065 – DECEMBER 2002

ELECTRICAL CHARACTERISTICS

all specifications at T = 25°C, V 1–V 3 (= V ) = V

= 3.3 V, f = 27 MHz, crystal oscillation, f = 48 kHz (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DIGITAL INPUT/OUTPUT

Logic input

CMOS compatible

0.7V

(1)

3.6

Input logic level

Vdc

0.3 V

(1)

= V

= 0 V

100

Input logic current

Logic output

µA

±10

CMOS

(2)

= –4 mA

V – 0.4 V

Vdc

Output logic level

(2)

= 4 mA

0.4

Standard f

44.1

88.2

PLL1707

PLL1708

Double f

Half f

Standard f

22.05

44.1

Sampling frequency

kHz

Double f

88.2

MASTER CLOCK (MCKO1, MCKO2) CHARACTERISTICS (f = 27 MHz, C = C = 15 pF, C = 20 pF on measurement pin)

Master clock frequency

26.73

27.27

MHz

0.7 V

(3)

Input level

0.3 V

= V

= 0 V

±10

(3)

Input current

µA

±10

(4)

Output voltage

3.5

2.0

Vp-p

Output rise time

Output fall time

20% to 80% of V

80% to 20% of V

2.0

For crystal oscillation

For external clock

45%

51%

50%

55%

1.5

Duty cycle

(5)

Clock jitter

Power-up time

(6)

0.5

PLL AC CHARACTERISTICS (SCKO0–SCKO3) (f = 27 MHz, C = 20 pF on measurement pin)

SCKO0

SCKO1

SCKO2

SCKO3

SCKO0

SCKO1

SCKO2

SCKO3

Fixed

33.8688

Selectable for 48 kHz

24.576

8.192

36.864

24.576

36.864

PLL1707

PLL1708

256 f

384 f

12.288

18.432

33.8688

24.576

12.288

18.432

2.0

12.288

Output system clock

frequency

MHz

Fixed

Selectable for 48 kHz

12.288

4.096

6.144

36.864

24.576

36.864

256 f

384 f

Output rise time

Output fall time

Output duty cycle

20% to 80% of V

80% to 20% of V

2.0

(1)

(2)

(3)

(4)

(5)

Pins 5, 6, 7, 12: FS1/MD, FS2/MC, SR/MS, CSEL (Schmitt-trigger input with internal pulldown, 3.3-V tolerant)

Pins 2, 3, 14, 15, 18, 19: SCKO2, SCKO3, MCKO1, MCKO2, SCKO0, SCKO1

Pin 10: XT1

Pin 11: XT2

Jitter performance is specified as standard deviation of jitter for 27-MHz crystal oscillation and default SCKO frequency setting. Jitter

performancevaries with master clock mode, SCKO frequency setting and load capacitance on each clock output.

The delay time from power on to oscillation

The settling time when the sampling frequency is changed

The delay time from power on to lockup

(6)

(7)

(8)

(9)

= 27-MHz crystal oscillation, no load on MCKO1, MCKO2, SCKO0, SCKO1, SCKO2, SCKO3. Power supply current varies with sampling

frequency selection and load condition.

(10)

While all bits of CE[6:1] are 0, the PLL1708 goes into power-down mode.

ꢀ ꢁ ꢁ ꢂ ꢃ ꢄꢃ

ꢃ

ꢀ

ꢁ

ꢂ

ꢄ

ꢅ

www.ti.com

SLES065 – DECEMBER 2002

ELECTRICAL CHARACTERISTICS (continued)

all specifications at T = 25°C, V 1–V 3 (= V ) = V

= 3.3 V, f = 27 MHz, crystal oscillation, f = 48 kHz (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

100

150

300

UNIT

SCKO0, SCKO1

(5)

Output clock jitter

SCKO2, SCKO3

PLL1707, to stated output frequency

PLL1708, to stated output frequency

To stated output frequency

(7)

Frequency Settling Time

(8)

Power-up time

POWER SUPPLY REQUIREMENTS

, V Supply voltage range

2.7

3.3

3.6

Vdc

µA

CC DD

= V

= 3.3 V, f = 48 kHz

(10)

Power down

= V

(9)

Supply current

+ I

DD CC

350

550

Power dissipation

TEMPERATURE RANGE

Operating temperature

Thermal resistance

= 3.3 V, f = 48 kHz

–25

°C

PLL1707/8DBQ: 20-pin SSOP (150 mil)

150

°C/W

(1)

(2)

(3)

(4)

(5)

Pins 5, 6, 7, 12: FS1/MD, FS2/MC, SR/MS, CSEL (Schmitt-trigger input with internal pulldown, 3.3-V tolerant)

Pins 2, 3, 14, 15, 18, 19: SCKO2, SCKO3, MCKO1, MCKO2, SCKO0, SCKO1

Pin 10: XT1

Pin 11: XT2

Jitter performance is specified as standard deviation of jitter for 27-MHz crystal oscillation and default SCKO frequency setting. Jitter

performancevaries with master clock mode, SCKO frequency setting and load capacitance on each clock output.

The delay time from power on to oscillation

The settling time when the sampling frequency is changed

The delay time from power on to lockup

(6)

(7)

(8)

(9)

= 27-MHz crystal oscillation, no load on MCKO1, MCKO2, SCKO0, SCKO1, SCKO2, SCKO3. Power supply current varies with sampling

frequency selection and load condition.

(10)

While all bits of CE[6:1] are 0, the PLL1708 goes into power-down mode.

PIN ASSIGNMENTS

PLL1707

(TOP VIEW)

PLL1708

(TOP VIEW)

SCKO2

SCKO3

DGND1

FS1

SCKO1

SCKO0

DGND3

DGND2

MCKO2

MCKO1

SCKO2

SCKO3

DGND1

SCKO1

SCKO0

DGND3

DGND2

MCKO2

MCKO1

FS2

AGND

XT1

CSEL

XT2

AGND

XT1

CSEL

XT2

ꢀ ꢁꢁꢂ ꢃꢄ ꢃ

ꢀ ꢁꢁꢂ ꢃꢄ ꢅ

www.ti.com

TERMINAL

SLES065 – DECEMBER 2002

PLL1707 Terminal Functions

I/O

DESCRIPTION

NAME

NO.

AGND

CSEL

–

Analog ground

(1)

SCKO1 frequency selection control

Digital ground 1

DGND1

DGND2

DGND3

FS1

–

Digital ground 2

Digital ground 3

(1)

Sampling frequency group control 1

Sampling frequency group control 2

27-MHz master clock output 1

27-MHz master clock output 2

FS2

MCKO1

MCKO2

SCKO0

SCKO1

SCKO2

SCKO3

System clock output 0 (33.8688 MHz fixed)

System clock output 1 (selectable for 48 kHz)

System clock output 2 (256 f selectable)

System clock output 3 (384 f selectable)

(1)

Sampling rate control

–

Analog power supply, 3.3 V

Digital power supply 1, 3.3 V

Digital power supply 2, 3.3 V

Digital power supply 3, 3.3 V

XT1

XT2

27-MHz crystal oscillator, or external clock input

27-MHz crystal oscillator, must be OPEN for external clock input mode

(1)

Schmitt-trigger input with internal pulldown.

ꢀ ꢁ ꢁ ꢂ ꢃ ꢄꢃ

ꢃ

ꢀ

ꢁ

ꢂ

ꢄ

ꢅ

www.ti.com

SLES065 – DECEMBER 2002

PLL1708 Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

AGND

CSEL

NO.

–

Analog ground

(1)

SCKO1 frequency selection control

Digital ground 1

DGND1

DGND2

–

Digital ground 2

DGND3

Digital ground 3

(1)

Bit clock input for serial control

27-MHz master clock output 1

27-MHz master clock output 2

MCKO1

MCKO2

(1)

Data input for serial control

(1)

Chip select input for serial control

SCKO0

SCKO1

SCKO2

SCKO3

–

System clock output 0 (33.8688 MHz fixed)

System clock output 1 (selectable for 48 kHz)

System clock output 2 (256 f selectable)

System clock output 3 (384 f selectable)

Analog power supply, 3.3 V

Digital power supply 1, 3.3 V

Digital power supply 2, 3.3 V

Digital power supply 3, 3.3 V

XT1

XT2

27-MHz crystal oscillator, or external clock input

27-MHz crystal oscillator, must be OPEN for external clock input mode

(1)

Schmitt-trigger input with internal pulldown.

ꢀ ꢁꢁꢂ ꢃꢄ ꢃ

ꢀ ꢁꢁꢂ ꢃꢄ ꢅ

www.ti.com

SLES065 – DECEMBER 2002

TYPICAL PERFORMANCE CURVES

JITTER

LOAD CAPACITANCE

SAMPLING FREQUENCY

MCKO1

MCKO2

SCKO0

SCKO1

SCKO2

SCKO3

SCKO1

SCKO3

SCKO0

SCKO2

MCKO2

MCKO1

100

– Load Capacitance – pF

– Sampling Frequency – kHz

Figure 1

Figure 2

JITTER

FREE-AIR TEMPERATURE

SUPPLY VOLTAGE

SCKO1

SCKO3

SCKO1

SCKO0

SCKO3

MCKO2

SCKO2

MCKO2

MCKO1

SCKO2

–50

–25

100

2.7

3.0

3.3

3.6

– Free-Air Temperature – °C

– Supply Voltage – V

Figure 3

Figure 4

NOTE All specifications at T = 25°C, V 1–3 (= V ) = V

DD DD

= +3.3 V, f = 27 MHz, crystal oscillation, C , C = 15 pF, default frequency

M 1 2

(33.8688MHz for SCKO0, 36.864 MHz for SCKO1, 256 f and 384 f of 48 kHz for SCKO2 and SCKO3), C = 20 pF on measurement pin,

unless otherwise noted.

ꢀ ꢁ ꢁ ꢂ ꢃ ꢄꢃ

ꢃ

ꢀ

ꢁ

ꢂ

ꢄ

ꢅ

www.ti.com

SLES065 – DECEMBER 2002

DUTY CYCLE

SUPPLY VOLTAGE

FREE-AIR TEMPERATURE

MCKO1

MCKO2

SCKO2

SCKO1

MCKO1

SCKO2

SCKO1

SCKO3

SCKO0

2.7

3.0

3.3

3.6

–50

–25

100

– Supply Voltage – V

– Free-Air Temperature – °C

Figure 5

Figure 6

NOTE All specifications at T = 25°C, V 1–3 (= V ) = V

DD DD

= +3.3 V, f = 27 MHz, crystal oscillation, C , C = 15 pF, default frequency

M 1 2

(33.8688MHz for SCKO0, 36.864 MHz for SCKO1, 256 f and 384 f of 48 kHz for SCKO2 and SCKO3), C = 20 pF on measurement pin,

unless otherwise noted.

ꢀ ꢁꢁꢂ ꢃꢄ ꢃ

ꢀ ꢁꢁꢂ ꢃꢄ ꢅ

www.ti.com

SLES065 – DECEMBER 2002

THEORY OF OPERATION

MASTER CLOCK AND SYSTEM CLOCK OUTPUT

The PLL1707/8 consists of a dual PLL clock and master clock generator which generates four system clocks and two

buffered 27-MHz clocks from a 27-MHz master clock. Figure 7 shows the block diagram of the PLL1707/8. The PLL is

designed to accept a 27-MHz master clock.

SCKO3

384 f

Counter N

Counter M

Divider

SCKO0–3

Frequency

Control

Phase Detector

and

Loop Filter

VCO

PLL2

PLL1

Counter M

Counter N

Phase Detector

and

Loop Filter

VCO

OSC

Divider

XT1 XT2 MCKO1 MCKO2

27 MHz 27 MHz

SCKO0

33.8688 MHz

SCKO1

SCKO2

256 f

36.864/24.576 MHz

(36.864/24.576 MHz)

(18.432/12.288 MHz)

( ): PLL1708

Figure 7. Block Diagram

ꢀ ꢁ ꢁ ꢂ ꢃ ꢄꢃ

ꢃ

ꢀ

ꢁ

ꢂ

ꢄ

ꢅ

www.ti.com

SLES065 – DECEMBER 2002

The master clock can be either a crystal oscillator placed between XT1 (pin 10) and XT2 (pin 11), or an external input to

XT1. If an external master clock is used, XT2 must be open. Figure 8 illustrates possible system clock connection options,

and Figure 9 illustrates the 27-MHz master clock timing requirement.

MCKO2

MCKO1

MCKO2

MCKO1

27-MHz

Internal

Master

Clock

27-MHz

Internal

Master

Clock

XT1

XT2

External

Clock

Crystal

OSC

Circuit

Crystal

OSC

Circuit

XT2

PLL1707/PLL1708

C1, C2 = 10 pF to 33 pF

Crystal Resonator Connection

External Clock Input Connection

Figure 8. Master Clock Generator Connection Diagram

(XT1H)

0.7 V

0.3 V

XT1

(XT1L)

DESCRIPTION

SYMBOL

MIN

MAX

UNIT

Master clock pulse duration HIGH

Master clock pulse duration LOW

(XT1H)

(XT1L)

Figure 9. External Master Clock Timing Requirement

The PLL1707/8 provides a very low-jitter, high-accuracy clock. SCKO0 outputs a fixed 33.8688-MHz clock, SCKO1 outputs

256 f_S,384 f_S512 f_S,or 768 f_S(f_S= 48 kHz) which is selected by hardware or software control. The output frequency of

the remaining clocks is determined by the sampling frequency (f_S) under hardware or software control. SCKO2 and SCKO3

output 256-f_Sand 384-f_Ssystem clocks, respectively. Table 2 shows each sampling frequency which can be programmed.

The system clock output frequencies for programmed sampling frequencies are shown in Table 3. The half sampling

frequencies on SCKO2 and SCKO3 and 256 f_Sand 384 f_Son SCKO1 are supported only on the PLL1708.

Table 1. Generated System Clock SCKO1 Frequency

SCKO1 FREQUENCY

12.288 MHz

†

256 f

384 f

18.432 MHz

512 f

24.576 MHz

768 f

36.864 MHz

†

PLL1708 only

ꢀ ꢁꢁꢂ ꢃꢄ ꢃ

ꢀ ꢁꢁꢂ ꢃꢄ ꢅ

www.ti.com

SLES065 – DECEMBER 2002

Table 2. Sampling Frequencies

SAMPLING RATE

Half sampling frequencies

SAMPLING FREQUENCY (kHz)

†

22.05

44.1

88.2

Standard sampling frequencies

Double sampling frequencies

PLL1708 only

†

Table 3. Sampling Frequencies and System Clock Output Frequencies

256 f

384 f

SAMPLING FREQUENCY (kHz)

SAMPLING RATE

SCKO2 (MHZ) SCKO3 (MHZ)

†

Half

4.096

5.6448

6.144

8.4672

9.216

†

22.05

†

Half

44.1

Standard

Double

8.192

12.288

16.9344

18.432

24.576

33.8688

36.864

11.2896

12.288

16.384

22.5792

24.576

88.2

†

PLL1708 only

Response time from power on (or applying the clock to XT1) to SCKO settling time is typically 3 ms. Delay time from

sampling frequency change to SCKO settling is 300 ns maximum. Figure 10 illustrates SCKO transient timing in the

PLL1708.

300 ns

1–2 Clocks of MCKO1, 2

SCKO2

SCKO3

Stable

Clock Transition Region

Stable

SCKO0

SCKO1

33.8688 , 36.864, or 24.576 MHz

Figure 10. System Clock Transient Timing

The delay time for hardware control to use SR, FS2, FS1, or CSEL is 150 ns maximum. Figure 11 illustrates SCKO transient

timing in the PLL1707. Clock transient timing is not synchronized with the SCKOs. External buffers are recommended on

all output clocks in order to avoid degrading the jitter performance of the PLL1707/8.

ꢀ ꢁ ꢁ ꢂ ꢃ ꢄꢃ

ꢃ

ꢀ

ꢁ

ꢂ

ꢄ

ꢅ

www.ti.com

SLES065 – DECEMBER 2002

FS2, 1

CSEL

150 ns

50 ns

SCKO1

SCKO2

SCKO3

Stable

Clock Transition Region

Stable

SCKO0

33.8688 MHz

Figure 11. SCKO Transient Timing

POWER-ON RESET

The PLL1707/8 has an internal power-on reset circuit. The mode register of the PLL1708 is initialized with default settings

by power-on reset. Throughout the reset period, all clock outputs are enabled with the default settings after power-up time.

Initialization by internal power-on reset is done automatically during 1024 master clocks at V_DD> 2.0 V (TYP). Power-on

reset timing is shown in Figure 12.

2.4 V

2.0 V

1.6 V

Reset

Reset Removal

Internal Reset

Master Clock

1024 Master Clocks

Figure 12. Power-On Reset Timing

ꢀ ꢁꢁꢂ ꢃꢄ ꢃ

ꢀ ꢁꢁꢂ ꢃꢄ ꢅ

www.ti.com

SLES065 – DECEMBER 2002

FUNCTION CONTROL

The built-in functions of the PLL1707 can be controlled in the parallel mode (hardware mode), which uses SR (pin 7), FS1

(pin 5) and FS2 (pin 6). The PLL1708 can be controlled in the serial mode (software mode), which has a three-wire interface

using MS (pin 7), MC (pin 6), and MD (pin 5). The selectable functions are shown in Table 4.

Table 4. Selectable Functions

SELECTABLE FUNCTION

Sampling frequency select (32 kHz, 44.1 kHz, 48 kHz)

Sampling rate select (standard/double)

Sampling rate select (half)

PARALLEL MODE

SERIAL MODE

Yes

Each clock output enable/disable

Power down

SCKO1 configuration

PLL1707 (Parallel Mode)

In the parallel mode, the following functions can be selected:

Sampling Frequency Group Select

The sampling frequency group can be selected by FS1 (pin 5) and FS2 (pin 6).

FS2 (PIN 6)

LOW

FS1 (PIN 5)

LOW

SAMPLING FREQUENCY

48 kHz

LOW

HIGH

44.1 kHz

HIGH

LOW

32 kHz

HIGH

Reserved

Sampling Rate Select

The sampling rate can be selected by SR (pin 7)

SR (PIN 7)

LOW

SAMPLING RATE

Standard

Double

HIGH

System Clock SCKO1 Frequency Select

System clock SCKO1 frequency can be selected by CSEL (pin 12).

CSEL (PIN 12)

LOW

SCKO1 FREQUENCY

36.864 MHz

HIGH

24.576 MHz

PLL1708 (Serial Mode)

The built-in functions of the PLL1708 are shown in Table 5. These functions are controlled using the MS, MC, and MD serial

control signals.

Table 5. Selectable Functions

SELECTABLE FUNCTION

Sampling frequency select (32 kHz, 44.1 kHz, 48 kHz)

Sampling rate select (half, standard, double)

Each clock output enable/disable

Power down

DEFAULT

48-kHz group

Standard

Enabled

Disabled

SCKO1 configuration

36.864 MHz, 24.576 MHz

ꢀ ꢁ ꢁ ꢂ ꢃ ꢄꢃ

ꢃ

ꢀ

ꢁ

ꢂ

ꢄ

ꢅ

www.ti.com

SLES065 – DECEMBER 2002

Program-Register Bit Mapping

The built-in functions of the PLL1708 are controlled through a 16-bit program register. This register is loaded using MD,

MC and MS. After the 16 data bits are clocked in using the rising edge of MC, MS is used to latch the data into the register.

Table 6 shows the bit mapping of the register. The serial mode control format and control data input timing are shown in

Figure 13 and Figure 14, respectively.

D15

D14

D13

D12

D11

D10

Figure 13. Serial Mode Control Format

(MHH)

(MSL)

V /2

(MSS)

(MCL)

(MSS)

(MSH)

(MCH)

(MCY)

MSB

LSB

(MDH)

(MDS)

DESCRIPTION

SYMBOL

MIN

100

TYP

MAX

UNIT

MC pulse cycle time

(MCY)

MC pulse duration LOW

MC pulse duration HIGH

MD hold time

(MCL)

(MCH)

(MDH)

MD setup time

(MDS)

(1)

MS low-level time

MS high-level time

(2)

MS hold time

MC clocks

(MSL)

(MHH)

200

(MSH)

(3)

MS setup time

(MSS)

(1)

(2)

(3)

MC clocks: MC clock period

MC rising edge for LSB to MS rising edge

MS rising edge to the next MC rising edge. If the MC clock is stopped after the LSB, any MS rise time is accepted.

Figure 14. Control Data Input Timing

ꢀ ꢁꢁꢂ ꢃꢄ ꢃ

ꢀ ꢁꢁꢂ ꢃꢄ ꢅ

www.ti.com

SLES065 – DECEMBER 2002

Mode Register

D15

D14

D13

D12

D11

D10

CE6

CE5

CE4

CE3

CE2

CE1

SR2

SR1

FS2

FS1

Table 6. Mode Register Mapping

BIT NAME

CE6

DESCRIPTION

MCKO2 output enable/disable

MCKO1 output enable/disable

SCKO1 output enable/disable

SCKO3 output enable/disable

SCKO2 output enable/disable

SCKO0 output enable/disable

Sampling rate select

CE5

CE4

CE3

Mode control

CE2

CE1

SR[2:1]

FS[2:1]

Sampling frequency select

FS[2:1]: Sampling Frequency Group Select

FS2

FS1

SAMPLING FREQUENCY

48 kHz (default)

44.1 kHz

32 kHz

Reserved

SR[2:1]: Sampling Rate Select

SR2

SR1

SAMPLING RATE

Standard (default)

Double

Half

Reserved

CE [6:1]: Clock Output Control

CE1–CE6

CLOCK OUTPUT CONTROL

Clock output disable

Clock output enable (default)

While all the bits of CE [6:1] are 0, the PLL1708 goes into the power-down mode, all dynamic operation including PLLs

and the oscillator halts, but serial mode control is enabled for resumption.

ꢀ ꢁ ꢁ ꢂ ꢃ ꢄꢃ

ꢃ

ꢀ

ꢁ

ꢂ

ꢄ

ꢅ

www.ti.com

SLES065 – DECEMBER 2002

Configuration Register

D15

D14

D13

D12

D11

D10

RSV RSV RSV RSV RSV CFG1

RSV

Table 7. Configuration Register Mapping

BIT NAME

RSV

DESCRIPTION

Reserved, must be 0

SCKO1 configuration

Configuration

CFG1

CFG1: SCKO1 Configuration Control

CFG1

CONFIGURATION 1

36.864 MHz, 24.576 MHz for SCKO1 (default)

18.432 MHz, 12.288 MHz for SCKO1

The system clock SCKO1 frequency can be selected by CSEL (pin 12) and CFG1 (register).

CFG1

(REGISTER)

CSEL

(PIN 12)

SCKO1

LOW

HIGH

LOW

HIGH

36.864 MHz

24.576 MHz

18.432 MHz

12.288 MHz

CONNECTION DIAGRAM

Figure 15 shows the typical connection circuit for the PLL1707. There are four grounds for digital and analog power

supplies. However, the use of one common ground connection is recommended to avoid latch-up or other

power-supply-related troubles. Power supplies should be bypassed as close as possible to the device.

MPEG-2 APPLICATIONS

Typical applications for the PLL1707/8 are MPEG-2 based systems such as DVD recorders, HDD recorders, DVD players,

DVD add-on cards for multimedia PCs, digital HDTV systems, and set-top boxes. The PLL1707/8 provides audio system

clocks for a CD-DA DSP, DVD DSP, Karaoke DSP, ADC(s), and DAC(s) from a 27-MHz video clock.

ꢀ ꢁꢁꢂ ꢃꢄ ꢃ

ꢀ ꢁꢁꢂ ꢃꢄ ꢅ

www.ti.com

SLES065 – DECEMBER 2002

3.3 V

(2)

PLL1707/8

SCKO2

SCKO3

DGND1

SCKO1

SCKO0

DGND3

DGND2

MCKO2

MCKO1

(1)

(4)

FS1 (MD)

FS2 (MC)

SR(MS)

(2)

(1)

(3)

AGND

XT1

CSEL

XT2

(3)

Clock Outputs (5)

(1)

(2)

(3)

(4)

0.1-µF ceramic capacitor typical, depending on quality of power supply and pattern layout

10-µF aluminum electrolytic capacitor typical, depending on quality of power supply and pattern layout

27-MHz quartz crystal and 10–33 pF × 2 ceramic capacitors, which generate the appropriate amplitude of oscillation on XT1/XT2

This connection is for PLL1707 (parallel mode); when PLL1708 (serial mode) is to be used, control pins must be connected to serial interfaced

controller.

For good jitter performance, minimize the load capacitance on the clock output. It is recommended to drive the clock outputs through buffers,

especially if there are heavy loads on SCKO0 and SCKO1, and to minimize mutual interference by separating them or inserting a guard pattern

between them.

(5)

Figure 15. Typical Connection Diagram

ꢀ ꢁ ꢁ ꢂ ꢃ ꢄꢃ

ꢃ

ꢀ

ꢁ

ꢂ

ꢄ

ꢅ

www.ti.com

SLES065 – DECEMBER 2002

BLOCK DIAGRAM OF DVD PLAYER APPLICATION

PLL1707/8

384 f

SCKO3

27 MHz

Crystal

256 f

SCKO2

27 MHz

MCKO1/2

SCKO0

Front

CD-DA/

DVD DSP

MPEG/AC-3

Audio Decoder

Surround

PCM/DSD1608

Center, Subwoofer

Down Mix

BLOCK DIAGRAM OF HDD+DVD RECORDER APPLICATION

MPEG

Encoder

PCM1802

SCKO1

PLL1707/8

MCKO1/2

XTI

SCKO2, 3

MPEG

Decoder

PCM1742

27-MHz Master Clock

PACKAGE OPTION ADDENDUM

www.ti.com

17-May-2014

PACKAGING INFORMATION

Orderable Device

PLL1707DBQ

Status Package Type Package Pins Package

Eco Plan

Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

-25 to 85

Device Marking

Samples

Drawing

Qty

(1)

(2)

(6)

(3)

(4/5)

ACTIVE

SSOP

DBQ

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

PLL1707

PLL1707DBQG4

PLL1707DBQR

ACTIVE

DBQ

Green (RoHS

& no Sb/Br)

-25 to 85

PLL1707

2000

Green (RoHS

& no Sb/Br)

-25 to 85

PLL1707DBQRE4

PLL1707DBQRG4

ACTIVE

SSOP

DBQ

TBD

Call TI

-25 to 85

2000

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

PLL1707

PLL1708

PLL1708DBQ

PLL1708DBQG4

PLL1708DBQR

PLL1708DBQRG4

ACTIVE

SSOP

DBQ

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

-25 to 85

Green (RoHS

& no Sb/Br)

2000

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

17-May-2014

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

⁽⁶⁾Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF PLL1707 :

Automotive: PLL1707-Q1

•

NOTE: Qualified Version Definitions:

Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

•

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

16-Aug-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

PLL1707DBQR

PLL1708DBQR

SSOP

DBQ

2000

330.0

16.4

6.5

9.0

2.1

8.0

16.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

16-Aug-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

PLL1707DBQR

PLL1708DBQR

SSOP

DBQ

2000

367.0

38.0

Pack Materials-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other

changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest

issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and

complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale

supplied at the time of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary

to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

performed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and

applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide

adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or

other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information

published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or

endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the

third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration

and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered

documentation. Information of third parties may be subject to additional restrictions.

Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service

voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.

TI is not responsible or liable for any such statements.

Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements

concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support

that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which

anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause

harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use

of any TI components in safety-critical applications.

In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to

help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and

requirements. Nonetheless, such components are subject to these terms.

No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties

have executed a special agreement specifically governing such use.

Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in

military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components

which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and

regulatory requirements in connection with such use.

TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of

non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.

Products

Applications

Audio

www.ti.com/audio

amplifier.ti.com

dataconverter.ti.com

www.dlp.com

Automotive and Transportation www.ti.com/automotive

Communications and Telecom www.ti.com/communications

Amplifiers

Data Converters

DLP® Products

DSP

Computers and Peripherals

Consumer Electronics

Energy and Lighting

Industrial

www.ti.com/computers

www.ti.com/consumer-apps

www.ti.com/energy

dsp.ti.com

Clocks and Timers

Interface

www.ti.com/clocks

interface.ti.com

logic.ti.com

www.ti.com/industrial

www.ti.com/medical

Medical

Logic

Security

www.ti.com/security

Power Mgmt

Microcontrollers

RFID

power.ti.com

Space, Avionics and Defense

Video and Imaging

www.ti.com/space-avionics-defense

www.ti.com/video

microcontroller.ti.com

www.ti-rfid.com

www.ti.com/omap

OMAP Applications Processors

Wireless Connectivity

TI E2E Community

e2e.ti.com

www.ti.com/wirelessconnectivity

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

PLL1707 [TI]

相关型号：

PLL1707-Q1

PLL1707DBQ

PLL1707DBQ

PLL1707DBQR

PLL1707DBQR

PLL1707DBQRG4

PLL1707IDBQRQ1

PLL1708

PLL1708

PLL1708DBQ

PLL1708DBQ

PLL1708DBQG4