PLPV811DBVT [TI]
Nanopower Operational Amplifiers;
| 型号： | PLPV811DBVT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Nanopower Operational Amplifiers |
| 文件： | 总31页 (文件大小：1529K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LPV811, LPV812
SNOSD33B –NOVEMBER 2016–REVISED NOVEMBER 2016
LPV811/LPV812 Precision 425 nA Nanopower Operational Amplifiers
1 Features
3 Description
The LPV811 (single) and LPV812 (dual) are a ultra-
low-power precision operational amplifier family for
“Always ON” sensing applications in battery powered
wireless and low power wired equipment. With 8 kHz
of bandwidth from 425 nA of quiescent current and a
trimmed offset voltage to under 300µV, the LPV81x
amplifiers provide the required precision while
minimizing power consumption in equipment such as
gas detectors and portable electronic devices where
operational battery-life is critical.
1
•
Nanopower Supply Current: 425 nA/channel
Offset Voltage: 300 µV (max)
TcVos: 1 µV/°C
•
•
•
•
•
•
•
•
•
•
•
Gain-Bandwidth: 8 kHz
Unity-Gain Stable
Low Input Bias Current : 100 fA
Wide Supply Range: 1.6 V to 5.5 V
Rail-to-Rail Output
In addition to being ultra-low-power, the LPV81x
amplifiers have CMOS input stages with fempto-amp
bias currents for impedance source applications. The
LPV81x amplifiers also feature a negative-rail sensing
input stage and a rail-to-rail output stage that swings
within millivolts of the rails, maintaining the widest
dynamic range possible. EMI protection is designed
into the LPV81x in order to reduce system sensitivity
to unwanted RF signals from mobile phones, WiFi,
radio transmitters, and tag readers.
No Output Reversals
EMI Protection
Temperature Range: –40°C to 125°C
Industry Standard Packages:
–
–
Single in 5-pin SOT-23
Dual in 8-pin VSSOP
2 Applications
•
•
•
•
•
•
•
CO and O2 Gas Detectors (TIDA-0756)
PIR Motion Detectors
Device Information(1)
PART
NUMBER
PACKAGE
BODY SIZE
Current Sensing
Thermostats
LPV811
SOT-23 (5)
VSSOP (8)
2.90 mm x 1.60 mm
3.00 mm × 3.00 mm
IoT Remote Sensors
LPV812
Active RFID Readers and Tags
Portable Medical Equipment
LPV8xx Family of Nanopower Amplifiers
SUPPLY
CURRENT
(Typ/Ch)
OFFSET
VOLTAGE
(Max)
PART
NUMBER
CHANNELS
LPV801
LPV802
LPV811
LPV812
1
2
1
2
500 nA
320 nA
450 nA
425 nA
3.5 mV
3.5 mV
370 µV
300 µV
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Figure 1. Nanopower CO Sensor
Figure 2. LPV812 Offset Voltage Distribution
12
1 Mꢀ
21492 Amplifiers
10
8
ë+
RL
6
ëhÜÇ
+
CO
4
Sensor
2
0
Offset Voltage (µV)
C002
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LPV811, LPV812
SNOSD33B –NOVEMBER 2016–REVISED NOVEMBER 2016
www.ti.com
Table of Contents
8.1 Application Information............................................ 15
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 6
Detailed Description ............................................ 13
7.1 Overview ................................................................. 13
7.2 Functional Block Diagram ....................................... 13
7.3 Feature Description................................................. 13
7.4 Device Functional Modes........................................ 13
Application and Implementation ........................ 15
8.2 Typical Application: Three Terminal CO Gas Sensor
Amplifier ................................................................... 15
8.3 Do's and Don'ts ...................................................... 18
9
Power Supply Recommendations...................... 18
10 Layout................................................................... 18
10.1 Layout Guidelines ................................................. 18
10.2 Layout Example .................................................... 18
11 Device and Documentation Support ................. 19
11.1 Device Support .................................................... 19
11.2 Documentation Support ....................................... 19
11.3 Related Links ........................................................ 19
11.4 Receiving Notification of Documentation Updates 19
11.5 Community Resources.......................................... 19
11.6 Trademarks........................................................... 19
11.7 Electrostatic Discharge Caution............................ 20
11.8 Glossary................................................................ 20
7
8
12 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
Changes from Revision A (October 2016) to Revision B
Page
•
•
•
•
•
•
Added family upsell table to front page ................................................................................................................................. 1
Changed Front page O2 Sens circuit to Vos Disty Graph .................................................................................................... 1
Deleted larger family upsell table .......................................................................................................................................... 2
Deleted LPV811 preview "preliminary spec" table note. ....................................................................................................... 5
Added separate LPV811 CMRR Specification. ..................................................................................................................... 5
Added offset distribution graphs ............................................................................................................................................ 6
Changes from Original (August 2016) to Revision A
Page
•
Changed Product Preview to Production Data. ..................................................................................................................... 1
2
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Copyright © 2016, Texas Instruments Incorporated
LPV811, LPV812
www.ti.com
SNOSD33B –NOVEMBER 2016–REVISED NOVEMBER 2016
5 Pin Configuration and Functions
LPV812 8-Pin VSSOP
DGK Package
Top View
LPV811 5-Pin SOT-23
DBV Package
Top View
OUT A
-IN A
+IN A
V-
1
2
3
4
8
7
6
5
V+
A
OUT
V-
1
2
3
5
4
V+
OUT B
-IN B
+IN B
B
+IN
-IN
Pin Functions: LPV811 DBV
PIN
TYPE
DESCRIPTION
NAME
OUT
-IN
NUMBER
1
4
3
2
5
O
I
Output
Inverting Input
+IN
V-
I
Non-Inverting Input
P
P
Negative (lowest) power supply
Positive (highest) power supply
V+
Pin Functions: LPV812 DGK
PIN
TYPE
DESCRIPTION
NAME
OUT A
-IN A
+IN A
V-
NUMBER
1
2
3
4
5
6
7
8
O
I
Channel A Output
Channel A Inverting Input
Channel A Non-Inverting Input
Negative (lowest) power supply
Channel B Non-Inverting Input
Channel B Inverting Input
Channel B Output
I
P
I
+IN B
-IN B
OUT B
V+
I
O
P
Positive (highest) power supply
Copyright © 2016, Texas Instruments Incorporated
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LPV811, LPV812
SNOSD33B –NOVEMBER 2016–REVISED NOVEMBER 2016
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)
(1)
MIN
–0.3
MAX
6
UNIT
V
Supply voltage, Vs = (V+) - (V-)
(2) (3)
Voltage
Common mode
Differential
(V-) - 0.3
(V-) - 0.3
-10
(V+) + 0.3
(V+) + 0.3
10
V
Input pins
V
Input pins
Current
mA
Output short
current
Continuous Continuous
(4)
Storage temperature, Tstg
Junction temperature
–65
150
150
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Not to exceed -0.3V or +6.0V on ANY pin, referred to V-
(3) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.3 V beyond the supply rails should
be current-limited to 10 mA or less.
(4) Short-circuit to Vs/2, one amplifier per package. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±1000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions. Pins listed as ±2000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions. Pins listed as ±750 V may actually have higher performance.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.6
MAX
5.5
UNIT
V
Supply voltage (V+ – V–)
Specified temperature
-40
125
°C
6.4 Thermal Information
LPV811
DBV
(SOT-23)
LPV812
DGK
(VSSOP)
THERMAL METRIC(1)
UNIT
5 PINS
8 PINS
θJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
177.4
133.9
36.3
177.6
68.8
98.2
12.3
96.7
θJCtop
θJB
Junction-to-board thermal resistance
ºC/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
23.6
ψJB
35.7
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
4
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Copyright © 2016, Texas Instruments Incorporated
LPV811, LPV812
www.ti.com
SNOSD33B –NOVEMBER 2016–REVISED NOVEMBER 2016
6.5 Electrical Characteristics
TA = 25°C, VS = 1.8 V to 5 V, VCM = VOUT = VS/2, and RL≥ 10 MΩ to VS / 2, unless otherwise noted .
PARAMETER
OFFSET VOLTAGE
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Input offset voltage,
LPV811
VS = 1.8V and 3.3V, VCM = V-
±60
±55
±370
±300
µV
µV
VOS
Input offset voltage,
LPV812
VS = 1.8V and 3.3V, VCM = V-
ΔVOS/ΔT Input offset drift
PSRR Power-supply rejection
ratio
INPUT VOLTAGE RANGE
VCM = V-
TA = –40°C to 125°C
±1
µV/°C
µV/V
VS = 1.8V to 3.3V, VCM = V-
±1.6
±60
2.4
VCM
Common-mode voltage
VS = 3.3V
0
77
80
V
range
Common-mode rejection
ratio, LPV811
(V–) ≤ VCM ≤ (V+) – 0.9 V, VS = 3.3V
(V–) ≤ VCM ≤ (V+) – 0.9 V, VS = 3.3V
95
98
dB
dB
CMRR
Common-mode rejection
ratio, LPV812
INPUT BIAS CURRENT
IB
Input bias current
Input offset current
VS = 1.8V
VS = 1.8V
±100
±100
fA
fA
IOS
INPUT IMPEDANCE
Differential
7
3
pF
pF
Common mode
NOISE
En
Input voltage noise
ƒ = 0.1 Hz to 10 Hz
ƒ = 100 Hz
6.5
340
420
µVp-p
en
Input voltage noise
density
nV/√Hz
ƒ = 1 kHz
OPEN-LOOP GAIN
AOL
Open-loop voltage gain
(V–) + 0.3 V ≤ VO ≤ (V+) – 0.3 V, RL = 100 kΩ
VS = 1.8V, RL = 100 kΩ to V+/2
120
3.5
dB
OUTPUT
VOH
Voltage output swing
from positive rail
10
mV
VOL
Voltage output swing
from negative rail
VS = 1.8V, RL = 100 kΩ to V+/2
VS = 3.3V, Short to VS/2
ƒ = 1 KHz, IO = 0 A
2.5
4.7
90
10
ISC
ZO
Short-circuit current
mA
Open loop output
impedance
kΩ
FREQUENCY RESPONSE
GBP
Gain-bandwidth product
CL = 20 pF, RL = 10 MΩ, VS = 5V
8
2
kHz
G = 1, Rising Edge, CL = 20 pF, VS = 5V
G = 1, Falling Edge, CL = 20 pF, VS = 5V
SR
Slew rate (10% to 90%)
V/ms
2.1
POWER
SUPPLY
Quiescent Current,
LPV811
VCM = V-, IO = 0, VS = 3.3V
VCM = V-, IO = 0, VS = 3.3V
450
425
540
495
IQ
nA
Quiescent Current,
Per Channel, LPV812
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SNOSD33B –NOVEMBER 2016–REVISED NOVEMBER 2016
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6.6 Typical Characteristics
at TA = 25°C, RL = 10MΩ to VS/2 ,CL = 20pF, VCM = VS / 2V unless otherwise specified.
8
6
4
2
0
8
6
4
2
0
39107 Amplifiers
39107 Amplifiers
Offset Voltage (µV)
Offset Voltage (µV)
C001
C001
VS = 1.8V
TA = 25°C
LPV811
VS = 3.3V
TA = 25°C
LPV811
VCM = V-
RL=No Load
VCM = V-
RL=No Load
Figure 3. Offset Distribution of LPV811
Figure 4. Offset Distribution of LPV811
12
10
8
12
10
8
21492 Amplifiers
21492 Amplifiers
6
6
4
4
2
2
0
0
Offset Voltage (µV)
Offset Voltage (µV)
C002
C002
VS = 1.8V
TA = 25°C
LPV812, Channel A
VCM = V-
VS = 3.3V
TA = 25°C
LPV812, Channel A
VCM = V-
RL=No Load
RL=No Load
Figure 5. Offset Distribution of LPV812, CH A
Figure 6. Offset Distribution of LPV812, CH A
12
10
8
12
10
8
21492 Amplifiers
21492 Amplifiers
6
6
4
4
2
2
0
0
Offset Voltage (µV)
Offset Voltage (µV)
C002
C002
VS =1.8V
TA = 25°C
LPV812, Channel B
VCM = V-
VS = 3.3V
TA = 25°C
LPV812, Channel B
VCM = V-
RL=No Load
RL=No Load
Figure 7. Offset Distribution of LPV812, CH B
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Figure 8. Offset Distribution of LPV812, CH B
6
Copyright © 2016, Texas Instruments Incorporated
LPV811, LPV812
www.ti.com
SNOSD33B –NOVEMBER 2016–REVISED NOVEMBER 2016
Typical Characteristics (continued)
at TA = 25°C, RL = 10MΩ to VS/2 ,CL = 20pF, VCM = VS / 2V unless otherwise specified.
1000
900
800
700
600
500
400
300
200
100
0
1000
900
800
700
600
500
400
300
200
100
0
+125°C
+25°C
+125°C
+25°C
-40°C
-40°C
1.5
2
2.5
3
3.5
4
4.5
5
5.5
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Supply Voltage (V)
Supply Voltage (V)
C001
C001
VCM = V-
LPV811
RL=No Load
VCM = V-
LPV812
RL=No Load
Figure 9. Supply Current vs. Supply Voltage, LPV811
Figure 10. Supply Current vs. Supply Voltage, LPV812
500
500
+125°C
+25°C
-40°C
+125°C
400
400
300
+25°C
300
-40°C
200
200
100
100
0
0
œ100
œ200
œ300
œ400
œ500
œ100
œ200
œ300
œ400
œ500
0
0.15
0.3
0.45
0.6
0.75
0.9
0
0.4
0.8
1.2
1.6
2
2.4
Common Mode Voltage (V)
Common Mode Voltage (V)
C003
C003
VS= 1.8V
RL= 10MΩ
VS= 3.3V
RL= 10MΩ
Figure 11. Typical Offset Voltage vs. Common Mode Voltage
Figure 12. Typical Offset Voltage vs. Common Mode Voltage
500
1k
+125°C
400
+25°C
300
100
10
-40°C
200
100
0
1
œ100
œ200
œ300
œ400
œ500
100m
10m
1m
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
0
25
50
75
100
125
œ50
œ25
Common Mode Voltage (V)
Temperature (°C)
C003
C001
VS= 5V
RL= 10MΩ
VS= 5V
TA = -40 to 125
VCM = Vs/2
Figure 13. Typical Offset Voltage vs. Common Mode Voltage
Figure 14. Input Bias Current vs. Temperature
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SNOSD33B –NOVEMBER 2016–REVISED NOVEMBER 2016
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Typical Characteristics (continued)
at TA = 25°C, RL = 10MΩ to VS/2 ,CL = 20pF, VCM = VS / 2V unless otherwise specified.
100
100
80
80
60
60
40
40
20
20
0
0
œ20
œ40
œ60
œ80
œ100
œ20
œ40
œ60
œ80
œ100
0.0
0.2
0.3
0.5
0.6
0.8
0.9
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
Common Mode Voltage (V)
Common Mode Voltage (V)
C001
C002
VS= 1.8V
TA = -40°C
VS= 5V
TA = -40°C
Figure 15. Input Bias Current vs. Common Mode Voltage
Figure 16. Input Bias Current vs. Common Mode Voltage
1000
800
1000
800
600
600
400
400
200
200
0
0
œ200
œ400
œ600
œ800
œ1000
œ200
œ400
œ600
œ800
œ1000
0.0
0.2
0.3
0.5
0.6
0.8
0.9
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
Common Mode Voltage (V)
Common Mode Voltage (V)
C004
C005
VS= 1.8V
TA = 25°C
VS= 5V
TA = 25°C
Figure 17. Input Bias Current vs. Common Mode Voltage
Figure 18. Input Bias Current vs. Common Mode Voltage
500
400
500
400
300
300
200
200
100
100
0
0
œ100
œ200
œ300
œ400
œ500
œ100
œ200
œ300
œ400
œ500
0.0
0.2
0.3
0.5
0.6
0.8
0.9
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
Common Mode Voltage (V)
Common Mode Voltage (V)
C003
C006
VS= 1.8V
TA = 125°C
VS= 5V
TA = 125°C
Figure 19. Input Bias Current vs. Common Mode Voltage
Figure 20. Input Bias Current vs. Common Mode Voltage
8
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SNOSD33B –NOVEMBER 2016–REVISED NOVEMBER 2016
Typical Characteristics (continued)
at TA = 25°C, RL = 10MΩ to VS/2 ,CL = 20pF, VCM = VS / 2V unless otherwise specified.
10
10
+125°C
+25°C
-40°C
+125°C
+25°C
-40°C
1
1
100m
10m
1m
100m
10m
1m
100ꢀ
100ꢀ
1ꢀ
10ꢀ
100ꢀ
1m
10m
1ꢀ
10ꢀ
100ꢀ
1m
10m
Output Sourcing Current (A)
Output Sinking Current (A)
C003
C006
VS= 1.8V
RL= No Load
VS= 1.8V
RL= No Load
Figure 21. Output Swing vs. Sourcing Current, 1.8V
Figure 22. Output Swing vs. Sinking Current, 1.8V
10
10
+125°C
+25°C
-40°C
+125°C
+25°C
-40°C
1
100m
10m
1m
1
100m
10m
1m
100ꢀ
100ꢀ
1ꢀ
10ꢀ
100ꢀ
1m
10m
1ꢀ
10ꢀ
100ꢀ
1m
10m
Output Sourcing Current (A)
Output Sinking Current (A)
C001
C005
VS= 3.3V
RL= No Load
VS= 3.3V
RL= No Load
Figure 23. Output Swing vs. Sourcing Current, 3.3V
Figure 24. Output Swing vs. Sinking Current, 3.3V
10
10
+125°C
+25°C
-40°C
+125°C
+25°C
-40°C
1
100m
10m
1m
1
100m
10m
1m
100ꢀ
100ꢀ
1ꢀ
10ꢀ
100ꢀ
1m
10m
1ꢀ
10ꢀ
100ꢀ
1m
10m
Output Sourcing Current (A)
Output Sinking Current (A)
C001
C004
VS= 5V
RL= No Load
VS= 5V
RL= No Load
Figure 25. Output Swing vs. Sourcing Current, 5V
Figure 26. Output Swing vs. Sinking Current, 5V
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Typical Characteristics (continued)
at TA = 25°C, RL = 10MΩ to VS/2 ,CL = 20pF, VCM = VS / 2V unless otherwise specified.
500 us/div
500 us/div
C002
C002
TA = 25
RL= 10MΩ
Vout = 200mVpp
AV = +1
TA = 25
RL= 10MΩ
Vout = 200mVpp
VS= ±0.9V
CL= 20pF
VS= ±2.5V
CL= 20pF
AV = +1
Figure 27. Small Signal Pulse Response, 1.8V
Figure 28. Small Signal Pulse Response, 5V
500 us/div
500 us/div
C002
C002
TA = 25
RL= 10MΩ
Vout = 1Vpp
AV = +1
TA = 25
RL= 10MΩ
Vout = 2Vpp
AV = +1
VS= ±0.9V
CL= 20pF
VS= ±2.5V
CL= 20pF
Figure 29. Large Signal Pulse Response, 1.8V
Figure 30. Large Signal Pulse Response, 5V
110
100
90
80
70
60
50
40
30
20
10
0
140
120
100
80
+PSRR
-PSRR
60
40
20
0
10
100
1k
10k
1
10
100
1k
10k
Frequency (Hz)
RL= 10MΩ
CL= 20p
Frequency (Hz)
RL= 10MΩ
CL= 20p
C001
C001
TA = 25
VS= 3.3V
VCM = Vs/2
ΔVS = 0.5Vpp
TA = 25
VS= 5V
ΔVCM = 0.5Vpp
AV = +1
VCM = Vs/2
AV = +1
Figure 32. ±PSRR vs Frequency
Figure 31. CMRR vs Frequency
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SNOSD33B –NOVEMBER 2016–REVISED NOVEMBER 2016
Typical Characteristics (continued)
at TA = 25°C, RL = 10MΩ to VS/2 ,CL = 20pF, VCM = VS / 2V unless otherwise specified.
160
140
120
100
80
180
158
135
113
90
160
140
120
100
80
180
158
135
113
90
125°C
25°C
-40°C
125°C
25°C
-40°C
GAIN
GAIN
60
68
60
68
PHASE
PHASE
40
45
40
45
20
23
20
23
0
0
0
0
œ20
-23
œ20
-23
1m
10m 100m
1
10
100
1k
10k 100k
1m
10m 100m
1
10
100
1k
10k 100k
Frequency (Hz)
Frequency (Hz)
C001
C002
TA = -40, 25, 125°C
VS= 5V
RL= 10MΩ
CL= 20pF
VOUT = 200mVPP
VCM = Vs/2
TA = -40, 25, 125°C
VS= 3.3V
RL= 10MΩ
CL= 20pF
VOUT = 200mVPP
VCM = Vs/2
Figure 33. Open Loop Gain and Phase, 5V, 10 MΩ Load
Figure 34. Open Loop Gain and Phase, 3.3V, 10 MΩ Load
160
180
158
135
113
90
160
180
158
135
113
90
125°C
25°C
-40°C
125°C
25°C
-40°C
140
120
100
80
140
120
100
80
GAIN
GAIN
60
68
60
68
PHASE
PHASE
40
45
40
45
20
23
20
23
0
0
0
0
œ20
-23
œ20
-23
1m
10m 100m
1
10
100
1k
10k 100k
1m
10m 100m
1
10
100
1k
10k 100k
Frequency (Hz)
Frequency (Hz)
C003
C002
TA = -40, 25, 125°C
VS= 5V
RL= 1MΩ
CL= 20pF
VOUT = 200mVPP
VCM = Vs/2
TA = -40, 25, 125°C
VS= 3.3V
RL= 1MΩ
CL= 20pF
VOUT = 200mVPP
VCM = Vs/2
Figure 35. Open Loop Gain and Phase, 5V, 1 MΩ Load
Figure 36. Open Loop Gain and Phase, 3.3V, 1 MΩ Load
160
180
158
135
113
90
160
180
158
135
113
90
125°C
25°C
-40°C
125°C
25°C
-40°C
140
120
100
80
140
120
100
80
GAIN
GAIN
60
68
60
68
PHASE
PHASE
40
45
40
45
20
23
20
23
0
0
0
0
œ20
-23
œ20
-23
1m
10m 100m
1
10
100
1k
10k 100k
1m
10m 100m
1
10
100
1k
10k 100k
Frequency (Hz)
Frequency (Hz)
C001
C002
TA = -40, 25, 125°C
VS= 5V
RL= 100kΩ
CL= 20pF
VOUT = 200mVPP
VCM = Vs/2
TA = -40, 25, 125°C
VS= 3.3V
RL= 100kΩ
CL= 20pF
VOUT = 200mVPP
VCM = Vs/2
Figure 37. Open Loop Gain and Phase, 5V, 100kΩ Load
Figure 38. Open Loop Gain and Phase, 3.3V, 100kΩ Load
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Typical Characteristics (continued)
at TA = 25°C, RL = 10MΩ to VS/2 ,CL = 20pF, VCM = VS / 2V unless otherwise specified.
1M
100k
10k
1k
160
140
120
100
80
180
158
135
113
90
125°C
25°C
-40°C
GAIN
60
68
PHASE
40
45
20
23
0
0
œ20
-23
100
1m
10m 100m
1
10
100
1k
10k 100k
100m
1
10
100
1k
10k
100k
Frequency (Hz)
C003
Frequency (Hz)
VS= 5 V
C001
TA = -40, 25, 125°C
VS= 1.8V
RL= 10MΩ
CL= 20pF
VOUT = 200mVPP
VCM = Vs/2
TA = 25°C
RL= 10MΩ
Figure 40. Open Loop Output Impedance
Figure 39. Open Loop Gain and Phase, 1.8V, 10 MΩ Load
160
180
158
135
113
90
10000
1000
100
125°C
25°C
-40°C
140
120
100
80
GAIN
60
68
PHASE
40
45
20
23
0
0
œ20
-23
1m
10m 100m
1
10
100
1k
10k 100k
10
100m
1
10
100
1k
10k
Frequency (Hz)
C003
Frequency (Hz)
RL= 1MΩ
C001
TA = -40, 25, 125°C
VS= 1.8V
RL= 1MΩ
CL= 20pF
VOUT = 200mVPP
VCM = Vs/2
TA = 25
VS= 5V
VCM = Vs/2
CL= 20pF
AV = +1
Figure 41. Open Loop Gain and Phase, 1.8V, 1 MΩ Load
Figure 42. Input Voltage Noise vs Frequency
160
180
158
135
113
90
120
100
80
60
40
20
0
LPV812, -20dBm
LPV812, -10dBm
LPV812, 0dBm
125°C
25°C
-40°C
140
120
100
80
GAIN
60
68
PHASE
40
45
20
23
0
0
œ20
-23
10k 100k
1m
10m 100m
1
10
100
1k
10
100
1000
Frequency (Hz)
C003
Frequency (MHz)
RL= 1MΩ
C001
TA = -40, 25, 125°C
VS= 1.8V
RL= 100kΩ
CL= 20pF
VOUT = 200mVPP
VCM = Vs/2
TA = 25
VCM = Vs/2
VS= 3.3V
CL= 20pF
AV = +1
Figure 43. Open Loop Gain and Phase, 1.8V, 100kΩ Load
Figure 44. EMIRR Performance
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7 Detailed Description
7.1 Overview
The LPV811 (single) and LPV812 (dual) series of nanoPower CMOS operational amplifiers are designed for
long-life battery-powered and energy harvested applications. They operate on a single supply with operation as
low as 1.6V. The Input Offset is trimmed to less than 300uV and the output is rail-to-rail and swings to within
3.5mV of the supplies with a 100kΩ load. The common-mode range extends to the negative supply making it
ideal for single-supply applications. EMI protection has been employed internally to reduce the effects of EMI.
Parameters that vary significantly with operating voltages or temperature are shown in the Typical Characteristics
curves.
7.2 Functional Block Diagram
V+
_
+
IN –
IN +
OUT
V–
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Texas Instruments Incorporated
7.3 Feature Description
The amplifier's differential inputs consist of a non-inverting input (+IN) and an inverting input (–IN). The amplifier
amplifies only the difference in voltage between the two inputs, which is called the differential input voltage. The
output voltage of the op-amp VOUT is given by Equation 1:
VOUT = AOL (IN+ – IN–)
where
•
AOL is the open-loop gain of the amplifier, typically around 120 dB (1,000,000x, or 1,000,000 Volts per
microvolt).
(1)
7.4 Device Functional Modes
7.4.1 Negative-Rail Sensing Input
The input common-mode voltage range of the LPV81x extends from (V-) to (V+) – 0.9 V. In this range, low offset
can be expected with a minimum of 77dB CMRR. The LPV81x is protected from output "inversions" or
"reversals".
7.4.2 Rail to Rail Output Stage
The LPV81x output voltage swings 3.5 mV from rails at 1.8 V supply, which provides the maximum possible
dynamic range at the output. This is particularly important when operating on low supply voltages.
The LPV81x Maximum Output Voltage Swing graph defines the maximum swing possible under a particular
output load.
7.4.3 Design Optimization for Nanopower Operation
When designing for ultra-low power, choose system feedback components carefully. To minimize quiescent
current consumption, select large-value feedback resistors. Any large resistors will react with stray capacitance in
the circuit and the input capacitance of the operational amplifier. These parasitic RC combinations can affect the
stability of the overall system. A feedback capacitor may be required to assure stability and limit overshoot or
gain peaking.
When possible, use AC coupling and AC feedback to reduce static current draw through the feedback elements.
Use film or ceramic capacitors since large electrolytics may have large static leakage currents in the nanoamps.
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Device Functional Modes (continued)
7.4.4 Driving Capacitive Load
The LPV81x is internally compensated for stable unity gain operation, with a 8 kHz typical gain bandwidth.
However, the unity gain follower is the most sensitive configuration to capacitive load. The combination of a
capacitive load placed directly on the output of an amplifier along with the amplifier’s output impedance creates a
phase lag, which reduces the phase margin of the amplifier. If the phase margin is significantly reduced, the
response will be under damped which causes peaking in the transfer and, when there is too much peaking, the
op amp might start oscillating.
In order to drive heavy (>50pF) capacitive loads, an isolation resistor, RISO, should be used, as shown in
Figure 45. By using this isolation resistor, the capacitive load is isolated from the amplifier’s output. The larger
the value of RISO, the more stable the amplifier will be. If the value of RISO is sufficiently large, the feedback loop
will be stable, independent of the value of CL. However, larger values of RISO result in reduced output swing and
reduced output current drive. The recommended value for RISO is 30-50kΩ.
R
ISO
-
V
OUT
V
IN
+
C
L
Figure 45. Resistive Isolation Of Capacitive Load
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LPV81x is a ultra-low power operational amplifier that provides 8 kHz bandwidth with only 425nA typical
quiescent current, trimmed input offset voltage and precision drift specifications. These rail-to-rail output
amplifiers are specifically designed for battery-powered applications. The input common-mode voltage range
extends to the negative supply rail and the output swings to within millivolts of the rails, maintaining a wide
dynamic range.
8.2 Typical Application: Three Terminal CO Gas Sensor Amplifier
R1
10 kꢀ
C1
0.1µF
Potentiostat (Bias Loop)
CE
R2
10 kΩ
2.5V
RE
CO Sensor
U1
+
VREF
WE
Transimpedance Amplifier (I to V conversion)
RF
ISENS
Riso
49.9 kꢀ
RL
U2
VTIA
+
VREF
C2
1µF
Figure 46. Three Terminal Gas Sensor Amplifier Schematic
8.2.1 Design Requirements
Figure 46 shows a simple micropower potentiostat circuit for use with three terminal unbiased CO sensors,
though it is applicable to many other type of three terminal gas sensors or electrochemical cells.
The basic sensor has three electrodes; The Sense or Working Electrode (“WE”), Counter Electrode (“CE”) and
Reference Electrode (“RE”). A current flows between the CE and WE proportional to the detected concentration.
The RE monitors the potential of the internal reference point. For an unbiased sensor, the WE and RE electrodes
must be maintained at the same potential by adjusting the bias on CE. Through the Potentiostat circuit formed by
U1, the servo feedback action will maintain the RE pin at a potential set by VREF
.
R1 is to maintain stability due to the large capacitance of the sensor. C1 and R2 form the Potentiostat integrator
and set the feedback time constant.
U2 forms a transimpedance amplifier ("TIA") to convert the resulting sensor current into a proportional voltage.
The transimpedance gain, and resulting sensitivity, is set by RF according to Equation 2.
VTIA = (-I * RF) + VREF
(2)
RL is a load resistor of which the value is normally specified by the sensor manufacturer (typically 10 ohms). The
potential at WE is set by the applied VREF. Riso provides capacitive isolation and, combined with C2, form the
output filter and ADC reservoir capacitor to drive the ADC.
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Typical Application: Three Terminal CO Gas Sensor Amplifier (continued)
8.2.2 Detailed Design Procedure
For this example, we will be using a CO sensor with a sensitivity of 69nA/ppm. The supply voltage and maximum
ADC input voltage is 2.5V, and the maximum concentration is 300ppm.
First the VREF voltage must be determined. This voltage is a compromise between maximum headroom and
resolution, as well as allowance for "footroom" for the minimum swing on the CE terminal, since the CE terminal
generally goes negative in relation to the RE potential as the concentration (sensor current) increases. Bench
measurements found the difference between CE and RE to be 180mV at 300ppm for this particular sensor.
To allow for negative CE swing "footroom" and voltage drop across the 10k resistor, 300mV was chosen for
VREF
.
Therefore +300mV will be used as the minimum VZERO to add some headroom.
VZERO = VREF = +300mV
where
•
•
VZERO is the zero concentration voltage
VREF is the reference voltage (300mV)
(3)
Next we calculate the maximum sensor current at highest expected concentration:
ISENSMAX = IPERPPM * ppmMAX = 69nA * 300ppm = 20.7uA
where
•
•
•
ISENSMAX is the maximum expected sensor current
IPERPPM is the manufacturer specified sensor current in Amps per ppm
ppmMAX is the maximum required ppm reading
(4)
(5)
Now find the available output swing range above the reference voltage available for the measurement:
VSWING = VOUTMAX – VZERO = 2.5V – 0.3V = 2.2V
where
•
•
VSWING is the expected change in output voltage
VOUTMAX is the maximum amplifier output swing (usually near V+)
Now we calculate the transimpedance resistor ®F) value using the maximum swing and the maximum sensor
current:
RF = VSWING / ISENSMAX = 2.2V / 20.7µA = 106.28 kΩ (we will use 110 kΩ for a common value)
(6)
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Typical Application: Three Terminal CO Gas Sensor Amplifier (continued)
8.2.3 Application Curve
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0.00
Vc
Vw
Vtia
Vdif
0
15
30
45
60
75
90
105
120
135
150
Time (sec)
C007
Figure 47. Monitored Voltages when exposed to 200ppm CO
Figure 47 shows the resulting circuit voltages when the sensor was exposed to 200ppm step of carbon monoxide
gas. VC is the monitored CE pin voltage and clearly shows the expected CE voltage dropping below the WE
voltage, VW, as the concentration increases.
VTIA is the output of the transimpedance amplifier U2. VDIFF is the calculated difference between VREF and VTIA
,
which will be used for the ppm calculation.
20
18
16
14
12
10
8
300
250
200
150
100
50
6
4
2
0
0
0
15
30
45
60
75
90 105 120 135 150
0
15
30
45
60
75
90 105 120 135 150
Time (sec)
Time (sec)
C002
C003
Figure 48. Calculated Sensor Current
Figure 49. Calculated ppm
Figure 48 shows the calculated sensor current using the formula in Equation 7 :
ISENSOR = VDIFF / RF = 1.52V / 110 kΩ = 13.8uA
(7)
(8)
Equation 8 shows the resulting conversion of the sensor current into ppm.
ppm = ISENSOR / IPERPPM = 13.8µA / 69nA = 200
Total supply current for the amplifier section is less than 700 nA, minus sensor current. Note that the sensor
current is sourced from the amplifier output, which in turn comes from the amplifier supply voltage. Therefore,
any continuous sensor current must also be included in supply current budget calculations.
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8.3 Do's and Don'ts
Do properly bypass the power supplies.
Do add series resistance to the output when driving capacitive loads, particularly cables, Muxes and ADC inputs.
Do add series current limiting resistors and external schottky clamp diodes if input voltage is expected to exceed
the supplies. Limit the current to 1mA or less (1KΩ per volt).
9 Power Supply Recommendations
The LPV81x is specified for operation from 1.6 V to 5.5 V (±0.8 V to ±2.75 V) over a –40°C to 125°C temperature
range. Parameters that can exhibit significant variance with regard to operating voltage or temperature are
presented in the Typical Characteristics.
CAUTION
Supply voltages larger than 6 V can permanently damage the device.
For proper operation, the power supplies must be properly decoupled. For decoupling the supply lines it is
suggested that 100 nF capacitors be placed as close as possible to the operational amplifier power supply pins.
For single supply, place a capacitor between V+ and V– supply leads. For dual supplies, place one capacitor
between V+ and ground, and one capacitor between V– and ground.
Low bandwidth nanopower devices do not have good high frequency (> 1 kHz) AC PSRR rejection against high-
frequency switching supplies and other 1 kHz and above noise sources, so extra supply filtering is recommended
if kilohertz or above noise is expected on the power supply lines.
10 Layout
10.1 Layout Guidelines
The V+ pin should be bypassed to ground with a low ESR capacitor.
The optimum placement is closest to the V+ and ground pins.
Care should be taken to minimize the loop area formed by the bypass capacitor connection between V+ and
ground.
The ground pin should be connected to the PCB ground plane at the pin of the device.
The feedback components should be placed as close to the device as possible to minimize strays.
10.2 Layout Example
Figure 50. SOT-23 Layout Example (Top View)
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
TINA-TI SPICE-Based Analog Simulation Program
DIP Adapter Evaluation Module
TI Universal Operational Amplifier Evaluation Module
TI FilterPro Filter Design Software
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
•
•
•
•
•
•
•
•
AN-1798 Designing with Electro-Chemical Sensors
AN-1803 Design Considerations for a Transimpedance Amplifier
AN-1852 Designing With pH Electrodes
Compensate Transimpedance Amplifiers Intuitively
Transimpedance Considerations for High-Speed Operational Amplifiers
Noise Analysis of FET Transimpedance Amplifiers
Circuit Board Layout Techniques
Handbook of Operational Amplifier Applications
11.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 1. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
SAMPLE & BUY
LPV811
LPV812
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
11.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.5 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.6 Trademarks
E2E is a trademark of Texas Instruments.
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11.6 Trademarks (continued)
All other trademarks are the property of their respective owners.
11.7 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
30-Nov-2016
PACKAGING INFORMATION
Orderable Device
LPV811DBVR
LPV811DBVT
LPV812DGKR
LPV812DGKT
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
SOT-23
SOT-23
VSSOP
VSSOP
DBV
5
5
8
8
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
15TM
15TM
ACTIVE
ACTIVE
ACTIVE
DBV
DGK
DGK
250
2500
250
Green (RoHS
& no Sb/Br)
CU SN
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
CU NIPDAUAG
LPV
812
Green (RoHS
& no Sb/Br)
LPV
812
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Nov-2016
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Dec-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LPV811DBVR
LPV811DBVT
LPV812DGKR
LPV812DGKT
SOT-23
SOT-23
VSSOP
VSSOP
DBV
DBV
DGK
DGK
5
5
8
8
3000
250
178.0
178.0
330.0
178.0
8.4
8.4
3.2
3.2
5.3
5.3
3.2
3.2
3.4
3.4
1.4
1.4
1.4
1.4
4.0
4.0
8.0
8.0
8.0
8.0
Q3
Q3
Q1
Q1
2500
250
12.4
13.4
12.0
12.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Dec-2016
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LPV811DBVR
LPV811DBVT
LPV812DGKR
LPV812DGKT
SOT-23
SOT-23
VSSOP
VSSOP
DBV
DBV
DGK
DGK
5
5
8
8
3000
250
210.0
210.0
364.0
202.0
185.0
185.0
364.0
201.0
35.0
35.0
27.0
28.0
2500
250
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
B
1.45 MAX
A
PIN 1
INDEX AREA
1
2
5
2X 0.95
1.9
3.05
2.75
1.9
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/C 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/C 04/2017
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/C 04/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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