PTCAN3413DR [TI]
3.3-V CAN FD transceiver with flexible IO and standby mode | D | 8 | -40 to 150;
| 型号： | PTCAN3413DR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3-V CAN FD transceiver with flexible IO and standby mode | D | 8 | -40 to 150 |
| 文件： | 总42页 (文件大小：2055K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TCAN3413, TCAN3414
ZHCSRW5 –MARCH 2023
TCAN341x 具有待机模式的3.3V CAN 收发器
1 特性
3 说明
• 3.3 V 单电源工作
TCAN3413 and TCAN3414 是符合 ISO 11898-2:2016
高速 CAN 规范物理层要求的控制器局域网 (CAN) FD
收发器。
– 无需使用5V 稳压器，从而节省BOM 成本并减
小PCB 空间
• 符合ISO 11898-2:2016 物理层标准要求
• 支持传统CAN 和经优化的CAN FD 性能（数据速
率为2、5 和8Mbps）
– 具有较短的对称传播延迟时间，可增加时序裕量
• TCAN3413：I/O 电压范围支持：
1.7V 至3.6V
此类收发器具有经过认证的电磁兼容性 (EMC)，适用
于数据速率高达 5 兆位/秒 (Mbps) 的传统 CAN 和
CAN FD 网络。这些器件可以在更简单的网络中实现高
达 8Mbps 的运行速度。TCAN3413 包括通过 VIO 引脚
实现的内部逻辑电平转换。允许收发器 I/O 直接连接到
1.8V、2.5V 或3.3V 逻辑电平。此类收发器支持低功耗
待机模式，并且可通过符合 ISO 11898-2:2016 所定义
唤醒模式(WUP) 的CAN 来唤醒。
• 接收器共模输入电压：±30V
• 保护特性：
– 总线故障保护：±58V
– 欠压保护
– TXD 显性超时(DTO)
– 热关断保护(TSD)
• 工作模式：
此外，该收发器支持热关断 (TSD)、TXD 显性超时
(DTO)、电源欠压检测和 ±58V 的总线故障保护。这些
器件定义了电源欠压或浮动引脚情况下的失效防护行
为。这些收发器采用业界通用的 SOIC-8、VSON-8 和
节省空间的小尺寸SOT-23 封装。
– 正常模式
– 支持远程唤醒请求功能的低功耗待机模式
封装信息
封装(1)
SOIC (D)
VSON (DRB)
封装尺寸（标称值）
4.90mm x 3.91mm
3.00mm x 3.00mm
器件型号
– 超低功耗关断模式：
仅TCAN3414
• 优化了未上电时的性能
TCAN3413
TCAN3414
SOT-23 (DDF)(2) 2.90mm x 1.60mm
– 总线和逻辑引脚为高阻抗（运行总线或应用上无
负载）
– 支持热插拔：在总线和RXD 输出上可实现上电
和断电无干扰运行
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
(2) 产品预发布
• 小型8 引脚SOIC SOT-23 和无引线VSON-8 封
装，提高了自动光学检测(AOI) 能力
表3-1. 器件信息
引脚5
超低功耗关断模式
低压I/O 支持
引脚8
器件型号
TCAN3414
2 应用
具有远程唤醒功能的
低功耗待机模式
• 工厂自动化
• 电网基础设施
• 工业运输
TCAN3413
• 电机驱动器
VOUT
VIN
VIN
3.3 V Voltage
Regulator
3
VCC
7
VDD
CANH
8
5
STB
SHDN
TCAN3414
MCU
4
1
CAN FD
Controller
RXD
TXD
6
CANL
GND
Optional:
Terminating Node
Optional: Filtering,
Transient and ESD
简化原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLSFS8
TCAN3413, TCAN3414
ZHCSRW5 –MARCH 2023
www.ti.com.cn
Table of Contents
8.3 Feature Description...................................................14
8.4 Device Functional Modes..........................................19
9 Application and Implementation..................................22
9.1 Application Information............................................. 22
9.2 Typical Application.................................................... 22
9.3 System Examples..................................................... 24
9.4 Power Supply Recommendations.............................26
9.5 Layout....................................................................... 27
10 Device and Documentation Support..........................28
10.1 接收文档更新通知................................................... 28
10.2 支持资源..................................................................28
10.3 Trademarks.............................................................28
10.4 静电放电警告.......................................................... 28
10.5 术语表..................................................................... 28
11 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 绝对最大额定值...........................................................4
6.2 ESD Ratings .............................................................. 4
6.3 ESD Ratings, IEC Transients......................................4
6.4 Recommended Operating Conditions.........................4
6.5 Thermal Characteristics..............................................4
6.6 Supply Characteristics................................................ 5
6.7 Dissipation Ratings..................................................... 6
6.8 Electrical Characteristics.............................................6
6.9 Switching Characteristics............................................8
7 Parameter Measurement Information.......................... 11
8 Detailed Description......................................................14
8.1 Overview...................................................................14
8.2 Functional Block Diagram.........................................14
Information.................................................................... 28
11.1 Tape and Reel Information......................................29
11.2 Mechanical Data..................................................... 31
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
March 2023
*
Initial Release
Copyright © 2023 Texas Instruments Incorporated
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Product Folder Links: TCAN3413 TCAN3414
English Data Sheet: SLLSFS8
TCAN3413, TCAN3414
ZHCSRW5 –MARCH 2023
www.ti.com.cn
5 Pin Configuration and Functions
TXD
1
2
3
4
8
7
6
5
STB
TXD
1
2
3
4
8
7
6
5
STB
GND
CANH
CANL
SHDN,V
GND
CANH
CANL
V
ꢀ
V
ꢀ
CC
RXD
CC
RXD
ꢀ
SHDN,V
ꢀ
IO
IO
Not to scale
Not to scale
图5-1. DDF Package, 8-Pin SOT
图5-2. D Package, 8-Pin SOIC
(Top View)
(Top View)
TXD
1
2
3
4
8
7
6
5
STB
GND
CANH
CANL
Thermal
Pad
V
ꢀ
CC
RXD
SHDN,V
ꢀ
IO
Not to scale
图5-3. DRB Package, 8-Pin VSON
(Top View)
表5-1. Pin Functions
Pins
Type(1)
Description
Name
TXD
GND
VCC
No.
1
Digital Input CAN transmit data input; integrated pull-up
2
G
Ground connection
3.3 V supply voltage
3
Supply
RXD
4
Digital Output CAN receive data output, tri-stated when device powered off
Device in ultra-low power shutdown mode if pin is high; integrated pull-down (TCAN3414
only)
SHDN
Digital Input
5
VIO
Supply
Bus IO
Bus IO
I/O supply voltage (TCAN3413 only)
Low-level CAN bus input/output line
High-level CAN bus input/output line
CANL
CANH
STB
6
7
8
Digital Input Standby input for mode control; integrated pull-up
Connect the thermal pad to any internal PCB ground plane using multiple vias for optimal
thermal performance.
Thermal Pad (VSON only)
—
(1) I = Input, O = Output, I/O = Input or Output, G = Ground.
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Product Folder Links: TCAN3413 TCAN3414
English Data Sheet: SLLSFS8
TCAN3413, TCAN3414
ZHCSRW5 –MARCH 2023
www.ti.com.cn
6 Specifications
6.1 绝对最大额定值
在自然通风条件下的工作温度范围内（除非另有说明）((1)) ((2))
最小值
–0.3
–0.3
–58
最大值
单位
VCC
6
V
电源电压
VIO
6
V
V
电源电压I/O 电平转换器（仅适用于TCAN3413）
CANH 和CANL 上的CAN 总线I/O 电压范围
VBUS
58
CANH 和CANL 之间的最大差分电压
VDIFF = (CANH - CANL)
VDIFF
58
V
–58
VLogic_Input
VRXD
IO(RXD)
TJ
6
6
V
V
逻辑引脚输入电压（TXD、STB、SHDN）
–0.3
–0.3
–8
逻辑输出电压范围(RXD)
RXD 输出电流
结温
8
mA
°C
°C
-40
165
150
TSTG
–65
存储温度
(1) 超出绝对最大额定值运行可能会对器件造成永久损坏。绝对最大额定值并不表示器件在这些条件下或在建议运行条件以外的任何其他条
件下能够正常运行。如果超出建议工作条件但在绝对最大额定值范围内使用，器件可能不会完全正常运行，这可能影响器件的可靠性、
功能和性能，并缩短器件寿命。
(2) 除差分I/O 总线电压外的所有电压值都是相对于接地引脚的值。
6.2 ESD Ratings
VALUE
UNIT
HBM classification level 3A for
all pins
±4000
V
Human-body model (HBM), per AEC Q100-002(1)
HBM classification level 3B for
global pins CANH and CANL
with respect to GND
VESD
Electrostatic discharge
±10000
±750
V
V
Charged-device model (CDM), per AEC Q100-011
CDM classification level C5 for all pins
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 ESD Ratings, IEC Transients
VALUE
UNIT
VESD System level electrostatic discharge
CANH, CANL w.r.t GND per IEC61000-4-2
±12000
V
6.4 Recommended Operating Conditions
MIN
3
NOM
MAX
UNIT
V
VCC
Supply voltage
3.3
3.6
3.6
VIO
Supply voltage for I/O level shifter (only for TCAN3413)
RXD terminal high-level output current
RXD terminal low-level output current
RXD terminal high-level output current (only for TCAN3413)
RXD terminal low-level output current (only for TCAN3413)
Junction temperature
1.7
–2
V
IOH(RXD)
IOL(RXD)
IOH(RXD)
IOL(RXD)
TJ
mA
mA
mA
mA
°C
2
–1.5
–40
1.5
150
6.5 Thermal Characteristics
TCAN3413/3414
DDF (SOT)
THERMAL METRIC(1)
UNIT
℃/W
D (SOIC)
DRB (VSON)
RΘJA
Junction-to-ambient thermal resistance
114.4
122.9
50.9
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLLSFS8
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ZHCSRW5 –MARCH 2023
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6.5 Thermal Characteristics (continued)
TCAN3413/3414
DDF (SOT)
THERMAL METRIC(1)
UNIT
D (SOIC)
DRB (VSON)
RΘJC(top)
RΘJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
49.0
58.0
7.0
51.7
45.7
1.3
55.8
23.2
1.4
℃/W
℃/W
℃/W
℃/W
℃/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ΨJT
57.1
N/A
45.4
N/A
23.2
7.7
ΨJB
RΘJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.6 Supply Characteristics
parameters valid over recommended operating conditions with -40℃≤TJ ≤150℃(Typical values are at VCC = 3.3 V; VIO
3.3 V for TCAN3413, Device ambient maintained at 27℃) unless otherwise noted
=
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TXD = 0 V, STB = 0 V
RL = 60 Ω, CL = open
See 图7-1
Dominant
Dominant
Recessive
TBD
55
mA
TXD = 0 V, STB = 0 V
RL = 50 Ω, CL = open
See 图7-1
Supply current normal
mode (TCAN3414)
ICC
TBD
TBD
60
mA
mA
TXD = VCC, STB = 0 V
RL = 50 Ω, CL = open
See 图7-1
8.2
TXD = 0 V, STB = 0 V
CANH = CANL = ±25 V
RL = open, CL = open
See 图7-1
Supply current normal
mode (TCAN3414)
Dominant with
bus fault
130
mA
µA
TXD = STB = VIO, RL = 50 Ω, CL = open,
TJ <= 85 °C, See 图7-1
TBD
TBD
TBD
TBD
TBD
TBD
2
3
Supply current standby mode (TCAN3413)
TXD = STB = VIO, RL = 50 Ω, CL = open,
TJ <= 125 °C, See 图7-1
ICC
TXD = STB = VIO, RL = 50 Ω, CL = open,
TJ <= 150 °C, See 图7-1
4
TXD = STB = VCC, RL = 50 Ω, CL = open,
TJ <= 85 °C, See 图7-1
15
16
17
TXD = STB = VCC, RL = 50 Ω, CL = open,
TJ <= 125 °C, See 图7-1
Supply current standby mode (TCAN3414)
µA
TXD = STB = VCC, RL = 50 Ω, CL = open,
TJ <= 150 °C, See 图7-1
TXD = 0 V, STB = 0 V
RL = 60 Ω, CL = open
RXD floating
Dominant
125
25
9
300
48
13
14
15
I/O supply current normal
mode
TXD = VIO, STB = 0 V
RL = 60 Ω, CL = open
RXD floating
recessive
IIO (only
for
TCAN34
13)
TXD = VIO, STB = VIO
RL = 60 Ω, CL = open
RXD floating, TJ <= 85 °C
µA
TXD = VIO, STB = VIO
RL = 60 Ω, CL = open
RXD floating, TJ <= 125 °C
I/O supply current standby mode
9
TXD = VIO, STB = VIO
RL = 60 Ω, CL = open
RXD floating, TJ <= 150 °C
9
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Product Folder Links: TCAN3413 TCAN3414
English Data Sheet: SLLSFS8
TCAN3413, TCAN3414
ZHCSRW5 –MARCH 2023
www.ti.com.cn
6.6 Supply Characteristics (continued)
parameters valid over recommended operating conditions with -40℃≤TJ ≤150℃(Typical values are at VCC = 3.3 V; VIO
3.3 V for TCAN3413, Device ambient maintained at 27℃) unless otherwise noted
=
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SHDN = VCC, RXD floating, TXD =
VCC, TJ <= 85 °C
2
Supply current (VCC pin current), shutdown
mode (TCAN3414)
ICC
µA
SHDN = VCC, RXD floating, TXD =
VCC, TJ <= 150 °C
5
UVCC(R) Undervoltage detection VCC rising
UVCC(F) Undervoltage detection on VCC falling
Ramp up
2.75
2.65
2.9
V
Ramp down
2.5
1.4
VHYS
Hysteresis voltage on UVCC
140
1.6
1.5
mV
(UVCC)
UVIO(R)
UVIO(F)
Undervoltage detection VIO rising (TCAN3413) Ramp up
1.65
V
Undervoltage detection on VIO
falling (TCAN3413)
Ramp down
VHYS(UVI
Hysteresis voltage on UVIO
100
mV
O)
6.7 Dissipation Ratings
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCC = 3.3 V, TJ = 27°C, RL = 60Ω, CL_RXD = 15
pF
60
mW
TXD input = 250 kHz 50% duty cycle square
wave
Average power dissipation
Normal mode
PD
VCC = 3.6 V, TJ = 150°C, RL = 50Ω, CL_RXD
=
15 pF
120
mW
°C
TXD input = 2.5 MHz 50% duty cycle square
wave
TTSD
Thermal shutdown temperature
192
10
TTSD_HYS Thermal shutdown hysteresis
6.8 Electrical Characteristics
parameters valid over recommended operating conditions with -40℃≤TJ ≤150℃(Typical values are at VCC = 3.3 V, VIO
3.3 V for TCAN3403, Device ambient maintained at 27℃) unless otherwise noted
=
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Driver Electrical Characteristics
CANH
CANL
TXD = 0 V, STB, SHDN = 0 V
50 Ω ≤RL ≤65 Ω, CL = open
See 图7-2 and 图8-3
2.25
0.5
VCC
V
V
Dominant output voltage
normal mode
VO(DOM)
1.25
TXD = VIO, STB, SHDN = 0 V
RL = open (no load), CL = open
See 图7-2 and 图8-3
Recessive output voltage
normal mode
VO(REC)
CANH and CANL
1.5
0.9
1.9
2.25
V
TXD = 250 kHz, 1 MHz, 2.5 MHz, STB,
SHDN = 0 V
RL = 60, CSPLIT = 4.7 nF, CL = open
Driver symmetry
VSYM
{(VO(CANH) + VO(CANL))/(VO(REC_CANH)
VO(REC_CANL)
+
1.1 V/V
400 mV
}
See 图7-2 and 图9-2
STB, SHDN = 0 V
RL = 60 Ω, CL = open
See 图7-2 and 图8-3
DC output symmetry
(CANHREC + CANLREC - CANHDOM - CANLDOM
VSYM_DC
–400
1.5
)
TXD = 0 V, STB. SHDN = 0 V
50 Ω ≤RL ≤65 Ω, CL = open
See 图7-2 and 图8-3
3
3
V
V
V
CANH - CANL
TXD = 0 V, STB, SHDN = 0 V
45 Ω ≤RL ≤70 Ω, CL = open
See 图7-2 and 图8-3
Differential output voltage
normal mode
Dominant
VOD(DOM)
1.4
TXD = 0 V, STB, SHDN = 0 V
RL = 2240 Ω, CL = open
See 图7-2 and 图8-3
CANH - CANL
1.5
3.4
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English Data Sheet: SLLSFS8
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6.8 Electrical Characteristics (continued)
parameters valid over recommended operating conditions with -40℃≤TJ ≤150℃(Typical values are at VCC = 3.3 V, VIO
3.3 V for TCAN3403, Device ambient maintained at 27℃) unless otherwise noted
=
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
TXD = VIO, STB, SHDN = 0 V
RL = 60 Ω, CL = open
See 图7-2 and 图8-3
CANH - CANL
CANH - CANL
12 mV
–120
Differential output voltage
normal mode
Recessive
VOD(REC)
TXD = VIO, STB, SHDN = 0 V
RL = open, CL = open
50 mV
–50
See 图7-2 and 图8-3
CANH
-0.1
-0.1
-0.2
0.1
0.1
0.2
V
V
V
TXD = STB = VIO
RL = open , CL = open
See 图7-2 and 图8-3
Bus output voltage standby
mode
VO(STB)
CANL
CANH - CANL
See 图7-7 and 图8-3, V(CANH) = -15 V to
40 V, CANL = open, TXD = 0 V
115 mA
115 mA
–115
–115
–7
Short-circuit bus output current, dominant,
normal mode
IOS(DOM)
See 图7-7 and 图8-3 , V(CAN_L) = -15 V to
40 V, CANH = open, TXD = 0 V
See 图7-7 and 图8-3 , V(CANH) = -27 V to
32 V, CANL = open, STB=0, TXD = VIO
7
7
mA
mA
Short-circuit steady-state output current,
recessive, normal mode
IOS(REC)
See 图7-7 and 图8-3 , V(CANL) = -27 V to
32 V, CANH = open, STB = 0, TXD = VIO
–7
Receiver Electrical Characteristics
See 图7-3 and 表8-6
-30 V ≤VCM ≤30 V, STB, SHDN= 0 V
VIT
Input threshold voltage normal mode
500
400
900 mV
See 图7-3 and 表8-6
-30 V ≤VCM ≤30 V, SHDN= 0 V, STB=
VIO
Input threshold standby mode, TCAN3414
Input threshold standby mode, TCAN3413
1150 mV
See 图7-3 and 表8-6
VIO = 3 V to 3.6 V, -30 V ≤VCM ≤30 V,
STB= VIO
VIT(STB)
400
400
1150 mV
1150 mV
See 图7-3 and 表8-6
VIO = 1.7 V to 1.9 V, 2.25 V to 2.75 V, -12
V ≤VCM ≤12 V, STB= VIO
Normal mode dominant state differential input
voltage range
See 图7-3 and 表8-6
-30 V ≤VCM ≤30 V, STB, SHDN= 0 V
VDOM
0.9
-4
9
V
V
Normal mode recessive state differential input
voltage range
See 图7-3 and 表8-6
-30 V ≤VCM ≤30 V, STB, SHDN= 0 V
VREC
0.5
See 图7-3 and 表8-6
SHDN= 0 V, STB = VIO, -30 V ≤VCM
30 V
Standby mode dominant state differential input
voltage range
VDOM(STB)
1.15
-4
9
V
≤
See 图7-3 and 表8-6
SHDN = 0 V, STB = VIO, -30 V ≤VCM
30 V
Standby mode recessive state differential input
voltage range
VREC(STB)
0.4
V
≤
Hysteresis voltage for input threshold normal
mode
See 图7-3 and 表8-6
-30 V ≤VCM ≤30 V, STB, SHDN= 0 V
VHYS
90
mV
Common mode range normal and standby
modes
VCM
30
5
V
See 图7-3 and 表8-6
–30
ILKG(IOFF)
CI
Unpowered bus input leakage current
Input capacitance to ground (CANH or CANL)
Differential input capacitance
CANH = CANL = 5 V, VCC = VIO = GND
µA
40 pF
20 pF
TXD = VIO
,
CID
RID
Differential input resistance
25
13
50
25
kΩ
kΩ
TXD = VIO, STB = 0 V -30 V ≤VCM ≤30
V, Delta V/Delta I
Single ended input resistance
(CANH or CANL)
RIN
Input resistance matching
[1 –(RIN(CANH) / RIN(CANL))] × 100 %
RIN(M)
V(CAN_H) = V(CAN_L) = 5 V
1
%
–1
TXD Terminal (CAN Transmit Data Input)
VIH
VIH
High-level input voltage
High-level input voltage
TCAN3414
TCAN3413
0.7 VCC
0.7 VIO
V
V
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6.8 Electrical Characteristics (continued)
parameters valid over recommended operating conditions with -40℃≤TJ ≤150℃(Typical values are at VCC = 3.3 V, VIO
3.3 V for TCAN3403, Device ambient maintained at 27℃) unless otherwise noted
=
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VIL
Low-level input voltage
TCAN3414
TCAN3413
0.3 VCC
0.3 VIO
1
V
VIL
Low-level input voltage
V
IIH
High-level input leakage current
Low-level input leakage current
Unpowered leakage current
Input capacitance
TXD = VCC = VIO = 3.6 V
0
-100
0
µA
µA
µA
pF
–2.5
–200
–1
IIL
TXD = 0 V, VCC = VIO = 3.6 V
TXD = 3.6 V, VCC = VIO = 0 V
–20
ILKG(OFF)
CI
1
6
RXD Terminal (CAN Receive Data Output)
TCAN3414
See 图7-3 , IO = –2 mA
VOH
VOH
VOL
High-level output voltage
High-level output voltage
Low-level output voltage
0.8 VCC
0.8 VIO
V
V
V
See 图7-3 , IO = –1.5 mA, TCAN3413
TCAN3414
See 图7-3 , IO = 2 mA
0.2 VCC
TCAN3413
See 图7-3 , IO = 1.5 mA
VOL
Low-level output voltage
0.2 VIO
1
V
ILKG(OFF)
Unpowered leakage current
RXD = 3.6 V, VCC = VIO = 0 V
0
µA
–1
STB Terminal (Standby Mode Input)
VIH
High-level input voltage
TCAN3414
0.7 VCC
0.7 VIO
V
V
VIH
High-level input voltage
TCAN3413
VIL
Low-level input voltage
TCAN3414
0.3 VCC
0.3 VIO
2
V
VIL
Low-level input voltage
TCAN3413
V
IIH
High-level input leakage current
Low-level input leakage current
Unpowered leakage current
VCC = VIO = STB = 3.6 V
VCC = VIO = 3.6 V, STB = 0 V
STB = 3.6V, VCC= VIO = 0 V
µA
µA
µA
–2
–20
–1
IIL
–2
ILKG(OFF)
0
1
SHDN Terminal (Shutdown mode input)
VIH
High-level input voltage
TCAN3414
0.7 VCC
V
V
VIL
Low-level input voltage
TCAN3414
0.3 VCC
IIH
High-level input leakage current
Low-level input leakage current
Unpowered leakage current
VCC = VIO = SHDN = 3.6 V
VCC = VIO = 3.6 V, SHDN = 0 V
SHDN = 3.6 V, VCC= VIO = 0 V
2
–2
–1
5.5 µA
IIL
2
1
µA
µA
ILKG(OFF)
0
6.9 Switching Characteristics
parameters valid over recommended operating conditions with -40℃≤TJ ≤150℃(Typical values are at VCC = 3.3 V, VIO
3.3 V for TCAN3403, Device ambient maintained at 27℃) unless otherwise noted
=
PARAMETER
TEST CONDITIONS
MIN
TYP
120
126
140
MAX
180
190
210
UNIT
Device Switching Characteristics
See 图7-4, normal mode, VCC = VIO = 3
V to 3.6 V, RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF
ns
TCAN3414, TCAN3413
See 图7-4 , normal mode, VCC = 3 to
3.6 V, VIO = 2.25 V to 2.75 V, RL = 60 Ω,
CL = 100 pF, CL(RXD) = 15 pF
TCAN3413
Total loop delay, driver input (TXD) to receiver
output (RXD), recessive to dominant
tPROP(LOOP1)
ns
See 图7-4 , normal mode, VCC = 3 to 3.6
V, VIO = 1.71 V to 1.89 V, RL = 60 Ω, CL
100 pF, CL(RXD) = 15 pF
TCAN3413
=
ns
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6.9 Switching Characteristics (continued)
parameters valid over recommended operating conditions with -40℃≤TJ ≤150℃(Typical values are at VCC = 3.3 V, VIO
3.3 V for TCAN3403, Device ambient maintained at 27℃) unless otherwise noted
=
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
See 图7-4 , normal mode, VCC = VIO = 3
V to 3.6 V, RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF
95
180
ns
TCAN3414, TCAN3413
See 图7-4 , normal mode, VCC = 3 to 3.6
Total loop delay, driver input (TXD) to receiver
output (RXD), dominant to recessive
V, VIO = 2.25 V to 2.75 V, RL = 60 Ω, CL
100 pF, CL(RXD) = 15 pF
TCAN3413
=
tPROP(LOOP2)
101
115
190
210
ns
ns
See 图7-4 , normal mode, VCC = 3 to 3.6
V, VIO = 1.71 V to 1.89 V, RL = 60 Ω, CL
100 pF, CL(RXD) = 15 pF
TCAN3413
=
See Figure8-5 in TCAN1044A datasheet
See 图7-5
Mode change time, from normal to standby or from
standby to normal
tMODE
tSHDN1
tSHDN2
30
40
µs
µs
µs
With TXD: low, Time from SHDN pin (low
to high edge 50%) to RXD going from
low to high 50%
Mode change time from normal mode to shutdown
mode
With TXD low, time from SHDN pin (high
to low edge 50%) to RXD going from
high to low 50%
Mode change time from shutdown mode to normal
mode
200
tWK_FILTER
Filter time for a valid wake-up pattern
Bus wake-up timeout value
0.5
0.8
1.8
6
µs
See 图8-5
tWK_TIMEOUT
ms
Driver Switching Characteristics
See 图7-2 , STB, SHDN = 0 V, RL = 60
Ω, CL = 100 pF, VCC = VIO = 3 V to 3.6 V
TCAN3414, TCAN3413
65
67
100
110
ns
ns
See 图7-2 ,STB, SHDN = 0 V, RL = 60
Ω, CL = 100 pF, VCC = 3 to 3.6 V, VIO
2.25 V to 2.75 V
=
Propagation delay time, low-to-high TXD edge to
driver recessive (dominant to recessive)
tprop(TxD-busrec)
TCAN3413
See 图7-2 ,STB, SHDN = 0 V, RL = 60
Ω, CL = 100 pF, VCC = 3 to 3.6 V, VIO
1.71 V to 1.89 V
TCAN3413
=
71
46
48
110
100
110
ns
ns
ns
See 图7-2 , STB, SHDN = 0 V, RL = 60
Ω, CL = 100 pF, VCC = VIO = 3 V to 3.6 V
TCAN3414, TCAN3413
See 图7-2 ,STB, SHDN = 0 V, RL = 60
Ω, CL = 100 pF, VCC = 3 to 3.6 V, VIO
2.25 V to 2.75 V
=
Propagation delay time, high-to-low TXD edge to
driver dominant (recessive to dominant)
tprop(TxD-busdom)
TCAN3413
See 图7-2 ,STB, SHDN = 0 V, RL = 60
Ω, CL = 100 pF, VCC = 3 to 3.6 V, VIO
1.71 V to 1.89 V
TCAN3413
=
53
110
28
ns
ns
, STB, SHDN = 0 V, RL = 60 Ω, CL = 100
pF, See 图7-2
tsk(p)
Pulse skew (|tprop(TxD-busrec) - tprop(TxD-busdom)|)
3.5
tR
tF
Differential output signal rise time
Differential output signal fall time
25
30
57
50
ns
ns
See 图7-2 , STB, SHDN = 0 V, RL = 60
Ω, CL = 100 pF
See 图7-6 , STB, SHDN = 0 V, RL = 60
Ω, CL = 100 pF
tTXD_DTO
Dominant timeout
1.2
4.0
ms
Receiver Switching Characteristics
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6.9 Switching Characteristics (continued)
parameters valid over recommended operating conditions with -40℃≤TJ ≤150℃(Typical values are at VCC = 3.3 V, VIO
3.3 V for TCAN3403, Device ambient maintained at 27℃) unless otherwise noted
=
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
See 图7-3 , STB, SHDN = 0 V,
CL(RXD) = 15 pF, VCC = VIO = 3 V to 3.6 V
TCAN3414, TCAN3413
55
90
ns
See 图7-3 , STB, SHDN = 0 V, CL(RXD)
15 pF, VCC = 3 to 3.6 V, VIO = 2.25 V to
2.75 V
=
Propagation delay time, bus recessive input to RXD
high output (dominant to recessive)
60
90
ns
tprop(busrec-RXD)
TCAN3413
See 图7-3 , STB, SHDN = 0 V, CL(RXD)
15 pF, VCC = 3 to 3.6 V, VIO = 1.71 V to
1.89 V
=
70
45
51
102
90
ns
ns
ns
TCAN3413
See 图7-3 , STB, SHDN = 0 V,
CL(RXD) = 15 pF, VCC = VIO = 3 V to 3.6 V
TCAN3414, TCAN3413
See 图7-3 , STB, SHDN = 0 V, CL(RXD)
15 pF, VCC = 3 to 3.6 V, VIO = 2.25 V to
2.75 V
=
Propagation delay time, bus dominant input to RXD
low output (recessive to dominant)
90
tprop(busdom-RXD)
TCAN3413
See 图7-3 , STB, SHDN = 0 V, CL(RXD)
15 pF, VCC = 3 to 3.6 V, VIO = 1.71 V to
1.89 V
=
60
100
ns
TCAN3413
tR
tF
RXD output signal rise time
RXD output signal fall time
8
7
25
28
ns
ns
See 图7-3 , STB, SHDN = 0 V
CL(RXD) = 15 pF
FD Timing Characteristics
Bit time on CAN bus output pins with tBIT(TXD) = 500
450
160
85
525
205
130
ns
ns
ns
ns
Bit time on CAN bus output pins with tBIT(TXD) = 200 See 图7-4 , STB, SHDN = 0 V, RL = 60
ns
tBIT(BUS)
Ω, CL = 100 pF, CL(RXD) = 15 pF
Bit time on CAN bus output pins with tBIT(TXD) = 125
ns(1)
Bit time on RXD output pins with tBIT(TXD) = 500 ns
Bit time on RXD output pins with tBIT(TXD) = 200 ns
Bit time on RXD output pins with tBIT(TXD) = 125 ns(1)
Receiver timing symmetry with tBIT(TXD) = 500 ns
Receiver timing symmetry with tBIT(TXD) = 200 ns
Receiver timing symmetry with tBIT(TXD) = 125 ns(1)
410
130
75
540
210
135
20
ns
ns
ns
ns
ns
ns
See 图7-4 , STB, SHDN = 0 V, RL = 60
Ω, CL = 100 pF, CL(RXD) = 15 pF
tBIT(RXD)
-50
-40
-40
See 图7-4 , STB, SHDN = 0 V, RL = 60
Ω, CL = 100 pF, CL(RXD) = 15 pF
ΔtREC = tBIT(RXD) - tBIT(BUS)
10
ΔtREC
10
(1) Min/Max limits based on characterization.
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7 Parameter Measurement Information
CANH
TXD
RL
CL
CANL
图7-1. ICC Test Circuit
CANH
RL
50%
50%
TXD
TXD
CL
VOD
VCC
VO(CANH)
tpLD
tpHR
0 V
CANL
90%
10%
0.9 V
VO(CANL)
VOD
0.5 V
tR
tF
图7-2. Driver Test Circuit and Measurement
CANH
1.5V
0.9V
VID
IO
RXD
0.5V
0V
VID
tpDL
tpRH
CL_RXD
VOH
VO
CANL
90%
VO(RXD)
50%
10%
VOL
tF
tR
图7-3. Receiver Test Circuit and Measurement
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TXD
VI
70%
tLOOP1
30%
30%
CANH
0 V
TXD
VI
RL
CL
tBIT(TXD)
5 x tBIT(TXD)
CANL
tBIT(BUS)
STB
0 V
900 mV
500 mV
RXD
+
VDIFF
VO
CL_RXD
œ
RXD
VOH
70%
30%
VOL
tBIT(RXD)
tLOOP2
图7-4. Transmitter and Receiver Timing Test Circuit and Measurement
CANH
VIH
TXD
STB
CL
0V
RL
STB
50%
CANL
VI
0V
tMODE
RXD
VOH
VO
CL_RXD
RXD
50%
VOL
图7-5. tMODE Test Circuit and Measurement
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VIH
CANH
TXD
TXD
0V
RL
CL
VOD
VOD(D)
CANL
0.9V
VOD
0.5V
0V
tTXD_DTO
图7-6. TXD Dominant Timeout Test Circuit and Measurement
200 ꢀs
IOS
CANH
TXD
VBUS
IOS
CANL
VBUS
VBUS
0V
or
0V
VBUS
VBUS
图7-7. Driver Short-Circuit Current Test and Measurement
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8 Detailed Description
8.1 Overview
The TCAN341x devices are 3.3 V CAN FD transceivers with robust EMC performance. The devices are data
rate agnostic making them backward compatible for supporting classical CAN applications while also supporting
CAN FD networks up to 8 Mbps. The devices have standby mode support which puts the transceiver in low
current consumption mode. Upon receiving valid wake-up pattern on CAN bus, the device signals to the micro-
controller through the RXD pin. The MCU can then place the device in normal mode using STB pin.
TCAN3414 supports ultra-low power shutdown mode where most of the internal blocks are disabled. This
feature is optimized for battery-powered applications. TCAN3413 supports VIO pin for low voltage logic level
interface. It can be interfaced to 1.8 V, 2.5 V or 3.3 V micro controllers.
8.2 Functional Block Diagram
VCC
3
SHDN or VIO
5
VCC or VIO
7
6
CANH
CANL
TSD
Dominant
time-out
TXD
STB
1
8
VCC or VIO
Shutdown
Mode Select
UVP
VCC or VIO
MUX
4
Logic Output
RXD
WUP Monitor
Low Power Receiver
2
GND
图8-1. Block Diagram
8.3 Feature Description
8.3.1 Pin Descripton
8.3.1.1 TXD
The TXD input is a logic-level signal from a CAN controller to the transceiver. The signal is referenced to VCC for
the TCAN3414, or to VIO for the TCAN3413.
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8.3.1.2 GND
GND is the ground pin of the transceiver. The pin must be connected to the PCB ground.
8.3.1.3 VCC
VCC provides the 3.3 V power supply to the CAN transceiver.
8.3.1.4 RXD
The RXD output is a logic-level signal from the CAN transceiver to the CAN controller. The signal is referenced
to VCC for TCAN3414 and VIO for TCAN3413. For TCAN3413, the pin is only driven once VIO is present.
When a CAN bus wake-up event takes place, RXD is driven low.
8.3.1.5 VIO (TCAN3413 only)
The VIO pin provides the digital I/O voltage to match the CAN controller voltage thus avoiding the requirement for
a level shifter. It supports voltages from 1.7 V to 3.6 V providing a wide range of controller support.
8.3.1.6 CANH and CANL
The CANH and CANL pins are the CAN high and CAN low differential bus pins. These pins are internally
connected to the CAN transmitter, receiver and the low-power wake-up receiver.
8.3.1.7 STB (Standby)
The STB pin is an input pin used for mode control of the transceiver. The STB pin can be supplied from either
the system processor or from a static system voltage source. STB pin has default pull-up resistor on-chip. So if
the pin is left floating or pulled high externally, device is in standby mode. If normal mode is the only intended
mode of operation, the STB pin can be tied directly to GND.
8.3.2 CAN Bus States
The CAN bus has two logical states during operation: recessive and dominant. See 图8-2 and 图8-3.
A dominant bus state occurs when the bus is driven differentially and corresponds to a logic low on the TXD and
RXD pins. A recessive bus state occurs when the bus is biased to approximately VCC/2 via the high-resistance
internal input resistors (RIN) of the receiver and corresponds to a logic high on the TXD and RXD pins.
A dominant state overwrites the recessive state during arbitration. Multiple CAN nodes may be transmitting a
dominant bit at the same time during arbitration, and in this case, the differential voltage of the bus is greater
than the differential voltage of a single driver.
The TCAN341x transceivers implement a low-power standby (STB) mode which enables a third bus state where
the bus pins are weakly biased to ground via the high resistance internal resistors of the receiver. See 图8-2 and
图8-3.
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Normal Mode
Standby Mode
CANH
1.9 V
VDIFF
VDIFF
CANL
Recessive
Dominant
Recessive
Time, t
图8-2. Bus States
CANH
1.9 V
GND
A
B
RXD
Bias
Unit
CANL
A. A - Normal Mode B - Standby Mode
图8-3. Simplified Recessive Common Mode Bias Unit and Receiver
8.3.3 TXD Dominant Timeout (DTO)
During normal mode, the only mode where the CAN driver is active, the TXD DTO circuit prevents the local node
from blocking network communication in the event of a hardware or software failure where TXD is held dominant
longer than the timeout period tTXD_DTO. The TXD DTO circuit is triggered by a falling edge on TXD. If no rising
edge is seen before the timeout period of the circuit, tTXD_DTO, the CAN driver is disabled. This frees the bus for
communication between other nodes on the network. The CAN driver is reactivated when a recessive signal is
seen on the TXD pin, thus clearing the dominant time out. The receiver remains active and biased to
approximately 1.9 V and the RXD output reflects the activity on the CAN bus during the TXD DTO fault.
The minimum dominant TXD time allowed by the TXD DTO circuit limits the minimum possible transmitted data
rate of the device. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD) for the
worst case, where five successive dominant bits are followed immediately by an error frame. The minimum
transmitted data rate may be calculated using 方程式1 .
Minimum Data Rate = 11 bits / tTXD_DTO = 11 bits / 1.2 ms = 9.2 kbps
(1)
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Fault is repaired & transmission capability
restored
TXD fault stuck dominant: example PCB failure or bad software
tTXD_DTO
TXD (driver)
Driver disabled freeing bus for other nodes
Normal CAN communication
Bus would be —stuck dominant“ blocking communication for the whole network but TXD DTO
prevents this and frees the bus for communication after the time tTXD_DTO
.
CAN Bus Signal
tTXD_DTO
Communication from other bus node(s)
Communication from repaired node
RXD (receiver)
Communication from local node
Communication from other bus node(s)
Communication from repaired local node
图8-4. Example Timing Diagram for TXD Dominant Timeout
8.3.4 CAN Bus short-circuit current limiting
The devices have several protection features that limit the short-circuit current when a CAN bus line is shorted.
These include CAN driver current limiting in the dominant and recessive states, and TXD dominant state timeout
which prevents permanently having the higher short-circuit current of a dominant state in case of a system fault.
During CAN communication the bus switches between the dominant and recessive states, thus the short-circuit
current may be viewed as either the current during each bus state or as a DC average current. When selecting
termination resistors or a common-mode choke for the CAN design the average power rating, IOS(AVG), should be
used. The percentage dominant is limited by the TXD DTO and the CAN protocol which has forced state
changes and recessive bits due to bit stuffing, control fields, and interframe space. This makes sure there is a
minimum amount of recessive time on the bus even if the data field contains a high percentage of dominant bits.
The average short-circuit current of the bus depends on the ratio of recessive to dominant bits and their
respective short-circuit currents. The average short-circuit current may be calculated using 方程式2.
IOS(AVG) = % Transmit x [(% REC_Bits x IOS(SS)_REC) + (% DOM_Bits x IOS(SS)_DOM)] + [% Receive x IOS(SS)_REC
]
(2)
Where:
• IOS(AVG) is the average short-circuit current
• % Transmit is the percentage the node is transmitting CAN messages
• % Receive is the percentage the node is receiving CAN messages
• % REC_Bits is the percentage of recessive bits in the transmitted CAN messages
• % DOM_Bits is the percentage of dominant bits in the transmitted CAN messages
• IOS(SS)_REC is the recessive steady state short-circuit current
• IOS(SS)_DOM is the dominant steady state short-circuit current
The short circuit current and the possible fault cases of the network should be taken into consideration when
sizing the power supply used to generate the transceivers VCC supply.
8.3.5 Thermal Shutdown (TSD)
If the junction temperature of the devices exceed the thermal shutdown threshold, TTSD, the device turns off the
CAN driver circuitry and blocks the TXD to bus transmission path. The shutdown condition is cleared when the
junction temperature of the device drops below TTSD. The CAN bus pins are biased to ~ 1.9 V during a TSD fault
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and the receiver to RXD path remains operational. The TCAN341x TSD circuit includes hysteresis which
prevents the CAN driver output from oscillating during a TSD fault.
8.3.6 Undervoltage Lockout
The supply pins, VCC and VIO, have undervoltage detection that places the device into a protected state. This
protects the bus during an undervoltage event on either supply pin.
表8-1. Undervoltage Lockout - TCAN3414
VCC
DEVICE STATE
BUS
RXD PIN
Normal if STB = GND and SHDN
= GND
> UVVCC
> UVVCC
Per TXD
Mirrors bus
Standby mode if STB = High and
SHDN = GND
Weak biased to GND
VCC, Remote wake request
See Remote Wake Request via
Wake-Up Pattern (WUP) in
Standby Mode
> UVVCC
< UVVCC
Shutdown mode if SHDN = High
Protected
Weak biased to GND
High impedance
VCC
High impedance
表8-2. Undervoltage Lockout - TCAN3413
VCC
VIO
DEVICE STATE
BUS
RXD PIN
> UVVCC
< UVVCC
> UVVIO
> UVVIO
Normal
Per TXD
Mirrors bus
STB = High: Standby Mode
Weak biased to GND
VIO: Remote wake request
See Remote Wake Request via
Wake-Up Pattern (WUP) in Standby
Mode
STB =Low: Protected Mode
Protected
High impedance
High impedance
High impedance
Recessive
> UVVCC
< UVVCC
< UVVIO
< UVVIO
High impedance
High impedance
Protected
Once the undervoltage condition is cleared and tMODE or tSHDN2 has expired, the TCAN341x transitions to normal
mode. The host controller again sends and receives CAN traffic.
8.3.7 Unpowered Device
For unpowered conditions, the TCAN341x is designed to be a passive or no load to the CAN bus. This is
because the bus pins were designed to have low leakage currents to not load the bus. This design consideration
is critical if some nodes of the network are unpowered while the rest of the network remains operational.
For unpowered scenario, the logic pins also have low leakage currents so they do not load other circuits which
may remain powered.
8.3.8 Floating pins
The TCAN341x devices have internal pull-up/pull-down resistors on critical pins which place the device into
known states if the pin floats. This internal bias should not be relied upon by design though, especially in noisy
environments, but instead should be considered a failsafe protection feature.
When a CAN controller supporting open-drain outputs is used, an adequate external pull-up resistor must be
chosen. This makes sure the TXD output of the CAN controller maintains acceptable bit time to the input of the
CAN transceiver. See 表8-3 for details on pin bias conditions.
表8-3. Pin Bias
Pin
Pull-up or Pull-down
Comment
Weakly biases TXD towards recessive to prevent bus blockage or
TXD DTO triggering
TXD
Pull-up
Weakly biases STB towards low-power standby mode to prevent
excessive system power
STB
Pull-up
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表8-3. Pin Bias (continued)
Pin
Pull-up or Pull-down
Comment
Weakly biases SHDN towards normal mode to allow normal
communication. SHDN pin has higher priority than STB for
TCAN3414.
SHDN
Pull-down
8.4 Device Functional Modes
8.4.1 Operating Modes
The TCAN341x has two main operating modes; normal mode and standby mode. Operating mode selection is
made by applying a high or low level to the STB pin. TCAN3414 has a third mode: shutdown activated through
SHDN pin. Pulling SHDN pin high disables most internal blocks and puts the device in lowest power
consumption mode.
表8-4. Operating Modes for STB pin
STB
High
Low
Device Mode
Driver
Disabled
Enabled
Receiver
RXD Pin
High (recessive) until valid WUP
is received
See Remote Wake Request via
Wake-Up Pattern (WUP) in
Standby Mode
Low current standby mode with
bus wake-up
Low-power receiver and bus
monitor enable
Normal Mode
Enabled
Mirrors bus state
8.4.2 Normal Mode
This is the normal operating mode of the TCAN341x. The CAN driver and receiver are fully operational and CAN
communication is bi-directional. The driver is translating a digital input on the TXD input to a differential output on
the CANH and CANL bus pins. The receiver is translating the differential signal from CANH and CANL to a
digital output on the RXD output.
8.4.3 Standby Mode
This is the low-power mode of the TCAN341x. The CAN driver and main receiver are switched off and bi-
directional CAN communication is not possible. The low-power receiver and bus monitor circuits are enabled to
allow for RXD wake-up requests via the CAN bus. A wake-up request is output to RXD as shown in Remote
Wake Request via Wake-Up Pattern (WUP) in Standby Mode. The local CAN protocol controller should monitor
RXD for transitions (high-to-low) and reactivate the device to normal mode by pulling the STB pin low. The CAN
bus pins are weakly pulled to GND in this mode; see See 图8-2 and 图8-3.
For TCAN3413 in standby mode, only the VIO supply is required; therefore, the VCC may be switched off for
additional system level current savings.
8.4.3.1 Remote Wake Request via Wake-Up Pattern (WUP) in Standby Mode
The TCAN341x devices support a remote wake-up request that is used to indicate to the host controller that the
bus is active and the node should return to normal operation.
The device uses the multiple filtered dominant wake-up pattern (WUP) from the ISO 11898-2:2016 standard to
qualify bus activity. Once a valid WUP has been received, the wake request is indicated to the controller by a
falling edge and low period corresponding to a filtered dominant on the RXD output of the device.
The WUP consists of a filtered dominant pulse, followed by a filtered recessive pulse, and finally by a second
filtered dominant pulse. The first filtered dominant initiates the WUP, and the bus monitor then waits on a filtered
recessive; other bus traffic does not reset the bus monitor. Once a filtered recessive is received the bus monitor
is waiting for a filtered dominant and again, other bus traffic does not reset the bus monitor. Immediately upon
reception of the second filtered dominant the bus monitor recognizes the WUP and drives the RXD output low
every time an additional filtered dominant signal is received from the bus.
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For a dominant or recessive to be considered filtered, the bus must be in that state for more than the tWK_FILTER
time. Due to variability in tWK_FILTER the following scenarios are applicable. Bus state times less than
tWK_FILTER(MIN) are never detected as part of a WUP and thus no wake request is generated. Bus state times
between tWK_FILTER(MIN) and tWK_FILTER(MAX) may be detected as part of a WUP and a wake-up request may be
generated. Bus state times greater than tWK_FILTER(MAX) are always detected as part of a WUP; therefore, a wake
request is always generated. See 图8-5 for the timing diagram of the wake-up pattern.
The pattern and tWK_FILTER time used for the WUP prevents noise and bus stuck dominant faults from causing
false wake-up requests while allowing any valid message to initiate a wake-up request.
The ISO 11898-2:2016 standard has defined times for a short and long wake-up filter time. The tWK_FILTER timing
for the device has been picked to be within the minimum and maximum values of both filter ranges. This timing
has been chosen such that a single bit time at 500 kbps, or two back-to-back bit times at 1 Mbps triggers the
filter in either bus state. Any CAN frame at 500 kbps or less would contain a valid WUP.
For an additional layer of robustness and to prevent false wake-ups, the device implements a wake-up timeout
feature. For a remote wake-up event to successfully occur, the entire WUP must be received within the timeout
value t ≤ tWK_TIMEOUT. If not, the internal logic is reset and the transceiver remains in its current state without
waking up. The full pattern must then be transmitted again, conforming to the constraints mentioned in this
section. See 图8-5 for the timing diagram of the wake-up pattern with wake timeout feature.
Bus Wake via RXD
Wake Up Pattern (WUP) received in t < tWK_Timeout
Request
Filtered
Dominant
Filtered
Dominant
Filtered
Recessive
Waiting for
Filtered
Dominant
Waiting for
Filtered
Recessive
Bus
Bus VDiff
RXD
≥ tWK_FILTER
≥ tWK_FILTER
≥ tWK_FILTER
≥ tWK_FILTER
Filtered Dominant RXD Output
Bus Wake Via RXD Requests
图8-5. Wake-Up Pattern (WUP) with tWK_TIMEOUT
8.4.4 Driver and Receiver Function
The TCAN341x logic I/O supports CMOS levels with respect to either VCC for 3.3-V systems (TCAN3414) or VIO
(TCAN3413) for compatibility with MCUs that support 1.8-V, 2.5-V, or 3.3-V systems.
表8-5. Driver Function Table
Bus Outputs
Device Mode
TXD Input(1)
Driven Bus State(2)
CANH
CANL
Low
High
Low
Dominant
Normal
High or open
High impedance
High impedance
High impedance
High impedance
High impedance
High impedance
Biased recessive
Biased to ground
Biased to ground
Standby
X
X
Shutdown
(1) X = irrelevant
(2) For bus state and bias See 图8-2 and 图8-3.
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表8-6. Receiver Function Table Normal and Standby Mode
Device Mode
Bus State
Dominant
Undefined
RXD Pin
Low
CAN Differential Inputs VID = VCANH –VCANL
VID ≥0.9 V
0.5 V < VID < 0.9 V
Undefined
Normal
Recessive
High
VID ≤0.5 V
Dominant
Undefined
Recessive
Open
VID ≥1.15 V
0.4 V < VID < 1.15 V
VID ≤0.4 V
High
Low if a remote wake event
Standby
Any
occurred See 图8-5
High
Open (VID ≈0 V)
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
The TCAN341x transceivers can be used in applications with a host controller or FPGA that includes the link
layer portion of the CAN protocol. 图 9-1 shows a typical configuration for 3.3-V controller applications. The bus
termination is shown for illustrative purposes.
9.2 Typical Application
VOUT
VIN
VIN
3.3 V Voltage
Regulator
3
VCC
7
VDD
CANH
8
5
STB
SHDN
TCAN3414
MCU
4
1
CAN FD
Controller
RXD
TXD
6
CANL
GND
Optional:
Terminating Node
Optional: Filtering,
Transient and ESD
图9-1. Transceiver Application Using 3.3-V I/O Connections
9.2.1 Design Requirements
9.2.1.1 CAN Termination
Termination may be a single 120-Ω resistor at each end of the bus, either on the cable or in a terminating node.
If filtering and stabilization of the common-mode voltage of the bus is desired then split termination may be used,
see 图 9-2. Split termination improves the electromagnetic emissions behavior of the network by filtering higher-
frequency common-mode noise that may be present on the differential signal lines.
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Standard Termination
Split Termination
CANH
CANH
RTERM/2
RTERM
TCAN Transceiver
TCAN Transceiver
CSPLIT
RTERM/2
CANL
CANL
图9-2. CAN Bus Termination Concepts
9.2.2 Detailed Design Procedures
9.2.2.1 Bus Loading, Length and Number of Nodes
A typical CAN application may have a maximum bus length of 40 meters and maximum stub length of 0.3 m.
However, with careful design, users can have longer cables, longer stub lengths, and many more nodes to a
bus. A high number of nodes requires a transceiver with high input impedance such as the TCAN341x.
Many CAN organizations and standards have scaled the use of CAN for applications outside the original ISO
11898-2 standard. The organizations made system level trade off decisions for data rate, cable length, and
parasitic loading of the bus. Examples of these CAN systems level specifications are ARINC 825, CANopen,
DeviceNet, SAE J2284, SAE J1939, and NMEA 2000.
A CAN network system design is a series of tradeoffs. In the ISO 11898-2:2016 specification the driver
differential output is specified with a bus load that can range from 50 Ω to 65 Ω where the differential output
must be greater than 1.5 V. The TCAN341x family is specified to meet the 1.5-V requirement down to 50 Ω and
is specified to meet 1.4-V differential output at 45-Ω bus load. The differential input resistance of the TCAN341x
is a minimum of 22 kΩ. If 55 TCAN341x transceivers are in parallel on a bus, this is equivalent to a 400-Ω
differential load in parallel with the nominal 60-Ω bus termination which gives a total bus load of approximately
52 Ω. Therefore, the TCAN341x family theoretically supports over 50 transceivers on a single bus segment.
However, for a CAN network design margin must be given for signal loss across the system and cabling,
parasitic loadings, timing, network imbalances, ground offsets, and signal integrity thus a practical maximum
number of nodes is often lower. Bus length may also be extended beyond 40 meters by careful system design
and data rate tradeoffs. For example, CANopen network design guidelines allow the network to be up to 1 km
with changes in the termination resistance, cabling, less than 64 nodes and significantly lowered data rate.
This flexibility in CAN network design is one of the key strengths of the various extensions and additional
standards that have been built on the original ISO 11898-2 CAN standard. However, when using this flexibility,
the CAN network system designer must take the responsibility of good network design to for robust network
operation.
See the application report SLLA270: Controller Area Network Physical layer requirements. This document
discusses in detail all system design physical layer parameters.
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Node 1
Node 2
Node 3
Node n
(with termination)
System Controller
System Controller
System Controller
System Controller
CAN FD
Controller
CAN FD
Controller
CAN FD
Controller
CAN FD
Controller
TCAN1043
RTERM
TCAN3413
TCAN1044A
TCAN3414
图9-3. Typical CAN Bus
9.3 System Examples
The TCAN341x CAN transceiver is typically used in applications with a host controller or FPGA that includes the
link layer portion of the CAN protocol. A 1.8-V or 2.5-V application is shown in 图 9-4. The bus termination is
shown for illustrative purposes.
VOUT
VIN
VIN
3.3 V Voltage
Regulator
3
VCC
7
CANH
8
STB
MCU
TCAN3413
VIN
4
1
CAN FD
Controller
RXD
TXD
6
1.8 V / 2.5 V
Regulator
CANL
VDD
GND
VIO
5
VOUT
Optional:
Terminating Node
Optional: Filtering,
Transient and ESD
图9-4. Typical Transceiver Application Using 1.8-V, 2.5-V I/O Connections
9.3.1 ISO 11898-2 Compatibility of TCAN341x Family of 3.3-V CAN Transceivers
9.3.1.1 Introduction
Many users value the low power consumption of operating their CAN transceivers from a 3.3-V supply. However,
some are concerned about the interoperability with 5 V supplied transceivers on the same bus. This section tries
to address those concerns.
9.3.1.2 Differential Signal
CAN is a differential bus where complementary signals are sent over two wires and the voltage difference
between the two wires defines the logical state of the bus. The differential CAN receiver monitors this voltage
difference and outputs the bus state with a single ended logic level output signal.
The CAN driver creates the differential voltage between CANH and CANL in the dominant state. The dominant
differential output of the TCAN341x is greater than 1.5 V and less than 3 V across a 60-Ωload as defined by the
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ISO 11898-2 standard. These are the same limiting values for 5 V supplied CAN transceivers. The bus
termination resistors drive the recessive bus state and not the CAN driver.
A CAN receiver is required to output a recessive state when less than 500 mV of differential voltage exists on the
bus, and a dominant state when more than 900 mV of differential voltage exists on the bus. The CAN receiver
must do this with common-mode input voltages from –12 V to 12 V. The TCAN341x device receivers meet and
exceed these receiver input specifications.
9.3.1.3 Common-Mode Signal
A common-mode signal is an average voltage of the two signal wires that the differential receiver rejects. The
common-mode signal comes from the CAN driver, ground noise, and coupled bus noise. The TCAN341x family
has the recessive bias voltage set to 1.9V. This is intentional to match the common mode of recessive output
with the common mode of dominant output signal from TCAN341x. Furthermore, TCAN341x has special design
techniques for optimum EMC performance in a heterogeneous bus consisting of TCAN341x and 5 V CAN
transceivers.
9.3.1.4 Interoperability of 3.3-V CAN in 5-V CAN Systems
The 3.3-V supplied TCAN341xx family of CAN transceivers are fully compatible with 5-V CAN transceivers. The
minimum differential output voltage is the same, and the receivers have the same input threshold specifications.
The only slight difference is in the recessive common mode output voltage which is little lower for 3.3-V CAN
transceiver than 5-V supplied transceiver. But this does not impact regular functionality. Furthermore, special
design techniques in TCAN341x provide optimum EMC performance in heterogeneous network consisting of
TCAN341x and 5 V supplied CAN transceivers.
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9.4 Power Supply Recommendations
The TCAN3414 transceiver is designed to operate with a main VCC input voltage supply range between 3 V and
3.6 V.
The TCAN3413 implements an I/O level shifting supply input, VIO, designed for a range between 1.8 V and 3.6
V.
Both the VCC and VIO inputs must be well regulated. In addition to the power supply filtering a decoupling
capacitance, typically 100 nF, should be placed near the CAN transceiver main VCC and VIO supply pins.
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9.5 Layout
Robust and reliable CAN node designs may require special layout techniques depending on the application and
design requirements. Since transient disturbances have high frequency content and a wide bandwidth, high-
frequency layout techniques should be applied during PCB design.
9.5.1 Layout Guidelines
• Place the protection and filtering circuitry close to the bus connector, J1, to prevent transients, ESD, and
noise from propagating onto the board. This layout example shows an optional transient voltage suppression
(TVS) diode, D1, which may be implemented if the system-level requirements exceed the specified rating of
the transceiver. This example also shows optional bus filter capacitors C4 and C5.
• Design the bus protection components in the direction of the signal path. Do not force the transient current to
divert from the signal path to reach the protection device.
• Decoupling capacitors should be placed as close as possible to the supply pins VCC and VIO of transceiver.
• Use at least two vias for supply and ground connections of bypass capacitors and protection devices to
minimize trace and via inductance.
备注
High-frequency current follows the path of least impedance and not the path of least resistance.
• This layout example shows how split termination could be implemented on the CAN node. The termination is
split into two resistors, R2 and R3, with the center or split tap of the termination connected to ground via
capacitor C3. Split termination provides common mode filtering for the bus. See 节9.2.1.1, and 节8.3.4 for
information on termination concepts and power ratings needed for the termination resistor(s).
9.5.2 Layout Example
µC V
R1
TXD
GND
VCC
STB
C4
STB
R2
R3
CANH
CANL
VIO
GND
VCC
C3
GND
Choke
C1
D1
J1
RXD
µC V
C2
C5
图9-5. Layout Example
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10 Device and Documentation Support
10.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
10.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
10.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
10.4 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
10.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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11.1 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
Reel
Diameter
(mm)
Reel
Width W1
(mm)
Package
Type
Package
Drawing
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
Device
Pins
SPQ
SOT-23-
THN
PTCAN3413DDFR
DDF
8
3000
180.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
PTCAN3413DRBR
PTCAN3413DR
VSON
SOIC
DRB
D
8
8
3000
2500
330.0
330.0
12.4
12.4
3.3
6.4
3.3
5.2
1.1
2.1
8.0
8.0
12.0
12.0
Q1
Q1
SOT-23-
THN
PTCAN3414DDFR
DDF
8
3000
180.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
PTCAN3414DRBR
PTCAN3414DR
VSON
SOIC
DRB
D
8
8
3000
2500
330.0
330.0
12.4
12.4
3.3
6.4
3.3
5.2
1.1
2.1
8.0
8.0
12.0
12.0
Q1
Q1
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TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
Device
Package Type
SOT-23-THN
VSON
Package Drawing Pins
SPQ
3000
3000
2500
3000
3000
2500
Length (mm) Width (mm)
Height (mm)
35.0
PTCAN3413DDFR
PTCAN3413DRBR
PTCAN3413DR
PTCAN3414DDFR
PTCAN3414DRBR
PTCAN3414DR
DDF
DRB
D
8
8
8
8
8
8
210.0
367.0
356.0
210.0
367.0
356.0
185.0
367.0
356.0
185.0
367.0
356.0
35.0
SOIC
35.0
SOT-23-THN
VSON
DDF
DRB
D
35.0
35.0
SOIC
35.0
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11.2 Mechanical Data
PACKAGE OUTLINE
D0008B
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
.041
[1.04]
4221445/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15], per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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Product Folder Links: TCAN3413 TCAN3414
English Data Sheet: SLLSFS8
TCAN3413, TCAN3414
ZHCSRW5 –MARCH 2023
www.ti.com.cn
EXAMPLE BOARD LAYOUT
D0008B
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.055)
[1.4]
8X (.061 )
[1.55]
SEE
DETAILS
SEE
DETAILS
SYMM
SYMM
1
1
8
8
8X (.024)
[0.6]
8X (.024)
[0.6]
SYMM
SYMM
(R.002 ) TYP
[0.05]
(R.002 )
[0.05]
TYP
5
5
4
4
6X (.050 )
[1.27]
6X (.050 )
[1.27]
(.213)
[5.4]
(.217)
[5.5]
HV / ISOLATION OPTION
.162 [4.1] CLEARANCE / CREEPAGE
IPC-7351 NOMINAL
.150 [3.85] CLEARANCE / CREEPAGE
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:6X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSDE
METAL
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221445/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008B
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
8X (.055)
[1.4]
SYMM
SYMM
1
1
8
8
8X (.024)
[0.6]
8X (.024)
[0.6]
SYMM
SYMM
(R.002 ) TYP
[0.05]
(R.002 )
[0.05]
TYP
5
5
4
4
6X (.050 )
[1.27]
6X (.050 )
[1.27]
(.217)
[5.5]
(.213)
[5.4]
HV / ISOLATION OPTION
.162 [4.1] CLEARANCE / CREEPAGE
IPC-7351 NOMINAL
.150 [3.85] CLEARANCE / CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:6X
4221445/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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Product Folder Links: TCAN3413 TCAN3414
English Data Sheet: SLLSFS8
TCAN3413, TCAN3414
ZHCSRW5 –MARCH 2023
www.ti.com.cn
PACKAGE OUTLINE
DDF0008A
SOT-23 - 1.1 mm max height
S
C
A
L
E
4
.
0
0
0
PLASTIC SMALL OUTLINE
C
2.95
2.65
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
6X 0.65
8
1
2.95
2.85
NOTE 3
2X
1.95
4
5
0.4
0.2
8X
0.1
C A
B
1.65
1.55
B
1.1 MAX
0.20
0.08
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.1
0.0
0 - 8
0.6
0.3
DETAIL A
TYPICAL
4222047/B 11/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
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Product Folder Links: TCAN3413 TCAN3414
English Data Sheet: SLLSFS8
TCAN3413, TCAN3414
ZHCSRW5 –MARCH 2023
www.ti.com.cn
EXAMPLE BOARD LAYOUT
DDF0008A
SOT-23 - 1.1 mm max height
PLASTIC SMALL OUTLINE
8X (1.05)
SYMM
1
8
8X (0.45)
SYMM
6X (0.65)
5
4
(R0.05)
TYP
(2.6)
LAND PATTERN EXAMPLE
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222047/B 11/2015
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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Product Folder Links: TCAN3413 TCAN3414
English Data Sheet: SLLSFS8
TCAN3413, TCAN3414
ZHCSRW5 –MARCH 2023
www.ti.com.cn
EXAMPLE STENCIL DESIGN
DDF0008A
SOT-23 - 1.1 mm max height
PLASTIC SMALL OUTLINE
8X (1.05)
SYMM
(R0.05) TYP
1
8
8X (0.45)
SYMM
6X (0.65)
5
4
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4222047/B 11/2015
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
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Product Folder Links: TCAN3413 TCAN3414
English Data Sheet: SLLSFS8
TCAN3413, TCAN3414
ZHCSRW5 –MARCH 2023
www.ti.com.cn
PACKAGE OUTLINE
VSON - 1 mm max height
DRB0008J
PLASTIC QUAD FLAT PACK- NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
0.1 MIN
(0.13)
SECTION A-A
TYPICAL
1 MAX
C
SEATING PLANE
0.05
0.00
0.08
C
1.75
1.55
(0.2) TYP
6X 0.65
(0.19)
4
5
SYMM
9
2.5
2.3
1.95
1
8
0.36
8X
0.26
0.1
0.05
PIN 1 ID
(OPTIONAL)
C
A B
SYMM
C
0.5
0.3
8X
4225036/A 06/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
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Product Folder Links: TCAN3413 TCAN3414
English Data Sheet: SLLSFS8
TCAN3413, TCAN3414
ZHCSRW5 –MARCH 2023
www.ti.com.cn
EXAMPLE BOARD LAYOUT
DRB0008F
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.6)
SYMM
8X (0.6)
1
8
8X (0.3)
(2.4)
(0.95)
6X (0.65)
4
5
(R0.05) TYP
(0.55)
( 0.2) VIA
TYP
(2.8)
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222121/C 10/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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Product Folder Links: TCAN3413 TCAN3414
English Data Sheet: SLLSFS8
TCAN3413, TCAN3414
ZHCSRW5 –MARCH 2023
www.ti.com.cn
EXAMPLE STENCIL DESIGN
VSON - 1 mm max height
DRB0008J
PLASTIC QUAD FLAT PACK- NO LEAD
(2.8)
2X
(1.51)
8X (0.6)
8X (0.31)
SYMM
1
8
2X
(1.06)
6X (0.65)
SYMM
(1.95)
(0.63)
9
(R0.05) TYP
4
5
METAL
TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
81% PRINTED COVERAGE BY AREA
SCALE: 20X
4225036/A 06/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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Product Folder Links: TCAN3413 TCAN3414
English Data Sheet: SLLSFS8
PACKAGE OPTION ADDENDUM
www.ti.com
2-Jul-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PTCAN3413DDFR
PTCAN3413DR
ACTIVE SOT-23-THIN
DDF
D
8
8
8
8
8
8
3000
2500
3000
3000
2500
3000
TBD
TBD
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
Samples
Samples
Samples
Samples
Samples
Samples
ACTIVE
ACTIVE
SOIC
SON
Call TI
Call TI
Call TI
Call TI
Call TI
PTCAN3413DRBR
PTCAN3414DDFR
PTCAN3414DR
DRB
DDF
D
ACTIVE SOT-23-THIN
ACTIVE
ACTIVE
SOIC
SON
PTCAN3414DRBR
DRB
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
2-Jul-2023
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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