PTMUX6219RQXR_技术文档

TMUX6219

ZHCSM12D –SEPTEMBER 2020 –REVISED AUGUST 2022

具有1.8V 逻辑电平的TMUX621936V、低Ron、2:1 (SPDT) 开关

1 特性

3 说明

• 双电源电压范围：±4.5 V 至±18 V

• 单电源电压范围：4.5V 至36V

• 低导通电阻：2.1 Ω

TMUX6219 是一款互补金属氧化物半导体 (CMOS) 开

关，采用单通道 2:1 (SPDT) 配置。此器件在单电源

（4.5V 至36V）、双电源（±4.5V 至±18V）或非对称

电源（例如V_DD= 5V，V_SS= −8V）供电时均能正常运

行。TMUX6219 可在源极 (Sx) 和漏极 (D) 引脚上支持

从V_SS到V_DD范围的双向模拟和数字信号。

• 低电荷注入：-10 pC

• 大电流支持：330 mA（最大值）(VSSOP)

• 大电流支持：440 mA（最大值）(WSON)

• –40°C 至+125°C 工作温度

• 兼容1.8 V 逻辑电平

• 失效防护逻辑

• 轨到轨运行

可以通过控制 EN 引脚来启用或禁用 TMUX6219。当

禁用时，两个信号路径开关都被关闭。当启用时，SEL

引脚可用于打开信号路径 1（S1 至 D）或信号路径 2

（S2 至 D）。所有逻辑控制输入均支持 1.8 V 到 V_DD

的逻辑电平，因此，当器件在有效电源电压范围内运行

时，可确保 TTL 和CMOS 逻辑兼容性。失效防护逻辑

电路允许先在控制引脚上施加电压，然后在电源引脚上

施加电压，从而保护器件免受潜在的损害。

• 双向信号路径

• 先断后合开关

2 应用

• 工厂自动化和工业控制

• 可编程逻辑控制器(PLC)

• 模拟输入模块

• 半导体测试

• 交流充电（桩）站

• 超声波扫描仪

• 患者监护和诊断

• 光纤网络

• 光学测试设备

• 远程无线电单元

• 有线网络

• 数据采集系统

• 燃气表

• 流量变送器

TMUX6219 是精密开关和多路复用器系列器件。这些

器件具有非常低的导通和关断泄漏电流以及较低的电荷

注入，因此可用于高精度测量应用。

器件信息⁽¹⁾

封装尺寸（标称值）

器件型号

TMUX6219

封装

VSSOP (8) (DGK)

WSON (8) (RQX)

3.00mm × 3.00mm

3.00mm × 2.00mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

V_SS

V_DD

S1

S2

D

Decoder

EN SEL

TMUX6219 方框图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SCDS420

TMUX6219

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ZHCSM12D –SEPTEMBER 2020 –REVISED AUGUST 2022

Table of Contents

7.7 t_{ON (VDD)}Time............................................................29

7.8 Propagation Delay.................................................... 29

7.9 Charge Injection........................................................30

7.10 Off Isolation.............................................................30

7.11 Crosstalk................................................................. 31

7.12 Bandwidth............................................................... 31

7.13 THD + Noise........................................................... 32

7.14 Power Supply Rejection Ratio (PSRR)...................32

8 Detailed Description......................................................33

8.1 Overview...................................................................33

8.2 Functional Block Diagram.........................................33

8.3 Feature Description...................................................33

8.4 Device Functional Modes..........................................35

8.5 Truth Tables.............................................................. 35

9 Application and Implementation..................................36

9.1 Application Information............................................. 36

9.2 Typical Application.................................................... 36

10 Power Supply Recommendations..............................37

11 Layout...........................................................................38

11.1 Layout Guidelines................................................... 38

11.2 Layout Example...................................................... 38

12 Device and Documentation Support..........................40

12.1 Documentation Support.......................................... 40

12.2 Receiving Notification of Documentation Updates..40

12.3 支持资源..................................................................40

12.4 Trademarks.............................................................40

12.5 Electrostatic Discharge Caution..............................40

12.6 术语表..................................................................... 40

13 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Thermal Information....................................................4

6.4 Recommended Operating Conditions.........................5

6.5 Source or Drain Continuous Current...........................5

6.6 ±15 V Dual Supply: Electrical Characteristics ............6

6.7 ±15 V Dual Supply: Switching Characteristics ...........7

6.8 36 V Single Supply: Electrical Characteristics ........... 9

6.9 36 V Single Supply: Switching Characteristics ........ 10

6.10 12 V Single Supply: Electrical Characteristics ....... 12

6.11 12 V Single Supply: Switching Characteristics .......13

6.12 +5 V / -8 V Dual Supply: Electrical

Characteristics ............................................................15

6.13 +5 V / -8 V Dual Supply: Switching

Characteristics ............................................................16

6.14 ±5 V Dual Supply: Electrical Characteristics ..........17

6.15 ±5 V Dual Supply: Switching Characteristics .........18

6.16 Typical Characteristics............................................20

7 Parameter Measurement Information..........................26

7.1 On-Resistance.......................................................... 26

7.2 Off-Leakage Current................................................. 26

7.3 On-Leakage Current................................................. 27

7.4 Transition Time......................................................... 27

7.5 t_ON(EN)and t_OFF(EN).................................................. 28

7.6 Break-Before-Make...................................................28

Information.................................................................... 40

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision C (June 2022) to Revision D (July 2022)

Page

• 将RQX 封装状态从预发布更改为正在供货...................................................................................................... 1

• Added +5 V / -8 V electrical and switching characteristics tables.....................................................................15

Changes from Revision B (January 2021) to Revision C (June 2022)

Page

• Added the RQX package details to the Pin Configuration and Functions section..............................................3

Changes from Revision A (October 2020) to Revision B (January 2021)

Page

• 将文档状态从预告信息更改为量产数据.............................................................................................................1

2

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ZHCSM12D –SEPTEMBER 2020 –REVISED AUGUST 2022

5 Pin Configuration and Functions

D

S1

1

2

3

4

8

7

6

5

S2

D

S1

1

2

3

4

8

7

6

5

S2

VSS

SEL

EN

Thermal

Pad

VSS

SEL

EN

GND

VDD

GND

VDD

Not to scale

图5-2. RQX Package,

8-Pin WSON

Not to scale

图5-1. DGK Package,

8-Pin VSSOP

(Top View)

表5-1. Pin Functions

DGK

1

TYPE⁽¹⁾

RQX

DESCRIPTION⁽²⁾

NAME

D

1

2

3

I/O

P

Drain pin. Can be an input or output.

Source pin 1. Can be an input or output.

Ground (0 V) reference

S1

2

GND

3

Positive power supply. This pin is the most positive power-supply potential. For reliable operation,

connect a decoupling capacitor ranging from 0.1 µF to 10 µF between V_DDand GND.

V_DD

4

P

Active high logic enable, has internal pull-up resistor. When this pin is low, all switches are turned off.

When this pin is high, the SEL logic input determine which switch is turned on.

EN

5

6

5

6

I

SEL

Logic control input, has internal pull-down resistor. Controls the switch connection as shown in 节8.5.

Negative power supply. This pin is the most negative power-supply potential. In single-supply

applications, this pin can be connected to ground. For reliable operation, connect a decoupling

capacitor ranging from 0.1 µF to 10 µF between V_SSand GND.

V_SS

7

8

7

8

P

S2

I/O

Source pin 2. Can be an input or output.

The thermal pad is not connected internally. It is recommended that the pad be tied to GND or VSS

for best performance.

Thermal Pad

—

(1) I = input, O = output, I/O = input and output, P = power.

(2) Refer to 节8.4 for what to do with unused pins.

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)^{(1) (2)}

MIN

MAX

UNIT

V

38

V_DD–V_SS

V_DD

Supply voltage

38

V

–0.5

–38

V_SS

0.5

V

V_SELor V_EN

I_SELor I_EN

V_Sor V_D

I_IK

Logic control input pin voltage (SEL, EN)⁽³⁾

Logic control input pin current (SEL, EN)⁽³⁾

Source or drain voltage (Sx, D)⁽³⁾

Diode clamp current⁽³⁾

38

V

–0.5

30

V_DD+0.5

30

mA

V

–30

V_SS–0.5

–30

mA

°C

I_Sor I_{D (CONT)}

T_A

Source or drain continuous current (Sx, D)

Ambient temperature

I_DC+ 10 %⁽⁴⁾

150

–55

–65

T_stg

Storage temperature

150

T_J

Junction temperature

150

Total power dissipation⁽⁵⁾

P_tot

460

mW

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) All voltages are with respect to ground, unless otherwise specified.

(3) Pins are diode-clamped to the power-supply rails. Over voltage signals must be voltage and current limited to maximum ratings.

(4) Refer to Source or Drain Continuous Current table for I_DCspecifications.

(5) For DGK package: P_totderates linearily above T_A= 70°C by 6.7mW/°C.

6.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/

JEDEC JS-001, all pins⁽¹⁾

±2000

V_(ESD)

Electrostatic discharge

V

Charged device model (CDM), per JEDEC

specification JESD22-C101, all pins⁽²⁾

±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Thermal Information

TMUX6219

DGK (VSSOP)

8 PINS

152.1

TMUX6219

RQX (WSON)

8 PINS

62.9

THERMAL METRIC⁽¹⁾

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

48.4

54.0

73.2

31.0

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

4.1

0.8

Ψ_JT

71.8

30.9

Ψ_JB

R_θJC(bot)

N/A

23.4

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

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6.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

4.5

V_SS

0

NOM

MAX

36

UNIT

V

(1)

Power supply voltage differential

V_DD–V_SS

V_DD

Positive power supply voltage

36

V

V_Sor V_D

V_SELor V_EN

I_Sor I_{D (CONT)}

T_A

Signal path input/output voltage (source or drain pin) (Sx, D)

Address or enable pin voltage

V_DD

36

V

(2)

Source or drain continuous current (Sx, D)

Ambient temperature

I_DC

mA

°C

125

–40

(1) V_DDand V_SScan be any value as long as 4.5 V ≤(V_DD–V_SS) ≤36 V, and the minimum V_DDis met.

(2) Refer to Source or Drain Continuous Current table for I_DCspecifications.

6.5 Source or Drain Continuous Current

at supply voltage of V_DD± 10%, V_SS± 10 % (unless otherwise noted)

CONTINUOUS CURRENT PER CHANNEL (I_DC

PACKAGE TEST CONDITIONS

±15 V Dual Supply

)

T_A= 25°C

T_A= 85°C

270

T_A= 125°C

UNIT

440

130

mA

+36 V Single Supply⁽¹⁾

+12 V Single Supply

±5 V Dual Supply

440

330

230

330

300

240

180

270

200

140

210

190

160

120

130

105

90

RQX (WSON)

DGK (VSSOP)

+5 V Single Supply

±15 V Dual Supply

+36 V Single Supply⁽¹⁾

+12 V Single Supply

±5 V Dual Supply

120

110

100

80

+5 V Single Supply

(1) Specified for nominal supply voltage only.

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MAX UNIT

ZHCSM12D –SEPTEMBER 2020 –REVISED AUGUST 2022

6.6 ±15 V Dual Supply: Electrical Characteristics

V_DD= +15 V ± 10%, V_SS= –15 V ±10%, GND = 0 V (unless otherwise noted)

Typical at V_DD= +15 V, V_SS= –15 V, T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

ANALOG SWITCH

25°C

2.1

2.9

3.8

Ω

V_S= –10 V to +10 V

I_D= –10 mA

Refer to On-Resistance

R_ON

On-resistance

–40°C to +85°C

–40°C to +125°C

25°C

4.5

0.05

0.5

0.25

0.3

V_S= –10 V to +10 V

I_D= –10 mA

Refer to On-Resistance

On-resistance mismatch between

channels

–40°C to +85°C

–40°C to +125°C

25°C

ΔR_ON

0.35

0.6

V_S= –10 V to +10 V

I_S= –10 mA

Refer to On-Resistance

0.7

R_{ON FLAT}On-resistance flatness

R_{ON DRIFT}On-resistance drift

–40°C to +85°C

–40°C to +125°C

0.85

V_S= 0 V, I_S= –10 mA

Refer to On-Resistance

0.01

0.05

–40°C to +125°C

Ω/°C

25°C

0.2

1.6

nA

V_DD= 16.5 V, V_SS= –16.5 V

Switch state is off

V_S= +10 V / –10 V

–0.2

–1.6

–40°C to +85°C

I_S(OFF)

Source off leakage current⁽¹⁾

V_D= –10 V / + 10 V

Refer to Off-Leakage Current

40

nA

–40°C to +125°C

–40

25°C

0.05

0.04

1

3

nA

V_DD= 16.5 V, V_SS= –16.5 V

Switch state is off

V_S= +10 V / –10 V

V_D= –10 V / + 10 V

Refer to Off-Leakage Current

–1

–3

–40°C to +85°C

I_D(OFF)

Drain off leakage current⁽¹⁾

60

nA

–40°C to +125°C

–60

25°C

1

2

nA

–1

–2

V_DD= 16.5 V, V_SS= –16.5 V

Switch state is on

V_S= V_D= ±10 V

I_S(ON)

I_D(ON)

Channel on leakage current⁽²⁾

–40°C to +85°C

–40°C to +125°C

Refer to On-Leakage Current

50

–50

LOGIC INPUTS (SEL / EN pins)

V_IH

V_IL

I_IH

Logic voltage high

1.3

0

36

0.8

1

V

–40°C to +125°C

Logic voltage low

V

Input leakage current

Logic input capacitance

0.005

µA

pF

I_IL

–1 –0.005

C_IN

3

POWER SUPPLY

25°C

30

3

40

48

62

10

15

25

µA

V_DD= 16.5 V, V_SS= –16.5 V

Logic inputs = 0 V, 5 V, or V_DD

I_DD

V_DDsupply current

–40°C to +85°C

–40°C to +125°C

25°C

V_DD= 16.5 V, V_SS= –16.5 V

Logic inputs = 0 V, 5 V, or V_DD

I_SS

V_SSsupply current

–40°C to +85°C

–40°C to +125°C

(1) When V_Sis positive, V_Dis negative, or when V_Sis negative, V_Dis positive.

(2) When V_Sis at a voltage potential, V_Dis floating, or when V_Dis at a voltage potential, V_Sis floating.

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6.7 ±15 V Dual Supply: Switching Characteristics

V_DD= +15 V ± 10%, V_SS= –15 V ±10%, GND = 0 V (unless otherwise noted)

Typical at V_DD= +15 V, V_SS= –15 V, T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

MAX UNIT

25°C

120

175

190

210

170

185

200

180

195

210

ns

ms

V_S= 10 V

R_L= 300 Ω, C_L= 35 pF

Refer to Transition Time

t_TRAN

Transition time from control input

–40°C to +85°C

–40°C to +125°C

25°C

V_S= 10 V

100

50

R_L= 300 Ω, C_L= 35 pF

Refer to Turn-on and Turn-off

Time

t_ON

Turn-on time from enable

Turn-off time from enable

Break-before-make time delay

–40°C to +85°C

–40°C to +125°C

25°C

(EN)

V_S= 10 V

R_L= 300 Ω, C_L= 35 pF

Refer to Turn-on and Turn-off

Time

t_OFF

–40°C to +85°C

–40°C to +125°C

25°C

(EN)

V_S= 10 V,

R_L= 300 Ω, C_L= 35 pF

Refer to Break-Before-Make

1

t_BBM

–40°C to +85°C

–40°C to +125°C

25°C

0.19

0.2

V_DDrise time = 100 ns

R_L= 300 Ω, C_L= 35 pF

Refer to Turn-on (VDD) Time

Device turn on time

(V_DDto output)

T_{ON (VDD)}

–40°C to +85°C

–40°C to +125°C

0.2

R_L= 50 Ω, C_L= 5 pF

Refer to Propagation Delay

t_PD

Propagation delay

Charge injection

25°C

700

ps

V_D= 0 V, C_L= 1 nF

Refer to Charge Injection

Q_INJ

pC

–10

R_L= 50 Ω, C_L= 5 pF

V_S= 0 V, f = 100 kHz

Refer to Off Isolation

O_ISO

Off-isolation

Crosstalk

25°C

dB

–75

–55

R_L= 50 Ω, C_L= 5 pF

V_S= 0 V, f = 1 MHz

Refer to Off Isolation

O_ISO

R_L= 50 Ω, C_L= 5 pF

V_S= 0 V, f = 100 kHz

Refer to Crosstalk

X_TALK

–117

–106

R_L= 50 Ω, C_L= 5 pF

V_S= 0 V, f = 1MHz

Refer to Crosstalk

X_TALK

Crosstalk

R_L= 50 Ω, C_L= 5 pF

V_S= 0 V

Refer to Bandwidth

BW

I_L

25°C

40

MHz

dB

–3dB Bandwidth

R_L= 50 Ω, C_L= 5 pF

V_S= 0 V, f = 1 MHz

Insertion loss

–0.18

V_PP= 0.62 V on V_DDand V_SS

R_L= 50 Ω, C_L= 5 pF,

f = 1 MHz

ACPSRR AC Power Supply Rejection Ratio

25°C

dB

%

–64

Refer to ACPSRR

V_PP= 15 V, V_BIAS= 0 V

R_L= 10 kΩ, C_L= 5 pF,

f = 20 Hz to 20 kHz

THD+N

Total Harmonic Distortion + Noise

0.0005

Refer to THD + Noise

C_S(OFF)

C_D(OFF)

Source off capacitance

Drain off capacitance

V_S= 0 V, f = 1 MHz

25°C

33

48

pF

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V_DD= +15 V ± 10%, V_SS= –15 V ±10%, GND = 0 V (unless otherwise noted)

Typical at V_DD= +15 V, V_SS= –15 V, T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

MAX UNIT

C_S(ON)

C_D(ON)

,

On capacitance

V_S= 0 V, f = 1 MHz

25°C

148

pF

8

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6.8 36 V Single Supply: Electrical Characteristics

V_DD= +36 V ± 10%, V_SS= 0 V, GND = 0 V (unless otherwise noted)

Typical at V_DD= +36 V, V_SS= 0 V, T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

MAX UNIT

ANALOG SWITCH

25°C

2.5

3.2

4.2

4.9

0.2

0.25

0.3

1

Ω

V_S= 0 V to 30 V

I_D= –10 mA

Refer to On-Resistance

R_ON

On-resistance

–40°C to +85°C

–40°C to +125°C

25°C

0.1

0.3

V_S= 0 V to 30 V

I_D= –10 mA

Refer to On-Resistance

On-resistance mismatch between

channels

–40°C to +85°C

–40°C to +125°C

25°C

ΔR_ON

V_S= 0 V to 30 V

I_S= –10 mA

Refer to On-Resistance

1.5

2

R_{ON FLAT}On-resistance flatness

R_{ON DRIFT}On-resistance drift

–40°C to +85°C

–40°C to +125°C

V_S= 18 V, I_S= –10 mA

Refer to On-Resistance

0.009

0.05

–40°C to +125°C

Ω/°C

V_DD= 39.6 V, V_SS= 0 V

Switch state is off

V_S= 30 V / 1 V

25°C

0.3

3.5

nA

–0.3

–3.5

–40°C to +85°C

I_S(OFF)

Source off leakage current⁽¹⁾

V_D= 1 V / 30 V

Refer to Off-Leakage Current

60

nA

–40°C to +125°C

–60

V_DD= 39.6 V, V_SS= 0 V

Switch state is off

V_S= 30 V / 1 V

V_D= 1 V / 30 V

Refer to Off-Leakage Current

25°C

0.05

1

nA

–1

6.2

–40°C to +85°C

–6.2

I_D(OFF)

Drain off leakage current⁽¹⁾

80

nA

–40°C to +125°C

–80

25°C

0.4

4.5

70

nA

V_DD= 39.6 V, V_SS= 0 V

Switch state is on

V_S= V_D= 30 V or 1 V

Refer to On-Leakage Current

–0.4

–4.5

–70

I_S(ON)

I_D(ON)

Channel on leakage current⁽²⁾

–40°C to +85°C

–40°C to +125°C

LOGIC INPUTS (SEL / EN pins)

V_IH

V_IL

I_IH

Logic voltage high

1.3

0

36

0.8

1

V

–40°C to +125°C

Logic voltage low

V

Input leakage current

Logic input capacitance

0.005

µA

pF

I_IL

–1 –0.005

C_IN

3

POWER SUPPLY

25°C

28

50

58

70

µA

V_DD= 39.6 V, V_SS= 0 V

Logic inputs = 0 V, 5 V, or V_DD

I_DD

V_DDsupply current

–40°C to +85°C

–40°C to +125°C

(1) When V_Sis 30 V, V_Dis 1 V, or when V_Sis 1 V, V_Dis 30 V.

(2) When V_Sis at a voltage potential, V_Dis floating, or when V_Dis at a voltage potential, V_Sis floating.

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ZHCSM12D –SEPTEMBER 2020 –REVISED AUGUST 2022

6.9 36 V Single Supply: Switching Characteristics

V_DD= +36 V ± 10%, V_SS= 0 V, GND = 0 V (unless otherwise noted)

Typical at V_DD= +36 V, V_SS= 0 V, T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

25°C

110

170

185

200

180

190

200

180

195

200

ns

ms

V_S= 18 V

R_L= 300 Ω, C_L= 35 pF

Refer to Transition Time

t_TRAN

Transition time from control input

–40°C to +85°C

–40°C to +125°C

25°C

V_S= 18 V

110

90

R_L= 300 Ω, C_L= 35 pF

Refer to Turn-on and Turn-off

Time

t_ON

Turn-on time from enable

Turn-off time from enable

Break-before-make time delay

–40°C to +85°C

–40°C to +125°C

25°C

(EN)

V_S= 18 V

R_L= 300 Ω, C_L= 35 pF

Refer to Turn-on and Turn-off

Time

t_OFF

–40°C to +85°C

–40°C to +125°C

25°C

(EN)

44

V_S= 18 V,

R_L= 300 Ω, C_L= 35 pF

Refer to Break-Before-Make

1

t_BBM

–40°C to +85°C

–40°C to +125°C

25°C

0.17

0.19

V_DDrise time = 100 ns

R_L= 300 Ω, C_L= 35 pF

Refer to Turn-on (VDD) Time

Device turn on time

(V_DDto output)

T_{ON (VDD)}

–40°C to +85°C

–40°C to +125°C

R_L= 50 Ω, C_L= 5 pF

Refer to Propagation Delay

t_PD

Propagation delay

Charge injection

25°C

920

ps

V_D= 18 V, C_L= 1 nF

Refer to Charge Injection

Q_INJ

pC

–13

R_L= 50 Ω, C_L= 5 pF

V_S= 6 V, f = 100 kHz

Refer to Off Isolation

O_ISO

Off-isolation

Crosstalk

25°C

dB

–75

–55

R_L= 50 Ω, C_L= 5 pF

V_S= 6 V, f = 1 MHz

Refer to Off Isolation

O_ISO

R_L= 50 Ω, C_L= 5 pF

V_S= 6 V, f = 100 kHz

Refer to Crosstalk

X_TALK

–117

–106

R_L= 50 Ω, C_L= 5 pF

V_S= 6 V, f = 1MHz

Refer to Crosstalk

X_TALK

Crosstalk

R_L= 50 Ω, C_L= 5 pF

V_S= 6 V,

Refer to Bandwidth

BW

I_L

25°C

38

MHz

dB

–3dB Bandwidth

R_L= 50 Ω, C_L= 5 pF

V_S= 6 V, f = 1 MHz

Insertion loss

–0.19

V_PP= 0.62 V on V_DDand V_SS

R_L= 50 Ω, C_L= 5 pF,

f = 1 MHz

ACPSRR AC Power Supply Rejection Ratio

25°C

dB

%

–60

Refer to ACPSRR

V_PP=18 V, V_BIAS= 18 V

R_L= 10 kΩ, C_L= 5 pF,

f = 20 Hz to 20 kHz

THD+N

Total Harmonic Distortion + Noise

0.0004

Refer to THD + Noise

C_S(OFF)

C_D(OFF)

Source off capacitance

Drain off capacitance

V_S= 6 V, f = 1 MHz

25°C

35

49

pF

10

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ZHCSM12D –SEPTEMBER 2020 –REVISED AUGUST 2022

V_DD= +36 V ± 10%, V_SS= 0 V, GND = 0 V (unless otherwise noted)

Typical at V_DD= +36 V, V_SS= 0 V, T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

MAX UNIT

C_S(ON),

C_D(ON)

On capacitance

V_S= 6 V, f = 1 MHz

25°C

146

pF

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ZHCSM12D –SEPTEMBER 2020 –REVISED AUGUST 2022

6.10 12 V Single Supply: Electrical Characteristics

V_DD= +12 V ± 10%, V_SS= 0 V, GND = 0 V (unless otherwise noted)

Typical at V_DD= +12 V, V_SS= 0 V, T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

ANALOG SWITCH

25°C

4.6

6

7.5

8.4

0.2

0.32

0.35

2

Ω

V_S= 0 V to 10 V

I_D= –10 mA

Refer to On-Resistance

R_ON

On-resistance

–40°C to +85°C

–40°C to +125°C

25°C

0.08

1.2

V_S= 0 V to 10 V

I_D= –10 mA

Refer to On-Resistance

On-resistance mismatch between

channels

–40°C to +85°C

–40°C to +125°C

25°C

ΔR_ON

V_S= 0 V to 10 V

I_S= –10 mA

Refer to On-Resistance

2.2

2.4

R_{ON FLAT}On-resistance flatness

R_{ON DRIFT}On-resistance drift

–40°C to +85°C

–40°C to +125°C

V_S= 6 V, I_S= –10 mA

Refer to On-Resistance

0.017

0.05

–40°C to +125°C

Ω/°C

V_DD= 13.2 V, V_SS= 0 V

Switch state is off

V_S= 10 V / 1 V

25°C

0.5

2

nA

–0.5

–2

–40°C to +85°C

I_S(OFF)

Source off leakage current⁽¹⁾

V_D= 1 V / 10 V

Refer to Off-Leakage Current

30

nA

–40°C to +125°C

–30

V_DD= 13.2 V, V_SS= 0 V

Switch state is off

V_S= 10 V / 1 V

V_D= 1 V / 10 V

Refer to Off-Leakage Current

25°C

0.05

0.5

3

nA

–0.5

–3

–40°C to +85°C

I_D(OFF)

Drain off leakage current⁽¹⁾

50

nA

–40°C to +125°C

–50

25°C

1.5

3

nA

V_DD= 13.2 V, V_SS= 0 V

Switch state is on

V_S= V_D= 10 V or 1 V

Refer to On-Leakage Current

–1.5

–3

I_S(ON)

I_D(ON)

Channel on leakage current⁽²⁾

–40°C to +85°C

–40°C to +125°C

40

–40

LOGIC INPUTS (SEL / EN pins)

V_IH

V_IL

I_IH

Logic voltage high

1.3

0

36

0.8

1

V

–40°C to +125°C

Logic voltage low

V

Input leakage current

Logic input capacitance

0.005

µA

pF

I_IL

–1 –0.005

C_IN

3

POWER SUPPLY

25°C

10

35

45

55

µA

V_DD= 13.2 V, V_SS= 0 V

Logic inputs = 0 V, 5 V, or V_DD

I_DD

V_DDsupply current

–40°C to +85°C

–40°C to +125°C

(1) When V_Sis 10 V, V_Dis 1 V, or when V_Sis 1 V, V_Dis 10 V.

(2) When V_Sis at a voltage potential, V_Dis floating, or when V_Dis at a voltage potential, V_Sis floating.

12

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ZHCSM12D –SEPTEMBER 2020 –REVISED AUGUST 2022

6.11 12 V Single Supply: Switching Characteristics

V_DD= +12 V ± 10%, V_SS= 0 V, GND = 0 V (unless otherwise noted)

Typical at V_DD= +12 V, V_SS= 0 V, T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

MAX UNIT

25°C

180

185

215

235

180

210

230

210

235

250

ns

ms

V_S= 8 V

R_L= 300 Ω, C_L= 35 pF

Refer to Transition Time

t_TRAN

Transition time from control input

–40°C to +85°C

–40°C to +125°C

25°C

V_S= 8 V

120

130

40

R_L= 300 Ω, C_L= 35 pF

Refer to Turn-on and Turn-off

Time

t_ON

Turn-on time from enable

Turn-off time from enable

Break-before-make time delay

–40°C to +85°C

–40°C to +125°C

25°C

(EN)

V_S= 8 V

R_L= 300 Ω, C_L= 35 pF

Refer to Turn-on and Turn-off

Time

t_OFF

–40°C to +85°C

–40°C to +125°C

25°C

(EN)

V_S= 8 V,

R_L= 300 Ω, C_L= 35 pF

Refer to Break-Before-Make

1

t_BBM

–40°C to +85°C

–40°C to +125°C

25°C

0.19

0.2

V_DDrise time = 100 ns

R_L= 300 Ω, C_L= 35 pF

Refer to Turn-on (VDD) Time

Device turn on time

(V_DDto output)

T_{ON (VDD)}

–40°C to +85°C

–40°C to +125°C

0.2

R_L= 50 Ω, C_L= 5 pF

Refer to Propagation Delay

t_PD

Propagation delay

Charge injection

25°C

740

ps

V_D= 6 V, C_L= 1 nF

Refer to Charge Injection

Q_INJ

pC

–6

R_L= 50 Ω, C_L= 5 pF

V_S= 6 V, f = 100 kHz

Refer to Off Isolation

O_ISO

Off-isolation

Crosstalk

25°C

dB

–75

–55

R_L= 50 Ω, C_L= 5 pF

V_S= 6 V, f = 1 MHz

Refer to Off Isolation

O_ISO

R_L= 50 Ω, C_L= 5 pF

V_S= 6 V, f = 100 kHz

Refer to Crosstalk

X_TALK

–117

–106

R_L= 50 Ω, C_L= 5 pF

V_S= 6 V, f = 1 MHz

Refer to Crosstalk

X_TALK

Crosstalk

R_L= 50 Ω, C_L= 5 pF

V_S= 6 V

Refer to Bandwidth

BW

I_L

25°C

42

MHz

dB

–3dB Bandwidth

R_L= 50 Ω, C_L= 5 pF

V_S= 6 V, f = 1 MHz

Insertion loss

–0.3

V_PP= 0.62 V on V_DDand V_SS

R_L= 50 Ω, C_L= 5 pF,

f = 1 MHz

ACPSRR AC Power Supply Rejection Ratio

25°C

dB

%

–65

Refer to ACPSRR

V_PP= 6 V, V_BIAS= 6 V

R_L= 10 kΩ, C_L= 5 pF,

f = 20 Hz to 20 kHz

THD+N

Total Harmonic Distortion + Noise

0.0009

Refer to THD + Noise

C_S(OFF)

C_D(OFF)

Source off capacitance

Drain off capacitance

V_S= 6 V, f = 1 MHz

25°C

38

56

pF

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ZHCSM12D –SEPTEMBER 2020 –REVISED AUGUST 2022

V_DD= +12 V ± 10%, V_SS= 0 V, GND = 0 V (unless otherwise noted)

Typical at V_DD= +12 V, V_SS= 0 V, T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

MAX UNIT

C_S(ON)

C_D(ON)

,

On capacitance

V_S= 6 V, f = 1 MHz

25°C

150

pF

14

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ZHCSM12D –SEPTEMBER 2020 –REVISED AUGUST 2022

6.12 +5 V / -8 V Dual Supply: Electrical Characteristics

V_DD= +5 V ± 10%, V_SS= –8 V ±10%, GND = 0 V (unless otherwise noted)

Typical at V_DD= +5 V, V_SS= –5 V, T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

MAX UNIT

ANALOG SWITCH

25°C

4.2

5.5

6.8

V_DD= +5 V, V_SS= –8 V

V_S= V_DDto V_SS

I_D= –10 mA

Refer to On-Resistance

Ω

R_ON

On-resistance

–40°C to +85°C

–40°C to +125°C

25°C

7.6

0.1

1

0.23

0.27

0.35

1.5

V_S= V_DDto V_SS

I_D= –10 mA

Refer to On-Resistance

On-resistance mismatch between

channels

–40°C to +85°C

–40°C to +125°C

25°C

ΔR_ON

V_S= V_DDto V_SS

I_D= –10 mA

Refer to On-Resistance

1.7

R_{ON FLAT}

On-resistance flatness

–40°C to +85°C

–40°C to +125°C

2

V_S= 0 V, I_S= –10 mA

Refer to On-Resistance

R_{ON DRIFT}On-resistance drift

0.019

0.1

–40°C to +125°C

Ω/°C

25°C

0.3

3

nA

V_DD= +5.5 V, V_SS= –8.8 V

Switch state is off

V_S= V_DD- 1 / V_SS+ 1

V_D= V_SS+ 1 / V_DD- 1

Refer to Off-Leakage Current

–0.3

–3

–40°C to +85°C

I_S(OFF)

Source off leakage current⁽¹⁾

50

nA

–40°C to +125°C

–50

25°C

0.1

0.5

3

nA

V_DD= +5.5 V, V_SS= –8.8 V

Switch state is off

V_S= V_DD- 1 / V_SS+ 1

V_D= V_SS+ 1 / V_DD- 1

Refer to Off-Leakage Current

–0.5

–3

–40°C to +85°C

I_D(OFF)

Drain off leakage current⁽¹⁾

55

nA

–40°C to +125°C

–55

25°C

0.5

3

nA

–0.5

–3

V_DD= +5.5 V, V_SS= –8.8 V

Switch state is on

V_S= V_D= V_DD- 1 / V_SS+ 1

Refer to On-Leakage Current

I_S(ON)

I_D(ON)

Channel on leakage current⁽²⁾

–40°C to +85°C

–40°C to +125°C

40

–40

LOGIC INPUTS (SEL / EN pins)

V_IH

V_IL

I_IH

Logic voltage high

1.3

0

44

0.8

1

V

–40°C to +125°C

Logic voltage low

V

Input leakage current

Logic input capacitance

0.005

µA

pF

I_IL

–1 –0.005

C_IN

3

POWER SUPPLY

25°C

24

1

30

37

42

5

µA

V_DD= +5.5 V, V_SS= –8.8 V

Logic inputs = 0 V, 5 V, or V_DD

I_DD

V_DDsupply current

–40°C to +85°C

–40°C to +125°C

25°C

V_DD= +5.5 V, V_SS= –8.8 V

Logic inputs = 0 V, 5 V, or V_DD

8

I_SS

V_SSsupply current

–40°C to +85°C

–40°C to +125°C

12

(1) When V_Sis positive, V_Dis negative, or when V_Sis negative, V_Dis positive.

(2) When V_Sis at a voltage potential, V_Dis floating, or when V_Dis at a voltage potential, V_Sis floating.

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ZHCSM12D –SEPTEMBER 2020 –REVISED AUGUST 2022

6.13 +5 V / -8 V Dual Supply: Switching Characteristics

V_DD= +5 V ± 10%, V_SS= –5 V ±10%, GND = 0 V (unless otherwise noted)

Typical at V_DD= +5 V, V_SS= –5 V, T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

MAX UNIT

25°C

180

190

220

240

180

215

240

220

245

270

ns

ms

V_S= 3 V

R_L= 300 Ω, C_L= 35 pF

Refer to Transition Time

t_TRAN

Transition time from control input

–40°C to +85°C

–40°C to +125°C

25°C

120

130

60

V_S= 3 V

t_ON

Turn-on time from enable

Turn-off time from enable

Break-before-make time delay

–40°C to +85°C

–40°C to +125°C

25°C

R_L= 300 Ω, C_L= 35 pF

Refer to Turn-on and Turn-off Time

(EN)

V_S= 3 V

t_OFF

–40°C to +85°C

–40°C to +125°C

25°C

R_L= 300 Ω, C_L= 35 pF

Refer to Turn-on and Turn-off Time

(EN)

V_S= 3 V,

R_L= 300 Ω, C_L= 35 pF

Refer to Break-Before-Make

1

t_BBM

–40°C to +85°C

–40°C to +125°C

25°C

0.19

V_DDrise time = 1us

R_L= 300 Ω, C_L= 35pF

Refer to Turn-on (VDD) Time

Device turn on time

(V_DDto output)

1

T_{ON (VDD)}

–40°C to +85°C

–40°C to +125°C

R_L= 50 Ω, C_L= 5 pF

Refer to Propagation Delay

t_PD

Propagation delay

Charge injection

25°C

650

14

ps

V_D= 0 V, C_L= 1 nF

Refer to Charge Injection

Q_INJ

pC

R_L= 50 Ω, C_L= 5 pF

V_S= 0 V, f = 100 kHz

Refer to Off Isolation

O_ISO

Off-isolation

Crosstalk

25°C

dB

–75

–55

–80

–70

R_L= 50 Ω, C_L= 5 pF

V_S= 0 V, f = 1 MHz

Refer to Off Isolation

O_ISO

R_L= 50 Ω, C_L= 5 pF

V_S= 0 V, f = 100 kHz

Refer to Crosstalk

X_TALK

R_L= 50 Ω, C_L= 5 pF

V_S= 0 V, f = 1MHz

Refer to Crosstalk

X_TALK

Crosstalk

R_L= 50 Ω, C_L= 5 pF

V_S= 0 V,

Refer to Bandwidth

BW

I_L

25°C

42

MHz

dB

–3dB Bandwidth

R_L= 50 Ω, C_L= 5 pF

V_S= 0 V, f = 1 MHz

Insertion loss

–0.3

V_PP= 0.62 V on V_DDand V_SS

R_L= 50 Ω, C_L= 5 pF,

f = 1 MHz

ACPSRR AC Power Supply Rejection Ratio

25°C

dB

%

–68

Refer to ACPSRR

V_PP= 5 V, V_BIAS= 0 V

R_L= 10 kΩ, C_L= 5 pF,

f = 20 Hz to 20 kHz

THD+N

Total Harmonic Distortion + Noise

0.001

Refer to THD + Noise

C_S(OFF)

C_D(OFF)

Source off capacitance

Drain off capacitance

V_S= 0 V, f = 1 MHz

25°C

36

53

pF

C_S(ON),

C_D(ON)

On capacitance

V_S= 0 V, f = 1 MHz

25°C

142

pF

16

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ZHCSM12D –SEPTEMBER 2020 –REVISED AUGUST 2022

6.14 ±5 V Dual Supply: Electrical Characteristics

V_DD= +5 V ± 10%, V_SS= –5 V ±10%, GND = 0 V (unless otherwise noted)

Typical at V_DD= +5 V, V_SS= –5 V, T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

MAX UNIT

ANALOG SWITCH

25°C

4

7.2

8.6

V_DD= +4.5 V, V_SS= –4.5 V

V_S= –4.5 V to +4.5 V

I_D= –10 mA

Ω

–40°C to +85°C

R_ON

On-resistance

10

0.3

–40°C to +125°C

25°C

Ω

Refer to On-Resistance

0.1

1.3

V_S= –4.5 V to +4.5 V

I_D= –10 mA

Refer to On-Resistance

On-resistance mismatch between

channels

0.35

0.4

–40°C to +85°C

–40°C to +125°C

25°C

ΔR_ON

2.2

V_S= –4.5 V to +4.5 V

I_D= –10 mA

Refer to On-Resistance

2.5

R_{ON FLAT}On-resistance flatness

R_{ON DRIFT}On-resistance drift

–40°C to +85°C

–40°C to +125°C

2.8

V_S= 0 V, I_S= –10 mA

Refer to On-Resistance

0.019

0.05

–40°C to +125°C

Ω/°C

25°C

0.3

1

nA

V_DD= +5.5 V, V_SS= –5.5 V

Switch state is off

V_S= +4.5 V / –4.5 V

–0.3

–1

–40°C to +85°C

I_S(OFF)

Source off leakage current⁽¹⁾

V_D= –4.5 V / + 4.5 V

Refer to Off-Leakage Current

30

nA

–40°C to +125°C

–30

25°C

0.05

0.4

3

nA

V_DD= +5.5 V, V_SS= –5.5 V

Switch state is off

V_S= +4.5 V / –4.5 V

V_D= –4.5 V / + 4.5 V

Refer to Off-Leakage Current

–0.4

–3

–40°C to +85°C

I_D(OFF)

Drain off leakage current⁽¹⁾

50

nA

–40°C to +125°C

–50

25°C

0.4

3

nA

–0.4

–3

V_DD= +5.5 V, V_SS= –5.5 V

Switch state is on

V_S= V_D= ±4.5 V

I_S(ON)

I_D(ON)

Channel on leakage current⁽²⁾

–40°C to +85°C

–40°C to +125°C

Refer to On-Leakage Current

40

–40

LOGIC INPUTS (SEL / EN pins)

V_IH

V_IL

I_IH

Logic voltage high

1.3

0

36

0.8

1

V

–40°C to +125°C

Logic voltage low

V

Input leakage current

Logic input capacitance

0.005

µA

pF

I_IL

–1 –0.005

C_IN

3

POWER SUPPLY

25°C

20

35

40

50

5

µA

V_DD= +5.5 V, V_SS= –5.5 V

Logic inputs = 0 V, 5 V, or V_DD

I_DD

V_DDsupply current

–40°C to +85°C

–40°C to +125°C

25°C

0.001

V_DD= +5.5 V, V_SS= –5.5 V

Logic inputs = 0 V, 5 V, or V_DD

8

I_SS

V_SSsupply current

–40°C to +85°C

–40°C to +125°C

15

(1) When V_Sis positive, V_Dis negative, or when V_Sis negative, V_Dis positive.

(2) When V_Sis at a voltage potential, V_Dis floating, or when V_Dis at a voltage potential, V_Sis floating.

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6.15 ±5 V Dual Supply: Switching Characteristics

V_DD= +5 V ± 10%, V_SS= –5 V ±10%, GND = 0 V (unless otherwise noted)

Typical at V_DD= +5 V, V_SS= –5 V, T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

25°C

300

400

490

550

300

350

380

280

330

350

ns

ms

V_S= 3 V

R_L= 300 Ω, C_L= 35 pF

Refer to Transition Time

t_TRAN

Transition time from control input

–40°C to +85°C

–40°C to +125°C

25°C

V_S= 3 V

220

210

50

R_L= 300 Ω, C_L= 35 pF

Refer to Turn-on and Turn-off

Time

t_ON

Turn-on time from enable

Turn-off time from enable

Break-before-make time delay

–40°C to +85°C

–40°C to +125°C

25°C

(EN)

V_S= 3 V

R_L= 300 Ω, C_L= 35 pF

Refer to Turn-on and Turn-off

Time

t_OFF

–40°C to +85°C

–40°C to +125°C

25°C

(EN)

V_S= 3 V,

R_L= 300 Ω, C_L= 35 pF

Refer to Break-Before-Make

1

t_BBM

–40°C to +85°C

–40°C to +125°C

25°C

0.19

V_DDrise time = 100 ns

R_L= 300 Ω, C_L= 35pF

Refer to Turn-on (VDD) Time

Device turn on time

(V_DDto output)

1

T_{ON (VDD)}

–40°C to +85°C

–40°C to +125°C

R_L= 50 Ω, C_L= 5 pF

Refer to Propagation Delay

t_PD

Propagation delay

Charge injection

25°C

650

ps

V_D= 0 V, C_L= 1 nF

Refer to Charge Injection

Q_INJ

pC

–5

R_L= 50 Ω, C_L= 5 pF

V_S= 0 V, f = 100 kHz

Refer to Off Isolation

O_ISO

Off-isolation

Crosstalk

25°C

dB

–75

–55

R_L= 50 Ω, C_L= 5 pF

V_S= 0 V, f = 1 MHz

Refer to Off Isolation

O_ISO

R_L= 50 Ω, C_L= 5 pF

V_S= 0 V, f = 100 kHz

Refer to Crosstalk

X_TALK

–117

–106

R_L= 50 Ω, C_L= 5 pF

V_S= 0 V, f = 1 MHz

Refer to Crosstalk

X_TALK

Crosstalk

R_L= 50 Ω, C_L= 5 pF

V_S= 0 V,

Refer to Bandwidth

BW

I_L

25°C

43

MHz

dB

–3dB Bandwidth

R_L= 50 Ω, C_L= 5 pF

V_S= 0 V, f = 1 MHz

Insertion loss

–0.35

V_PP= 0.62 V on V_DDand V_SS

R_L= 50 Ω, C_L= 5 pF,

f = 1 MHz

ACPSRR AC Power Supply Rejection Ratio

25°C

dB

%

–68

Refer to ACPSRR

V_PP= 5 V, V_BIAS= 0 V

R_L= 10 kΩ, C_L= 5 pF,

f = 20 Hz to 20 kHz

THD+N

Total Harmonic Distortion + Noise

0.001

Refer to THD + Noise

C_S(OFF)

C_D(OFF)

Source off capacitance

Drain off capacitance

V_S= 0 V, f = 1 MHz

25°C

40

60

pF

18

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V_DD= +5 V ± 10%, V_SS= –5 V ±10%, GND = 0 V (unless otherwise noted)

Typical at V_DD= +5 V, V_SS= –5 V, T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

MAX UNIT

C_S(ON),

C_D(ON)

On capacitance

V_S= 0 V, f = 1 MHz

25°C

150

pF

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6.16 Typical Characteristics

at T_A= 25°C

4

V_DD= 18 V, V_SS= –18 V

V_DD= 15 V, V_SS= –15 V

V_DD= 13.5 V, V_SS= −13.5 V

3.5

3

2.5

2

1.5

1

-20

-15

-10

-5

0

5

10

15

20

V_Sor V_D- Source or Drain Voltage (V)

图6-1. On-Resistance vs Source or Drain Voltage –Dual

图6-2. On-Resistance vs Source or Drain Voltage –Dual

Supply

5

V_DD= 36 V, V_SS= 0 V

V_DD= 24 V, V_SS= 0 V

V_DD= 18 V, V_SS= 0 V

4

3

2

1

0

4

8

12

16

20

24

28

32

36

V_Sor V_D- Source or Drain Voltage (V)

图6-4. On-Resistance vs Source or Drain Voltage –Single

图6-3. On-Resistance vs Source or Drain Voltage –Single

Supply

12

T_A= 125C

T_A= 85C

11

T_A= 25C

T_A= -40C

10

9

8

7

6

5

4

3

2

1

-8 -7 -6 -5 -4 -3 -2 -1

0

1

2

3

4

5

V_Sor V_D- Source or Drain Voltage (V)

V_DD= 15 V, V_SS= −15 V

V_DD= 5 V, V_SS= −8 V

图6-5. On-Resistance vs Temperature

图6-6. On-Resistance vs Temperature

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6.16 Typical Characteristics (continued)

at T_A= 25°C

V_DD= 12 V, V_SS= 0 V

V_DD= 5 V, V_SS= −5 V

图6-8. On-Resistance vs Temperature

图6-7. On-Resistance vs Temperature

15

10

5

I_D(OFF)V_S/V_D= –4.5 V/4.5 V

I_D(OFF)V_S/V_D= 4.5 V/–4.5 V

I_ON–4.5 V

I_ON4.5 V

I_S(OFF)V_S/V_D= –4.5 V/4.5 V

I_S(OFF)V_S/V_D= 4.5 V/–4.5 V

0

-5

-10

-15

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (°C)

V_DD= 36 V, V_SS= 0 V

V_DD= 5 V, V_SS= −5 V

图6-9. On-Resistance vs Temperature

图6-10. Leakage Current vs Temperature

V_DD= 36 V, V_SS= 0 V

V_DD= 15 V, V_SS= −15 V

图6-12. Leakage Current vs Temperature

图6-11. Leakage Current vs Temperature

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6.16 Typical Characteristics (continued)

at T_A= 25°C

50

45

40

35

30

25

20

15

V_DD= 15 V, V_SS= –15 V

V_DD= 5 V, V_SS= –5 V

V_DD= 12 V, V_SS= 0 V

V_DD= 5 V, V_SS= 0 V

0

4

8

12

16

20

24

28

32

36

Logic Voltage (V)

V_DD= 12 V, V_SS= 0 V

图6-13. Leakage Current vs Temperature

图6-14. Supply Current vs Logic Voltage

100

80

V_DD= 15 V, V_SS= –15 V

V_DD= 5 V, V_SS= –5 V

V_DD= 15 V, V_SS= –15 V

V_DD= 5 V, V_SS= –5 V

80

60

40

20

0

60

40

20

0

-20

-40

-60

-20

-40

-20

-15

-10

-5

0

5

10

15

20

-20

-15

-10

-5

0

5

10

15

20

Source Voltage (V)

Drain Voltage (V)

图6-15. Charge Injection vs Source Voltage –Dual Supply

图6-16. Charge Injection vs Drain Voltage –Dual Supply

130

120

V_DD= 36 V, V_SS= 0 V

V_DD= 20 V, V_SS= 0 V

V_DD= 15 V, V_SS= 0 V

V_DD= 12 V, V_SS= 0 V

110

100

80

60

40

20

0

V_DD= 20 V, V_SS= 0 V

V_DD= 15 V, V_SS= 0 V

V_DD= 12 V, V_SS= 0 V

V_DD= 5 V, V_SS= 0 V

90

V_DD= 5 V, V_SS= 0 V

70

50

30

10

-10

-30

-50

-70

-20

-40

-60

0

4

8

12

16

20

24

28

32

36

0

4

8

12

16

20

24

28

32

36

Source Voltage (V)

Drain Voltage (V)

D018

图6-18. Charge Injection vs Drian Voltage –Single Supply

图6-17. Charge Injection vs Source Voltage –Single Supply

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6.16 Typical Characteristics (continued)

at T_A= 25°C

120

115

110

105

100

95

Transiton_Falling

Transiton_Rising

90

85

80

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (°C)

V_DD= 36 V, V_SS= 0 V

V_DD= 15 V, V_SS= −15 V

图6-20. T_TRANSITIONvs Temperature

图6-19. T_TRANSITIONvs Temperature

120

115

110

105

100

95

T_(OFF)

T_(ON)

90

85

80

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (°C)

V_DD= 15 V, V_SS= −15 V

V_DD= 36 V, V_SS= 0 V

图6-21. T_ONand T_OFFvs Temperature

图6-22. T_ONand T_OFFvs Temperature

0

V_DD= 15V, V_SS= –15V

V_DD= 36V, V_SS= 0V

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

-140

100

1k

10k

100k

1M

10M

100M

Frequency (Hz)

Switch ON (EN = 1)

图6-24. Crosstalk vs Frequency

图6-23. Off-Isolation vs Frequency

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6.16 Typical Characteristics (continued)

at T_A= 25°C

0.002

0.001

V_DD= 15 V, V_SS= –15 V

V_DD= 5 V, V_SS= –5V

0.0008

0.0007

0.0006

0.0005

0.0004

0.0003

10

100

1k

10k

Frequency (Hz)

Switch OFF (EN = 0)

图6-25. Crosstalk vs Frequency

图6-26. THD+N vs Frequency (Dual Supply)

V_DD= 15 V, V_SS= −15 V

图6-27. THD+N vs Frequency (Single Supply)

图6-28. On Response vs Frequency

V_DD= +15 V, V_SS= −15 V

图6-29. ACPSRR vs Frequency

图6-30. Capacitance vs Source Voltage or Drain Voltage

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6.16 Typical Characteristics (continued)

at T_A= 25°C

V_DD= 12 V, V_SS= 0 V

图6-31. Capacitance vs Source Voltage or Drain Voltage

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7 Parameter Measurement Information

7.1 On-Resistance

The on-resistance of a device is the ohmic resistance between the source (Sx) and drain (D) pins of the device.

The on-resistance varies with input voltage and supply voltage. The symbol R_ONis used to denote on-

resistance. 图 7-1 shows the measurement setup used to measure R_ON. Voltage (V) and current (I_SD) are

measured using the following setup, where R_ONis computed as R_ON= V / I_SD

:

V

I_SD

Sx

Dx

V_S

RON

图7-1. On-Resistance

7.2 Off-Leakage Current

There are two types of leakage currents associated with a switch during the off state:

1. Source off-leakage current.

2. Drain off-leakage current.

Source leakage current is defined as the leakage current flowing into or out of the source pin when the switch is

off. This current is denoted by the symbol I_S(OFF)

Drain leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is off.

This current is denoted by the symbol I_D(OFF)

图7-2 shows the setup used to measure both off-leakage currents.

.

V_DD

V_SS

V_DD

V_SS

I_{s (OFF)}

I_{D (OFF)}

S1

S2

S1

S2

A

D

A

V_S

V_D

GND

I_S(OFF)

I_D(OFF)

图7-2. Off-Leakage Measurement Setup

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7.3 On-Leakage Current

Source on-leakage current is defined as the leakage current flowing into or out of the source pin when the switch

is on. This current is denoted by the symbol I_S(ON)

.

Drain on-leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is

on. This current is denoted by the symbol I_D(ON)

.

Either the source pin or drain pin is left floating during the measurement. 图 7-3 shows the circuit used for

measuring the on-leakage current, denoted by I_S(ON)or I_D(ON)

.

V_DD

V_SS

V_DD

V_SS

I_{s (ON)}

I_{D (ON)}

S1

S2

S1

S2

N.C.

A

D

A

N.C.

V_S

GND

I_S(ON)

I_D(ON)

图7-3. On-Leakage Measurement Setup

7.4 Transition Time

Transition time is defined as the time taken by the output of the device to rise or fall 90% after the address signal

has risen or fallen past the logic threshold. The 90% transition measurement is utilized to provide the timing of

the device. System level timing can then account for the time constant added from the load resistance and load

capacitance. 图7-4 shows the setup used to measure transition time, denoted by the symbol t_TRANSITION

.

V_DD

V_SS

0.1 µF

V_S

3 V

0 V

V_DD

V_SS

V_SEL

t_r< 20 ns

t_f< 20 ns

50%

S1

S2

D

Output

C_L

t_TRANSITION

90%

R_L

SEL

Output

10%

GND

V_SEL

0 V

图7-4. Transition-Time Measurement Setup

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7.5 t_ON(EN)and t_OFF(EN)

Turn-on time is defined as the time taken by the output of the device to rise to 90% after the enable has risen

past the logic threshold. The 90% measurement is utilized to provide the timing of the device. System level

timing can then account for the time constant added from the load resistance and load capacitance. 图 7-5

shows the setup used to measure turn-on time, denoted by the symbol t_ON(EN)

.

Turn-off time is defined as the time taken by the output of the device to fall to 10% after the enable has fallen

past the logic threshold. The 10% measurement is utilized to provide the timing of the device. System level

timing can then account for the time constant added from the load resistance and load capacitance. 图 7-5

shows the setup used to measure turn-off time, denoted by the symbol t_OFF(EN)

.

V_DD

V_SS

0.1 µF

3 V

V_DD

V_SS

V_EN

t_r< 20 ns

t_f< 20 ns

50%

S1

S2

V_S

0 V

D

Output

C_L

t_ON

t_OFF

90%

R_L

EN

Output

10%

GND

V_EN

0 V

图7-5. Turn-On and Turn-Off Time Measurement Setup

7.6 Break-Before-Make

Break-before-make delay is a safety feature that prevents two inputs from connecting when the device is

switching. The output first breaks from the on-state switch before making the connection with the next on-state

switch. The time delay between the break and the make is known as break-before-make delay. 图7-6 shows the

setup used to measure break-before-make delay, denoted by the symbol t_OPEN(BBM)

.

V_DD

V_SS

0.1 µF

3 V

V_DD

V_SS

V_SEL

t_r< 20 ns

t_f< 20 ns

S1

S2

V_S

0 V

D

Output

C_L

R_L

80%

SEL

Output

0 V

t_BBM

1

t_BBM2

V_SEL

GND

t_{OPEN (BBM)}= min ( t_BBM1, t_BBM2)

图7-6. Break-Before-Make Delay Measurement Setup

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7.7 t_{ON (VDD)}Time

The t_{ON (VDD)}time is defined as the time taken by the output of the device to rise to 90% after the supply has

risen past the supply threshold. The 90% measurement is used to provide the timing of the device turning on in

the system. 图7-7 shows the setup used to measure turn on time, denoted by the symbol t_{ON (VDD)}

.

V_SS

0.1 µF

V_DD

Supply

Ramp

V_DD

V_SS

t_r= 10 µs

4.5 V

V_S

S2

S1

0 V

D

Output

C_L

t_ON

90%

R_L

EN

Output

3 V

SEL

GND

0 V

图7-7. t_{ON (VDD)}Time Measurement Setup

7.8 Propagation Delay

Propagation delay is defined as the time taken by the output of the device to rise or fall 50% after the input signal

has risen or fallen past the 50% threshold. 图 7-8 shows the setup used to measure propagation delay, denoted

by the symbol t_PD

.

V_DD

V_SS

0.1 µF

250 mV

Input

V_DD

S1

S2

V_SS

50%

t_r< 40 ps

(V_S)

t_f< 40 ps

50 Ω

V_S

0 V

D

Output

C_L

t_PD

1

t_{PD 2}

R_L

Output

0 V

50%

GND

t_{Prop Delay}= max ( t_PD1, t_PD2)

图7-8. Propagation Delay Measurement Setup

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7.9 Charge Injection

The TMUX6219 has a transmission-gate topology. Any mismatch in capacitance between the NMOS and PMOS

transistors results in a charge injected into the drain or source during the falling or rising edge of the gate signal.

The amount of charge injected into the source or drain of the device is known as charge injection, and is

denoted by the symbol Q_C. 图 7-9 shows the setup used to measure charge injection from source (Sx) to drain

(D).

V_DD

V_SS

0.1 µF

3 V

V_EN

V_DD

V_SS

t_r< 20 ns

t_f< 20 ns

Output

S1

S2

D

0 V

V_D

C_L

N.C.

Output

V_D

EN

V_OUT

Q_INJ= C_L×

V_OUT

V_EN

GND

图7-9. Charge-Injection Measurement Setup

7.10 Off Isolation

Off isolation is defined as the ratio of the signal at the drain pin (D) of the device when a signal is applied to the

source pin (Sx) of an off-channel. 图 7-10 shows the setup used to measure, and the equation used to calculate

off isolation.

V_DD

V_SS

0.1 µF

Network Analyzer

V_DD

V_SS

V_S

S1

D

50

V_OUT

V_SIG

50

S2

50

GND

图7-10. Off Isolation Measurement Setup

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7.11 Crosstalk

Crosstalk is defined as the ratio of the signal at the drain pin (D) of a different channel, when a signal is applied

at the source pin (Sx) of an on-channel. 图 7-11 shows the setup used to measure, and the equation used to

calculate crosstalk.

V_DD

V_SS

0.1 µF

Network Analyzer

V_DD

V_SS

V_S

S1

S2

D

50

V_OUT

50

V_SIG

GND

图7-11. Crosstalk Measurement Setup

7.12 Bandwidth

Bandwidth is defined as the range of frequencies that are attenuated by less than 3 dB when the input is applied

to the source pin (Sx) of an on-channel, and the output is measured at the drain pin (D) of the device. 图 7-12

shows the setup used to measure bandwidth.

V_DD

V_SS

0.1 µF

Network Analyzer

V_DD

V_SS

V_S

S1

D

50

V_OUT

V_SIG

50

S2

50

GND

图7-12. Bandwidth Measurement Setup

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7.13 THD + Noise

The total harmonic distortion (THD) of a signal is a measurement of the harmonic distortion, and is defined as

the ratio of the sum of the powers of all harmonic components to the power of the fundamental frequency at the

mux output.

The on-resistance of the device varies with the amplitude of the input signal and results in distortion when the

drain pin is connected to a low-impedance load. Total harmonic distortion plus noise is denoted as THD + N.

V_DD

V_SS

0.1 µF

V_DD

V_SS

Audio Precision

S1

D

40

V_OUT

V_S

R_L

Other

Sx pins

50

GND

图7-13. THD + N Measurement Setup

7.14 Power Supply Rejection Ratio (PSRR)

PSRR measures the ability of a device to prevent noise and spurious signals that appear on the supply voltage

pin from coupling to the output of the switch. The DC voltage on the device supply is modulated by a sine wave

of 620 mV_PP. The ratio of the amplitude of signal on the output to the amplitude of the modulated signal is the

ACPSRR. A high ratio represents a high degree of tolerance to supply rail variation.

This helps stabilize the supply and immediately filter as much of the supply noise as possible.

V_DD

Network Analyzer

V_SS

DC Bias

Injector

With and Without

Capacitor

50 Ω

0.1 µF

V_DD

S1

V_SS

620 mV_PP

V_IN

V_BIAS

50 Ω

S2

50 Ω

V_OUT

D

C_L

R_L

GND

图7-14. ACPSRR Measurement Setup

32

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8 Detailed Description

8.1 Overview

The TMUX6219 is a 2:1, 1-channel switch. Each input is turned on or turned off based on the state of the select

line and enable pin.

8.2 Functional Block Diagram

V_SS

V_DD

S1

S2

D

Decoder

EN SEL

图8-1. TMUX6219 Functional Block Diagram

8.3 Feature Description

8.3.1 Bidirectional Operation

The TMUX6219 conducts equally well from source (Sx) to drain (D) or from drain (D) to source (Sx). Each

channel has very similar characteristics in both directions and supports both analog and digital signals.

8.3.2 Rail to Rail Operation

The valid signal path input or output voltage for TMUX6219 ranges from V_SSto V_DD

.

8.3.3 1.8 V Logic Compatible Inputs

The TMUX6219 has 1.8-V logic compatible control for all logic control inputs. 1.8-V logic level inputs allows the

TMUX6219 to interface with processors that have lower logic I/O rails and eliminates the need for an external

translator, which saves both space and BOM cost. For more information on 1.8 V logic implementations refer to

Simplifying Design with 1.8 V logic Muxes and Switches.

8.3.4 Fail-Safe Logic

The TMUX6219 supports Fail-Safe Logic on the control input pins (EN and SEL) allowing for operation up to 36

V above ground, regardless of the state of the supply pins. This feature allows voltages on the control pins to be

applied before the supply pin, protecting the device from potential damage. Fail-Safe Logic minimizes system

complexity by removing the need for power supply sequencing on the logic control pins. For example, the Fail-

Safe Logic feature allows the logic input pins of the TMUX6219 to be ramped to +36 V while V_DDand V_SS= 0 V.

The logic control inputs are protected against positive faults of up to +36 V in powered-off condition, but do not

offer protection against negative overvoltage conditions.

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8.3.5 Latch-Up Immune

Latch-up is a condition where a low impedance path is created between a supply pin and ground. This condition

is caused by a trigger (current injection or overvoltage), but once activated, the low impedance path remains

even after the trigger is no longer present. This low impedance path may cause system upset or catastrophic

damage due to excessive current levels. The latch-up condition typically requires a power cycle to eliminate the

low impedance path.

The TMUX62xx family of devices are constructed on Silicon on Insulator (SOI) based process where an oxide

layer is added between the PMOS and NMOS transistor of each CMOS switch to prevent parasitic structures

from forming. The oxide layer is also known as an insulating trench and prevents triggering of latch up events

due to overvoltage or current injections. The latch-up immunity feature allows the TMUX62xx family of switches

and multiplexers to be used in harsh environments.

8.3.6 Ultra-Low Charge Injection

The TMUX6219 has a transmission gate topology, as shown in 图 8-2. Any mismatch in the stray capacitance

associated with the NMOS and PMOS causes an output level change whenever the switch is opened or closed.

OFF ON

C_GDN

C_GSN

D

S

C_GSP

C_GDP

OFF ON

图8-2. Transmission Gate Topology

The TMUX6219 contains specialized architecture to reduce charge injection on the source (Sx). To further

reduce charge injection in a sensitive application, a compensation capacitor (Cp) can be added on the drain (D).

This will ensure that excess charge from the switch transition will be pushed into the compensation capacitor on

the drain (D) instead of the source (Sx). As a general rule, Cp should be 20× larger than the equivalent load

capacitance on the source (Sx). 图 8-3 shows charge injection variation with source voltage with different

compensation capacitors on the Drain side.

图8-3. Charge Injection Compensation

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8.4 Device Functional Modes

When the EN pin of the TMUX6219 is pulled high, one of the switches is closed based on the state of the SEL

pin. When the EN pin is pulled low, both of the switches are in an open state regardless of the state of the SEL

pin. The control pins can be as high as 36 V.

The TMUX6219 can be operated without any external components except for the supply decoupling capacitors.

The EN pin has an internal pull-up resistor of 4 MΩ and SEL pin has internal pull-down resistor of 4 MΩ. If

unused, the EN pin must be tied to V_DDand SEL pin must be tied to GND to ensure the device does not

consume additional current as highlighted in Implications of Slow or Floating CMOS Inputs. Unused signal path

inputs (S1, S2, or D) should be connected to GND.

8.5 Truth Tables

表8-1 provides the truth tables for the TMUX6219.

表8-1. TMUX6219 Truth Table

EN SEL

Selected Source Connected To Drain (D) Pin

0

1

X⁽¹⁾

All sources are off (HI-Z)

0

S1

S2

1

(1) X denotes do not care.

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9 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

9.1 Application Information

TMUX6219 is part of the precision switches and multiplexers family of devices. TMUX6219 offers low RON, low

on and off leakage currents and ultra-low charge injection performance. These properties make TMUX6219 ideal

for implementing high precision industrial systems requiring selection of one of two inputs or outputs.

9.2 Typical Application

9.2.1 Power Amplifier Gate Driver

One application of the TMUX6219 is for input control of a power amplifier gate driver. Utilizing a switch allows a

system to control when the DAC is connected to the power amplifier and can stop biasing the power amplifier by

switching the gate to V_SS. The wide dual supply range of ±4.5 V to ±18 V allows the switch to work with GaN

power amplifiers, and the wide single supply range 4.5 V to 36 V works well with LDMOS power amplifiers.

图9-1 shows the TMUX6219 configured for control of the power amplifier gate driver in GaN application.

8 V

Output

voltage

DAC

V_DD

RF Tx/Rx

TMUX6219

œ12 V/0 V

1.8 V

œ12 V

RF Input

MCU

0 V to 1.8 V

V_SS

图9-1. Power Amplifier Gate Driver

9.2.2 Design Requirements

For the design example, use the parameters listed in 表9-1.

表9-1. Design Parameters

VALUES

PARAMETERS

GAN application

8 V

LDMOS application

Supply (V_DD

)

5 V

0 V

Supply (V_SS

)

−12 V

MUX I/O signal range

Control logic thresholds

EN

0 V to 5 V (Rail-to-Rail)

1.8 V compatiable (up to V_DD

−12 V to 8 V (Rail-to-Rail)

1.8 V compatiable (up to V_DD

)

EN pulled high to enable the switch

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9.2.3 Detailed Design Procedure

The application shown in 图 9-1 demonstrates how to toggle between the DAC output and low signal voltage for

control of a GaN power amplifier using a single control input. The DAC output is utilized to bias the gate of the

power amplifier and can be disconnected from the circuit using the select pin of the switch. The TMUX6219 can

support 1.8 V logic signals on the control input, allowing the device to interface with low logic controls of an

FPGA or MCU. The TMUX6219 can operate without any external components except for the supply decoupling

capacitors. The select pin has an internal pull-down resistor to prevent floating input logic. All inputs to the switch

must fall within the recommended operating conditions of the TMUX6219 including signal range and continuous

current. For this design with a positive supply of 8 V on V_DDand negative supply of −12 V on V_SS, the signal

range can be 8 V to −12 V. The maximum continuous current (I_DC) can be up to 330 mA as shown in the

Recommended Operating Conditions table for wide-range current measurement.

9.2.4 Application Curve

The low on and off leakage currents of TMUX6219 and ultra-low charge injection performance make this device

ideal for implementing high precision industrial systems. 图 9-2 shows the plot for the charge injection versus

source voltage for the TMUX6219.

80

V_DD= 15 V, V_SS= –15 V

V_DD= 5 V, V_SS= –5 V

60

40

20

0

-20

-40

-20

-15

-10

-5

0

5

10

15

20

Drain Voltage (V)

图9-2. Charge Injection vs Drain Voltage

10 Power Supply Recommendations

The TMUX6219 operates across a wide supply range of of ±4.5 V to ±18 V (4.5 V to 36 V in single-supply

mode). As shown in 图9-1, the device also performs well with asymmetrical supplies such as V_DD= 5 V and V_SS

= –8 V.

Power-supply bypassing improves noise margin and prevents switching noise propagation from the supply rails

to other components. Good power-supply decoupling is important to achieve optimum performance. For

improved supply noise immunity, use a supply decoupling capacitor ranging from 0.1 μF to 10 μF at both the

V_DDand V_SSpins to ground. Place the bypass capacitors as close to the power supply pins of the device as

possible using low-impedance connections. TI recommends using multi-layer ceramic chip capacitors (MLCCs)

that offer low equivalent series resistance (ESR) and inductance (ESL) characteristics for power-supply

decoupling purposes. For very sensitive systems, or for systems in harsh noise environments, avoiding the use

of vias for connecting the capacitors to the device pins may offer superior noise immunity. The use of multiple

vias in parallel lowers the overall inductance and is beneficial for connections to power and ground planes.

Always ensure the ground (GND) connection is established before supplies are ramped.

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11 Layout

11.1 Layout Guidelines

When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of

the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This

increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance

of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must

turn corners. 图 11-1 shows progressively better techniques of rounding corners. Only the last example (BEST)

maintains constant trace width and minimizes reflections.

WORST

BETTER

BEST

2W

1W min.

W

图11-1. Trace Example

Route high-speed signals using a minimum of vias and corners which reduces signal reflections and impedance

changes. When a via must be used, increase the clearance size around it to minimize its capacitance. Each via

introduces discontinuities in the signal’s transmission line and increases the chance of picking up interference

from the other layers of the board. Be careful when designing test points, through-hole pins are not

recommended at high frequencies.

图11-2 illustrates an example of a PCB layout with the TMUX6219. Some key considerations are as follows:

• Decouple the supply pins with a 0.1-µF and 1 µF capacitor, and place the lowest value capacitor as close to

the pin as possible. Make sure that the capacitor voltage rating is sufficient for the supply voltage.

• Keep the input lines as short as possible.

• Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup.

• Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if

possible, and only make perpendicular crossings when necessary.

• Using multiple vias in parallel will lower the overall inductance and is beneficial for connection to ground

planes.

11.2 Layout Example

S2

V_SS

SEL

EN

D

TMUX6219

S1

GND

VDD

Wide (low inductance)

trace for power

C

Wide (low inductance)

trace for power

Via to ground plane

图11-2. TMUX6219DGK Layout Example

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Wide (low inductance)

trace for power

S2

D

VSS

SEL

EN

S1

GND

VSS

Wide (low inductance)

trace for power

Via to ground plane

图11-3. TMUX6219RQX Layout Example

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation, see the following:

• Texas Instruments, Improve Stability Issues with Low CON Multiplexers application brief

• Texas Instruments, Improving Signal Measurement Accuracy in Automated Test Equipment application brief

• Texas Instruments, Multiplexers and Signal Switches Glossary application report

• Texas Instruments, QFN/SON PCB Attachment application report

• Texas Instruments, Quad Flatpack No-Lead Logic Packages application report

• Texas Instruments, Simplifying Design with 1.8 V logic Muxes and Switches application brief

• Texas Instruments, System-Level Protection for High-Voltage Analog Multiplexers application report

• Texas Instruments, True Differential, 4 x 2 MUX, Analog Front End, Simultaneous-Sampling ADC Circuit

application report

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

12.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

12.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

40

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PACKAGE OUTLINE

RQX0008A

WSON - 0.8 mm max height

S

C

A

L

E

5

.

0

PLASTIC SMALL OUTLINE - NO LEAD

3.1

2.9

A

B

PIN 1 INDEX AREA

2.1

1.9

0.8

0.7

C

SEATING PLANE

0.08 C

0.05

0.00

1.8 0.1

SYMM

EXPOSED

THERMAL PAD

(0.2) TYP

4

5

SYMM

1.65 0.1

9

2X 1.5

6X 0.5

8

1

PIN 1 ID

0.3

0.2

8X

0.45

0.35

8X

0.1

0.05

C A B

4225821/A 04/2020

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

RQX0008A

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

(1.8)

SEE SOLDER MASK

DETAIL

8X (0.6)

SYMM

8X (0.25)

1

8

(1.65)

9

SYMM

6X (0.5)

(0.575)

(R0.05) TYP

5

4

(

0.2) TYP

VIA

(2.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

METAL UNDER

SOLDER MASK

METAL EDGE

EXPOSED METAL

SOLDER MASK

OPENING

EXPOSED

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4225821/A 04/2020

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

RQX0008A

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

8X (0.6)

(1.63)

8

1

8X (0.25)

SYMM

(1.51)

9

6X (0.5)

(R0.05) TYP

4

5

SYMM

(2.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 MM THICK STENCIL

SCALE: 20X

EXPOSED PAD 9

83% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

4225821/A 04/2020

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	PTMUX6219RQXR
厂家：	TEXAS INSTRUMENTS
描述：	具有 1.8V 逻辑控制的 36V 低导通电阻、2:1、单通道多路复用器 \| RQX \| 8 \| -40 to 125 复用器
文件：	总50页 (文件大小：2396K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PTMUX6219RQXR [TI]

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