PTPS6522053RHBR_技术文档

TPS65220

ZHCSQO4 –DECEMBER 2022

TPS65220 适用于ARM Cortex^®-A53 处理器和FPGA 的集成电源管理IC

1 特性

3 说明

• 3 个高达2.3MHz 非固定开关频率或固定频率模式

的降压转换器：

TPS65220 是一款电源管理 IC (PMIC)，旨在为便携式

和固定式应用中的各种 SoC 供电。该 PMIC 的额定环

境温度范围为 -40°C 至 +125°C，因此适用于各种工业

应用。该器件包括三个同步直流/直流降压转换器和四

个线性稳压器。

– 1 个VIN：2.5V –5.5V；I_OUT：3.5A；V_OUT

0.6V –3.4V

– 2 个VIN：2.5V –5.5V；I_OUT：2A；V_OUT0.6V

–3.4V

• 4 个线性稳压器：

直流/直流转换器能够提供 1 个3.5A 电流和2 个2A 电

流。这些转换器需要一个 470nH 的小型电感器、一个

4.7μF 的输入电容，以及每个电源轨一个最小 10μF

的输出电容。

– 2 个VIN：1.5V –5.5V；I_OUT：400mA；

V_OUT：0.6V –3.4V（可配置为负载开关和旁路

模式，支持SD 卡）

其中两个 LDO 在0.6V 至3.4V 的输出电压范围内支持

400mA 的输出电流。这些 LDO 支持旁路模式，充当

负载开关，并允许在工作期间改变电压。其他两个

LDO 在 1.2V 至 3.3V 的输出电压范围内支持 300mA

的输出电流。这些LDO 也支持负载开关模式。

– 2 个VIN：2.2V –5.5V；I_OUT：300mA；

V_OUT：1.2V –3.3V（可配置为负载开关）

• 所有三个降压转换器上的动态电压调节

• 低IQ/PFM 的PWM 模式（准固定频率）或固定频

率模式

• 可编程电源时序和默认电压

• I²C 接口，支持标准模式、快速模式和快速模式增

强版

• 设计为支持具有多达14 个以上电源轨的系统（2 个

TPS65220，每个7 个电源轨+ GPO 控制的外部电

源轨）

I2C 接口、IO、GPIO 和多功能引脚(MFP) 可实现与各

种SoC 的无缝连接。

器件信息⁽¹⁾

器件型号

封装

封装尺寸（标称值）

TPS65220

5.00mm × 5.00mm

32 引脚QFN

• 2 个GPO、1 个GPIO 和3 个多功能引脚

• EEPROM 可编程性

• 提供功能安全

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

VSYS (2.5 V

PMIC

to 5 V)

2 应用

0.6 – 3.4 V, 3.5 A

0.6 – 3.4 V, 2 A

BUCK1

BUCK2

BUCK3

VSYS

PVIN_Bx

PVIN_LDOx

3

• AM62x 和AM64x 等低功耗工业MPU

• HMI

• PLC

• 工业PC

• 楼宇安全

• HVAC

• 视频监控

• 数据集中器：

• 智能仪表

• 保护继电器

• 患者监护和诊断

• 成像

3

0.6 – 3.4 V, 400 mA

VSYS

LDO1

LDO2

1.2 – 3.3 V, 300 mA

LDO3

LDO4

Push-

button

(optional)

SCL

SDA

nINT

EN/PB/VSENSE

nRSTOUT

VSEL_SD

MODE/STBY

RESET

GPIO

GPO1

GPO2

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLVSGY1

TPS65220

ZHCSQO4 –DECEMBER 2022

www.ti.com.cn

Table of Contents

7.3 Feature Description...................................................15

7.4 Device Functional Modes..........................................39

7.5 Device Registers.......................................................46

8 Application and Implementation................................121

8.1 Application Information........................................... 121

8.2 Typical Application.................................................. 121

8.3 Power Supply Recommendations...........................121

8.4 Layout..................................................................... 121

9 Device and Documentation Support..........................122

9.1 Device Support....................................................... 122

9.2 Documentation Support.......................................... 122

9.3 接收文档更新通知................................................... 122

9.4 支持资源..................................................................122

9.5 Trademarks.............................................................122

9.6 Electrostatic Discharge Caution..............................122

9.7 术语表..................................................................... 122

10 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 7

6.1 Absolute Maximum Ratings........................................ 7

6.2 ESD Ratings............................................................... 7

6.3 Recommended Operating Conditions.........................7

6.4 Thermal Information....................................................8

6.5 BUCK1 Converter....................................................... 9

6.6 BUCK2, BUCK3 Converter......................................... 9

6.7 General Purpose LDOs (LDO1, LDO2).................... 10

6.8 General Purpose LDOs (LDO3, LDO4).....................11

6.9 GPIOs and multi-function pins (EN/PB/VSENSE,

nRSTOUT, nINT, GPO1, GPO2, GPIO, MODE/

RESET, MODE/STBY, VSEL_SD/VSEL_DDR)...........12

7 Detailed Description......................................................14

7.1 Overview...................................................................14

7.2 Functional Block Diagram.........................................15

Information.................................................................. 122

10.1 Tape and Reel Information....................................123

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

DATE

REVISION

NOTES

December 2022

*

Initial Release

2

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5 Pin Configuration and Functions

1

2

3

4

5

6

7

8

24 FB_B3

FB_B1

VLDO4

23

22

21

20

LX_B1_1

LX_B1_2

PVIN_LDO34

VLDO3

PVIN_B1_1

PVIN_B1_2

PVIN_LDO1

VLDO1

PVIN_LDO2

19 VLDO2

Thermal Pad

(GND)

nRSTOUT

GPO2

18

17

GPO1

图5-1. RHB Package, 32-pin QFN (Top View)

表5-1. Pin Functions

CONNECTION if not used

(output rails must be

permanently disabled)

PIN NAME

FB_B1

PIN NO.

TYPE

DESCRIPTION

Feedback Input for Buck1. Connect to Buck1

1

I

output filter. Nominal output voltage is configured in Connect to GND

EEPROM.

Switch Pin for Buck1. Connect one side of the

Leave floating

LX_B1_1

LX_B1_2

2

3

PWR

Buck1-inductor to this pin.

2nd Switch Pin for Buck1. Connect one side of the

Leave floating

Buck1-inductor to this pin. Connect to LX_B1_1.

Power Input for BUCK1. Bypass this pin to ground

with a 4.7 μF or greater ceramic capacitor. Voltage

on PVIN_B1_1 pin must not exceed voltage on

VSYS pin.

PVIN_B1_1

PVIN_B1_2

4

5

PWR

Connect to VSYS

2nd Power Input for BUCK1. This pin shares the

bypass capacitor from pin 4. Voltage on

PVIN_B1_2 pin must not exceed voltage on VSYS

Connect to VSYS

pin.

Power Input for LDO1. Voltage on PVIN_LDO1 pin

Connect to VSYS

PVIN_LDO1

VLDO1

6

7

PWR

must not exceed voltage on VSYS pin.

Output Voltage of LDO1. Nominal output voltage is

configured in EEPROM. Bypass this pin to ground Leave floating

with a 2.2 µF or greater ceramic capacitor.

General Purpose Open-Drain Output. Configurable

GPO1

SDA

8

9

O

in the power-up and power-down-sequence to

enable an external rail.

Leave floating

Connect to VIO

Data Pin for the I2C Serial Port. The I2C logic

levels depend on the external pull-up voltage.

I/O

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表5-1. Pin Functions (continued)

CONNECTION if not used

PIN NAME

SCL

PIN NO.

TYPE

DESCRIPTION

(output rails must be

permanently disabled)

Clock Pin for the I2C Serial Port. The I2C logic

levels depend on the external pull-up voltage.

10

11

I

Connect to VIO

Interrupt Request Output. Open-drain driver is

pulled low for fault conditions. Released if bit is

cleared

nINT

O

Leave floating

n/a (connect to GND)

n/a

Multi-Function-Pin:

Configured as VSEL_SD: SD-card-IO-voltage

select. Connected to SoC. Trigger a voltage

change between 1.8 V and register-based VOUT

on LDO1 or LDO2. Polarity is configurable.

Configured as VSEL_DDR: DDR-voltage selection.

Hard-wired pull-up (1.35 V), pull-down (register

based VOUT) or floating (1.2 V)

VSEL_SD/

VSEL_DDR

12

13

I

Input supply pin for reference system. Bypass this

pin to ground with a 2.2 µF or greater ceramic

capacitor (can be shared with PVIN-capacitors).

VSYS

PWR

Internal Reference Voltage: For Internal Use Only.

Bypass this pin to ground with a 2.2 µF or greater

ceramic capacitor.

VDD1P8

AGND

14

15

PWR

GND

n/a

Ground pin for Analog GND

GPO-configuration: General Purpose Open-Drain

Output. Configurable in the power-up and power-

down-sequence to enable an external rail.

GPIO-configuration:

GPIO

16

I/O

Leave floating

Synchronizing I/O. Used to synchronize two or

more TPS65220. The pin is level-sensitive.

General Purpose Open-Drain Output. Configurable

in the power-up and power-down-sequence to

enable an external rail.

GPO2

nRSTOUT

VLDO2

17

18

19

O

Leave floating

Reset-output to SoC. Controlled by sequencer.

High in ACTIVE and STBY state.

Output Voltage of LDO2. Nominal output voltage is

configured in EEPROM. Bypass this pin to ground Leave floating

with a 2.2 µF or greater ceramic capacitor.

PWR

Power Input for LDO2. Bypass this pin to ground

with a 2.2 μF or greater ceramic capacitor. Voltage

on PVIN_LDO2 pin must not exceed voltage on

VSYS pin.

PVIN_LDO2 20

PWR

Connect to VSYS

Output Voltage of LDO3. Nominal output voltage is

configured in EEPROM. Bypass this pin to ground Leave floating

with a 2.2 µF or greater ceramic capacitor.

VLDO3

21

Power Input for LDO3 and LDO4. Bypass this pin

to ground with a 4.7 μF or greater ceramic

capacitor. Voltage on PVIN_LDO34 pin must not

PVIN_LDO34 22

Connect to VSYS

exceed voltage on VSYS pin.

Output Voltage of LDO4. Nominal output voltage is

VLDO4

FB_B3

23

24

PWR

I

configured in EEPROM.Bypass this pin to ground

with a 2.2 µF or greater ceramic capacitor.

Leave floating

Feedback Input for Buck3. Connect to Buck3

output filter. Nominal output voltage is configured in Connect to GND

EEPROM.

4

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PIN NAME

表5-1. Pin Functions (continued)

CONNECTION if not used

(output rails must be

permanently disabled)

PIN NO.

TYPE

DESCRIPTION

ON-request input.

Configured as EN: Device enable pin, high level is

ON-request, low-level is OFF-request.

Configured as PB: Push-button monitor input. 600

ms low-level is an ON-request, 8 s low-level is an

OFF-request.

Configured as VSENSE: Power-fail comparator

input. Set sense voltage using a resistor divider

connected from the input to the pre-regulator to this

pin to ground. Detects rising/falling voltage on pre-

regulator and triggers ON- / OFF-request.

The pin is edge-sensitive with a wait-time in PB-

configuration and deglitch time for EN- and

VSENSE-configuration.

EN/PB/

VSENSE

n/a (configure as EN and connect

to VSYS)

25

I

Power Input for BUCK3. Bypass this pin to ground

with a 4.7 μF or greater ceramic capacitor. Voltage

on PVIN_B3 pin must not exceed voltage on VSYS

pin.

PVIN_B3

LX_B3

26

27

PWR

Connect to VSYS

Leave floating

Switch Pin for Buck3. Connect one side of the

Buck3-inductor to this pin.

Multi-Function-Pin:

Configured as MODE: Connected to SoC or hard-

wired pull-up/-down. Forces the Buck-converters

into PWM or permits auto-entry in PFM-mode.

Configured as RESET: Connected to SoC. Forces

a WARM or COLD reset (configurable), WARM

reset resetting output voltages to defaults, COLD

reset sequencing down all enabled rails and power

up again.

n/a (tie high or low, dependent on

configuration, see 'PWM/PFM

and Reset (MODE/RESET)'

MODE/RESET 28

I

Polarity is configurable.

The pin is level-sensitive for MODE-configuration,

edge-sensitive for RESET-configuration.

Switch Pin for Buck2. Connect one side of the

Buck2-inductor to this pin.

LX_B2

29

30

PWR

Leave floating

Power Input for BUCK2. Bypass this pin to ground

with a 4.7 μF or greater ceramic capacitor. Voltage

on PVIN_B2 pin must not exceed voltage on VSYS

pin.

PVIN_B2

Connect to VSYS

Multi-Function-Pin:

Configured as MODE:

Connected to SoC or hard-wired pull-up/-down.

Forces the Buck-converters into PWM or permits

auto-entry in PFM-mode.

n/a (tie high or low, dependent on

configuration, see 'PWM/PFM

MODE/STBY 31

I

Configured as STBY: Low-power-mode command, and Low Power Modes (MODE/

STBY)'

disables selected rails.

Both functions, MODE and STBY, can be

combined.

The pin is level-sensitive.

Feedback Input for Buck2. Connect to Buck2

output filter. Nominal output voltage is configured in Connect to GND

EEPROM.

FB_B2

32

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表5-1. Pin Functions (continued)

CONNECTION if not used

PIN NAME

PGND

PIN NO.

TYPE

DESCRIPTION

(output rails must be

permanently disabled)

Power-Ground. The exposed pad must be

connected to a continuous ground plane of the

printed circuit board by multiple interconnect vias

directly under the TPS65220 to maximize electrical

and thermal conduction.

PowerPad

GND

n/a

6

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

POS

MIN

MAX

UNIT

1.1.1

1.1.2

1.1.5

1.1.6

Input voltage

VSYS

6

V

–0.3

PVIN_B1, PVIN_B2, PVIN_B3, PVIN_LDO1,

PVIN_LDO2, PVIN_LDO34

6

V

–0.3

FB_B1, FB_B2, FB_B3

EN/PB/VSENSE, MODE/STBY, MODE/RESET,

VSEL_SD/VSEL_DDR

PVIN_Bx +

0.3 V, up to

6 V

1.2.1

Output voltage

LX_B1, LX_B2, LX_B3

V

–0.3

1.2.2

1.2.3

Output voltage

LX_B1, LX_B2, LX_B3 spikes for maximum 10ns

GPO1, GPO2, GPIO

10

6

V

–2

–0.3

PVIN_LDOx

+ 0.3 V, up

to 6 V

1.2.4

Output voltage

VLDO1, VLDO2, VLDO4, VLDO4

V

–0.3

1.2.5

1.2.6

1.2.7

1.4.1

1.4.2

Output voltage

VDD1P8

2

6

V

–0.3

-40

SDA, SCL

nINT, nRSTOUT

6

V

Operating junction temperature, T_J

Storage temperature, T_stg

150

°C

-40

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If

used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

6.2 ESD Ratings

POS

2.1

2.2

VALUE

UNIT

Electrostatic discharge, Human Body

Model

Human body model (HBM), per ANSI/

ESDA/JEDEC JS-001, all pins⁽¹⁾

V_(ESD)

±2000

V

Electrostatic discharge, Charged Device

Model

Charged device model (CDM), per JEDEC

specification JESD22-C101, all pins⁽²⁾

±500

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

POS

MIN

NOM

MAX

UNIT

3.1.1

V_VSYS

Input voltage

BUCKx Pins

2.5 ⁽¹⁾

5.5

V

V_{PVIN_B1}, V_{PVIN_B2}

V_{PVIN_B3}

V_{LX_B1}, V_{LX_B2}

V_{LX_B3}

,

3.1.2

2.5

5.5 ⁽²⁾

V

,

C_{PVIN_B1}, C_{PVIN_B2}

C_{PVIN_B3}

,

3.1.7

3.1.8

3.1.9a

BUCKx Input Capacitance

BUCKx Output Inductance

3.9

330

10

4.7

µF

nH

µF

L_B1, L_B2, L_B3

470

611

75

C_{OUT_B1}, C_{OUT_B2}

,

BUCKx Output Capacitance, forced PWM or

auto-PFM, low bandwidth case

C_{OUT_B3}

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6.3 Recommended Operating Conditions (continued)

over operating free-air temperature range (unless otherwise noted)

POS

MIN

NOM

MAX

UNIT

C_{OUT_B1}, C_{OUT_B2}

C_{OUT_B3}

,

BUCKx Output Capacitance, fixed frequency,

low BW case

3.1.9b

3.1.10a

3.1.10b

3.1.11

12

36

220

µF

C_{OUT_B1}, C_{OUT_B2}

C_{OUT_B3}

BUCKx Output Capacitance, forced PWM or

auto-PFM, high bandwidth case

30

48

0

µF

V

C_{OUT_B1}, C_{OUT_B2}

C_{OUT_B3}

BUCKx Output Capacitance, fixed frequency,

high BW case

144

V_{FB_B1}, V_{FB_B2}

,

BUCKx FB Pins

5.5 ⁽²⁾

V_{FB_B3}

3.1.12

3.1.13

3.1.15

3.1.16

3.1.17

3.1.18

3.1.19

3.1.20

3.1.21

3.1.22

3.1.23

3.1.24

3.1.25

3.1.26

3.1.27

V_{PVIN_LDO1}, V_{PVIN_LDO2}

V_VLDO1, V_VLDO2

C_{PVIN_LDO1}, C_{PVIN_LDO2}

C_VLDO1, C_VLDO2

V_{PVIN_LDO3}, V_{PVIN_LDO4}

V_VLDO3, V_VLDO4

C_{PVIN_LDO34}

LDO Input Voltage

1.5

0.6

1.6

2.2

1.2

2.2

1.6

0

5.5 ⁽²⁾

3.6

V

LDO Input Voltage in bypass mode

LDO Output Voltage Range

LDO Input Capacitance

LDO Output Capacitance

LDO Input Voltage

3.4

V

2.2

µF

V

20

5.5 ⁽²⁾

3.3

LDO Output Voltage Range

LDO Input Capacitance

LDO Output Capacitance

VDD1P8 pin

V

4.7

2.2

µF

V

C_VLDO3, C_VLDO4

V_VDD1P8

30 ⁽³⁾

1.8

4

C_VDD1P8

Internal Regulator Decoupling Capacitance

VSYS Input Decoupling Capacitance

Digital Outputs

1

2.2

µF

V

C_VSYS

1

V_nINT, V_nRSTOUT

V_GPO1, V_GPO2, V_GPIO

V_SCL, V_SDA

0

3.4

5.5 ⁽²⁾

3.4

Digital Outputs

0

V

I2C Interface

0

V

V_EN/PB/VSENSE, V_MODE/STBY

,

3.1.28

V_MODE/RESET

,

Digital Inputs

0

5.5 ⁽²⁾

V

V_{VSEL_SD/VSEL/DDR}

3.3.1

3.3.2

T_{A_}

T_{J_}

Operating free-air temperature

Operating junction temperature

125

150

°C

–40

(1) For EEPROM programming, VSYS(min)=3.3V

(2) Must not exceed VSYS

(3) In slow-ramp-mode. Fast-ramp supports 15µF maximum

6.4 Thermal Information

TPS65219

THERMAL METRIC⁽¹⁾

RHB (QFN)

UNIT

32 PINS, 5x5mm²

R_ΘJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

31.3

20.4

10.9

0.3

°C/W

R_ΘJC(top)

R_ΘJB

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

Ψ_JT

10.8

2.8

Ψ_JB

R_ΘJC(bot)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

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6.5 BUCK1 Converter

over operating free-air temperature range (unless otherwise noted)

POS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Electrical Characteristics

Buck supply voltage, maximum

VSYS

5.1.1a V_{IN_BUCK1}

Input voltage⁽¹⁾

2.5

5.5

3.4

V

Output voltage configurable in

25mV-steps for 0.6V ≤V_OUT≤

1.4V, in 100mV steps for 1.4V <

Buck Output Voltage configurable

Range

5.1.1b V_{OUT_BUCK1}

0.6

V

_OUT≤3.4V

5.1.4

5.1.5

V_{OUT_STEP_LOW}

Output voltage Steps

25

mV

0.6V ≤V_OUT≤1.4V

1.5V ≤V_OUT≤3.4V

V_{OUT_STEP_HIGH}Output voltage Steps

100

I_OUT= I_{OUT_MAX}

V_OUT= 0.6V to 3.4V,

V_IN- V_OUT> 700 mV

forced PWM, low BW case

,

DC Output Voltage Accuracy in

forced PWM mode, low and high

BW case

V_{OUT_ACC_DC_PW}

5.1.6a

1.5%

3.5%

1.5%

–1.5%

–3.0%

–1.5%

M

I_OUT= 1mA,

DC Output Voltage Accuracy in

V_OUT= 0.6V to 3.4V,

V_IN- V_OUT> 500 mV

auto-PFM, low BW case

5.1.6b V_{OUT_ACC_DC_PFM}auto-PFM mode, low and high BW

case

I_OUT= I_{OUT_MAX}

V_OUT= 0.6V to 3.4V,

V_IN- V_OUT> 1000 mV

fixed frequency, low BW case

,

DC Output Voltage Accuracy in

5.1.6c V_{OUT_ACC_DC_FF}Fixed Frequency mode, low and

high BW case

5.3.1

5.4.1

I_{OUT_MAX}

L_SW

Maximum Operating Current

Output Inductance

3.5

A

330

10

470

611

nH

DCR = 50mΩ max

ESR = 10mΩ max

Output Capacitance in auto-PFM or

forced PWM for low BW case

5.4.2a C_OUT

75

36

μF

Output Capacitance in fixed

frequency for low BW case

5.4.2b C_{OUT_FF}

12

30

48

ESR = 10mΩ max

Output Capacitance in auto-PFM or

forced PWM for high BW case

5.4.3a C_{OUT_HIGH_BW}

5.4.3b C_{OUT_HIGH_BW_FF}

220

144

Output Capacitance in fixed

frequency for high BW case

Timing Requirements

Switching Characteristics

Forced PWM, V_IN= 3.3V to 5V,

V_OUT= 0.8V to 1.8V,

I_OUT= 1A to 3A

Switching Frequency, forced PWM,

high or low BW case

5.6.1a f_SW

5.6.1b f_SW

2.3

MHz

Switching Frequency, fixed

Fixed - Frequency, V_IN= 3.3V to 5V,

frequency, high or low BW case, no V_OUT= 0.8V to 1.8V,

2.18

1.95

2.42 MHz

2.65 MHz

Spread Spectrum

I_OUT= 1A to 3A

Fixed - Frequency, V_IN= 3.3V to 5V,

V_OUT= 0.8V to 1.8V,

I_OUT= 1A to 3A

Switching Frequency, fixed

frequency, high or low BW case,

with Spread Spectrum enabled

5.6.2

f_{SW_SS_EN}

Spread spectrum enabled

(1) PVIN_Bx must not exceed VSYS

6.6 BUCK2, BUCK3 Converter

over operating free-air temperature range (unless otherwise noted)

POS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Electrical Characteristics

Buck supply voltage, maximum

VSYS

6.1.1a V_{IN_BUCK23}

Input Voltage⁽¹⁾

2.5

5.5

V

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MAX UNIT

6.6 BUCK2, BUCK3 Converter (continued)

over operating free-air temperature range (unless otherwise noted)

POS

PARAMETER

TEST CONDITIONS

MIN

TYP

Output voltage configurable in

Buck Output Voltage configurable

Range

25mV-steps for 0.6V ≤V_OUT≤

1.4V, in 100mV steps for 1.4V <

6.1.1b V_{OUT_BUCK23}

0.6

3.4

V

_OUT≤3.4V

Output voltage Steps Buck2 and

Buck3

6.1.4

6.1.5

V_{OUT_STEP_LOW}

25

mV

0.6V ≤V_OUT≤1.4V

V_{OUT_STEP_HIGH}Output voltage Steps Buck2, Buck3

100

1.5V ≤V_OUT≤3.4V

I_OUT= I_{OUT_MAX}

V_OUT= 0.6V to 3.4V,

V_IN- V_OUT> 700 mV

forced PWM, low BW case

,

DC Output Voltage Accuracy in

V_{OUT_ACC_DC_PW}

6.1.6a

forced PWM mode, low and high

1.5%

3.5%

1.5%

–1.5%

–3.0%

–1.5%

M

BW case

I_OUT= 1mA,

DC Output Voltage Accuracy in

V_OUT= 0.6V to 3.4V,

V_IN- V_OUT> 500 mV

auto-PFM, low BW case

6.1.6b V_{OUT_ACC_DC_PFM}auto-PFM mode, low and high BW

case

I_OUT= I_{OUT_MAX}

V_OUT= 0.6V to 3.4V,

V_IN- V_OUT> 1000 mV

fixed frequency, low BW case

,

DC Output Voltage Accuracy in

6.1.6c V_{OUT_ACC_DC_FF}Fixed Frequency mode, low and

high BW case

6.3.1

6.4.1

I_{OUT_MAX}

L_SW

Maximum Operating Current

Output Inductance

2.0

A

330

10

470

611

nH

DCR = 50mΩ max

ESR = 10mΩ max

Output Capacitance in auto-PFM or

forced PWM for low BW case

6.4.2a C_OUT

75

36

μF

Output Capacitance in fixed

frequency for low BW case

6.4.2b C_{OUT_FF}

12

30

48

ESR = 10mΩ max

Output Capacitance in auto-PFM or

forced PWM for high BW case

6.4.3a C_{OUT_HIGH_BW}

6.4.3b C_{OUT_HIGH_BW_FF}

220

144

Output Capacitance in fixed

frequency for high BW case

Timing Requirements

Switching Characteristics

Forced PWM, V_IN= 3.3V to 5V,

V_OUT= 0.8V to 1.8V,

I_OUT= 1A to 1.8A

Switching Frequency, forced PWM,

high or low BW case

6.6.1a f_SW

6.6.1b f_SW

2.3

MHz

Switching Frequency, fixed

Fixed - Frequency, V_IN= 3.3V to 5V,

frequency, high or low BW case, no V_OUT= 0.8V to 1.8V,

2.18

1.95

2.42 MHz

2.65 MHz

Spread Spectrum

I_OUT= 1A to 1.8A

Fixed - Frequency, V_IN= 3.3V to 5V,

V_OUT= 0.8V to 1.8V,

I_OUT= 1A to 1.8A

Switching Frequency, fixed

frequency, high or low BW case,

with Spread Spectrum enabled

6.6.2

f_{SW_SS_EN}

Spread spectrum enabled

(1) PVIN_Bx must not exceed VSYS

6.7 General Purpose LDOs (LDO1, LDO2)

over operating free-air temperature range (unless otherwise noted)

POS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Electrical Characteristics

7.1.1

7.1.2

7.1.3

V_{IN_LDO}

Input Voltage (LDO-mode)⁽¹⁾

Input Voltage (bypass-mode)^{(1) (5)}

Input Voltage (LSW-mode)⁽¹⁾

LDO-mode, maximum VSYS

Bypass-mode, maximum VSYS

LSW-mode, maximum VSYS

1.5

5.5

3.4

5.5

V

V_{IN_LDO_BYP}

V_{IN_LDO_LSW}

10

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6.7 General Purpose LDOs (LDO1, LDO2) (continued)

over operating free-air temperature range (unless otherwise noted)

POS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

LDO Output Voltage configurable

Range

LDO mode, with 50-mV steps, V_IN

V_OUT> 300 mV

-

7.1.4

V_{OUT_LDO}

0.6

3.4

V

LDO Output Voltage configurable

Range in bypass-mode

Bypass mode, configurable V_OUT

range with 50-mV steps

7.1.5

7.1.6

V_{OUT_LDO_BYP}

V_{OUT_STEP}

1.5

V

Output Voltage Steps

50

mV

LDO mode, 0.6V ≤V_OUT≤3.4V

Total DC Output Voltage accuracy,

LDO-mode, V_IN- V_OUT> 300 mV,

V_{OUT_ACCURACY_}including Voltage References, DC

7.1.8

7.1.9

7.3.1

7.4.1

1.1%

11

–1.1%

–11

load and line regulations, process

V

_OUT≥1V

H

and temperature variations

Total DC Output Voltage accuracy,

including Voltage References, DC

load and line regulations, process

LDO-mode, V_IN- V_OUT> 300 mV,

V_OUT< 1V

V_{OUT_ACCURACY_L}

mV

mA

µF

and temperature variations

V

_{PVIN_LDOxmin}≤V_IN≤

V_{PVIN_LDOxmax}

,

I_{OUT_MAX}

Output Current

400

Applies to LDO-, bypass- and LSW-

mode

Connected from PVIN_LDOx to

GND

Applies to LDO-, bypass- and LSW-

mode

C_IN

Input Filtering Capacitance ⁽²⁾

Output Filtering Capacitance⁽³⁾

1.6

2.2

Connected from VLDOx to GND,

LDO-mode

7.4.2

7.4.3

7.4.4

C_OUT

4

20

50

µF

Total Capacitance at Output (Local

+ POL), LDO-mode⁽⁴⁾

C_{OUT_TOTAL}

C_{OUT_TOTAL_BYP}

C_{OUT_TOTAL_LSW}

C_ESR

1 MHz < f < 10 MHz

Total Capacitance at Output (Local

+ POL), bypass-mode⁽⁴⁾

Total Capacitance at Output (Local

+ POL), LSW-mode⁽⁴⁾

7.4.5

7.4.6

1 MHz < f < 10 MHz

50

20

µF

Filtering capacitor ESR max

10

mΩ

Timing Requirements

7.5.5

7.5.6

t_{TRANS_1P8_3P3}

t_{TRANS_3P3_1P8}

Transition Time 1.8V - 3.3V

Transition Time 3.3V - 1.8V

V_IN= 4.0V, I_OUT= 300mA

2

ms

(1) PVIN_LDOx must not exceed VSYS

(2) Input capacitors must be placed as close as possible to the device pins.

(3) When DC voltage is applied to a ceramic capacitor, the effective capacitance is reduced due to DC bias effect. The table above

therefore lists the minimum value as CAPACITANCE. In order to meet the minimum capacitance requirement, the nominal value of the

capacitor may have to be scaled accordingly to take the drop of capacitance into account for a given dc voltage at the outputs of

regulators.

(4) Additional capacitance, including local and POL, beyond the specified value can cause the LDO to become unstable

(5) PVIN_LDOx voltage must be within (configured VOUT) and (configured VOUT + 200mV), maximum 3.6V.

6.8 General Purpose LDOs (LDO3, LDO4)

over operating free-air temperature range (unless otherwise noted)

POS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Electrical Characteristics

8.1.1

8.1.2

V_IN

Input Voltage (LDO-mode) ⁽¹⁾

Input Voltage (LSW-mode) ⁽¹⁾

LDO-mode, maximum V_VSYS

LSW-mode, maximum V_VSYS

2.2

5.5

V

LDO Output Voltage configurable

Range

8.1.3

V_OUT

V_IN= 2.2V to 5.5V, maximum V_VSYS

1.2

3.3

V

8.1.4

8.1.5

V_{OUT_STEP}

V_DROPOUT

Output voltage Steps

Dropout Voltage

50

mV

1.2V ≤V_OUT≤3.3V

150

300

V

_INmin≤V_IN≤V_IN, I_OUT= I_OUTmax

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over operating free-air temperature range (unless otherwise noted)

POS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Total DC accuracy including DC

load and line regulation for all valid LDO-mode, V_IN- V_OUT> 300 mV

output voltages

V_{OUT_DC_ACCURA}

8.1.6

1%

–1%

CY

V_{LOAD_REGULATIO}

8.1.6a

1%

DC load regulation, ΔV_OUT

1 mA ≤I_OUT≤I_OUTmax

–1%

N

V

_INmin≤V_IN≤V_INmax, I_OUT

=

8.2.2a V_{LINE_REGULATION}

DC line regulation, ΔV_OUT/ V_OUT

I_OUTmax

8.3.1

8.4.1

I_OUT

C_IN

Output Current

300

mA

µF

Input Filtering Capacitance (2)

2.2

1.6

4.7

2.2

Connected from VLDOx to GND,

LDO-mode

8.4.2

C_OUT

Output Filtering Capacitance ⁽²⁾

4

µF

1 MHz < f < 10 MHz, impedance

between output and point-of-load

maximum 6nH

Total Capacitance at Output (Local

+ POL), fast ramp-time ⁽³⁾

8.4.3a C_{OUT_TOTAL_FAST}

15

1 MHz < f < 10 MHz, impedance

between output and point-of-load

maximum 6nH

Total Capacitance at Output (Local

+ POL), slow ramp-time ⁽³⁾

8.4.3b C_{OUT_TOTAL_SLOW}

30

20

µF

8.4.4

C_ESR

Filtering capacitor ESR max

1MHz to 10MHz

10

mΩ

Timing Requirements

(1) PVIN_LDOx must not exceed VSYS

(2) When DC voltage is applied to a ceramic capacitor, the effective capacitance is reduced due to DC bias effect. The table above

therefore lists the minimum value as CAPACITANCE. In order to meet the minimum capacitance requirement, the nominal value of the

capacitor may have to be scaled accordingly to take the drop of capacitance into account for a given dc voltage at the outputs of

regulators.

(3) Additional capacitance, including local and POL, beyond the specified value can cause the LDO to become unstable

6.9 GPIOs and multi-function pins (EN/PB/VSENSE, nRSTOUT, nINT, GPO1, GPO2, GPIO,

MODE/RESET, MODE/STBY, VSEL_SD/VSEL_DDR)

over operating free-air temperature range (unless otherwise noted)

POS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Electrical Characteristics

Low-level Output Voltage (open-

drain)

VIO = 3.6V, I_OL= 2mA, GPO1,

GPO2, GPIO, nRSTOUT, nINT

9.1.1

9.1.2

V_OL

0.40

0.4

V

EN/PB, MODE/STBY, MODE/

RESET and VSEL_SD/VSEL_DDR,

GPIO

V_IL

Low-level Input Voltage

High-level Input Voltage

EN/PB, MODE/STBY, MODE/

RESET and VSEL_SD/VSEL_DDR,

GPIO

9.1.3

V_IH

1.26

V

VSENSE Comparator Threshold

(EN/PB/VSENSE)

9.1.4

9.1.5

V_VSENSE

1.08

8

1.20

30

1.32

55

V

VSENSE Comparator Hysteresis

(EN/PB/VSENSE)

V_{VSENSE_HYS}

mV

Input leakage current (GPIO,

EN/PB/VSENSE, MODE/STBY,

MODE/RESET, VSEL_SD/VSEL/

DDR)

9.1.6

9.1.7

9.1.8

I_LKG

C_IN

I_PD

V_IN= 3.3 V

1.0

10

35

μA

pF

Internal input pin

capacitance (GPIO, EN/PB/

VSENSE, MODE/STBY, MODE/

RESET, VSEL_SD/VSEL/DDR)

on pins GPO1, GPO2, GPIO,

pull-down current, available 100us MODE/STBY, MODE/RESET,

after VSYS is applied

18

25

nA

VSEL_SD/VSEL_DDR, nINT,

nRSTOUT

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over operating free-air temperature range (unless otherwise noted)

POS

9.1.9

9.1.10 V_{PIN_VSYS_ONLY}

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Pin leakage when VSYS is present,

but digital supply is not

I_{LKG_VSYS_ONLY}

SDA only

1

μA

Pin voltage when VSYS is present, GPO1, GPO2, GPIO, nRSTOUT,

but digital supply is not

0.4

V

nINT, I_OL=2mA

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7 Detailed Description

7.1 Overview

The TPS65220 provides three step-down converters, four LDOs, three general-purpose I/Os and three multi-

Function pins. The system can be supplied by a single cell Li-Ion battery, two primary cells or a regulated supply.

The device is characterized across a -40°C to +125°C temperature range, which makes the PMIC an excellent

choice for various industrial applications.

The I2C interface provides comprehensive features for using TPS65220. All rails, both GPOs and the GPIO can

be enabled or disabled. Voltage thresholds for the undervoltage monitoring can be customized.

The integrated voltage supervisor monitors Buck 1–3 and LDO1–4 for undervoltage. The monitor has two

sensitivity settings. A power good signal is provided to report the successful ramp of the seven rails and GPOs.

The nRSTOUT pin is pulled low until the device enters ACTIVE state. When powering down from ACTIVE- or

STBY-state, nRSTOUT is pulled low again. The nRSTOUT pin has an open-drain output. A fault-pin, nINT,

notifies the SoC about faults.

Buck1 step-down converter can supply up to 3.5 A of current, Buck2 and Buck3 can supply up to 2 A each. The

default output voltages for each converter can be adjusted through the I2C interface. All three buck-converters

feature dynamic voltage scaling. The step-down converters operate in a low power mode at light load or can be

forced into PWM operation for noise sensitive applications.

LDO1 and LDO2 support output currents of 400 mA at an output voltage range of 0.6 V to 3.4 V. These LDOs

support bypass mode, acting as a load-switch, and allow voltage-changes during operation for applications like

SD-card-supply, adjusting the IO-supply of the SD-card from 3.3 V to 1.8 V after initialization.

LDO3 and LDO4 support output currents of 300 mA at an output voltage range of 1.2 V to 3.3 V. These LDOs

support load-switch-mode, but not bypass mode.

The I2C-interface, IOs, GPIOs, and multi-function-pins (MFP) allow a seamless interface to a wide range of

SoCs.

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7.2 Functional Block Diagram

TPS65220

PIN_LDO1

VLDO1

From 1.5-V to VSYS

supply

PVIN_B1

From 2.5-V to VSYS

system power

2.2

F

1.8-V/3.3-V SD-card-IO supply,

0.85V low-power-core supply

or 1.8-V Analog supply

DVS

4.7

F

LDO1

LX_B1_1

LX_B1_2

DVS

(adjustable 0.6V to 3.4V)

0.75-V core supply

(adjustable 0.6V to 3.4V)

10 F (depends on configuration)

Buck1

FB_B1

PIN_LDO2

VLDO2

From 1.5-V to VSYS

supply

2.2

F

1.8-V/3.3-V SD-card-IO supply,

0.85V low-power-core supply

or 1.8-V Analog supply

PVIN_B2

From 2.5-V to VSYS

system power

DVS

LDO2

4.7

10

F

3.3-V IO-supply

(adjustable 0.6V to 3.4V,

(adjustable 0.6V to 3.4V)

LX_B2

FB_B2

DVS

3.3V requires higher min VIN!)

Buck2

F

(depends on configuration)

1.8-V Analog-supply

(adjustable 1.2V to 3.3V)

VLDO3

LDO3

LDO4

PVIN_B3

From 2.5-V to VSYS

system power

2.2

F

4.7

10

F

PIN_LDO34

VLDO4

From 2.2-V to VSYS

supply

LX_B3

FB_B3

1.1-V DDR supply

DVS

(adjustable 0.6V to 3.4V)

F (depends on configuration)

4.7

2.2

F

Buck3

1.8-V IO-supply

(adjustable 1.2V to 3.3V)

FB_B1

FB_B2

Supervisor

and up-/

down-

FB_B3

VLDO1

VLDO2

AGND

VLDO3

VLDO4

sequencer

VSYS

From 2.5-V to 5.5-V

system power

F

VIO

10

2.2

VDD1P8

SCL

SDA

INT LDO

From SOC

2.2

F

I²C

VIO

10

VIO

To / from SOC

10

nRSTOUT

nINT

VIO

10

OD

To SOC

GPO1

GPO2

OD

VIO

To External rail EN

10

VIO

10

DIGITAL

MODE/STBY

From SOC

VIO

10

To External rail EN

or to 2nd TPS65220

GPIO

MODE/RESET

OD

From SOC

PB/EN/

VSENSE

VSYS

VSEL_SD/

VSEL_DDR

Momentary push-button

Thermal

Pad

图7-1. Functional Block Diagram

7.3 Feature Description

7.3.1 Power-Up Sequencing

The TPS65220 allows flexible sequencing of the rails. The order of the rails, including GPO1, GPO2, GPIO for

the external rails, and the nRSTOUT pin is defined by the NVM. Prior to starting the power-up sequence, the

device checks if the voltage on all rails fell below the SCG-threshold to avoid starting into a pre-biased rail. The

sequence is timing based. In addition, the previous rail must have passed the UV-threshold, else the subsequent

rail is not enabled. If UV is masked, the sequence proceeds even if the UV-threshold is not reached. GPO1,

GPO2, GPIO, and LDOs configured in bypass- or LSW-mode are not monitored for under-voltage, thus their

outputs do not gate subsequent rails.

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In case the sequence is interrupted due to an unmasked fault on a rail, the device powers down. The TPS65220

attempts to power up two more times. If both of those re-tries fail to enter ACTIVE state, the device remains in

INITIALIZE state until VSYS is power-cycled. While it is encouraged to keep this retry-counter active, one can

disable it by setting bit MASK_RETRY_COUNT in INT_MASK_UV register.

To disable the retry-counter, set bit MASK_RETRY_COUNT in INT_MASK_UV register. When set, the device

attempts to retry infinitely.

The TPS65220 allows to configure the power-down sequence independent from the power-up sequence. The

sequences are configured in the non-volatile memory.

At initial power-up, the device monitors the VSYS supply voltage and allows power-up and transition to

INITIALZE state only if VSYS passed the VSYS_{POR_Rising}threshold.

The power-up sequence is configured as follows:

• The slot (respectively the position in the sequence) for each rail and GPO1, GPO2, GPIO, and nRSTOUT is

defined using the corresponding *_SEQUENCE_SLOT registers, the four MSB for the power-up sequence,

the four LSB for the power-down sequence.

• The duration of each slot is defined in the POWER_UP_SLOT_DURATION_x registers and can be

configured as 0 ms, 1.5 ms, 3 ms or 10 ms. In total, 16 slots can be configured, allowing the sequence to

span over multiple TPS65220-devices if more rails need to be supported.

• In addition to the timing as defined above, the power-up-sequence is also gated by the UV-monitor: a

subsequent rail only gets enabled after the previous one passed the under-voltage threshold (unless UV is

masked). If a rail has not reached the UV-threshold by the end of t_RAMP(respectively t_{RAMP_LSW}, t_{RAMP_SLOW}

,

t_{RAMP_FAST}), the sequence is aborted and the device sequences down at the end of the slot-duration. For the

respective rail, the device sets INT_BUCK_x_y_IS_SET respectively INT_LDO_x_y_IS_SET bit in

INT_SOURCE register and BUCKx_UV respectively LDOx_UV bit in INT_BUCK_x_y respectively

INT_LDO_x_y register as well as bit TIMEOUT in the INT_TIMEOUT_RV_SD register.

• The initiation of the sequence is gated by the successful discharge of all rails, irrespective if enabled during

the sequence or not. If the device is unable to discharge all rails below the SCG-threshold, the device sets

INT_BUCK_x_y_IS_SET respectively INT_LDO_x_y_IS_SET bit in INT_SOURCE register and BUCKx_RV

respectively LDOx_RV bit if the residual voltage is still present after 4 ms to 5 ms and the device remains in

INITIALIZE state.

• The initiation of the sequence is gated by the die-temperature: if any one of the WARM detections is

unmasked, the device does not power-up until the temperature on all sensors fell below T_{WARM_falling}

threshold if INITIALIZE state was entered due to a thermal event, respectively until the temperature on all

sensors is below T_{WARM_rising}threshold if INITIALIZE state was entered from OFF-state. If all thermal sensors

are masked (WARM detection not causing a power-down), the device does not power-up until the

temperature on all sensors is below T_{HOT_falling}threshold

备注

All rails get discharged prior to enable (irrespective if discharge-function is disabled).

An ON-request is deglitched to not trigger on noise. After the deglitch time, the device takes approximately 300

μs until the first slot of the sequence starts. In case discharging of pre-biased rails is not completed by that time,

the start of the sequence is further gated until all rails have discharged below SCG-voltage level.

Below graphic shows an example for a power-up-sequence.

16

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VSYS & PVIN_Bx

(&PVIN_LDOx)

EEPROM-load, ~2.3ms

ON-request

t_DEGLITCH

*

DVDD3V3 (VDDSHVx)

Buck2

1.5ms **

DVDD1V8 (VDDSHVy) or 2.5V-IO

LDO4 / GPO1

DVDDSHV_MMCx

LDO1

VDDA_1V8

LDO3

~3ms

VDDS_DDR

Buck3

1.5ms

VDD_CORE

Buck1

1.5ms

VDDR_CORE

LDO2

MCU_OSC0_XI

MCU_OSC0_XO

10ms+1.5ms

MCU_PORz

nRSTOUT

10ms

until RESET and

STBY are relevant

External signal or supply

PMIC outputs

*

depends on EN / PB / VSENSE and long/short configuration, ~0 if FSD is enabled

End of

sequence

** if applicable, slot-duration needs to adopt for enable- & ramp-time of external rail

图7-2. Power-up sequencing (example)

For details on ON-requests please see Push Button and Enable Input (PB/EN/VSENSE).

CAUTION

I2C commands must only be issued after EEPROM-load completed.

7.3.2 Power-Down Sequencing

An OFF-request or a shut-down-fault triggers the power-down sequence. The OFF-request can be triggered by a

falling edge on EN/PB/VSENSE if configured for EN or VSENSE respectively a long press of the push-button if

configured as PB or by an I2C-command to I2C_OFF_REQ in MFP_CTRL register. This bit self-clears.

An I2C-triggered shut-down requires a renewed ON-request on the EN/PB/VSENSE pin. In case of EN- or

VSENSE-configuration, a low-going edge followed by a high-going-edge is required on the EN/PB/VSENSE-pin.

The falling-edge deglitch time for EN or VSENSE configuration t_{DEGL_EN/VSENSE_I2C}is shorter than the deglitch-

time for pin-induced OFF-requests (t_{DEGL_EN_Fall}and t_{DEGL_VSENSE_Fall}). The deglitch-times for PB-configuration

remain.

In many cases, the power-down sequence follows the reverse power-up sequence. In some applications, all rails

can be required to shut down at the same time with no delay between rails or require wait-times to allow

discharging of rail.

The power-down sequence is configured as follows:

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• The slot (respectively the position in the sequence) for each rail and GPO1, GPO2, GPIO, and nRSTOUT is

defined using the corresponding *_SEQUENCE_SLOT registers, the four MSB for the ON-sequence, the four

LSB for the down-sequencing.

• The duration of each slot is defined in the POWER_DOWN_SLOT_DURATION_x registers and can be

configured as 0 ms, 1.5 ms, 3 ms or 10 ms. In total, 16 slots can be configured, allowing the sequence to

span over multiple TPS65220-devices if more rails need to be supported.

• In addition to the slot-duration, the power-down sequence is also gated by the previous rail being discharged

below the SCG-threshold, unless active discharge is disabled on the previous rail. If that does not occur, the

power-down of subsequent rails is paused. To allow for power-down in case of biased or shorted rails, the

sequence continues despite an incomplete discharge of the previous rail after eight times the slot-duration (or

12 ms in case of slot-duration of 0 ms).

• To bypass the discharge-check, set the bit BYPASS_RAILS_DISCHARGED_CHECK in register

GENERAL_CONFIG to '1'.

备注

In case active discharge on a rail is disabled, unsuccessful discharge of the rail within the slot duration

does not gate the disable of the subsequent rail, but the sequence is purely timing based. In case of

residual voltage, the RV-bit is be set regardless.

Active discharge is enabled by default and not NVM based. Thus, if desired, discharge need to be disabled after

each VSYS-power-cycle. During RESET or OFF-request, the discharge configuration is not reset, as long as

VSYS is present. However, in INITIALIZE state and prior to the power-up-sequence, all rails get discharged,

regardless of the setting.

During the power-down-sequence, non-EEPROM-backed bits get reset, with the exception of unmasked

interrupt bits and *_DISCHARGE_EN bits.

Below graphic shows an example for a power-down-sequence.

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OFF-request

t_DEGLITCH

MCU_PORz

nRSTOUT

VDDS_DDR

Buck3

VDDR_CORE

LDO2

MCU_OSC0_XI

MCU_OSC0_XO

*

VDD_CORE

Buck1

DVDD1V8 (VDDSHVy) (and/or 2.5V-IO)

LDO4 / GPO1

VDDA_1V8

LDO3

DVDDSHV_MMCx

LDO1

*

DVDD3V3 (VDDSHVx)

Buck2

*

VSYS & PVIN_Bx (& PVIN_LDOx)

External signal or supply

PMIC outputs

* discharge-duration depends on Vout, Cout and load. Slot-duration needs to adopt.

Slot-duration extends up to 8x its configured value.

图7-3. Power-down sequencing (example)

CAUTION

Do not change the registers related to an ongoing sequence by I2C-command!

Non-NVM-bits are not accessible for approximately 80 μs after starting a transition into INITIALIZE

state.

7.3.3 Push Button and Enable Input (EN/PB/VSENSE)

The EN/PB/VSENSE pin is used to enable the PMIC. The pin can be configured in three ways:

• Device enable (EN):

– This pin needs to be pulled high to enable the device. Pulling this pin low disables the device.

– The deglitch-time of the EN-pin is configured by EN_PB_VSENSE_DEGL in MFP_2_CONFIG register.

– The power-up sequence starts if the EN input is above the V_IL-threshold low for the configured

t_{DEGL_EN_Rise}

.

– To signify the power-up based on an EN/PB/VSENSE pin-event, the device sets bit

POWER_UP_FROM_EN_PB_VSENSE in POWER_UP_STATUS_REG register. This bit does not assert

the nINT pin. Write W1C to clear the bit.

– The power-down sequence starts if the EN input is below the V_IH-threshold for t_{DEGL_EN_Fall}

.

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– In case of a shut-down fault, no renewed on-request is required. The device automatically executes the

power-up sequence if EN input is still above the V_IH-threshold. (EN considered level-sensitive)

– In case of a cold reset (regardless if by RESET-pin or I2C-request), no renewed on-request is required.

The device automatically executes the power-up sequence if EN input is still above the V_IH-threshold. (EN

considered level-sensitive)

• Push-Button (PB):

– The PB pin is a CMOS-type input used to power-up the PMIC. Typically, the PB pin is connected to a

momentary switch to ground and an external pullup resistor.

– The hold-time of the push-button is configured by EN_PB_VSENSE_DEGL in MFP_2_CONFIG register.

– The power-up sequence starts if the PB input is below the V_IL-threshold low for the configured t_{PB_ON}

.

– To signify the power-up based on an EN/PB/VSENSE pin-event, the device sets bit

POWER_UP_FROM_EN_PB_VSENSE in POWER_UP_STATUS_REG register. This bit does not assert

the nINT pin. Write W1C to clear the bit.

– The PB pin has a rising-edge deglitch t_{PB_RISE_DEGL}to filter bouncing of the switch

– The power-down sequence starts if the PB input is held low for t_{PB_OFF}-time (not configurable).

– In case of a shut-down fault, no renewed on-request is required. The device automatically executes the

power-up sequence without a PB-press.

– In case of a cold reset (regardless if by RESET-pin or I2C-request), no renewed on-request is required.

The device automatically executes the power-up sequence without a PB-press.

– A push-button press is only recognized after VSYS is above VSYS_POR-threshold or the PB must be held

long enough after VSYS is above VSYS_POR-threshold.

– Following bits in the signify the PB-press events:

• PB_FALLING_EDGE_DETECTED: PB was pressed for for a time-interval longer than t_{PB_INT_DEGL}

since the previous time this bit was cleared. This bit when set, does assert nINT pin (if config bit

MASK_INT_FOR_PB='0'). Write W1C to clear.

• PB_RISING_EDGE_DETECTED: PB was released for a time-interval longer than t_{PB_INT_DEGL}since

the previous time this bit was cleared. This bit when set, does assert nINT pin (if config bit

MASK_INT_FOR_PB='0'). Write W1C to clear.

• PB_REAL_TIME_STATUS: Deglitched (t_{PB_INT_DEGL}) real-time status of PB pin. Valid only when

EN/PB/VSENSE pin is configured as PB. This bit does not assert the nINT pin.

• Power-fail comparator input (VSENSE):

– Connected to a resistor divider from the supply-line of the pre-regulator, this pin can be used to sense the

supply-voltage to the pre-regulator.

– The deglitch-time of the VSENSE-pin is configurable by EN_PB_VSENSE_DEGL in MFP_2_CONFIG

register.

– Power-up is gated by VSYS being above the VSYS_{POR_Rising}-threshold and the VSENSE input is above

the V_VSENSE-threshold (not deglitched)

– The power-up sequence starts if the VSENSE input rises above V_VSENSE

.

– To signify the power-up based on an EN/PB/VSENSE pin-event, the device sets bit

POWER_UP_FROM_EN_PB_VSENSE in POWER_UP_STATUS_REG register. This bit does not assert

the nINT pin. Write W1C to clear the bit.

– The power-down sequence starts if the VSENSE input falls below the V_VSENSE-threshold for

t_{DEGL_VSENSE_Fall}, to avoid an un-sequenced power-off due to the loss of VSYS-supply-voltage.

– In case of a shut-down fault, no renewed on-request is required. The device automatically executes the

power-up sequence if VSENSE input is still above the V_VSENSE-threshold.

– In case of a cold reset (regardless if by RESET-pin or I2C-request), no renewed on-request is required.

The device automatically executes the power-up sequence if VSENSE input is still above the V_VSENSE

-

threshold.

• OFF-request by I2C-command

– An OFF-request can also be triggered by an I2C-command to I2C_OFF_REQ in MFP_CTRL register.

– After such an OFF-request, a new ON-request is required:

• In case of EN-configuration, the EN input requires a rising edge (EN considered edge-sensitive)

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• In case of PB-configuration, the PB needs to be pressed for a valid ON-request

• In case of VSENSE-configuration, the VSENSE input requires a rising edge (VSENSE considered

edge-sensitive). This can be done by power cycling the pre-regulator.

• The falling-edge deglitch time for EN or VSENSE configuration t_{DEGL_EN/VSENSE_I2C}is shorter than the

deglitch-time for pin-induced OFF-requests (t_{DEGL_EN_Fall}and t_{DEGL_VSENSE_Fall}). The deglitch-times for

PB-configuration remain.

• First Supply detection (FSD)

– First Supply detection (FSD) allows power-up as soon as supply voltage is applied, even if EN/PB/

VSENSE pin is at OFF_REQ status.

– FSD can be used in combination with any ON-request configuration, EN, PB or VSENSE.

– FSD can be enabled by setting PU_ON_FSD bit in MFP_2_CONFIG.

– At first power-up the EN/PB/VSENSE pin is treated as if the pin had a valid ON request.

– Once VSYS is above the VSYS_{POR_Rising}-threshold, the PMIC

• loads the EEPROM

• enters INITIALIZE state

• perform the discharge-check

• initiates the power-up-sequence, regardless of the EN/PB/VSENSE-pin-state.

– To signify the power-up based on FSD, the device sets bit POWER_UP_FROM_FSD in

POWER_UP_STATUS_REG register. The nINT-pin does not toggle based on this bit. Write W1C to clear

the bit.

– Thereafter, the EN/PB/VSENSE-pin is treated as if the pin had a valid ON-request, until we enter ACTIVE

state (at the expiration of the last slot in the power-up-sequence).

– After that the device adheres to post-deglitch EN/PB/VSENSE-pin-status: if pin status has changed prior

to entering ACTIVE state or in ACTIVE state, the device does adhere to the pin state. For example, if the

EN/PB/VSENSE-pin is configured for EN, the device does power down in case the EN-pin is low (for

longer than the deglitch time) at the time the device enters ACTIVE state.

– The duration for how long the ON-request is considered valid, regardless of the pin-state, can be

controlled by length of nRSTOUT slot (and empty slots thereafter), as the PMIC enters ACTIVE state only

after the last slot of the sequence expired.

7.3.4 Reset to SoC (nRSTOUT)

The reset output (nRSTOUT) is an open-drain output, intended to release the reset to the SoC or FPGA at the

end of the power-up sequence. The timing for nRSTOUT is configured in the sequence. nRSTOUT is driven low

until the device enters ACTIVE state or when powering-down from ACTIVE- or STBY-state. The pin is driven

high during ACTIVE- and STBY-state.

7.3.5 Low Voltage Buck Converters (Buck2 and Buck3)

The TPS65220 provides two buck converters. Both Buck2 and Buck3 are capable of supporting up to 1.5A of

load current. The buck converters have an input voltage range from 2.5 V to 5.5 V, and can be connected either

directly to the system power or the output of a another buck converter. The output voltage is programmable in

the range of 0.6 V to 3.4 V: in 25mV-steps up to 1.4V, in 100mV-steps between 1.4V and 3.4V.

• The ON/OFF state of the buck converters in ACTIVE state is controlled by the corresponding BUCKx_EN bit

in the ENABLE_CTRL register.

• The ON/OFF state of the buck converters in STBY state is controlled by the corresponding

BUCKx_STBY_EN bit in the STBY_1_CONFIG register.

• In INITIALIZE state, the buck converters are off, regardless of bit-settings.

CAUTION

In case of buck-regulators that are not to be used at all, the FB_Bx pin must be tied to GND and the

LX_Bx pin must be left floating.

• The converters activity can be controlled by the sequencer or through I2C communication.

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Buck-switch-modes:

• Fixed frequency mode

– The converters can be forced into fixed frequency mode for best EMI-control by setting bit

BUCK_FF_ENABLE bit in BUCKS_CONFIG register. If fixed-frequency mode is enabled, the regulators

also support optional spread-spectrum. Spread-spectrum can be enabled by setting bit

BUCK_SS_ENABLE in BUCKS_CONFIG register. Both of these settings are global for all three buck

converters. If fixed-frequency mode is enabled, the regulators support individual out-of-phase switching:

the phase-relation of the buck rails can be configured in 90°-steps in relation to the phase of Buck1 by

BUCKx_PHASE_CONFIG in the BUCKS_CONFIG register. This bit must only change when this regulator

is disabled.

• Quasi-fixed-frequency mode

– The converters can operate in forced-PWM mode, irrespective of load-current, or can be allowed to enter

pulse-frequency-modulation (PFM) for low load-currents. The mode is controlled by either the MODE/

STBY pin or the MODE/RESET pin if either of those is configured as 'MODE', or by an I2C-command to

MODE_I2C_CTRL bit in MFP_1_CONFIG register (see pin-configuration and I2C-command in 'PWM/PFM

and Low Power Modes (MODE/STBY)' and PWM/PFM and Reset (MODE/RESET)' section.

– During a transition to ACTIVE state or to INITIALIZE state, the buck converters are forced to PWM,

irrespective of the pin-state. PFM-entry is only allowed when the device enters ACTIVE state, upon

completion of the sequence and expiration of the last power-up-slot.

– In case of a DVFS-induced output voltage change, the TPS65220 temporarily forces the buck-regulators

into PWM until the voltage change completed. If PFM is allowed, the entry and exit into PFM is load-

current dependent. PFM starts when the inductor current reaches 0 A, which is the case at a load current

approximately calculated by:

– I_LOAD= {[(V_{PVIN_Bx}- V_BUCKx) / L] × (V_BUCKx/ V_{PVIN_Bx}) × (1 / f_SW)} / 2

CAUTION

The user MUST NOT CHANGE the BUCK_FF_ENABLE! The bit is pre-configured by the

manufacturer.

• The converters can be individually configured further for a high-bandwidth-mode for optimum transient-

response or lower bandwidth, allowing minimum output filter capacitance. The selection is done by the

BUCKx_BW_SEL bits in GENERAL_CONFIG register and is available for both configurations, fixed-

frequency and quasi-fixed-frequency. This bit must only change if this regulator is disabled. Please note the

higher output-capacitance requirements for high bandwidth use case!

• If VSEL_SD/VSEL_DRR is configured as 'VSEL_DDR' by the VSEL_DDR_SD bit in MFP_1_CONFIG

register, the output voltage of Buck3 can be controlled by pulling the VSEL_SD/VSEL_DDR pin high, low or

leave the pin floating. These settings supports DDR3LV, DDR4, and DDR4LV supply voltages without an

EEPROM change.

CAUTION

The VSEL_DDR-pin needs to be hard-wired and must not change during operation.

• The buck converters have an active discharge function. The discharge function can be disabled individually

per rail in the DISCHARGE_CONFIG register. If discharge is enabled, the device discharges the output is

discharged to ground whenever a rail is disabled.

• Prior to a sequence into ACTIVE state (from INITIALIZE or STBY state), the device discharges the disabled

rails regardless of the discharge-configuration to avoid starting into a pre-biased output.

• If a rail is enabled by an I2C-command, active discharge is not enforced, but the rail is only enabled if the

output voltage is below the SCG-threshold.

• This register is not EEPROM-backed and does reset if the device enters OFF-state.

• When in INITIALIZE state (during RESET or an I2C-OFF-request), the discharge configuration is not reset.

Note: the power-down-sequence can be violated if the discharge function is disabled.

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All Buck Converters support Dynamic Voltage Frequency Scaling (DVFS). The output-voltage can be changed

during the operation to optimize the operating voltage for the operation point of the SoC in the lower output

voltage range between 0.6 V and 1.4 V. The voltage change is controlled by writing to BUCK1_VOUT

respectively BUCK2_VOUT or BUCK3_VOUT registers. During a DVFS-induced voltage transition, the active

discharge function is temporarily enabled, irrespective of the discharge-configuration.

Output Capacitance Requirements

The buck converters require sufficient output-capacitance for stability. The required minimum and supported

maximum capacitance depends on the configuration:

• for fixed-frequency, low-bandwidth configuration, a minimum capacitance of 12uF is required and a maximum

total capacitance of 36uF is supported

• for quasi-fixed-frequency, low-bandwidth configuration, a minimum capacitance of 10uF is required and a

maximum total capacitance of 75uF is supported

• for fixed-frequency, high-bandwidth configuration, a minimum capacitance of 48uF is required and a

maximum total capacitance of 144uF is supported

• for quasi-fixed-frequency, high-bandwidth configuration, a minimum capacitance of 30uF is required and a

maximum total capacitance of 220uF is supported

Buck Fault Handling

• The TPS65220 detects under voltages on the buck converter outputs. The reaction to the detection of an

under-voltage is dependent on the configuration of the respective BUCKx_UV bit and the MASK_EFFECT bit

in INT_MASK_BUCKS. If not masked, the device sets bit INT_BUCK_1_2_IS_SET respectively

INT_BUCK_3_IS_SET bit in INT_SOURCE register and bit BUCKx_UV in INT_BUCK_1_2 respectively

INT_BUCK_3 register.

During a voltage transition (for example, when triggered by a DVFS induced voltage change), the device

blanks the undervoltage detection by default and activates the undervoltage detection when the voltage

transition completed.

If the device detects an undervoltage during the sequence into ACTIVE state (from INITIALIZE or STBY) and

UV is not masked, the power-down-sequence starts at the end of the current slot.

If the device detects an undervoltage in ACTIVE-state or STBY-state and UV is not masked, the power-down

sequence starts immediately. OC-detection is not maskable.

• The TPS65220 provides cycle-by-cycle current-limit on the buck converter outputs. If the device detects over-

current for t_{DEGLITCH_OC_short}, respectively for t_{DEGLITCH_OC_long}(configurable individually per rail with

EN_LONG_DEGL_FOR_OC_BUCKx in OC_DEGL_CONFIG register; applicable for rising-edge only), the

device sets INT_BUCK_1_2_IS_SET respectively INT_BUCK_3_IS_SET bit in INT_SOURCE register and bit

BUCKx_OC (for positive over-current) respectively BUCKx_NEG_OC (for negative over-current) in

INT_BUCK_1_2 respectively INT_BUCK_3 register.

During a voltage transition (for example, when triggered by a DVFS induced voltage change), the over

current detection is blanked and only gets activated when the voltage transition is completed.

If the over-current occurs during the sequence into ACTIVE state (from INITIALIZE or STBY), the device

disables the affected rail immediately and starts the power-down-sequence at the end of the current slot.

If the over-current occurs in ACTIVE-state or STBY-state, the device disables the affected rail immediately

and starts the power-down sequence.

OC-detection is not maskable, but the deglitch-time is configurable. It is strongly recommended to use

t_{DEGLITCH_OC_short}. Extended over-current can lead to increased aging or overshoot upon recovery.

• The TPS65220 detects short-to-ground (SCG) faults on the buck-outputs. The reaction to the detection of an

SCG event is to set INT_BUCK_1_2_IS_SET respectively INT_BUCK_3_IS_SET bit in INT_SOURCE

register and bit BUCKx_SCG in INT_BUCK_1_2 respectively INT_BUCK_3 register. The affected rail is

disabled immediately. The device sequences down all outputs and transitions into the INITIALIZE state.

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SCG-detection is not maskable.

If a rail gets enabled, the device blanks SCG detection initially to allow the rail to ramp above the SCG-

threshold.

• The TPS65220 detects residual voltage (RV) faults on the buck-outputs. The reaction to the detection of an

RV event is to set INT_RV_IS_SET bit in INT_SOURCE register and bit BUCKx_RV in INT_RV register. The

RV-detection is not maskable, but the nINT-reaction can be configured globally for all rails by

MASK_INT_FOR_RV in INT_MASK_WARM register. The BUCKx_RV-flag is set regardless of masking,

INT_RV_IS_SET bit is only set if nINT is asserted. The fault-reaction time and potential state-transition

depends on the situation when residual voltage is detected:

– If the device detects residual voltage during an ON-request in the INITIALIZE state, the device gates

power-up and the device remains in INITIALIZE state. If the RV-condition exists for more than 4 ms to 5

ms, the device sets BUCKx_RV-bit. If the RV-condition is not present any more, the device transitions to

ACTIVE state.

– If the device detects residual voltage during power-up, ACTIVE_TO_STANDBY, or

STANDBY_TO_ACTIVE sequences, the sequence is aborted and the device powers down.

– If the device detects residual voltage for more than 80 ms on any rail that was disabled during STBY state

during a request to leave STBY state, the device transitions into INITIALIZE state. The device sets the

BUCKx_RV-bit if the condition persists for 4 ms to 5 ms, but less than 80 ms.

– If the device detects residual voltage during power-up, ACTIVE_TO_STANDBY, or

STANDBY_TO_ACTIVE sequences, the sequence is aborted and the device powers down.

– If residual voltage is detected during an EN-command of the rail by I2C, the BUCKx_RV-flag is set

immediately, but no state transition occurs.

• The buck converters have a local over-temperature sensor. The reaction to a temperature warning is

dependent on the configuration of the respective SENSOR_x_WARM_MASK bit in MASK_CONFIG register

and the MASK_EFFECT bits in INT_MASK_BUCKS register. If the temperature at the sensor exceeds

T_{WARM_Rising}and is not masked, the device sets INT_SYSTEM_IS_SET bit in INT_SOURCE register and

SENSOR_x_WARM bit in INT_SYSTEM register. In case the sensor detects a temperature exceeding

T_{HOT_Rising}, the converters power dissipation and junction temperature exceeds safe operating value. The

device powers down all active outputs immediately and sets INT_SYSTEM_IS_SET bit in INT_SOURCE

register and SENSOR_x_HOT bit in INT_SYSTEM register. The TPS65220 automatically recovers once the

temperature drops below the T_{WARM_Falling}threshold value (or below the T_{HOT_Falling}threshold value in case

T_WARM is masked). The _HOT bit remains set and needs to be cleared by writing '1'. The HOT-detection is

not maskable.

CAUTION

The buck can only supply output currents up to the respective current limit, including during start-up.

Depending on the charge-current into the filter- and load-capacitance, the device potentially cannot

drive the full output current to the load while ramping. As a rule of thumb, for a total load-capacitance

exceeding 50 μF, the load current must not exceed 25% of the rated output current. This limit

applies also for dynamic output-voltage changes.

CAUTION

The TPS65220 does not offer differential feedback pins. The device does not support remote

sensing. Since a single-ended trace is susceptible to noise and must be as short as possible and

thus connect directly to the output filter.

表7-1. BUCK output voltage settings

BUCKx_VSET [decimal]

BUCKx_VSET [binary]

BUCKx_VSET [hexadecimal]

VOUT (Buck1 & Buck2 and

Buck3) [V]

0

1

2

000000

000001

000010

00

01

02

0.600

0.625

0.650

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表7-1. BUCK output voltage settings (continued)

BUCKx_VSET [decimal]

BUCKx_VSET [binary]

BUCKx_VSET [hexadecimal]

VOUT (Buck1 & Buck2 and

Buck3) [V]

3

000011

000100

000101

000110

000111

001000

001001

001010

001011

001100

001101

001110

001111

010000

010001

010010

010011

010100

010101

010110

010111

011000

011001

011010

011011

011100

011101

011110

011111

100000

100001

100010

100011

100100

100101

100110

100111

101000

101001

101010

101011

101100

101101

101110

101111

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

0.675

0.700

0.725

0.750

0.775

0.800

0.825

0.850

0.875

0.900

0.925

0.950

0.975

1.000

1.025

1.050

1.075

1.100

1.125

1.150

1.175

1.200

1.225

1.250

1.275

1.300

1.325

1.350

1.375

1.400

1.500

1.600

1.700

1.800

1.900

2.000

2.100

2.200

2.300

2.400

2.500

2.600

2.700

2.800

2.900

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

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表7-1. BUCK output voltage settings (continued)

BUCKx_VSET [decimal]

BUCKx_VSET [binary]

BUCKx_VSET [hexadecimal]

VOUT (Buck1 & Buck2 and

Buck3) [V]

3.000

3.100

3.200

3.300

3.400

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

110000

110001

110010

110011

110100

110101

110110

110111

111000

111001

111010

111011

111100

111101

111110

111111

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

7.3.5.1 Dual Random Spread Spectrum (DRSS)

The bucks provide a digital spread spectrum which reduces the EMI of the power supply over a wide frequency

range. Setting BUCK_SS_ENABLE to 1 enables the spread spectrum on all three bucks. Spread Spectrum is

only applicable if the bucks are configured for fixed frequency, BUCK_FF_ENABLE set to 1. The internal

modulator dithers the internal clock when the spread spectrum is enabled.

DRSS (a) combines a low-frequency triangular modulation profile (b) with a high frequency cycle-by-cycle

random modulation profile (c). The low frequency triangular modulation improves performance in lower radio

frequency bands (for example, the AM band), while the high frequency random modulation improves

performance in higher radio frequency bands (for example, the FM band). In addition, the frequency of the

triangular modulation is further modulated randomly to reduce the likelihood of any audible tones. To minimize

output voltage ripple caused by spread spectrum, duty cycle is modified on a cycle-by-cycle basis to maintain a

nearly constant duty cycle when dithering is enabled. See 图7-4 as an example of the modulation.

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Frequency

(a) Low + High Frequency

Random Modulation

f_SW

(b) Low Frequency

Random Modulation

(c) High Frequency

Random Modulation

Spread Spectrum

Enabled

Spread Spectrum

Disabled

图7-4. Dual Random Spread Spectrum

7.3.6 Linear Regulators (LDO1 through LDO4)

The TPS65220 offers a total of four linear regulators, where LDO1 and LDO2 share their properties and LDO3

and LDO4 share theirs.

LDO1 and LDO2: 400 mA, 0.6 V .. 3.4 V

Both, LDO1 and LDO2 are general-purpose LDOs intended to provide power to analog circuitry on the SOC or

peripherals. The LDOs have an input voltage range from 1.5V to 5.5V, and can be connected either directly to

the system power or the output of a Buck converter. The output voltage is programmable in the range of 0.6V to

3.4V in 50mV-steps. Both LDOs support up to 400 mA. The LDOs can be configured in by-pass-mode, acting as

load-switches. If configured in bypass-mode, the desired output voltage still needs to be specified in

LDOx_VOUT register. The LDOs also support output-voltage changes while enabled, supporting functions like

SD-card-IO-supply, changing from 3.3V to 1.8V after initialization, either in LDO-mode at a supply-voltage above

3.3V or with a 3.3V supply changing between bypass-mode and LDO-mode. The LDOs also support Load-switch

mode (LSW_mode): in this case, output voltages of 1.5V up to 5.5V are supported. The desired voltage does not

need to be configured in the LDOx_VOUT register.

• In case of SD-card-supply, one of the LDOs can be controlled by the VSEL_SD/VSEL_DDR, configured as

VSEL_SD. Which LDO is controlled is selected by VSEL_RAIL bit in MFP_1_CONFIG register. The polarity

of the pin can be configured via VSEL_SD_POLARITY bit in MFP_1_CONFIG register.

Alternatively, an I2C communication to VSEL_SD_I2C_CTRL in MFP_1_CONFIG register controls the

change of the output voltage. Therefore, even if VSEL_SD/VSEL_DDR pin is configured as VSEL_DDR, the

VSEL_RAIL bit still needs to be configured to define which LDO is affected by the I2C-command.

• The LDOs can be configured as linear regulators or operate in bypass-mode or be configured as a load-

switch (LSW-mode). The mode is configured by LDOx_LSW_CONFIG and LSW_BYP_CONFIG bits in

LDOx_VOUT register.

CAUTION

If an LDO is configured in bypass-mode, the output voltage must be configured and the PVIN_LDOx

supply voltage must match the configured output voltage. PVIN_LDOx voltage must be within

(configured VOUT) and (configured VOUT + 200mV). Violation of this can result in instability.

In bypass- or LSW-mode, the LDO acts as a switch, where VOUT is VIN minus the drop over the

FET-resistance (R_BYPASS, R_LSW).

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Output Capacitance Requirements

The LDO regulators require sufficient output-capacitance for stability. The required minimum and supported

maximum capacitance depends on the configuration:

• in LDO-mode, a minimum capacitance of 1.6 uF is required and a maximum total load capacitance (output

filter and point-of-load combined) of 20 uF is supported

• in LSW- or bypass-mode, a minimum capacitance of 1.6 uF is required and a maximum total capacitance

(output filter and point-of-load combined) of 50 uF is supported

LDO3 and LDO4: 300 mA, 1.2 V .. 3.3 V

Both, LDO3 and LDO4 are general-purpose LDOs intended to provide power to analog circuitry on the SoC or

peripherals. The LDOs have an input voltage range from 2.2 V to 5.5 V, and can be connected either directly to

the system power or the output of a Buck converter. Note, these LDOs need a headroom between VSYS and the

LDO-output voltage of minimum 150 mV. The output voltage is programmable in the range of 1.2 V to 3.3 V in 50

mV-steps. Both LDOs support up to 300 mA. The LDOs can be configured to act as load-switches. In this case,

output voltages of 2.2 V up to 5.5 V are supported. The desired voltage does not need to be configured in the

LDOx_VOUT register.

These LDOs support a fast-ramp-mode with limited output capacitance and a slow-ramp-mode, allowing for

larger total load capacitance.

Output Capacitance Requirements

The LDO regulators require sufficient output-capacitance for stability. The required minimum and supported

maximum capacitance depends on the configuration:

• for slow-ramp LDO-mode or LSW-mode, a minimum capacitance of 1.6 uF is required and a maximum total

capacitance (output filter and point-of-load combined) of 30 uF is supported

• for fast-ramp LDO-mode or LSW-mode, a minimum capacitance of 1.6 uF is required and a maximum total

capacitance (output filter and point-of-load combined) of 15 uF is supported

LDO1, LDO2, LDO3 and LDO4

• The ON/OFF state of the LDOs in ACTIVE state is controlled by the corresponding LDOx_EN bit in the

ENABLE_CTRL register.

• The ON/OFF state of the LDOs in STBY state is controlled by the corresponding LDOx_STBY_EN bit in the

STBY_1_CONFIG register.

• In INITIALIZE state, the LDOs are off, regardless of bit-settings.

CAUTION

In case of linear regulators that are not to be used at all, the VLDOx pin must be left floating.

• Each of the LDOs can be configured as linear regulators or be configured as a load-switch (LSW-mode).

LDO1 and LDO2 can also operate in bypass-mode. The mode is configured by LDOx_LSW_CONFIG and

LSW_BYP_CONFIG bits in LDOx_VOUT register individually per regulator.

CAUTION

A mode change between LDO(/bypass) and LSW-mode must only be performed, when the

regulator is disabled!

(A change between LDO and bypass-mode (supported by LDO1 and LDO2 only) is supported

during operation.)

• The LDOs have an active discharge function. Whenever LDOx is disabled, the output is discharged to

ground. The discharge function can be disabled individually per rail in the DISCHARGE_CONFIG register.

• Prior to a sequence into ACTIVE state (from INITIALIZE or STBY state), the device discharges the disabled

rails regardless of the discharge-configuration to avoid starting into a pre-biased output.

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• If a rail is enabled by an I2C-command, active discharge is not enforced, but the rail is only enabled if the

output voltage is below the SCG-threshold.

• This register is not EEPROM-backed and is reset if the device enters OFF-state.

• When in INITIALIZE state (during RESET or an I2C-OFF-request), the discharge configuration is not reset.

Note: the power-down-sequence can be violated if the discharge function is disabled

LDO Fault Handling

• The TPS65220 detects under-voltages on the LDO-outputs. The reaction to the detection of an under-voltage

is dependent on the configuration of the LDOx_UV_MASK bit in INT_MASK_LDOS register and the

MASK_EFFECT in INT_MASK_BUCKS register. If not masked, the device sets bit INT_LDO_1_2_IS_SET

respectively INT_LDO_3_4_IS_SET bit in INT_SOURCE register and bit LDOx_UV in INT_LDO_1_2 register

respectively INT_LDO_3_4 register.

During a voltage transition (at power-up or triggered by toggling VSEL_SD-pin or an I2C-command), the

device blanks the undervoltage detection by default and activates the undervoltage detection when the

voltage transition completed.

If the device detects an undervoltage during the sequence into ACTIVE state (from INITIALIZE or STBY) and

UV is not masked, the power-down-sequence starts at the end of the current slot.

If the device detects an undervoltage in ACTIVE-state or STBY-state and UV is not masked, the power-down

sequence starts immediately. OC-detection is not maskable.

CAUTION

If a LDO is configured in bypass-mode or LSW-mode, UV-detection is not supported.

• The TPS65220 provides current-limit on the LDO-outputs. If the PMIC detects over-current for

t_{DEGLITCH_OC_short}, respectively for t_{DEGLITCH_OC_long}(configurable individually per rail with

EN_LONG_DEGL_FOR_OC_LDOx in OC_DEGL_CONFIG register; applicable for rising-edge only), the

device sets INT_LDO_1_2_IS_SET respectively INT_LDO_3_4_IS_SET bit in INT_SOURCE register and bit

LDOx_OC in INT_LDO_1_2 respectively INT_LDO_3_4 register. The effected rail is disabled immediately.

During a voltage transition (at power-up or triggered by toggling VSEL_SD-pin or an I2C-command), the

overcurrent detection is blanked and gets activated when the voltage transition completed.

If the over-current occurs during the sequence into ACTIVE state (from INITIALIZE or STBY), the device

disables the affected rail immediately and starts the power-down-sequence at the end of the current slot.

If the over-current occurs in ACTIVE-state or STBY-state, the device disables the affected rail immediately

and starts the power-down sequence.

OC-detection is not maskable, but the deglitch-time is configurable. It is strongly recommended to use

t_{DEGLITCH_OC_short}. Extended over-current can lead to increased aging or overshoot upon recovery.

• The TPS65220 detects short-to-ground (SCG) faults on the LDO-outputs. The reaction to the detection of an

SCG event is to set INT_LDO_1_2_IS_SET respectively INT_LDO_3_4_IS_SET bit in INT_SOURCE register

and bit LDOx_SCG in INT_LDO_1_2 register respectively INT_LDO_3_4 register. The affected rail is

disabled immediately. The device sequences down all outputs and transitions into INTIALIZE state.

SCG-detection is not maskable.

If a rail gets enabled, the device blanks SCG detection initially to allow the rail to ramp above the SCG-

threshold.

• The TPS65220 detects residual voltage (RV) faults on the LDO-outputs. The reaction to the detection of an

RV event is to set INT_RV_IS_SET bit in INT_SOURCE register and bit LDOx_RV in INT_RV register. The

RV-detection is not maskable, but the nINT-reaction can be configured globally for all rails by

MASK_INT_FOR_RV in INT_MASK_WARM register. The device sets the LDOx_RV-flag regardless of

masking, INT_RV_IS_SET bit is only set if nINT is asserted. The fault-reaction time and potential state-

transition depends on the situation when the faults are detected:

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– If the device detects residual voltage during an ON-request in the INITIALIZE state, the PMIC gates

power-up and the device remains in INITIALIZE state. If the RV-condition is detected for more than 4 ms

to 5 ms, the device sets the LDOx_RV-bit but remains in INITIALIZE state as long as the RV-condition

exists. If the RV-condition is not present any more, the device transitions to ACTIVE state, provided the

ON-request is still valid.

– If the device detects residual voltage during power-up, ACTIVE_TO_STANDBY, or

STANDBY_TO_ACTIVE sequences, the sequence is aborted and the device powers down.

– If the device detects residual voltage for more than 80 ms on any rail that was disabled during STBY state

during a request to leave STBY state, the device transitions into INITIALIZE state. The device sets the

LDOx_RV-bit if the condition persists for 4 ms to 5 ms, but less than 80 ms.

– If the device detects residual voltage during power-up, ACTIVE_TO_STANDBY, or

STANDBY_TO_ACTIVE sequences, the sequence is aborted and the device powers down.

– If the device detects residual voltage during an EN-command of the rail by I2C, the LDOx_RV-bit is set

immediately, but no state transition occurs.

• The LDOs have a local over-temperature sensor. The reaction to a temperature warning is dependent on the

configuration of the respective SENSOR_x_WARM_MASK bit in and the MASK_EFFECT bit in

INT_MASK_BUCKS register. If the temperature at the sensor exceeds T_{WARM_Rising}and is not masked, the

device sets INT_SYSTEM_IS_SET bit in INT_SOURCE register and SENSOR_x_WARM bit in INT_SYSTEM

register. In case the sensor detects a temperature exceeding T_{HOT_Rising}, the converters power dissipation

and junction temperature exceeds safe operating value. The device powers down all active outputs

immediately and sets INT_SYSTEM_IS_SET bit in INT_SOURCE register and SENSOR_x_HOT bit in

INT_SYSTEM register. The TPS65220 automatically recovers once the temperature drops below the

T_{WARM_FAlling}threshold value (or below the T_{HOT_FAlling}threshold value in case T_WARM is masked). The

_HOT bit remains set and needs to be cleared by writing '1'. The HOT-detection is not maskable.

表7-2. LDO output voltage settings

LDOx_ VSET

[decimal]

LDOx_VSET [binary] LDOx_ VSET [hexa- VOUT (LDO1 and

VOUT (LDO1 and

LDO2, bypass-

mode) [V]

VOUT (LDO3 and

LDO4, LDO mode)

[V]

decimal]

LDO2, LDO mode)

[V]

0

000000

000001

000010

000011

000100

000101

000110

000111

001000

001001

001010

001011

001100

001101

001110

001111

010000

010001

010010

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

0.60

0.65

0.70

0.75

0.80

0.85

0.90

0.95

1.00

1.05

1.10

1.15

1.20

1.25

1.30

1.35

1.40

1.45

1.50

reserved

1.50

1.20

1.25

1.30

1.35

1.40

1.45

1.50

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

12

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表7-2. LDO output voltage settings (continued)

LDOx_ VSET

[decimal]

LDOx_VSET [binary] LDOx_ VSET [hexa- VOUT (LDO1 and

VOUT (LDO1 and

LDO2, bypass-

mode) [V]

VOUT (LDO3 and

LDO4, LDO mode)

[V]

decimal]

LDO2, LDO mode)

[V]

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

010011

010100

010101

010110

010111

011000

011001

011010

011011

011100

011101

011110

011111

100000

100001

100010

100011

100100

100101

100110

100111

101000

101001

101010

101011

101100

101101

101110

101111

110000

110001

110010

110011

110100

110101

110110

110111

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

1.55

1.60

1.65

1.70

1.75

1.80

1.85

1.90

1.95

2.00

2.05

2.10

2.15

2.20

2.25

2.30

2.35

2.40

2.45

2.50

2.55

2.60

2.65

2.70

2.75

2.80

2.85

2.90

2.95

3.00

3.05

3.10

3.15

3.20

3.25

3.30

3.35

1.55

1.60

1.65

1.70

1.75

1.80

1.85

1.90

1.95

2.00

2.05

2.10

2.15

2.20

2.25

2.30

2.35

2.40

2.45

2.50

2.55

2.60

2.65

2.70

2.75

2.80

2.85

2.90

2.95

3.00

3.05

3.10

3.15

3.20

3.25

3.30

3.35

1.55

1.60

1.65

1.70

1.75

1.80

1.85

1.90

1.95

2.00

2.05

2.10

2.15

2.20

2.25

2.30

2.35

2.40

2.45

2.50

2.55

2.60

2.65

2.70

2.75

2.80

2.85

2.90

2.95

3.00

3.05

3.10

3.15

3.20

3.25

3.30

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表7-2. LDO output voltage settings (continued)

LDOx_ VSET

[decimal]

LDOx_VSET [binary] LDOx_ VSET [hexa- VOUT (LDO1 and

VOUT (LDO1 and

LDO2, bypass-

mode) [V]

VOUT (LDO3 and

LDO4, LDO mode)

[V]

decimal]

LDO2, LDO mode)

[V]

56

57

58

59

60

61

62

63

111000

111001

111010

111011

111100

111101

111110

111111

38

39

3A

3B

3C

3D

3E

3F

3.40

3.30

7.3.7 Interrupt Pin (nINT)

During power-up, the output of the nINT pin does depend on whether any INT_SOURCE flags are set and the

configuration of the MASK_EFFECT bit in INT_MASK_BUCKS register-. If one or more flags are set, then nINT

pin is pulled low and is only released high after those flags have been cleared by writing ‘1’ to them. Note,

the nINT-pin can only transition 'high' if a VIO-voltage for the pull-up is available.

In ACTIVE or STBY state, the nINT pin signals any event or fault condition to the host processor. Whenever a

fault or event occurs in the IC, the corresponding interrupt bit is set in the INT register, and the open-drain output

is driven low. In case the device transitions to INITIALIZE state, the nINT pin is pulled low as well, regardless if

the transition is triggered by an OFF-request or a fault.

If the fault is no longer present, a W1C (write '1' to clear) needs to be performed on the failure bits. This

command also allows the nINT-pin to release (return to Hi-Z state).

If a failure persists, the corresponding bit remains set and the INT pin remains low.

The UV-faults can be individually masked per rail in INT_MASK_UV registers. The thermal sensors can

individually be masked by SENSOR_x_WARM_MASK in the MASK_CONFIG register. The effect of the masking

for UV and WARM is defined globally by MASK_EFFECT bits in MASK_CONFIG register.

The nINT reaction for RV-faults is defined globally by MASK_INT_FOR_RV bits in MASK_CONFIG register.

• 00b = no state change, no nINT reaction, no bit set

• 01b = no state change, no nINT reaction, bit set

• 10b = no state change, nINT reaction, bit set (same as 11b)

• 11b = no state change, nINT reaction, bit set (same as 10b)

CAUTION

Masking poses a risk to the device or the system. In case the masking is performed by I2C-

command, the masking bits do get reset to EEPROM-based default after transitioning to INITIALIZE

state. Bits corresponding to faults newly configured via I2C as SD-faults do not get cleared.

It is strongly discouraged to mask OC- and UV-detection on the same rail.

7.3.8 PWM/PFM and Low Power Modes (MODE/STBY)

The TPS65220 supports low power modes through the I2C-control or through the MODE/STBY pin. The

configuration of the pin is selected by MODE_STBY_CONFIG in MFP_2_CONFIG register. The polarity of this

pin can be configured by writing to MODE_STBY_POLARITY in MFP_1_CONFIG register. The polarity-

configuration must not change after power-up. Only either MODE/RESET or MODE/STBY must be configured as

MODE. If both are configured as MODE, MODE/RESET takes priority and MODE/STBY is ignored.

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MODE/STBY configured as 'MODE':

• If configured as 'MODE', the pin-status determines the switching-mode of the buck-converters. This selection

is only applicable in quasi-fixed-frequency mode.

• Forcing this pin for longer than t_{DEGLITCH_MFP}forces the buck-regulators into PWM-mode (irrespective of load

current). De-asserting this pin low allows the buck regulators to enter PFM-mode. The entry into PFM and

exit from PFM is governed by the load current. Only one pin, either MODE/STBY or MODE/RESET must be

configured as 'MODE'.

• The selection of auto-PFM/forced-PWM can also be controlled by writing to the bit MODE_I2C_CTRL in

MFP_1_CONFIG register.

• A change of the MODE does not cause a state-transition.

• During power-up of any one of the three bucks, a MODE change is blanked on this rail and only takes effect

after the ramp completed.

MODE/STBY configured as 'STBY':

• Forcing this pin for longer than t_{DEGLITCH_MFP}sequences down the rails selected to turn off in the

STBY_1_CONFIG respectively the STBY_2_CONFIG register. De-asserting this pin sequences the selected

rails on again.

• A transition into and out of STBY state can also be controlled by writing to the bit STBY_I2C_CTRL in

MFP_CTRL register, provided I2C communication is supported during STBY state.

• A change of the MODE/STBY pin configured as 'STBY' does cause a state-transition by definition.

• Regardless of the pin-setting, the device always powers up into ACTIVE state. The device reacts to the

STBY-pin-state or I2C-commands only after entering ACTIVE state.

MODE/STBY configured as 'MODE & STBY':

• The pin can be configured to perform both functions, MODE and STBY simultaneously

• Forcing this pin for longer than t_{DEGLITCH_MFP}sequences down the rails selected to turn off in the

STBY_1_CONFIG respectively the STBY_2_CONFIG register and allows auto-PFM entry (only applicable in

quasi-fixed-frequency mode). De-asserting this pin sequences the selected rails on again and forces the

buck-regulators to forced-PWM. Polarity settings need to be harmonized for this configuration.

• If a transition into and out of STBY state is commanded by writing to the bit STBY_I2C_CTRL in MFP_CTRL

register (provided I2C communication is supported during STBY state), a separate command for the MODE-

change is required by writing to the bit MODE_I2C_CTRL in MFP_1_CONFIG register.

• A change of the MODE/STBY pin configured as 'MODE&STBY' does cause a state-transition by definition.

• By default STBY is deasserted and the pin is ignored until the device completed the power-up-sequence.

During power-up of any one of the three bucks, a MODE-change is blanked on this rail and only takes effect

after the ramp completed. A state-change commanded by STBY-pin is reacted to even during the ramp of

rails (except during INITIALIZE-to-ACTIVE transition).

Please see the truth-table for pin- and I2C-commands in Section PWM/PFM and Reset (MODE/RESET)

7.3.9 PWM/PFM and Reset (MODE/RESET)

This pin can be configured as an alternative MODE pin (in case MODE/STBY is configured for STBY-function) or

as a RESET pin. The configuration of the pin is selected by MODE_RESET_CONFIG in MFP_2_CONFIG

register. The polarity of this pin can be configured by writing to MODE_RESET_POLARITY in MFP_1_CONFIG

register. The polarity-configuration must not change after power-up. Only MODE/RESET or MODE/STBY must

be configured as MODE. If both are configured as MODE, MODE/RESET takes priority and MODE/STBY is

ignored.

MODE/RESET configured as 'MODE':

• If configured as 'MODE', the pin-status determines the switching-mode of the buck-converters. This selection

is only applicable in quasi-fixed-frequency mode.

• Forcing this pin for longer than t_{DEGLITCH_MFP}forces the buck-regulators into PWM-mode (irrespective of load

current). De-asserting this pin low allows the buck regulators to enter PFM-mode. The entry into PFM and

exit from PFM is governed by the load current. Only one pin, either MODE/STBY or MODE/RESET must be

configured as 'MODE'.

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• The selection of auto-PFM/forced-PWM can also be controlled by writing to the bit MODE_I2C_CTRL in

MFP_1_CONFIG register.

• A change of the MODE does not cause a state-transition.

• During power-up of any one of the three bucks, a MODE-change is blanked on this rail and only takes effect

after the ramp completed.

MODE/RESET configured as 'RESET':

• In RESET configuration, this pin is edge sensitive, but still applies the deglitch time. Consequently, toggling

this pin and holding the pin for longer than t_{DEGLITCH_RESET}causes a reset.

• By default, RESET is deasserted and RESET requests, via pin or I2C, are only serviced if the device is in

ACTIVE state, STBY state, or transitions between these 2 states.

• The TPS65220 supports WARM or COLD reset. The configuration is made by bit

WARM_COLD_RESET_CONFIG in MFP_2_CONFIG register.

– If configured for COLD reset, the device executes the power down sequence and transitions to INITIALIZE

state. Then, EEPROM is reloaded and rails power-up again in normal power-up-sequence, provided there

are no faults and no OFF-request. The execution of a COLD-reset sets the bit COLD_RESET_ISSUED in

POWER_UP_STATUS_REG register. The read-out of this bit allows to track if a COLD-reset was

performed. The bit gets set regardless if the reset was commanded by I2C or by the pin. The nINT-pin

does not toggle based on this bit. Write W1C to clear the bit.

– If configured for WARM reset, all enabled rails remain on, but the output voltage of rails that support

dynamic voltage change is reset to the boot-voltage. Specifically, following configurations get reset to their

boot-value: BUCK1_VSET, BUCK2_VSET, BUCK3_VSET, LDO1_VSET, LDO2_VSET,

LDO1_BYP_CONFIG, LDO2_BYP_CONFIG and VSEL_SD_I2C_CTRL.

All other bits, even in the same register, remain at their current state. For example, LDOx_LSW_CONFIG,

BUCKx_BW_SEL, BUCKx_UV_THR_SEL and the MFP_1_CONFIG register bits do NOT get reset during

a WARM-reset.

WARM Reset cannot override the VSEL_SD-pin command. In other words: even if a WARM Reset occurs,

if the VSEL_SD pin is commanding 1.8V-LDO mode, that remain in effect.

• A reset can also be triggered by writing to the bit WARM_RESET_I2C_CTRL respectively the bit

COLD_RESET_I2C_CTRL in MFP_CTRL register.

备注

Shut-down-faults and OFF-requests take priority over a RESET-request. If a RESET-requests occurs

simultaneously with one of those, the device enters INITIALIZE state and requires a new ON-request

to start up.

Reset requests, via pin or I2c, are only serviced in ACTIVE state, STBY state, or a transition between

these two states.

Please see below truth-table for pin- and I2C-commands.

表7-3. MODE, STBY and RESET configuration

Pin-setting

MODE

STBY

Polarity

Pin-state

I2C-bit

resulting function

forced PWM

auto-PFM

forced PWM

auto-PFM

STBY

MODE/STBY

x

0

1

x

0

x

H

L

H

L

H

L

H

x

STBY

L

STBY

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表7-3. MODE, STBY and RESET configuration (continued)

MODE/STBY

MODE/RESET

STBY

0

1

x

0

1

x

0

1

H

L

H

L

H

L

ACTIVE

STBY

L

ACTIVE

STBY

H

x

STBY

MODE*

RESET

forced PWM

auto-PFM

forced PWM

auto-PFM

RESET

L

H

L

H

x

L

RESET

H

L

ACTIVE

H

RESET

The * for MODE indicates that the MODE/RESET pin takes priority in case both, MODE/RESET and MODE/

STBY are configured as 'MODE', and thus the respective pin to be observed is MODE/RESET.

7.3.10 Voltage Select pin (VSEL_SD/VSEL_DDR)

The function of this pin is configured by VSEL_DDR_SD in MFP_1_CONFIG.

When configured as VSEL_SD, the bit VSEL_RAIL in MFP_1_CONFIG register selects LDO1 or LDO2 to be

controlled by the pin. The configuration must not change after power-up.

VSEL_SD/VSEL_DDR configured as 'VSEL_SD': SD-card-IO-select:

The polarity of this pin can be configured by writing to VSEL_SD_POLARITY in MFP_1_CONFIG register.

Toggling the pin changes the output voltage of the selected LDO between hard-coded 1.8 V and the voltage

configured in LDOx_VOUT. For the SD-card-IO-supply, LDOx_VOUT must be configured for 3.3 V. A change of

the VSEL_SD status does not cause a state-transition.

CAUTION

In SD-card-configuration, customer must configure the pin-polarity and drive the pin so that the LDO

delivers 3.3 V at start-up.

VSEL_SD/VSEL_DDR configured as 'VSEL_DDR':

Pulling this pin high sets the output voltage of Buck3 to 1.35 V (DDR3LV), leaving the pin floating sets the output

voltage of Buck3 to 1.2 V (DDR4, LP-DDR3, some LP-DDR2), pulling the pin low sets the output voltage of the

Buck3 voltage configured in BUCK3_VOUT. For LP-DDR4, BUCK3_VOUT must be configured to 1.1 V.

CAUTION

This function needs to be hard-wired and must not change during operation.

CAUTION

The VSEL_RAIL still needs to be configured for the LDO that supplies the SD-card-IO-voltage, as an

I2C-command toggles the selected LDO-rail for the SD-card. The VSEL_SD_POLARITY bit has no

effect if the pin is configured as VSEL_DDR.

The Table below shows the various combinations.

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表7-4. VSEL_SD/VSEL_DDR configuration options

VSEL_DDR_SD

0:DDR

VSEL_SD_POLARIT VSEL_RAIL

Y

PIN status

VSEL_SD/

VSEL_DDR

Output (V)

BUCK3_VOUT

1.2 V

Rail

n/a

0 =LDO1; 1=LDO2

(needed for I2C

control)

0

BUCK3

0:DDR

n/a

0 =LDO1; 1=LDO2

(needed for I2C

control)

open

1

0:DDR

0 =LDO1; 1=LDO2

(needed for I2C

control)

1.35 V

1:SD

0

1

0

1

0 =LDO1

1 =LDO2

0

1

0

1

0

1

0

1

1.8 V

LDO1

LDO2

LDO1_VOUT

1.8 V

LDO2_VOUT

1.8 V

7.3.11 General Purpose Inputs or Outputs (GPO1, GPO2, and GPIO)

GPO1 and GPO2 pins are always configured as an output.

The GPIO-pin is an input/output, however, the input-functionality is only used in multi-PMIC configuration. In

single-PMIC configuration, the pin can be used as an output. The state can be read by polling the bit

GPIO_STATUS bit in MFP_CTRL register.

The I/O-configuration of the GPIO-pin is done by the MULTI_DEVICE_ENABLE bit in MFP_1_CONFIG register.

If configured as outputs, these pins can be used to sequence external rails. The GP(I)Os can be included in the

sequence or be controlled via I2C-interface, writing to GPOx_EN respectively GPIO_EN bit in

GENERAL_CONFIG register. The GPO is released high if activated.

The GPIO function is to be used if multiple TPS65220 need to be synchronized, in case more rails need to be

supplied. See application section on usage. See section "Multi-PMIC operation" for details.

The polarity of these pins is not changeable.

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7.3.12 I²C-Compatible Interface

The default I²C1 7-bit device address of the TPS65220 is set to 0x30 (0b0110000 in binary), but can be changed

if needed, for example for multi-PMIC-operation.

The I²C-compatible synchronous serial interface provides access to the configurable functions and registers on

the device. This protocol uses a two-wire interface for bidirectional communications between the devices

connected to the bus. The two interface lines are the serial data line (SDA), and the serial clock line (SCL).

Every device on the bus is assigned a unique address and acts as either a controller or a target depending on

whether it generates or receives the serial clock SCL. The SCL and SDA lines must each have a pullup resistor

placed somewhere on the line and remain HIGH even when the bus is idle. The TPS65220 supports standard

mode (100 kHz), fast mode (400 kHz), and fast mode plus (1 MHz) when VIO is 3.3 V or 1.8 V.

7.3.12.1 Data Validity

The data on the SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, the

state of the data line can only be changed when clock signal is LOW.

SCL

SDA

data

change

allowed

data

change

allowed

data

change

allowed

data

valid

data

valid

图7-5. Data Validity Diagram

7.3.12.2 Start and Stop Conditions

The device is controlled through an I²C-compatible interface. START and STOP conditions classify the beginning

and end of the I²C session. A START condition is defined as the SDA signal going from HIGH to LOW while the

SCL signal is HIGH. A STOP condition is defined as the SDA signal going from LOW to HIGH while the SCL

signal is HIGH. The I²C controller device always generates the START and STOP conditions.

SDA

SCL

S

P

START

STOP

Condition

图7-6. Start and Stop Sequences

The I²C bus is considered busy after a START condition and free after a STOP condition. The I²C controller

device can generate repeated START conditions during data transmission. A START and a repeated START

condition are equivalent function-wise. 图 7-7 shows the SDA and SCL signal timing for the I²C-compatible bus.

For timing values, see the Specification section.

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t_BUF

SDA

t_HD;STA

t_rCL

t_fDA

t_rDA

t_SP

t_LOW

t_fCL

SCL

t_HD;STA

t_SU;STA

t_SU;STO

t_HIGH

t_HD;DAT

S

t_SU;DAT

S

RS

P

START

REPEATED

START

STOP

START

图7-7. I²C-Compatible Timing

7.3.12.3 Transferring Data

Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.

Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated

by the controller device. The controller device releases the SDA line (HIGH) during the acknowledge clock pulse.

The device pulls down the SDA line during the 9th clock pulse, signifying an acknowledge. The device generates

an acknowledge after each byte has been received.

There is one exception to the acknowledge after every byte rule. When the controller device is the receiver, it

must indicate to the transmitter an end of data by not-acknowledging (negative acknowledge) the last byte

clocked out of the target device. This negative acknowledge still includes the acknowledge clock pulse

(generated by the controller device), but the SDA line is not pulled down.

After the START condition, the bus controller device sends a chip address. This address is seven bits long

followed by an eighth bit which is a data direction bit (READ or WRITE). For the eighth bit, a 0 indicates a

WRITE and a 1 indicates a READ. The second byte selects the register to which the data is written. The third

byte contains data to write to the selected register. 图 7-8 shows an example bit format of device address

110000-Bin = 60Hex.

MSB

LSB

1

0

R/W

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

I²C Address (chip address)

图7-8. Example Device Address

START

ACK

ACK STOP

I2C_ID[7:1]

0

ADDR[7:0]

WDATA[7:0]

STOP

SCL

SDA

0x60

0x36

0x16

图7-9. I²C Write Cycle without CRC

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REPEATED

START

STOP

NCK

START

ACK

I2C_ID[7:1]

0

ADDR[7:0]

I2C_ID[7:1]

1

RDATA[7:0]

STOP

SCL

0x60

0x36

0x60

0x16

SDA

When READ function is to be accomplished, a WRITE function must precede the READ function as shown above.

图7-10. I²C Read Cycle without CRC

7.4 Device Functional Modes

OFF

Outputs OFF

From any state:

VSYS < VSYS_{POR_Falling}||

VDD1P8 fault

(immediate shut down)

ON_Requests:

(PB = ‘low’ for t > t_{PB_ON}) ||

(EN = ‘high’) ||

(VSENSE > V_VSENSE&& EN = ‘high’)

Monitors off

nRSTOUT

nINT = ‘0’

OFF_Requests:

(PB = ‘low’ for t = t_{PB_OFF}) ||

(EN = ‘low’) ||

(VSENSE < V_VSENSE) ||

(RESET = ‘low’) ||

VSYS > VSYS_{POR_Rising}

!VDD1P8 fault

&

(OFF-request by I2C)

INITIALIZE

From any state or

during transitions:

(OFF_Request) ||

(RESET = low’) ¹⁾

(SD-fault) ¹⁾

(sequencing down)

(HOT = ‘1’)

(ìmmediate shut-down)

Outputs OFF

SD_Faults:

(VSYS > VSYS_OVP) ||

(SCG = ‘1’) ||

Monitors off ²⁾

nRSTOUT

(UV = ‘1’) ^*)||

(WARM = ‘1’) ^*)

(OC = ‘1’) ||

nINT =Fault- & Mask-

dependent

if VIO

is present

(HOT = ‘1’) ||

(RV_SD = ‘1’) ||

(TIMEOUT = ‘1’)

(

^*)unless masked)

Changes to the following bits or pins do not

(necessarily) cause a state-transition:

MODE, VSEL_SD/VSEL_DDR, enabling or

disabling of rails

Configuration dependent

(ON_Request) &

!(SD_fault) &

all rails discharged

(sequencing up)

TIMEOUT

(sequencing down

remaining active rails)

TIMEOUT

(sequencing down)

!STBY-request (polarity configurable)

(sequencing up select rails)

STBY

Selected

Outputs ON

TIMEOUT

(sequencing down)

ACTIVE

Outputs ON

All Monitors on

nRSTOUT

nINT =

Fault- & Mask-

dependent

All Monitors on,

nRSTOUT = ‘1’

nINT =

Fault- & Mask-

dependent

STBY-request (polarity configurable)

(sequencing down select rails)

1) in case of a RESET or a SD-fault, the device transi ons from INITIALIZE state to the ACTIVE state without a new

Push-bu on-ON_Request. In EN or VSENSE con gura on, the ON-request must s ll be valid to transi on to ACTIVE state.

2) If INITIALIZE state was entered due to a Thermal-Shut-Down, the temperature monitors remain ac ve un l the

temperature on all sensors fell below T_WARMthreshold. Thermal-Shut-Down causes immediate shut-shutdown,

no sequencing down

图7-11. State diagram

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7.4.1 Modes of Operation

7.4.1.1 OFF State

In OFF state, the PMIC is insufficiently supplied. Neither internal logic nor external rails are available. If VSYS

exceeds VSYS_POR voltage and the internal 1.8V-rail (VDD1P8) is in regulation, the device enters the

INITIALIZE state.

7.4.1.2 INITIALIZE State

In INITIALIZE state, the device is completely shut down with the exception of a few circuits to monitor the

EN/PB/VSENSE input. Whenever entering the INITIALIZE state, the PMIC reads the memory and loads the

registers to their EEPROM-default values. The I²C communication interface is turned off .

Entry to INITIALIZE state is gated if any one of the thermal sensors is above the T_{WARM_Rising}threshold and

WARM-detection is not masked.

The EEPROM loading takes approximately 2.3 ms. The power-up sequence can only execute after the

EEPROM-load and if all rails are discharged below the V_{BUCKx_SCG_TH}respectively V_{LDOx_SCG_TH}threshold.

If INITIALIZE state was entered from OFF state, bit POWER_UP_FROM_OFF in POWER_UP_STATUS_REG

register is set and remains set until a write-1-clear is issued. Read-out of this bit allows to determine if INITIALZE

state was entered from OFF state or due to a Shut-down-fault or OFF-request.

In INITIALIZE state, the nINT pin status is dependent if faults are and masking thereof. If no faults are present or

nINT-reaction for those are masked, nINT-pin is pulled high, provided a VIO-voltage for the pull-up is available.

To transition from the INITIALIZE state to the ACTIVE state, one of the ON-requests must occur:

• The EN input is 'high' (if EN/PB/VSENSE is configured as 'EN' or 'VSENSE')

• The PB input is pulled low for at least t_{PB_ON_SLOW}respectively t_{PB_ON_FAST}(if EN/PB/VSENSE is configured

as 'PB')

备注

The DISCHARGE_CONFIG register is purposefully omitted from RESET when entering INITIALIZE

state from ACTIVE or STBY state. When entering INITIALIZE state from OFF state, the EEPROM

content is loaded. If the discharge configuration changed after power-up, a different start-up behavior

can occur, depending if the INITIALIZE state was entered from OFF state or from ACTIVE/STBY.

7.4.1.3 ACTIVE State

The ACTIVE state is the normal mode of operation when the system is up and running. All enabled bucks

converters and LDOs are operational and can be controlled through the I2C interface. After a wake-up event, the

PMIC discharges potential residual voltages on the outputs, regardless of the discharge-configuration. ACTIVE

state can also be directly entered from STBY state by de-asserting the STBY pin high or by an I2C command.

See STBY state description for details. To transition to STBY, the STBY pin must be forced or an I2C command

to STBY_I2C_CTRL in MFP_CTRL register must be issued.

To transition to INITIALIZE state, one of the following OFF_Requests must occur:

• The EN input is 'low' (if EN/PB/VSENSE is configured as 'EN' or 'VSENSE')

• The PB input is pulled low for at least t_{PB_OFF}(if EN/PB/VSENSE is configured as 'PB')

• An I2C OFF-request is issued

If a shut-down-fault (SD_Fault) occurs while in the ACTIVE state, TPS65220 sequences down the active outputs

and transition to the INITIALIZE state. The device does transition to ACTIVE state without a new

Push-button-ON_Request. In EN or VSENSE configuration, the ON-request must still be valid to transition to

ACTIVE state.

7.4.1.4 STBY State

STBY state is a low-power mode of operation intended to support system standby. The mode can be entered by

the MODE/STBY pin, if configured as 'STBY' or by an I2C-command to STBY_I2C_CTRL in MFP_CTRL

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register. Typically, the majority of power rails are turned off with the exception of rails required by the SoC during

this state. Which rails power down in STBY state can be configured in STBY_1_CONFIG and STBY_2_CONFIG

register.

The monitoring functions are all available: Under-voltage- (UV), Short-to-GND- (SCG) and Over-current- (OC)

detection, thermal warning (WARM) and thermal-shutdown (TSD/HOT) remain active.

The device enters ACTIVE state if STBY is de-asserted or an I2C command is received (provided VIO-supply

remained active). Before starting the STBY to ACTIVE sequence, disabled rails are discharged. In case this fails

to complete within 80 ms, the device also runs into a timeout-condition and transitions to INITIALIZE state. The

device sets bit TIMEOUT in the INT_TIMEOUT_RV_SD register and the fault flags for the rail that caused the

shut-down.

The sequence into and out of STBY state is the same as for power-down respectively for power-up. Rails that

remain on in STBY are skipped, but their respective slots are still executed.

CAUTION

The device cannot transition from INITIALIZE state to STBY state directly, it must first enter ACTIVE

state.

CAUTION

Only rails that were enabled in ACTIVE state can remain enabled in STBY. Previously disabled rails

cannot be turned on in STBY-state. Activity in STBY-state requires a AND-combination of

LDOx_EN / BUCKx_EN and LDOx_STBY_EN/BUCKx_STBY_EN.

CAUTION

Do not change the registers related to an ongoing sequence by I2C-command!

Non-NVM-bits are not accessible for ~80 us after starting a transition into INITIALIZE state.

7.4.1.5 Fault Handling

Detectable Faults

The TPS65220 offers various fault-detections. Per default, all of them lead to a sequenced shut-down. Some of

them are maskable and the reaction to masked faults is configurable.

The device provides the following fault-detections on the supply voltage (VSYS) and internal voltage supply

(VDD1P8):

• Undervoltage on VSYS, resulting in transition to OFF state or gating start-up

• Overvoltage-protection on VSYS, resulting in transition to OFF state

• Under- or Overvoltage on internal 1.8V-supply (VDD1P8), resulting in transition to OFF state or gating start-

up.

None of these faults are maskable.

The TPS65220 provides the following fault-detections on the buck- and LDO-outputs:

• Undervoltage detection (UV)

• Over Current detection (OC), triggering on positive as well as (for buck-converters) negative current-limit

• Short-to-GND detection (SCG)

• Temperature warning (WARM) and Thermal Shut Down (TSD / HOT)

• Residual Voltage (RV) and Residual Voltage - Shutdown (RV_SD)

• Timeout (TO)

SCG, OC, HOT, RV_SD and TO are not maskable. If any one of those occurs, the device powers down. Positive

and negative current limit share the same mask-bit per regulator.

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The reaction to UV, RV and WARM faults is configurable. If not masked, a fault triggers a sequenced shut-down.

UV, RV and WARM can be masked individually per regulator in INT_MASK_BUCKS, INT_MASK_LDOS and

INT_MASK_WARM registers. No state-transition occurs in case of a masked fault. Whether bits are set and if

nINT is pulled low can be configured globally by MASK_EFFECT bits in MASK_CONFIG register. Positive and

negative current limit share the same mask-bit per regulator.

• 00b = no state change, no nINT reaction, no bit set

• 01b = no state change, no nINT reaction, bit set

• 10b = no state change, nINT reaction, bit set (same as 11b)

• 11b = no state change, nINT reaction, bit set (same as 10b)

For any fault that corresponds to a shut-down condition, the fault-bit remains asserted until a W1C (write-one-

clear) operation is performed via I2C (assuming the fault is not present any more). In case of a shut-down fault,

no renewed on-request is required. The device automatically executes the power up sequence if the fault is no

longer present as long as EN/VSENSE is still high and no PB-press is required for a restart.

For any fault that is not a shut-down condition (for example because the fault is masked), the bit is cleared when

going to the INITIALIZE state.

Thermal Warning and Shutdown

There are two thermal thresholds: Thermal-warning (WARM) and Thermal Shutdown (TSD / HOT).

• Thermal Warning, WARM-threshold:

• if the temperature exceeds T_{WARM_Rising}threshold, the SENSOR_x_WARM-bit is set and the PMIC

sequences down (unless masked).

• if the temperature fell below T_{WARM_Falling}threshold, the device powers up again, without a new

Push-button-ON_Request. In EN or VSENSE configuration, the ON-request must still be valid to transition to

ACTIVE state.

• if the temperature exceeds T_{WARM_Rising}threshold, but SENSOR_x_WARM_MASK bit is /bits are set, the

PMIC remains in ACTIVE state. Fault-reporting occurs as configured by MASK_EFFECT bits. The processor

makes the decision to either sequence the power down or throttles back on the running applications to

reduce the power consumption and hopefully avoiding a Thermal Shutdown situation.

• Thermal Shutdown, HOT-threshold, applicable if WARM-threshold is masked:

• if the temperature exceeds T_{HOT_Rising}threshold, the SENSOR_x_HOT-bit is set and the PMIC powers off all

rails immediately. This power down is simultaneously and not sequenced.

• in case ALL sensors are masked for WARM-detection (all SENSOR_x_WARM_MASK bits are set), the PMIC

does power back up once the temperature drops below the T_{HOT_Falling}threshold, provided a valid ON-

request is present.

• in case any one of the sensors is unmasked for WARM-detection, the PMIC does power back up once the

temperature drops below the T_{WARM_Falling}threshold, without a new

Push-button-ON_Request. In EN or VSENSE configuration, the ON-request must still be valid to transition to

ACTIVE state.

Residual Voltage

Residual voltage checks are performed at various occasions: before starting the INITIALIZE- to ACTIVE-

transition and any time before a rail is enabled, regardless if during the sequence, by I2C-command or during the

STBY- to ACTIVE-transition. RV-checks are also performed during the sequences, to detect if a rail that is

supposed to be disabled is pulled up by another rail. The treatment of RV-faults depends on the situation when

the fault occurs:

• INITIALIZE to ACTIVE:

– if residual voltage is detected for more than 4 ms to 5 ms prior to the execution of the sequence, the

respective INT_RV_IS_SET bit in INT_SOURCE register and LDOx_RV respectively BUCKx_RV bit in

INT_RV register is set and remains set, even if the discharge is successful at a later time and the ON-

request is executed.

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– if the residual voltage is detected during the sequence, this constitutes a shutdown-fault: the device

initiates the power-down-sequence at the end of the slot-duration. The device sets the respective

INT_TIMEOUT_RV_SD_IS_SET bit in INT_SOURCE register, LDOx_RV_SD respectively

BUCKx_RV_SD bit and bit TIMEOUT in INT_TIMEOUT_RV_SD register.

• ACTIVE to STBY:

– if active discharge is enabled and residual voltage is detected after eight times the power-down slot-

duration, this constitutes a shutdown-fault: the device sequences down at the end of the slot. The device

sets INT_TIMEOUT_RV_SD_IS_SET bit in INT_SOURCE register, the LDOx_RV_SD respectively

BUCKx_RV_SD bit and the bit TIMEOUT in INT_TIMEOUT_RV_SD register.

– if the residual voltage is detected during the sequence, this constitutes a shutdown-fault: the device

sequences down at the end of the slot-duration and sets bit INT_TIMEOUT_RV_SD_IS_SET in

INT_SOURCE register and LDOx_RV_SD respectively BUCKx_RV_SD bit in INT_TIMEOUT_RV_SD

register.

• STBY to ACTIVE:

– if residual voltage is detected prior to the execution of the sequence for more than 4 ms to 5 ms, the

device sets INT_RV_IS_SET bit in INT_SOURCE register and LDOx_RV respectively BUCKx_RV bit in

INT_RV register. The bit remains set, even if the discharge is successful before timeout expires and the

STBY-to-ACTIVE-sequence is executed.

– if residual voltage is detected for more than 80 ms prior to the execution of the sequence, this constitutes

a shutdown-fault: the device sequences down and sets the bit INT_TIMEOUT_RV_SD_IS_SET in

INT_SOURCE register and LDOx_RV_SD respectively BUCKx_RV_SD bit in INT_TIMEOUT_RV_SD

register. In addition, the device sets the bit TIMEOUT in INT_TIMEOUT_RV_SD register.

– if the residual voltage is detected during the sequence, this constitutes a shutdown-fault: the device

sequences down at the end of the slot-duration and sets the INT_TIMEOUT_RV_SD_IS_SET bit in

INT_SOURCE register and LDOx_RV_SD respectively BUCKx_RV_SD bit in INT_TIMEOUT_RV_SD

register. The TIMEOUT bit is not set in this case.

• ACTIVE to INITIALIZE or STBY to INITIALIZE

– if the residual voltage is detected at the end of the power-down slot-duration of the respective rail, this

gates the disabling of the subsequent rail for up to eight times the slot-duration, but then the power-

sequence continues regardless of the residual voltage. No bit is set in this case.

• MASKING of RV-bits

– the reaction of the nINT-pin reaction in case of residual voltage detection is maskable for LDOx_RV

respectively BUCKx_RV bits by MASK_INT_FOR_RV bit in MASK_CONFIG register.

– neither the bit nor the shutdown-fault-reaction in case of residual voltage detection is maskable for

LDOx_RV_SD respectively BUCKx_RV_SD bits.

• Timeout

– Timeout occurs if residual voltage cannot be discharged in time. The bit TIMEOUT in

INT_TIMEOUT_RV_SD register is set. See details above.

备注

In case active discharge on a rail is disabled, the unsuccessful discharge of that rail within the slot

duration does not gate the disable of the subsequent rail.

During power-down, the device sets neither RV-bits nor RV_SD-bits for rails with disabled discharge.

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CAUTION

For every detected Shut-Down fault, irrespective if prior to the sequence due to unsuccessful

discharge, during the power-up-sequence or in ACTIVE or STBY state, the retry counter

(RETRY_COUNT in POWER_UP_STATUS_REG register) is incremented. The device attempts two

retries to power-up. If both fail, a power-cycle on VSYS is required to reset the retry counter. Any

successful power-up also resets the retry counter.

If faults are masked and do not cause a shut-down, the retry counter does not increment.

To disable the retry-counter, set bit MASK_RETRY_COUNT in INT_MASK_UV register. When set,

the device attempts to retry infinitely.

Below table gives an overview of the fault-behavior in ACTIVE and STBY states if unmasked and whether a fault

is maskable.

CAUTION

Masking of faults can pose a risk to the device or the system, including but not limited to starting into

a pre-biased output.

It is strongly discouraged to mask OC- and UV-detection on the same rail.

表7-5. Fault Handling

Block

Fault

ACTIVE or STBY state (if fault ACTIVE or STBY state (if fault IS masked)

NOT masked)

BUCK & LDO

Residual voltage - shutdown- Fault triggers a sequenced shut- Not maskable

Fault - RV_SD *)

down to INITIALIZE state

Residual voltage - RV

Fault does not trigger state-

change

Fault does not trigger state-change

Timeout - TO *)

Fault triggers a sequenced shut- Fault does not trigger state-change

down to INITIALIZE state

Undervoltage - UV

Overcurrent - OC

Short-to-GND - SCG

Fault triggers a sequenced shut- Fault does not trigger state-change

down to INITIALIZE state

Fault triggers a sequenced shut- Not maskable

down to INITIALIZE state

Fault triggers a sequenced shut- Not maskable

down to INITIALIZE state

Temperature warning - WARM Fault triggers a sequenced shut- Yes

down to INITIALIZE state

Temperature shut-down - HOT Fault triggers an immediate

shut-down to INITIALIZE state

Not maskable

(not sequenced)

VSYS

Undervoltage - UV

Overvoltage - OV

Fault triggers an immediate

shut-down to OFF state (not

sequenced)

Not maskable

VSYS

Fault triggers an immediate

shut-down to OFF state (not

sequenced)

VDD1P8

Undervoltage or Overvoltage - Fault triggers an immediate

UV or OV

shut-down to OFF state (not

sequenced)

44

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*) RV_SD and TIMEOUT faults can only occur during a sequence

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7.5 Device Registers

表 7-6 lists the memory-mapped registers for the Device registers. All register offset addresses not listed in 表

7-6 should be considered as reserved locations and the register contents should not be modified.

表7-6. DEVICE Registers

Offset Acronym

Register Name

Section

节7.5.1

节7.5.2

节7.5.3

节7.5.4

节7.5.5

节7.5.6

节7.5.7

节7.5.8

节7.5.9

节7.5.10

节7.5.11

节7.5.12

节7.5.13

节7.5.14

节7.5.15

节7.5.16

节7.5.17

节7.5.18

节7.5.19

节7.5.20

节7.5.21

节7.5.22

节7.5.23

0h

1h

TI_DEV_ID

NVM_ID

2h

ENABLE_CTRL

3h

BUCKS_CONFIG

4h

LDO4_VOUT

5h

LDO3_VOUT

6h

LDO2_VOUT

7h

LDO1_VOUT

8h

BUCK3_VOUT

9h

BUCK2_VOUT

Ah

Bh

Ch

Dh

Eh

Fh

BUCK1_VOUT

LDO4_SEQUENCE_SLOT

LDO3_SEQUENCE_SLOT

LDO2_SEQUENCE_SLOT

LDO1_SEQUENCE_SLOT

BUCK3_SEQUENCE_SLOT

BUCK2_SEQUENCE_SLOT

BUCK1_SEQUENCE_SLOT

nRST_SEQUENCE_SLOT

GPIO_SEQUENCE_SLOT

GPO2_SEQUENCE_SLOT

GPO1_SEQUENCE_SLOT

10h

11h

12h

13h

14h

15h

16h

POWER_UP_SLOT_DURATION

_1

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

POWER_UP_SLOT_DURATION

_2

节7.5.24

节7.5.25

节7.5.26

节7.5.27

节7.5.28

节7.5.29

节7.5.30

POWER_UP_SLOT_DURATION

_3

POWER_UP_SLOT_DURATION

_4

POWER_DOWN_SLOT_DURATI

ON_1

POWER_DOWN_SLOT_DURATI

ON_2

POWER_DOWN_SLOT_DURATI

ON_3

POWER_DOWN_SLOT_DURATI

ON_4

1Eh

1Fh

20h

21h

GENERAL_CONFIG

MFP_1_CONFIG

MFP_2_CONFIG

STBY_1_CONFIG

节7.5.31

节7.5.32

节7.5.33

节7.5.34

46

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表7-6. DEVICE Registers (continued)

Offset Acronym

Register Name

Section

节7.5.35

节7.5.36

节7.5.37

节7.5.38

节7.5.39

节7.5.40

22h

23h

24h

25h

26h

27h

STBY_2_CONFIG

OC_DEGL_CONFIG

INT_MASK_UV

MASK_CONFIG

I2C_ADDRESS_REG

USER_GENERAL_NVM_STORA

GE_REG

28h

29h

2Ah

2Bh

2Ch

2Dh

2Eh

2Fh

30h

31h

32h

33h

34h

35h

36h

37h

41h

MANUFACTURING_VER

MFP_CTRL

节7.5.41

节7.5.42

节7.5.43

节7.5.44

节7.5.45

节7.5.46

节7.5.47

节7.5.48

节7.5.49

节7.5.50

节7.5.51

节7.5.52

节7.5.53

节7.5.54

节7.5.55

节7.5.56

节7.5.57

DISCHARGE_CONFIG

INT_SOURCE

INT_LDO_3_4

INT_LDO_1_2

INT_BUCK_3

INT_BUCK_1_2

INT_SYSTEM

INT_RV

INT_TIMEOUT_RV_SD

INT_PB

USER_NVM_CMD_REG

POWER_UP_STATUS_REG

SPARE_2

SPARE_3

FACTORY_CONFIG_2

Complex bit access types are encoded to fit into small table cells. 表 7-7 shows the codes that are used for

access types in this section.

表7-7. Device Access Type Codes

Access Type

Read Type

R

Code

Description

R

Read

Write Type

W

Write

W1C

W

Write

1C

1 to clear

WSelfClrF

W

Write

Reset or Default Value

-n

Value after reset or the default

value

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7.5.1 TI_DEV_ID Register (Offset = 0h) [Reset = 00h]

TI_DEV_ID is shown in 图7-11 and described in 表7-8.

Return to the 表7-6.

图7-12. TI_DEV_ID Register

7

6

5

4

3

2

1

0

TI_DEVICE_ID

R/W-0h

表7-8. TI_DEV_ID Register Field Descriptions

Bit

7-0

Field

TI_DEVICE_ID

Type

Reset

Description

R/W

0h

TI_DEVICE_ID[7]: 0 - TA: -40oC to 105oC, TJ: -40oC to 125oC 1 -

TA: -40oC to 125oC, TJ: -40oC to 150oC TI_DEVICE_ID[6:0] =

Device GPN !!!! Note: This register can be programmed only by the

manufacturer. !!! Refer to Technical Reference Manual / User's Guide

for specific numbering and associated configuration. (Default from

NVM memory)

48

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7.5.2 NVM_ID Register (Offset = 1h) [Reset = 00h]

NVM_ID is shown in 图7-12 and described in 表7-9.

Return to the 表7-6.

图7-13. NVM_ID Register

7

6

5

4

3

2

1

0

TI_NVM_ID

R/W-0h

表7-9. NVM_ID Register Field Descriptions

Bit

7-0

Field

TI_NVM_ID

Type

Reset

Description

R/W

0h

NVM ID of the IC !!! Note: This register can be programmed only by

the manufacturer. !!! Refer to Technical Reference Manual / User's

Guide for specific numbering and associated configuration. (Default

from NVM memory)

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7.5.3 ENABLE_CTRL Register (Offset = 2h) [Reset = X]

ENABLE_CTRL is shown in 图7-13 and described in 表7-10.

Return to the 表7-6.

图7-14. ENABLE_CTRL Register

7

6

5

4

3

2

1

0

RESERVED

R-X

LDO4_EN

R/W-0h

LDO3_EN

R/W-0h

LDO2_EN

R/W-0h

LDO1_EN

R/W-0h

BUCK3_EN

R/W-0h

BUCK2_EN

R/W-0h

BUCK1_EN

R/W-0h

表7-10. ENABLE_CTRL Register Field Descriptions

Bit

7

Field

RESERVED

Type

Reset

Description

R

X

Reserved

6

LDO4_EN

LDO3_EN

LDO2_EN

LDO1_EN

BUCK3_EN

BUCK2_EN

BUCK1_EN

R/W

0h

Enable LDO4 regulator (Default from NVM memory)

0h = Disabled

1h = Enabled

5

4

3

2

1

0

R/W

0h

Enable LDO3 regulator (Default from NVM memory)

0h = Disabled

1h = Enabled

Enable LDO2 regulator (Default from NVM memory)

0h = Disabled

1h = Enabled

Enable LDO1 regulator (Default from NVM memory)

0h = Disabled

1h = Enabled

Enable BUCK3 regulator (Default from NVM memory)

0h = Disabled

1h = Enabled

Enable BUCK2 regulator (Default from NVM memory)

0h = Disabled

1h = Enabled

Enable BUCK1 regulator (Default from NVM memory)

0h = Disabled

1h = Enabled

50

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7.5.4 BUCKS_CONFIG Register (Offset = 3h) [Reset = 00h]

BUCKS_CONFIG is shown in 图7-14 and described in 表7-11.

Return to the 表7-6.

图7-15. BUCKS_CONFIG Register

7

6

5

4

3

2

1

0

USER_NVM_S USER_NVM_S BUCK_SS_EN BUCK_FF_ENA

BUCK3_PHASE_CONFIG

R/W-0h

BUCK2_PHASE_CONFIG

PARE_2

PARE_1

ABLE

BLE

R/W-0h

表7-11. BUCKS_CONFIG Register Field Descriptions

Bit

7

Field

Type

R/W

Reset

Description

USER_NVM_SPARE_2

USER_NVM_SPARE_1

BUCK_SS_ENABLE

0h

Spare bit in user NVM space (Default from NVM memory)

6

0h

5

0h

Spread spectrum enabled on Bucks (only applicable in FF-mode)

(Default from NVM memory)

0h = Spread spectrum disabled

1h = Spread spectrum enabled

4

BUCK_FF_ENABLE

R/W

0h

All Bucks set into fixed frequency mode. !!! NOTE: MUST NOT

CHANGE AT ANY TIME !!! (Default from NVM memory)

0h = Quasi-fixed frequency mode

1h = Fixed frequency mode

3-2

BUCK3_PHASE_CONFIG R/W

Phase of BUCK3 clock. !!! NOTE: ONLY CHANGE WHILE RAIL IS

DISABLED !!! (Default from NVM memory)

0h = 0 degrees (only applicable if Bucks are configured for fixed

frequency)

1h = 90 degrees (only applicable if Bucks are configured for fixed

frequency)

2h = 180 degrees (only applicable if Bucks are configured for fixed

frequency)

3h = 270 degrees

1-0

BUCK2_PHASE_CONFIG R/W

0h

Phase of BUCK2 clock. !!! NOTE: ONLY CHANGE WHILE RAIL IS

DISABLED !!! (Default from NVM memory)

0h = 0 degrees (only applicable if Bucks are configured for fixed

frequency)

1h = 90 degrees (only applicable if Bucks are configured for fixed

frequency)

2h = 180 degrees (only applicable if Bucks are configured for fixed

frequency)

3h = 270 degrees

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7.5.5 LDO4_VOUT Register (Offset = 4h) [Reset = 00h]

LDO4_VOUT is shown in 图7-15 and described in 表7-12.

Return to the 表7-6.

图7-16. LDO4_VOUT Register

7

6

5

4

3

2

1

0

LDO4_SLOW_ LDO4_LSW_C

LDO4_VSET

R/W-0h

PU_RAMP

ONFIG

R/W-0h

表7-12. LDO4_VOUT Register Field Descriptions

Bit

Field

Type

Reset

Description

7

LDO4_SLOW_PU_RAMP R/W

0h

LDO4 Power-up ramp When set high, slows down the power-up

ramp to ~3ms. Cout max 30uF When set low, ramp time is ~660us.

Cout max 15uF (Default from NVM memory)

0h = Fast ramp for power-up (~660us)

1h = Slow ramp for power-up (~3ms)

6

LDO4_LSW_CONFIG

R/W

0h

LDO4 LDO or LSW Mode. !!! NOTE: ONLY CHANGE WHILE RAIL

IS DISABLED !!! (Default from NVM memory)

0h = LDO Mode

1h = LSW Mode

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表7-12. LDO4_VOUT Register Field Descriptions (continued)

Bit

Field

LDO4_VSET

Type

Reset

Description

5-0

R/W

0h

Voltage selection for LDO4. The output voltage range is from 1.2V to

3.3V. (Default from NVM memory)

0h = 1.200V

1h = 1.200V

2h = 1.200V

3h = 1.200V

4h = 1.200V

5h = 1.200V

6h = 1.200V

7h = 1.200V

8h = 1.200V

9h = 1.200V

Ah = 1.200V

Bh = 1.200V

Ch = 1.200V

Dh = 1.250V

Eh = 1.300V

Fh = 1.350V

10h = 1.400V

11h = 1.450V

12h = 1.500V

13h = 1.550V

14h = 1.600V

15h = 1.650V

16h = 1.700V

17h = 1.750V

18h = 1.800V

19h = 1.850V

1Ah = 1.900V

1Bh = 1.950V

1Ch = 2.000V

1Dh = 2.050V

1Eh = 2.100V

1Fh = 2.150V

20h = 2.200V

21h = 2.250V

22h = 2.300V

23h = 2.350V

24h = 2.400V

25h = 2.450V

26h = 2.500V

27h = 2.550V

28h = 2.600V

29h = 2.650V

2Ah = 2.700V

2Bh = 2.750V

2Ch = 2.800V

2Dh = 2.850V

2Eh = 2.900V

2Fh = 2.950V

30h = 3.000V

31h = 3.050V

32h = 3.100V

33h = 3.150V

34h = 3.200V

35h = 3.250V

36h = 3.300V

37h = 3.300V

38h = 3.300V

39h = 3.300V

3Ah = 3.300V

3Bh = 3.300V

3Ch = 3.300V

3Dh = 3.300V

3Eh = 3.300V

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表7-12. LDO4_VOUT Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

3Fh = 3.300V

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7.5.6 LDO3_VOUT Register (Offset = 5h) [Reset = 00h]

LDO3_VOUT is shown in 图7-16 and described in 表7-13.

Return to the 表7-6.

图7-17. LDO3_VOUT Register

7

6

5

4

3

2

1

0

LDO3_SLOW_ LDO3_LSW_C

LDO3_VSET

R/W-0h

PU_RAMP

ONFIG

R/W-0h

表7-13. LDO3_VOUT Register Field Descriptions

Bit

Field

Type

Reset

Description

7

LDO3_SLOW_PU_RAMP R/W

0h

LDO3 Power-up ramp When set high, slows down the power-up

ramp to ~3ms. Cout max 30uF When set low, ramp time is ~660us.

Cout max 15uF (Default from NVM memory)

0h = Fast ramp for power-up (~660us)

1h = Slow ramp for power-up (~3ms)

6

LDO3_LSW_CONFIG

R/W

0h

LDO3 LDO or LSW Mode. !!! NOTE: ONLY CHANGE WHILE RAIL

IS DISABLED !!! (Default from NVM memory)

0h = LDO Mode

1h = LSW Mode

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表7-13. LDO3_VOUT Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

5-0

LDO3_VSET

R/W

0h

Voltage selection for LDO3. The output voltage range is from 1.2V to

3.3V. (Default from NVM memory)

0h = 1.200V

1h = 1.200V

2h = 1.200V

3h = 1.200V

4h = 1.200V

5h = 1.200V

6h = 1.200V

7h = 1.200V

8h = 1.200V

9h = 1.200V

Ah = 1.200V

Bh = 1.200V

Ch = 1.200V

Dh = 1.250V

Eh = 1.300V

Fh = 1.350V

10h = 1.400V

11h = 1.450V

12h = 1.500V

13h = 1.550V

14h = 1.600V

15h = 1.650V

16h = 1.700V

17h = 1.750V

18h = 1.800V

19h = 1.850V

1Ah = 1.900V

1Bh = 1.950V

1Ch = 2.000V

1Dh = 2.050V

1Eh = 2.100V

1Fh = 2.150V

20h = 2.200V

21h = 2.250V

22h = 2.300V

23h = 2.350V

24h = 2.400V

25h = 2.450V

26h = 2.500V

27h = 2.550V

28h = 2.600V

29h = 2.650V

2Ah = 2.700V

2Bh = 2.750V

2Ch = 2.800V

2Dh = 2.850V

2Eh = 2.900V

2Fh = 2.950V

30h = 3.000V

31h = 3.050V

32h = 3.100V

33h = 3.150V

34h = 3.200V

35h = 3.250V

36h = 3.300V

37h = 3.300V

38h = 3.300V

39h = 3.300V

3Ah = 3.300V

3Bh = 3.300V

3Ch = 3.300V

3Dh = 3.300V

3Eh = 3.300V

56

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表7-13. LDO3_VOUT Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

3Fh = 3.300V

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7.5.7 LDO2_VOUT Register (Offset = 6h) [Reset = 00h]

LDO2_VOUT is shown in 图7-17 and described in 表7-14.

Return to the 表7-6.

图7-18. LDO2_VOUT Register

7

6

5

4

3

2

1

0

LDO2_LSW_C LDO2_BYP_CO

LDO2_VSET

R/W-0h

ONFIG

NFIG

R/W-0h

表7-14. LDO2_VOUT Register Field Descriptions

Bit

Field

LDO2_LSW_CONFIG

Type

Reset

Description

7

R/W

0h

LDO2 LDO/Bypass or LSW Mode. !!! NOTE: ONLY CHANGE WHILE

RAIL IS DISABLED !!! (Default from NVM memory)

0h = LDO/BYP Mode: For LDO-Mode set LDO2_EN=1,

LDO2_LSW_CONFIG=0, LDO2_BYP_CONFIG=0 and configure

desired LDO2_VSET. For Bypass-mode set LDO2_EN=1,

LDO2_LSW_CONFIG=0, LDO2_BYP_CONFIG=1 and configure

desired LDO2_VSET

1h = LDO1 configured as Load-switch

6

LDO2_BYP_CONFIG

R/W

0h

LDO2 LDO or Bypass Mode. (Default from NVM memory)

0h = LDO Mode: For LDO-Mode set LDO2_EN=1,

LDO2_LSW_CONFIG=0, LDO2_BYP_CONFIG=0 and configure

desired LDO2_VSET

1h = Bypass Mode: For Bypass-mode set LDO2_EN=1,

LDO2_LSW_CONFIG=0, LDO2_BYP_CONFIG=1 and configure

desired LDO2_VSET

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表7-14. LDO2_VOUT Register Field Descriptions (continued)

Bit

Field

LDO2_VSET

Type

Reset

Description

5-0

R/W

0h

Voltage selection for LDO2. The output voltage range is from 0.6V to

3.4V in LDO-mode and 1.5V to 3.4V in bypass-mode. (Default from

NVM memory)

0h = 0.600V / reserved

1h = 0.650V / reserved

2h = 0.700V / reserved

3h = 0.750V / reserved

4h = 0.800V / reserved

5h = 0.850V / reserved

6h = 0.900V / reserved

7h = 0.950V / reserved

8h = 1.000V / reserved

9h = 1.050V / reserved

Ah = 1.100V / reserved

Bh = 1.150V / reserved

Ch = 1.200V / reserved

Dh = 1.250V / reserved

Eh = 1.300V / reserved

Fh = 1.350V / reserved

10h = 1.400V / reserved

11h = 1.450V / reserved

12h = 1.500V

13h = 1.550V

14h = 1.600V

15h = 1.650V

16h = 1.700V

17h = 1.750V

18h = 1.800V

19h = 1.850V

1Ah = 1.900V

1Bh = 1.950V

1Ch = 2.000V

1Dh = 2.050V

1Eh = 2.100V

1Fh = 2.150V

20h = 2.200V

21h = 2.250V

22h = 2.300V

23h = 2.350V

24h = 2.400V

25h = 2.450V

26h = 2.500V

27h = 2.550V

28h = 2.600V

29h = 2.650V

2Ah = 2.700V

2Bh = 2.750V

2Ch = 2.800V

2Dh = 2.850V

2Eh = 2.900V

2Fh = 2.950V

30h = 3.000V

31h = 3.050V

32h = 3.100V

33h = 3.150V

34h = 3.200V

35h = 3.250V

36h = 3.300V

37h = 3.350V

38h = 3.400V

39h = 3.400V

3Ah = 3.400V

3Bh = 3.400V

3Ch = 3.400V

3Dh = 3.400V

3Eh = 3.400V

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表7-14. LDO2_VOUT Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

3Fh = 3.400V

60

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7.5.8 LDO1_VOUT Register (Offset = 7h) [Reset = 00h]

LDO1_VOUT is shown in 图7-18 and described in 表7-15.

Return to the 表7-6.

图7-19. LDO1_VOUT Register

7

6

5

4

3

2

1

0

LDO1_LSW_C LDO1_BYP_CO

LDO1_VSET

R/W-0h

ONFIG

NFIG

R/W-0h

表7-15. LDO1_VOUT Register Field Descriptions

Bit

Field

LDO1_LSW_CONFIG

Type

Reset

Description

7

R/W

0h

LDO1 LDO/Bypass or LSW Mode. !!! NOTE: ONLY CHANGE WHILE

RAIL IS DISABLED !!! (Default from NVM memory)

0h = LDO/BYP Mode: For LDO-Mode set LDO1_EN=1,

LDO1_LSW_CONFIG=0, LDO1_BYP_CONFIG=0 and configure

desired LDO1_VSET. For Bypass-mode set LDO1_EN=1,

LDO1_LSW_CONFIG=0, LDO1_BYP_CONFIG=1 and configure

desired LDO1_VSET

1h = LDO1 configured as Load-switch

6

LDO1_BYP_CONFIG

R/W

0h

LDO1 LDO or Bypass Mode. (Default from NVM memory)

0h = LDO Mode: For LDO-Mode set LDO1_EN=1,

LDO1_LSW_CONFIG=0, LDO1_BYP_CONFIG=0 and configure

desired LDO1_VSET

1h = Bypass Mode: For Bypass-mode set LDO1_EN=1,

LDO1_LSW_CONFIG=0, LDO1_BYP_CONFIG=1 and configure

desired LDO1_VSET

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表7-15. LDO1_VOUT Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

5-0

LDO1_VSET

R/W

0h

Voltage selection for LDO1. The output voltage range is from 0.6V to

3.4V in LDO-mode and 1.5V to 3.4V in bypass-mode. (Default from

NVM memory)

0h = 0.600V / reserved

1h = 0.650V / reserved

2h = 0.700V / reserved

3h = 0.750V / reserved

4h = 0.800V / reserved

5h = 0.850V / reserved

6h = 0.900V / reserved

7h = 0.950V / reserved

8h = 1.000V / reserved

9h = 1.050V / reserved

Ah = 1.100V / reserved

Bh = 1.150V / reserved

Ch = 1.200V / reserved

Dh = 1.250V / reserved

Eh = 1.300V / reserved

Fh = 1.350V / reserved

10h = 1.400V / reserved

11h = 1.450V / reserved

12h = 1.500V

13h = 1.550V

14h = 1.600V

15h = 1.650V

16h = 1.700V

17h = 1.750V

18h = 1.800V

19h = 1.850V

1Ah = 1.900V

1Bh = 1.950V

1Ch = 2.000V

1Dh = 2.050V

1Eh = 2.100V

1Fh = 2.150V

20h = 2.200V

21h = 2.250V

22h = 2.300V

23h = 2.350V

24h = 2.400V

25h = 2.450V

26h = 2.500V

27h = 2.550V

28h = 2.600V

29h = 2.650V

2Ah = 2.700V

2Bh = 2.750V

2Ch = 2.800V

2Dh = 2.850V

2Eh = 2.900V

2Fh = 2.950V

30h = 3.000V

31h = 3.050V

32h = 3.100V

33h = 3.150V

34h = 3.200V

35h = 3.250V

36h = 3.300V

37h = 3.350V

38h = 3.400V

39h = 3.400V

3Ah = 3.400V

3Bh = 3.400V

3Ch = 3.400V

3Dh = 3.400V

3Eh = 3.400V

62

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表7-15. LDO1_VOUT Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

3Fh = 3.400V

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7.5.9 BUCK3_VOUT Register (Offset = 8h) [Reset = 00h]

BUCK3_VOUT is shown in 图7-19 and described in 表7-16.

Return to the 表7-6.

图7-20. BUCK3_VOUT Register

7

6

5

4

3

2

1

0

BUCK3_BW_S BUCK3_UV_TH

BUCK3_VSET

R/W-0h

EL

R_SEL

R/W-0h

表7-16. BUCK3_VOUT Register Field Descriptions

Bit

Field

Type

Reset

Description

7

BUCK3_BW_SEL

R/W

0h

BUCK3 Bandwidth selection. !!! NOTE: ONLY CHANGE WHILE

RAIL IS DISABLED !!! (Default from NVM memory)

0h = low bandwidth

1h = high bandwidth

6

BUCK3_UV_THR_SEL

R/W

0h

UV threshold selection for BUCK3. (Default from NVM memory)

0h = -5% UV detection level

1h = -10% UV detection level

64

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表7-16. BUCK3_VOUT Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

5-0

BUCK3_VSET

R/W

0h

Voltage selection for BUCK3. The output voltage range is from 0.6V

to 3.4V. (Default from NVM memory)

0h = 0.600V

1h = 0.625V

2h = 0.650V

3h = 0.675V

4h = 0.700V

5h = 0.725V

6h = 0.750V

7h = 0.775V

8h = 0.800V

9h = 0.825V

Ah = 0.850V

Bh = 0.875V

Ch = 0.900V

Dh = 0.925V

Eh = 0.950V

Fh = 0.975V

10h = 1.000V

11h = 1.025V

12h = 1.050V

13h = 1.075V

14h = 1.100V

15h = 1.125V

16h = 1.150V

17h = 1.175V

18h = 1.200V

19h = 1.225V

1Ah = 1.250V

1Bh = 1.275V

1Ch = 1.300V

1Dh = 1.325V

1Eh = 1.350V

1Fh = 1.375V

20h = 1.400V

21h = 1.500V

22h = 1.600V

23h = 1.700V

24h = 1.800V

25h = 1.900V

26h = 2.000V

27h = 2.100V

28h = 2.200V

29h = 2.300V

2Ah = 2.400V

2Bh = 2.500V

2Ch = 2.600V

2Dh = 2.700V

2Eh = 2.800V

2Fh = 2.900V

30h = 3.000V

31h = 3.100V

32h = 3.200V

33h = 3.300V

34h = 3.400V

35h = 3.400V

36h = 3.400V

37h = 3.400V

38h = 3.400V

39h = 3.400V

3Ah = 3.400V

3Bh = 3.400V

3Ch = 3.400V

3Dh = 3.400V

3Eh = 3.400V

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表7-16. BUCK3_VOUT Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

3Fh = 3.400V

66

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7.5.10 BUCK2_VOUT Register (Offset = 9h) [Reset = 00h]

BUCK2_VOUT is shown in 图7-20 and described in 表7-17.

Return to the 表7-6.

图7-21. BUCK2_VOUT Register

7

6

5

4

3

2

1

0

BUCK2_BW_S BUCK2_UV_TH

BUCK2_VSET

R/W-0h

EL

R_SEL

R/W-0h

表7-17. BUCK2_VOUT Register Field Descriptions

Bit

Field

Type

Reset

Description

7

BUCK2_BW_SEL

R/W

0h

BUCK2 Bandwidth selection. !!! NOTE: ONLY CHANGE WHILE

RAIL IS DISABLED !!! (Default from NVM memory)

0h = low bandwidth

1h = high bandwidth

6

BUCK2_UV_THR_SEL

R/W

0h

UV threshold selection for BUCK2. (Default from NVM memory)

0h = -5% UV detection level

1h = -10% UV detection level

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表7-17. BUCK2_VOUT Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

5-0

BUCK2_VSET

R/W

0h

Voltage selection for BUCK2. The output voltage range is from 0.6V

to 3.4V. (Default from NVM memory)

0h = 0.600V

1h = 0.625V

2h = 0.650V

3h = 0.675V

4h = 0.700V

5h = 0.725V

6h = 0.750V

7h = 0.775V

8h = 0.800V

9h = 0.825V

Ah = 0.850V

Bh = 0.875V

Ch = 0.900V

Dh = 0.925V

Eh = 0.950V

Fh = 0.975V

10h = 1.000V

11h = 1.025V

12h = 1.050V

13h = 1.075V

14h = 1.100V

15h = 1.125V

16h = 1.150V

17h = 1.175V

18h = 1.200V

19h = 1.225V

1Ah = 1.250V

1Bh = 1.275V

1Ch = 1.300V

1Dh = 1.325V

1Eh = 1.350V

1Fh = 1.375V

20h = 1.400V

21h = 1.500V

22h = 1.600V

23h = 1.700V

24h = 1.800V

25h = 1.900V

26h = 2.000V

27h = 2.100V

28h = 2.200V

29h = 2.300V

2Ah = 2.400V

2Bh = 2.500V

2Ch = 2.600V

2Dh = 2.700V

2Eh = 2.800V

2Fh = 2.900V

30h = 3.000V

31h = 3.100V

32h = 3.200V

33h = 3.300V

34h = 3.400V

35h = 3.400V

36h = 3.400V

37h = 3.400V

38h = 3.400V

39h = 3.400V

3Ah = 3.400V

3Bh = 3.400V

3Ch = 3.400V

3Dh = 3.400V

3Eh = 3.400V

68

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表7-17. BUCK2_VOUT Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

3Fh = 3.400V

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7.5.11 BUCK1_VOUT Register (Offset = Ah) [Reset = 00h]

BUCK1_VOUT is shown in 图7-21 and described in 表7-18.

Return to the 表7-6.

图7-22. BUCK1_VOUT Register

7

6

5

4

3

2

1

0

BUCK1_BW_S BUCK1_UV_TH

BUCK1_VSET

R/W-0h

EL

R_SEL

R/W-0h

表7-18. BUCK1_VOUT Register Field Descriptions

Bit

Field

Type

Reset

Description

7

BUCK1_BW_SEL

R/W

0h

BUCK1 Bandwidth selection. !!! NOTE: ONLY CHANGE WHILE

RAIL IS DISABLED !!! (Default from NVM memory)

0h = low bandwidth

1h = high bandwidth

6

BUCK1_UV_THR_SEL

R/W

0h

UV threshold selection for BUCK1. (Default from NVM memory)

0h = -5% UV detection level

1h = -10% UV detection level

70

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表7-18. BUCK1_VOUT Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

5-0

BUCK1_VSET

R/W

0h

Voltage selection for BUCK1. The output voltage range is from 0.6V

to 3.4V. (Default from NVM memory)

0h = 0.600V

1h = 0.625V

2h = 0.650V

3h = 0.675V

4h = 0.700V

5h = 0.725V

6h = 0.750V

7h = 0.775V

8h = 0.800V

9h = 0.825V

Ah = 0.850V

Bh = 0.875V

Ch = 0.900V

Dh = 0.925V

Eh = 0.950V

Fh = 0.975V

10h = 1.000V

11h = 1.025V

12h = 1.050V

13h = 1.075V

14h = 1.100V

15h = 1.125V

16h = 1.150V

17h = 1.175V

18h = 1.200V

19h = 1.225V

1Ah = 1.250V

1Bh = 1.275V

1Ch = 1.300V

1Dh = 1.325V

1Eh = 1.350V

1Fh = 1.375V

20h = 1.400V

21h = 1.500V

22h = 1.600V

23h = 1.700V

24h = 1.800V

25h = 1.900V

26h = 2.000V

27h = 2.100V

28h = 2.200V

29h = 2.300V

2Ah = 2.400V

2Bh = 2.500V

2Ch = 2.600V

2Dh = 2.700V

2Eh = 2.800V

2Fh = 2.900V

30h = 3.000V

31h = 3.100V

32h = 3.200V

33h = 3.300V

34h = 3.400V

35h = 3.400V

36h = 3.400V

37h = 3.400V

38h = 3.400V

39h = 3.400V

3Ah = 3.400V

3Bh = 3.400V

3Ch = 3.400V

3Dh = 3.400V

3Eh = 3.400V

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表7-18. BUCK1_VOUT Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

3Fh = 3.400V

72

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7.5.12 LDO4_SEQUENCE_SLOT Register (Offset = Bh) [Reset = 00h]

LDO4_SEQUENCE_SLOT is shown in 图7-22 and described in 表7-19.

Return to the 表7-6.

图7-23. LDO4_SEQUENCE_SLOT Register

7

6

5

4

3

2

1

0

LDO4_SEQUENCE_ON_SLOT

R/W-0h

LDO4_SEQUENCE_OFF_SLOT

R/W-0h

表7-19. LDO4_SEQUENCE_SLOT Register Field Descriptions

Bit

7-4

Field

Type

Reset

Description

LDO4_SEQUENCE_ON_ R/W

SLOT

0h

LDO4 slot number for power-up (Default from NVM memory)

0h = slot 0

1h = slot 1

2h = slot 2

3h = slot 3

4h = slot 4

5h = slot 5

6h = slot 6

7h = slot 7

8h = slot 8

9h = slot 9

Ah = slot 10

Bh = slot 11

Ch = slot 12

Dh = slot 13

Eh = slot 14

Fh = slot 15

3-0

LDO4_SEQUENCE_OFF_ R/W

SLOT

0h

LDO4 slot number for power-down (Default from NVM memory)

0h = slot 0

1h = slot 1

2h = slot 2

3h = slot 3

4h = slot 4

5h = slot 5

6h = slot 6

7h = slot 7

8h = slot 8

9h = slot 9

Ah = slot 10

Bh = slot 11

Ch = slot 12

Dh = slot 13

Eh = slot 14

Fh = slot 15

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7.5.13 LDO3_SEQUENCE_SLOT Register (Offset = Ch) [Reset = 00h]

LDO3_SEQUENCE_SLOT is shown in 图7-23 and described in 表7-20.

Return to the 表7-6.

图7-24. LDO3_SEQUENCE_SLOT Register

7

6

5

4

3

2

1

0

LDO3_SEQUENCE_ON_SLOT

R/W-0h

LDO3_SEQUENCE_OFF_SLOT

R/W-0h

表7-20. LDO3_SEQUENCE_SLOT Register Field Descriptions

Bit

7-4

Field

Type

Reset

Description

LDO3_SEQUENCE_ON_ R/W

SLOT

0h

LDO3 slot number for power-up (Default from NVM memory)

0h = slot 0

1h = slot 1

2h = slot 2

3h = slot 3

4h = slot 4

5h = slot 5

6h = slot 6

7h = slot 7

8h = slot 8

9h = slot 9

Ah = slot 10

Bh = slot 11

Ch = slot 12

Dh = slot 13

Eh = slot 14

Fh = slot 15

3-0

LDO3_SEQUENCE_OFF_ R/W

SLOT

0h

LDO3 slot number for power-down (Default from NVM memory)

0h = slot 0

1h = slot 1

2h = slot 2

3h = slot 3

4h = slot 4

5h = slot 5

6h = slot 6

7h = slot 7

8h = slot 8

9h = slot 9

Ah = slot 10

Bh = slot 11

Ch = slot 12

Dh = slot 13

Eh = slot 14

Fh = slot 15

74

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7.5.14 LDO2_SEQUENCE_SLOT Register (Offset = Dh) [Reset = 00h]

LDO2_SEQUENCE_SLOT is shown in 图7-24 and described in 表7-21.

Return to the 表7-6.

图7-25. LDO2_SEQUENCE_SLOT Register

7

6

5

4

3

2

1

0

LDO2_SEQUENCE_ON_SLOT

R/W-0h

LDO2_SEQUENCE_OFF_SLOT

R/W-0h

表7-21. LDO2_SEQUENCE_SLOT Register Field Descriptions

Bit

7-4

Field

Type

Reset

Description

LDO2_SEQUENCE_ON_ R/W

SLOT

0h

LDO2 slot number for power-up (Default from NVM memory)

0h = slot 0

1h = slot 1

2h = slot 2

3h = slot 3

4h = slot 4

5h = slot 5

6h = slot 6

7h = slot 7

8h = slot 8

9h = slot 9

Ah = slot 10

Bh = slot 11

Ch = slot 12

Dh = slot 13

Eh = slot 14

Fh = slot 15

3-0

LDO2_SEQUENCE_OFF_ R/W

SLOT

0h

LDO2 slot number for power-down (Default from NVM memory)

0h = slot 0

1h = slot 1

2h = slot 2

3h = slot 3

4h = slot 4

5h = slot 5

6h = slot 6

7h = slot 7

8h = slot 8

9h = slot 9

Ah = slot 10

Bh = slot 11

Ch = slot 12

Dh = slot 13

Eh = slot 14

Fh = slot 15

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7.5.15 LDO1_SEQUENCE_SLOT Register (Offset = Eh) [Reset = 00h]

LDO1_SEQUENCE_SLOT is shown in 图7-25 and described in 表7-22.

Return to the 表7-6.

图7-26. LDO1_SEQUENCE_SLOT Register

7

6

5

4

3

2

1

0

LDO1_SEQUENCE_ON_SLOT

R/W-0h

LDO1_SEQUENCE_OFF_SLOT

R/W-0h

表7-22. LDO1_SEQUENCE_SLOT Register Field Descriptions

Bit

7-4

Field

Type

Reset

Description

LDO1_SEQUENCE_ON_ R/W

SLOT

0h

LDO1 slot number for power-up (Default from NVM memory)

0h = slot 0

1h = slot 1

2h = slot 2

3h = slot 3

4h = slot 4

5h = slot 5

6h = slot 6

7h = slot 7

8h = slot 8

9h = slot 9

Ah = slot 10

Bh = slot 11

Ch = slot 12

Dh = slot 13

Eh = slot 14

Fh = slot 15

3-0

LDO1_SEQUENCE_OFF_ R/W

SLOT

0h

LDO1 slot number for power-down (Default from NVM memory)

0h = slot 0

1h = slot 1

2h = slot 2

3h = slot 3

4h = slot 4

5h = slot 5

6h = slot 6

7h = slot 7

8h = slot 8

9h = slot 9

Ah = slot 10

Bh = slot 11

Ch = slot 12

Dh = slot 13

Eh = slot 14

Fh = slot 15

76

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7.5.16 BUCK3_SEQUENCE_SLOT Register (Offset = Fh) [Reset = 00h]

BUCK3_SEQUENCE_SLOT is shown in 图7-26 and described in 表7-23.

Return to the 表7-6.

图7-27. BUCK3_SEQUENCE_SLOT Register

7

6

5

4

3

2

1

0

BUCK3_SEQUENCE_ON_SLOT

R/W-0h

BUCK3_SEQUENCE_OFF_SLOT

R/W-0h

表7-23. BUCK3_SEQUENCE_SLOT Register Field Descriptions

Bit

7-4

Field

Type

Reset

Description

BUCK3_SEQUENCE_ON R/W

_SLOT

0h

BUCK3 slot number for power-up (Default from NVM memory)

0h = slot 0

1h = slot 1

2h = slot 2

3h = slot 3

4h = slot 4

5h = slot 5

6h = slot 6

7h = slot 7

8h = slot 8

9h = slot 9

Ah = slot 10

Bh = slot 11

Ch = slot 12

Dh = slot 13

Eh = slot 14

Fh = slot 15

3-0

BUCK3_SEQUENCE_OF R/W

F_SLOT

0h

BUCK3 slot number for power-down (Default from NVM memory)

0h = slot 0

1h = slot 1

2h = slot 2

3h = slot 3

4h = slot 4

5h = slot 5

6h = slot 6

7h = slot 7

8h = slot 8

9h = slot 9

Ah = slot 10

Bh = slot 11

Ch = slot 12

Dh = slot 13

Eh = slot 14

Fh = slot 15

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7.5.17 BUCK2_SEQUENCE_SLOT Register (Offset = 10h) [Reset = 00h]

BUCK2_SEQUENCE_SLOT is shown in 图7-27 and described in 表7-24.

Return to the 表7-6.

图7-28. BUCK2_SEQUENCE_SLOT Register

7

6

5

4

3

2

1

0

BUCK2_SEQUENCE_ON_SLOT

R/W-0h

BUCK2_SEQUENCE_OFF_SLOT

R/W-0h

表7-24. BUCK2_SEQUENCE_SLOT Register Field Descriptions

Bit

7-4

Field

Type

Reset

Description

BUCK2_SEQUENCE_ON R/W

_SLOT

0h

BUCK2 Slot number for power-up (Default from NVM memory)

0h = slot 0

1h = slot 1

2h = slot 2

3h = slot 3

4h = slot 4

5h = slot 5

6h = slot 6

7h = slot 7

8h = slot 8

9h = slot 9

Ah = slot 10

Bh = slot 11

Ch = slot 12

Dh = slot 13

Eh = slot 14

Fh = slot 15

3-0

BUCK2_SEQUENCE_OF R/W

F_SLOT

0h

BUCK2 slot number for power-down (Default from NVM memory)

0h = slot 0

1h = slot 1

2h = slot 2

3h = slot 3

4h = slot 4

5h = slot 5

6h = slot 6

7h = slot 7

8h = slot 8

9h = slot 9

Ah = slot 10

Bh = slot 11

Ch = slot 12

Dh = slot 13

Eh = slot 14

Fh = slot 15

78

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7.5.18 BUCK1_SEQUENCE_SLOT Register (Offset = 11h) [Reset = 00h]

BUCK1_SEQUENCE_SLOT is shown in 图7-28 and described in 表7-25.

Return to the 表7-6.

图7-29. BUCK1_SEQUENCE_SLOT Register

7

6

5

4

3

2

1

0

BUCK1_SEQUENCE_ON_SLOT

R/W-0h

BUCK1_SEQUENCE_OFF_SLOT

R/W-0h

表7-25. BUCK1_SEQUENCE_SLOT Register Field Descriptions

Bit

7-4

Field

Type

Reset

Description

BUCK1_SEQUENCE_ON R/W

_SLOT

0h

BUCK1 Slot number for power-up (Default from NVM memory)

0h = slot 0

1h = slot 1

2h = slot 2

3h = slot 3

4h = slot 4

5h = slot 5

6h = slot 6

7h = slot 7

8h = slot 8

9h = slot 9

Ah = slot 10

Bh = slot 11

Ch = slot 12

Dh = slot 13

Eh = slot 14

Fh = slot 15

3-0

BUCK1_SEQUENCE_OF R/W

F_SLOT

0h

BUCK1 slot number for power-down (Default from NVM memory)

0h = slot 0

1h = slot 1

2h = slot 2

3h = slot 3

4h = slot 4

5h = slot 5

6h = slot 6

7h = slot 7

8h = slot 8

9h = slot 9

Ah = slot 10

Bh = slot 11

Ch = slot 12

Dh = slot 13

Eh = slot 14

Fh = slot 15

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7.5.19 nRST_SEQUENCE_SLOT Register (Offset = 12h) [Reset = 00h]

nRST_SEQUENCE_SLOT is shown in 图7-29 and described in 表7-26.

Return to the 表7-6.

图7-30. nRST_SEQUENCE_SLOT Register

7

6

5

4

3

2

1

0

nRST_SEQUENCE_ON_SLOT

R/W-0h

nRST_SEQUENCE_OFF_SLOT

R/W-0h

表7-26. nRST_SEQUENCE_SLOT Register Field Descriptions

Bit

7-4

Field

Type

Reset

Description

nRST_SEQUENCE_ON_ R/W

SLOT

0h

nRST slot number for power-up (Default from NVM memory)

0h = slot 0

1h = slot 1

2h = slot 2

3h = slot 3

4h = slot 4

5h = slot 5

6h = slot 6

7h = slot 7

8h = slot 8

9h = slot 9

Ah = slot 10

Bh = slot 11

Ch = slot 12

Dh = slot 13

Eh = slot 14

Fh = slot 15

3-0

nRST_SEQUENCE_OFF_ R/W

SLOT

0h

nRST slot number for power-down (Default from NVM memory)

0h = slot 0

1h = slot 1

2h = slot 2

3h = slot 3

4h = slot 4

5h = slot 5

6h = slot 6

7h = slot 7

8h = slot 8

9h = slot 9

Ah = slot 10

Bh = slot 11

Ch = slot 12

Dh = slot 13

Eh = slot 14

Fh = slot 15

80

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7.5.20 GPIO_SEQUENCE_SLOT Register (Offset = 13h) [Reset = 00h]

GPIO_SEQUENCE_SLOT is shown in 图7-30 and described in 表7-27.

Return to the 表7-6.

图7-31. GPIO_SEQUENCE_SLOT Register

7

6

5

4

3

2

1

0

GPIO_SEQUENCE_ON_SLOT

R/W-0h

GPIO_SEQUENCE_OFF_SLOT

R/W-0h

表7-27. GPIO_SEQUENCE_SLOT Register Field Descriptions

Bit

7-4

Field

Type

Reset

Description

GPIO_SEQUENCE_ON_ R/W

SLOT

0h

GPIO slot number for power-up (Default from NVM memory)

0h = slot 0

1h = slot 1

2h = slot 2

3h = slot 3

4h = slot 4

5h = slot 5

6h = slot 6

7h = slot 7

8h = slot 8

9h = slot 9

Ah = slot 10

Bh = slot 11

Ch = slot 12

Dh = slot 13

Eh = slot 14

Fh = slot 15

3-0

GPIO_SEQUENCE_OFF_ R/W

SLOT

0h

GPIO slot number for power-down (Default from NVM memory)

0h = slot 0

1h = slot 1

2h = slot 2

3h = slot 3

4h = slot 4

5h = slot 5

6h = slot 6

7h = slot 7

8h = slot 8

9h = slot 9

Ah = slot 10

Bh = slot 11

Ch = slot 12

Dh = slot 13

Eh = slot 14

Fh = slot 15

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7.5.21 GPO2_SEQUENCE_SLOT Register (Offset = 14h) [Reset = 00h]

GPO2_SEQUENCE_SLOT is shown in 图7-31 and described in 表7-28.

Return to the 表7-6.

图7-32. GPO2_SEQUENCE_SLOT Register

7

6

5

4

3

2

1

0

GPO2_SEQUENCE_ON_SLOT

R/W-0h

GPO2_SEQUENCE_OFF_SLOT

R/W-0h

表7-28. GPO2_SEQUENCE_SLOT Register Field Descriptions

Bit

7-4

Field

Type

Reset

Description

GPO2_SEQUENCE_ON_ R/W

SLOT

0h

GPO2 slot number for power-up (Default from NVM memory)

0h = slot 0

1h = slot 1

2h = slot 2

3h = slot 3

4h = slot 4

5h = slot 5

6h = slot 6

7h = slot 7

8h = slot 8

9h = slot 9

Ah = slot 10

Bh = slot 11

Ch = slot 12

Dh = slot 13

Eh = slot 14

Fh = slot 15

3-0

GPO2_SEQUENCE_OFF R/W

_SLOT

0h

GPO2 slot number for power-down (Default from NVM memory)

0h = slot 0

1h = slot 1

2h = slot 2

3h = slot 3

4h = slot 4

5h = slot 5

6h = slot 6

7h = slot 7

8h = slot 8

9h = slot 9

Ah = slot 10

Bh = slot 11

Ch = slot 12

Dh = slot 13

Eh = slot 14

Fh = slot 15

82

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7.5.22 GPO1_SEQUENCE_SLOT Register (Offset = 15h) [Reset = 00h]

GPO1_SEQUENCE_SLOT is shown in 图7-32 and described in 表7-29.

Return to the 表7-6.

图7-33. GPO1_SEQUENCE_SLOT Register

7

6

5

4

3

2

1

0

GPO1_SEQUENCE_ON_SLOT

R/W-0h

GPO1_SEQUENCE_OFF_SLOT

R/W-0h

表7-29. GPO1_SEQUENCE_SLOT Register Field Descriptions

Bit

7-4

Field

Type

Reset

Description

GPO1_SEQUENCE_ON_ R/W

SLOT

0h

GPO1 slot number for power-up (Default from NVM memory)

0h = slot 0

1h = slot 1

2h = slot 2

3h = slot 3

4h = slot 4

5h = slot 5

6h = slot 6

7h = slot 7

8h = slot 8

9h = slot 9

Ah = slot 10

Bh = slot 11

Ch = slot 12

Dh = slot 13

Eh = slot 14

Fh = slot 15

3-0

GPO1_SEQUENCE_OFF R/W

_SLOT

0h

GPO1 slot number for power-down (Default from NVM memory)

0h = slot 0

1h = slot 1

2h = slot 2

3h = slot 3

4h = slot 4

5h = slot 5

6h = slot 6

7h = slot 7

8h = slot 8

9h = slot 9

Ah = slot 10

Bh = slot 11

Ch = slot 12

Dh = slot 13

Eh = slot 14

Fh = slot 15

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7.5.23 POWER_UP_SLOT_DURATION_1 Register (Offset = 16h) [Reset = 00h]

POWER_UP_SLOT_DURATION_1 is shown in 图7-33 and described in 表7-30.

Return to the 表7-6.

图7-34. POWER_UP_SLOT_DURATION_1 Register

7

6

5

4

3

2

1

0

POWER_UP_SLOT_0_DURATIO POWER_UP_SLOT_1_DURATIO POWER_UP_SLOT_2_DURATIO POWER_UP_SLOT_3_DURATIO

N

R/W-0h

表7-30. POWER_UP_SLOT_DURATION_1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

POWER_UP_SLOT_0_D R/W

URATION

0h

Duration of slot 0 during the power-up and standby-to-active

sequences. (Default from NVM memory)

0h = 0ms

1h = 1.5ms

2h = 3ms

3h = 10ms

5-4

3-2

1-0

POWER_UP_SLOT_1_D R/W

URATION

0h

Duration of slot 1 during the power-up and standby-to-active

sequences. (Default from NVM memory)

0h = 0ms

1h = 1.5ms

2h = 3ms

3h = 10ms

POWER_UP_SLOT_2_D R/W

URATION

Duration of slot 2 during the power-up and standby-to-active

sequences. (Default from NVM memory)

0h = 0ms

1h = 1.5ms

2h = 3ms

3h = 10ms

POWER_UP_SLOT_3_D R/W

URATION

Duration of slot 3 during the power-up and standby-to-active

sequences. (Default from NVM memory)

0h = 0ms

1h = 1.5ms

2h = 3ms

3h = 10ms

84

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7.5.24 POWER_UP_SLOT_DURATION_2 Register (Offset = 17h) [Reset = 00h]

POWER_UP_SLOT_DURATION_2 is shown in 图7-34 and described in 表7-31.

Return to the 表7-6.

图7-35. POWER_UP_SLOT_DURATION_2 Register

7

6

5

4

3

2

1

0

POWER_UP_SLOT_4_DURATIO POWER_UP_SLOT_5_DURATIO POWER_UP_SLOT_6_DURATIO POWER_UP_SLOT_7_DURATIO

N

R/W-0h

表7-31. POWER_UP_SLOT_DURATION_2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

POWER_UP_SLOT_4_D R/W

URATION

0h

Duration of slot 4 during the power-up and standby-to-active

sequences. (Default from NVM memory)

0h = 0ms

1h = 1.5ms

2h = 3ms

3h = 10ms

5-4

3-2

1-0

POWER_UP_SLOT_5_D R/W

URATION

0h

Duration of slot 5 during the power-up and standby-to-active

sequences. (Default from NVM memory)

0h = 0ms

1h = 1.5ms

2h = 3ms

3h = 10ms

POWER_UP_SLOT_6_D R/W

URATION

Duration of slot 6 during the power-up and standby-to-active

sequences. (Default from NVM memory)

0h = 0ms

1h = 1.5ms

2h = 3ms

3h = 10ms

POWER_UP_SLOT_7_D R/W

URATION

Duration of slot 7 during the power-up and standby-to-active

sequences. (Default from NVM memory)

0h = 0ms

1h = 1.5ms

2h = 3ms

3h = 10ms

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7.5.25 POWER_UP_SLOT_DURATION_3 Register (Offset = 18h) [Reset = 00h]

POWER_UP_SLOT_DURATION_3 is shown in 图7-35 and described in 表7-32.

Return to the 表7-6.

图7-36. POWER_UP_SLOT_DURATION_3 Register

7

6

5

4

3

2

1

0

POWER_UP_SLOT_8_DURATIO POWER_UP_SLOT_9_DURATIO POWER_UP_SLOT_10_DURATI POWER_UP_SLOT_11_DURATI

N

ON

R/W-0h

表7-32. POWER_UP_SLOT_DURATION_3 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

POWER_UP_SLOT_8_D R/W

URATION

0h

Duration of slot 8 during the power-up and standby-to-active

sequences. (Default from NVM memory)

0h = 0ms

1h = 1.5ms

2h = 3ms

3h = 10ms

5-4

3-2

1-0

POWER_UP_SLOT_9_D R/W

URATION

0h

Duration of slot 9 during the power-up and standby-to-active

sequences. (Default from NVM memory)

0h = 0ms

1h = 1.5ms

2h = 3ms

3h = 10ms

POWER_UP_SLOT_10_D R/W

URATION

Duration of slot 10 during the power-up and standby-to-active

sequences. (Default from NVM memory)

0h = 0ms

1h = 1.5ms

2h = 3ms

3h = 10ms

POWER_UP_SLOT_11_D R/W

URATION

Duration of slot 11 during the power-up and standby-to-active

sequences. (Default from NVM memory)

0h = 0ms

1h = 1.5ms

2h = 3ms

3h = 10ms

86

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7.5.26 POWER_UP_SLOT_DURATION_4 Register (Offset = 19h) [Reset = 00h]

POWER_UP_SLOT_DURATION_4 is shown in 图7-36 and described in 表7-33.

Return to the 表7-6.

图7-37. POWER_UP_SLOT_DURATION_4 Register

7

6

5

4

3

2

1

0

POWER_UP_SLOT_12_DURATI POWER_UP_SLOT_13_DURATI POWER_UP_SLOT_14_DURATI POWER_UP_SLOT_15_DURATI

ON

R/W-0h

表7-33. POWER_UP_SLOT_DURATION_4 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

POWER_UP_SLOT_12_D R/W

URATION

0h

Duration of slot 12 during the power-up and standby-to-active

sequences. (Default from NVM memory)

0h = 0ms

1h = 1.5ms

2h = 3ms

3h = 10ms

5-4

3-2

1-0

POWER_UP_SLOT_13_D R/W

URATION

0h

Duration of slot 13 during the power-up and standby-to-active

sequences. (Default from NVM memory)

0h = 0ms

1h = 1.5ms

2h = 3ms

3h = 10ms

POWER_UP_SLOT_14_D R/W

URATION

Duration of slot 14 during the power-up and standby-to-active

sequences. (Default from NVM memory)

0h = 0ms

1h = 1.5ms

2h = 3ms

3h = 10ms

POWER_UP_SLOT_15_D R/W

URATION

Duration of slot 15 during the power-up and standby-to-active

sequences. (Default from NVM memory)

0h = 0ms

1h = 1.5ms

2h = 3ms

3h = 10ms

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7.5.27 POWER_DOWN_SLOT_DURATION_1 Register (Offset = 1Ah) [Reset = 00h]

POWER_DOWN_SLOT_DURATION_1 is shown in 图7-37 and described in 表7-34.

Return to the 表7-6.

图7-38. POWER_DOWN_SLOT_DURATION_1 Register

7

6

5

4

3

2

1

0

POWER_DOWN_SLOT_0_DUR POWER_DOWN_SLOT_1_DUR POWER_DOWN_SLOT_2_DUR POWER_DOWN_SLOT_3_DUR

ATION

R/W-0h

表7-34. POWER_DOWN_SLOT_DURATION_1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

POWER_DOWN_SLOT_0 R/W

_DURATION

0h

Duration of slot 0 during the power-down and active-to-standby

sequences. (Default from NVM memory)

0h = 0ms

1h = 1.5ms

2h = 3ms

3h = 10ms

5-4

3-2

1-0

POWER_DOWN_SLOT_1 R/W

_DURATION

0h

Duration of slot 1 during the power-down and active-to-standby

sequences. (Default from NVM memory)

0h = 0ms

1h = 1.5ms

2h = 3ms

3h = 10ms

POWER_DOWN_SLOT_2 R/W

_DURATION

Duration of slot 2 during the power-down and active-to-standby

sequences. (Default from NVM memory)

0h = 0ms

1h = 1.5ms

2h = 3ms

3h = 10ms

POWER_DOWN_SLOT_3 R/W

_DURATION

Duration of slot 3 during the power-down and active-to-standby

sequences. (Default from NVM memory)

0h = 0ms

1h = 1.5ms

2h = 3ms

3h = 10ms

88

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7.5.28 POWER_DOWN_SLOT_DURATION_2 Register (Offset = 1Bh) [Reset = 00h]

POWER_DOWN_SLOT_DURATION_2 is shown in 图7-38 and described in 表7-35.

Return to the 表7-6.

图7-39. POWER_DOWN_SLOT_DURATION_2 Register

7

6

5

4

3

2

1

0

POWER_DOWN_SLOT_4_DUR POWER_DOWN_SLOT_5_DUR POWER_DOWN_SLOT_6_DUR POWER_DOWN_SLOT_7_DUR

ATION

R/W-0h

表7-35. POWER_DOWN_SLOT_DURATION_2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

POWER_DOWN_SLOT_4 R/W

_DURATION

0h

Duration of slot 4 during the power-down and active-to-standby

sequences. (Default from NVM memory)

0h = 0ms

1h = 1.5ms

2h = 3ms

3h = 10ms

5-4

3-2

1-0

POWER_DOWN_SLOT_5 R/W

_DURATION

0h

Duration of slot 5 during the power-down and active-to-standby

sequences. (Default from NVM memory)

0h = 0ms

1h = 1.5ms

2h = 3ms

3h = 10ms

POWER_DOWN_SLOT_6 R/W

_DURATION

Duration of slot 6 during the power-down and active-to-standby

sequences. (Default from NVM memory)

0h = 0ms

1h = 1.5ms

2h = 3ms

3h = 10ms

POWER_DOWN_SLOT_7 R/W

_DURATION

Duration of slot 7 during the power-down and active-to-standby

sequences. (Default from NVM memory)

0h = 0ms

1h = 1.5ms

2h = 3ms

3h = 10ms

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7.5.29 POWER_DOWN_SLOT_DURATION_3 Register (Offset = 1Ch) [Reset = 00h]

POWER_DOWN_SLOT_DURATION_3 is shown in 图7-39 and described in 表7-36.

Return to the 表7-6.

图7-40. POWER_DOWN_SLOT_DURATION_3 Register

7

6

5

4

3

2

1

0

POWER_DOWN_SLOT_8_DUR POWER_DOWN_SLOT_9_DUR POWER_DOWN_SLOT_10_DU POWER_DOWN_SLOT_11_DUR

ATION

RATION

ATION

R/W-0h

表7-36. POWER_DOWN_SLOT_DURATION_3 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

POWER_DOWN_SLOT_8 R/W

_DURATION

0h

Duration of slot 8 during the power-down and active-to-standby

sequences. (Default from NVM memory)

0h = 0ms

1h = 1.5ms

2h = 3ms

3h = 10ms

5-4

3-2

1-0

POWER_DOWN_SLOT_9 R/W

_DURATION

0h

Duration of slot 9 during the power-down and active-to-standby

sequences. (Default from NVM memory)

0h = 0ms

1h = 1.5ms

2h = 3ms

3h = 10ms

POWER_DOWN_SLOT_1 R/W

0_DURATION

Duration of slot 10 during the power-down and active-to-standby

sequences. (Default from NVM memory)

0h = 0ms

1h = 1.5ms

2h = 3ms

3h = 10ms

POWER_DOWN_SLOT_1 R/W

1_DURATION

Duration of slot 11 during the power-down and active-to-standby

sequences. (Default from NVM memory)

0h = 0ms

1h = 1.5ms

2h = 3ms

3h = 10ms

90

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7.5.30 POWER_DOWN_SLOT_DURATION_4 Register (Offset = 1Dh) [Reset = 00h]

POWER_DOWN_SLOT_DURATION_4 is shown in 图7-40 and described in 表7-37.

Return to the 表7-6.

图7-41. POWER_DOWN_SLOT_DURATION_4 Register

7

6

5

4

3

2

1

0

POWER_DOWN_SLOT_12_DU POWER_DOWN_SLOT_13_DU POWER_DOWN_SLOT_14_DU POWER_DOWN_SLOT_15_DU

RATION

R/W-0h

表7-37. POWER_DOWN_SLOT_DURATION_4 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

POWER_DOWN_SLOT_1 R/W

2_DURATION

0h

Duration of slot 12 during the power-down and active-to-standby

sequences. (Default from NVM memory)

0h = 0ms

1h = 1.5ms

2h = 3ms

3h = 10ms

5-4

3-2

1-0

POWER_DOWN_SLOT_1 R/W

3_DURATION

0h

Duration of slot 13 during the power-down and active-to-standby

sequences. (Default from NVM memory)

0h = 0ms

1h = 1.5ms

2h = 3ms

3h = 10ms

POWER_DOWN_SLOT_1 R/W

4_DURATION

Duration of slot 14 during the power-down and active-to-standby

sequences. (Default from NVM memory)

0h = 0ms

1h = 1.5ms

2h = 3ms

3h = 10ms

POWER_DOWN_SLOT_1 R/W

5_DURATION

Duration of slot 15 during the power-down and active-to-standby

sequences. (Default from NVM memory)

0h = 0ms

1h = 1.5ms

2h = 3ms

3h = 10ms

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7.5.31 GENERAL_CONFIG Register (Offset = 1Eh) [Reset = 00h]

GENERAL_CONFIG is shown in 图7-41 and described in 表7-38.

Return to the 表7-6.

图7-42. GENERAL_CONFIG Register

7

6

5

4

3

2

1

0

BYPASS_RAIL LDO4_UV_THR LDO3_UV_THR LDO2_UV_THR LDO1_UV_THR

GPIO_EN

GPO2_EN

GPO1_EN

S_DISCHARGE

D_CHECK

R/W-0h

表7-38. GENERAL_CONFIG Register Field Descriptions

Bit

Field

Type

Reset

Description

7

BYPASS_RAILS_DISCHA R/W

RGED_CHECK

0h

Bypass the all-rails discharged check to commence a transition to

ACTIVE state, and the rails-in-slot discharged check executed in

each slot during a power-down to INITIALIZE state. Does not bypass

the check for RV(Pre-biased) condition prior to enabling a regulator.

(Default from NVM memory)

0h = Discharged checks enforced

1h = Discharged checks during PowerUp and PowerDown bypassed

6

5

4

3

2

LDO4_UV_THR

LDO3_UV_THR

LDO2_UV_THR

LDO1_UV_THR

GPIO_EN

R/W

0h

UV threshold selection bit for LDO4. (Default from NVM memory)

0h = -5% UV detection level

1h = -10% UV detection level

UV threshold selection bit for LDO3. (Default from NVM memory)

0h = -5% UV detection level

1h = -10% UV detection level

UV threshold selection bit for LDO2. (Default from NVM memory)

0h = -5% UV detection level

1h = -10% UV detection level

UV threshold selection bit for LDO1. (Default from NVM memory)

0h = -5% UV detection level

1h = -10% UV detection level

Both an enable and state control of GPIO. This bit enables the GPIO

function and also controls the state of the GPIO pin. (Default from

NVM memory)

0h = The GPIO function is disabled. The output state is low.

1h = The GPIO function is enabled. The output state is 'high'.

1

0

GPO2_EN

GPO1_EN

R/W

0h

Both an enable and state control of GPO2. This bit enables the

GPO2 function and also controls the state of the GPO2 pin. (Default

from NVM memory)

0h = The GPO2 function is disabled. The output state is low.

1h = The GPO2 function is enabled. The output state is Hi-Z.

Both an enable and state control of GPO1. This bit enables the

GPO1 function and also controls the state of the GPO1 pin. (Default

from NVM memory)

0h = The GPO1 function is disabled. The output state is low.

1h = The GPO1 function is enabled. The output state is Hi-Z.

92

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7.5.32 MFP_1_CONFIG Register (Offset = 1Fh) [Reset = 00h]

MFP_1_CONFIG is shown in 图7-42 and described in 表7-39.

Return to the 表7-6.

图7-43. MFP_1_CONFIG Register

7

6

5

4

3

2

1

0

MODE_I2C_CT VSEL_SD_I2C_ MODE_RESET MODE_STBY_ MULTI_DEVICE

VSEL_RAIL

VSEL_SD_POL VSEL_DDR_SD

ARITY

RL

CTRL

_POLARITY

POLARITY

_ENABLE

R/W-0h

表7-39. MFP_1_CONFIG Register Field Descriptions

Bit

Field

Type

Reset

Description

7

MODE_I2C_CTRL

R/W

0h

MODE control using I2C. Consolidated with MODE control via

MODE/RESET and/or MODE/STBY pins. Refer to table in the data

sheet. (Default from NVM memory)

0h = Auto PFM

1h = Forced PWM

6

5

4

VSEL_SD_I2C_CTRL

R/W

0h

VSEL_SD control using I2C. Applicable only if VSEL_SD/

VSEL_DDR pin is configured as "VSEL_DDR". (Default from NVM

memory)

0h = 1.8V

1h = LDOx_VOUT register setting

MODE_RESET_POLARIT R/W

Y

MODE_RESET Pin Polarity configuration. !!! Note: Ok to change

during operation, but consider immediate reaction: MODE-change or

RESET-entry !!! (Default from NVM memory)

0h = [if configured as mode] LOW:

1h = [if configured as MODE] HIGH:

MODE_STBY_POLARITY R/W

MULTI_DEVICE_ENABLE R/W

MODE_STBY Pin Polarity configuration. !!! Note: Ok to change

during operation, but consider immediate reaction: MODE-change or

STATE-change !!! (Default from NVM memory)

0h = MODE/STBY = low = STBY state, disabling selected rails; high

= ACTIVE state; (if configured as a STBY pin or MODE and STBY

pin).

1h = [if configured as MODE] HIGH:

3

0h

Configures the device as a single device where GPO is used as

GPO function, or as a multi-device configuration where GPO is used

for synchronization with other devices. !!! NOTE: ONLY CHANGE IN

INITIALIZE STATE !!! (Default from NVM memory)

0h = Single-device configuration, GPIO pin configured as GPO

1h = Multi-device configuration, GPIO pin configured as GPIO

2

1

VSEL_RAIL

R/W

0h

LDO controlled by VSEL_SD/VSEL_DDR. !!! NOTE: ONLY CHANGE

IN INITIALIZE STATE !!! (Default from NVM memory)

0h = LDO1

1h = LDO2

VSEL_SD_POLARITY

SD Card Voltage Select !!! Note: Ok to change during operation, but

consider immediate reaction: change of SD-card supply voltage !!!

(Default from NVM memory)

0h = LOW:

1h = HIGH:

0

VSEL_DDR_SD

R/W

0h

VSEL_SD/VSEL_DDR Configuration !!! NOTE: ONLY CHANGE IN

INITIALIZE STATE !!! (Default from NVM memory)

0h = VSEL pin configured as DDR to set the voltage on Buck3

1h = VSEL pin configured as SD to set the voltage on the

VSEL_RAIL

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7.5.33 MFP_2_CONFIG Register (Offset = 20h) [Reset = 00h]

MFP_2_CONFIG is shown in 图7-43 and described in 表7-40.

Return to the 表7-6.

图7-44. MFP_2_CONFIG Register

7

6

5

4

3

2

1

0

PU_ON_FSD WARM_COLD_

EN_PB_VSENSE_CONFIG

EN_PB_VSENS MODE_RESET

MODE_STBY_CONFIG

RESET_CONFI

G

E_DEGL

_CONFIG

R/W-0h

表7-40. MFP_2_CONFIG Register Field Descriptions

Bit

Field

PU_ON_FSD

Type

Reset

Description

7

R/W

0h

Power up upon First Supply Detected (FSD). So when VSYS is

applied, device does power up to ACTIVE state even if EN/PB/

VSENSE pin is at OFF_REQ status. (Default from NVM memory)

0h = Power up to ACTIVE state only if EN/PB/VSENSE pin is at

ON_REQUEST status

1h = First Supply Detection (FSD) Enabled.

6

5-4

3

WARM_COLD_RESET_C R/W

ONFIG

0h

Selection between WARM or COLD Reset, when a RESET event is

triggered via MODE/RESET pin (does not apply to RESET via I2C)

(Default from NVM memory)

0h = COLD RESET

1h = WARM RESET (Do not power down. Only reset target voltage

and Bypass mode configs for DVS-capable regulators to their NVM

values)

EN_PB_VSENSE_CONFI R/W

G

Enable / Push-Button / VSENSE Configuration. Do not change via

I2C after NVM load (except as a precursor before programming

NVM) (Default from NVM memory)

0h = Device Enable Configuration

1h = Push Button Configuration

2h = VSENSE Configuration

3h = Device Enable Configuration

EN_PB_VSENSE_DEGL R/W

MODE_RESET_CONFIG R/W

Enable / Push-Button / VSENSE Deglitch !!! NOTE: ONLY CHANGE

IN INITIALIZE STATE! Consider immediate reaction when changing

from EN/VSENSE to PB or vice versa: power-up !!! (Default from

NVM memory)

0h = short (typ: 200ms if configured as PB)

1h = long (typ: 50ms if configured as EN or VSENSE)

2

0h

MODE/RESET Configuration (Default from NVM memory)

0h = MODE

1h = RESET

1-0

MODE_STBY_CONFIG

R/W

MODE_STDBY Configuration (Default from NVM memory)

0h = MODE

1h = STBY

2h = MODE and STBY

3h = MODE

94

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7.5.34 STBY_1_CONFIG Register (Offset = 21h) [Reset = X]

STBY_1_CONFIG is shown in 图7-44 and described in 表7-41.

Return to the 表7-6.

图7-45. STBY_1_CONFIG Register

7

6

5

4

3

2

1

0

RESERVED

LDO4_STBY_E LDO3_STBY_E LDO2_STBY_E LDO1_STBY_E BUCK3_STBY_ BUCK2_STBY_ BUCK1_STBY_

N

EN

R-X

R/W-0h

表7-41. STBY_1_CONFIG Register Field Descriptions

Bit

7

Field

RESERVED

Type

Reset

Description

R

X

Reserved

6

LDO4_STBY_EN

LDO3_STBY_EN

LDO2_STBY_EN

LDO1_STBY_EN

BUCK3_STBY_EN

BUCK2_STBY_EN

BUCK1_STBY_EN

R/W

0h

Enable LDO4 in STANDBY state. (Default from NVM memory)

0h = Disabled in STBY Mode

1h = Enabled in STBY Mode

5

4

3

2

1

0

R/W

0h

Enable LDO3 in STANDBY state. (Default from NVM memory)

0h = Disabled in STBY Mode

1h = Enabled in STBY Mode

Enable LDO2 in STANDBY state. (Default from NVM memory)

0h = Disabled in STBY Mode

1h = Enabled in STBY Mode

Enable LDO1 in STANDBY state. (Default from NVM memory)

0h = Disabled in STBY Mode

1h = Enabled in STBY Mode

Enable BUCK3 in STANDBY state. (Default from NVM memory)

0h = Disabled in STBY Mode

1h = Enabled in STBY Mode

Enable BUCK2 in STANDBY state. (Default from NVM memory)

0h = Disabled in STBY Mode

1h = Enabled in STBY Mode

Enable BUCK1 in STANDBY state. (Default from NVM memory)

0h = Disabled in STBY Mode

1h = Enabled in STBY Mode

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7.5.35 STBY_2_CONFIG Register (Offset = 22h) [Reset = X]

STBY_2_CONFIG is shown in 图7-45 and described in 表7-42.

Return to the 表7-6.

图7-46. STBY_2_CONFIG Register

7

6

5

4

3

2

1

0

RESERVED

R-X

RESERVED

R-X

RESERVED

R-X

GPIO_STBY_E GPO2_STBY_E GPO1_STBY_E

N

R-X

R/W-0h

表7-42. STBY_2_CONFIG Register Field Descriptions

Bit

7

Field

RESERVED

Type

Reset

Description

Reserved

R

X

6

RESERVED

GPIO_STBY_EN

R

X

5

R

X

4

R

X

3

R

X

2

R/W

0h

Enable GPIO in STANDBY state. (Default from NVM memory)

0h = Disabled in STBY Mode

1h = Enabled in STBY Mode

1

0

GPO2_STBY_EN

GPO1_STBY_EN

R/W

0h

Enable GPO2 in STANDBY state. (Default from NVM memory)

0h = Disabled in STBY Mode

1h = Enabled in STBY Mode

Enable GPO1 in STANDBY state. (Default from NVM memory)

0h = Disabled in STBY Mode

1h = Enabled in STBY Mode

96

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7.5.36 OC_DEGL_CONFIG Register (Offset = 23h) [Reset = X]

OC_DEGL_CONFIG is shown in 图7-46 and described in 表7-43.

Return to the 表7-6.

图7-47. OC_DEGL_CONFIG Register

7

6

5

4

3

2

1

0

RESERVED

EN_LONG_DE EN_LONG_DE EN_LONG_DE EN_LONG_DE EN_LONG_DE EN_LONG_DE EN_LONG_DE

GL_FOR_OC_L GL_FOR_OC_L GL_FOR_OC_L GL_FOR_OC_L GL_FOR_OC_ GL_FOR_OC_ GL_FOR_OC_

DO4

DO3

DO2

DO1

BUCK3

BUCK2

BUCK1

R-X

R/W-0h

表7-43. OC_DEGL_CONFIG Register Field Descriptions

Bit

7

Field

RESERVED

Type

Reset

Description

R

X

Reserved

6

EN_LONG_DEGL_FOR_ R/W

OC_LDO4

0h

When set, enables the long-deglitch option for OverCurrent signal of

LDO4. When clear, enables the short-deglitch option for OverCurrent

signal of LDO4. (Default from NVM memory)

0h = Deglitch duration for OverCurrent signals of LDO4 is ~20us

1h = Deglitch duration for OverCurrent signals of LDO4 is ~2ms

5

4

3

2

EN_LONG_DEGL_FOR_ R/W

OC_LDO3

0h

When set, enables the long-deglitch option for OverCurrent signal of

LDO3. When clear, enables the short-deglitch option for OverCurrent

signal of LDO3. (Default from NVM memory)

0h = Deglitch duration for OverCurrent signals of LDO3 is ~20us

1h = Deglitch duration for OverCurrent signals of LDO3 is ~2ms

EN_LONG_DEGL_FOR_ R/W

OC_LDO2

When set, enables the long-deglitch option for OverCurrent signal of

LDO2. When clear, enables the short-deglitch option for OverCurrent

signal of LDO2. (Default from NVM memory)

0h = Deglitch duration for OverCurrent signals of LDO2 is ~20us

1h = Deglitch duration for OverCurrent signals of LDO2 is ~2ms

EN_LONG_DEGL_FOR_ R/W

OC_LDO1

When set, enables the long-deglitch option for OverCurrent signal of

LDO1. When clear, enables the short-deglitch option for OverCurrent

signal of LDO1. (Default from NVM memory)

0h = Deglitch duration for OverCurrent signals of LDO1 is ~20us

1h = Deglitch duration for OverCurrent signals of LDO1 is ~2ms

EN_LONG_DEGL_FOR_ R/W

OC_BUCK3

When set, enables the long-deglitch option for OverCurrent signals

of BUCK3. When clear, enables the short-deglitch option for

OverCurrent signals of BUCK3. (Default from NVM memory)

0h = Deglitch duration for OverCurrent signals for BUCK3 (High-Side

Overcurrent, Low-Side Overcurrent and Low-Side Reverse/Negative

OverCurrent) is ~20us

1h = Deglitch duration for OverCurrent signals for BUCK3 (High-Side

Overcurrent, Low-Side Overcurrent and Low-Side Reverse/Negative

OverCurrent) is ~2ms

1

EN_LONG_DEGL_FOR_ R/W

OC_BUCK2

0h

When set, enables the long-deglitch option for OverCurrent signals

of BUCK2. When clear, enables the short-deglitch option for

OverCurrent signals of BUCK2. (Default from NVM memory)

0h = Deglitch duration for OverCurrent signals for BUCK2 (High-Side

Overcurrent, Low-Side Overcurrent and Low-Side Reverse/Negative

OverCurrent) is ~20us

1h = Deglitch duration for OverCurrent signals for BUCK2 (High-Side

Overcurrent, Low-Side Overcurrent and Low-Side Reverse/Negative

OverCurrent) is ~2ms

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表7-43. OC_DEGL_CONFIG Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

0

EN_LONG_DEGL_FOR_ R/W

OC_BUCK1

0h

When set, enables the long-deglitch option for OverCurrent signals

of BUCK1. When clear, enables the short-deglitch option for

OverCurrent signals of BUCK1. (Default from NVM memory)

0h = Deglitch duration for OverCurrent signals for BUCK1 (High-Side

Overcurrent, Low-Side Overcurrent and Low-Side Reverse/Negative

OverCurrent) is ~20us

1h = Deglitch duration for OverCurrent signals for BUCK1 (High-Side

Overcurrent, Low-Side Overcurrent and Low-Side Reverse/Negative

OverCurrent) is ~2ms

98

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7.5.37 INT_MASK_UV Register (Offset = 24h) [Reset = 00h]

INT_MASK_UV is shown in 图7-47 and described in 表7-44.

Return to the 表7-6.

图7-48. INT_MASK_UV Register

7

6

5

4

3

2

1

0

MASK_RETRY BUCK3_UV_M BUCK2_UV_M BUCK1_UV_M LDO4_UV_MA LDO3_UV_MA LDO2_UV_MA LDO1_UV_MA

_COUNT

ASK

SK

R/W-0h

表7-44. INT_MASK_UV Register Field Descriptions

Bit

Field

Type

Reset

Description

7

MASK_RETRY_COUNT

R/W

0h

When set, device can power up even after two retries. (Default from

NVM memory)

0h = Device does retry up to 2 times, then stay off

1h = Device does retry infinitely

6

5

4

3

BUCK3_UV_MASK

BUCK2_UV_MASK

BUCK1_UV_MASK

LDO4_UV_MASK

R/W

0h

BUCK3 Undervoltage Mask. (Default from NVM memory)

0h = un-masked (Faults reported)

1h = masked (Faults not reported)

BUCK2 Undervoltage Mask. (Default from NVM memory)

0h = un-masked (Faults reported)

1h = masked (Faults not reported)

BUCK1 Undervoltage Mask. (Default from NVM memory)

0h = un-masked (Faults reported)

1h = masked (Faults not reported)

LDO4 Undervoltage Mask - Always masked in BYP or LSW modes.

(Default from NVM memory)

0h = un-masked (Faults reported)

1h = masked (Faults not reported)

2

1

0

LDO3_UV_MASK

LDO2_UV_MASK

LDO1_UV_MASK

R/W

0h

LDO3 Undervoltage Mask - Always masked in BYP or LSW modes.

(Default from NVM memory)

0h = un-masked (Faults reported)

1h = masked (Faults not reported)

LDO2 Undervoltage Mask - Always masked in BYP or LSW modes.

(Default from NVM memory)

0h = un-masked (Faults reported)

1h = masked (Faults not reported)

LDO1 Undervoltage Mask - Always masked in BYP or LSW modes.

(Default from NVM memory)

0h = un-masked (Faults reported)

1h = masked (Faults not reported)

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7.5.38 MASK_CONFIG Register (Offset = 25h) [Reset = 80h]

MASK_CONFIG is shown in 图7-48 and described in 表7-45.

Return to the 表7-6.

图7-49. MASK_CONFIG Register

7

6

5

4

3

2

1

0

MASK_INT_FO

R_PB

MASK_EFFECT

MASK_INT_FO SENSOR_0_W SENSOR_1_W SENSOR_2_W SENSOR_3_W

R_RV

ARM_MASK

R/W-1h

R/W-0h

表7-45. MASK_CONFIG Register Field Descriptions

Bit

Field

Type

Reset

Description

7

MASK_INT_FOR_PB

R/W

1h

Masking bit to control whether nINT pin is sensitive to PushButton

(PB) press/release events or not. (Default from NVM memory)

0h = un-masked (nINT pulled low for any PB events)

1h = masked (nINT not sensitive to any PB events)

6-5

4

MASK_EFFECT

R/W

0h

Effect of masking (global) (Default from NVM memory)

0h = no state change, no nINT reaction, no bit set for Faults

1h = no state change, no nINT reaction, bit set for Faults

2h = no state change, nINT reaction, bit set for Faults (same as 11b)

3h = no state change, nINT reaction, bit set for Faults (same as 10b)

MASK_INT_FOR_RV

Masking bit to control whether nINT pin is sensitive to RV (Residual

Voltage) events or not. (Default from NVM memory)

0h = un-masked (nINT pulled low for any RV events during transition

to ACTIVE state or during enabling of rails)

1h = masked (nINT not sensitive to any RV events)

3

2

1

0

SENSOR_0_WARM_MAS R/W

K

0h

Die Temperature Warm Fault Mask, Sensor 0. (Default from NVM

memory)

0h = un-masked (Faults reported)

1h = masked (Faults not reported)

SENSOR_1_WARM_MAS R/W

K

Die Temperature Warm Fault Mask, Sensor 1. (Default from NVM

memory)

0h = un-masked (Faults reported)

1h = masked (Faults not reported)

SENSOR_2_WARM_MAS R/W

K

Die Temperature Warm Fault Mask, Sensor 2. (Default from NVM

memory)

0h = un-masked (Faults reported)

1h = masked (Faults not reported)

SENSOR_3_WARM_MAS R/W

K

Die Temperature Warm Fault Mask, Sensor 3. (Default from NVM

memory)

0h = un-masked (Faults reported)

1h = masked (Faults not reported)

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7.5.39 I2C_ADDRESS_REG Register (Offset = 26h) [Reset = 48h]

I2C_ADDRESS_REG is shown in 图7-49 and described in 表7-46.

Return to the 表7-6.

图7-50. I2C_ADDRESS_REG Register

7

6

5

4

3

2

1

0

DIY_NVM_PRO

GRAM_CMD_I

SSUED

I2C_ADDRESS

R/W-0h

R/W-48h

表7-46. I2C_ADDRESS_REG Register Field Descriptions

Bit

Field

Type

Reset

Description

7

DIY_NVM_PROGRAM_C R/W

MD_ISSUED

0h

Bit that indicates whether a DIY program command was attempted.

Once set, remains always set. (Default from NVM memory)

0h = NVM data not changed

1h = NVM data attempted to be changed via DIY program command

6-0

I2C_ADDRESS

R/W

48h

I2C secondary address. !!! Note: Ok to change during operation, but

consider immediate reaction: new address for read/write !!! (Default

from NVM memory)

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7.5.40 USER_GENERAL_NVM_STORAGE_REG Register (Offset = 27h) [Reset = 48h]

USER_GENERAL_NVM_STORAGE_REG is shown in 图7-50 and described in 表7-47.

Return to the 表7-6.

图7-51. USER_GENERAL_NVM_STORAGE_REG Register

7

6

5

4

3

2

1

0

USER_GENERAL_NVM_STORAGE

R/W-48h

表7-47. USER_GENERAL_NVM_STORAGE_REG Register Field Descriptions

Bit

7-0

Field

Type

Reset

Description

USER_GENERAL_NVM_ R/W

STORAGE

48h

8-bit NVM-based register available to the user to use to store user-

data, for example NVM-ID of customer-modified NVM-version or

other purposes. (Default from NVM memory)

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7.5.41 MANUFACTURING_VER Register (Offset = 28h) [Reset = 00h]

MANUFACTURING_VER is shown in 图7-51 and described in 表7-48.

Return to the 表7-6.

图7-52. MANUFACTURING_VER Register

7

6

5

4

3

2

1

0

SILICON_REV

R-0h

表7-48. MANUFACTURING_VER Register Field Descriptions

Bit

7-0

Field

SILICON_REV

Type

Reset

Description

R

0h

SILICON_REV[7:6] - Reserved SILICON_REV[5:3] - ALR

SILICON_REV[2:0] - Metal Silicon Revision - Hard wired (not under

NVM control)

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7.5.42 MFP_CTRL Register (Offset = 29h) [Reset = X]

MFP_CTRL is shown in 图7-52 and described in 表7-49.

Return to the 表7-6.

图7-53. MFP_CTRL Register

7

6

5

4

3

2

1

0

RESERVED

GPIO_STATUS WARM_RESET COLD_RESET_ STBY_I2C_CT I2C_OFF_REQ

_I2C_CTRL

I2C_CTRL

RL

R-X

R-0h

R/WSelfClrF-0h

R/W-0h

R/WSelfClrF-0h

表7-49. MFP_CTRL Register Field Descriptions

Bit

7

Field

RESERVED

Type

Reset

Description

Reserved

R

X

6

RESERVED

GPIO_STATUS

R

X

5

R

X

4

R

0h

Indicates the real-time value of GPIO pin

0h = The GPIO pin is currently '0'

1h = The GPIO pin is currently '1'

3

2

1

0

WARM_RESET_I2C_CTR R/WSelfClrF 0h

L

Triggers a WARM RESET when written as '1'. Note: This bit self-

clears automatically, so cannot be read as '1' after the write.

0h = normal operation

1h = WARM_RESET

COLD_RESET_I2C_CTR R/W

L

0h

Triggers a COLD RESET when set high. Cleared upon entry to

INITIALIZE.

0h = normal operation

1h = COLD_RESET

STBY_I2C_CTRL

I2C_OFF_REQ

R/W

STBY control using I2C. Consolidated with STBY control via MODE/

STBY pin. Refer to table in spec.

0h = normal operation

1h = STBY mode

R/WSelfClrF 0h

When '1' is written to this bit: Trigger OFF request. When '0': No

effect. Does self-clear.

0h = No effect

1h = Trigger OFF Request

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7.5.43 DISCHARGE_CONFIG Register (Offset = 2Ah) [Reset = X]

DISCHARGE_CONFIG is shown in 图7-53 and described in 表7-50.

Return to the 表7-6.

图7-54. DISCHARGE_CONFIG Register

7

6

5

4

3

2

1

0

RESERVED

LDO4_DISCHA LDO3_DISCHA LDO2_DISCHA LDO1_DISCHA BUCK3_DISCH BUCK2_DISCH BUCK1_DISCH

RGE_EN

ARGE_EN

R-X

R/W-1h

表7-50. DISCHARGE_CONFIG Register Field Descriptions

Bit

7

Field

RESERVED

Type

Reset

Description

R

X

Reserved

6

LDO4_DISCHARGE_EN R/W

LDO3_DISCHARGE_EN R/W

LDO2_DISCHARGE_EN R/W

LDO1_DISCHARGE_EN R/W

BUCK3_DISCHARGE_EN R/W

BUCK2_DISCHARGE_EN R/W

BUCK1_DISCHARGE_EN R/W

1h

Discharge setting for LDO4

0h = No Discharge

1h = 250 Ω

5

4

3

2

1

0

1h

Discharge setting for LDO3

0h = No Discharge

1h = 250 Ω

Discharge setting for LDO2

0h = No Discharge

1h = 200 Ω

Discharge setting for LDO1

0h = No Discharge

1h = 200 Ω

Discharge setting for BUCK3

0h = No Discharge

1h = 125 Ω

Discharge setting for BUCK2

0h = No Discharge

1h = 125 Ω

Discharge setting for BUCK1

0h = No Discharge

1h = 125 Ω

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7.5.44 INT_SOURCE Register (Offset = 2Bh) [Reset = 00h]

INT_SOURCE is shown in 图7-54 and described in 表7-51.

Return to the 表7-6.

图7-55. INT_SOURCE Register

7

6

5

4

3

2

1

0

INT_PB_IS_SE INT_LDO_3_4_ INT_LDO_1_2_ INT_BUCK_3_I INT_BUCK_1_2 INT_SYSTEM_I INT_RV_IS_SE INT_TIMEOUT_

T

IS_SET

S_SET

_IS_SET

S_SET

T

RV_SD_IS_SE

T

R-0h

表7-51. INT_SOURCE Register Field Descriptions

Bit

Field

Type

Reset

Description

7

6

5

4

3

2

1

0

INT_PB_IS_SET

R

0h

One or more sources of the INT present in register INT_PB

0h = No bits set in INT_PB

1h = One or more bits set in INT_PB

INT_LDO_3_4_IS_SET

INT_LDO_1_2_IS_SET

INT_BUCK_3_IS_SET

INT_BUCK_1_2_IS_SET

INT_SYSTEM_IS_SET

INT_RV_IS_SET

R

0h

One or more sources of the INT present in register INT_LDO_3_4

0h = No bits set in INT_LDO_3_4

1h = One or more bits set in INT_LDO_3_4

One or more sources of the INT present in register INT_LDO_1_2

0h = No bits set in INT_LDO_1_2

1h = One or more bits set in INT_LDO_1_2

One or more sources of the INT present in register INT_BUCK_3

0h = No bits set in INT_BUCK_3

1h = One or more bits set in INT_BUCK_3

One or more sources of the INT present in register INT_BUCK_1_2

0h = No bits set in INT_BUCK_1_2

1h = One or more bits set in INT_BUCK_1_2

One or more sources of the INT present in register INT_SYSTEM

0h = No bits set in INT_SYSTEM

1h = One or more bits set in INT_SYSTEM

One or more sources of the INT present in register INT_RV

0h = No bits set in INT_RV

1h = One or more bits set in INT_RV

INT_TIMEOUT_RV_SD_I

S_SET

One or more sources of the INT present in register

INT_TIMEOUT_RV_SD

0h = No bits set in INT_TIMEOUT_RV_SD

1h = One or more bits set in INT_TIMEOUT_RV_SD

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7.5.45 INT_LDO_3_4 Register (Offset = 2Ch) [Reset = X]

INT_LDO_3_4 is shown in 图7-55 and described in 表7-52.

Return to the 表7-6.

图7-56. INT_LDO_3_4 Register

7

6

5

4

3

2

1

0

RESERVED

R-X

RESERVED

R-X

LDO4_UV

R/W1C-0h

LDO4_OC

R/W1C-0h

LDO4_SCG

R/W1C-0h

LDO3_UV

R/W1C-0h

LDO3_OC

R/W1C-0h

LDO3_SCG

R/W1C-0h

表7-52. INT_LDO_3_4 Register Field Descriptions

Bit

7

Field

RESERVED

Type

Reset

Description

Reserved

R

X

6

RESERVED

LDO4_UV

R

X

5

R/W1C

0h

LDO4 Undervoltage Fault. Is automatically cleared upon a transition

to INITIALIZE state, if corresponding *_UV_MASK bit in register

INT_MASK_UV is '1'

0h = No Fault detected

1h = Fault detected

4

3

2

LDO4_OC

LDO4_SCG

LDO3_UV

R/W1C

0h

LDO4 Overcurrent Fault.

0h = No Fault detected

1h = Fault detected

LDO4 Short Circuit to Ground Fault

0h = No Fault detected

1h = Fault detected

LDO3 Undervoltage Fault. Is automatically cleared upon a transition

to INITIALIZE state, if corresponding *_UV_MASK bit in register

INT_MASK_UV is '1'

0h = No Fault detected

1h = Fault detected

1

0

LDO3_OC

R/W1C

0h

LDO3 Overcurrent Fault

0h = No Fault detected

1h = Fault detected

LDO3_SCG

LDO3 Short Circuit to Ground Fault

0h = No Fault detected

1h = Fault detected

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7.5.46 INT_LDO_1_2 Register (Offset = 2Dh) [Reset = X]

INT_LDO_1_2 is shown in 图7-56 and described in 表7-53.

Return to the 表7-6.

图7-57. INT_LDO_1_2 Register

7

6

5

4

3

2

1

0

RESERVED

R-X

RESERVED

R-X

LDO2_UV

R/W1C-0h

LDO2_OC

R/W1C-0h

LDO2_SCG

R/W1C-0h

LDO1_UV

R/W1C-0h

LDO1_OC

R/W1C-0h

LDO1_SCG

R/W1C-0h

表7-53. INT_LDO_1_2 Register Field Descriptions

Bit

7

Field

RESERVED

Type

Reset

Description

Reserved

R

X

6

RESERVED

LDO2_UV

R

X

5

R/W1C

0h

LDO2 Undervoltage Fault. Is automatically cleared upon a transition

to INITIALIZE state, if corresponding *_UV_MASK bit in register

INT_MASK_UV is '1'

0h = No Fault detected

1h = Fault detected

4

3

2

LDO2_OC

LDO2_SCG

LDO1_UV

R/W1C

0h

LDO2 Overcurrent Fault

0h = No Fault detected

1h = Fault detected

LDO2 Short Circuit to Ground Fault

0h = No Fault detected

1h = Fault detected

LDO1 Undervoltage Fault. Is automatically cleared upon a transition

to INITIALIZE state, if corresponding *_UV_MASK bit in register

INT_MASK_UV is '1'

0h = No Fault detected

1h = Fault detected

1

0

LDO1_OC

R/W1C

0h

LDO1 Overcurrent Fault

0h = No Fault detected

1h = Fault detected

LDO1_SCG

LDO1 Short Circuit to Ground Fault

0h = No Fault detected

1h = Fault detected

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7.5.47 INT_BUCK_3 Register (Offset = 2Eh) [Reset = X]

INT_BUCK_3 is shown in 图7-57 and described in 表7-54.

Return to the 表7-6.

图7-58. INT_BUCK_3 Register

7

6

5

4

3

2

1

0

RESERVED

BUCK3_UV

BUCK3_NEG_

OC

BUCK3_OC

BUCK3_SCG

R-X

R/W1C-0h

表7-54. INT_BUCK_3 Register Field Descriptions

Bit

7

Field

RESERVED

Type

Reset

Description

Reserved

R

X

6

RESERVED

BUCK3_UV

R

X

5

R

X

4

R

X

3

R/W1C

0h

BUCK3 Undervoltage Fault. Is automatically cleared upon a

transition to INITIALIZE state, if corresponding *_UV_MASK bit in

register INT_MASK_UV is '1'

0h = No Fault detected

1h = Fault detected

2

1

0

BUCK3_NEG_OC

BUCK3_OC

R/W1C

0h

BUCK3 Negative Overcurrent Fault

0h = No Fault detected

1h = Fault detected

BUCK3 Positive Overcurrent Fault

0h = No Fault detected

1h = Fault detected

BUCK3_SCG

BUCK3 Short Circuit to Ground Fault

0h = No Fault detected

1h = Fault detected

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7.5.48 INT_BUCK_1_2 Register (Offset = 2Fh) [Reset = 00h]

INT_BUCK_1_2 is shown in 图7-58 and described in 表7-55.

Return to the 表7-6.

图7-59. INT_BUCK_1_2 Register

7

6

5

4

3

2

1

0

BUCK2_UV

BUCK2_NEG_

OC

BUCK2_OC

BUCK2_SCG

BUCK1_UV

BUCK1_NEG_

OC

BUCK1_OC

BUCK1_SCG

R/W1C-0h

表7-55. INT_BUCK_1_2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

BUCK2_UV

R/W1C

0h

BUCK2 Undervoltage Fault. Is automatically cleared upon a

transition to INITIALIZE state, if corresponding *_UV_MASK bit in

register INT_MASK_UV is '1'

0h = No Fault detected

1h = Fault detected

6

5

4

3

BUCK2_NEG_OC

BUCK2_OC

R/W1C

0h

BUCK2 Negative Overcurrent Fault

0h = No Fault detected

1h = Fault detected

BUCK2 Positive Overcurrent Fault

0h = No Fault detected

1h = Fault detected

BUCK2_SCG

BUCK1_UV

BUCK2 Short Circuit to Ground Fault

0h = No Fault detected

1h = Fault detected

BUCK1 Undervoltage Fault. Is automatically cleared upon a

transition to INITIALIZE state, if corresponding *_UV_MASK bit in

register INT_MASK_UV is '1'

0h = No Fault detected

1h = Fault detected

2

1

0

BUCK1_NEG_OC

BUCK1_OC

R/W1C

0h

BUCK1 Negative Overcurrent Fault

0h = No Fault detected

1h = Fault detected

BUCK1 Positive Overcurrent Fault

0h = No Fault detected

1h = Fault detected

BUCK1_SCG

BUCK1 Short Circuit to Ground Fault

0h = No Fault detected

1h = Fault detected

110

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7.5.49 INT_SYSTEM Register (Offset = 30h) [Reset = 00h]

INT_SYSTEM is shown in 图7-59 and described in 表7-56.

Return to the 表7-6.

图7-60. INT_SYSTEM Register

7

6

5

4

3

2

1

0

SENSOR_0_H SENSOR_1_H SENSOR_2_H SENSOR_3_H SENSOR_0_W SENSOR_1_W SENSOR_2_W SENSOR_3_W

OT

ARM

R/W1C-0h

表7-56. INT_SYSTEM Register Field Descriptions

Bit

Field

Type

Reset

Description

7

SENSOR_0_HOT

SENSOR_1_HOT

SENSOR_2_HOT

SENSOR_3_HOT

SENSOR_0_WARM

R/W1C

0h

TSD Hot detection for sensor 0

0h = No Fault detected

1h = Fault detected

6

5

4

3

R/W1C

0h

TSD Hot detection for sensor 1

0h = No Fault detected

1h = Fault detected

TSD Hot detection for sensor 2

0h = No Fault detected

1h = Fault detected

TSD Hot detection for sensor 3

0h = No Fault detected

1h = Fault detected

TSD Warm detection for sensor 0. Is automatically cleared upon a

transition to INITIALIZE state, if corresponding *_WARM_MASK bit

in register MASK_CONFIG is '1'

0h = No Fault detected

1h = Fault detected

2

1

0

SENSOR_1_WARM

SENSOR_2_WARM

SENSOR_3_WARM

R/W1C

0h

TSD Warm detection for sensor 1. Is automatically cleared upon a

transition to INITIALIZE state, if corresponding *_WARM_MASK bit

in register MASK_CONFIG is '1'

0h = No Fault detected

1h = Fault detected

TSD Warm detection for sensor 2. Is automatically cleared upon a

transition to INITIALIZE state, if corresponding *_WARM_MASK bit

in register MASK_CONFIG is '1'

0h = No Fault detected

1h = Fault detected

TSD Warm detection for sensor 3. Is automatically cleared upon a

transition to INITIALIZE state, if corresponding *_WARM_MASK bit

in register MASK_CONFIG is '1'

0h = No Fault detected

1h = Fault detected

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7.5.50 INT_RV Register (Offset = 31h) [Reset = X]

INT_RV is shown in 图7-60 and described in 表7-57.

Return to the 表7-6.

图7-61. INT_RV Register

7

6

5

4

3

2

1

0

RESERVED

R-X

LDO4_RV

R/W1C-0h

LDO3_RV

R/W1C-0h

LDO2_RV

R/W1C-0h

LDO1_RV

R/W1C-0h

BUCK3_RV

R/W1C-0h

BUCK2_RV

R/W1C-0h

BUCK1_RV

R/W1C-0h

表7-57. INT_RV Register Field Descriptions

Bit

7

Field

RESERVED

Type

Reset

Description

R

X

Reserved

6

LDO4_RV

LDO3_RV

LDO2_RV

LDO1_RV

BUCK3_RV

BUCK2_RV

BUCK1_RV

R/W1C

0h

RV event detected on LDO4 rail during rail-turn-on, or after 4-5 ms

during discharge checks prior to entering power sequence to

ACTIVE state

0h = No RV detected

1h = RV detected

5

4

3

2

1

0

R/W1C

0h

RV event detected on LDO3 rail during rail-turn-on, or after 4-5 ms

during discharge checks prior to entering power sequence to

ACTIVE state

0h = No RV detected

1h = RV detected

RV event detected on LDO2 rail during rail-turn-on, or after 4-5 ms

during discharge checks prior to entering power sequence to

ACTIVE state

0h = No RV detected

1h = RV detected

RV event detected on LDO1 rail during rail-turn-on, or after 4-5 ms

during discharge checks prior to entering power sequence to

ACTIVE state

0h = No RV detected

1h = RV detected

RV event detected on BUCK3 rail during rail-turn-on, or after 4-5 ms

during discharge checks prior to entering power sequence to

ACTIVE state

0h = No RV detected

1h = RV detected

RV event detected on BUCK2 rail during rail-turn-on, or after 4-5 ms

during discharge checks prior to entering power sequence to

ACTIVE state

0h = No RV detected

1h = RV detected

RV event detected on BUCK1 rail during rail-turn-on, or after 4-5 ms

during discharge checks prior to entering power sequence to

ACTIVE state

0h = No RV detected

1h = RV detected

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7.5.51 INT_TIMEOUT_RV_SD Register (Offset = 32h) [Reset = 00h]

INT_TIMEOUT_RV_SD is shown in 图7-61 and described in 表7-58.

Return to the 表7-6.

图7-62. INT_TIMEOUT_RV_SD Register

7

6

5

4

3

2

1

0

TIMEOUT

R/W1C-0h

LDO4_RV_SD LDO3_RV_SD LDO2_RV_SD LDO1_RV_SD BUCK3_RV_SD BUCK2_RV_SD BUCK1_RV_SD

R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h

表7-58. INT_TIMEOUT_RV_SD Register Field Descriptions

Bit

Field

Type

Reset

Description

7

TIMEOUT

R/W1C

0h

Is set if ShutDown occurred due to a TimeOut while: 1. Transitioning

to ACTIVE state, and one or more rails did not rise past the UV level

at the end of the assigned slot (and UV on this rail is configured as a

SD fault). Which rail(s) is/are indicated by the *_UV bits in the INT_*

registers. 2. Transitioning to STANDBY state, and one or more rails

did not fall below the SCG level at the end of the assigned slot and

discharge is enabled for that rail (which rail(s) is/are indicated by the

corresponding RV_SD bit(s) in this register).

0h = No SD due to TimeOut occurred

1h = SD due to TimeOut occurred

6

5

4

LDO4_RV_SD

R/W1C

0h

RV on LDO4 rail caused a shutdown during: 1. A transition to

STANDBY state, this rail did not discharge at the end of the assigned

slot and discharge is enabled for this rail 2. A transition to STANDBY

state, RV was observed on this rail during the transition after this rail

was disabled and discharge was enabled 3. A transition to ACTIVE

state, RV was observed on this rail during the transition when this rail

was OFF (rails are expected to be discharged before commencing

the sequence to ACTIVE) 4. This rail did not discharge and therefore

caused a Timeout-SD while attempting to discharge all rails at the

start of a transition from STANDBY to ACTIVE (TIMEOUT bit gets

also set in this case)

0h = No SD due to RV/DISCHARGE_TIMEOUT on LDO4 occurred

1h = SD due to RV/DISCHARGE_TIMEOUT on LDO4 occurred

LDO3_RV_SD