PTPSI2140QDWQRQ1 [TI]

具有 2mA 雪崩额定值的汽车类 1200V、50mA 隔离开关

| DWQ | 11 | -40 to 125;


型号：	PTPSI2140QDWQRQ1
厂家：	TEXAS INSTRUMENTS
描述：	具有 2mA 雪崩额定值的汽车类 1200V、50mA 隔离开关 \| DWQ \| 11 \| -40 to 125 开关
文件：	总39页 (文件大小：1934K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPSI2140-Q1

ZHCSQF3B –APRIL 2022 –REVISED JUNE 2023

TPSI2140-Q1 具有2mA 雪崩额定值的1200V、50mA 汽车类隔离开关

该器件的初级侧仅由 9mA 的输入电流供电，并集成了

一个失效防护 EN 引脚，可防止对 VDD 电源反向供电

1 特性

• 符合汽车应用要求

的任何可能性。在大多数应用中，器件的 VDD 引脚应

连接到 5V 至 20V 的系统电源，并且器件的 EN 引脚

应由逻辑高电平介于2.1V 至20V 之间的GPIO 输出驱

动。在其他应用中，VDD 和 EN 引脚可直接由系统电

源或 GPIO 输出驱动。TPSI2140-Q1 的所有控制配置

都不需要光继电器解决方案通常所需的其他外部元件，

例如电阻器和/或低侧开关。

– AEC-Q100 等级1：–40°C 至125°C，T_A

• 集成雪崩额定MOSFET

– 针对过压条件下的可靠性认证进行设计和认证，

包括系统级电介质耐压测试(Hi-Pot)

• I_AVA= 2mA（5s 脉冲），1mA（60s 脉冲）

– 1200V 关断电压

– R_ON= 130Ω(T_J= 25°C)

– T_ON，T_OFF< 700μs

• 低初级侧电源电流

次级侧都包含背对背MOSFET，从S1 至S2 的关断电

压为 ±1.2 kV。TPSI2140-Q1 MOSFET 的雪崩稳健性

和热敏感封装设计使其能够可靠地支持系统级电介质耐

压测试 (HiPot)，并且无需任何外部元件即可承受高达

2mA 的直流快速充电器浪涌电流。

– 9mA 导通状态电流

– 3.5 μA 关断状态电流

• 功能安全型

封装信息

封装⁽¹⁾

– 可帮助进行ISO 26262 和IEC 61508 系统设计

的文档

• 稳健可靠的隔离栅：

封装尺寸（标称值）

器件型号

TPSI2140-Q1

10.3mm × 7.5mm

SOIC 11 引脚(DWQ)

– 在1000V_RMS/1500V_DC工作电压下预计寿命超

过26 年

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

– 隔离额定值V_ISO高达3750V_RMS/5300V_DC

– 峰值浪涌V_IOSM高达5000V

– ± 100 V/ns CMTI（典型值）

• SOIC 11 引脚(DWQ) 封装，具有宽引脚，可提高

热性能

HV+

R_ISO1

TPSI2140-Q1

4.5–20 V

VDD

HV-

3–20 V

Micro

Insulation

resistance to

chassis

GND

ground

– 爬电距离和间隙≥8mm（初级-次级）

– 爬电距离和间隙≥6mm（开关端子之间）

• 安全相关认证

– （计划）DIN VDE V 0884-11:2017-01

– （计划）UL 1577 组件认证计划

2 应用

V_ADC

• 固态继电器

R_ISO2

• 混合动力、电动和动力传动系统

• 电池管理系统(BMS)

• 能量存储系统(ESS)

• 太阳能

TPSI2140-Q1 简化版应用原理图

• 车载充电器

• 电动汽车充电基础设施

• 另请参阅与这些应用相关的TI 参考设计。

3 说明

TPSI2140-Q1 是一款隔离式固态继电器，专为高电压

汽车和工业应用而设计。TPSI2140-Q1 与 TI 具有高可

靠性的电容隔离技术和内部背对背 MOSFET 整合在一

起，形成了一款完全集成式解决方案，无需次级侧电

源。

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLVSFR3

TPSI2140-Q1

ZHCSQF3B –APRIL 2022 –REVISED JUNE 2023

www.ti.com.cn

Table of Contents

8 Detailed Description......................................................12

8.1 Overview...................................................................12

8.2 Functional Block Diagram.........................................12

8.3 Feature Description...................................................13

8.4 Device Functional Modes..........................................14

9 Application and Implementation..................................15

9.1 Application Information............................................. 15

9.2 Typical Application.................................................... 15

9.3 Power Supply Recommendations.............................22

9.4 Layout....................................................................... 22

10 Device and Documentation Support..........................31

10.1 接收文档更新通知................................................... 31

10.2 支持资源..................................................................31

10.3 Trademarks.............................................................31

10.4 静电放电警告.......................................................... 31

10.5 术语表..................................................................... 31

11 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

5.1 Pin Functions.............................................................. 3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Recommended Operating Conditions.........................5

6.4 Thermal Information....................................................5

6.5 Power Ratings.............................................................5

6.6 Insulation Specifications............................................. 6

6.7 Safety-Related Certifications...................................... 7

6.8 Safety Limiting Values.................................................7

6.9 Electrical Characteristics.............................................8

6.10 Switching Characteristics........................................10

7 Parameter Measurement Information.......................... 11

Information.................................................................... 32

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision A (November 2022) to Revision B (June 2023)

Page

• 将状态从预告信息更改为量产数据 ................................................................................................................... 1

• 更新了“特性”部分中的集成雪崩额定 MOSFET 说明，以添加耐压测试说明.................................................. 1

• 在“应用”部分中添加了能源存储系统(ESS) 并更新了链接.............................................................................1

• Added reference to Layout Guidelines in the Avalanche Robustness section................................................. 13

• Updated Layout Guidelines to include further EMI considerations and clarified the high voltage and thermal

considerations...................................................................................................................................................22

• Updated EVM images in Layout Example section to show the secondary side metallization for optimized

thermals............................................................................................................................................................23

• Added Interlayer Stitch Capacitance Option for EMI and Thermal Optimization in Layout Example section...23

English Data Sheet: SLVSFR3

Submit Document Feedback

Product Folder Links: TPSI2140-Q1

TPSI2140-Q1

ZHCSQF3B –APRIL 2022 –REVISED JUNE 2023

www.ti.com.cn

5 Pin Configuration and Functions

VDD

GND

NC/GND

GND

图5-1. TPSI2140-Q1 DWQ Package, 11-Pin SOIC (Top View)

5.1 Pin Functions

PIN NO.

PIN NAME

TYPE⁽¹⁾

DESCRIPTION

VDD

GND

Power supply for primary side

Ground supply for primary side

Active high switch enable signal

GND

NC/GND

GND

NC/GND

GND

Internally connected, connect externally to ground or leave floating

Internally connected to GND, connect externally to ground or leave floating

Switch input

I/O

For thermal dissipation only, see Layout Guidelines for more information

Switch input

I/O

(1) P = power, I = input, O = output, GND = ground, NC = no connect

Submit Document Feedback

Product Folder Links: TPSI2140-Q1

English Data Sheet: SLVSFR3

TPSI2140-Q1

ZHCSQF3B –APRIL 2022 –REVISED JUNE 2023

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

PARAMETER

MIN

–0.3

–55

–2

MAX

20.7

UNIT

V_VDD

V_EN

Primary side supply voltage⁽²⁾

Enable voltage⁽²⁾

I_S1,S2

Switch current, S1/S2

°C

Repetitive avalanche rating, 5s pulse, S1/S2⁽³⁾

Repetitive avalanche rating, 60s pulse, S1/S2⁽⁴⁾

Junction temperature

I_AVA,S1,S2

–1

T_J

150

–40

–65

T_stg

Storage temperature

°C

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If

used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

(2) Voltage values are with respect to GND.

(3) 5 minutes accumulated over lifetime in increments of no longer than 5 second periods, duty cycle < 33%

(4) 5 minutes accumulated over lifetime in increments of no longer than 60 second periods, duty cycle < 10%

6.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per AEC

Q100-002⁽¹⁾HBM ESD Classification

Level 2

HBM_Prim

HBM_Sec

CDM

Primary Side Pins No. 1-8

Secondary Side Pins No. 9-11

All pins

±2000

Electrostatic discharge

Human body model (HBM), per AEC

Q100-002⁽¹⁾HBM ESD Classification

Level 1C

±1500

±750

Charged device model (CDM), per AEC

Q100-011

Electrostatic discharge

CDM ESD Classification Level C4

(1) AEC Q100-002 indicates that HBM stressing must be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

English Data Sheet: SLVSFR3

Submit Document Feedback

Product Folder Links: TPSI2140-Q1

TPSI2140-Q1

ZHCSQF3B –APRIL 2022 –REVISED JUNE 2023

www.ti.com.cn

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

PARAMETER

MIN

4.5

NOM

MAX

UNIT

V_VDD

V_EN

V_S2-S1

I_S1,S2

T_A

Primary side supply voltage⁽¹⁾

Enable voltage⁽¹⁾

Switch input voltage

1200

–1200

–50

–40

Switch current

°C

Ambient operating temperature

Junction operating temperature

125

150

T_J

(1) Voltage values are with respect to GND.

6.4 Thermal Information

DEVICE

THERMAL METRIC ⁽¹⁾

DWQ (SOIC)

UNIT

11 PINS

R_ϴJA

Junction-to-ambient thermal resistance

Junction-to-ambient thermal resistance^{(2) (3)}

Junction-to-ambient thermal resistance^{(2) (4)}

Junction-to-board thermal resistance

°C/W

R_{ϴJA, EVM, 60S}

R_{ϴJA, EVM, 5S}

R_ϴJB

R_ϴJC(top)

ψ_JT

Junction-to-case (top) thermal resistance

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Ψ_JB

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2) EVM PCB dimensions are 74.25mm x 43mm x 1mm. 4 layer PCB with 2oz Cu on layers 1,4 and 1oz Cu on layer 2,3.

(3) Performance of EVM with power applied for 60s.

(4) Performance of EVM with power applied for 5s.

6.5 Power Ratings

PARAMETER

TEST CONDITIONS

V_VDD= 5 V,

V_EN= 5 V peak to peak,

V_S1-S2= 1200V, R_S1= 500kΩ

f_EN= 1Hz square wave

MIN

TYP

MAX

UNIT

P_D

Maximum power dissipation, total

Maximum power dissipation (primary)

Maximum power dissipation (secondary)

P_{D_P}

P_{D_S}

Submit Document Feedback

Product Folder Links: TPSI2140-Q1

English Data Sheet: SLVSFR3

TPSI2140-Q1

ZHCSQF3B –APRIL 2022 –REVISED JUNE 2023

www.ti.com.cn

UNIT

6.6 Insulation Specifications

PARAMETER

TEST CONDITIONS

VALUE

IEC 60664-1

CLR

CPG

External clearance⁽¹⁾

External Creepage⁽¹⁾

Shortest terminal-to-terminal distance through air

Shortest terminal-to-terminal distance across the

package surface

DTI

CTI

Distance through the insulation

Comparative tracking index

Material Group

Minimum internal gap (internal clearance)

DIN EN 60112 (VDE 0303-11); IEC 60112

According to IEC 60664-1

>10.5

>600

µm

I-IV

I-III

I-II

Rated mains voltage ≤300 V_RMS

Rated mains voltage ≤600 V_RMS

Rated mains voltage ≤1000 V_RMS

Overvoltage category per IEC 60664-1

DIN V VDE 0884-11:2017-01⁽²⁾, IEC 60747-17:2020

V_IORM

Maximum repetitive peak isolation voltage

AC voltage (bipolar)

1414

1000

1500

5300

6360

V_PK

V_RMS

V_DC

V_PK

AC voltage (sine wave)

V_IOWM

Maximum isolation working voltage

DC voltage

V_TEST= V_IOTM, t = 60 s (qualification)

V_TEST= 1.2 × V_IOTM, t = 1 s (100% production)

V_IOTM

Maximum transient isolation voltage

Maximum surge isolation voltage⁽³⁾

V_PK

Tested in oil per IEC 62638-1, 1.2/50 µs

waveform, V_TEST= 1.3 × V_IOSM= 6500 V_PK

(qualification)

V_IOSM

5000

≤5

V_PK

Method a: After I/O safety test subgroup 2/3,V_ini

V_IOTM, t_ini= 60 s; V_pd(m)= 1.2 × V_IORM= 1800

V_PK, t_m= 10 s

Method a: After environmental tests subgroup 1,

q_pd

Apparent charge⁽⁴⁾

V_ini= V_IOTM, t_ini= 60 s; V_pd(m)= 1.3 × V_IORM

1950 V_PK, t_m= 10 s

≤5

Method b1: At routine test (100% production) and

preconditioning (type test), V_ini= V_IOTM, t_ini= 1 s;

V_pd(m)= 1.5 × V_IORM= 2250 V_PK, t_m= 1 s

≤5

C_IO

R_IO

Barrier capacitance, input to output⁽⁵⁾

Insulation resistance, input to output⁽⁵⁾

V_IO= 0.4 × sin (2πft), f = 1 MHz

V_IO= 500 V, T_A= 25°C

>10¹²

>10¹¹

>10⁹

V_IO= 500 V, 100°C ≤T_A≤125°C

V_IO= 500 V at T_S= 150°C

Pollution degree

Climatic category

40/150/21

UL 1577

V_TEST= V_ISO, t = 60 s (qualification)

V_TEST= 1.2 × V_ISO, t = 1 s (100% production)

V_ISO

Withstand isolation voltage

3750

V_RMS

Misc.

V_ISO

5300

V_DC

(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.

Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the

isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in

certain cases. Techniques such as inserting grooves, ribs, or both on a printed-circuit board are used to help increase these

specifications.

(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured

by means of suitable protective circuits.

(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.

(4) Apparent charge is electrical discharge caused by a partial discharge (pd).

(5) All pins on each side of the barrier tied together creating a two-pin device.

English Data Sheet: SLVSFR3

Submit Document Feedback

Product Folder Links: TPSI2140-Q1

TPSI2140-Q1

ZHCSQF3B –APRIL 2022 –REVISED JUNE 2023

www.ti.com.cn

6.7 Safety-Related Certifications

VDE

CSA

CQC

TUV

Plan to certify according to

DIN V VDE V

0884-11:2017-01

Plan to certify according to

UL 1577 Component

Recognition Program

Maximum transient

isolation voltage, 5300

V_PK

;

Not Planned, contact TI to

Not Planned, contact TI to Not Planned, contact TI to

Maximum repetitive peak request.

isolation voltage, 1500

Single protection, 3750

V_RMS

request.

V_PK

;

Maximum surge isolation

voltage, 6000 V_PK

Certificate planned

6.8 Safety Limiting Values

PARAMETER^{(1) (2)}

TEST CONDITIONS

MIN

TYP

MAX

UNIT

_θJA= 70°C/W, V_VDD= 20 V,

Safety VDD Current

T_J= 150°C, T_A= 25°C

_θJA= 70°C/W, V_VDD= 20 V,

Safety Switch Current (On State)

2.7

1.5

T_J= 150°C, T_A= 25°C

I_S

Safety Switch Current (Off State, 5

second)

R_{θJA, EVM, 5S}⁽³⁾= 30°C/W, V_VDD= 0 V,

T_J= 150°C, T_A= 25°C

Safety Switch Current (Off State, 60

second)

R_{θJA, EVM, 60S}⁽³⁾= 52°C/W, V_VDD= 0 V,

T_J= 150°C, T_A= 25°C

_θJA= 70°C/W,

P_S

T_S

Safety input, output, or total power

Maximum safety temperature

1.78

150

T_J= 150°C, T_A= 25°C.

°C

(1) Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the I/O

can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and

damage the isolation barrier, potentially leading to secondary system failures.

(2) The safety-limiting constraint is the maximum junction temperature specified in the data sheet. The power dissipation and junction-to-

air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-

to-air thermal resistance in the Thermal Information table is that of a device installed on a high-K test board for leaded surface-mount

packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient

temperature plus the power times the junction-to-air thermal resistance.

(3) Assuming PCB layout similar to EVM in Layout Guideline section.

Submit Document Feedback

Product Folder Links: TPSI2140-Q1

English Data Sheet: SLVSFR3

TPSI2140-Q1

ZHCSQF3B –APRIL 2022 –REVISED JUNE 2023

www.ti.com.cn

6.9 Electrical Characteristics

Unless otherwise noted, all minimum/maximum specifications are over recommended operating conditions. All typical values

are measured at T_J= 25C, V_VDD= 5V, V_EN= 5V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

PRIMARY SIDE SUPPLY (VDD)

V_{UVLO_R}

V_{UVLO_F}

VDD undervoltage threshold rising

VDD undervoltage threshold falling

VDD rising

4.2

4.1

4.4

4.3

VDD falling

3.9

VDD undervoltage threshold

hysteresis

V_{UVLO_HYS}

100

150

VDD current, device powered on

T_J= 25°C

µA

I_{VDD_ON}

–40°C ≤T_J≤150°C

V_VDD= 5 V, V_EN= 0 V, T_J= 25°C

V_VDD= 5 V, V_EN= 0 V, T_J= 105°C

V_VDD= 5 V, V_EN= 0 V, T_J= 125°C

3.5

4.5

5.2

VDD current, 5 V, device powered off

V_VDD= 5 V, V_EN= 0 V, –40°C ≤

T_J≤150°C

µA

I_{VDD_OFF}

V_VDD= 20 V, V_EN= 0 V, T_J= 25°C

V_VDD= 20 V, V_EN= 0 V, T_J= 105°C

V_VDD= 20 V, V_EN= 0 V, T_J= 125°C

10.5

VDD current, 20 V, device powered

off

µA

V_VDD= 20 V, V_EN= 0 V, –40°C ≤

T_J≤150°C

FET CHARACTERISTICS (S1, S2)

I_O= 2 mA, T_J= 25°C

130

176

192

210

175

235

250

275

300

0.1

0.5

1.5

I_O= 2 mA, T_J= 85°C

I_O= 2 mA, T_J= 105°C

R_DSON

On resistance

I_O= 2 mA, T_J= 125°C

I_O= 2 mA, –40°C ≤T_J≤150°C

V = +/–1200 V, T_J= 25°C

V = +/–1200 V, T_J= 85°C

V = +/–1200 V, T_J= 105°C

V = +/–1200 V, T_J= 125°C

0.02

Off leakage, 1200 V

µA

V = +/–1200 V, –40°C ≤T_J≤

150°C

I_OFF

0.02

0.1

0.3

V = +/–1000 V, T_J= 25°C

V = +/–1000 V, T_J= 85°C

V = +/–1000 V, T_J= 105°C

V = +/–1000 V, T_J= 125°C

Off leakage, 1000 V

Avalanche voltage

µA

V = +/–1000 V, –40°C ≤T_J≤

150°C

I_O= 10 µA, T_J= 25°C

1300

1550

V_AVA

I_O= 100 µA, T_J= 150°C

V_S1= 1000 V, V_S2= 0 V OR V_S2

1000 V, V_S1= 0 V

V_{SM_OFF}

C_OSS

SM voltage

400

600

S1, S2 capacitance

V_S1,S2= 0 V, SM float, F = 1 MHz

LOGIC-LEVEL INPUT (EN)

V_IL

Input logic low voltage

0.0

2.1

0.8

20.0

300

V_IH

Input logic high voltage

Input logic hysteresis

V_HYS

100

250

English Data Sheet: SLVSFR3

Submit Document Feedback

Product Folder Links: TPSI2140-Q1

TPSI2140-Q1

ZHCSQF3B –APRIL 2022 –REVISED JUNE 2023

www.ti.com.cn

6.9 Electrical Characteristics (continued)

Unless otherwise noted, all minimum/maximum specifications are over recommended operating conditions. All typical values

are measured at T_J= 25C, V_VDD= 5V, V_EN= 5V.

PARAMETER

TEST CONDITIONS

MIN

–0.1

TYP

MAX UNIT

I_IL

Input logic low current

Input logic high current

VDD fail-safe current

V_EN= 0 V

0.1

6.5

µA

I_IL

V_EN= 0.8 V

I_IH

V_EN= 5 V

I_IH

V_EN= 20 V

100

–0.1

175

350

0.1

I_{VDD_FS}

V_EN= 20 V, V_VDD= 0 V

Two point measurement, V_EN= 0.5 V

and V_EN= 0.8 V

R_PD

Pulldown resistance

100

200

350

kΩ

NOISE IMMUNITY

CMTI

Common-mode transient immunity

|V_CM| = 1000 V

100.0 V/ns

Submit Document Feedback

Product Folder Links: TPSI2140-Q1

English Data Sheet: SLVSFR3

TPSI2140-Q1

ZHCSQF3B –APRIL 2022 –REVISED JUNE 2023

www.ti.com.cn

6.10 Switching Characteristics

Unless otherwise noted, all minimum/maximum specifications are over recommended operating conditions. All typical values

are measured at T_A= 25C, V_VDD= 5V, V_EN= 5V.

MODE

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Switching Characteristics

Input HI to Output voltage falling

propagation delay

t_{PD_ON}

t_F

100

300

100

Output fall time

t_ON

Input HI to Output LO delay

160

400

µs

EN switching

V_IN= 1000 V R_L= 1 MΩ

Input LO to Output voltage rising

propagation delay

t_{PD_OFF}

150

200

t_R

Output rise time

600

700

t_OFF

Input LO to Output HI delay

200

Input HI to Output voltage falling

propagation delay

t_{PD_ON}

t_F

240

400

100

Output fall time

t_ON

Input HI to Output LO delay

260

500

µs

EN and VDD

switching

V_IN= 1000 V R_L= 1 MΩ

Input LO to Output voltage rising

propagation delay

t_{PD_OFF}

150

200

t_R

Output rise time

600

700

t_OFF

Input LO to Output HI delay

200

English Data Sheet: SLVSFR3

Submit Document Feedback

Product Folder Links: TPSI2140-Q1

TPSI2140-Q1

ZHCSQF3B –APRIL 2022 –REVISED JUNE 2023

www.ti.com.cn

7 Parameter Measurement Information

V_IN

V_IH

1 M

4.5–20 V

V_IN

TPSI2140-Q1

V_IL

VDD

V_IN

90%

V_SW

10%

tt_{PD_HI}

tt_Ft

tt_{PD_LO}

tt_Rt

GND

tt_ON

tt_OFF

图7-1. Timing Diagram, EN Switching

V_IN

V_IH

1 M

V_IN

TPSI2140-Q1

V_IL

V_IN

VDD

90%

10%

V_SW

tt_{PD_HI}

tt_Ft

tt_{PD_LO}

tt_Rt

GND

tt_ON

tt_OFF

图7-2. Timing Diagram, EN and VDD Switching

Submit Document Feedback

Product Folder Links: TPSI2140-Q1

English Data Sheet: SLVSFR3

TPSI2140-Q1

ZHCSQF3B –APRIL 2022 –REVISED JUNE 2023

www.ti.com.cn

8 Detailed Description

8.1 Overview

The TPSI2140-Q1 is an isolated solid state relay designed for high voltage automotive and industrial

applications. TI's high reliability capacitive isolation technology in combination with back-to-back MOSFETs form

a completely integrated solution requiring no secondary side power supply.

As seen in the Functional Block Diagram, the primary side consists of a driver which delivers power and enable

logic information to each of the internal MOSFETs on the secondary side. The on-board oscillator controls the

frequency of the driver's operation and the Spread Spectrum Modulation (SSM) controller varies the driver

frequency to improve system EMI performance. When the enable pin is brought HI and the VDD voltage is

above the UVLO threshold, the oscillator starts and the driver sends power and a logic HI across the barrier.

When the enable pin is brought LO or the VDD voltage falls below the UVLO threshold, the driver is disabled.

The lack of activity communicates a logic LO to the secondary side and the MOSFETs are disabled.

Each MOSFET on the secondary side has a dedicated full-bridge rectifier to form its local power supply and a

receiver. The receiver determines the logic state delivered from the primary side through the capacitive isolation

barrier and uses a slew rate controlled driver to drive the MOSFET's gate. Each receiver performs signal

conditioning on the signals received across the barrier in order to filter common mode interference and ensure

that the MOSFETs are controlled according to the logic sent by the primary side driver and the system.

The avalanche robust MOSFETs and the thermal benefits of the widened pins on the 11 DWQ package enable

the TPSI2140-Q1 to support dielectric withstand testing (HiPot) and DC fast charger surge currents of up to 2

mA without requiring any external protection components.

8.2 Functional Block Diagram

VDD

UVLO

SiO₂

Based

Capacitive

Isolation

Barrier

Fail -

Safe

Input

Control

Oscillator

GND

图8-1. TPSI2140-Q1 Block Diagram

English Data Sheet: SLVSFR3

Submit Document Feedback

Product Folder Links: TPSI2140-Q1

TPSI2140-Q1

ZHCSQF3B –APRIL 2022 –REVISED JUNE 2023

www.ti.com.cn

8.3 Feature Description

8.3.1 Avalanche Robustness

When the voltage between the S1 and S2 pins exceeds +/-1200 V the secondary side MOSFETs could enter an

avalanche mode of operation. The MOSFETs and the 11 DWQ package have been designed and qualified to be

robust in this mode of operation to support Dielectric Withstand Testing (HiPot). To help ensure the thermal

performance of the the system in this mode of operation, refer to the PCB Layout Guidelines.

Submit Document Feedback

Product Folder Links: TPSI2140-Q1

English Data Sheet: SLVSFR3

TPSI2140-Q1

ZHCSQF3B –APRIL 2022 –REVISED JUNE 2023

www.ti.com.cn

8.4 Device Functional Modes

表8-1. Device Functional Modes

VDD

S1-S2 State

COMMENTS

OFF

VDD current is in OFF state range.

VDD current is in ON state range.

VDD current is in OFF state range.

Powered Up⁽¹⁾

OFF

Powered Down⁽²⁾

Primary side analog is powered on, VDD current is between

OFF state and ON state ranges.

OFF

(1) VDD ≥VDD undervoltage rising threshold.

(2) VDD ≤VDD undervoltage falling threshold.

Submit Document Feedback

Product Folder Links: TPSI2140-Q1

English Data Sheet: SLVSFR3

TPSI2140-Q1

ZHCSQF3B –APRIL 2022 –REVISED JUNE 2023

www.ti.com.cn

9 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

9.1 Application Information

The TPSI2140-Q1 is a 1200-V, 50-mA automotive isolated switch optimized for high voltage switching in

measurement applications, especially those that require switching across an isolation barrier or galvanically

isolated domain. Common end equipments include energy storage systems (ESS), solar panel arrays, EV

chargers, and EV battery management systems. The device enables the system designer to reduce cost and

improve reliability by replacing mechanical relays and optically isolated devices.

The TPSI2140-Q1's enable input is fail safe and does not need to be driven from the same domain as the VDD

pin supply.

The TPSI2140-Q1 supports an input voltage range of 4.5 V to 20 V on the VDD primary supply pin and a logic

high of 2.1 V to 20 V on the enable pin. The secondary side supports high voltage switching from –1200 V to

1200 V.

TI Reference Designs

The TI reference designs linked below are a helpful introduction to high voltage applications using the

TPSI2140-Q1. To maximize the thermal performance of the TPSI2140-Q1 for dielectric withstand testing (HiPot),

please follow the Layout Guidelines contained within this datasheet.

• TIDA-010232: High Voltage Insulation Monitoring

• TIDA-01513: Automotive High Voltage and Isolation Leakage Measurements

9.2 Typical Application

Insulation Resistance Monitoring

In high voltage applications such as electric vehicle systems, the high voltage battery pack is intentionally

isolated from the chassis domain of the car to protect the driver and prevent damage to electrical components.

These systems actively monitor the integrity of this insulation to ensure the safety of the system throughout its

lifetime. This active monitoring is referred to as insulation resistance monitoring (also known as isolation check,

insulation check, isolation monitoring, insulation monitoring, and residual current monitoring (RCM)) and is

performed by measuring the resistances from each of the battery terminals to the chassis ground, illustrated

below as R_ISOPand R_ISON

R_ISOP

VPACK

R_ISON

图9-1. Insulation Resistance Model

There are multiple design architectures using the TPSI2140-Q1 to measure these insulation resistances, R_ISOP

and R_ISON. Some architectures employ a microcontroller that performs measurements from the high voltage

domain, which will be referred to in this document as the Battery V- Reference architecture. Others use a

Submit Document Feedback

Product Folder Links: TPSI2140-Q1

English Data Sheet: SLVSFR3

TPSI2140-Q1

ZHCSQF3B –APRIL 2022 –REVISED JUNE 2023

www.ti.com.cn

microcontroller in the low voltage domain, which will be referred to in this document as the Chassis Ground

Reference architecture. The primary difference between the two architectures is the node that the MCU uses as

its GND reference. An example of a Battery V- MCU is the BQ79631-Q1 UIR sensor.

Chassis Ground Reference

Battery V- Reference

RDIV1

SW1

R_ISOP

SW1

R_ISOP

SW2

MCU

RDIV2

RDIV3

MCU

VPACK

ADC0 VDD

VPACK

RDIV1

VDD

ADC

ADC1

GND

R_ISON

GND

RDIV2

R_ISON

SW2

RDIV4

图9-2. Different MCU ADC Reference Examples

The two following sections demonstrate the measurement algorithms and the systems of equations used to

calculate the isolation resistances using each architecture.

Battery V- Reference Example

A Battery V- Reference architecture is shown below with the TPSI2140-Q1 illustrated as a switch (SW1 and

SW2). SW2 initiates a connection between the chassis and PACK- and enables the measurement path to the

ADC. SW1 initiates a connection between the chassis and the PACK+. RDIV1 and RDIV2 form a divider which

scales the measured voltages down to the appropriate ADC range.

SW1

R_ISOP

SW2

MCU

VPACK

VDD

ADC

RDIV1

RDIV2

R_ISON

GND

图9-3. Battery V- Reference Architecture

English Data Sheet: SLVSFR3

Submit Document Feedback

Product Folder Links: TPSI2140-Q1

TPSI2140-Q1

ZHCSQF3B –APRIL 2022 –REVISED JUNE 2023

www.ti.com.cn

Two ADC measurements must be taken in order to obtain enough information to calculate the two unknown

isolation resistances. The first measurement is taken with SW1 open and SW2 closed. The second

measurement is taken with SW1 closed and SW2 closed. With these two measurements it is possible to solve

the system of equations and calculate R_ISOPand R_ISON

In the following example the voltage on the chassis ground is arbitrarily referred to as V_RISONx

For the first ADC measurement SW2 is closed as shown below and the following equations relate the ADC

voltage to the other parameters in the system in this condition:

• V_ADC1measurement 1: SW1 open, SW2 closed

+ R

ISON

+ R

DIV1

DIV2

+ R

DIV2

= V

(1)

(2)

RISON1

PACK

ISOP

ISON

DIV1

DIV2

= V

ADC1

RISON1

+ R

DIV1

DIV2

SW1

R_ISOP

VPACK

SW2

MCU

VDD

ADC

RDIV1

R_ISON

GND

RDIV2

图9-4. Battery V- Reference Switch Positions for ADC1 Measurement

For the second ADC measurement SW1 and SW2 are closed as shown below and the following equations relate

the ADC voltage to the other parameters in the system in this condition:

• V_ADC2measurement 2: SW1 closed, SW2 closed

+ R

ISON

+ R

DIV1

DIV2

+ R

DIV2

= V

(3)

(4)

RISON2

PACK

ISOP

ISON

DIV1

DIV2

+ R

= V

ADC2

RISON2

DIV1

DIV2

Submit Document Feedback

Product Folder Links: TPSI2140-Q1

English Data Sheet: SLVSFR3

TPSI2140-Q1

ZHCSQF3B –APRIL 2022 –REVISED JUNE 2023

www.ti.com.cn

SW1

R_ISOP

SW2

VPACK

MCU

VDD

ADC

RDIV1

R_ISON

GND

RDIV2

图9-5. Battery V- Reference Switch Positions for ADC2 Measurement

Chassis Ground Reference Example

A Chassis Ground Reference architecture is shown below. SW1 and SW2 initiate connections to the PACK+ and

PACK-, and enable their corresponding measurement paths to their ADCs through their corresponding resistor

dividers. RDIV1, RDIV2, RDIV3, and RDIV4 scale the measured voltages down to the appropriate ADC ranges.

This first measurement is taken with SW1 closed and SW2 open and the second measurement is taken with

SW1 open and SW2 closed.

• VADC0: SW1 closed, SW2 open

+ R

ISOP

DIV1

+ R

DIV2

+ R

ISON

DIV2

+ R

= V

PACK

(5)

(6)

ADC1

RDIV2

DIV1

DIV2

ISOP

DIV1

DIV2

• VADC1: SW1 open, SW2 closed

+ R

DIV4

ISON

DIV3

+ R

DIV3

+ R

= V

= − V

PACK

ADC2

RDIV3

+ R

ISOP

DIV3

DIV4

ISON

DIV3

DIV4

English Data Sheet: SLVSFR3

Submit Document Feedback

Product Folder Links: TPSI2140-Q1

TPSI2140-Q1

ZHCSQF3B –APRIL 2022 –REVISED JUNE 2023

www.ti.com.cn

RDIV1

R_ISOP

SW1

MCU

RDIV2

RDIV3

ADC0 VDD

ADC1

VPACK

GND

R_ISON

SW2

RDIV4

图9-6. Chassis Ground Reference Switch Positions for ADC1 Measurement

RDIV1

R_ISOP

SW1

MCU

RDIV2

VPACK

ADC0 VDD

ADC1

GND

RDIV3

R_ISON

SW2

RDIV4

图9-7. Chassis Ground Reference Switch Positions for ADC2 Measurement

Battery V- Reference and Chassis Ground Reference Architectures with the TPSI2140-Q1

The circuits in 图 9-8 and 图 9-9 demonstrate how to connect the TPSI2140-Q1 as a switch in each of the

architectures above.

Submit Document Feedback

Product Folder Links: TPSI2140-Q1

English Data Sheet: SLVSFR3

TPSI2140-Q1

ZHCSQF3B –APRIL 2022 –REVISED JUNE 2023

www.ti.com.cn

R_ISO1

TPSI2140-Q1

VDD

HV+

MCU

Insulation

resistance to

chassis

GPIO

ground

ADC_IN

GND

R_ISO2

HV-

图9-8. TPSI2140-Q1 Insulation Resistance Monitoring –Battery V- Reference

HV+

R_ISO1

TPSI2140-Q1

VDD

HV-

Insulation

resistance to

chassis

MCU

GPIO

ADC_IN

GND

ground

GND

R_ISO2

图9-9. TPSI2140-Q1 Insulation Resistance Monitoring –Chassis Ground Reference

9.2.1 Dielectric Withstand Testing (HiPot)

The TPSI2140-Q1 is specifically designed to support dielectric withstand testing. In a high voltage system, a

dielectric withstand test (HiPot) may be administered during the characterization, production or maintenance of

the system to validate the reliability of the insulation barriers and galvanically isolated domains it contains. These

withstand voltage tests intentionally stress the components spanning these domains and put them in an

overvoltage condition. MOSFETs that are placed under these overvoltage conditions will enter avalanche mode

and begin conducting current at a high voltage, dissipating high power and heating up. The design and

qualification of the TPSI2140-Q1 was completed with this state in mind and supports up to 2 mA I_AVAfor 5

seconds intervals and 1 mA I_AVAfor 60 second intervals.

The dielectric withstand test voltage (V_HiPot), the TPSI2140-Q1's avalanche voltage (V_AVA), and the resistance

(R) in series with the TPSI2140-Q1 should limit the avalanche current (I_AVA) to the corresponding current limit

depending on the test duration. In addition, the PCB design should follow the recommendations in the Layout

Guidelines section to ensure adequate thermal performance to keep the junction temperature (T_J) below the

absolute maximum rating of the TPSI2140-Q1.

English Data Sheet: SLVSFR3

Submit Document Feedback

Product Folder Links: TPSI2140-Q1

TPSI2140-Q1

ZHCSQF3B –APRIL 2022 –REVISED JUNE 2023

www.ti.com.cn

TPSI2140-Q1

V_HIPOT

VDD

V_AVA

1300V @25C

2mA (5s)

1mA (60s)

I_AVA

GND

图9-10. Dielectric Withstand Test (HiPot) - Simplified Schematic

9.2.2 Design Requirements

表 9-1 lists the Design Requirements for a typical insulation resistance monitoring application using the Chassis

Ground Reference architecture and the TPSI2140-Q1 for switching.

表9-1. Typical Design Parameters For Insulation Resistance Monitoring Using the TPSI2140-Q1 –

Chassis Ground Reference Architecture

PARAMETER

VALUE

1000 V

5 V ±10 %

3500 V

5 s

V_PACKVoltage (maximum)

Primary side supply (V_VDD

Dielectric withstand voltage test

Surge voltage (IEC61000-3-5)

)

2500 V

9.2.3 Design Procedure - Chassis Ground Reference

HV+

HV-

R_ISO1

TPSI2140-Q1

VDD

Insulation

resistance to

chassis

MCU

GPIO

ADC_IN

GND

ground

GND

R_ISO2

图9-11. Chassis Ground Reference

R_ISO1Selection

In order to protect the TPSI2140-Q1, R_ISO1must be sized to limit the current in an overvoltage condition. The

amount of resistance required to protect the TPSI2140-Q1 depends on the amount of overvoltage applied. For

example, during a dielectric withstand voltage test (HiPot) of 3500 V for 5 seconds, the S1 to S2 voltage will be

clamped to 1300 V (V_AVAminimum) by the TPSI2140-Q1 and the R_ISO1resistance required to keep the current

under 2 mA would be 1.1 MΩ.

− V

AVA

HIPOT

3500V − 1300V

1.1 MΩ

= 2 . 0mA

(7)

AVA

ISO1

Submit Document Feedback

Product Folder Links: TPSI2140-Q1

English Data Sheet: SLVSFR3

TPSI2140-Q1

ZHCSQF3B –APRIL 2022 –REVISED JUNE 2023

www.ti.com.cn

If the high potential test lasts for 60 seconds, the R_ISO1resistance must be doubled to 2.2 MΩ to keep the

current below 1 mA.

DC Overvoltage

2000 V

R_ISO1Minimum (5 second intervals)

R_ISO1Minimum (60 second intervals)

350 kΩ

600 kΩ

1100 kΩ

1500 kΩ

700 kΩ

1200 kΩ

2200 kΩ

3000 MΩ

2500 V

3500 V

4300 V

9.3 Power Supply Recommendations

To ensure a reliable supply voltage, TI recommends that a 100-nF ceramic capacitor be placed between the

VDD pin and the GND pin of the TPSI2140-Q1. The capacitor should be placed as close to the device's VDD pin

as possible < 10 mm.

9.4 Layout

9.4.1 Layout Guidelines

Component placement:

Decoupling capacitors for the primary side VDD supply must be placed as close as possible to the device pins.

EMI considerations:

The TPSI2140-Q1 employs spread spectrum modulation (SSM) and in some systems, no additional system

design considerations are required to meet the EMI performance needs.

However, the system designer may choose to take additional measures to minimize EMI depending on the

system requirements and safety preferences of the system designer. The measures listed below reduce

emissions by providing a capacitive return path from the secondary side to the primary side or by increasing the

common mode loop impedance with an inductive component on the primary side.

• Capacitive Return Paths:

– An interlayer stitching capacitance in the range of 10-20 pF can be implemented on the PCB. This zero-

cost implementation is typically preferred as it also serves the purpose of thermal performance

improvement if placed directly underneath the TPSI2140-Q1. Please see the Layout Example for more

details.

– Most system designs already employ discrete Y capacitors or contain an amount of parasitic Y

capacitance between the high voltage and low voltage domains. If this Y capacitance is located on the

same board as the TPSI2140-Q1, they will act as a capacitive return path.

– Discrete high voltage capacitors could also be placed between the GND pin and the S1 or S2 terminals.

• Inductive Components:

– A pair of ferrite beads or a common mode choke with a high frequency impedance in the range of 10 kΩ

may be placed in series with the system VDD pin and GND pin supply on the primary side of the

TPSI2140-Q1.

High-voltage considerations:

The creepage from the primary side to the secondary side and from the creepage from the S1 pin to S2 pin of

the TPSI2140-Q1 should be maintained according to system requirements. It is most likely that the system

designer will avoid any top layer PCB routing underneath the body of the package or between the S1 and S2

pins.

Thermal considerations:

If the system designer plans to use the TPSI2140-Q1 in avalanche mode, it is important for the PCB layout to be

designed with thermal performance in mind. Proper PCB layout can help dissipate heat from the device to the

PCB and keep the junction temperature (T_J) under the absolute maximum rating. Floating inner layer planes or

Submit Document Feedback

Product Folder Links: TPSI2140-Q1

English Data Sheet: SLVSFR3

TPSI2140-Q1

ZHCSQF3B –APRIL 2022 –REVISED JUNE 2023

www.ti.com.cn

the planes used to implement a stitch capacitor can be drawn beneath the secondary side pins or directly

beneath the TPSI2140-Q1 for improved heat dissipation. An example of this can be seen in the Layout Example.

9.4.2 Layout Example

Varying PCB implementations are possible depending on both the system EMI requirements and the system

dielectric withstand testing (HiPot) parameters. The following sections detail the TPSI2140-Q1 EVM with

Thermal Optimization with secondary side metallization for optimized thermal performance and the Interlayer

Stitch Capacitance Option for EMI and Thermal Optimization.

TPSI2140-Q1 EVM with Thermal Optimization

The TPSI2140-Q1 EVM images below demonstrate a secondary side thermal metallization pattern and internal

floating metal that provides thermal relief to the TPSI2140-Q1 during system dielectric withstand testing (HiPot).

The TPSI2140-Q1 Secondary Side Layout Recommendation for Optimized Thermal Performance: Top Layer 1

shows the top side creepage and clearance considerations.

图9-12. TPSI2140-Q1 EVM - Component View

Submit Document Feedback

Product Folder Links: TPSI2140-Q1

English Data Sheet: SLVSFR3

TPSI2140-Q1

ZHCSQF3B –APRIL 2022 –REVISED JUNE 2023

www.ti.com.cn

图9-13. TPSI2140-Q1 EVM - Layer 1

图9-14. TPSI2140-Q1 EVM - Layer 2

English Data Sheet: SLVSFR3

Submit Document Feedback

Product Folder Links: TPSI2140-Q1

TPSI2140-Q1

ZHCSQF3B –APRIL 2022 –REVISED JUNE 2023

www.ti.com.cn

图9-15. TPSI2140-Q1 EVM - Layer 3

图9-16. TPSI2140-Q1 EVM - Layer 4

Submit Document Feedback

Product Folder Links: TPSI2140-Q1

English Data Sheet: SLVSFR3

TPSI2140-Q1

ZHCSQF3B –APRIL 2022 –REVISED JUNE 2023

www.ti.com.cn

7mm

Top Layer

1 VDD

2 GND

3 EN

>3mm

Maintain

Creepage

Distance of

16mm

>3mm

TPSI2140-Q1

图9-17. TPSI2140-Q1 Secondary Side Layout Recommendation for Optimized Thermal Performance: Top

Layer 1

English Data Sheet: SLVSFR3

Submit Document Feedback

Product Folder Links: TPSI2140-Q1

TPSI2140-Q1

ZHCSQF3B –APRIL 2022 –REVISED JUNE 2023

www.ti.com.cn

7mm

Layer 2

Floating plane

on inner layer for

thermal relief

16mm

Plane overlaps

pins on top side

TPSI2140-Q1

图9-18. TPSI2140-Q1 Secondary Side Layout Recommendation for Optimized Thermal Performance:

Inner Layer 2

Submit Document Feedback

Product Folder Links: TPSI2140-Q1

English Data Sheet: SLVSFR3

TPSI2140-Q1

ZHCSQF3B –APRIL 2022 –REVISED JUNE 2023

www.ti.com.cn

7mm

Layer 3

Floating plane

on inner layer for

thermal relief

16mm

Plane overlaps

pins on top side

TPSI2140-Q1

图9-19. TPSI2140-Q1 Secondary Side Layout Recommendation for Optimized Thermal Performance:

Inner Layer 3

English Data Sheet: SLVSFR3

Submit Document Feedback

Product Folder Links: TPSI2140-Q1

TPSI2140-Q1

ZHCSQF3B –APRIL 2022 –REVISED JUNE 2023

www.ti.com.cn

Bottom Layer

7mm

Floating plane

on bottom layer

for thermal relief

Plane overlaps

pins on top side

16mm

TPSI2140-Q1

图9-20. TPSI2140-Q1 Secondary Side Layout Recommendation for Optimized Thermal Performance:

Bottom Layer 4

Interlayer Stitch Capacitance Option for EMI and Thermal Optimization

The layout example below demonstrates an EMI optimized and thermally optimized PCB Design for high voltage

switching applications. The overlapping metal layers beneath the TPSI2140-Q1 form an interlayer stitching

capacitance between the primary side ground and the S2 pin and increase the board copper content, improving

the thermal performance for dielectric withstand testing (HiPot). Using S1 or S2 as the secondary side interlayer

stitching capacitance terminal is equally effective. Metal islands on the S1 and S2 pin on the top side and inner

layers further improve the thermal performance. Care should be taken to maintain both the vertical and

horizontal interlayer dielectric (ILD) spacings between high voltage terminals required by the system.

Submit Document Feedback

Product Folder Links: TPSI2140-Q1

English Data Sheet: SLVSFR3

TPSI2140-Q1

ZHCSQF3B –APRIL 2022 –REVISED JUNE 2023

www.ti.com.cn

V_DD

VDD

GND

MCU

GND

Primary Side

Ground Plane

图9-21. TPSI2140-Q1 Layout with Interlayer Stitch Capacitance: Top Layer (1)

Primary Side

Ground Plane

Top Side Package Outlines

Maintain required

ILD spacing

图9-22. TPSI2140-Q1 Layout with Interlayer Stitch Capacitance: Inner Layer (2,4)

Maintain required

ILD spacing

Primary Side

Ground Plane

Top Side Package Outlines

图9-23. TPSI2140-Q1 Layout with Interlayer Stitch Capacitance: Inner Layer (3)

English Data Sheet: SLVSFR3

Submit Document Feedback

Product Folder Links: TPSI2140-Q1

TPSI2140-Q1

ZHCSQF3B –APRIL 2022 –REVISED JUNE 2023

www.ti.com.cn

10 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,

generate code, and develop solutions are listed below.

10.1 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

10.2 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

10.3 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

10.4 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

10.5 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

Submit Document Feedback

Product Folder Links: TPSI2140-Q1

English Data Sheet: SLVSFR3

TPSI2140-Q1

ZHCSQF3B –APRIL 2022 –REVISED JUNE 2023

www.ti.com.cn

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

English Data Sheet: SLVSFR3

Submit Document Feedback

Product Folder Links: TPSI2140-Q1

PACKAGE OPTION ADDENDUM

www.ti.com

7-Jul-2023

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPSI2140QDWQRQ1

ACTIVE

SOIC

DWQ

2000 RoHS & Green

NIPDAU

Level-3-260C-168 HR

-40 to 125

2140Q

Samples

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

19-Jun-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPSI2140QDWQRQ1

SOIC

DWQ

2000

330.0

16.4

10.75 10.7

2.7

12.0

16.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

19-Jun-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SOIC DWQ 11

SPQ

Length (mm) Width (mm) Height (mm)

350.0 350.0 43.0

TPSI2140QDWQRQ1

2000

Pack Materials-Page 2

PACKAGE OUTLINE

DWQ0011A

SOIC - 2.65 mm max height

SMALL OUTLINE PACKAGE

SEATING PLANE

0.1 C

10.63

9.97

TYP

PIN 1 ID

AREA

2x 4.173

7x 1.27

10.5

10.1

NOTE 3

8.346

0.51

0.31

1.05

0.85

7.6

7.4

NOTE 4

2.65 max

0.25

C A B

0.304

0.204

TYP

0.25

GAGE PLANE

SEE DETAIL A

0.3

0.1

0 - 8

1.27

0.4

DETAIL A

TYPICAL

(1.4)

4226292/B 12/2022

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm, per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.

5. Reference JEDEC registration MS-013.

www.ti.com

EXAMPLE BOARD LAYOUT

DWQ0011A

SOIC - 2.65 mm max height

SMALL OUTLINE PACKAGE

SYMM

8x (2)

3 X (2)

3x (1.15)

8 x (1.65)

8X (0.6)

3x(1.65)

3x (1.15)

8x (0.6)

SYMM

2x (4.173)

2x(4.173)

7X (1.27)

R0.075 TYP

(9.3)

(9.75)

IPC-7351 NOMINAL

7.3 mm CLEARANCE/CREEPAGE

HV / ISOLATION OPTION

8.1 mm CLEARANCE/CREEPAGE

LAND PATTERN EXAMPLE

SCALE:4X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4226292/B 12/2022

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DWQ0011A

SOIC - 2.65 mm max height

SMALL OUTLINE PACKAGE

SYMM

8x (2)

3 X (2)

3x (1.15)

8 x (1.65)

3x(1.65)

3x (1.15)

8x (0.6)

8X (0.6)

SYMM

2x (4.173)

2x(4.173)

7X (1.27)

R0.075 TYP

(9.3)

(9.75)

IPC-7351 NOMINAL

7.3 mm CLEARANCE/CREEPAGE

HV / ISOLATION OPTION

8.1 mm CLEARANCE/CREEPAGE

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:4X

4226292/B 12/2022

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

PTPSI2140QDWQRQ1 [TI]

相关型号：

PTPSM365R6FRDN

PTPSM53604RDAR

PTPSM82913RDUR

PTPSM831D31MOA

PTPSM843A26RDGR

PTPSM843B22RDGR

PTPSM863252RDXR

PTPSM863257RDXR

PTQA420025N2AD

PTQA420025N2AS

PTQA420025N2AZ

PTQA420025P2AD